commit | 806622ce7aa915b2378f6709a143b9f7d9bcc373 | [log] [tgz] |
---|---|---|
author | Paul Ma <magf@bitland.corp-partner.google.com> | Tue Mar 31 03:20:19 2020 |
committer | Commit Bot <commit-bot@chromium.org> | Thu Apr 02 16:40:00 2020 |
tree | e1c3fdc7ebd8b5f5490dcc35dcad9b6912495823 | |
parent | df26358ce36cdaddf3fadef96b21f49232c2887e [diff] |
soc/amd/picasso: Adjust AcpiGpe0Blk io base address Change AcpiGpe0Blk io base address to 0x420. Original base address is 0x410. 0x410 can be accessed normally. But 0x414 is abnormal. We can write to it successfully, but always read back 0. BUG=b:147745443, b:150239200 BRANCH=none TEST=Use "iotools io_write32 0x424 0x08" to write value and "iotools io_read32 0x424" can get the same value. Change-Id: I716a0216c5f1f510d9d494857c121920c077c7a3 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2128395 Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Commit-Queue: Raul E Rangel <rrangel@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.