UPSTREAM: cezanne: Add new blobs
This is an initial release out of CezannePI-FP6 1.0.0.1 for
beginning development. Full coreboot compatibility will be
added in a subsequent update.
BUG=b:175143925
TEST=emerge-guybrush coreboot
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
Change-Id: I3bc8d10f33cdd439899f7ff7c9f8fb69e8096552
(cherry picked from commit 3e4a2e530f6f6dab7e9dc4af3feff9bdb2073b18)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/amd_blobs/+/2653367
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
Tested-by: Mathew King <mathewk@chromium.org>
Auto-Submit: Mathew King <mathewk@chromium.org>
diff --git a/cezanne/Cezanne Vbios Release Notes.txt b/cezanne/Cezanne Vbios Release Notes.txt
new file mode 100644
index 0000000..b3f64cb
--- /dev/null
+++ b/cezanne/Cezanne Vbios Release Notes.txt
Binary files differ
diff --git a/cezanne/CezanneGenericVbios.bin b/cezanne/CezanneGenericVbios.bin
new file mode 100644
index 0000000..582f5dd
--- /dev/null
+++ b/cezanne/CezanneGenericVbios.bin
Binary files differ
diff --git a/cezanne/PSP/APOB_NV_RV.bin b/cezanne/PSP/APOB_NV_RV.bin
new file mode 100644
index 0000000..4d45d9b
--- /dev/null
+++ b/cezanne/PSP/APOB_NV_RV.bin
@@ -0,0 +1 @@
+ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
\ No newline at end of file
diff --git a/cezanne/PSP/AblPostCode.h b/cezanne/PSP/AblPostCode.h
new file mode 100644
index 0000000..04e2a6a
--- /dev/null
+++ b/cezanne/PSP/AblPostCode.h
@@ -0,0 +1,484 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AblPostCode.h
+ *
+ * Contains definition needed for ABL Post Codes
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: PSP
+ * @e \$Revision: 83676 $ @e \$Date: 2012-12-07 15:57:01 -0600 (Fri, 07 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2020 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * AMD is granting You permission to use this software and documentation (if
+ * any) (collectively, the "Software") pursuant to the terms and conditions of
+ * the Software License Agreement included with the Software. If You do not have
+ * a copy of the Software License Agreement, contact Your AMD representative for
+ * a copy.
+ *
+ * You agree that You will not reverse engineer or decompile the Software, in
+ * whole or in part, except as allowed by applicable law.
+ *
+ * WARRANTY DISCLAIMER: THE SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
+ * KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ * BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, QUALITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON-INFRINGEMENT AND WARRANTIES
+ * ARISING FROM CUSTOM OF TRADE OR COURSE OF USAGE WITH RESPECT TO THE SOFTWARE,
+ * INCLUDING WITHOUT LIMITATION, THAT THE SOFTWARE WILL RUN UNINTERRUPTED OR
+ * ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF THE SOFTWARE IS
+ * ASSUMED BY YOU. Some jurisdictions do not allow the exclusion of implied
+ * warranties, so the above exclusion may not apply to You, but only to the
+ * extent required by law.
+ *
+ * LIMITATION OF LIABILITY AND INDEMNIFICATION: TO THE EXTENT NOT PROHIBITED BY
+ * APPLICABLE LAW, AMD AND ITS LICENSORS WILL NOT, UNDER ANY CIRCUMSTANCES BE
+ * LIABLE TO YOU FOR ANY PUNITIVE, DIRECT, INCIDENTAL, INDIRECT, SPECIAL OR
+ * CONSEQUENTIAL DAMAGES ARISING FROM POSSESSION OR USE OF THE SOFTWARE OR
+ * OTHERWISE IN CONNECTION WITH ANY PROVISION OF THIS AGREEMENT EVEN IF AMD AND
+ * ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THIS
+ * INCLUDES, WITHOUT LIMITATION, DAMAGES DUE TO LOST OR MISAPPROPRIATED DATA,
+ * LOST PROFITS OR CONFIDENTIAL OR OTHER INFORMATION, FOR BUSINESS INTERRUPTION,
+ * FOR PERSONAL INJURY, FOR LOSS OF PRIVACY, FOR FAILURE TO MEET ANY DUTY
+ * INCLUDING OF GOOD FAITH OR REASONABLE CARE, FOR NEGLIGENCE AND FOR ANY OTHER
+ * PECUNIARY OR OTHER LOSS WHTSOEVER. In no event shall AMD's total liability to
+ * You for all damages, losses, and causes of action (whether in contract, tort
+ * (including negligence) or otherwise) exceed the amount of $50 USD. You agree
+ * to defend, indemnify and hold harmless AMD, its subsidiaries and affiliates
+ * and their respective licensors, directors, officers, employees, affiliates or
+ * agents from and against any and all loss, damage, liability and other
+ * expenses (including reasonable attorneys' fees), resulting from Your
+ * possession or use of the Software or violation of the terms and conditions of
+ * this Agreement.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: Notice to U.S. Government End Users. The
+ * Software and related documentation are "commercial items", as that term is
+ * defined at 48 C.F.R. Section 2.101, consisting of "commercial computer
+ * software" and "commercial computer software documentation", as such terms are
+ * used in 48 C.F.R. Section 12.212 and 48 C.F.R. Section 227.7202,
+ * respectively. Consistent with 48 C.F.R. Section 12.212 or 48 C.F.R. Sections
+ * 227.7202-1 through 227.7202-4, as applicable, the commercial computer
+ * software and commercial computer software documentation are being licensed to
+ * U.S. Government end users: (a) only as commercial items, and (b) with only
+ * those rights as are granted to all other end users pursuant to the terms and
+ * conditions set forth in this Agreement. Unpublished rights are reserved under
+ * the copyright laws of the United States.
+ *
+ * EXPORT RESTRICTIONS: You shall adhere to all applicable U.S. import/export
+ * laws and regulations, as well as the import/export control laws and
+ * regulations of other countries as applicable. You further agree You will not
+ * export, re-export, or transfer, directly or indirectly, any product,
+ * technical data, software or source code received from AMD under this license,
+ * or the direct product of such technical data or software to any country for
+ * which the United States or any other applicable government requires an export
+ * license or other governmental approval without first obtaining such licenses
+ * or approvals, or in violation of any applicable laws or regulations of the
+ * United States or the country where the technical data or software was
+ * obtained. You acknowledges the technical data and software received will not,
+ * in the absence of authorization from U.S. or local law and regulations as
+ * applicable, be used by or exported, re-exported or transferred to: (i) any
+ * sanctioned or embargoed country, or to nationals or residents of such
+ * countries; (ii) any restricted end-user as identified on any applicable
+ * government end-user list; or (iii) any party where the end-use involves
+ * nuclear, chemical/biological weapons, rocket systems, or unmanned air
+ * vehicles. For the most current Country Group listings, or for additional
+ * information about the EAR or Your obligations under those regulations, please
+ * refer to the website of the U.S. Bureau of Industry and Security at
+ * http://www.bis.doc.gov/.
+ *******************************************************************************
+ */
+
+ #ifndef _ABLPOSTCODE_H_
+ #define _ABLPOSTCODE_H_
+
+/// <PostCodePrefix> 0xEA000000
+/**
+ * AGESA ABL Test Points
+ *
+ * These are the values displayed to the user to indicate progress through boot.
+ *
+ */
+typedef enum {
+ StartProcessorTestPoints = 0xE000, ///< Entry used for range testing for @b Processor related TPs
+
+ // Memory test points
+ TpProcMemBeforeMemDataInit = 0xE001, ///< Memory structure initialization (Public interface)
+ TpProcMemBeforeSpdProcessing = 0xE002, ///< SPD Data processing (Public interface)
+ TpProcMemAmdMemAutoPhase1 = 0xE003, ///< Memory configuration (Public interface) Phase 1
+ TpProcMemDramInit = 0xE004, ///< DRAM initialization
+ TpProcMemSPDChecking = 0xE005, ///< ProcMemSPDChecking
+ TpProcMemModeChecking = 0xE006, ///< ProcMemModeChecking
+ TpProcMemSpeedTclConfig = 0xE007, ///< Speed and TCL configuration
+ TpProcMemSpdTiming = 0xE008, ///< ProcMemSpdTiming
+ TpProcMemDramMapping = 0xE009, ///< ProcMemDramMapping
+ TpProcMemPlatformSpecificConfig = 0xE00A, ///< ProcMemPlatformSpecificConfig
+ TPProcMemPhyCompensation = 0xE00B, ///< ProcMemPhyCompensation
+ TpProcMemStartDcts = 0xE00C, ///< ProcMemStartDcts
+ TpProcMemBeforeDramInit = 0xE00D, ///< ProcMemBeforeDramInit (Public interface)
+ TpProcMemPhyFenceTraining = 0xE00E, ///< ProcMemPhyFenceTraining
+ TpProcMemSynchronizeDcts = 0xE00F, ///< ProcMemSynchronizeDcts
+ TpProcMemSystemMemoryMapping = 0xE010, ///< ProcMemSystemMemoryMapping
+ TpProcMemMtrrConfiguration = 0xE011, ///< ProcMemMtrrConfiguration
+ TpProcMemDramTraining = 0xE012, ///< ProcMemDramTraining
+ TpProcMemBeforeAnyTraining = 0xE013, ///< ProcMemBeforeAnyTraining(Public interface)
+ // PMU Test Points
+ TpProcMemPmuBeforeFirmwareLoad = 0xE014, ///< ABL Mem - PMU - Before PMU Firmware load
+ TpProcMemPmuAfterFirmwareLoad = 0xE015, ///< ABL Mem - PMU - After PMU Firmware load
+ TpProcMemPmuPopulateSramTimings = 0xE016, ///< ABL Mem - PMU Populate SRAM Timing
+ TpProcMemPmuPopulateSramConfig = 0xE017, ///< ABL Mem - PMU Populate SRAM Config
+ TpProcMemPmuWriteSramMsgBlock = 0xE018, ///< ABL Mem - PMU Write SRAM Msg Block
+ TpProcMemPmuWaitForPhyCalComplete = 0xE019, ///< ABL Mem - Wait for Phy Cal Complete
+ TpProcMemPmuPhyCalComplete = 0xE01A, ///< ABL Mem - Phy Cal Complete
+ TpProcMemPmuStart = 0xE01B, ///< ABL Mem - PMU Start
+ TpProcMemPmuStarted = 0xE01C, ///< ABL Mem - PMU Started
+ TpProcMemPmuWaitingForComplete = 0xE01D, ///< ABL Mem - PMU Waiting for Complete
+ TpProcMemPmuStageDevInit = 0xE01E, ///< ABL Mem - PMU Stage Dec Init
+ TpProcMemPmuStageTrainWrLvl = 0xE01F, ///< ABL Mem - PMU Stage Training Wr Lvl
+ TpProcMemPmuStageTrainRxEn = 0xE020, ///< ABL Mem - PMU Stage Training Rx En
+ TpProcMemPmuStageTrainRdDqs1D = 0xE021, ///< ABL Mem - PMU Stage Training Rd Dqs
+ TpProcMemPmuStageTrainRd2D = 0xE022, ///< ABL Mem - PMU Stage Traning Rd 2D
+ TpProcMemPmuStageTrainWr2D = 0xE023, ///< ABL Mem - PMU Stage Training Wr 2D
+ TpProcMemPmuStagePMUQEmpty = 0xE024, ///< ABL Mem - PMU Queue Empty
+ TpProcMemPmuUSMsgStart = 0xE025, ///< ABL Mem - PMU US message Start
+ TpProcMemPmuUSMsgEnd = 0xE026, ///< ABL Mem - PMU US message End
+ TpProcMemPmuComplete = 0xE027, ///< ABL Mem - PMU Complete
+ TpProcMemAfterPmuTraining = 0xE028, ///< ABL Mem - PMU - After PMU Training
+ TpProcMemBeforeDisablePmu = 0xE029, ///< ABL Mem - PMU - Before Disable PMU
+ //Original Post code
+ TpProcMemTransmitDqsTraining = 0xE02A, ///< ABL Mem - ProcMemTransmitDqsTraining
+ TpProcMemTxDqStartSweep = 0xE02B, ///< ABL Mem - Start write sweep
+ TpProcMemTxDqSetDelay = 0xE02C, ///< ABL Mem - Set Transmit DQ delay
+ TpProcMemTxDqWritePattern = 0xE02D, ///< ABL Mem - Write test pattern
+ TpProcMemTxDqReadPattern = 0xE02E, ///< ABL Mem - Read Test pattern
+ TpProcMemTxDqTestPattern = 0xE02F, ///< ABL Mem - Compare Test pattern
+ TpProcMemTxDqResults = 0xE030, ///< ABL Mem - Update results
+ TpProcMemTxDqFindWindow = 0xE031, ///< ABL Mem - Start Find passing window
+ TpProcMemMaxRdLatencyTraining = 0xE032, ///< ABL Mem - ProcMemMaxRdLatencyTraining
+ TpProcMemMaxRdLatStartSweep = 0xE033, ///< ABL Mem - Start sweep
+ TpProcMemMaxRdLatSetDelay = 0xE034, ///< ABL Mem - Set delay
+ TpProcMemMaxRdLatWritePattern = 0xE035, ///< ABL Mem - Write test pattern
+ TpProcMemMaxRdLatReadPattern = 0xE036, ///< ABL Mem - Read Test pattern
+ TpProcMemMaxRdLatTestPattern = 0xE037, ///< ABL Mem - Compare Test pattern
+ TpProcMemOnlineSpareInit = 0xE038, ///< ABL Mem - Online Spare init
+ TpProcMemChipSelectInterleaveInit = 0xE039, ///< ABL Mem - Chip select Interleave Init
+ TpProcMemNodeInterleaveInit = 0xE03A, ///< ABL Mem - Node Interleave Init
+ TpProcMemChannelInterleaveInit = 0xE03B, ///< ABL Mem - Channel Interleave Init
+ TpProcMemEccInitialization = 0xE03C, ///< ABL Mem - ECC initialization
+ TpProcMemPlatformSpecificInit = 0xE03D, ///< ABL Mem - Platform Specific Init
+ TpProcMemBeforeAgesaReadSpd = 0xE03E, ///< ABL Mem - Before callout for "AgesaReadSpd"
+ TpProcMemAfterAgesaReadSpd = 0xE03F, ///< ABL Mem - After callout for "AgesaReadSpd"
+ TpProcMemBeforeAgesaHookBeforeDramInit = 0xE040, ///< ABL Mem - Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeDramInit = 0xE041, ///< ABL Mem - After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemBeforeAgesaHookBeforeDQSTraining = 0xE042, ///< ABL Mem - Before optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemAfterAgesaHookBeforeDQSTraining = 0xE043, ///< ABL Mem - After optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemBeforeAgesaHookBeforeExitSelfRef = 0xE044, ///< ABL Mem - Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeExitSelfRef = 0xE045, ///< ABL Mem - After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterMemDataInit = 0xE046, ///< ABL Mem - After MemDataInit
+ TpProcMemInitializeMCT = 0xE047, ///< ABL Mem - Before InitializeMCT
+ TpProcMemLvDdr3 = 0xE048, ///< ABL Mem - Before LV DDR3
+ TpProcMemInitMCT = 0xE049, ///< ABL Mem - Before InitMCT
+ TpProcMemOtherTiming = 0xE04A, ///< ABL Mem - Before OtherTiming
+ TpProcMemUMAMemTyping = 0xE04B, ///< ABL Mem - Before UMAMemTyping
+ TpProcMemSetDqsEccTmgs = 0xE04C, ///< ABL Mem - Before SetDqsEccTmgs
+ TpProcMemMemClr = 0xE04D, ///< ABL Mem - Before MemClr
+ TpProcMemOnDimmThermal = 0xE04E, ///< ABL Mem - Before On DIMM Thermal
+ TpProcMemDmi = 0xE04F, ///< ABL Mem - Before DMI
+ TpProcMemEnd = 0xE050, ///< ABL MEM - End of phase 3 memory code
+
+ // CPU test points
+ TpProcCpuInitAfterTrainingStart = 0xE051, ///< Entry point CPU init after training
+ TpProcCpuInitAfterTrainingEnd = 0xE052, ///< Exit point CPU init after training
+ TpProcCpuApobInitStart = 0xE053, ///< Entry point CPU APOB data init
+ TpProcCpuApobInitEnd = 0xE054, ///< Exit point CPU APOB data init
+ TpProcCpuOptimizedBootStart = 0xE055, ///< Entry point CPU Optimized boot init
+ TpProcCpuOptimizedBootEnd = 0xE056, ///< Exit point CPU Optimized boot init
+ TpProcCpuApobCcxEdcInitStart = 0xE057, ///< Entry point CPU APOB EDC info init
+ TpProcCpuApobCcxEdcInitEnd = 0xE058, ///< Exit point CPU APOB EDC info init
+ TpProcCpuApobCcdMapStart = 0xE059, ///< Entry point CPU APOB CCD map data init
+ TpProcCpuApobCcdMapEnd = 0xE05A, ///< Exit point CPU APOB CCD map data init
+
+ // Extended memory test point
+ TpProcMemSendMRS2 = 0xE080, ///< ProcMemSendMRS2
+ TpProcMemSendMRS3 = 0xE081, ///< Sedding MRS3
+ TpProcMemSendMRS1 = 0xE082, ///< Sending MRS1
+ TpProcMemSendMRS0 = 0xE083, ///< Sending MRS0
+ TpProcMemContinPatternGenRead = 0xE084, ///< Continuous Pattern Read
+ TpProcMemContinPatternGenWrite = 0xE085, ///< Continuous Pattern Write
+ TpProcMem2dRdDqsTraining = 0xE086, ///< Mem: 2d RdDqs Training begin
+ TpProcMemBefore2dTrainExtVrefChange = 0xE087, ///< Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemAfter2dTrainExtVrefChange = 0xE088, ///< Mem: After optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemConfigureDCTForGeneral = 0xE089, ///< Configure DCT For General use begin
+ TpProcMemProcConfigureDCTForTraining = 0xE08A, ///< Configure DCT For training begin
+ TpProcMemConfigureDCTNonExplicitSeq = 0xE08B, ///< Configure DCT For Non-Explicit
+ TpProcMemSynchronizeChannels = 0xE08C, ///< Configure to Sync channels
+ TpProcMemC6StorageAllocation = 0xE08D, ///< Allocate C6 Storage
+ TpProcMemLvDdr4 = 0xE08E, ///< Before LV DDR4
+ TpProcMemLvLpddr3 = 0xE08F, ///< Before LV DDR3
+
+ // Gnb Earlier init
+ TP0x90 = 0xE090, ///< TP0x90
+ TP0x91 = 0xE091, ///< GNB earlier interface
+ TP0x92 = 0xE092, ///< GNB internal debug code
+ TP0x93 = 0xE093, ///< GNB internal debug code
+ TP0x94 = 0xE094, ///< GNB internal debug code
+ TP0x95 = 0xE095, ///< GNB internal debug code
+ TP0x96 = 0xE096, ///< GNB internal debug code
+ TP0x97 = 0xE097, ///< GNB internal debug code
+ TP0x98 = 0xE098, ///< GNB internal debug code
+ TP0x99 = 0xE099, ///< GNB internal debug code
+ TP0x9A = 0xE09A, ///< GNB internal debug code
+ TP0x9B = 0xE09B, ///< GNB internal debug code
+ TP0x9C = 0xE09C, ///< GNB internal debug code
+ TP0x9D = 0xE09D, ///< GNB internal debug code
+ TP0x9E = 0xE09E, ///< GNB internal debug code
+ TP0x9F = 0xE09F, ///< GNB internal debug code
+ TP0xA0 = 0xE0A0, ///< TP0xA0
+ TP0xA1 = 0xE0A1, ///< GNB internal debug code
+ TP0xA2 = 0xE0A2, ///< GNB internal debug code
+ TP0xA3 = 0xE0A3, ///< GNB internal debug code
+ TP0xA4 = 0xE0A4, ///< GNB internal debug code
+ TP0xA5 = 0xE0A5, ///< GNB internal debug code
+ TP0xA6 = 0xE0A6, ///< GNB internal debug code
+ TP0xA7 = 0xE0A7, ///< GNB internal debug code
+ TP0xA8 = 0xE0A8, ///< GNB internal debug code
+ TP0xA9 = 0xE0A9, ///< GNB internal debug code
+ TP0xAA = 0xE0AA, ///< GNB internal debug code
+ TP0xAB = 0xE0AB, ///< GNB internal debug code
+ TP0xAC = 0xE0AC, ///< GNB internal debug code
+ TP0xAD = 0xE0AD, ///< GNB internal debug code
+ TP0xAE = 0xE0AE, ///< GNB internal debug code
+ TP0xAF = 0xE0AF, ///< GNB internal debug code
+
+ TpAbl1Begin = 0xE0B0, ///< Abl1Begin
+ TpAbl1Initialization = 0xE0B1, ///< ABL 1 Initialization
+ TpAbl1DfEarly = 0xE0B2, ///< ABL 1 DF Early
+ TpAbl1DfPreTraining = 0xE0B3, ///< ABL 1 DF Pre Training
+ TpAbl1DebugSync = 0xE0B4, ///< ABL 1 Debug Synchronization
+ TpAbl1ErrorDetected = 0xE0B5, ///< ABL 1 Error Detected
+ TpAbl1GlobalMemErrorDetected = 0xE0B6, ///< ABL 1 Global memory error detected
+ TpAbl1End = 0xE0B7, ///< ABL 1 End
+ TpAbl2Begin = 0xE0B8, ///< ABL 2 Begin
+ TpAbl2Initialization = 0xE0B9, ///< ABL 2 Initialization
+ TpAbl2DfAfterTraining = 0xE0BA, ///< ABL 2 After Training
+ TpAbl2DebugSync = 0xE0BB, ///< ABL 2 Debug Synchronization
+ TpAbl2ErrorDetected = 0xE0BC, ///< ABL 2 Error detected
+ TpAbl2GlobalMemErrorDetected = 0xE0BD, ///< ABL 2 Global memory error detected
+ TpAbl2End = 0xE0BE, ///< ABL 2 End
+ TpAbl3Begin = 0xE0BF, ///< ABL 3 Begin
+ TpAbl3Initialization = 0xE0C0, ///< ABL 3 Initialziation
+ TpAbl3GmiGopInitStage1 = 0xE1C0, ///< ABL 3 GMI/xGMI Initialization Stage 1
+ TpAbl3GmiGopInitStage1Warning = 0xB1C0, ///< ABL 3 GMI/xGMI Initialization Stage 1 Warning
+ TpAbl3GmiGopInitState1Error = 0xF1C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Error
+ TpAbl3GmiGopInitStage2 = 0xE2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2
+ TpAbl3GmiGopInitStage2Warning = 0xB2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Warning
+ TpAbl3GmiGopInitState2Error = 0xF2C0, ///< ABL 3 GMI/xGMI Initialization Stage 2 Error
+ TpAbl3GmiGopInitStage3 = 0xE3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3
+ TpAbl3GmiGopInitStage3Warning = 0xB3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3 Warning
+ TpAbl3GmiGopInitState3Error = 0xF3C0, ///< ABL 3 GMI/xGMI Initialization Stage 3 Error
+ TpAbl3GmiGopInitStage4 = 0xE4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4
+ TpAbl3GmiGopInitStage4Warning = 0xB4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4 Warning
+ TpAbl3GmiGopInitState4Error = 0xF4C0, ///< ABL 3 GMI/xGMI Initialization Stage 4 Error
+ TpAbl3GmiGopInitStage5 = 0xE5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5
+ TpAbl3GmiGopInitStage5Warning = 0xB5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5 Warning
+ TpAbl3GmiGopInitState5Error = 0xF5C0, ///< ABL 3 GMI/xGMI Initialization Stage 5 Error
+ TpAbl3GmiGopInitStage6 = 0xE6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6
+ TpAbl3GmiGopInitStage6Warning = 0xB6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6 Warning
+ TpAbl3GmiGopInitState6Error = 0xF6C0, ///< ABL 3 GMI/xGMI Initialization Stage 6 Error
+ TpAbl3GmiGopInitStage7 = 0xE7C0, ///< ABL 3 GMI/xGMI Initialization Stage 7
+ TpAbl3GmiGopInitStage8 = 0xE8C0, ///< ABL 3 GMI/xGMI Initialization Stage 8
+ TpAbl3GmiGopInitStage9 = 0xE9C0, ///< ABL 3 GMI/xGMI Initialization Stage 9
+ TpAbl3GmiGopInitStage9Error = 0xF9C0, ///< ABL 3 GMI/xGMI Initialization Stage 9 Error
+ TpAbl3GmiGopInitStage10 = 0xEAC0, ///< ABL 3 GMI/xGMI Initialization Stage 10
+ TpAbl3GmiGopInitStage10Error = 0xFAC0, ///< ABL 3 GMI/xGMI Initialization Stage 10 Error
+ TpAbl3ProgramUmcKeys = 0xE0C1, ///< Abl3ProgramUmcKeys
+ TpAbl3DfFinalInitialization = 0xE0C2, ///< ABL 3 DF Finial Initalization
+ TpAbl3ExecuteSyncFunction = 0xE0C3, ///< ABL 3 Execute Synchronization Function
+ TpAbl3DebugSync = 0xE0C4, ///< ABL 3 Debug Synchronization Function
+ TpAbl3ErrorDetected = 0xE0C5, ///< ABL 3 Error Detected
+ TpAbl3GlobalMemErrorDetected = 0xE0C6, ///< ABL 3 Global memroy error detected
+ TpAbl4ColdInitialization = 0xE0C7, ///< ABL 4 Initialiation - cold boot
+ TpAbl4MemTest = 0xE0C8, ///< ABL 4 Memory test - cold boot
+ TpAbl4Apob = 0xE0C9, ///< ABL 4 APOB Initialzation - cold boot
+ TpAbl4Finalize = 0xE0CA, ///< ABL 4 Finalize memory settings - cold boot
+ TpAbl4CpuInizialOptimizedBoot = 0xE0CB, ///< ABL 4 CPU Initialize Optimized Boot - cold boot
+ TpAbl4GmicieTraining = 0xE0CC, ///< ABL 4 Gmi Pcie Training - cold boot
+ TpAbl4ColdEnd = 0xE0CD, ///< ABL 4 Cold boot End
+ TpAbl4ResumeInitialization = 0xE0CE, ///< ABL 4 Initialization - Resume boot
+ TpAbl4ResumeEnd = 0xE0CF, ///< ABL 4 Resume End
+ TpAbl4End = 0xE0D0, ///< ABL 4 End Cold/Resume boot
+ TpProcMemAmdMemAutoPhase2 = 0xE0D1, ///< ABL 2 memory initialization
+ TpProcMemAmdMemAutoPhase3 = 0xE0D2, ///< ABL 3 memory initialization
+ TpAbl3End = 0xE0D3, ///< ABL 3 End
+ TpAbl1EnterMemFlow = 0xE0D4, ///< ABL 1 Enter Memory Flow
+ TpAbl1MemFlowMemClkSync = 0xE0D5, ///< Memorry flow memory clock synchronization
+ TpIfBeforeGetIdsData = 0xE0E0, ///< Before IDS calls out to get IDS data
+ TpIfAfterGetIdsData = 0xE0E1, ///< After IDS calls out to get IDS data
+ // PMU test points
+ TpProcMemPmuFailed = 0xE0F9, ///< Failed PMU training.
+ TpProcMemPhase1End = 0xE0FA, ///< End of phase 1 memory code
+ TpProcMemPhase2End = 0xE0FB, ///< End of phase 2 memory code
+
+ // ABL0 test points
+ TpAbl0Begin = 0xE0FC, ///< Abl0Begin
+ TpAbl0End = 0xE0FD, ///< ABL 0 End
+ TpAbl0FatalBegin = 0xE0FE, ///< Abl0 Begin with Fatal Mode
+ TpAbl0FatalEnd = 0xE0FF, ///< ABL 0 End with Fatal Mode
+
+ // ABL5 test points
+ TpAbl7End = 0xE100, ///< ABL 7 End
+ TpAbl7ResumeInitialization = 0xE101, ///< ABL 7 Resume boot
+ TpAbl6End = 0xE102, ///< ABL 6 End
+ TpAbl6Initialization = 0xE103, ///< ABL 6 Initialization
+ TpProcMemPhase1bEnd = 0xE104, ///< End of phase 1b memory code
+ TpProcMemAmdMemAutoPhase1b = 0xE105, ///< ABL 1b memory initialization
+ TpAbl6GlobalMemErrorDetected = 0xE106, ///< ABL 6 Global memroy error detected
+ TpAbl1bDebugSync = 0xE107, ///< ABL 1b Debug Synchronization Function
+ TpAbl4bDebugSync = 0xE108, ///< ABL 4b Debug Synchronization Function
+ TpAbl1bBegin = 0xE109, ///< AblbBegin
+ TpAbl4bBegin = 0xE10A, ///< Ab4bBegin
+
+ TpProcApobHmacFailOnS3 = 0xE10B, ///< BSP encountered HMAC fail on APOB Header
+
+ TpAbl18End = 0xE10C, ///< ABL 18 End
+ TpAbl18ResumeInitialization = 0xE10D, ///< ABL 18 Resume boot
+ TpAbl15End = 0xE10E, ///< ABL 15 End
+ TpAbl15Initialization = 0xE10F, ///< ABL 15 Initialization
+
+ TpProcBeforeUmcBasedDeviceInit = 0xE110, ///< Before UMC based device initialization
+ TpProcAfterUmcBasedDeviceInit = 0xE111, ///< After UMC based device initialization
+
+ TpAblErroGeneralAssert = 0xE2A0, ///< ABL Eroor General ASSERT
+ TpAblErrorUnknown = 0xE2A1, ///< Unknown Error
+ TpAblErrorLogInitError = 0xE2A3, ///< ABL Error Log Inig Error
+ TpAblErrorOdtHeap = 0xE2A4, ///< ABL Error for On DIMM thermal Heap allocation error
+ TpAblErrorMemoryTest = 0xE2A5, ///< ABL Error for memory test error
+ TpAblErrorExecutingMemoryTest = 0xE2A6, ///< ABL Error while executing memory test error
+ TpAblErrorDpprMemAutoHeapAlocError = 0xE2A7, ///< ABL Error DDR Post Packge Repair Mem Auto Heap Alloc error
+ TpAblErrorDpprNoApobHeapAlocError = 0xE2A8, ///< ABL Error for DDR Post Package repair Apob Heap Alloc error
+ TpAblErrorDpprNoPprTblHeapAlocError = 0xE2A9, ///< ABL Error for DDR Post Package Repair No PPR Table Heap Aloc error
+ TpAblErrorEccMemAutoHeapAlocError = 0xE2AA, ///< ABL Error for Ecc Mem Auto Aloc Error error
+ TpAblErrorSocScanHeapAlocError = 0xE2AB, ///< ABL Error for Soc Scan Heap Aloc error
+ TpAblErrorSocScanNoDieError = 0xE2AC, ///< ABL Error for Soc Scan No Die error
+ TpAblErrorNbTecHeapAlocError = 0xE2AD, ///< ABL Error for Nb Tech Heap Aloc error
+ TpAblErrorNoNbConstError = 0xE2AE, ///< ABL Error for No Nb Constructor error
+ TpAblErrorNoTechConstError = 0xE2B0, ///< ABL Error for No Tech Constructor error
+ TpAblErrorAbl1bAutoAloc = 0xE2B1, ///< ABL Error for ABL1b Auto Alocation error
+ TpAblErrorAbl1bNoNbConst = 0xE2B2, ///< ABL Error for ABL1b No NB Constructor error
+ TpAblErrorAbl2NoNbConst = 0xE2B3, ///< ABL Error for ABL2 No Nb Constructor error
+ TpAblErrorAbl3AutoAloc = 0xE2B4, ///< ABL Error for ABL3 Auto Allocation error
+ TpAblErrorAbl3NoNbConst = 0xE2B5, ///< ABL Error for ABL3 No Nb Constructor error
+ TpAblErrorAbl1bGen = 0xE2B6, ///< ABL Error for ABL1b General error
+ TpAblErrorAbl2Gen = 0xE2B7, ///< ABL Error for ABL2 General error
+ TpAblErrorAbl3Gen = 0xE2B8, ///< ABL Error for ABL3 General error
+ TpAblErrorGetTargetSpeed = 0xE2B9, ///< ABL Error for Get Target Speed error
+ TpAblErrorFlowP1FamilySupport = 0xE2BA, ///< ABL Error for Flow P1 Family Support error
+ TpAblErrorNoValidDdr4Dimms = 0xE2BB, ///< ABL Error for No Valid Ddr4 Dimms error
+ TpAblErrorNoDimmPresent = 0xE2BC, ///< ABL Error for No Dimm Present error
+ TpAblErrorFlowP2FamilySupport = 0xE2BD, ///< ABL Error for Flow P2 Family Supprot error
+ TpAblErrorHeapDealocForPmuSramMsgBlock = 0xE2BE, ///< ABL Error for Heap Deallocation for PMU Sram Msg Block error
+ TpAblErrorDdrRecovery = 0xE2BF, ///< ABL Error for DDR Recovery error
+ TpAblErrorRrwTest = 0xEBC0, ///< ABL Error for RRW Test error
+ TpAblErrorOdtInit = 0xE2C1, ///< ABL Error for On Die Thermal error
+ TpAblErrorHeapAllocForDctStructAndChDefStruct = 0xE2C2, ///< ABL Error for Heap Allocation For Dct Struct Amd Ch Def structure error
+ TpAblErrorHeapAlocForPmuSramMsgBlock = 0xE2C3, ///< ABL Error for Heap Allocation for PMU SRAM Msg block error
+ TpAblErrorHeapPhyPllLockFailure = 0xE2C4, ///< ABL Error for Heap Phy PLL lock Flure error
+ TpAblErrorPmuTraining = 0xE2C5, ///< ABL Error for Pmu Training error
+ TpAblErrorFailureToLoadOrVerifyPmuFw = 0xE2C6, ///< ABL Error for Failure to Load or Verify PMU FW error
+ TpAblErrorAllocateForPmuSramMsgBlockNoInit = 0xE2C7, ///< ABL Error for Allocate for PMU SRAM Msg Block No Init error
+ TpAblErrorFailureBiosPmuFwMismatchAgesaPmuFwVersion = 0xE2C8, ///< ABL Error for Failure BIOS PMU FW Mismatch AGESA PMU FW version error
+ TpAblErrorAgesaMemoryTest = 0xE2C9, ///< ABL Error for Agesa memory test error
+ TpAblErrorDeallocateForPmuSramMsgBlock = 0xE2CA, ///< ABL Error for Deallocate for PMU SRAM Msg Block error
+ TpAblErrorModuleTypeMismatchRDimm = 0xE2CB, ///< ABL Error for Module Type Mismatch RDIMM error
+ TpAblErrorModuleTypeMismatchLRDimm = 0xE2CC, ///< ABL Error for Module type Mismatch LRDIMM error
+ TpAblErrorMemAutoNvdimm = 0xE2CD, ///< ABL Error for MEm Auto NVDIM error
+ TpAblErrorUnknownResponse = 0xE2CE, ///< ABL Error for Unknowm Responce error
+ TpAblErrorMemOverclockErrorRrwTestResults = 0xE2CF, ///< ABL Error for Over Clock Error RRW Test Results Error
+ TpAblErrorOverClockErrorPmuTraining = 0xE2D0, ///< ABL Error for Over Clock Error PMU Training Error
+ TpAblErrorAbl1GenError = 0xE2D1, ///< ABL Error for ABL1 General Error
+ TpAblErrorAbl2GenError = 0xE2D2, ///< ABL Error for ABL2 General Error
+ TpAblErrorAbl3GenError = 0xE2D3, ///< ABL Error for ABL3 General Error
+ TpAblErrorAbl5GenError = 0xE2D4, ///< ABL Error for ABL4 General Error
+ TpAblErrorOverClockMemInit = 0xE2D5, ///< ABL Error over clock Mem Init Error
+ TpAblErrorOverClockMemOther = 0xE2D6, ///< ABL Error over clock Mem Other Error
+ TpAblErrorAbl6GenError = 0xE2D7, ///< ABL Error for ABL6 General Error
+ TpEventLogInit = 0xE2D8, ///< ABL Error Event Log Error
+ TpAblErrorAbl1FatalError = 0xE2D9, ///< ABL Error FATAL ABL1 Log Error
+ TpAblErrorAbl2FatalError = 0xE2DA, ///< ABL Error FATAL ABL2 Log Error
+ TpAblErrorAbl3FatalError = 0xE2DB, ///< ABL Error FATAL ABL3 Log Error
+ TpAblErrorAbl4FatalError = 0xE2DC, ///< ABL Error FATAL ABL4 Log Error
+ TpAblErrorSlaveSyncFunctionExecutionError = 0xE2DD, ///< ABL Error Slave Sync function execution Error
+ TpAblErrorSlaveSyncCommWithDataSentToMasterError = 0xE2DE, ///< ABL Error Slave Sync communicaton with data set to master Error
+ TpAblErrorSlaveBroadcastCommFromMasterToSlaveError = 0xE2DF, ///< ABL Error Slave broadcast communication from master to slave Error
+ TpAblErrorAbl6FatalError = 0xE2E0, ///< ABL Error FATAL ABL6 Log Error
+ TpAblErrorSlaveOfflineMsgError = 0xE2E1, ///< ABL Error Slave Offline Error
+ TpAblErrorSlaveInformsMasterErrorInoError = 0xE2E2, ///< ABL Error Slave Informs Master Error Info Error
+ TpAblErrorHeapLocateForPmuSramMsgBlock = 0xE2E3, ///< ABL Error Error Heap Locate for PMU SRAM Msg Block Error
+ TpAblErrorAbl2AutoAloc = 0xE2E4, ///< ABL Error ABL2 Auto Error
+ TpAblErrorFlowP3FamilySupport = 0xE2E5, ///< ABL Error Flow P3 Family support Error
+ TpAblErrorAbl4GenError = 0xE2E5, ///< ABL Error Abl 4 Gen Error
+ TpAblErrorMbistHeapAlloc = 0xE2EB, ///< ABL Error MBIST Heap Allocation Error
+ TpAblErrorMbistResultsError = 0xE2EC, ///< ABL Error MBIST Results Error
+ TpAblErrorNoDimmSmbusInfoError = 0xE2ED, ///< ABL Error NO Dimm Smcus Info Error
+ TpAblErrorPorMaxFreqTblError = 0xE2EE, ///< ABL Error Por Max Freq Table Error
+ TpAblErrorUnsupportedDimmConfuglError = 0xE2EF, ///< ABL Error Unsupproted DIMM Config Error
+ TpAblErrorNoPsTableError = 0xE2F0, ///< ABL Error No Ps Table Error
+ TpAblErrorCadBusTmgNoFoundError = 0xE2F1, ///< ABL Error Cad Bus Timing Not Found Error
+ TpAblErrorDataBusTmgNoFoundError = 0xE2F2, ///< ABL Error Data Bus Timing Not Found Error
+ TpAblErrorLrIbtNotFoundError = 0xE2F3, ///< ABL Error LrDIMM IBT Not Found Error
+ TpAblErrorUnsupportedDimmConfigMaxFreqError = 0xE2F4, ///< ABL Error Unsupprote Dimm Config Max Freq Error Error
+ TpAblErrorMr0NotFoundError = 0xE2F5, ///< ABL Error Mr0 Not Found Error
+ TpAblErrorOdtPAtNotFoundError = 0xE2F6, ///< ABL Error Obt Pattern Not found Error
+ TpAblErrorRc10OpSpeedNotFoundError = 0xE2F7, ///< ABL Error Rc10 Op Speed Not FOund Error
+ TpAblErrorRc2IbtNotFoundError = 0xE2F8, ///< ABL Error Rc2 Ibt Not Found Error
+ TpAblErrorRttNotFoundError = 0xE2F9, ///< ABL Error Rtt Not Found Error
+ TpAblErrorChecksumReStrtError = 0xE2FA, ///< ABL Error Checksum ReStrt Results Error
+ TpAblErrorNoChipselectError = 0xE2FB, ///< ABL Error No Chipselect Results Error
+ TpAblErrorNoCommonCasLAtError = 0xE2FC, ///< ABL Error No Common Cas Latency Results Error
+ TpAblErrorCasLatXceedsTaaMaxError = 0xE2FD, ///< ABL Error Cas Latecncy exceeds Taa Max Error
+ TpAblErrorNvdimmArmMissmatcPowerPolicyError = 0xE2FE, ///< ABL Error Nvdimm Arm Missmatch Power Policy Error
+ TpAblErrorNvdimmArmMissmatchPowerSouceError = 0xE2FF, ///< ABL Error Nvdimm Arm Missmatch Power Source Error
+ TpAblErrorAbl1MemInitError = 0xE300, ///< ABL Error ABL 1 Mem Init Error
+ TpAblErrorAbl2MemInitError = 0xE301, ///< ABL Error ABL 2 Mem Init Error
+ TpAblErrorAbl4MemInitError = 0xE302, ///< ABL Error ABL 4 Mem Init Error
+ TpAblErrorAbl6MemInitError = 0xE303, ///< ABL Error ABL 6 Mem Init Error
+ TpAblErrorAbl1ErrorReportError = 0xE304, ///< ABL Error ABL 1 error repor Error
+ TpAblErrorAbl2ErrorReportError = 0xE305, ///< ABL Error ABL 2 error repor Error
+ TpAblErrorAbl3ErrorReportError = 0xE306, ///< ABL Error ABL 3 error repor Error
+ TpAblErrorAbl4ErrorReportError = 0xE307, ///< ABL Error ABL 4 error repor Error
+ TpAblErrorAbl6ErrorReportError = 0xE308, ///< ABL Error ABL 6 error repor Error
+ TpAblErrorMsgSlaveSyncFunctionExecutionError = 0xE30A, ///< ABL Error message slave sync function execution Error
+ TpAblErrorSlaveOfflineError = 0xE30B, ///< ABL Error slave offline Error
+ TpAblErrorSyncMasterError = 0xE30C, ///< ABL Error Sync Master Error
+ TpAblErrorSlaveInformsMasterInfoMsgError = 0xE30D, ///< ABL Error Slave Informs Master Info Message Error
+ TpAblErrorMemLrdimmMixCfgError = 0xE30E, ///< ABL Error Mix Hynix LRDIMM with other vendor LRDIMM in a channel
+ TpAblErrorGenAssertError = 0xE30F, ///< ABL Error General Assert Error
+ TpAblErrorNoDimmOnAnyChannelInSystem = 0xE310, ///< ABL ErrorNo Dimms On Any Channel in sysem
+ TpAblErrorSharedHeapAlocError = 0xE311, ///< ABL Error for Shared Heap Aloc error
+ TpAblErrorMainHeapAlocError = 0xE312, ///< ABL Error for Main Heap Aloc error
+ TpAblErrorSharedAutolocError = 0xE313, ///< ABL Error for Shared Heap loc error
+ TpAblErrorMainAutolocError = 0xE314, ///< ABL Error for Main Heap loc error
+ TpAblErrorNoMemoryAvailableInSystem = 0xE316, ///< ABL Error No memory available in system
+ TpAblErrorMixedEccAndNonEccDimmInChannel = 0xE320, ///< ABL Error Mixed Ecc and Non-Ecc DIMM in a channel
+ TpAblErrorMixed3DSAndNon3DSDimmInChannel = 0xE321, ///< ABL Error Mixed 3DS and Non-3DS DIMM in a channel
+ TpAblErrorMixedX4AndX8DimmInChannel = 0xE322, ///< ABL Error Mixed x4 and x8 DIMM in a channel
+ TpAblMbistDefaultRrwTest = 0xE323, ///< ABL Memory MBIST Rrw default test
+ TpAblMemoryMbistInterfaceTest = 0xE324, ///< ABL Memory MBIST Interface test
+ TpAblMemoryMbistDataEyeTest = 0xE325, ///< ABL Memory MBIST DataEye
+ TpAblMemoryPostPackageRepair = 0xE326, ///< ABL Memory Post Package Repair
+ TpAblErrorS0i3DfRestoreBufferError = 0xE327, ///< ABL Error S0i3 DF restore buffer Error
+ TpAblErrorCpuOPNMismatchInSockets = 0xE328, ///< ABL Error CPU OPN Mismatch in case of Multi Socket population
+ TpProcRecoverableApcbChecksumError = 0xE329, ///< Recoverable APCB Checksum Error
+ TpProcFatalApcbChecksumError = 0xE32A, ///< Fatal APCB Checksum Error
+ TpAblErrorBistFailure = 0xE32B, ///< ABL Error BIST Failure
+ EndAgesaTps = 0xEFFF, ///< EndAgesas
+} AGESA_TP;
+
+
+#endif
+
+
diff --git a/cezanne/PSP/AgesaBLReleaseNotes.txt b/cezanne/PSP/AgesaBLReleaseNotes.txt
new file mode 100644
index 0000000..f8207ec
--- /dev/null
+++ b/cezanne/PSP/AgesaBLReleaseNotes.txt
@@ -0,0 +1,2385 @@
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN0B036070 for Cezanne
+
+Date: November 03 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN0B036070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x0B036070
+
+Features and Fixes:
+project Program/
+ PLAT-72212 CZN: ABL Release RABLCZN0B036070
+ PLAT-68263 [CZN] [ABL] Increase SPL for production
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN0A196070 for Cezanne
+
+Date: October 19 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN0A196070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x0A196070
+
+Features and Fixes:
+project Memory/
+ PLAT-71128 [DDR4 tSYNC_GEAR] Update the value of tSync Gear to tMod + 4
+ PLAT-70899 [CZN] Correcting tXSR timing
+
+project Program/
+ PLAT-71402 CZN: ABL Release RABLCZN0A196070
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN0A126070 for Cezanne
+
+Date: October 12 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN0A126070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x0A126070
+
+Features and Fixes:
+project FCH/
+ PLAT-70317 Update ESPI initialization sequence in CZN
+
+project Program/
+ PLAT-71052 CZN: ABL Release RABLCZN0A126070
+ PLAT-68581: [CZN][PSP] CfgRegInstAccRegLock set to 0 after windows sleep and wakup
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN09286070 for Cezanne
+
+Date: September 28 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN09286070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x09286070
+
+Features and Fixes:
+project APCB/
+ PLAT-69931 [CZN] Pass PSP-fTPM NVstorage size info to PSP
+
+project APOB/
+ PLAT-69940 S0i3 ABL: APCB table load time optimization (S3 APCB restore)
+
+project FCH/
+ PLAT-69987 Set APCB_TOKEN_UID_ESPI_IORANGEx_SIZE_VALUE to 0 ABL will skip IORANGx decode
+
+project Lib/
+ PLAT-69940 S0i3 ABL: APCB table load time optimization (S3 APCB restore)
+
+project Memory/
+ PLAT-68554 [CZN] Remove Presilicon skip of Program UMC Keys
+
+project Program/
+ PLAT-70498 CZN: ABL Release RABLCZN09286070
+ PLAT-69940 S0i3 ABL: APCB table load time optimization (S3 APCB restore)
+ PLAT-69931 [CZN] Pass PSP-fTPM NVstorage size info to PSP (patch 1)
+ PLAT-69931 [CZN] Pass PSP-fTPM NVstorage size info to PSP
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN09216070 for Cezanne
+
+Date: September 21 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\RABLCZN09216070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN09216070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x09216070
+
+Features and Fixes:
+project Lib/
+ PLAT-69940 S0i3 ABL: APCB table load time optimization, part2
+project Memory/
+ PLAT-69999 [RN][CZN] - Changing Vref CA Seed for LPDDDR4x
+project Program/
+ PLAT-70145 CZN: ABL Release RABLCZN09216070
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN09176070 for Cezanne
+
+Date: September 17 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\RABLCZN09176070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN09176070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x09176070
+
+Features and Fixes:
+project APCB/
+ PLAT-69912 [CZN] Create new ABL interface for laptop platform to adjust VDDIO before training
+project APOB/
+ PLAT-69940 S0i3 ABL: APCB table load time optimization
+project Lib/
+ PLAT-69940 S0i3 ABL: APCB table load time optimization
+ PLAT-69912 [CZN] Create new ABL interface for laptop platform to adjust VDDIO before training
+project Program/
+ PLAT-69841 CZN: ABL Release RABLCZN09146070
+ PLAT-69940 S0i3 ABL: APCB table load time optimization
+ PLAT-69912 [CZN] Create new ABL interface for laptop platform to adjust VDDIO before training
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN09146070 for Cezanne
+
+Date: September 14 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\RABLCZN09146070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m RABLCZN09146070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x09146070
+
+Features and Fixes:
+project FCH/
+ Revert "PLAT-68659 [CZN]Code enhencement to mask eSPI slave IO/MMIO decode during eSPI initialization"
+ PLAT-69221 [CZN]eSPI/ACPI module implementation in ABL
+
+project NBIO/
+ PLAT-69697 [RyzenMaster][VMR/CZN] Max allowed Fabric clock speed should be increased to 4000MHz
+
+project Program/
+ PLAT-69841 CZN: ABL Release RABLCZN09146070
+ PLAT-68263 [CZN] [ABL] Increase SPL for production
+ PLAT-64342 [CZN] ABL needs to pass TPM config to PSP (Cover Context Restore path)
+ PLAT-69221 [CZN]eSPI/ACPI module implementation in ABL
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN09076070 for Cezanne
+
+Date: September 07 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN09076070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN09076070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x09076070
+
+Features and Fixes:
+project APOB/
+ PLAT-66640:[CZN] Replicate to Cezanne Report fixed 1T hole above 4G as reserved to OS
+
+project CCX/
+ PLAT-67685: [CZN_AM4][Farm] system hang with PC:A59E while running S5*1000. PC stuck at 206C1 #ChangeCorePllFreq(): .Fail rate:1/24
+
+project FCH/
+ PLAT-68659 [CZN]Code enhencement to mask eSPI slave IO/MMIO decode during eSPI initialization
+
+project Lib/
+ PLAT-69202 [CZN] Data abort when triggering error out script
+ PLAT-68984 [CZN] Add EcRamAccessLib for OC and Board ID detection
+ PLAT-68827 [VanGogh] Split OC help function from APCB to OverclockingMiscLib
+
+project Program/
+ PLAT-69303 CZN: ABL Release WABLCZN09076070
+ PLAT-68984 [CZN] Add EcRamAccessLib for OC and Board ID detection
+ PLAT-68827 [VanGogh] Split OC help function from APCB to OverclockingMiscLib
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08316070 for Cezanne
+
+Date: August 31 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08316070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08316070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08316070
+
+Features and Fixes:
+project Lib/
+ PLAT-67466 [VanGogh] Split SPD read function from APCB to SpdReadPlatformLib
+project Memory/
+ PLAT-68714 [CZN] DllGain update to support Fast CLDO Bypass
+project Program/
+ PLAT-67466 [VanGogh] Split SPD read function from APCB to SpdReadPlatformLib
+ PLAT-66952:(CZN AM4) when disabling igpu and using dgpu, sdma0 halt blocks s0i3 entry (missing call in ABL)
+ PLAT-68743 CZN: ABL Release WABLCZN08266070
+project Tools/
+ PLAT-68917 [CZN] Update ABL signed with new signing keys
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08266070 for Cezanne
+
+Date: August 26 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08266070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08266070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08266070
+
+Features and Fixes:
+project Lib/
+ PLAT-61090 [RN] System hang when write 0xE to Port CF9h to initiate a cold reset
+ PLAT-68575 [CZN] Enhance memory copy and memory fill to reduce post-time
+
+project Memory/
+ PLAT-68714 [CZN] DllGain update to support Fast CLDO Bypass
+ PLAT-68557 [CZN] Enhance PIE programming to reduce post-time
+
+project Program/
+ PLAT-68743 CZN: ABL Release WABLCZN08266070
+ PLAT-68214 [CZN][ComnoAM4v2][Artic]: BIOS can not auto load default when run Memory OC Failure Recovery.
+
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08246070 for Cezanne
+
+Date: August 24 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08246070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08246070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08246070
+
+Features and Fixes:
+
+project Lib/
+ PLAT-67856 [CZN-FP6]DataCtrl bit 19:16 and bit 0 not change for TSME enable/disable
+ PLAT-68150 [CZN] Reduce post-time when Abl Console out disabled
+
+project Program/
+ PLAT-68552 CZN: ABL Release WABLCZN08246070
+ PLAT-68238: [CZN] Remove ABL RT global build file dependency
+ PLAT-68220 ComboAM4v2 1082RC1 BadWord issue - PSP
+ PLAT-64962 [RN] Script Opcode does not work when PMU training fail
+ PLAT-68211: [CZN] ABL RT Release RABLRTCZN20081800
+ PLAT-68151: [CZN] Increment SPL value to support firmware anti rollback feature for production
+ PLAT-68150 [CZN] Reduce post-time when Abl Console out disabled
+
+project Tools/
+ PLAT-68238: [CZN] Remove ABL RT global build file dependency
+ PLAT-68151: [CZN] Increment SPL value to support firmware anti rollback feature for production
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08176070 for Cezanne
+
+Date: August 17 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08176070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08176070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08176070
+
+project Lib/
+ PLAT-68015 [CZN] Enhance interface for MCM Sync Function
+ PLAT-58658: [CZN] Unified BIOS - Skip APCB recovery dynamically
+
+project Memory/
+ PLAT-68015 [CZN] Enhance interface for MCM Sync Function
+
+project Program/
+ PLAT-68133 CZN: ABL Release WABLCZN08176070
+ PLAT-68015 [CZN] Enhance interface for MCM Sync Function
+ PLAT-58658: [CZN] Unified BIOS - Skip APCB recovery dynamically
+ PLAT-58658: [CZN] Unified BIOS - Skip APCB recovery dynamically
+
+project Tools/
+ PLAT-67928 [ABL TOOLS] Updates to PMU FW Signing Script for CZN
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08106070 for Cezanne
+
+Date: August 10 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08106070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08106070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08106070
+
+project Memory/
+ PLAT-67289 [CZN] Disabling PPT when reducing speed to 1600
+
+project Program/
+ PLAT-67740 CZN: ABL Release WABLCZN08106070
+ PLAT-67004 [Cezanne AM4/FP6] Memory training fail after VDDIO and Overclocking change
+ PLAT-67266: [CZN] Update build flow to support Security Patch Level (SPL) value
+
+project Tools/
+ PLAT-67266: [CZN] Update build flow to support Security Patch Level (SPL) value
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN08036070 for Cezanne
+
+Date: August 03 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN08036070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN08036070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x08036070
+
+project Memory/
+ PLAT-66712 CZN FP6: Support BIOS automatic Memory OC Failure Recovery
+
+project Program/
+ PLAT-67387 CZN: ABL Release WABLCZN08036070
+ PLAT-66712 CZN FP6: Support BIOS automatic Memory OC Failure Recovery
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN07276071 for Cezanne
+
+Date: July 27 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN07276071
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN07276071.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x07276071
+
+project Lib/
+ PLAT-59907 BIOS: CBS options to set UMC::DataCtrl rigister fileds are not workingble/Disable
+
+project Memory/
+ PLAT-59907 BIOS: CBS options to set UMC::DataCtrl rigister fileds are not workingble/Disable
+
+project Program/
+ PLAT-67107 CZN: ABL Release WABLCZN07276071
+ PLAT-59907 BIOS: CBS options to set UMC::DataCtrl rigister fileds are not workingble/Disable
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN07276070 for Cezanne
+
+Date: July 27 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN07276070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN07276070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x07276070
+
+project APCB/
+ PLAT-66912 [ABL][CZN FP6/AM4] Add APCB token to control RPMC
+
+project CCX/
+ PLAT-66756: [CZN] BIOS: Please use attached S3 image (ID = 19506dac) to the BIOS
+
+project Lib/
+ PLAT-65840 [CZN] Memory token get method convert into APCB V3 native interface
+
+project Memory/
+ PLAT-66606 [CZN FP6] termination was incorrect when under OC mode
+
+project NBIO/
+ PLAT-62412 CZN AM4 BIOS lacks a way to disable ChldxHash (Auto=Enable)
+ PLAT-66195 [IQE][CZN-FP6][20H1]cannot resume HWDRM playback on Netflix/PRDJS after S3
+
+project Program/
+ PLAT-67091 CZN: ABL Release WABLCZN07276070
+ PLAT-66912 [ABL][CZN FP6/AM4] Add APCB token to control RPMC
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN07206070 for Cezanne
+
+Date: July 20 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN07206070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN07206070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x07206070
+
+project DF/
+ PLAT-66405: [CZN] ComboAM4v2 1080 RC3 DF registers init value fail
+
+project Lib/
+ PLAT-66453 [CZN] Enable Fuse control Pro checking
+
+project Program/
+ PLAT-66778 CZN: ABL Release WABLCZN07206070
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN07136070 for Cezanne
+
+Date: July 13 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN07136070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN07136070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x07136070
+
+project APCB/
+ PLAT-65987 [CZN] APCB Token to override Maximum Activity Count (MAC) for memory
+ PLAT-65981 [CZN] Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings
+
+project Lib/
+ PLAT-56480 [RN_AM4] DDR4 Overclocking Range to DDR8000 (4000MHz)
+ PLAT-66152 [CZN] ABL serial out function fail on FCH UART0
+
+project Memory/
+ PLAT-65987 [CZN] APCB Token to override Maximum Activity Count (MAC) for memory
+ PLAT-65981 [CZN] Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings
+ PLAT-65867 - [CZN] CZN LP4/4x - Disabling DBI by default
+
+project Program/
+ PLAT-66380 CZN: ABL Release WABLCZN07136070
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN07066070 for Cezanne
+
+Date: July 06 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for FP6
+ AgesaBootloader_U_prod_CZN.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for DDR4
+ AgesaBootloader_U_prod_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ ABL Binary for LPDDR4
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Cezanne\WABLCZN07066070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN07066070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x07066070
+
+project Memory/
+ PLAT-65455 [CZN] LP4 RFM - using the correct RAAIMT increment for new Tref
+ PLAT-65487 [CZN][LPDDR4] Setup option for MBIST Vref step not working
+
+project Program/
+ PLAT-65976 CZN: ABL Release WABLCZN07066070
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN06296070 for Cezanne
+
+Date: June 29 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\VMR\ This Release notes file for AM4
+ AgesaBootloader_U_prod_VMR AgesaModulePkg\Firmwares\VMR\ Main AGESA Bootloader
+
+DXIO Version: v
+DXIO PHY Version: v
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Vermeer\WABLCZN06296070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN06296070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x06296070
+
+project Memory/
+ PLAT-65744 [CZN] Margin test fail when power optimize enabled with SR+DR dimm
+
+project NBIO/
+ PLAT-62412 CZN AM4 BIOS lacks a way to disable ChldxHash (called before ConfigSocRail)
+
+project Program/
+ PLAT-65768 CZN: ABL Release WABLCZN06296070
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN06226070 for Cezanne
+
+Date: June 22 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\VMR\ This Release notes file for AM4
+ AgesaBootloader_U_prod_VMR AgesaModulePkg\Firmwares\VMR\ Main AGESA Bootloader
+
+DXIO Version: v
+DXIO PHY Version: v
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Vermeer\WABLCZN06226070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN06226070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x06226070
+
+project Lib/
+ PLAT-64962 [RN] Script Opcode does not work when PMU training fail
+
+project Memory/
+ PLAT-64579 [CZN] LP4 - need DFECtrl=0 when Power Optimization enabled
+
+project Program/
+ PLAT-65479 CZN: ABL Release WABLCZN06226070
+ PLAT-64962 [RN] Script Opcode does not work when PMU training fail
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN06156070 for Cezanne
+
+Date: June 15 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\VMR\ This Release notes file for AM4
+ AgesaBootloader_U_prod_VMR AgesaModulePkg\Firmwares\VMR\ Main AGESA Bootloader
+
+DXIO Version: v
+DXIO PHY Version: v
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Vermeer\WABLCZN06156070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN06156070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x06156070
+
+project Memory/
+ PLAT-64091 [CZN] LP4 - DDR PHY Power Saving
+ PLAT-64393 [CZN AM4/RN AM4] Disable 'Memory Power Optimized Settings' on AM4 program
+
+project Program/
+ PLAT-65090 CZN: ABL Release WABLCZN06156070
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+----------------------------------------------------------------------------
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN06086070 for Cezanne
+
+Date: June 08 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\VMR\ This Release notes file for AM4
+ AgesaBootloader_U_prod_VMR AgesaModulePkg\Firmwares\VMR\ Main AGESA Bootloader
+
+DXIO Version: v
+DXIO PHY Version: v
+
+Path to files:
+ \\atlcorpnetfs\Biosonly\simulation\Vermeer\WABLCZN06086070
+
+Repo Manifest Info:
+ repo init -u ssh://gerritgit/BIOS/ec/Client/Components/AGESA/ABL-V2/manifest -b Custom -m WABLCZN06086070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x06086070
+
+project Memory/
+ PLAT-64717 [CZN ]need to add offset for M1 & M3 on CPU side at speed 3200 & 2933 Single Rank
+ PLAT-63893 Renior FP6 DDR4 BIOS's MBIST data eye function is abnormal
+ PLAT-64124 [Renoir] DRAM ECC Symbol Size setting mismatching
+ PLAT-64050 [CZN AM4] Post Code stuck at AC90 with 4GB 2133 UDIMMs
+
+project Program/
+ PLAT-64741 CZN: ABL Release WABLCZN06086070
+ PLAT-64342 [CZN] ABL needs to pass TPM config to PSP
+
+"This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP)."
+--------------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN05256070 for Cezanne
+
+Date: May 25, 2020
+
+--------------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+Path to files:
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN05256070.xml
+
+Based On:
+ trunk_Cn
+
+ABL Version String:
+ 0x05256070
+
+Features and Fixes:
+project APCB/
+ PLAT-63830 [VanGogh] Remove unsupported feature Conditional Pso
+ PLAT-59099 [CZN] PSP BL loads either MP2-SFH or MP2-I2C based on AMD PBS option - ABL
+project APOB/
+ PLAT-63699: [VanGogh] MEM - Update ABL-to-PMFW Handshake for LPDDR5
+project CCX/
+ PLAT-63716 [GN B0] BIOS: Please include attached S3 Image (S3 Image ID = 190134f6) for B0 bringup
+ PLAT-61461 BIOS: S3 Image for DSM A0 BIOS
+project DF/
+ PLAT-63771 DramContentionMonitor[DramContentionMonEn] should be cleared for SpecDramRd optimised settings
+ PLAT-63714 GN B0 PPR has incorrect init for Floss widget config
+project Lib/
+ PLAT-63830 [VanGogh] Remove unsupported feature Conditional Pso
+ PLAT-63699: [VanGogh] MEM - Update ABL-to-PMFW Handshake for LPDDR5
+project Memory/
+ PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting(enable lpddr4)
+ PLAT-63572 [CZN] Incorrect MemClkFreq above DDR-5000
+ PLAT-63776: Extend the refresh off delay in Memory Healing BIST
+ PLAT-63830 [VanGogh] Remove unsupported feature Conditional Pso
+ PLAT-61267: [VanGogh] MEM - UMC Turn around timings
+ PLAT-62341 DFE and VrefDac1 Off For Power Savings
+ PLAT-63699: [VanGogh] MEM - Update ABL-to-PMFW Handshake for LPDDR5
+project NBIO/
+ PLAT-59099 [CZN] PSP BL loads either MP2-SFH or MP2-I2C based on AMD PBS option - ABL
+ PLAT-63699: [VanGogh] MEM - Update ABL-to-PMFW Handshake for LPDDR5
+project Program/
+ PLAT-64007 CZN: ABL Release WABLCZN05256070
+ PLAT-63873:CBS Option and APCB token requested for X3D Disable
+ PLAT-63830 [VanGogh] Remove unsupported feature Conditional Pso
+ PLAT-59099 [CZN] PSP BL loads either MP2-SFH or MP2-I2C based on AMD PBS option - ABL
+ PLAT-63726 [VanGogh] ABL Release MABLMV05196010
+ PLAT-63699: [VanGogh] MEM - Update ABL-to-PMFW Handshake for LPDDR5
+
+--------------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN05186070 for Cezanne
+
+Date: May 18, 2020
+
+--------------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+Path to files:
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN05186070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x05186070
+
+Features and Fixes:
+project APCB/
+ MERO-628:[Mero] Add support for enabling all PCIe links before x86 for Chachani SLT - ABL
+ PLAT-61324, [Milan] ABL Support for pre-x86 dTPM
+ PLAT-63356: Milan MEM - Add support for staggering LRDIMM Refresh after Exit Self-Refresh
+project APOB/
+ PLAT-61223: [VanGogh] MEM - UMC AMD Timings
+project CCX/
+ PLAT-54775:Replicate to Van Gogh [VMR] Clear SmmLock at the beginning of S3 resume
+ PLAT-63218 [GN B0] BIOS: Please include attached S3 Image (S3 Image ID =190194b4) for B0 bring
+ PLAT-61260: Set InitPkg7[2] = 0 and disable Enhanced Bus Lock
+ PLAT-63221 [VMR B0] Use attached S3 image (ID=19211ba4) for B0 bring up BIOS
+project DF/
+ PLAT-63585 [VN] DF registers init value fail
+ Mero-673 [Mero-ABL] Adjust FMR base address
+ PLAT-61260: Set InitPkg7[2] = 0 and disable Enhanced Bus Lock
+project Lib/
+ PLAT-61223: [VanGogh] MEM - UMC AMD Timings
+ PLAT-63093: [Milan] "DRAM Hardware History Mechanism" CBS option not functional
+ MERO-151 [Mero-ABL] Boot.cfg.500 Boot config table definies multiple memory configurations chosen during boot
+ PLAT-63474: PLAT-[MR][VN] Update Memory Symbols to 'FF3' from 'RN'
+ PLAT-63218 [GN B0] BIOS: Please include attached S3 Image (S3 Image ID =190194b4) for B0 bring
+ PLAT-63356: Milan MEM - Add support for staggering LRDIMM Refresh after Exit Self-Refresh
+ Mero-635 [Mero-Platform] Merge code from MVG to client master
+ PLAT-63221 [VMR B0] Use attached S3 image (ID=19211ba4) for B0 bring up BIOS
+project Memory/
+ PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting
+ PLAT-63670 [VMR]interleaving data is incorrect for one DIMM single rank memory on Artic
+ PLAT-63459 [RN AM4]interleaving data is incorrect for one DIMM single rank memory on Artic
+ PLAT-61223: [VanGogh] MEM - UMC AMD Timings
+ PLAT-63093: [Milan] "DRAM Hardware History Mechanism" CBS option not functional
+ PLAT-61221: [VanGogh] MEM - PMU Handshake with ABL
+ PLAT-61220: [VanGogh] MEM - Load PMU FW and mapping images
+ MERO-151 [Mero-ABL] Boot.cfg.500 Boot config table definies multiple memory configurations chosen during boot
+ PLAT-61377 [MVG-ABL] ABL error to load/verify PMU FW
+ PLAT-63474: PLAT-[MR][VN] Update Memory Symbols to 'FF3' from 'RN'
+ PLAT-62418: Milan MEM - Replicate fix in Plat-57708 to Milan
+ PLAT-63356: Milan MEM - Add support for staggering LRDIMM Refresh after Exit Self-Refresh
+ PLAT-63354: Milan - Mem - Dram timing tables have old value for tDLLk for >DDR2400
+project NBIO/
+ MERO-587:[Mero][CVIP] S-PCIe: CVIP PCIe bridge hotplug enabling
+ MERO-646:Add new SVC call for reporting empty NVMe disk
+project Program/
+ PLAT-61223: [VanGogh] MEM - UMC AMD Timings
+ PLAT-61223: [VanGogh] MEM - UMC AMD Timings
+ Prepare and Release WABLGN05205010 for Milan Weekly BIOS
+ Update release note for 0050 release
+ MERO-151 [Mero-ABL] Boot.cfg.500 Boot config table definies multiple memory configurations chosen during boot
+ PLAT-63523: [MR][VN] Update ABL Build script to point to correct version of Python
+ PLAT-63474: PLAT-[MR][VN] Update Memory Symbols to 'FF3' from 'RN'
+ MERO-628:[Mero] Add support for enabling all PCIe links before x86 for Chachani SLT - ABL
+ PLAT_63400 VMR: ABL Release WABLVM05124010
+ PLAT-63444 [VanGogh] ABL Release MABLMV05136010
+ PLAT-63439 [VN] Unsigned ABL can't boot due to FwID mismatch
+ MERO-587:[Mero][CVIP] S-PCIe: CVIP PCIe bridge hotplug enabling
+ PLAT-63218 [GN B0] BIOS: Please include attached S3 Image (S3 Image ID =190194b4) for B0 bring
+ PLAT-61324, [Milan] ABL Support for pre-x86 dTPM
+ Mero-673 [Mero-ABL] Adjust FMR base address
+ MERO-646:Add new SVC call for reporting empty NVMe disk
+ PLAT-63221 [VMR B0] Use attached S3 image (ID=19211ba4) for B0 bring up BIOS
+ Mero-635 [VN-ABL] Merge code from MVG to client master
+project Tools/
+ PLAT-61220: [VanGogh] MEM - Load PMU FW and mapping images
+ Update MR to support signing
+
+--------------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN05116070 for Cezanne
+
+Date: May 11, 2020
+
+--------------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+Path to files:
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN05116070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x05116070
+
+Features and Fixes:
+project APCB/
+ PLAT-62734: [VanGogh] MEM - Add a CBS option to enable/disable RFM
+ PLAT-61862: New CBS option (internal) required in BIOS
+project CCX/
+ PLAT-62347 Failures seen in modules in BTS test
+project DF/
+ PLAT-62347 Failures seen in Modules in BTS Test
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+ PLAT-60848 Milan Disable C2Cxferwidget
+ PLAT-61862: New CBS option (internal) required in BIOS
+ PLAT-62388: [CZN] Update UMA size
+project FCH/
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+project Lib/
+ PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting
+ PLAT-61222: [VanGogh] MEM - UMC Jedec Timings
+ PLAT-63097: [VanGogh] MEM - Add back end code to enable/disable RFM
+ PLAT-62355: [VanGogh] MEM - Add back end code to enable/disable Link ECC
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+ Changes required to boot through ABL.
+ PLAT-62388: [CZN] Update UMA size
+project Memory/
+ Revert "PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting"
+ Mero-635 [Mero-ABL] Merge code from MVG to client master
+ PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting
+ PLAT-60945 [CZN] DDR4 - Enabling Power Savings Optimization
+ PLAT-62397 [CZN AM4] BankGroupSwap overrided by BankGroupSwapAlt
+ PLAT-61222: [VanGogh] MEM - UMC Jedec Timings
+ PLAT-53584: [VanGogh] MEM - Basic UMC/SPD init
+ PLAT-63097: [VanGogh] MEM - Add back end code to enable/disable RFM
+ PLAT-62355: [VanGogh] MEM - Add back end code to enable/disable Link ECC
+ PLAT-63084 [CZN] Boot hang with master ABL
+ VN - Changes required to boot through the ABL
+project NBIO/
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+ PLAT-62412 CZN AM4 BIOS lacks a way to disable ChldxHash
+project Program/
+ PLAT-63324 [CZN] ABL Release WABLCZN05116070
+ Revert "PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting"
+ PLAT-63124 [CZN_FP6]change "Memory power optimized setting" to enable as the default setting
+ MERO-635:[MERO-ABL] Merge code from MVG to client master
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+ Prepare and Release WABLGN05135010 for Milan Weekly BIOS
+ PLAT-63255 [VanGogh] ABL Release MABLMV05086010
+ MERO-635:[MERO-ABL] Seperate Mero ABL specific code from client master
+ PLAT-63184 [CZN] Memory context save restore support
+ PLAT-63065 [CZN] S3 Resume hang on Majolica @ EA00E101
+ PLAT-62412 CZN AM4 BIOS lacks a way to disable ChldxHash
+ VN - Changes to get through the ABL
+
+--------------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN05046070 for Cezanne
+
+Date: May 04, 2020
+
+--------------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+Path to files:
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN05046070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x05046070
+
+Features and Fixes:
+project APCB/
+ PLAT-61526: [Milan] External CBS Option to override Maximum Activity Count (MAC) for memory
+ PLAT-62209: [VanGogh] MEM - Add new APCB Tokens for CBS UMC Options
+ PLAT-61613: New DF BIOS option (internal) required
+ PLAT-62085 [CZN] BIOS Option for UMC Powergating
+ PLAT-61828: Replicate to VN: APCB sync with CBS variable - APCB token update
+ PLAT-51675: Implement MATs memory test for DDR4
+ PLAT-61577 [RN] Add token to control Wifi OTA override
+ PLAT-61454: [Mero][VanGogh][ABL] Merge from SCBU repo to Client Master
+ PLAT-61033: Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings, part 2
+ PLAT-60945 [CZN] DDR4 - Enabling Power Savings Optimization
+project APOB/
+ PLAT-61065: [VanGogh/Mero] Merge code back to ABLmaster - DF
+project CCX/
+ PLAT-62215: [CZN] Update S3 image to CL321652
+ PLAT-49878: Core failures in BTS 15.1.36.0397
+ PLAT-61442: [VanGogh/Mero] Merge code back to AGESA master - CCX
+ PLAT-61368: [BA] update S3 image
+ [BA ABL] merge code from E010 to master
+ PLAT-61075: Automatically reduce the max ASID count available when 8TB of DRAM is detected
+project DF/
+ PLAT-62352: [Mero/VanGogh] PSP region has incorrect RngId
+ PLAT-61613: New DF BIOS option (internal) required
+ PALT-62378: [CZN] Limiting TSME to Ryzen Pro OPNs - ABL
+ PLAT-62308: [CZN] Incorrect Core bit on S0i3 resume
+ PLAT-62308: [CZN] Incorrect Core bit on S0i3 resume
+ PLAT-61911 S0i3: ABL initialization of DF:PIE0->PspSmuId_n0->SmuUnitId
+ PLAT-62080: [CZN] Correct CoherentSlaveModeCtrlA0 Init value
+ PLAT-62079: [CZN] Correct DisPrbMig
+ PLAT-62078:[CZN] Update D18F1x274 (CcdUnitIdMask) bit[4:0]=0x1 to latest PPR
+ PLAT-61713 [CZN] Update DF::PspSmuId_instPIE_n0[SmuUnitId]
+ PLAT-61719 [CZN] Failed to enable SMT through AOD module
+ PLAT-61720 ABL Restore DfCstateClkPwrDnEn to 0 during S0i3 Resume on LPDDR4 config
+ PLAT-61716 [CZN] Workaround for S0i3 resume DRAM access stuck
+ PLAT-61715 When disabling iGPU and using dGPU, sdma0 halt blocks s0i3 entry
+ PLAT-61712 [CZN] F1x300[PhysicalCoreEn] is not restored on S3
+ PLAT-61061: [VanGogh/Mero] Merge code back to AGESA master - DF
+ PLAT-61061: [VanGogh/Mero] Merge code back to AGESA master - DF
+ PLAT-61367: [BA] update MMIO register
+ [BA ABL] merge code from E010 to master
+ PLAT-61075: Automatically reduce the max ASID count available when 8TB of DRAM is detected
+ PLAT-61219 - (RN AM4) when disabling igpu and using dgpu, sdma0 halt blocks s0i3 entry
+project FCH/
+ PLAT-60777 [MVG] AGESA FCH: merge MVG AGESA/ABL change back to trunk
+project Lib/
+ PLAT-61526: [Milan] External CBS Option to override Maximum Activity Count (MAC) for memory
+ PALT-62378: [CZN] Limiting TSME to Ryzen Pro OPNs - ABL
+ PLAT-62215: [CZN] Update S3 image to CL321652
+ PLAT-62124: Add additional option in CBS::ABL BreakPoint (internal) item
+ PLAT-61426 [RN] Remove degrade to 1866 for some selective DIMM
+ PLAT-61587 [RN AM4] Open decode of non-standard IO port for Error Indicator
+ PLAT-51675: Implement MATs memory test for DDR4
+ PLAT-61581: [ABL] [Lib] Build error in common code
+ PLAT-61454: [Mero][VanGogh][ABL] Merge from SCBU repo to Client Master
+ PLAT-61442: [VanGogh/Mero] Merge code back to AGESA master - CCX
+ [BA ABL] merge code from E010 to master
+ PLAT-61075: Automatically reduce the max ASID count available when 8TB of DRAM is detected
+project Memory/
+ PLAT-61526: [Milan] External CBS Option to override Maximum Activity Count (MAC) for memory
+ PLAT-59547: VanGogh Secure Boot Support - ABL
+ PLAT-61335 [Renoir]Memory run to 1600MHz after change memory speed to 3466MHz
+ PLAT-53557 [RN] [AM4] Extend tRcdRd, tRcdWr, and tRP CBS settings
+ PLAT-62086 [CZN] DF data mask setting not in sync with UMC data mask set by memory ABL
+ PLAT-59851 [CZN] Add AGESA MEM Support for LPDDR4 RFM Identifier
+ PLAT-59852 [CZN] Add AGESA MEM Support for LPDDR4x tWR Scaling
+ PLAT-61426 [RN] Remove degrade to 1866 for some selective DIMM
+ PLAT-60569 [CZN] DDR4 PIE Update
+ PLAT-51675: Implement MATs memory test for DDR4
+ PLAT-61521: Improve 2R Nvdimm-N support
+ PLAT-61427 Replicate to Vermeer Milan SP3 MEM - Remove workaround Plat-58035 for B0 IOD(build issue)
+ PLAT-61427 Replicate to Vermeer Milan SP3 MEM - Remove workaround Plat-58035 for B0 IOD.
+ PLAT-60411 [VMR]MBIST fails acrross memory configurations when set test mode as both.
+ PLAT-61454: [Mero][VanGogh][ABL] Merge from SCBU repo to Client Master
+ PLAT-60620 [CZN] Updating termination/drive strength for LP4x DRx8 (Bug Fix)
+ PLAT-61186 [RN]DDR4 Program Optimal Phy PLL Settings update
+ PLAT-61033: Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings, part 2
+ PLAT-61075: Automatically reduce the max ASID count available when 8TB of DRAM is detected
+ PLAT-60620 [CZN] Updating termination/drive strength for LP4x DRx8
+ PLAT-60052 [CZN] Power optimization for lower MPstates for LP4/LP4x
+project NBIO/
+ PLAT-61335 [Renoir]Memory run to 1600MHz after change memory speed to 3466MHz
+ PLAT-61518 White Line Flash/Video Corruption if overclocking with XMP enabled DIMM
+ PLAT-61577 [RN] Add token to control Wifi OTA override
+ PLAT-58611: Remove PCIe Gen3/4 capabilities from PCIe Core2
+ PLAT-61062 - [VanGogh/Mero] Merge code back to AGESA master - NBIO
+ [BA ABL] merge code from E010 to master
+ PLAT-61218 - (RN AM4) when disabling igpu and using dgpu, sdma0 halt blocks s0i3 entry
+ PLAT-61247: Add SOC check to Milan CPU WAFL bridge Device ID
+project Program/
+ Prepare and Release WABLGN06055010 for Milan Weekly BIOS
+ PLAT-59547: VanGogh Secure Boot Support - ABL
+ PLAT-62306 [CZN] Enable build flag of ABL debug print
+ PLAT-62215: [CZN] Update S3 image to CL321652
+ PLAT-62140: [BA] enable sign with BADAMI's own key
+ Prepare and Release WABLGN04295010 for Milan Weekly BIOS
+ PLAT-62013:[CZN] Add Bixby early training support for CZN AM4
+ PLAT-61717: [CZN] Add ABL RT driver for s0i3 support
+ PLAT-61725 VMR: ABL Release WABLVM04204010
+ PLAT-61650 [CZN] Add token to control Wifi OTA override
+ PLAT-61369 VMR: ABL Release WABLVM04134010
+ Prepare and Release WABLGN04225010 for Milan Weekly BIOS
+ PLAT-61577 [RN] Add token to control Wifi OTA override
+ PLAT-59888 [RN] ABL needs to pass TPM config to PSP (Cover Context Restore path)
+ PLAT-61519 - Sync RN/CZN ABL changes to master
+ PLAT-61454: [Mero][VanGogh][ABL] Merge from SCBU repo to Client Master
+ PLAT-59918: Renoir PMFW Release version 55.53.0 (Update PSPSMC definition)
+ PLAT-61368: [BA] update S3 image
+ Prepare and Release WABLGN04155010 for Milan Weekly BIOS
+ PLAT-61118 VMR: ABL Release WABLVM04054010
+ [BA ABL] merge code from E010 to master
+ PLAT-61218 - (RN AM4) when disabling igpu and using dgpu, sdma0 halt blocks s0i3 entry
+project Tools/
+ PLAT-59547: VanGogh Secure Boot Support - ABL
+ PLAT-62140: [BA] enable sign with BADAMI's own key
+ PLAT-61649: [Mero/VanGogh] Build failure - ABL SPClient config missing
+ [BA ABL] merge code from E010 to master
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN04076070 for Cezanne
+
+Date: April 07, 2020
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN04076070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x04076070
+
+Features and Fixes:
+project APCB/
+ PLAT-61033: Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings
+ PLAT-60860 [RN][ABL]Beep Sound cannot Work with All DIMMs Unplugged
+ PLAT-60550: Need Power Down delay configuration under UMC common options
+ PLAT-60716 RN AM4: Boot after VDDIO and Memory OC change fails memory training
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-60518 [RN] Create APCB token to control DPM level trimming
+ PLAT-59888 [RN] ABL needs to pass TPM config to PSP
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Implement filter)
+ PLAT-59623 Update DDR OC available Settings for VMR
+project APOB/
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-56402 [RN] [LPDDR4] S3 Resume does not restore PPT
+project CCX/
+ PLAT-60621: [CZN] Clear SmmBaseLock on S3 Resume
+ PLAT-60621:[VMR] Clear SmmBaseLock on S3 resume
+project DF/
+ PLAT-59486 DF BTS has revealed some mismatches which does not match PPR values
+ PLAT-60957 DF Debug Option-> SPF -> Clean Victim vs Probe interlock Control issue
+ PLAT-49879: DF failures in BTS 15.1.36.0397
+ PLAT-60383 Increase the size in the call to load Phy FW binary
+ PLAT-59992 [GN]API change for DXIO call "pspMp0_dxio_loadPhyFirmware_WAFLAndPCIe"
+ [PLAT-54251]ABL reserved DRAM for RAS Error injection
+project FCH/
+ PLAT-58989 [ComboAM4V2] [Vermeer] System will spend about 1s at post code 0xE092 after warm reset with VMR on Qogir board -- to clear/set SATA_Dis before/after DXIO early training when SATA disabled
+project Lib/
+ PLAT-60906: [RN] Rollback PLAT-54637 xGMI 3-link Configuration Link Distribution Update
+ PLAT-61033: Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings
+ PLAT-60860 [RN][ABL]Beep Sound cannot Work with All DIMMs Unplugged
+ PLAT-60716 RN AM4: Boot after VDDIO and Memory OC change fails memory training
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-60274, When appending tokens, the coreApcbSet routines do not clear existing data prior to writing the token value.
+ PLAT-56402 [RN] [LPDDR4] S3 Resume does not restore PPT
+ PLAT-58989 [ComboAM4V2] [Vermeer] System will spend about 1s at post code 0xE092 after warm reset with VMR on Qogir board -- to clear/set SATA_Dis before/after DXIO early training when SATA disabled
+ PLAT-56539 [Renoir] Limiting TSME to Ryzen Pro OPNs - ABL (Default enable TSME)
+ PLAT-59187 [RN] Reduce resume time when Abl Console out disabled
+ PLAT-59181 [RN] Reduce resume time by updating native APCB v3 interface
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Implement filter)
+ PLAT-60013 [RN][Renoir]Memory Safe Mode support on Artic
+project Memory/
+ PLAT-54558: NVDIMM fail S5 shutdown push to persistence test, part 2
+ PLAT-61033: Add AGESA MEM Option for SubUrgRefLowerBound, UrgRefLimit Platform Settings
+ PLAT-61035: Milan SP3 MEM - Remove workaround Plat-58035 for B0 IOD
+ PLAT-59935 [VMR]C- of P0 got low margin with D die 3200 @ VDDIO derate to 1.14v.
+ PLAT-60550: Need Power Down delay configuration under UMC common options
+ PLAT-56172 [RN][LP4] Enable ppt by default in BIOS
+ PLAT-52232 [VMR] Enable Memory Context Save and Restore Function(Add 3-step MR6)
+ PLAT-60810, [Milan] SCMTool.efi LIST not shows "PERSISTENT RAM" with 128GB RDIMM x12 + 32GB NVDIMM x4
+ PLAT-56402 [RN] [LPDDR4] S3 Resume does not restore PPT
+ PLAT-56247 [RN] [LPDDR4] MR12 Input converting Range1
+ PLAT-56330 [RN][LP4] Add SMU call for starting timer based periodic re-training in the restore path
+ PLAT-56041 [RN][LPDDR4] Set Seed Vref CA (MR12) for LP4 (Not LP4x)
+ PLAT-56313 [RN][LP4] Revise RN LPDDR4 Mop sequence for Mission mode and Context-restore
+ PLAT-55881 [RN] Celadon Write margin issue - MR6 read value is 0 in srsm index 0x1E
+ PLAT-51727: [RN] [LPDDR4] MBIST Data Eye Test
+ PLAT-55917 [RN] [LP4] Disable Valid_D1 bit in MOP Array for MR12/MR14 after StartupPState
+ PLAT-56318 [RN][LP4] Software DRAM reset sequence for Context-restore
+ PLAT-56402 [RN] [LPDDR4] S3 Resume does not restore PPT
+ PLAT-55995: [RN][LPDDR4] PPT Workaround incorrectly applied
+ PLAT-60479: MBIST RX dataeyes broken on 0071 BIOS
+ PLAT-58835: [Milan] NVDIMM_N failed training in Windows OS
+ PLAT-56539 [Renoir] Limiting TSME to Ryzen Pro OPNs - ABL (Default enable TSME)
+ PLAT-48575 [RN DDR4] Update SRSM Tzqoper/Tzoper per Latest Recommendation for DLL Reset on MPxExit
+ PLAT-54508 [RN AM4]Phy power saving settings are not programed correctly
+ PLAT-56693 [RN] [LPDDR4/4x] SRx16 fail S3 resume/Context Restore with ppt
+ PLAT-58888 [RN] Per P-State Uclk DivMode to apply CWL set
+ PLAT-59623 Update DDR OC available Settings for VMR
+ PLAT-60573, [Milan] System hangs or gets into a continuous reboot loop when setting to NPS0
+ PLAT-57471: NVDIMM fail S5 shutdown push to persistence test
+ PLAT-57768 RegClkGateEn bit should be set in UmcCtrlMiscCfg
+ PLAT-59557: LRDIMM/LRDIMM3DS fail the RRW test when RCD parity disabled
+ [PLAT-54251]ABL reserved DRAM for RASError Injection
+ PLAT-59620 Update RxDatChnDly programming for VMR (same as was done on MTS/MTS2)
+project NBIO/
+ PLAT-59859: Milan CPU WAFL bridge Device ID is different with PPR PCI Device ID Assignments
+ PLAT-60971: [RMB] SMU FW 69.0.3 release
+ PLAT-60518 [RN] Create APCB token to control DPM level trimming
+ PLAT-59181 [RN] Reduce resume time by updating native APCB v3 interface
+project Program/
+ PLAT-61105: Milan][GN] Prepare and Release RABLGN00725010 for MilanPI_SP3_0072
+ PLAT-60716 RN AM4: Boot after VDDIO and Memory OC change fails memory training
+ PLAT-60971: [RMB] SMU FW 69.0.3 release
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-60862 VMR: ABL Release WABLVM03304010
+ PLAT-60866 Renoir 1003RC4 bad word - ABL
+ Prepare and Release WABLGN04015010 for Milan Weekly BIOS
+ PLAT-58649: [RN][ComboAM4v2][Qogir]: System hang at PC:0300 when resume from S3.
+ PLAT-58487: [RN AM4][Qogir] System stunk at PC 0x7 or A930 when warm reset
+ PLAT-58989 [ComboAM4V2] [Vermeer] System will spend about 1s at post code 0xE092 after warm reset with VMR on Qogir board -- to clear/set SATA_Dis before/after DXIO early training when SATA disabled
+ PLAT-59181 [RN] Reduce resume time by updating native APCB v3 interface
+ PLAT-59888 [RN] ABL needs to pass TPM config to PSP
+ [CZN] Reduce resume time by updating native APCB v3 interface
+ PLAT-59186 [RN] Terminate loop invalid replay buffer to reduce resume time
+ PLAT-59186 [CZN] Terminate loop invalid replay buffer to reduce resume time
+ PLAT-60583 VMR: ABL Release WABLVM03234010
+ Prepare and Release WABLGN03255010 for Weekly BIOS
+ PLAT-60459 [CZN] Assert on S3 Resume path
+ [PLAT-54251]ABL reserved DRAM for RAS Error Injection
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN03166070 for Cezanne
+
+Date: March 16, 2020
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN03166070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x03166070
+
+Features and Fixes:
+project APCB/
+ PLAT-57713: [RMB] Add existing NBIO Support
+ PLAT-59098: [Milan] Missing some checks for early training of two links
+project CCX/
+ PLAT-59538 Workarounds lost in SMT Disabled config
+project DF/
+ PLAT-60001, [Milan] Enhance the mechanism for bad DIMM handling
+ PLAT-59829 [CZN] Remove GcmEnable from s0i3 resume path
+ PLAT-59627 Change SPF replacement policy to LRT for better performance
+ PLAT-59295 EnExtSpfARC needs conditional initialization for workaround in GN B0
+project Lib/
+ PLAT-57713: [RMB] Add existing NBIO Support
+project Memory/
+ PLAT-59988: Milan - 3DS LRDIMM mix(slot0-2S2R, slot1-2S4R & visa-versa) hangs at post code 001F
+ PLAT-60268, Milan Ethanol-X hangs at post code E316 with internal bios
+ PLAT-49459 [Milan] Limiting the number of memory controllers in 2P mode hangs simnow in ABL (separate workaround)
+ PLAT-54263: Milan placeholder to track SSP plat-47624
+ PLAT-60001, [Milan] Enhance the mechanism for bad DIMM handling
+ PLAT-59635, [GN] Error logs along with APCB_TOKEN_UID_FCH_CONSOLE_OUT_BASIC_ENABLE = 1
+project NBIO/
+ PLAT-57713: [RMB] Add existing NBIO Support
+ PLAT-57713: [RMB] Add existing NBIO Support
+ PLAT-59098: [Milan] Missing some checks for early training of two links
+project Program/
+ PLAT-59994 [VMR] WABLVM03134010 release
+ PLAT-49459 [Milan] Limiting the number of memory controllers in 2P mode hangs simnow in ABL (separate workaround)
+ Prepare and Release WABLGN03185010 for Milan Weekly BIOS
+ PLAT-57713: [RMB] Add existing NBIO Support
+ PLAT-57713: [RMB] Add existing NBIO Support
+ Prepare and Release WABLGN03115010 for Milan Weekly BIOS
+ PLAT-59624 [CZN] Remove ABL6 from s0i3 resume flow
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: WABLCZN03056070 for Cezanne
+
+Date: March 05, 2020
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ TypeId0x30_AgesaBootloaderU_CZN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/WABLCZN03056070.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x03056070
+
+Features and Fixes:
+
+project APCB/
+ PLAT-59301: [GN] Add interface to disable NVDIMM feature for memory margin test
+ PLAT-59203 Hot Temperature causes memory issues for 128GB and 256GB LRDIMM, lower the DIMM sensor upper temp for 3DS memory.
+ PLAT-58600 [CZN] Add customizable ABL breakpoints
+project CCX/
+ PLAT-59401 [CZN] Update S3 image to CL312339
+ PLAT-56220:[ComboAM4v2][VMR_Qogir]: MSR 0xC001_0015 bit 25 is set to 0 (correct should be 1) after Core Performance Boost disabled in BIOS setup
+ PLAT-58816: [Milan] Workarounds lost in SMT Disabled config
+ PLAT-55218: [RMB] Port Vermeer Zen3 Cerberus support to RMB
+project DF/
+ PLAT-58449 NPS1/Auto not honored when down CCD to 2CCD
+ PLAT-55219: [RMB] Port Cezanne DF support to RMB
+project Lib/
+ PLAT-59401 [CZN] Update S3 image to CL312339
+ PLAT-59301: [GN] Add interface to disable NVDIMM feature for memory margin test
+ PLAT-59203 Hot Temperature causes memory issues for 128GB and 256GB LRDIMM.
+ PLAT-59108 [Renoir_AM4] Serial out can't output when connected with SIO
+ Revert "PLAT-58600 [CZN] Add customizable ABL breakpoints"
+ PLAT-58600 [CZN] Add customizable ABL breakpoints
+ PLAT-58854: [CZN] Unified BIOS - C2PMSG_98 [11] EnableIoRedirect support
+project Memory/
+ PLAT-58175 [RN] [LPDDR4/X] Power Savings Update for Lower MPStates
+ PLAT-59445, [GN] System hung postcode AC90 with bad Dimm populated
+ PLAT-59301: [GN] Add interface to disable NVDIMM feature for memory margin test
+ PLAT-59297: [GN] Output more NVDIMM status register contents to console log for debugging
+ PLAT-59203 Hot Temperature causes memory issues for 128GB and 256GB LRDIMM, lower the DIMM sensor upper temp for 3DS memory.
+ PLAT-59147 Reduplicate to RNAM4: [MTS] Remove error level of CAS Latency
+ PLAT-52892: Early page activate is not getting disabled at BIOS
+ PLAT-58403: Daytonax shows different channel locations when bad dimm is inserted in channel-D
+ PLAT-58114: [Ryzen Master] [RN] Applied RttPark values are not reflecting after restart
+project Program/
+ PLAT-59401 [CZN] Update S3 image to CL312339
+ PLAT-56220:[ComboAM4v2][VMR_Qogir]: MSR 0xC001_0015 bit 25 is set to 0 (correct should be 1) after Core Performance Boost disabled in BIOS
+ setup Prepare and Release WABLGN03045010 for Milan Weekly BIOS
+ PLAT-59095: [RMB] Update ABL SRAM Layout to match Vangogh
+ Revert "PLAT-58600 [CZN] Add customizable ABL breakpoints"
+ Prepare and Release WABLGN02265010 for Milan Weekly BIOS
+ PLAT-58600 [CZN] Add customizable ABL breakpoints
+ PLAT-58963: [Milan][GN] Prepare and Release RABLGN00715010 for MilanPI_SP3_0071
+ Prepare and Release WABLGN02195010 for Milan Weekly BIOS
+ PLAT-57363: [Milan] Release ABL FW in encrypted form
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: RABLCZN02146010 for Cezanne
+
+Date: Feb 14, 2020
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ TypeIdx30_AgesaBootloader_U_CN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/RABLCZN02146010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x02146010
+
+Features and Fixes:
+
+APCB/
+ PLAT-57617: Allow customers to relocate the ROM3 base address via an APCB token
+ PLAT-46844: Milan - MEM - Enablement for DDR4 UDIMM/RDIMM CTLE with Pstates enabled
+ PLAT-57908: CBS Option and APCB token requested for X3D Disable
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-48155 [SSP] Pre-dram early video hangs when accessing legacy video I/O
+ PLAT-47592 Add new APCB token to control Display Splash Screen
+
+APOB/
+ PLAT-49888 Need a BIOS which supports loading APCB based on SubProgram
+ PLAT-56222 [RN] Unified Phy Save List
+
+CCX/
+ PLAT-58109 S3 Image for DistributedTriggering_v4 and IC_HWAMASK
+ PLAT-58108: [RMB] Rembrandt ABL initial support
+ PLAT-58110 [GN] BIOS: S3 Image for DistributedTriggering_v4 and IC_HWAMASK + S3 Image ID
+ PLAT-57246 S3 Image for IC_HWAMASK and older fixes
+ PLAT-57172 [CZN] Add S3 image for pre LSF
+ PLAT-57247: [GN] BIOS: S3 Image for IC_HWAMASK[2:1] = 0x3 + older fixes
+ PLAT-56031:[VMR] Enable Memory Context Save and Restore Function - CPU
+ PLAT-56569: [VMR] BIOS: S3 Image with Fix for EX SCHQ MCA (updated Int Sched Token fix) + FPPRF
+ PLAT-56567 [GN] BIOS: S3 Image with Fix for EX SCHQ MCA (updated Int Sched Token fix) + FPPRF
+ PLAT-49888 Need a BIOS which supports loading APCB based on SubProgram
+ PLAT-56190 [VMR] S3 Image with fix for int scheduler + FPPRF + DE_DBGCFG0 bits 28/30 cleared
+ PLAT-56191 [GN] BIOS: S3 Image with Fix for Int Scheduler + FPPRF + DE_DBGCFG0 bits 28/30 cleared
+
+DF/
+ PLAT-58699: [CZN] replication [RN] DRTM abnormal during context restore mode
+ PLAT-57108 change DF CAKE component map register value
+ PLAT-58108: [RMB] Rembrandt ABL initial support
+ PLAT-57427: [Replicated][GN][ABLv2] Assertion when xGMI 3-Link is selected
+ PLAT-56632 Replicate to [Milan] FuseDisable_CAKE must be set for XGMI 3-link config
+ PLAT-56904: [RN] CBS option 'Disable DF to external downstream IP SyncFloodPropagation' doesn't work
+ Revert "PLAT-52985: [RN-FP6] Get wrong Carve Out size with iGPU Configuration selcet UMA_AUTO and UMA Version select Auto, and Display Resulotion selcet 1920x 1080 and below"
+
+FCH/
+
+Lib/
+ PLAT-54351 [CZN] ABL memory update changes from RN
+ PLAT-46844: Milan - MEM - Enablement for DDR4 UDIMM/RDIMM CTLE with Pstates enabled
+ PLAT-58108: [RMB] Rembrandt ABL initial support
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-53804 Vermeer: Updated BIOS / SMU DDR Overclocking Range to DDR8000 (4000MHz)
+ PLAT-57401 [ComboAM4v2][VMR] System can't boot up and hang @PC: 0xEE00000d
+ PLAT-57172 [CZN] Add S3 image for pre LSF
+ PLAT-56031:[VMR] Enable Memory Context Save and Restore Function - CPU
+ PLAT-56480 [RN_AM4] DDR4 Overclocking Range to DDR8000 (4000MHz) (Fix E0d0 issue)
+ PLAT-49888 Need a BIOS which supports loading APCB based on SubProgram
+ PLAT-56222 [RN] Unified Phy Save List
+
+Memory/
+ PLAT-56168: RegClkGateEn bit should be set in MiscCfg and UmcCtrlMiscCfg
+ PLAT-54263: Genesis placeholder to track SSP plat-47624
+ PLAT-56477: SUT waiting at POST code E325 for more than 24 hours when MBIST mode is Data Eye
+ PLAT-46844: Milan - MEM - Enablement for DDR4 UDIMM/RDIMM CTLE with Pstates enabled
+ PLAT-39994, [Milan] MBIST - Static and Target Static Lanes Select Control Setup not working as expected
+ PLAT-56261: [GN] Implement Thermometer Rounding Error Workaround for DDR PHY
+ PLAT-58035: Milan PI - Revert PLAT-52852 to re-enable Rome workaround on Milan A0
+ PLAT-58081: Update PMU 1D and 2D message block settings
+ PLAT-57980: [GN] ABL remove some commented out code, no functional change
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ Revert "PLAT-50885 [RN] [DDR4] Optimize DDR4 drive strength & ODT settings (Update DRAM Drv, DFE and FFE default policy)"
+ PLAT-57401 [ComboAM4v2][VMR] System can't boot up and hang @PC: 0xEE00000d
+ PLAT-49459: [Milan] Limiting the number of memory controllers in 2P mode hangs simnow in ABL
+ PLAT-57137 [VMR/Qogir] System will hang at PC 0x00B0 on Qogir when only build VMR BIOS not Combo MTS and VMR
+ PLAT-52232 [VMR] Enable Memory Context Save and Restore Function (S3 issue)
+ PLAT-49888 Need a BIOS which supports loading APCB based on SubProgram
+ PLAT-54946 [VMR]Tristate C[2:0] setting for power saving is not correct.
+ PLAT-56222 [RN] Unified Phy Save List
+
+NBIO/
+ PLAT-57908: CBS Option and APCB token requested for X3D Disable
+ PLAT-57979: [GN] ABL does not pass CBS internal item 'DF PState FClk Limit' settings to SMU
+ PLAT-55308 [Milan] Early VGA fail when ASPEED demo card insert in Slot2/Slot3/Slot4
+ PLAT-48241 Early video feature request for Pilot4
+ PLAT-48155 [SSP] Pre-dram early video hangs when accessing legacy video I/O
+ PLAT-47592 Add new APCB token to control Display Splash Screen
+
+Program/
+ PLAT-57617: Allow customers to relocate the ROM3 base address via an APCB token
+ PLAT-54351 [CZN] ABL memory update changes from RN
+ PLAT-58694 [CZN] Apply VBL data config routine during Memory Context Save/Restore feature enable.
+ PLAT-58690 [CZN] Remove redundant ABL
+ PLAT-58672 [CZN] Rename ABL binary
+ PLAT-58574 VMR: ABL Release WABLVM02094010
+ Prepare and Release WABLGN02125010 for Milan Weekly BIOS
+ PLAT-57908: CBS Option and APCB token requested for X3D Disable
+ PLAT-55463 Invoke ABL binaries/indicate resume for s0i3
+ Prepare and Release WABLGN02055010 for Milan Weekly BIOS
+ PLAT-58108: [RMB] Rembrandt ABL initial support
+ Prepare and Release WABLGN01295010 for Milan Weekly BIOS
+ PLAT-57980: [GN] ABL remove some commented out code, no functional change
+ PLAT-41658, Respond to SoC BIST failures by downcoring and continuing to boot
+ PLAT-57802 VMR: ABL Release WABLVM01194010
+ PLAT-57863: [Milan][GN] Prepare and Release RABLGN00705010 for MilanPI_SP3_0070
+ Prepare and Release WABLGN01225010 for Milan Weekly BIOS
+ PLAT-57172 [CZN] Add S3 image for pre LSF
+ PLAT-57433 VMR: ABL Release WABLVM01134010
+ PLAT-57426 [VMR] ABL need to retrain when mem save/restore boot fail
+ PLAT-57137 [VMR/Qogir] System will hang at PC 0x00B0 on Qogir when only build VMR BIOS not Combo MTS and VMR
+ Prepare and Release WABLGN01155010 for Milan Weekly BIOS
+ PLAT-56618 [CZN] Update ABL to compressed binary
+ PLAT-57075 VMR: ABL Release WABLVM01064010
+ PLAT-56031:[VMR] Enable Memory Context Save and Restore Function - CPU
+ PLAT-56707 [RN] ABL need to retrain when mem save/restore boot fail
+ PLAT-56719 VMR: ABL Release WABLVM9C234010
+ Prepare and Release WABLGN9C255010 for Milan Weekly BIOS
+ PLAT-56372 VMR: ABL Release WABLVM9C164010
+ PLAT-49888 Need a BIOS which supports loading APCB based on SubProgram
+ Prepare and Release WABLGN9C185010 ABL for Milan Weekly BIOS
+ PLAT-56222 [RN] Unified Phy Save List
+
+Tools/
+ PLAT-58672 [CZN] Rename ABL binary
+ PLAT-58108: [RMB] Rembrandt ABL initial support
+ PLAT-56659 [CZN] Compressed ABL binary fails to load by PSP BL
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: RABLCZN9C0A6010 for Cezanne
+
+Date: Dec 10, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ TypeIdx30_AgesaBootloader_U_CN.csbin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/RABLCZN9C0A6010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x9C0A6010
+
+Features and Fixes:
+
+APCB/
+ PLAT-46188 Add APCB token to control PCIe GEN2 De-emphasis in ABL for Early Trained BMC link via WAFL
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 2)
+ PLAT-55075: [RN]LPDDR4] Add function to send SMU Message to Enable Timer-based Periodic Retraining
+ PLAT-51770: [Milan] Memory MBIST Feature Enabling
+ PLAT-50610 Need a BIOS PCD option that exposes CCMConfig:ForceRdBlkLToC to address customer performance observation
+ PLAT-54490 [RN] Cache Mapped SMN address to speed up ABL post
+
+APOB/
+ PLAT-54000: [RN] [LP4] DQSPreambleControl.LP4SttcPreBridgeRxEn setting is not matching to MR1 OP[3]
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+
+CCX/
+ PLAT-50648: [RN_FP6]System auto restart when boot to Ubuntu with mem_encrypt=on in kernel command line
+ PLAT-55441: [RN][ComboAM4v2][Artic]: MSR 0xC001_0015 bit 25 is set to 0 (should be 1) for core1/2/3 after disable CPB in BIOS setup.
+ PLAT-55190 [GN] BIOS: S3 image update for BIOS --> FPPRF and Integer Sch token (V2 IPC improvement)
+ PLAT-54353: [VMR] Clear SmmLock at the beginning of S3 resume
+ PLAT-55192 [VMR] BIOS: S3 image update for BIOS --> FPPRF and Integer Sch token (V2 IPC improvement)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (Fix build issue)
+ PLAT-54639: [VMR] BIOS: S3 image update for BIOS --> FPPRF and Integer Sch token
+ PLAT-54383: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (DF)
+ PLAT-54005 [CZN] E030/LSD stuck at x86 release
+ PLAT-53936 [GN] BIOS: S3 image update for BIOS
+ PLAT-53938: [VMR] BIOS: S3 image update for BIOS
+ PLAT-53938: [VMR] BIOS: S3 image update for BIOS
+ PLAT-44566: BIOS: Provide BIOS setup option to Enable/Disable -VMGuard3
+
+DF/
+ PLAT-52985: [RN-FP6] Get wrong Carve Out size with iGPU Configuration selcet UMA_AUTO and UMA Version select Auto, and Display Resulotion selcet 1920x 1080 and below
+ PLAT-55161: Replicate to Vermeer RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (DF)
+ PLAT-55160: Replicate to Cezanne RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (DF)
+ PLAT-55563: [RN] DRTM abnormal during context restore mode
+ PLAT-54637 xGMI 3-link Configuration Link Distribution Update
+ PLAT-50610 Need a BIOS PCD option that exposes CCMConfig:ForceRdBlkLToC to address customer performance observation
+ PLAT-54325 Badami initial support
+ PLAT-52606 System unable to re-enter s0i3 after autowake
+ PLAT-54383: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (DF)
+ PLAT-54489 [VMR] DXIO v46.597: GMI2 OTP Update
+ PLAT-54038 [CZN] Disable Loadstep and Loadrelease in DF
+ PLAT-53901: [RN] Disable Loadstep and Loadrelease in DF
+ PLAT-54013 [RN] Turn off Memory Clear by default
+ PLAT-53060: DF register system value do not match PPR value
+
+FCH/
+
+Lib/
+ PLAT-54765 [CZN] Unified BIOS - No ABL debug log when environment flag is set to 0
+ PLAT-52232 [VMR] Enable Memory Context Save and Restore Function
+ PLAT-55770: [Milan PI 0.0.6.1. RC1] Milan Daytona-X platform hangs at post code E2C5 or E0BB
+ PLAT-55188 - [BA] Initial creation of NBIO code for Badami
+ PLAT-55190 [GN] BIOS: S3 image update for BIOS --> FPPRF and Integer Sch token (V2 IPC improvement)
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 2)
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 1)
+ PLAT-54826: Replicate to Vermeer Choose unsupported 'Memory Clock Speed' BIOS setup item will hang at POST 0xD4.
+ PLAT-54637 xGMI 3-link Configuration Link Distribution Update
+ PLAT-55273 :[RN] Apply VBL data config routine during Memory Context Save/Restore feature enable.
+ PLAT-54000: [RN] [LP4] DQSPreambleControl.LP4SttcPreBridgeRxEn setting is not matching to MR1 OP[3]
+ SWDEV-209716: Catch the APCB corruption in ABL and return error code BL_ERR_DATA_CORRUPTION (0x10) to PSP
+ PLAT-51770: [Milan] Memory MBIST Feature Enabling
+ PLAT-53036, Dmidecode unable to read smbios type 17-Memory Device information for populated DIMM Channels for Socket 1
+ PLAT-54325 Badami initial support
+ PLAT-54876 [RN]ABL and APOB won't return correct Module Manufacturing Location and date
+ PLAT-53340 Trace to dram address maps are not getting setup for CS (GN)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (Fix build issue)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+ PLAT-50869: LRDIMM gets ECC errors after clock stop exit
+ PLAT-54608: [RN] Correct ABL1 post code
+ PLAT-54490 [RN] Cache Mapped SMN address to speed up ABL post (temporarily disable SMN cache)
+ PLAT-54490 [RN] Cache Mapped SMN address to speed up ABL post
+ PLAT-46410: Unsupported config error incorrectly given for a supported ChA RDIMM/Ch B LRDIMM config
+ PLAT-50759: [RN] LPDDR4 - Enabling DDR PHY Lane
+
+Memory/
+ PLAT-55148: [RN] [LPDDR4] Update PIE initialization for x8 devices for PPT
+ PLAT-52232 [VMR] Enable Memory Context Save and Restore Function
+ PLAT-55194: [GN] Channel Disable - Remove extra write to UMC::Phy::SequencerOverride
+ PLAT-55389 [RN] Updating PMU fw for LPDDR4 (Revert WA:PLAT-52510)
+ PLAT-55212 [RN][LP4] Change Drive strength for DDR1600 to save memory power
+ PLAT-50885 [RN] [DDR4] Optimize DDR4 drive strength & ODT settings (Update DRAM Drv, DFE and FFE default policy)
+ PLAT-54010 [RN DDR4] GlobalVrefInSel mess up after training when PHY vref seed <0x52
+ PLAT-54137: [VMR]Margining failed on nominal voltage when VDDIO decrease to 1.14v with DR 3200 1DPC.
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 2)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (Fix S3 issue)
+ PLAT-55164 [RN][LP4] Update MR22 settings for LP4 DR, LP4 definitions are inverted for CS and CLK ODT as compared to LP4x (patch 1)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+ PLAT-55164 [RN][LP4] Update MR22 settings for LP4 DR, LP4 definitions are inverted for CS and CLK ODT as compared to LP4x
+ PLAT-55075: [RN]LPDDR4] Add function to send SMU Message to Enable Timer-based Periodic Retraining
+ PLAT-54495: [RN] [LPDDR4] ABL workaround for per mempstate ppt support
+ PLAT-53842: RN - MEM - LPDDR4 Mop array changes to support S3/Context-Restore with new PPT Mop format, Memeye and Mbist.
+ PLAT-55077: [RN][LPDDR4] Remove Software DFI Init Sequence, Issue PSPSMC_MSG_SwitchToStartupDfPstate to last trained PState
+ Revert "PLAT-51421: Update PIE to skip PPT correctly on DFI_FREQ = 0x1[3:0]"
+ PLAT-55076: [RN][LPDDR4] ABL Should not disable Hclk
+ PLAT-55078: [RN][LPDDR4] Disable LPDDR Frequency Set Point Optimization for PPT
+ PLAT-55091: [RN][LPDDR4] AcsmPlayback registers must be programmed per-pstate
+ PLAT-55093: [RN][LPDDR4] DRAM Phy bitfield RdDbiEnabled must be consistent with UMC/MRS Setting
+ PLAT-54000: [RN] [LP4] DQSPreambleControl.LP4SttcPreBridgeRxEn setting is not matching to MR1 OP[3]
+ PLAT-55036 [RN][LP4x] DRx16 and SRx16 VrefCA Seed Value Changes (MR12)
+ PLAT-51770: [Milan] Memory MBIST Feature Enabling
+ PLAT-53036, Dmidecode unable to read smbios type 17-Memory Device information for populated DIMM Channels for Socket 1
+ PLAT-52103: ABL_MEM_ERROR_LRDIMM_MIXMFG should be an ALERT not an ERROR
+ PLAT-48723: [SSP] NVDIMM-N failed training after warm reset (CF9_06), part 3
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (Fix build issue)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+ PLAT-50869: LRDIMM gets ECC errors after clock stop exit
+ PLAT-54651: [GN] Should not override return value from SMU PSPSMC_MSG_GetStartupDfPstate
+ PLAT-46839: SP3 3DS RDIMM mix (slot0=2S2R slot1=2S4R) 2 of 2 failed to boot
+ PLAT-54490 [RN] Cache Mapped SMN address to speed up ABL post
+ PLAT-53652: [GN] Dram addressing: BankBit incorrect for LRDIMM 4DR when disable all feature in DRAM memory Mapping
+ PLAT-53965 [RN] UMC uses indexed address mode
+ PLAT-53558 [RN] [LPDDR4] Global DAC MP1-2 + Min function
+ PLAT-46410: Unsupported config error incorrectly given for a supported ChA RDIMM/Ch B LRDIMM config
+ PLAT-51825: [RN DDR4] MBIST fails across memory configurations
+ PLAT-50759: [RN] LPDDR4 - Enabling DDR PHY Lane
+ PLAT-51595 [RN] [LPDDR4] Convert User Input MR12/14
+
+NBIO/
+ PLAT-46188 Add APCB token to control PCIe GEN2 De-emphasis in ABL for Early Trained BMC link via WAFL
+ PLAT-55188 - [BA] Initial creation of NBIO code for Badami
+ PLAT-53898: [RN] Customized TX_VBOOST_LVL and TX_TERM_CTRL setting for combo phy in SMU (Update SMU ID)
+ PLAT-55075: [RN]LPDDR4] Add function to send SMU Message to Enable Timer-based Periodic Retraining
+ PLAT-53898: [RN] Customized TX_VBOOST_LVL and TX_TERM_CTRL setting for combo phy in SMU
+ PLAT-54672:[VRM] Need to seperate BIOS option for VDDG into VDDG IOD and VDDG CCD
+ PLAT-54204: Move Bixby training after memory initialization in ABL
+
+Program/
+ PLAT-52232 [VMR] Enable Memory Context Save and Restore Function
+ PLAT-55188 - [BA] Initial creation of NBIO code for Badami
+ PLAT-55190 [GN] BIOS: S3 image update for BIOS --> FPPRF and Integer Sch token (V2 IPC improvement)
+ PLAT-55563: [RN] DRTM abnormal during context restore mode
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 2)
+ PLAT-55478 [RN] Provide error indicator opcode table for customization (Part 1)
+ PLAT-55211: PMFW Release version 55.34.0 (Update CZN PSP Message header)
+ PLAT-55273 [RN] Apply VBL data config routine during Memory Context Save/Restore feature enable. (WA size issue on LPDDR4 image)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+ PLAT-55273 :[RN] Apply VBL data config routine during Memory Context Save/Restore feature enable.
+ PLAT-55211: Renoir PMFW Release version 55.34.0 (Update PSP Message header)
+ PLAT-53842: RN - MEM - LPDDR4 Mop array changes to support S3/Context-Restore with new PPT Mop format, Memeye and Mbist.
+ PLAT-54672:[VRM] Need to seperate BIOS option for VDDG into VDDG IOD and VDDG CCD
+ PLAT-54672:[VRM] Need to seperate BIOS option for VDDG into VDDG IOD and VDDG CCD
+ PLAT-54325 Badami initial support
+ PLAT-54546 [CZN] Update ABL for new naming rule
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4 (Fix build issue)
+ PLAT-46419: RN - Memory Context Save/Restore support in LPDDR4/ DDR4
+ PLAT-54608: [RN] Correct ABL1 post code
+ PLAT-54490 [RN] Cache Mapped SMN address to speed up ABL post
+ PLAT-54204: Move Bixby training after memory initialization in ABL
+
+Tools/
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN9A286010 for Cezanne
+
+Date: Oct 28, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN9A286010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x9A286010
+
+Features and Fixes:
+ PLAT-53386: [CZN] update S3 image to CL299145
+ PLAT-52326 L3 config bits set incorrectly in GN A0 silicon
+ PLAT-53711: [GN] Integrate DXIO FW version 45.632 into ABL
+ PLAT-53471 [CZN] Incorrect cores per CCX
+ PLAT-53776 [RN] Reduce smn remapping
+ PLAT-48594 [RN] PMU FW loading timesink
+ PLAT-53408 [RN] ABL serial out function fail on FCH UART0 after PI0081
+ PLAT-53146: [RNAM4] Mapping of Channel and UMC is incorrect
+ PLAT-53778 [RN] Reduce polling interval to 1ms for UMC registers
+ PLAT-53777 [RN] Optimize PMU FW loading process
+ PLAT-53365 [RN] LPDDR4 Performance Optimization
+ PLAT-52669: [RN] LPDDR4 - Update on PerBankRefEn in CBS
+ PLAT-52824: [VMR] APCB code should not include internal files
+ PLAT-53437: Milan SP3 MEM - Remove unnecessary Manual DFI_Init_start after Dram Training
+ PLAT-53147 [RN] [LP4] Set bit time =4 in 2D Msg Blk control for PMU training
+ PLAT-53138 [RN][LPDDR4X][DRx8] Please increase the speed limit to 3733MT/s from 2666MT/s (issue fix)
+ PLAT-52938: [VMR]VDDP voltage cannot adjust by AOD.
+ PLAT-53637 [CZN] Fix S0i3 resume path in ABL
+ PLAT-51732 [CZN] Unified BIOS - APCB support
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN9A166010 for Cezanne
+
+Date: Oct 16, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN9A166010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x9A166010
+
+Features and Fixes:
+
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN99186010 for Cezanne
+
+Date: Sep 18, 2019
+
+ PLAT-50393: [GN] Internal CBS option to stop after training failure (instead of disable the channel)
+ PLAT-52478: [RN] Update Static info table to support DP_dphy_tx_term_ctrl
+ PLAT-51967, [GN] Add an APCB token to enable/disable clock outputs by default
+ PLAT-52218: Add a new option to print ABL log only on normal boot or S3/S0i3 resume path
+ PLAT-52146: [RN] Update Static info table to support DP_dphy_tx_vboost_lvl
+ PLAT-49663 GN BIOS: SEV specific CBS option changes for Internal/Debug purpose
+ PLAT-51769: [Milan] Enable Post Package Repair Feature
+ PLAT-52506: [RN][LP4] ABL not setting PeriodicRetrainEn based on the setup option
+ PLAT-44754 BIOS: Provide BIOS setup option to Enable/Disable - PPIN
+ PLAT-52050: [VMR B0] add S3 image and CPUID for VMR B0
+ PLAT-51853: CPUID Not Reporting SNP Capability
+ PLAT-51207 Write Data Compression should be turned on in the Milan BIOS post bringup
+ PLAT-51200 Set SOCID in initpkg7 and DE_CTL appropriately
+ PLAT-51201 Init ChXiVmgCfg0 VmgMode
+ PLAT-52951: [RN] No UMA memory is allocated when UMA sets to specified mode and UMA size is 4GB
+ PLAT-52325 [GN] Please integrate DXIO FW version 45.630 into ABL
+ PLAT-52251: DsNpReqLimit should be 0 in GN
+ PLAT-52259 [GN] Integrate DXIO FW version 45.629
+ PLAT-51928: PIE register config changes for AVIC perf bug
+ PLAT-51846: DF register mismatch between PPR and system values
+ PLAT-51256 :[RN] DF registers init value fail
+ PLAT-51802: GN: BIOS fix needed for RMPUPDATE x86 instruction
+ PLAT-51732 [CZN] Unified BIOS - APCB support
+ PLAT-48723: [SSP] NVDIMM-N failed training after warm reset (CF9_06)
+ PLAT-47922 [RN][LP4] Training Retries in BIOS to be updated for LPDDR4
+ PLAT-52290: [GN][Milan] Enable ABL Console log over SOL for CRBs
+ PLAT-50461 [Renoir_FP6_MP2] HP9DS1+HP2DC sensor does not work after cold boot
+ PLAT-51224: [RN][LP4] PHY Registers list for save/restore in LP4 mode
+ PLAT-51873: [VMR B0] Use C2P_MSG_97 & 98 as Env Flag
+ PLAT-51885 [RN][LP4] Locate max freq table failure with LPDDR4
+ PLAT-39433: Memory RAS CBS setting change
+ PLAT-53005 [RN] S3 resume failure with DR+DR and DR+SR
+ PLAT-51106 [RN] LPDDR4 Enable HW Thermal Throttling for 50% ThrottlePct (Fix ThermMrrCtrl)
+ PLAT-52953 [RN] [LPDDR4] Thermal Throttling Below Threshold
+ PLAT-52510 [RN][LPDDR4] Implement workaround for DFE issue in PMU FW for LP4x
+ PLAT-52914: [GN] UMC::Phy::ForceClkDisable and UMC::CH::BeqCtrl2[DfiDramClkDis] incorrect on some DIMM config
+ PLAT-52904: [GN] Missing UMC::DramTiming15[CmdParLatency] in TcksrxS & Tcksre calculation
+ PLAT-52852: Milan SP3 MEM - Enable TwoActEn for Milan A0 systems
+ PLAT-47246: System hang at 0xEE00001F with bad DIMM population
+ PLAT-44839: MCA_DESTAT address is wrong in AGESA memory tester
+ PLAT-51726: [RN] [LPDDR4] MBIST Connectivity Test
+ PLAT-52456: [GN] ABL does not configure DIMM temperature sensor, part 2
+ PLAT-51503 [RN DDR4] BIOS should disable ECC if either the Dram or Fuse DO NOT have ECC capability
+ PLAT-52438 [RN][LP4] Enable CA training with CA OPT option for non-terminating rank
+ PLAT-51966, [GN] SPD Optimized token - non-CBS
+ PLAT-50260: PC ee070001 When running S3/S4 on specific systems FR - 6/27
+ PLAT-51851 [RN][LP4] For memory speed 1600 MT/s, use Global Vref for power saving
+ PLAT-47132 CP: S3 replay buffer overwritten by unaligned sub-index
+ PLAT-43347: CBS setting to select different refresh modes All bank, Per bank, Per 2 bank refreshes
+ PLAT-46615 RN - Use Global Vref for speed 1600
+ PLAT-52209 [RN][LP4] Change VrefCA seed for LP4x SRx16
+ PLAT-51931 [RN][LP4x][DR][x8] Default BIOS settings for LP4x DRx8
+ PLAT-47520: Update bit field for UMC::Phy::SequencerOverride for Chl Disable
+ PLAT-52056: [GN] Incorrect ABL post code in the end of ABL0 execution
+ PLAT-51916: [GN] Remove RDIMM 2R speed cap DDR2666
+ PLAT-51892 [RN] Reduce program to program cross-influence
+ PLAT-51909: [GN] ColBit and BankBit incorrect on BankGroupSwapAlt enabled
+ PLAT-51560 [RN][LP4] ProcODT cannot be updated thru the existing CBS option
+ PLAT-51772 [RN] [LPDDR4] Update Trfc value in SPD for the default DRx16 LP4x device (issue fix)
+ PLAT-50882: [RN] [LPDDR4] Add high effort PMU for higher LPDDR4x speed operation
+ PLAT-51818: [GN] Correct two APCB tokens to match Rome BIOS behavior
+ PLAT-47672 [RN] Update DdrMaxRate/DdrMaxRateEnf definition for combo DDR4/LPDDR4 OPN (issue fix)
+ PLAT-50881 [RN] [LPDDR4] 3733/4266 BIOS recipe (Disable DFE by default)
+ PLAT-47385: [ABLv2] Halt ABL execution after ABL triggers warm reset for bad DIMM isolation
+ PLAT-52515: Memory Training not performed on all PStates
+ PLAT-48795: [RN][AM4] Add new data type in APCB 2.0 to support RV1/ PCO/ RV2 Bixby
+ PLAT-52519 [RN]: FW should save-restore CcdUnitIdMask in S0i3
+ PLAT-51970, [GN] Board ID cannot be read from EEPROM on socket 1
+ PLAT-51717: [CZN] use C2P_MSG_97 & 98 as environment flag
+ PLAT-51095: [CZN] C2PMSG_98 - AblVerboseMessaging support
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN99186010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x99186010
+
+Features and Fixes:
+ PLAT-50890: GN - Remove SP3 Package Motherboard Type 0 support from Milan BIOS
+ PLAT-51487 [RN] [LP4] Please add CBS options for all other MRs for LP4/LP4X
+ PLAT-51418 Enable APCB update through setup and sync with SSP production
+ PLAT-51415: [GN] Force SMU to Limit Highest, and more
+ PLAT-49517 [RN] ABL: move eSPI configuration init to AB Add APCB tokens.
+ PLAT-51341 [RN][LPDDR4] Need a CBS option to program MR22 individually per rank
+ PLAT-51330 [RN][LPDDR4]Need a CBS option to update phyvref for LP4/LP4x
+ PLAT-51337 [RN][LPDDR4]Need a CBS option to update CA and DQ ODT for LP4/LP4x MR11
+ PLAT-51328 [RN][LPDDR4]Need a CBS option to update a VrefDQ seed value for LP4/LP4x MR14
+ PLAT-51126 [RN][LPDDR4]Add a CBS option to update a vrefca seed value for LP4/LP4x MR12
+ PLAT-51200 Set SOCID in initpkg7 and DE_CTL appropriately
+ PLAT-51201 Init ChXiVmgCfg0 VmgMode
+ PLAT-51717: [CZN] use C2P_MSG_97 & 98 as environment flag
+ PLAT-51018 [RN] The Part Number shows Unknown in SMBIOS Type17
+ PLAT-51689: Init Value of CCMPerCluster missing in PPR
+ PLAT-51609: [VMR] Integrate DXIO FW v46.590 for Vermeer
+ PLAT-49958: [GN] Add 4K interleave size option
+ PLAT-51553: TargetRemap register programming constraint
+ PLAT-51565 [GN] Integrate DXIO FW version 45.624 into ABL
+ PLAT-49431: Request to consolidate MP0/MP1 privileged space at top of memory
+ PLAT-51177 [RN]: Update DF register CoherentSlaveModeCtrlA0[EncryptTMZWrites] in BIOS
+ PLAT-51759 [RN] [DDR4] PLL related PHY registers are not restored for S3
+ PLAT-50881 [RN] [LPDDR4] 3733/4266 BIOS recipe
+ PLAT-51325: Update ABL MEM Register Map for PwrDownDly and AggrPwrDownDly
+ PLAT-51617: update mmresume to fix issue with VMR S3
+ PLAT-51421: Update PIE to skip PPT correctly on DFI_FREQ = 0x1[3:0]
+ PLAT-51488 [RN] [LP4] Update PMU msg blk UseBroadcastMR to use per rank MR commands
+ PLAT-51469 [RN][LPDDR4] Update PHYVref and DQ Vref seeds for LPDDR4x/LPDDR4
+ PLAT-51433 [RN][LPDDR4] Update MR12 and MR14 CBS option back-end behavior
+ PLAT-51337 [RN][LPDDR4]Need a CBS option to update CA and DQ ODT for LP4/LP4x MR11
+ PLAT-51603:Set DFPState ModeSel to Normal by default
+ PLAT-51095: [CZN] C2PMSG_98 - AblVerboseMessaging support
+ PLAT-51357 Renoir 0072 bad word - ABL
+ PLAT-51406: [Milan] Update Makefile to enable ABL Console Logging at Serial Ports
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN99066010 for Cezanne
+
+Date: Sep 06, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN99066010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x99066010
+
+Features and Fixes:
+ PLAT-46282: [RN] CBS options for LPDDR4/4x Periodic Retraining
+ PLAT-50373: [RN] LPDDR4 - BIOS to optimized FSP sequence in SRSM
+ PLAT-50988: [RN] CPPC bit of CPUID_Fn80000008_EBX should be set to 1 by default
+ PLAT-50697: [Renoir] clear SmmLock when S3 resume
+ PLAT-51130: [CZN] E010 at mem test requires DisOutgoingProbe set to 1b
+ PLAT-50849 [RN]: Incorrect memory info hob report if APCB_TOKEN_UID_UMAABOVE4G_VALUE disabled.
+ PLAT-50826: ABL dxioRegs SMN writes have unnecessary SMN read
+ PLAT-49784: [CZN] Use C2PMSG_97 for environment flag in ABL
+ PLAT-50929: [RN][LP4] CBS option for "WLS" is not working and default option needs to be correct as well
+ PLAT-50978 [RN] [LPDDR4] Add Max Frequency Support Table
+ PLAT-50889: [RN]LPDDR4] MBIST RRW Test does not capture read data on channel B
+ PLAT-48302 [Renoir][LP4] chiplet 7 instance of CA bus not being programmed correctly
+ PLAT-49326: [RN][LP4] x8 LP4x DRAM fail training
+ PLAT-49768: [RN[[LPDDR4/4x] WDQS extension mode aka the Tphy_wrlat_early version of WDQS Extension"
+ PLAT-51062 MTS: ABL Release WABLVM99044010
+ PLAT-44441: [ABLv2] Remove redundant Smbus speed setting in BoardID Smbus method
+ PLAT-50991 RN: ABL Release WABLRN99033030
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN98286010 for Cezanne
+
+Date: Aug 28, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN98286010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x98286010
+
+Features and Fixes:
+ PLAT-46987: Milan new feature support - 6 channel interleaving
+ PLAT-50477: [GN] Sync DF with latest production Rome
+ PLAT-50011 - Rep[Vermeer]ABL --> SMU message and CBS option to override the ChIdxHashEn fuse
+ PLAT-47264 [GN] Pre-memory link training
+ PLAT-48653: [Renoir] AGESA CPU Supports Boot From Rom
+ PLAT-50559: [CB] wrong address is used for L3CRB
+ PLAT-50405: [VMR] three registers have wrong value in S3 image
+ PLAT-49716: [GN] DSM workaround for multi-threaded cacheable scenario denied by CBA0 RTL
+ PLAT-49671: [VMR] DSM workaround for multi-threaded cachaeble scenario denied by CBA0 RTL
+ PLAT-50481: [GN] Integrate DXIO FW version 36.618
+ PLAT-50540: [VMR] update DXIO FW to 46.586
+ PLAT-50200: Vermeer DF to UMC request credit optimization
+ PLAT-45001: [MTS ABL] implement the function which provides BusBase/Limit
+ PLAT-49951: GN DF to UMC request credit optimization
+ PLAT-49946: [GN] Skip Phy RAM ECC workaround in emulation
+ PLAT-49872: [RN] Workaround for S0i3 resume DRAM access stuck
+ PLAT-49844: [VMR] update mp0 DXIO FW to v46.585
+ PLAT-42360: [ABLv2] ConsoleOutBasicCtrl should not depend on ConsoleOut filter
+ PLAT-50282: [CZN] Correct enabled Core/CCX bit mapping
+ PLAT-49819 [RN] ABL not sending S3Exit command to MP2 on S3Exit and S4 Resume
+ PLAT-49936: [VMR] Memory updates from MTS / Directory Restructure
+ PLAT-48946: [RN] [LPDDR4] Bank Swap
+ PLAT-48234 [RN] Update SrsmTiming0.Tcksrx Programming (following UclkDiv1Mode)
+ PLAT-49630: Rome [MEM] Support vendor-specific alternative frequency change sequence
+ PLAT-48028: Need additional debug data in ABL for CS and Rank for the DIMM failure
+ PLAT-50193 [RN[LPDDR4/4x] Update tRRD and tFAW settings based on LP4/4x device rated speed (base on native speed)
+ PLAT-49323 [RN] [LPDDR4] DDR-3733 and DDR-4267 not consider OC
+ PLAT-48954: [RN][LP4] Remove traffic Throttling from BU BIOS and update/fix TO timings
+ PLAT-50006: [RN] LPDDR4 Control Mappings
+ PLAT-50394: [RN] LPDDR4 MR13 Raw Hex Value should use FSP1/0 depending on MP State
+ PLAT-49103: [RN] [LPDDR4] SRSM VrefDQ Per SC, Per Rank
+ PLAT-48884: [RN] LPDDR4 MOP Array update for Raw Hex Values
+ PLAT-50291 [RN][LP4] Detect LPDDR4x via SPD byte 2
+ PLAT-49101 [RN] [LPDDR4] Remove Average VrefDQ Statements
+ PLAT-49766: [MILAN][MEM] Modify ABL based on Bump to Pin & ODT Pattern table
+ PLAT-48357: [RN] DDR4 ECC is not working properly in BIOS
+ PLAT-50671 [RN] GET_PMU_STAGE not returning MPState
+ PLAT-50577: GPU Host Translation Cache Registers to disable
+ PLAT-49980 [RN] VDDP voltage control option not working (New SMU MSG)
+ PLAT-49117 [RN] SET_MEM_FREQ call should update ConfigSocRail Speed
+ PLAT-50790: [CZN] disable serial port and enable IoRedirection for ABL
+ PLAT-50761: [CZN] update BootRomTable.h
+ PLAT-43520: [ABLV2] Incorrect port width used in BoardID IO method & PLAT-43985: [ABLV2] Incorrect PCI access function called to enable IO port decode in BoardId IO method
+ PLAT-49980: [RN] VDDP voltage control option not working
+ PLAT-50657 - ABL Build error on SMU message
+ PLAT-44041 [RN] Multiple APCB support selected thru EC RAM (Fix issue)
+ PLAT-50446: [RN] CCX1 per core/thread DF save incorrect
+ PLAT-50241: [VMR] enable serial log for ABL
+
+
+----------------------------------------------------------------------------
+
+ABL Delivery Release Notes
+
+Copyright 2019, Advanced Micro Devices, Inc.
+
+Version: MABLCZN98126010 for Cezanne
+
+Date: Aug 12, 2019
+
+----------------------------------------------------------------------------
+
+Content:
+Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL Post Code Definitions
+ AgesaBLReleaseNotes.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file for AM4
+ AgesaBootloader_U_prod_CN.bin AgesaModulePkg\Firmwares\CZN\ Unified AGESA Bootloader
+ APCB.h Include\APCB.h AGESA PSP Configuration Block Definition
+ APOB.h Include\APOB.h AGESA PSP Output Block Definition
+
+
+Path to files:
+
+
+XML Path:
+ /BIOS/ec/Client/Components/AGESA/ABL-V2/manifest/Custom/MABLCZN98126010.xml
+
+Based On:
+ master
+
+ABL Version String:
+ 0x98126010
+
+Features and Fixes:
+ Initial ABL release for E.0.1.0
\ No newline at end of file
diff --git a/cezanne/PSP/AgesaRTReleaseNote.txt b/cezanne/PSP/AgesaRTReleaseNote.txt
new file mode 100644
index 0000000..fa0c471
--- /dev/null
+++ b/cezanne/PSP/AgesaRTReleaseNote.txt
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------------
+ABL RT Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: ABL RT RABLRTCZN20081800 for Cezanne
+
+Date: August 18 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL/ABL RT Post Code Definitions
+ AgesaRTReleaseNote.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x2D_AgesaRunTimeDrv_CZN.sbin AgesaModulePkg\Firmwares\CZN\ Main AGESA Runtime Driver
+
+Based On:
+ trunk_Cn
+
+ABL RT Version String:
+ 0x08183030
+
+ABL RT Features and Fixes:
+ - PLAT-68151: [CZN] Increment SPL value to support firmware anti rollback feature for production
+
+Known Issue(s):
+
+----------------------------------------------------------------------------
+ABL RT Delivery Release Notes
+
+Copyright 2020, Advanced Micro Devices, Inc.
+
+Version: ABL RT RABLRTCZN20042100 for Cezanne
+
+Date: April 21 2020
+
+----------------------------------------------------------------------------
+
+Content:
+
+ Filename AGESA V9 Destination Folder Description
+ AblPostCode.h AgesaModulePkg\Firmwares\CZN\ ABL/ABL RT Post Code Definitions
+ AgesaRTReleaseNote.txt AgesaModulePkg\Firmwares\CZN\ This Release notes file
+ TypeId0x2D_AgesaRunTimeDrv_CZN.sbin AgesaModulePkg\Firmwares\CZN\ Main AGESA Runtime Driver
+
+Based On:
+ Initial version
+
+ABL RT Version String:
+ 0x04213030
+
+ABL RT Features and Fixes:
+
+ Initial ABL RT Modern Standby support
+
+Known Issue(s):
+
diff --git a/cezanne/PSP/Cezanne VBL Release Notes.txt b/cezanne/PSP/Cezanne VBL Release Notes.txt
new file mode 100644
index 0000000..b66504c
--- /dev/null
+++ b/cezanne/PSP/Cezanne VBL Release Notes.txt
@@ -0,0 +1,261 @@
+============================ Cezanne 17.10.0.26 VBL release ========================================
+Cezanne generic VBL 17.10.0.26
+Cezanne A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. PLAT-67393[CZN][ComboAM4v2][Artic]: SUT will hang PC 20A0/2097 when flash Capsule BIOS with 64G memory installed
+
+============================ Cezanne 17.10.0.25 VBL release ========================================
+Cezanne generic VBL 17.10.0.25
+Cezanne A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. PLAT-67659:Increment SPL value to support firmware anti rollback feature for production
+
+============================ Cezanne 17.10.0.24 VBL release ========================================
+Cezanne generic VBL 17.10.0.24
+Cezanne A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Changing GCEA SDP tag limit for CZN LPDDR4 system.
+
+============================ Cezanne 17.10.0.23 VBL release ========================================
+Cezanne generic VBL 17.10.0.23
+Cezanne A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Update the LANEx_ANA_TX_LP_ATT setting to improve SI
+
+============================ Cezanne 17.10.0.22 VBL release ========================================
+Cezanne generic VBL 17.10.0.22
+Cezanne A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Update the eDP/DP/HDMI MPLLb settings for CZN/LCN
+
+============================ Renoir 17.10.0.21 VBL release ========================================
+Renoir generic VBL 17.10.0.21
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Update the MMEA/GCEA shadow registers settings
+
+============================ Renoir 17.10.0.20 VBL release ========================================
+Renoir generic VBL 17.10.0.20
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Update the DAGB0_WR_DATA_CREDIT[16:23]MIDDLE_BURST_CREDITS setting to 0x62 for PLAT-62751
+
+============================ Renoir 17.10.0.19 VBL release ========================================
+Renoir generic VBL 17.10.0.19
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Update the vboost_lvl setting and enable tx_vboost_lvl override in SUP_DIG_LVL_OVRD_IN
+
+============================ Renoir 17.10.0.18 VBL release ========================================
+Renoir generic VBL 17.10.0.18
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Set bit 14 & bit 13 @LANEX_DIG_ASIC_TX_OVRD_IN_1 to 0x1 for eDP only; others keep as H/W default 0
+
+============================ Renoir 17.10.0.17 VBL release ========================================
+Renoir generic VBL 17.10.0.17
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Set bit 14 & bit 13 @LANEX_DIG_ASIC_TX_OVRD_IN_1 to 0x1 for eDP/DP; others(HDMI/DVI) keep as H/W default setting 0.
+
+============================ Renoir 17.10.0.16 VBL release ========================================
+Renoir generic VBL 17.10.0.16
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. Set bit 14 & bit 13 @LANEX_DIG_ASIC_TX_OVRD_IN_1 to 0x1 to fix eDP PHY Power is really high issue.
+
+============================ Renoir 17.10.0.15 VBL release ========================================
+Renoir generic VBL 17.10.0.15
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader_prod.sbin is the FW sign.
+
+Major feature:
+1. it's GFX only and for DEGSIGMH10-933<- these are the ones we just asked to add
+ +ATC_L2_DEBUG2.DISABLE_2M_CACHE=0x1
+ +ATC_L2_CNTL2.BANK_SELECT=0x9
+ +ATC_L2_CNTL2.L2_BIGK_FRAGMENT_SIZE=0x9
+2. PLAT-53684 [RN] Renoir 0090RC3 MMHUB registers init value fail
+ Description:DAGB0 write data credits
+
+ PreS3 Value = 6C6C6C70h (_aliasSMN=>MMHUBx000020C)
+ [24:31]SMALL_BURST_CREDITS
+ PreS3 Value = 6Ch (_aliasSMN)
+ Fail. Expected Value = Init:68h(Read:6Ch) (_aliasSMN)
+ [8:15]LARGE_BURST_CREDITS
+ PreS3 Value = 6Ch (_aliasSMN)
+ Fail. Expected Value = Init:60h(Read:6Ch) (_aliasSMN)
+
+============================ Renoir 17.10.0.14 VBL release ========================================
+Renoir generic VBL 17.10.0.14
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Get customized tx_term_ctrl from static info tabe
+2. PLAT-49688 BME fault after BIOS posts, clear ATHUB fault status by ATC_ATS_FAULT_DEBUG[1]CLEAR_FAULT_STATUS_ADDR=0x1
+
+============================ Renoir 17.10.0.13 VBL release ========================================
+Renoir generic VBL 17.10.0.13
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Get customized tx_vboost_lvl from static info tabe
+2. RTGPLAT-2317 Updates to MMEA&GCEA shadow register
+
+============================ Renoir 17.10.0.12 VBL release ========================================
+Renoir generic VBL 17.10.0.12
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Update new eDP early on sequence
+
+============================ Renoir 17.10.0.10 VBL release ========================================
+Renoir generic VBL 17.10.0.10
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Sync the Phy settings to the 015 Vbios which takes the GDB updated till August 23, 2019.
+
+
+============================ Renoir 17.10.0.9 VBL release ========================================
+Renoir generic VBL 17.10.0.9
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Move the display PHY FW loading from VBios back to Vbl.
+2. Fix to (PLAT-49161) (Workflow Issue Updated) [RN] GCEA shadow registers are not programmed correctly
+
+============================ Renoir 17.10.0.8 VBL release ========================================
+Renoir generic VBL 17.10.0.8
+Renoir A0 0x1636 105_D27000_00A
+
+The VbiosBootLoader.sbin is the test key 2K sign.
+The VbiosBootLoader_FW.sbin is the FW sign.
+
+Major feature:
+1. Move the display PHY FW loading from VBL to Vbios.
+
+============================ Renoir 17.10.0.7 VBL release ========================================
+Renoir generic VBL 17.10.0.7
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.sbin
+
+Major feature:
+1. Remove the following mirroe registers from VBL, Sbios will take care of them.
+ COPY# +MC_VM_NB_LOWER_TOP_OF_DRAM2.LOWER_TOM2=NB_LOWER_TOP_OF_DRAM2
+ COPY# +MC_VM_NB_MMIOBASE.MMIOBASE=NB_MMIOBASE
+ COPY# +MC_VM_NB_MMIOLIMIT.MMIOLIMIT=NB_MMIOLIMIT
+ COPY# +MC_VM_NB_PCI_ARB.VGA_HOLE=NB_PCI_ARB
+ COPY# +MC_VM_NB_PCI_CTRL.MMIOENABLE=NB_PCI_CTRL
+ COPY# +MC_VM_NB_TOP_OF_DRAM_SLOT1.TOP_OF_DRAM=NB_TOP_OF_DRAM_SLOT1
+ COPY# +MC_VM_NB_UPPER_TOP_OF_DRAM2.UPPER_TOM2=NB_UPPER_TOP_OF_DRAM2
+2. Support the static info table.
+3. Sign Renoir test key 2K with out compress and encrypt.
+4. Change the revision number to 17.10.0.7.
+
+============================ Renoir 17.10.0.6 VBL release ========================================
+Renoir generic VBL 17.10.0.6
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Display PHY FW updated to dwc_usbc31dptxphy_phy_x4_ns_pcs_raw_sram.renoir_bringup.fw received from Joanne on June 23.
+2. Sign Renoir test key 2K with out compress and encrypt.
+3. Change the revision number to 17.10.0.6.
+
+============================ Renoir 17.10.0.5 VBL release ========================================
+Renoir generic VBL 17.10.0.5
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Golden settings updated to PPR rev 103 released on June 7.
+2. Sign Renoir test key 2K with out compress and encrypt.
+3. Change the revision number to 17.10.0.5.
+
+============================ Renoir 17.10.0.4 VBL release ========================================
+Renoir generic VBL 17.10.0.4
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Change the revision number to 17.10.0.4.
+2. VBL DP Phy Static Info Table
+
+============================ Renoir 17.10.0.3 VBL release ========================================
+Renoir generic VBL 17.10.0.3
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Change the revision number to 17.10.0.3.
+2. load display PHY firmware and phy init.
+
+
+============================ Renoir 17.10.0.2 VBL release ========================================
+Renoir generic VBL 17.10.0.2
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Change the revision number to 17.10.0.2.
+2. ASIC init is moved from Vbios to VBL
+
+============================ Renoir 17.10.0.1 VBL release ========================================
+Renoir generic VBL 17.10.0.1
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Change the revision number to 17.10.0.1.
+2. enable VBL GFX power up sequence by sending message ID VBIOSSMC_MSG_PowerUpGfx to SMU.
+
+
+============================ Renoir 004 VBL release ========================================
+Renoir generic VBL 004
+Renoir A0 0x1636 105_D27000_00A VbiosBootLoader.bin
+
+Major feature:
+1. Prototype Renoir PSP Vbios boot loader for Simnow and HWE.
+2. Part of the Asic init is moved from Legacy Vbios, including Nbif init, AThub init, GMHub init, HDP init. This VBL should work together with Leagcy Vbios 004.
diff --git a/cezanne/PSP/MP2FWCZNReleaseNote.txt b/cezanne/PSP/MP2FWCZNReleaseNote.txt
new file mode 100644
index 0000000..0b0cf5f
--- /dev/null
+++ b/cezanne/PSP/MP2FWCZNReleaseNote.txt
@@ -0,0 +1,78 @@
++-----------------------------------------+
+| MP2 SFH Firmware Release Notes - CEZANNE
++-----------------------------------------+
++----------------------------------------------------------------------------------------------
+| Version 7.0.0.1
++----------------------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 12/02/20
+|
+| * Features enabled
+| - Process 32 C2P Message Interupt
+| - Process 6 GPIO Interupt
+| - P2C Message Register is enabled
+| - Support S3/S0ix Entry/Exit
+| - Secondary Accelerometer Uses GPIO271
+|
+| Jira ID : [PLAT-58706] [CZN] Secondary Accel uses GPIO271
+|
+| * Limitation
+|
++----------------------------------------------------------------------------------------------
+| Version 7.0.0.3
++----------------------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 12/06/20
+|
+| * Features enabled
+| - Add Support for dual sensors using interrupt
+| - ALS calibration and retrieval of calibration factor
+|
+| Jira ID : [PLAT-65021] [CZN] Retrieving of calibration factor value after BIOS update
+|
+| * Limitation
+|
++----------------------------------------------------------------------------------------------
+| Version 7.0.0.5
++----------------------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 17/07/20
+|
+| * Features enabled
+| - Add Support for "on-table" detection
+| - Add new parameters in the config file
+|
+| Jira ID : [PLAT-66692] [CZN] Add support for "on-table" detection
+|
+| * Limitation
+|
++----------------------------------------------------------------------------------------------
+| Version 7.0.6.3
++----------------------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 15/09/20
+|
+| * Features enabled
+| - Add Support for "on-table" detection
+| - Add new parameters in the config file
+|
+| Jira ID : [PLAT-69915] [CZN] Support Boot with lid close and detect close mode
+|
+| * Limitation
+|
++----------------------------------------------------------------------------------------------
+| Version 7.0.6.4
++----------------------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 29/09/20
+|
+| * Features enabled
+| - Add Support for "on-table" detection
+| - Add new parameters in the config file
+|
+| Jira ID : [PLAT-70227] [CZN_FP6][MP2 SFH] Sometimes sensors does not work after system
+| reboot or cold boot
+|
+| * Limitation
+|
++----------------------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/cezanne/PSP/MP2FWConfig.sbin b/cezanne/PSP/MP2FWConfig.sbin
new file mode 100644
index 0000000..0a60aa5
--- /dev/null
+++ b/cezanne/PSP/MP2FWConfig.sbin
Binary files differ
diff --git a/cezanne/PSP/PSP_ReleaseNotes.txt b/cezanne/PSP/PSP_ReleaseNotes.txt
new file mode 100644
index 0000000..2c284e8
--- /dev/null
+++ b/cezanne/PSP/PSP_ReleaseNotes.txt
@@ -0,0 +1,2565 @@
+//----------------------------------------------------------------------------
+// PSP FW Delivery Release Note
+//
+// Copyright 2020, Advanced Micro Devices, Inc.
+// Date: November 23, 2020
+//----------------------------------------------------------------------------
+
+Content:
+ *FOR INTERNAL USE ONLY*
+ PSP FW Deliverables for Renoir.
+ This Build is compiled using the ARM license from the AMD license server.
+
+TODO: update list of files
+Files
+ boot_loader_RN.bin [version: 0.11.2.63] - PSP off-chip Legacy Stage 2 BootLoader (entry type 0x1), signed with production key
+ boot_loader_AB_RN.bin [version: 0.11.2.63] - PSP off-chip A/B Stage 2 BootLoader (entry type 0x1), signed with production key
+ boot_loader_stage1_RN.bin [version: 0.11.2.63] - PSP off-chip Stage 1 BootLoader (entry type 0x1), signed with production key
+ PspRecoveryBootLoader_RN.bin [version: 0.11.2.63] - PSP off-chip Recovery BootLoader (entry type 0x3), signed with production key
+ debug_unlock_RN.bin [version: 0.11.2.63] - PSP secure unlock (entry type 0x13), signed with production key
+ psp_os_combined_NV12.bin [version: 0.11.2.63] - PSP secure OS (entry type 0x2), signed with production key
+ drv_sys_RN.bin [version: 0.11.2.63] - PSP system driver (entry type 0x28), signed with production key
+ dr_ftpm_prod_RN.csbin [version: 3.51.0.5] - PSP fTPM (entry type 0xC), compressed and signed with production key
+ dr_drtm_prod_RN.csbin [version: 04.11.00.1D] - PSP DRTM (entry type 0x47), compressed and signed with production key
+ rsmu_sec_policy.rn_L0.sbin [version: B.9.0.78] - Security Gasket (entry type 0x24)
+ rsmu_sec_policy.rn_L1.sbin [version: B.9.1.78] - Security Policy for tOS (entry type 0x45)
+ spl_table_RN.sbin [version: 5.11.0.5C] - Firmware Anti-rollback information file (entry type 0x55)
+ spl_table_CZN.sbin [version: 5.11.1.63] - Firmware Anti-rollback information file (entry type 0x55)
+
+Release Version 0.11.1.63
+-----------------------------------
+* CZN SPL table updated to v05.11.01.63
+
+Bootloader
+----------------
+NA
+
+Trusted OS
+----------------
+PLAT-69424 : [CZN] System hang with post code A5F0 in BIOS flash stress test - reverted old workaround
+ and provided a proper fix
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+N/A
+
+Release Version 0.11.1.63
+-----------------------------------
+* CZN SPL table updated to v05.11.01.63
+
+Bootloader
+----------------
+PLAT-71974: Legacy recovery process stuck in 0xEEA90022
+PLAT-71710: Fix fusing of Bios Key Revision ID
+PLAT-70156: SUT stuck at Postcode 00000000 with ROM MX25U25673G
+PLAT-71863: Update BL/debug_unlock to armcc v5.06
+PLAT-69014: SVC call to disable RDRAND enhancement
+
+Trusted OS
+----------------
+PLAT-69424 : [CZN] System hang with post code A5F0 in BIOS flash stress test.
+PLAT-71710: Fix fusing of Bios Key Revision ID
+PLAT-64628: Adds cmd to show security violation timestamp
+SWDEV-258598: Interleave dis-assembly with source code
+LWPQA-564: Dead default in switch statement
+LWPQA-561: Dead default in switch
+LWPQA-562: Unnecessary header file
+LWPQA-563: Unnecessary header file
+LWPQA-560: Unnecessary header file
+PLAT-71511: [RPMC] Report RPMC Available Counter Addresses to BIOS
+RTGPLAT-5747:[NV2x]:Debug unlock thread in trusted OS need not be killed for unlocked device.
+SWDEV-257638: Dont error out loading of USB PD FW when TMR is not present
+PLAT-71433: Document the used bits of C2PMSG_38 register
+PLAT-71181: Align RMB header files to MTO 1322172
+PLAT-70273: Wait for DF restore on z-state exit
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.62
+-----------------------------------
+* DRTM updated to v04.11.00.1D
+
+Bootloader
+----------------
+PLAT-71298: Add corruption info for recovery mode in tOS.
+PLAT-64168: ROM Armor v2 changes - phase9
+PLAT-70258: Support 2 instance type 0x62 for A/B recovery
+PLAT-71042: Fix smn_with_size mapping/unmapping bugs
+PLAT-71380: Add missing Svc_BIOSDirectorySearchV2 declaration
+PLAT-71091: Fix BIOS OEM leaf key validation
+PLAT-70767: [RPMC] Handle Counter Reading Fail Case
+PLAT-68343: [RPMC] Update RpmcAvailableFlag in RPMC disabled case
+
+Trusted OS
+----------------
+PLAT-71298 Add corruption info for recovery mode in tOS.
+PLAT-64168: ROM Armor v2 changes - phase9
+RTGPLAT-5690: Resolved Guest Fw load failure
+RTGPLAT-5765: [NV2x] RAP L0 Rollback Validation failure via RAP-TA
+SWDEV-256542: [Mi200] Flip override bit UTCL2IUGPAOVERRIDE
+SWDEV-256542: [Mi200] Override CP Guest Phy Addr bit for UTCL2
+AER-232: [A1]Secure part can't load win GFX driver
+PLAT-70750: Rollback of [AER][VGH] Binaries named in the TypeId format.
+PLAT-66360: [RMB] Update CS-SEED-based KDF and Key Unwrapping
+PLAT-70811: Add zstate entry/exit driver command IDs
+PLAT-70274: Added Z-state init to S3-resume
+PLAT-70268: Unpowergate CCP on z-state exit
+MNTPLAT-745: HID-SPI banged after S0i3 with DRTM enabled
+PLAT-68879:Add functionality to MPM read/write reg API
+PLAT-70272: Change TOS to use MP0 RSMU clock
+AER-206: Move UVD security accesses to UVD PG programming
+PLAT-63918:[Navi] Enable protection bit for CCP side channel protection
+SWDEV-240041: Resolving a bitwise and typo and coverity defect
+PLAT-70274: Moved z-state setup code out of z-state entry
+PLAT-70079: TOS should ensure driver sets up TMRs before allowing loading of gfx fw
+PLAT-68839:Add functionality to MPM memory mapping API
+SWDEV-213799: MPIO RAS error handling in TOS
+PLAT-68882: Add API to restore and verify AMF FW in MPM DRAM
+SWDEV-251569: [MI200][tOS][RAP] RAP V2 validation integration via RAP TA
+DERMBE-439: Unmask SMU cmd interrupt on z-state entry
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+MNTPLAT-745: HID-SPI banged after S0i3 with DRTM enabled
+
+Release Version 0.11.0.61 (Cancelled)
+-----------------------------------
+Bootloader
+----------------
+PLAT-70737 Fix SPI FIFO size
+PLAT-70767 RPMC read counter before releasing cores
+PLAT-70595: Remove alignment constraints when copying from SPIROM
+FEAT-33379: Configuration of ROM through SPI-ROM Configuration external binary
+PLAT-70761: Refactor PSP-SMU mailbox commands for APU
+PLAT-64168: Changes for ROM Armor v2 - phase8
+DERMBE-337: Apply GFX DLDO policy on PMFW cmd 0x1B
+PLAT-70432 RPMC handle extended status 0x00
+PLAT-70464: Make MP2-SFH default
+PLAT-70346: Remove unnecessary debug prints
+
+Trusted OS
+----------------
+LWPQA-462: Replacing _smc(0) syntax on SmcCall
+SWDEV-255293 - [MI-200]: Mode 2 Reset - suppport GFX SDP Port disable
+LWPQA-510: Unnecessary header include
+LWPQA-508: Added #ifdef guard on include for RMB
+PLAT-70522: [RN] Adding ATAG parameters to pass on DMAr information to KVM.
+AER-165: Do not enable UVD_REG_FILTER_EN in non-secured BIOS on Chachani systems
+SWDEV-255233: Update MI200 TOS FW Id
+PLAT-60666: [VGH] Implement TMZ in PSP TOS
+PLAT-70465: RN support for X470 annd B450 Promontory Chipsets
+PLAT-60176: Updates gfx component list for RMB
+PLAT-70750: [AER][VGH] Binaries named in the TypeId format.
+PLAT-64168: Changes for ROM Armor v2 - phase8
+FEAT-34947: [tOS][RAP] Robustness improvements for GFX DPM handling for RAP validation
+SWDEV-249497: [Mi200] Save/ Restore bootrom table fields into SRAM
+SWDEV-251569 : [PSP TOS] RAP v2 support in RAP TA
+DERMBE-337: Apply GFX DLDO policy on PMFW cmd 0x1B
+PLAT-70625: [CZN] PRO fuse data register change
+DERMBE-298: [RMB] Apply UVD policy after UVD power up
+PLAT-70616: Add mutex to SendPspSmuMessage function
+SWDEV-248735:MI200 Rectified internal VCN register offsets
+PLAT-70549: Set API permissions for MFD
+SWDEV-251576 : GFX DPM: Restore CLKB / VDD_GFX L0 Security Settings on GFX OFF exitT
+SWDEV-252903: [MI200][tOS][RAS] Whitelist Register Access Failure
+SWDEV-248568 : [PSP TOS] RAP v2 Update Based on additional comments
+PLAT-70349 VGH: Add function for DRV_SYS_CMD_ID_PRIV_GET_HSP_SRAM_SMN_ADDR
+PLAT-60493: save MSMU dRAM on S3
+PLAT-70063: Include tee_crypto.h in tcg_logs.h
+PLAT-70080: [VN][RMB] Update VCN internal reg offsets
+SWDEV-248568 : (amd-tee2.0) Update RAP V1 EventTypes
+PLAT-67368 : System BSOD 0xEA in S4/S5/Reboot loop.
+SWDEV-253502 : fix pointer issue (because of RAP V2 change to PSP TOS)
+SWDEV-253120: Apply GRBM CAM policy on non-secure or unlocked part
+SWDEV-253168: Enable TOS profiling for Navi21
+RTGPLAT-5037:[Navi2x] LIVMIN/D0I3 support
+SWDEV-248568 : RAP V2 Integration in Trusted OS for L1 policy apply
+FEAT-34773: Caller side implementation of fwar
+FEAT-32981: Fw Attestation Database API
+SWDEV-247728 [NV][SRIOV]Introduce a PF command for VF FW clean
+
+fTPM
+-----
+PLAT-66418 VGH: SWDEV-229523 Merge HSP NV Support changes to amd-staging branch
+PLAT-70462 VGH: [FTPM] Get HSP SRAM address from PSP
+PLAT-68945: FTPM TA code enhancement against CERT violations
+
+DRTM
+-----
+PLAT-68805: DRTM TA binary name enhancement and minor compile error fix.
+
+
+Release Version 0.11.0.60
+-----------------------------------
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+PLAT-64168: Enforce ROM Armor v2 - phase7
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+N/A
+
+Release Version 0.11.0.5F
+-----------------------------------
+Bootloader
+----------------
+PLAT-69153 [BOOTLOADER]RPMC tool reports incorrect status after resuming from S0i3
+PLAT-69745[BOOTLOADER]A/B Recovery reason logging support
+PLAT-68205: [RPMC] Remove Duplicate Macro Definitions
+
+Trusted OS
+----------------
+PLAT-69289: [tOS] Pass Tpm Ext NV information using FLAG_ID_TPM_EXT_EN
+PLAT-69716: Armcc Compiler upgrades from v5 to v5.06
+PLAT-68862: [TOS] Add data checking to the CcpGenerateRandom
+PLAT-61278: [VN] [HSP] PCR Measurements in tOS
+PLAT-69710:Replace hardcoded values
+PLAT-66316 VGH: Set HSPNV buffer CmdResp field Bit 31 to 1 by HSPNv thread in system driver during Interface Setup
+
+fTPM
+-----
+PLAT-68945: FTPM TA code enhancement against CERT violations.
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.5E
+-----------------------------------
+* Cezanne: Switched to Cezanne-specific signing keys
+
+Bootloader
+----------------
+PLAT-69759: SVC call to enable extended fTPM storage
+FEAT-33378: Configuration of ROM through SPI-ROM Configuration external binary
+PLAT-67627 [BOOTLOADER]System can't boot with case 2&3 of BIOS layout
+PLAT-61152: [RPMC]Support of RPMC Capable Macronix SPI-Parts
+PLAT-69289: [BOOTLOADER] Pass fTPM extended storage flag to TOS
+PLAT-57225: RDRAND performance enhancement
+PLAT-66438: remove incorrect code from RPMC
+PLAT-67620: SUT failed to boot the first time with GD25LQ128D QE bit cleared
+PLAT-60739: [RPMC] Remove Redundant Code
+PLAT-68679: Clear the MMU page tables on startup
+PLAT-67218: [RPMC]Add ADS Check for Giga Device Parts
+
+Trusted OS
+----------------
+SWDEV-252142: [MI200][RWL] Fix build error due to misaligned concatenation
+SWDEV-214841 - Update to Arm Compiler v6
+SWDEV-249184: Disable TOS profiling for Navi21
+SWDEV-251923: fix usbpd update issue
+PLAT-69694: [REV] Disable HSP in default on ToS
+SWDEV-214841 - Update to Arm Compiler v6
+PLAT-68599:Add API to Initialize MFD
+SWDEV-250905:[Navi2x] Clear the "boot mode" after the BACO boot
+ FEAT-33002: enable spi access functions for NV21
+DERMBE-231: Run USB configure command to only in SMI mode
+DERMBE-325: Add SMU load USB FW cmd arguments for RMB
+PLAT-57225: RDRAND performance enhancement
+SWDEV-250408: [MI200] Fix RWL binary load failure due to skipping PSP-FW-header twice
+PLAT-67835: [AER] exclude CVIP and CLKA3 on RSMU table
+SWDEV-247524: [NV21][tOS] Skip GFX Sec-Pol reapplication in secure-unlocked state
+PLAT-69000: [CZN_AM4] No video with hang PC: A69B while running reboot
+PLAT-68843:Add functionality to MPM SRAM mapping API
+SWDEV-211107:MI200-RAS: Rectify bug in MCA Syndrom register access
+SWDEV-211107:MI200-RAS:SMN Slave Timeout and SMN Data Parity handling
+SWDEV-250303: Update PSP TOS to pass down VFID from GFX Mailbox
+SWDEV-211109: [Mi200] Handle Poison Data conumption (dGPU)
+PLAT-68190: Pass MPM config and DRAM address to BIOS
+SWDEV-246861:MI200-RAS : Handle WAFLC interrupt
+SWDEV-248518:MI200-VCN 0/1 FW move Cache/Data in seperate TMRs
+
+fTPM
+-----
+PLAT-68805: FTPM TA binary name adjustment.
+PLAT-69442 CZN: [FTPM] Configure TPM NV size to 32K/16K based on FLAG_ID_TPM_EXT_NV_EN from PSP tOS
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.5D
+-----------------------------------
+Bootloader
+----------------
+PLAT-65875: Add defines for hard-coded values in TPM SVC Call
+PLAT-68637: System can't boot with ROM XMC25QH256B
+PLAT-68593: Cezanne signing for firmware components
+PLAT-68343: [RPMC] Provisioning RPMC Key on SPI Parts already Programmed
+
+Trusted OS
+----------------
+SWDEV-248077: Fix return value during error case
+FEAT-33002: [NV21] enhace block protection for SPI access
+PLAT-68494: Add API function calls to PrivDispatch_v2
+FEAT-33002:[NV21] use the hard coded hmac key from BL
+PLAT-68090:Update firmware file names
+PLAT-67722: Skip MPM RSMU interrupt setup when MPM is disabled
+PLAT-68593: Cezanne signing for firmware components
+PLAT-66947: Add SMU-to-PSP cmd for CLKB GC sec policy
+PLAT-68504: Update USB unified binaries to search by SocFwID for relevant programs
+SWDEV-211109: [Mi200] Handle Poison Data conumption (A+A)
+PLAT-68343: [RPMC] Provisioning RPMC Key on SPI Parts already Programmed
+PLAT-66314: support Aerith on amd-tee2.0
+PLAT-68510: [VN] ISP FW loading GFX-9 conditional compiling bug fix
+SWDEV-240694: [NV12][Virtualization] Resolve AWS EventGuard5 test
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+PLAT-68541: Update SOC FW ID of DRTM TA in PSP FW Image Header
+PLAT-67985: DRTM TA code enhancement against CERT coding standard violations
+
+
+
+Release Version 0.11.0.5C
+-----------------------------------
+* Renoir L0 Security policy is updated to B.9.0.78
+* Renoir L1 Security policy is updated to B.9.1.78
+* Renoir SPL table 5.11.0.5C
+* Cezanne SPL table 5.11.0.5C
+
+Bootloader
+----------------
+PLAT-68313: Remove Svc_ReadSecureRTC implementation
+PLAT-66438: avoid legacy registers in RPMC
+PLAT-64168: ROM-Armor ver2 for client - phase5
+
+Trusted OS
+----------------
+RTGPLAT-4734: [Navi22] TMR setup of VCN1 shall be done based on Clock setting.
+PLAT-68387: Unified table entries need to adhere to specified struct
+PLAT-67407: [VRMR]: Fix the coverity defects
+PLAT-64168: Enforce ROM Armor v2 security-policy - phase6
+FEAT-33001:Boot config data bug fix
+DERMBE-279:[RMB] Update security violation logging
+PLAT-67804:update reg to LSE 1294576
+SWDEV-246295:NV21 - Enabled the sharing of XGMI Topology to SMU
+PLAT-64168: ROM-Armor ver2 for client - phase5
+SWDEV-248234: [Navi23]Enable NP mode for nv23
+PLAT-68081: FwType and Subtype must be enforced when loading/validating USB PHY FW
+PLAT-68076: Fix dGPU compile warning
+SWDEV-245537: [NV21] Support preset Trace Log message in the TOS System Driver
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+N/A
+
+
+
+Release Version 0.11.0.5B
+-----------------------------------
+Bootloader
+----------------
+PLAT-67894: Add BIOS Key antirollback enforcement
+PLAT-67664: Increment SPL value for Renoir PSP components for FAR deployment
+PLAT-67810: [BOOTLOADER] Make key derivation compatible with TOS
+PLAT-67015: Support of RPMC Capable Giga SPI-Parts
+PLAT-66702:[BOOTLOADER]Emit Morse coded sound on errors
+PLAT-66608: [RPMC]Remove Redundant Code and Add More Annotations
+
+Trusted OS
+----------------
+PLAT-60855: [TOS] Add APCB sign/validate BIOS commands
+SWDEV-247939:[Navi2x] Fix Debug unlock failure issue
+SWDEV-248077: Fix the coverity errors
+PLAT-67664: Increment SPL value for Renoir PSP components for FAR deployment
+SWDEV-240996:Updated TMR Fabric ID and VCN/VCN1 defines for LSE
+PLAT-67579: update A/B recovery in ToS
+DERMBE-272: [RMB] Remove MMHUB reg s0i3 save/restore
+PLAT-62057:[RMB] remove the saving of MSMU7 in s0i3
+RTGPLAT-4707:[Navi23] Correct the MMHUB0 FID value
+SWDEV-247528: Reset VCN counters on VCN FW load in TMR region
+SWDEV-246727: Fix encrypted counter location in VCN TMR memory
+SWDEV-246727: fix build flag issue to get VCN encrypt conter offset
+PLAT-66446: [CZN]pre-requisite check control to manage DRTM enablement
+SWDEV-245749: [MI200][RWL] Update Register Access Whitelist (RWL) for RAS section
+SWDEV-241899: [MI100][tOS] Bug Fix in xGMI-TA read-write API core function
+PLAT-66608: [RPMC]Remove Redundant Code and Add More Annotations
+SWDEV-244681: Add Write enablement/ disablement to DF Fence macro
+PLAT-58030: Move rsmu_config.h for RMB and VGH to shared_bl2os
+SWDEV-246092: RMB [VN] S0i3: DMCUB sequence for S0i3
+SWDEV-240996:MI200 - Header files updated to LSE bootcode
+FEAT-33001: Cleaning up SPI controller
+
+fTPM
+-----
+PLAT-67820: MakeFile change to add SPL Value in FTPM FW Header
+
+DRTM
+-----
+PLAT-67293: Enable DRTM service only on FAR-enabled system
+
+
+Release Version 0.11.0.5A
+-----------------------------------
+Bootloader
+----------------
+PLAT-66529 new Soft Chain Fuse bit for port 80 writes
+
+Trusted OS
+----------------
+PLAT-67370, PLAT-67405: Promontory LP chipset support for CZN
+PLAT-66529 new Soft Chain Fuse bit for port 80 writes
+SWDEV-245870: [Mi200] Protect BL reserved SMN TLB
+PLAT-66825: [TOS] Align the BL_TMR_INFO's address fields
+PLAT-67400: [VRMR]: Correct the number of TMR slot
+PLAT-65009 RN: Provide increment of SMC transaction status back to fTPM driver
+DERMBE-231: Read from and write to USB configuration registers
+DERMBE-233: [RMB] Update DMUB soft reset register
+FEAT-33357: [NV21] [tOS] Trigger SMU to exit GFX-OFF before validating L0 and GFX_ON RAP validation
+
+fTPM
+-----
+PLAT-65009 RN: FTPM wait for PSP Storage update completion before responding to TPM2_Shutdown
+
+DRTM
+-----
+N/A
+
+Release Version 0.11.0.59
+-----------------------------------
+Bootloader
+----------------
+LAT-67069: Fix MP0_OVERRIDE Register Definition Overlapping Issue
+PLAT-66608: [RN] RPMC Enalbe Fail on SPI ROM
+PLAT-60843: Add back the build change to sort linked files
+PLAT-63504: [BOOTLOADER] Move PSP DRAM mapping after it is ready
+PLAT-65714: [RPMC] Fix Root/HMAC Key Update Fail Issue
+
+Trusted OS
+----------------
+PLAT-66652: Load MFD from secure DRAM region
+SWDEV-244097:MI200 Update MAX_HD_LINK macro to support 128 link records
+FEAT-33002: [Navi21],bug fixes for boot config feature
+PLAT-67136: Set Recovery flag when booting from partition B
+SWDEV-245982: fix TOS to return the error code during PDFW update sequence
+PLAT-67012: [RMB] Update PSP only registers saved to MP2 SRAM
+PLAT-60183: [RMB] Power gate CCP when MP0 is idle
+PLAT-66136: [RMB] Add Z-state CCP register Save/Restore
+SWDEV-245706 Remove vfgate auto-disable.
+SWDEV-245704 Check CAP-loaded for all gest FW, including ones not in DFC.
+SWDEV-245702 Stop clearing DFC immediately after it is loaded.
+SWDEV-245701 Clear driver CAP binary for VF on VFGATE_ENABLE.
+SWDEV-245699 Go back to using known-working MMHUB mapping function for DFC TMR.
+SWDEV-245696 Fix setting of DFC-loaded flag for host-guest compatibility.
+FEAT-33004: [NAVI21], support new GFX command to get set or invalidate
+PLAT-66608: [RN] RPMC Enalbe Fail on SPI ROM
+PLAT-66968: Trigger recovery in TOS when FAR enforcement fails loading modules
+PLAT-66841: [RMB] Change MSMU instance used for MSMU save/restore
+SWDEV-244739: [MI200] [tOS] Bug fix for searching into hashtable for whitelisted registers
+RTGPLAT-4013: Navi21: Fix SMU timeout issue if main PMFW is not loaded
+RTGPLAT-4013: Fix TMR address issue while updating USBPD update
+RTGPLAT-4941: [RMB] Change MSMU scratch regs used for RLC info
+PLAT-66133: Fix virtual address mapping in MSMU dRAM save
+PLAT-60843: Add back the build change to sort linked files
+SWDEV-244739: [MI200][tOS] Implement DrvSys RAS whitelist register access API Functions
+SWDEV-245308: use feature specific build options in VGH / RMB
+PLAT-65447: [RMB] Expand VCN TMR in PSP
+DERMBE-206: Add check if RLC TOC is loaded before use
+FEAT-33004: remove obsolete function.
+SWDEV-242749: Fix for firmware coding standard (2)
+FEAT-33001: Temporary commenting out SPI init until integration testing
+SWDEV-244420:[Navi23] Use the right number of UMC channels
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+PLAT-66955: DRTM TA SPL value injection via TA property
+PLAT-66830: DRTM TA minor code enhancement(debug/production version differentiation, error code optimization, address assignment optimization)
+
+
+Release Version 0.11.0.58
+-----------------------------------
+Bootloader
+----------------
+SWDEV-243209: [NV21] Load Boot Config data in PSP BL
+
+Trusted OS
+----------------
+FEAT-33001: Update SPI controller interface
+SWDEV-233192: gAsicType = ASIC_VGH breaks GFX HMD
+SWDEV-244681: [Mi200] Support for UMC GPU Fence register modifications
+PLAT-61278: [VN] [HSP] PCR Measurements in tOS
+PLAT-66342: [CZN] Wireless Manageability should not be enabled on non-pro SoCs
+[RELEASE][Navi12][SRIOV] Release Version 00.18.00.56
+SWDEV-241899: Generalize Hashtable Interface, Improve Internals & Map WL entries to WL-Hashtable
+PLAT-66446: Enable_PRO_Check for FW to check and control L3 security feature
+FEAT-33001: Read SPI FW through SMU IO interface
+SWDEV-232438: Update TOS SDU for MI200 MP1 unlock
+[RELEASE][MI200] Release version 00.27.00.58
+SWDEV-242889: [NV21] Add further validation to driver TMR region creation
+DERMBE-165: [RMB] Update GFX TOC FW IDs
+SWDEV-243799: MI200 - Disable sharing of Topology for XGMI DPM
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.57
+-----------------------------------
+** SPL table version 5.11.0.56 is included
+
+Bootloader
+----------------
+PLAT-65714: RPMC separate status and response
+
+Trusted OS
+----------------
+SWDEV-243807 Add DFC case to ResetIpFw().
+PLAT-66297 Corrupted the entry 0x44/0x58/0x59 can't enter recovery mode
+SWDEV-243808 Fix DRV_CAP alignment, must be 16 for CCP copy.
+SWDEV-211109: [Mi200] Handle Sync Flood exeption as a result of DF Freeze
+SWDEV-243799:MI200 Enabled loading and reloading of PMFW
+SWDEV-228638: AMDSPI OS driver caused DRTM Failure in OS
+PLAT-66135: Move Z9 entry message ack to start of handler
+SWDEV-242868: [Mi200] Get RAS error inj permission from either mbx or GPIO
+SWDEV-243591:[Navi22] Fix build flag for VCN1 TMR set up
+SWDEV-240041: Removed typedefs due to coverity defects
+RTGPLAT-4852: Navi22 Non-production enablement Navi22
+PLAT-65823: FAR/SPL state check feature of DRTM Sequence
+RTGPLAT-4852:[Navi22], fix number of TMZ index/data
+RTGPLAT-4013: Navi21: Fix SMU timeout issue if main PMFW is not loaded
+SWDEV-236998: Navi21: fix BSOD issue when copying FW from System memory to LFB
+SWDEV-211107: [Mi200] Support mode1 reset
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+SWDEV-237329: [Navi 1x, 2x]: psp_os: Enable profiling for TOS
+SWDEV-237329: [NAVI 1x, 2x]: psp_os: Add capability to profile TOS
+SWDEV-241899: [MI200][tOS] Init register access whitelist binary
+SWDEV-242924: [NV21] Enable STB support in TOS
+
+fTPM
+-----
+N/A
+
+DRTM
+-----
+PLAT-65823: FAR/SPL state check feature of DRTM Sequence
+PLAT-64523: SMM Supervisor Production Key & SPL Enforcement
+
+Release Version 0.11.0.56
+-----------------------------------
+Cancelled
+
+Release Version 0.11.0.55
+-----------------------------------
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+RTGPLAT-4780:[Navi2x] Correcting the COMMON_COMPILE_TIME_ASSERT on FW ID table
+SWCSD-1364: Fix issues reported by legal scan's tool
+RTGPLAT-4780:[Navi2x] Add the missing FW ID table entry
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+PLAT-63640: [RMB][HSP] Add PCR measurements in TOS
+
+fTPM
+-----
+PLAT-65812 RN: Fix for TPM vulnerability--non-orderly shutdown-failedTries
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.54
+-----------------------------------
+Bootloader
+----------------
+PLAT-64168: ROM-Armor ver2 for client - phase4
+PLAT-63653 Properly serialize SPI commands
+
+Trusted OS
+----------------
+PLAT-62057: Revert change in SaveMSMUdram
+SWDEV-241508 Changed FW clear command to use actual FW size.
+PLAT-65659: Access SECIP13 through SMN in kernel suspend
+SWDEV-206580: Encrypted FW - use feature specific flags
+SWDEV-241482: Add asic specific build option file
+PLAT-62057: [RMB] Save MSMU dRAM contents on S0i3 entry
+DERMBE-134: [RMB] Update MMHUB FID from 0x6 to 0x9
+SWDEV-214033: TOCTOU in validation of GPU IP firmware enables loading unvalidated image data
+PLAT-63431: Return SPL fuse value on query command from BIOS
+SWDEV-241863: Fix compilation warning in SYS DRV for non-dGPU targets
+PLAT-64921: [RMB] added new line to rmb_hw_regs.h
+PLAT-64921: [RMB] Update register defines to LSD CL 1269420
+SWDEV-241654: Revert non-volatile register types
+SWDEV-241046: [MI200][tOS] Load register access whitelist binary
+DERMBE-134: [RMB] Increase define for MAX_SDMA_FW_SIZE to 8320 DWORDs
+DERMBE-134: [RMB] Update MMHUB FID from 0x6 to 0x9
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.53 (Not promoted)
+-----------------------------------
+Bootloader
+----------------
+PLAT-60317 : SUT not boot with ROM XM25QU128BH
+PLAT-63845: [RN] Use RPMC fuse and BIOS command as condition to program RPMC Prod Root Key
+PLAT-59100:[BOOTLOADER]fixed the compiling warning of type case
+
+Trusted OS
+----------------
+TGPLAT-4707:[Navi23] Correct the MMHUB FID
+RTGPLAT-4642: Navi22: Enable VCN1 in Trusted OS
+PLAT-62746: Log agesa driver load status
+SWLSD-12: Address concern of privilege escalation from Driver to tOS or DrvSys.
+SWDEV-240325: [Mi200][RAS TA] Add RAS TA permission list based on KeyID
+SWDEV-240041: Added in-line suppression for discussed errors
+FEAT-32964: Send max number of VFs to TAs.
+FEAT-32965: Adding new GFX command to get number of VFs from GIM driver
+FEAT-32969: CLean up TA session context for specific Vfid:
+SWDEV-232312 TOS saves CCXSEC MSMU dRAM to PSP private memory
+FEAT-32964: Increasing MAX TA session from 16 to 32:
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.52 (Not promoted)
+-----------------------------------
+Bootloader
+----------------
+PLAT-64900: [BUILD] Revert "Make build identical on different environments"
+PLAT-63500: [RPMC]Add BIT9 in HSTI to specify if RPMC SPI-ROM is avilable
+PLAT-63843: [RN] RPMC Root Key provisioning at Manufacture
+PLAT-60256: Fix SPL value fuse issue identified from FAR testing on Renoir
+
+Trusted OS
+----------------
+PLAT-64900: [BUILD] Revert "Make build identical on different environments"
+PLAT-63500: [RPMC]Add BIT9 in HSTI to specify if RPMC SPI-ROM is avilable
+SWDEV-231923: Store HSP data when PSP enters to S0i3
+PLAT-63843: [RN] RPMC Root Key provisioning at Manufacture
+SWDEV-206580: Encrypted FW - use iKEK/tKEK in CCP LSB slot 4
+PLAT-64785: [RMB] Re-enable interrupts on z-state exit
+FEAT-32799: [Navi21] [tOS] Validate duplicated RAP registers across subsections
+PLAT-64769: [RMB] Move BL2TOS mailbox SRAM location
+SWDEV-240041: 7 Coverity Defect Fixes
+PLAT-64836: "Change HDP flush register and add poll for completion"
+FEAT-31759: [Navi21][tOS]Combine GC_INTERNAL_INDEX_DATA_PAIRS_SRIOV RAP w/ GC_INTERNAL_SRIOV RAP
+PLAT-60256: Fix SPL value fuse issue identified from FAR testing on Renoir
+PLAT-58012: Improve PSP's traces in smart trace buffer
+PLAT-61976: [RMB] Restore VCN DPG RAM on Z9 VPB exit
+SWDEV-239307: [NV21] Ensure SMU FW is loaded before sending GFXOFF disable/enable commands in debug unlock sequence
+PLAT-63772: [RMB] Remove accesses to B0 RSMUs
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.51
+-----------------------------------
+Bootloader
+----------------
+PLAT-55947 : [RN_FP6] SUT not boot after set to Quad mode with ROM GD25LQ128D
+PLAT-59100[BOOTLOADER]loads either MP2-SFH or MP2-I2C based on AMD PBS option
+PLAT-61455: [BOOTLOADER] Trigger recovery when BIOS FW fails to load
+
+Trusted OS
+----------------
+PLAT-64900: [BUILD] Revert "Make build identical on different environments"
+PLAT-63500: [RPMC]Add BIT9 in HSTI to specify if RPMC SPI-ROM is avilable
+SWDEV-231923: Store HSP data when PSP enters to S0i3
+PLAT-63843: [RN] RPMC Root Key provisioning at Manufacture
+SWDEV-206580: Encrypted FW - use iKEK/tKEK in CCP LSB slot 4
+PLAT-64785: [RMB] Re-enable interrupts on z-state exit
+FEAT-32799: [Navi21] [tOS] Validate duplicated RAP registers across subsections
+PLAT-64769: [RMB] Move BL2TOS mailbox SRAM location
+SWDEV-240041: 7 Coverity Defect Fixes
+PLAT-64038 : Remove bad words from release notes
+[RELEASE]: [Navi 10, 14]: PSPFW Release Version 00.1x.00.55
+PLAT-64836: "Change HDP flush register and add poll for completion"
+FEAT-31759: [Navi21][tOS]Combine GC_INTERNAL_INDEX_DATA_PAIRS_SRIOV RAP w/ GC_INTERNAL_SRIOV RAP
+PLAT-60256: Fix SPL value fuse issue identified from FAR testing on Renoir
+PLAT-58012: Improve PSP's traces in smart trace buffer
+SWDEV-239359: [RELEASE] [Navi21] PSP TOS FW release version 00.21.00.51
+PLAT-61976: [RMB] Restore VCN DPG RAM on Z9 VPB exit
+SWDEV-239307: [NV21] Ensure SMU FW is loaded before sending GFXOFF disable/enable commands in debug unlock sequence
+PLAT-63772: [RMB] Remove accesses to B0 RSMUs
+
+
+Trusted OS
+----------------
+PLAT-64168: ROM-Armor ver2 for client - phase3
+RTGPLAT-4197: Disable GFXOFF before starting debug unlock
+PLAT-64417: [VN] ISP FW memory size reduction
+RTGPLAT-4250: [Navi2x] Handle DF C-state change via PMFW
+RTGPLAT-4301: [MMSCH], MMSCH init for VCN1
+FEAT-32200: [Navi21] [tOS] [RAP] Validate index-data pair RAP
+PLAT-64168: ROM-Armor ver2 for client - phase2
+PLAT-64168: ROM-Armor ver2 for client - phase1
+PLAT-64279 RN: Remove unused API DRV_SYS_CMD_ID_PRIV_SMI_SPI_READ_MC and the associated functions
+PLAT-64248: [MVG] A bug in the Gfx-10 HW IP TAP_DELAYS & SE0_TAP_DELAYS mapping
+SWDEV-237043:MI200 - Updated the SDMA FW destination size
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.50
+-----------------------------------
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+PLAT-63773: [RMB] Add RSMUs for CCX, DF, and UMC MSMUs to config
+PLAT-63847: [RMB] Correct the MP0 unit ID bit positions in mmHUB TLB2 register
+SWDEV-237624: TL print additional check
+RTGPLAT-4500: fix Navi22 DrvSys build issue
+SWDEV-237788 VFGATE: clear pending VF interrupt flag before interrupt re-enable.
+PLAT-63481 VGH: Create Thread to Parse HSP Shared buffer contend
+SWCSD-1364: Fix issues reported by legal scan's tool
+PLAT-63629: Vangogh: Add support for SMU message to trigger RLC AutoLoad and RLC enablement
+PLAT-63601: Update MP0_DFP_PGRAM_CPU_CNTL__PGFSM_MEM_SDDS* reg shift and mask definitions
+SWLSD-12: Additional validation of pointers in kernel syscalls.
+RTGPLAT-4105: Add missing header defines for MI-200/NV21
+PLAT-61278: [VN] [HSP] PCR Measurements in tOS
+RTGPLAT-4105: [Navi21] Add node ID to TMR fid
+SWDEV-226358: Enable logging in TL in TOS
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.4F
+-----------------------------------
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+SWDEV-237050 Have NV12 change DF C-State directly as is done in NV10/NV14
+PLAT-58331 verify singanture and add TMR protection to DMCUB
+PLAT-63779: [VN] MMHUB spec AxUSER definition changed causes bad TMR mapping
+SWCSD-1364: Fix Knoll code's license issue
+PLAT-63635: Fix enforcing security policy on non-secure parts
+Revert "PLAT-61974: [RMB] Skip switching DPM states in TOS"
+SWDEV-235126: Do not fail the CVIP load query command.
+SWDEV-229327: HDMI Certification HDCP 1.4 1A-08 item - Error
+RTGPLAT-3982:[Navi2x] Add FW ID fields for Navi2x in header file
+FEAT-30987: [Navi 21] bug fix for AC timing table
+PLAT-63104: [RMB] Update Register Header
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+PLAT-63484: Add support for version number display in BVM
+
+Release Version 0.11.0.4E
+-----------------------------------
+Bootloader
+----------------
+PLAT-61966: [RN] Update PSP_BL_AMD_TEE_SHAREDDATA RpmcErrorCode Field
+PLAT-61258: [BL][CZN]Verify CS-SEED fusing
+PLAT-63450: [BOOTLOADER] Correcting CS-Seed test vector
+SWDEV-220087: Fix Coverity issue - unused value
+
+Trusted OS
+----------------
+PLAT-63362, PLAT-63361, PLAT-61707: Add CZN CS-SEED based keys (Promontory, Knoll)
+PLAT-61966: [RN] Update PSP_BL_AMD_TEE_SHAREDDATA RpmcErrorCode Field
+PLAT-60172: [RMB] Re-enable TMR, IOMMU, and Security Policy support for HSP-fTPM
+SWDEV-230041 [Navi12][PSP] New command to clear up FW in TOC/TMR when VF driver gets unloaded
+PLAT-60967: Re-enable RPMCSetConfiguration
+PLAT-61278: [VN] [HSP] PCR Measurements in tOS
+PLAT-63107: [VN] Save/Restore FMR registers in/from MP2 SRAM through S0i3
+RTGPLAT-4253: Navi 1x: Check PGFSM power status before doing forced bank display
+RTGPLAT-4253: Navi 1x: Add registers required for PG status checking
+PLAT-62175: Prohibit to MMIO access 0xFED80D00-0xFED80DFF due to FCH security policy
+SWDEV-235366: [NV12] VF Gating causes intermittent PSP hang
+FEAT-30990: [Navi21], adding more permission for PPLIB TA
+FEAT-31759: [Navi21][tOS][RAP] Validate 1VF L1 Policy
+RTGPLAT-4316:[Navi2X] TMZ sequence for navi21 during GFX OFF exit
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+
+Release Version 0.11.0.4D
+-----------------------------------
+Bootloader
+----------------
+PLAT-60733: [RN] Initialize PSB fusing values from BIOS key token
+PLAT-61856: Adapt new design for bios cmd for storage health
+
+Trusted OS
+----------------
+RTGPLAT-4140: NV21- Replace Blank SRAM with TRNG for CCP clear
+PLAT-60733: [RN] Initialize PSB fusing values from BIOS key token
+SWDEV-234631:Trace log in TOS, call to integrate lib restore function
+PLAT-61856: Adapt new design for bios cmd for storage health
+SWDEV-230737 - Re-synchronize the PSP GFX Interface between PSP FW and GFX driver in swPSP
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+PLAT-62192: [VN] Expand TMR for VCN FW to 2MB and set separate TMR for VCN data
+SWLSD-6 Pass VfGate pResp pointer inside of Buf[] array.
+RTGPLAT-4128:[Navi23] Add Navi23 register headers and enable compilation
+SWDEV-234173:MI100 - Apply changes for one VF mode
+PLAT-63056: Add validation of parameters in kernel and DrvSys functions.
+SWDEV-226358: Trace log in TOS: calling tl_print_s
+SWLSD-6: Add validation of pDomain pointer for ECC point multiplication.
+SWLSD-11, SWLSD-9: Fix address validation in DrvSys.
+SWDEV-226306: TL 2.0, dump CLB in DRB
+SWLSD-8: Fix issue in tOS where Drivers from inferior Trust Level can access System Driver stack.
+SWDEV-226359: MP0 TRACE LOG, HDT command handler
+PLAT-62185 VGH: Add functions for DRV_SYS_CMD_ID_MAP_SMN and DRV_SYS_CMD_ID_UNMAP_SMN
+SWDEV-226754: Navi 1x: Indicate VBL to skip USB init in Mode 1 reset
+
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.4C
+-----------------------------------
+BootLoader
+----------------
+PLAT-57221: [BOOTLOADER] Fix incorrect FwType in recovery BL
+PLAT-61634: Enforce specific fw types validated by TOS
+PLAT-62262: [BOOTLOADER] Add CZN signing
+PLAT-62277: [BOOTLOADER] Support Cezanne bootrom layout
+
+Trusted OS
+----------------
+PLAT-61634: Enforce specific fw types validated by TOS
+FEAT-30991: [Navi21]Uncommenting permission bit for PPLIB TA permission check
+FEAT-30992: [Navi21]: Adding new permission check for PPLIB SVC
+FEAT-30991: Navi21: Adding new key ID for new PPLIB key
+FEAT-31759: [Navi21]: [tOS][RAP] Apply 1VF L1 policy.
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+SWLSD-5: Fix fTPM issue introduced by bug in parameter cheks.
+MERO-19 Add support for new Crypto Algorithms supported in CCP 12.0
+PLAT-60553: Adds kernel API for tOS to enter into debug mode
+PLAT-56608: Workaround for BSOD A006 issue
+SWLSD-13: [Kernel] Restrict Svc_CreateUserThread() to System process.
+SWDEV-228332: Enable CVIP security policy
+SWDEV-220638: SWDEV-220798: Set GC AEB[56] = 1
+SWDEV-226901: Navi21: Read VCN counters from VCN1's cache1 location
+RTGPLAT-4244: Revert "PLAT-58139:[Navi2x] Support DF Cstate toggle via PMFW"
+
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.4B
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+SWDEV-230950: [VGH] Pass HSP measurement to TOS
+SWLSD-12: Add validation of pointers in kernel syscalls
+SWDEV-232689: Access violation reading CVIP carveout address
+PLAT-57481: Add Initial Z-state support
+PLAT-60437: [RMB] Remove unneeded RSMU ID from config
+PLAT-60505: PSP FW changes for GFX FLR
+PLAT-61974: [RMB] Skip switching DPM states in TOS
+FEAT-30987: [NV21] AC timing table, UMC reg read write
+RTGPLAT-4010: [Navi2x] Clear asynchronous abort condition without handling the abort
+PLAT-58139: [Navi2x] Support DF Cstate toggle via PMFW
+PLAT-61981: VG EMU SECUREGFXOFF MP0 Write to TMR causes SyncFlood
+SWLSD-5: Fix S0i3 issue introduced by kernel parameter checks
+SWDEV-233192: gAsicType = ASIC_VGH breaks GFX HMD driver
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.4A
+-----------------------------------
+*DRTM TA updated to version 04.11.00.13
+
+Bootloader
+----------------
+PLAT-61003 Use ADS bit to locate SPI ROM specific UID
+
+Trusted OS
+----------------
+PLAT-61843: [TOS] Add back support in PROM B550A
+FEAT-30986: [Navi21]: AC Timing Table: copy AC table from TMR to TA
+SWLSD-5: Add more address checks in tOS kernel.
+PLAT-61322: Update security violation logging implementation
+SWLSD-4: Fix possible TOCTOU issues in DrvSys interface.
+PLAT-61412: Fix TOS initial DPM value
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+Add STB (Smart Trace Buffer) support in DRTM TA
+
+Release Version 0.11.0.49
+-----------------------------------
+Bootloader
+----------------
+PLAT-60967: Enable RPMC feature
+PLAT-59673[DRTM]Feature disable with PSP-fTPM
+PLAT-61266: [RN] Add option for BIOS to control RPMC
+PLAT-61512: MP0 hard hang with status 80060000
+PLAT-59883 : [RN] Add support for SPI ROMs that without enable QE in default.
+PLAT-61517: [BL] Refactor headers and version management
+
+Trusted OS
+----------------
+PLAT-59673[DRTM]Feature disable with PSP-fTPM
+SWDEV-230017:MI200-Migration to LSD model
+SWDEV-227728: [NV21] Apply ENTRY_TYPE_POLICY_GC_INTERNAL_INDEX_DATA_PAIR_SROIV security policy
+PLAT-61511: [VGH] [tOS] Fix RLC TMR base address loaded to the RLC BootLoad Address h/w registers
+PLAT-56608: Workaround for BSOD A006 issue
+PLAT-60780: [RMB] Remove support for TMR, IOMMU, and DRTM sec policy
+PLAT-60780[VN]Revisit TMR, IOMMU, Security policy for VN/HSP-fTPM
+PLAT-61179: BSOD 0xEA occurred when running reboot
+SWDEV-211101: MI200 TOS 4k Secure debug unlock support
+RTGPLAT-3918: [RMB] Load MSMU Scratch Registers with RLC bootloader address/size
+PLAT-61452: [RMB] Set asic type value
+PLAT-61378: VG - Mismatch between PSPFW and PMFW loading USB PHY for USB1/2 instances
+PLAT-58627[VN]-Add a new RevID for PRO part checking
+PLAT-61154 VGH: PLAT-61155 VGH, Add function in sys_drv for DRV_SYS_CMD_ID_PRIV_GET_TPM_CONFIG and DRV_SYS_CMD_ID_PRIV_GET_DOORBELL_EVENT_HANDLE
+FEAT-30985: [Navi21]: Share the TMR address of AC timing table with TOS
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+PLAT-61139 Skip CCX1/WLAN for secure policy
+RTGPLAT-3852: [NAVI 1x]: drv_sys: Fix TOC TMR boundry TOC id based on latest TOC design
+SWDEV-228334: Release the CVIP HW from reset.
+SWDEV-231110: Remove CVIP FW load test code.
+SWDEV-228317: Return actual CVIP Key usage flag.
+RTGPLAT-4056: Navi22: Add register headers for Navi22
+
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.48
+-----------------------------------
+*DRTM update to 4.11.0.12
+*fTPM update to 3.42.0.5
+
+Bootloader
+----------------
+PLAT-60919: PSP incorrectly to clean status on FCH::PM::S5_RESET_STATUS register.
+PLAT-60451: Skip MMHUB enablement with iGPU disabled
+
+Trusted OS
+----------------
+SWDEV-227305: Updating release TMR flag when sending USB PD FW via I2C
+PLAT-61264 Remove SKINIT SLB DMA Protection after DRTM launch
+SWDEV-228334: Release the CVIP HW from reset.
+SWDEV-221737: [SRIOV] [NV12] [AWS] Add support for host compatibility and guest capability features.
+SWDEV-229688: MP0 trace log,updating TL init to match TL lib
+SWDEV-229408: Ignore Coverity parse error on mailbox_blbros.h
+SWDEV-230347: addressing warnings for Disabling UUID search in DLM printf
+PLAT-56326: Manage 16MB DRAM space for HSP, DRTM and SKINIT
+PLAT-60891: AEB_BLOCK_UPDATE bit has to be clear before unlock MP2
+SWDEV-230347: Disable UUID search in DLM print if MP0 Trace Log is disabled
+SWDEV-228324: Develop TOS handler for the SMU_PSP_CVIP_POWER_ON message
+SWDEV-228335: Complete the CVIP Firmware Load Status Polling API
+
+fTPM
+-----
+Modify FTPM Makefile to add FW version and type in PSP Fw Header and to correct the Signing function used for RV
+
+DRTM
+-----
+PLAT-61264: Remove SLB DMA protection after DRTM Launch to help DRTM Stability issue.
+
+
+Release Version 0.11.0.47
+-----------------------------------
+
+Bootloader
+----------------
+[PLAT-60385] Fix Hard-Coded Index in UMC
+
+Trusted OS
+----------------
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+PLAT-58717: Disable mp0 power gating feature
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+LWPQA-204: Add key tokens for mi200 pre-si signing
+SWDEV-228324: Develop TOS handler for the SMU_PSP_CVIP_POWER_ON message
+PLAT-60953: [RMB] Update registers for PPR 0.14
+SWDEV-228833: GFX10 SR-IOV: Add MEC ucode version to CP address space
+[RELEASE] [NAVI 10] PSPFW Release Version 00.10.00.47
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+SWDEV-227677: Modify tOS kernel reset sequence to allow DRAM to be not one-to-one mapped.
+SWDEV-226303: MP0 Trace Log: Adding link to tl_lib for NV21
+SWDEV-229688: MP0 Trace Log: calling TL init-deinit in drv sys
+PLAT-60960: Expose API for putting trace in smart-trace buffer
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+N/A
+
+
+Release Version 0.11.0.46
+-----------------------------------
+* L0 Security policy is updated to B.9.0.75
+* L1 Security policy is updated to B.9.1.75
+* DRTM is updated to 4.11.0.11
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-60842 Remap entire SRAM before jump to TOS
+PLAT-60843: [BUILD] Make build identical on different OS
+
+Trusted OS
+----------------
+PLAT-60843: [BUILD] Make build identical on different OS
+PLAT-58942 SMM Isolation Support
+[PLAT-58508]Update structure SUSPEND_DRAM
+PLAT-60695: [TOS] Remove support for PROM/PROM LP
+PLAT-60855: [TOS] Add APOB/APCB signing/validation service (WIP)
+PLAT-59472 - [RMB] TOS Initialization (Phase-1)
+[PLAT-58508]Update structure UMC_STATE_INFO with macro UMCCH_MAX_NUM
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+PLAT-54423: Enforce ROM-Armor policy on S3/S0i3 resumes
+SWDEV-226356: MP0 Trace Log: Reading Source ID from UUID
+[SWDEV-228330] TOS CVIP Carveout Use Preparation
+[SWDEV-228327] CVIP SRAM Initialization - Crack the CVIP FW Image
+SWDEV-228377:MI200-TOS: RSMU MMIO Start address modified
+SWDEV-228315: Shift new TLB value for SMNv13 support 8-bits hops count in SMN TLB
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+PLAT-58942 SMM Isolation Support.
+
+
+Release Version 0.11.0.45
+-----------------------------------
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+Revert "SWDEV-227677: Modify tOS kernel reset sequence to allow DRAM to be not one-to-one mapped."
+SWDEV-226306: Trace Log in TOS - support copy of CLB to DRB
+SWDEV-228329: MP0 Trace Log: Adding verbosity level to Drv_Sys DLM print
+[SWDEV-228781] Structure for HSP messages should be packed
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+PLAT-59467: Report ACPI device in IVRS table during DRTM boot
+
+Release Version 0.11.0.44 (Rejected)
+-----------------------------------
+
+Bootloader
+----------------
+[PLAT-58508]Update UMC Configuration
+[BOOTLOADER]PLAT-60374 Add the Error logging when triggered the recovery mode
+[BOOTLOADER]PLAT-59782 Pass TPM selection info from BIOS -> ABL -> PSP
+
+Trusted OS
+----------------
+SWDEV-216591: Secure BIO - ISP FW authentication and loading
+SWDEV-225191: enable External aborts for Navi 1x platform
+SWDEV-227305: Updating release TMR flag when sending USB PD FW via I2C
+[SWDEV-221391] Pass the CVIP carveout from BL to tOS
+RTGPLAT-3917: [MVG] PSP needs to load MSMU scratch registers with RLC bootloader address/size
+SWDEV-227728: Populate only mismatch information in RAP output_param.
+PLAT-60547: [VGH/VN] [tOS] Modification of the TMR physical address conversion from the GPU virtuall address
+SWDEV-227437:MI200-TOS: Enable MMHUB initialization for MI200
+SWDEV-227677: Modify tOS kernel reset sequence to allow DRAM to be not one-to-one mapped.
+RTGPLAT-2717: clear external aborts on Navi 1x
+[TOS] PLAT-60379: Storage thread to use kernel event
+PLAT-59467: Report ACPI device in IVRS table during DRTM boot.
+RTGPLAT-3851: XGMI: Ensure that current Die is not Node Fenced on Mem Sharing Disable
+FEAT-30961 [Vega10][SRIOV][Azure] Report last-attempted driver version in VF_GATE status response.
+PLAT-60471: [VGH/VN] bug in RSMU ID definitions
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.43
+-----------------------------------
+
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+PLAT-60371: S4 suspend fails after S0i3 resume
+PLAT-58150: [VMR]: RAS: Handle TWIX errors in Trusted OS
+PLAT-58154: [VMR]: RAS: MBAT Re-init for power gated NBIO/PCIe instances
+[TOS] PLAT-58798: Allow MP2 FW to write to PSP storage
+[SWDEV-206589] support for IP FW loading
+FEAT-29971: retiring MPV unlock and xgmi reg list for non prod mode
+SWCSD-1364: Legal scan for Renior release to customer
+PLAT-57915, PLAT-57917: Fix tOS kernel issue that migh cause race conditions between threads.
+[SWDEV-206589] [tOS] Support for IP FW loading
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.42
+-----------------------------------
+* PLAT-59351 Update CCP HAL library for new SHA engine
+
+Bootloader
+----------------
+N/A
+
+Trusted OS
+----------------
+PLAT-59983 - Avoid DRTM TMR setup range check with SMM TSEG region
+FEAT-30956:[Navi2x] Remove APCC register save/restore from PSP
+[PLAT-58736] Rev Header version in Headers for TOS and DRVSYS
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.41
+-----------------------------------
+
+Bootloader
+----------------
+PLAT-59615 Fix Index out of Bound Issue in RPMC
+[PLAT-58736] Update offset of FwType field in PSP signing header
+[PLAT-59075] Add test mode for anti rollback feature
+
+Trusted OS
+----------------
+[TOS] PLAT-57225: Disabling late DF security policy
+PLAT-58665: System hangs when resuming from S0i3, when VBS enabled
+[TOS] PLAT-57939: Fix Crossfire enablement
+FEAT-30095: non prod TA Key ID
+RTGPLAT-3763: PSP should respond to RESET command from PMFW
+PLAT-56411: Enable enforcing of DF & FCH security-policies
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.40
+-----------------------------------
+* L0 Security policy is updated to B.9.0.74
+* L1 Security policy is updated to B.9.1.74
+* DRTM is updated to 4.11.0.F
+
+Bootloader
+----------------
+PLAT-58094 Provision RPMC with temporary root key
+[BOOTLOADER]PLAT-59185[RN] BIOS in ROM2 32M support (case 4)
+[BOOTLOADER] Remove unnecessary header include
+SWCSD-1364: Legal scan for Renoir release to customer
+
+Trusted OS
+----------------
+SWDEV-222509:[Navi2x] Update the DMCUB sequence as per DMCUB_design_spec
+RTGPLAT-3688:[Navi2x] Save the APCC tuning register values for later restore
+SWDEV-221891: [TOS] Handle command GFX_CMD_ID_SAVE_RESTORE for GFX_FW_TYPE_VCN1
+SWDEV-219157 - MI100 TMR: mGPU Address Calculation and FabricID Update
+SWDEV-224787: Use of pCmd in CVIP Load Thread crashes the code.
+RTGPLAT-3571: Navi21: Remove size check for VCN RAM firmware
+RTGPLAT-3522: Navi21: Move DRAM accesses before reset by SMU
+PSP-2626: Updating PSP 10 Secure OS.
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+PLAT-58191- IOMMU hand-off / configuration deficiencies during DRTM Secure Launch + DMAr disabled fix
+
+
+Release Version 0.11.0.3F
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-59196: Remove programming of GPIO21/22
+[BOOTLOADER] PLAT-56684 Decrease Key DB SRAM region size
+[BOOTLOADER] PLAT-57929 Fix FRA-unlock issue
+[BOOTLOADER] PLAT-58708 - Program SPI mode and speed in A/B recovery
+[BOOTLOADER] PLAT-58456 - [RN] Load VBL in recovery mode
+[BOOTLOADER] PLAT-56658 Prevent address from returning as error from syscall
+
+Trusted OS
+----------------
+RTGPLAT-3565: The TMR region setup return status must be validated
+PLAT-58798: Add Mp2-to-PSP mailbox
+[TOS] PLAT-58567: Add Support for CS2019.B Promontory
+PLAT-59025: Release other TMRs before MP0 TMR in DestroyTmr()
+PLAT-58996: [VGH] [tOS] Update conversion virtual-2-physical addresses base registers for TMR
+FEAT-30093: Navi21: Implement non production APIs
+PLAT-58996: [VGH] [tOS] Update conversion virtual-2-physical addresses base registers for TMR
+RTGPLAT-3597: Navi1x: Fix ROS0 toc size to align to 64KB
+PLAT-58991: Allow BIOS cmds without parameters
+RTGPLAT-3597: Navi1x/2x: Align the size of RWS section to 64KB
+RTGPLAT-3597: Navi: Fix TOC TMR boundry TOC id based on latest TOC design
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.3E
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-58787: Stagi1 BL - System can't resume from S0i3 on 32MB BIOS
+[BOOTLOADER] PLAT-58957: Remove PEI validation on s0i3
+[BOOTLOADER] Improve SMN single-access functions
+
+Trusted OS
+----------------
+
+FEAT-30094: NV21: update access permission for Non Production Trusted OS mode
+SWDEV-223228: [DRV_SYS] Provide finer grainer debug info to better facilitate Security Policy debugging capabilities
+RTGPLAT-3522: Navi21: Clear pending security violations before jumping to Bootrom.
+[SWDEV-223509]MI200:TOS-Update SMU-13 Public/Private CRU based on LSC+
+Revert "PLAT-58139: Navi21: Support DF Cstate toggle via PMFW in Trusted OS"
+[SWDEV-223417]MI200:TOS - Support for SDMA[0-4] FW load in TOS
+RTGPLAT-3551: [TOS] Skip SMU FW load if system exited from BACO/BAMACO
+PLAT-58744: [VRMR]: Windows restart fails with data abort
+RTGPLAT-3471: Navi21: Fix extracting of SMU command in mode1 reset sequence
+PLAT-58191- IOMMU hand-off / configuration deficiencies during DRTM Secure Launch
+FEAT-27282 [Navi12][VG10][SRIOV] MARC_0 Register programming.
+PLAT-58788: TOS: Fix the register addresses of BLOCK_CPU
+PLAT-58696: [VMR]: Fix the build warnings in the amd-tee2.0
+PLAT-58755: Update tOS build procedures in accordance with the new FWType field and values
+RTGPLAT-58427: Renoir: Added detection of major revID 0xE for DRTM feature verification
+FEAT-29979 - SR-IOV: Disable VMR for GFX 10 SR-IOV products
+SWDEV-217840: [VGH] AMD ROM Armor
+
+fTPM
+-----
+Rebuilt with updated library, no code changes.
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.3D
+-----------------------------------
+
+Bootloader
+----------------
+PLAT-58405: Workaround for PKG_TYPE lost
+
+Trusted OS
+----------------
+RTGPLAT-2776:[Navi2x] Load DMCUB to the TMR region set by PSP BL
+SWDEV-216603: Asynchronous CVIP FW loading.
+RTGPLAT-3307:[Navi2x] Clean reset of DMCUB when loaded from tOS
+SWDEV-222554: Create Cvip FW variants of PSP IP FW download functions
+SWDEV-214037: NCC: checking Process permission before accessing kernel syscalls
+PLAT-58012: Add smart-trace-buffer (aka Mp2-trace) with MP0 traces
+PLAT-54423: [RN] ROM-Armor feature
+PLAT-58139: Navi21: Support DF Cstate toggle via PMFW in Trusted OS
+PLAT-58152: [VMR]: RAS: MP1 Fatal Error Handling
+PLAT-52750: Add support for RSMU configuration for Vermeer
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+Release Version 0.11.0.3C
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-56060 Fix fusing code in PSP BL
+[BOOTLOADER] Refactor serial print function
+[BOOTLOADER] Port Coverity Dead Code Fix
+[RMB] Add ASIC Type for Rembrandt
+
+Trusted OS
+----------------
+PLAT-55003 - [amd-tee-api-lib] Update DRV_PARAMS to match the size of SYS_DRV_PARAMS
+PLAT-58429: Destroy-TMR a GFX cmd should not release all TMRs allocation
+RTGPLAT-2679: Navi21: Update mininum bootloader version for debug unlock support
+RTGPLAT-3423: Navi21: Set VCN unitid for VCPU instruction fetches
+RTGPLAT-3457: [Navi21] [TOS] Set MP1_FW_OVERRIDE.AEB_BLOCK_UPDATE upon BACO entry
+PLAT-57938 Support Recovery mode for DRTM
+SWDEV-207563 - NV21 SRIOV: VCN VF FW Loading in TMR
+RTGPLAT-3415: Navi21: Fix data type of RsmuId variable
+[TOS] MERO-441 Add support for TA to determine the caller interface (TEE vs. TEE2)
+FEAT-30115 - NV12 SRIOV: Clear GFX/MM Load Vectors during VF FLR
+PLAT-58163: [VGH] [tOS] [ BL] Adopt TMR registers h/w changes.
+SWDEV-220649:[VGH] HSP interface support
+PLAT-58163: [VGH] [tOS] [ BL] Adopt TMR registers h/w changes.
+PLAT-58163: [VGH] [tOS] [ BL] Adopt TMR registers h/w changes.
+RTGPLAT-3252: fix PnP issue on Navi 1x
+SWDEV-219857: NV21/MI100/MI200 Clear dgpu encryption keys if enabled
+SWDEV-207563 - NV12 SRIOV: VCN VF FW Loading in TMR
+SWDEV-216603: Skeleton implementation of asynchronous CVIP FW loading.
+PLAT-57655: [TOS]: [VRMR]: Enable applying of the late DF policy
+RTGPLAT-3386: Navi21: Add support for SE tap delay firmware type
+FEAT-29637: [tOS] RAP TA SVC call backs in TOS System Driver
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.3B
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] Fix stage1 bootloader build
+
+Trusted OS
+----------------
+SWDEV-216605: Add new Gfx-to-PSP API for asynchronous CVIP FW loading.
+[Mero] Fix compiler warning due to change 310284 in smu_mailbox
+
+fTPM
+-----
+NA
+
+DRTM
+-----
+NA
+
+
+Release Version 0.11.0.3A
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] Fix modulus copy buffer overrun
+[BOOTLOADER] Free LSB slots in CryptoShaFromLsb
+[BOOTLOADER]PLAT-57760: Fix boot mode detection
+[BOOTLOADER] PLAT-55651 - Remove L2 BIOS directory loading in recovery
+[BOOTLOADER] PLAT-57622 Resolving Coverity scan errors
+[BOOTLOADER] DESPCPSP-59:Add FT5 package type definition for Pollock.
+[BOOTLOADER] PLAT-56684: Remove unnecessary global buffer
+[BOOTLOADER] PLAT-56302 MP2 needs power gating on RN AM4
+[BOOTLOADER][TOS] PLAT-53198 - [RN] Skip RSMU interrupt for CLKB registers when iGPU is disabled
+[BOOTLOADER] PLAT-57229: Resolve Coverity Errors for NULL Pointer Dereferences
+
+Trusted OS
+----------------
+PLAT-58007: Integer Overflow in SMI INFO in BIOS command handler
+SWDEV-218805 - NV12 SRIOV: L1 Policy Update for 1VF Mode
+[PLAT 57915, PLAT- 57917] Add mutex logic and 2-retry on IP FW signature validation failure
+PLAT-52749: [TOS]: [VRMR]: Add support for Secure Debug Unlock for Vermeer SoC
+[Mero] Glitch attack mitigation - Cold reset message to PSP from MP1
+PLAT-57707: ACP change to not hinder SMN adjustment
+PLAT-56502 [RN] - System Reboot during DRTM sequence due to TMR violation
+SWDEV-218550: Refactor hashtable to maintain RO & RW whitelisted registers for both MGPU & SGPU in a single unified hashtable for loop-back testing
+[TOS] FEAT-29639 - Add support for Wireless Manageability
+[213882]MI200:TOS: Add support for VCN 0 and VCN 1 RAM commands for GPU PA programming
+RTGPLAT-3200: drv_sys: Palamida scan: Use standard AMD copyrights
+Add initial support for building RMB
+PLAT-57343 Renior AM4 can't power on with PT B550A(0x43D1)
+PSP-3521: Complete implementation of TA-to-TA communication.
+RTGPLAT-3284: Navi21: Add support for TOC version #6
+NV PORT of FEAT-29964 [Vega10][SRIOV][Azure] SRIOV Mailbox Gating
+[SWDEV-213847]MI200:TOS-Updated Fabric ID for MMHUB settings
+MERO-298 Add support for Keep-Alive TA property
+PSP-3521: Handle TA parameters in TA-to-TA communication.
+SWDEV-219199 - NV12 SRIOV: VMR Setup Size Verification
+[SWDEV-213847]MI200:TOS-Add support for TMR fencing
+RTGPLAT-2776:[Navi2x] Enable DMCUB firmware load from SYS DRV
+PLAT-57205: TOS: Remove firmware validation using Root key in Trusted OS
+PLAT-57202: TOS: [VRMR] Add members to AMDTEE mailbox
+PLAT-57421: [Renoir] Limiting KVM feature to Ryzen Pro OPNs
+PLAT-53905:[VRMR] Add support for Unwrapping Promontory Key
+SWDEV-215018 Support for CCP SECIP13
+SWDEV-218885: [NV21] Enable XGMI APIs for MCM builds
+PSP-3521: Handle TA parameters in TA-to-TA communication.
+SWDEV-218885: [NV21] Enable XGMI APIs for MCM builds
+SWDEV-218807 - NV12 SRIOV: Revert VDDGFX Section on Debug Unlock
+[SWDEV-218783]MI200:TOS Implement legacy RSMU AEB settings
+RTGPLAT-3213: PSP-TOS: Palamida scan: Fix files without copyrights
+RTGPLAT-3214: TOS: Palamida scan: Use standard AMD copyrights
+[PLAT-57281] Add drv_sys function to access RSA CcpModExp directly
+[TOS] Update for CCP HAL SHA changes
+PLAT-56164: Set default DPM level of all threads to low.
+
+fTPM
+-----
+Added Mutex logic to acquire and use mutex shared with system driver
+
+DRTM
+-----
+Initial production release
+
+
+Release Version 0.11.0.39
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] Fix CCP double LSB slot allocation
+[BOOTLOADER] PLAT-56090 AB Support directory addr mode 2 in stage1 BL
+[BOOTLOADER] PLAT-57038 Support new layout for PSP in ROM 1 and BIOS in ROM2
+[BOOTLOADER] PLAT-57159 System can't resume from S0i3 on 32 MB BIOS
+[BOOTLOADER] Resolve Coverity Errors - Unnecessary Headers(HFA)
+[BOOTLOADER] Remove Deadcode in InitDataScrambleKeyAllUmc
+[BOOTLOADER] Resolve Unused value Coverity Errors
+[BOOTLOADER] Use constant-time memcmp when comparing HMAC
+[BOOTLOADER] PLAT-57015 Refactor ValidateOEMPublicKey in PSP BL
+[BOOTLOADER] Fix buffer overflow in key derivation
+[BOOTLOADER]PLAT-56498: Implement reset-based legacy recovery
+[BOOTLOADER] Fix crypto cache maintenance bugs
+[BOOTLOADER] PLAT-56606: Add support for legacy compression
+[BOOTLOADER] PLAT-55776: Implement Svc_SetBixbyInfo
+[BOOTLOADER]PLAT-54956: Enable SMU paging from ABL
+
+Trusted OS
+----------------
+RTGPLAT-3155: TOS: Palamida scan: Strip out internal amd server URL
+RTGPLAT-3214: use AMD standard copyright
+PLAT-56922: PlayReady test is failing post S4 wakeup on Renoir
+PLAT-56164: Rename PlayReady APIs to HW DRM
+RTGPLAT-2179: [Navi1x]: Implement new command to read USB-PD firmware from LFB
+RTGPLAT-2179:[NV1X]: Apply TMR fence for USB-PD firmware
+RTGPLAT-1901: Navi21: Add support for PM firmware load in trusted OS
+RTGPLAT-3090: Navi21: SMNIF TLBs restore as part of mode1 reset sequence in trusted OS
+RTGPLAT-3168: Fix memory leak in Usbpd_GetFwVersion
+RTGPLAT-2179: [Navi21]: Enable USB-PD for Navi21
+FEAT-29981 [Vega10][SRIOV][Azure] Support for driver capability table (CAP). Front-door loading support and encoding
+PLAT-56741: Update failure in PSP on S0i3 resume to SMU
+RTGPLAT-2179: implement get USB PD FW version from device over I2C
+RTGPLAT-2179: Implement system call to map system memory
+RTGPLAT-2179: Use memory type in Mmhub map function
+RTGPLAT-2179: [NV1X]: Trigger USB-PD firmware update
+RTGPLAT-2179: [NV1X, NV2X]: Interface to receive command from external host tool
+RTGPLAT-2179: update the PD update sequence as per PD device vendor recomendation
+RTGPLAT-2179: Move "AsciiToDec" function to utilities.c file
+RTGPLAT-3091: Use ASIC specific definition for address of GCMC_VM_FB_LOCATION_BASE register
+SWDEV-21388 - MI-100: VCN1 TMR Offset Update
+FEAT-29972 - MI-100 SRIOV: MMSCH-PSP Communication for VCN0/VCN1 FW Loading in TMR
+PLAT-56164: Performance optimization of PlayReady transcription
+PLAT-56164: Rename PlayReady APIs to HW DRM
+RTGPLAT-2937: MI-100: Update XGMI Topology constraints for 8P
+[TOS] Fix a bug in TeeOpenPersistentObj
+SWDEV-213008: Add support for SMU13 SoC in managing SMN TLBs
+
+Release Version 0.11.0.38
+-----------------------------------
+
+Bootloader
+----------------
+[BOOTLOADER] Load iKEK from L1 directory
+
+Trusted OS
+----------------
+
+PLAT-56164: Add Playready specific SysDrv API calls.
+PLAT-56505: MP0CLK DPM Updates
+PLAT-56424: Update PSP to SMU mailbox interface in TOS
+PLAT-56500: [tOS] AMD-TEE 2.0 tOS versification
+FEAT-29976 - MI-100 SRIOV: VCN0/1 FW Loading in PF TMR for PF/VF
+PLAT-53903:[VRMR] Add support for PCIe Gen4 enable/disable
+RTGPLAT-2179: [NV1X]: Fix multi-byte read issue
+PLAT-52328 - RN - DRTM support in PSP tOS
+SWDEV-213882 : MI100: add support for VCN1 RAM programming
+FEAT-29974 - MI-100 SRIOV: TMR Fence Configuration for VCN0, VCN1, MMSCH
+RTGPLAT-2174: Navi21: Add support to load VCN firmware on VCN1 PF instance
+SWDEV-207568: Navi21: XGMI TA enhancements and topology support in GIM
+RTGPLAT-2174: Navi21: Add support for RAM1 firmware for VCN1 PF instance.
+DIAG-6427: MI-100/MI-200/Navi2x - xGMI TA to support xGMI loopback registers accesses
+[tOS] Fix tOS to BL mbox bug
+PLAT-56243: PSP FW accessing Invalid RSMU address
+
+
+Release Version 0.11.0.37
+-----------------------------------
+*rsmu_sec_policy.rn_L0.sbin reverted to version: B.9.0.4C*
+*rsmu_sec_policy.rn_L1.sbin reverted to version: B.9.1.4C*
+
+Bootloader
+----------------
+PLAT-56170 Program GC RSMU Timeout
+
+Trusted OS
+----------------
+PLAT-56175: Fix error in response to BIOS cmd
+SWDEV-195709: [tOS] Trusted OS: DRAM reserved space for MP0 Trace Buffer
+PLAT-52747: TOS: [VRMR]: Add S3 support in amd-tee2.0
+PLAT-56175 : [tOS] Fix error in response to BIOS cmd
+[TOS] RN: Enter Safe Idle mode in S0i2.X
+
+Release Version 0.11.0.36
+-----------------------------------
+*Legacy & A/B Recovery Enabled*
+*DRTM Disabled*
+PLAT-55841 - Revert Security Policy 53 to 4C
+*rsmu_sec_policy.rn_L0.sbin reverted to version: B.9.0.4C*
+*rsmu_sec_policy.rn_L1.sbin reverted to version: B.9.1.4C*
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-56065 - Disable RPMC Availability
+[BOOTLOADER] Separate debug unlock and boot loader builds
+[BOOTLOADER] Prevent reading past L1 table
+[BOOTLOADER] Add function to simplify loading RSA Key components
+[BOOTLOADER] Load soft fuse in recovery
+[BOOTLOADER] PLAT-55065 Add BUILD_APU_CPU compile flag
+
+Trusted OS
+----------------
+SWDEV-211148: Bug in TLB Address Calculation on MCM GPUs
+[TOS]PLAT-56007: New SMU message for ACP SMA DMA Completion
+PLAT-53906: TOS: [VRMR]: Fence register programming
+PLAT-55765: [tOS] Cleaning static TMR allocation.
+PLAT-54423: ROM-Armor feature implementation (phase-3)
+SWDEV-211102 - MI-200 - Add MI-200 Asic Type
+[TOS] Add BIOS CMD handler to set active partition
+[PLAT-55003] Increased size of DRV_PARAMS to match up with SYS_DRV_PARAMS
+[TOS] Update BIOS to PSP mailbox interface
+[TOS] Notify BIOS of recovery state
+FEAT-29047: [Navi21] Enable TOS support for XGMI use cases
+SWDEV-214476: MI-200 TMR MMHUB1 FID Update
+[TOS] Add definitions for A-B recovery
+[TOS] Run scheduler if interrupts are handled
+PLAT-55765: [tOS] Cleaning static TMR allocation.
+[TOS] PLAT-54301 Initialize Current Timestamp
+Address Coverity Issues for PDS Feature
+
+Release Version 0.11.0.35
+-----------------------------------
+*A/B Recovery Enabled*
+*DRTM Enabled - added dr_drtm_prod_RN.csbin version: 4.11.0.C*
+PLAT-55653 - [RN] Security Policy v53
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.53*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.53*
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-55651 - TEMP: Load L2 BIOS directory on Recovery
+[BOOTLOADER] Remove incomplete type references
+[BOOTLOADER] PLAT-53166 - Enable PSP debug print flag support
+[BOOTLOADER] Notify tOS of SBIOS Layout
+[BOOTLOADER] Recovery fixes/improvements
+[BOOTLOADER] PLAT-53665 Save/Restore spi-controller registers on S0i3 resume
+[BOOTLOADER] Add L2 directory table check
+[BOOTLOADER] Disable port80 write until initialized
+
+Trusted OS
+----------------
+PLAT-55507 - PSP to unhalt SDMA on S0i3 resume
+[TOS] Bug fix when initalizing persistent object
+PLAT-54423: ROM-Armor feature implementation (phase-2)
+SWDEV-214476: MI-100 TMR Setup - Update MMHUB Fabric ID Values
+SWDEV-209874 - MI100 SRIOV: Remove BACO Exit Check on SMU FW Loading
+PLAT-55343: PSP to not unhalt SDMA
+PSP-3515 - Address Coverity issues for tOS.
+PLAT-54423: Build fix for VRMR
+SWDEV-206584: [VGH] [tOS] Basic initialization
+PSP-3521: implement TEE calls for TA-to-TA communication.
+SWDEV-214035: MI200: compiling TOS for MI200
+RTGPLAT-2177: Navi21: Update TMR_BASE_NEXT_OFFSET
+[TOS] Implementation to save persistent object to NVRAM
+PLAT-54423: ROM-Armor feature implementation (phase-1)
+SWDEV-211148: MI200: adding hops to current smn functionality
+PLAT-55278: [RN] Bug in RSMU Security Violation logging
+PLAT-52542: TOS: [VRMR]: Support for HT/privileged address range in Secure Kernel
+PLAT-52542: TOS: [VRMR]: Enable Syshub Support
+PLAT-52471: TOS: [VRMR]: SMU-PSP and PSP-SMU message ID support
+[TOS] RN: Skip ISP RSMU interrupt enablement
+SWDEV-206584: [VGH] [tOS] Basic initialization
+RTGPLAT-2823: drv_sys: Don't enable USB D-state handling in TOS while BACO exit
+
+Release Version 0.11.0.33
+-----------------------------------
+*dr_ftpm_prod_RN.csbin updated to version: 3.27.0.5*
+PLAT-55105 - [RN] Security Policy v2D
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.2D*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.2D*
+
+Bootloader
+----------------
+[BOOTLOADER] PLAT-54920 Fix RPMC-related S3/S0i3 resume regression
+[BOOTLOADER] Trigger recovery on SVC_LoadXXX calls
+[BOOTLOADER] S0i3 disable DF C-state for DF access
+[BOOTLOADER] PLAT-55002 - Skip DRAM Checks when booting from SPI-ROM
+Revert "[BOOTLOADER] TEMP: S0i3 resume skip wait for SMU DRAM response"
+[BOOTLOADER] Enable A-B recovery
+
+Trusted OS
+----------------
+SWDEV-207560 - NV2x SRIOV: PF FLR Enablement
+MERO-20: Implementation of Persistent Objects in tOS.
+PLAT-52467: TOS: [VRMR]: Do not initialize GFX mailbox registers
+PLAT-54887: TOS: [VRMR]: Enable port 80 support for logging
+MERO-20: Implementation of Persistent Objects in tOS.
+PLAT-53209: "[CZN] MP0_C2PMSG_ATTR_1 is not programmed correctly"
+SWDEV-206584: [VGH] [tOS] Basic initialization
+PLAT-52468: TOS: [VRMR]: BIOS-PSP mailbox handling
+PLAT-52659: TOS: [VRMR]: Bootloader to Trusted Os mailbox
+PLAT-52466: TOS: [APU/CPU]: Introduce APU_CPU build flag
+PLAT-52466: TOS: [VRMR]: Support for Vermeer Soc: Build Macro
+PLAT-52466: TOS: [VRMR]: Support for Vermeer Soc: Compilation support
+
+Release Version 0.11.0.32
+-----------------------------------
+*dr_ftpm_prod_RN.csbin reverted to version: 3.25.0.5*
+GC change will not be applied to security policy:
+PLAT-53660 - [RN] GC instance of VM_IOMMU_CONTROL_REGISTER.IOMMUEN not set on secured part
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.4B*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.4B*
+
+Bootloader
+----------------
+[BOOTLOADER] Skip storing debug prints in buffer when disabled
+[BOOTLOADER] PLAT-53182 Fix LoadAPOB source address
+[BOOTLOADER] Late apply of DMU security policy
+[BOOTLOADER] Serial IO redirection based on environment
+[BOOTLOADER] PLAT-52328 - RN - DRTM support in PSP BL
+
+Trusted OS
+----------------
+SWDEV-210896: MI200: adding register definition
+SWDEV-210896: MI200: adding build flags for MI200
+PLAT-52328 - RN - DRTM support in PSP tOS
+SWDEV-211102 : MI200: Adding ASIC type
+RTGPLAT-2679: [TOS] Enable Secure Debug Unlock in Navi 21
+RTGPLAT-2713: [TOS] Define TMZ index and data registers for Navi 21
+RTGPLAT-2249: Navi2x: Change for 8KB bootrom table for mode1 reset.
+RTGPLAT-2249 : Navi2x : Support for mode1 reset
+RTGPLAT-2623: Navi2x: Support for bootrom table size of 8KB.
+
+Release Version 0.11.0.30
+-----------------------------------
+GC change applied to security policy:
+PLAT-53660 - [RN] GC instance of VM_IOMMU_CONTROL_REGISTER.IOMMUEN not set on secured part
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.2C*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.2C*
+
+Bootloader
+----------------
+[BOOTLOADER] Fix UnmapSmn affecting adjacent mapping
+[BOOTLOADER] Fix reading of DISABLE_SECURE_DEBUG_UNLOCK fuse bit
+[BOOTLOADER] FEAT-27034 Add Anti-rollback.
+[BOOTLOADER] Enter recovery if StartUserModuleRestoreInterrupts( ) returns BL_ERR_DATA_CORRUPTION
+[BOOTLOADER] PLAT-52328 - RN - DRTM support in PSP BL
+[BOOTLOADER] PLAT-52317 Halt if PEI image corrupted on S3
+
+Trusted OS
+----------------
+RTGPLAT-2635: MI100 Update XGMI reg list for loopback test
+RTGPLAT-1723: trusted_os: Add TOC adaptation for Navi2x
+PLAT-52328 - RN - DRTM support in PSP tOS
+RTGPLAT-1807: MI100 PF FLR - Bootrom SMNIF TLBs
+MERO-20: Implementation of Persistent Objects in tOS.
+SWDEV-206074 - Navi21 SR-IOV: Add support for XGMI P2P Programming
+RTGPLAT-2623: Navi2x: Change to BOOTROM_DATA_SIZE for migration to BTO
+[RTGPLAT-2156]MI100 - TLB2 mapping corrected to Gfx9 requirement
+
+Release Version 0.18.0.2F
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+FEAT-27282 [Navi12][VG10][SRIOV] MARC_0 Register programming. Interface fixes specified by virtualization.
+
+
+Release Version 0.11.0.2E
+-----------------------------------
+Bootloader
+----------------
+[BOOTLOADER] FEAT-27034 PSP Firmware Anti-Rollback Protection
+[BOOTLOADER] PLAT-51430: SCAN Chain Fails on Secure Parts
+[BOOTLOADER] Enable Warm reset
+[BOOTLOADER] PLAT-52085 - [Renoir] Remove PSP debug message
+[BOOTLOADER] PLAT-52328 - RN - DRTM support in PSP BL
+[BOOTLOADER] Bug Fix
+[BOOTLOADER] Legacy Recovery Bug Fix
+[BOOTLOADER] FEAT-27034 Add Anti-rollback.
+[BOOTLOADER] Legacy Recovery Enablement [BOOTLOADER] Consolidate post code logger
+
+Trusted OS
+----------------
+MERO-20: Implementation of Persistent Objects in tOS.
+[TOS] FEAT-27034 PSP Firmware Anti-Rollback Protection
+PLAT-52328 - RN - DRTM support in PSP tOS
+[TOS] PLAT-52760: Assign C2P 63 register to indicate TEE capability
+SWDEV-207557 - Navi21: Enable SR-IOV base functionality
+RTGPLAT-2468: compile out External aborts for Navi 1x platform
+RTGPLAT-2468: fix arm CPSR bit definitions
+[TOS] PLAT-50482 Re-enable PSP security policy revert
+SWDEV-207558 - Navi21 - Extend IH Register programming interface in PSP for secure MARC
+SWDEV-205685: Allowed register list for XGMI loop back test
+[TOS] Skip applying DF late policy on S0i3
+PLAT-53430: Remove DMCU-ERAM and DMCU-ISR restoration in S3 and S0i3 resume path
+PLAT-52328 - Bug fix for the issue introduced in commit [51ded44]
+RTGPLAT-2467: Navi 1x: Configure TMZ registers in TOS
+
+Release Version 0.11.0.2C
+-----------------------------------
+*dr_ftpm_prod_RN.csbin updated to version: 3.27.0.5*
+
+Bootloader
+----------------
+[BOOTLOADER] Add EFS offset as per the spec
+[BOOTLOADER]PLAT-53065: Skip SPI config on emulation
+[BOOTLOADER]PLAT-50895 - Skip eSPI access in reset
+
+Trusted OS
+----------------
+PLAT-52328 - RN - DRTM support in PSP tOS/BL
+RTGPLAT-2509: Update MMHUB Fabric ID for Navi21
+PLAT-52575: [RN] Block DCN firmware DMCU_ERAM & DMCU_ISR loading via Gfx interface. Do not block tOS booting in case if GFX fuse is disabled and DMCU were not loaded.
+
+Release Version 0.11.0.2B
+-----------------------------------
+*Requires updated gfx driver and security policy
+*GFX Driver: http://osibuilds.amd.com/#/job/917386
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.36*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.36*
+
+BootLoader
+----------------
+[BOOTLOADER] PLAT-52340 Apply ATC hardware bug workaround
+
+Trusted OS
+----------------
+[TOS] RN: PLAT-52517 Power gate CCP when PSP is idle
+[SWDEV-205530] - MI100 SR-IOV: no register address in L1 violations dump
+MERO-20: Implementation of Persistent Objects in tOS.
+
+Release Version 0.11.0.2A
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-32445 [PSP Phase II] Arbitrary memory overwrite in VerifyBiosRTM( )
+
+Trusted OS
+----------------
+SWDEV-205685: MI100: Support for allowed XGMI register read /write
+PLAT-52575: [RN] Block DCN firmware DMCU_ERAM & DMCU_ISR loading via Gfx interface
+SWDEV-205934 Corrected NodeId value in memory sharing disablement
+
+Release Version 0.11.0.29
+-----------------------------------
+*rsmu_sec_policy.rn_L0.sbin updated to version: B.9.0.29*
+*rsmu_sec_policy.rn_L1.sbin updated to version: B.9.1.29*
+
+BootLoader
+----------------
+[BOOTLOADER] PLAT-51686 Interrupt Timer not triggering callback into KMD
+[BOOTLOADER] FEAT-27034 update anti-rollback
+[BOOTLOADER] PLAT-50793 enforce DMCU fw type
+[BOOTLOADER] PLAT-51535,PLAT-49607 Support for Cezanne
+PLAT-52444 [BOOTLOADER] Add new service calls to map/unmap SMN window with size parameter
+
+Trusted OS
+----------------
+MERO-20: Implementation of Persistent Objects in tOS.
+SWDEV-204075 Disable memory access (read/ write) for all the peer Dies
+RTGPLAT-2387: fix SRM Index Data load vector issue
+
+Release Version 0.11.0.28
+-----------------------------------
+*dr_ftpm_prod_RN.csbin updated to version: 3.26.0.5*
+
+BootLoader
+----------------
+[BOOTLOADER] PLAT-52271 Skip RPMC init on S3/S0i3 Resume
+[BOOTLOADER] PLAT-50895 - Enable Port80 over LPC
+[BOOTLOADER][TOS] Add support for Bixby
+[BOOTLOADER] PLAT-50999 Remove switching to PSP SPI-ROM
+[BOOTLOADER] Fix to support compressed PMU FW
+[BOOTLOADER] Style fixes
+[BOOTLOADER] PLAT-51370 Don't clear watchdogfired bit
+[BOOTLOADER] PLAT-50895 - Set LPC voltage to 3.3V
+
+Trusted OS
+----------------
+PLAT-51670: Soft-Monotonic-Counter implementation (phase4)
+[SWDEV-205065] MI100: Allow force loading of L1 security policy for non-secure part if option is enabled in VBIOS
+[TEE OS]: Enable PSP Data Snapshot feature on Renoir
+[SWDEV-202880]MI100: RAS: Add Error Notification support for WAFL 0/1 Multi-Uncorrectable RAS Errors
+PLAT-51638 : Don't enter low power state when TrustZone is enabled
+RTGPLAT-2277 Corrected mask values for fields of MC_VM_XGMI_LFB registers
+DESPCPSP-54: [Renoir][ACP] PSP need to consider the 256 byte header info while loading the ACP FW
+PLAT-51666: Failure to flush HDP Fifo during driver to/from TA / tOS communication
+RTGPLAT-1775:drv_sys: Configure USB D-state Power Management Interrupts
+RTGPLAT-1775:drv_sys: Add support for USB d-state handling
+[RTGPLAT-2309] - MI100: CCP Target Address failure on loading MEC FW in VF Framebuffer
+RTGPLAT-1784 : Navi2x: Enable sGPU functionality in TOS
+SWDEV-202887 - MI100 Mode2 Reset Enablement
+SWDEV-202887 - MI100 Mode1 Reset and PF FLR Enablement
+
+Release Version 0.11.0.27
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] TEMP: S0i3 resume skip wait for SMU DRAM response
+[BOOTLOADER] PLAT-51454 Skip MP0DPM message on S0i3 resume
+[BOOTLOADER] Debug Print Cleanup
+[BOOTLOADER] PLAT-51509 - Enable HdtOut print
+[BOOTLOADER]PLAT-48877 Fix RTM bad key validation
+
+Trusted OS
+----------------
+[TOS] PLAT-51798 Disable CCP LSB DS
+RTGPLAT-2210: Transferred DF cstate disable/ enable function from P4V
+DESPCPSP-57 - NV12 SRIOV: Save PF VMID in RLC Autoload for VF FLR
+
+Release Version 0.11.0.26
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-50793 Add DMCU Firmware Copy
+[BOOTLOADER] Add a check for global buffer in CryptoHmacSha256 function
+[BOOTLOADER] Clean up AEB unlock code
+[BOOTLOADER] PLAT-49838 Check BIOS PEI hash on S3/S0i3 resume
+[BOOTLOADER] PLAT-50315 Fix BIOS PEI image hash calculation
+
+Trusted OS
+----------------
+MERO-18: Implementation of secondary TEE interface for Mero.
+Revert "RTGPLAT-2026: Disable wfi for Navi 10/14 as there are other system wide issues"
+[TOS] RN: Enable MP0 Power Features
+PLAT-51506: Disable Commercial Pro Part Check
+SWDEV-197072 GPU-P SR-IOV: PSP timeout during multi VM VF FLR test
+SWDEV-198271: [HDCP] Add support for SRM1 signature verification. DSA signature validation.
+[TOS] PLAT-49527 Don't power-gate when warm reset is coming
+PLAT-50794: [RN] tOS load DMCU from DRAM to its destination before USBC fw loading
+MERO-15: Add new SMU-to-PSP message IDs
+[SWDEV-202113]- MI-100 SR-IOV: Add Periodic FW validation for MEC VF FW
+[CONFIG] Ignore tags and .patch files
+RTGPLAT-2147: Avoid unhalt of SDMA0 and SDMA1 for GFX10 based SOC
+PLAT-49210: Soft-Monotonic-Counter implementation (phase-3)
+
+Release Version 0.11.0.23
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-50440 Support loading compressed FW
+[BOOTLOADER] FEAT-27034: Add mandatory SPL FW list
+[BOOTLOADER] Remove unnecessary print message
+[BOOTLOADER] Update secure gasket logic
+
+Trusted OS
+----------------
+PLAT-51098 : Fail signature verification of unencrypted KVM Fw binary
+
+Release Version 0.18.0.22
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+FEAT-27282 [Navi12][VG10][SRIOV] MARC_0 Register programming
+RTGPLAT-1813: Navi10: Disable WFI for Navi10 XT & XL SKU's
+RTGPLAT-1398: NV1x: Update USB-PD firmware over I2C channel
+RTGPLAT-1397: NV1x: Request SMU to get control of I2C lines
+FEAT-27430 - NV12 Mode1/PF FLR enablement
+RTGPLAT-2026: Disable wfi for Navi 10/14
+SWDEV-190384 - SR-IOV: Avoid Autoload RLC on FLR exit for GFX 9 products
+FEAT-25098 - NV12 SRIOV: VCN FW Validation Address Calculation
+
+Release Version 0.11.0.21
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Allow Early C2PMSG28 access on S0i3 resume
+[BOOTLOADER] Fix bug programming UMC keys during S3 resume
+[BOOTLOADER] Introduce PSP directory entries for A/B recovery
+
+Trusted OS
+----------------
+[TOS] Comment out check where DMCU FW is already loaded
+PLAT-49208: Update Visual Studio solution files, no code changes.
+[PLAT-50469] Fix UART initialization cases
+PLAT-38975: Renoir and Mero/VG USB PHY FW loading.
+PLAT-xxxxx: Early load DMCU IP FW.
+SWDEV-200719: Reduce frequency of PSP Power Gating
+SWDEV-201137: Code cleanup - rename gFbBasePhyAddr to gTmrBaseGpuVa.
+LAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi Change the setting of the DMUB Cache CW0/CW1 registers to work around the DMUB h/w bug.
+SWDEV-198271: Adding support for DSA signature validation.
+
+Release Version 0.11.0.20
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-49622: Lock down MP2 RAM1
+[BOOTLOADER] PLAT-49943 Enable EncryptTmzWrites
+[BOOTLOADER] PLAT-50194 Fix MMEA0_SECURE_CTRL programming
+[BOOTLOADER] FEAT-27034 Add stage2 anti-rollback
+[BOOTLOADER] BootROM mailbox re-used as TOS mailbox bug fix
+[BOOTLOADER] Set explicit status code values
+
+Trusted OS
+----------------
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi Change the setting of the DMUB Cache CW0/CW1 registers to work around the DMUB h/w bug.
+PLAT-50532: Temporary inform good status of PspStorage, till feature is enabled in drv_sys
+PLAT-50539: [RN] Enable SMU-2-PSP interface back after S3/S0i3 resume
+SWDEV-189108 PSP-SMU Firmware interface changes for XGMI DPM
+[TOS] Temporary workaround to ignore command 0x1B from BIOS
+[TOS] Temporary disable reverting PSP security policy during debug unlock
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi Change the setting of the DMUB Cache registers from GPU Virtual to FB Physical address.
+[TOS] PLAT-49831: Suspend SMU call in Secure Debug Unlock causing hard hang
+SWDEV-198271: Adding support for DSA signature validation.
+PLAT-49210: Use SMI-interface to write to PSP NVRAM and enable encryption PSP NVRAM records (phase2)
+PLAT-46938 : Enhance Dlm support for Ftpm Dlm prints
+
+Release Version 0.11.0.1E
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+[TOS] RN: Disable MP0 power features to fix S3
+PLAT-49208: Update Visual Studio solution files, no code changes.
+
+Release Version 0.11.0.1D
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Disable VCPU Instruction Fetch Monitor
+[BOOTLOADER] PLAT-46883 Fix bug of eDP early screen-on during S0i3
+[BOOTLOADER] Skip graphics register access on S0i3 resume
+[BOOTLOADER] FEAT-27034 Add anti-rollback
+[BOOTLOADER] PLAT-49718 Skip IP-discovery table loading in S3/S0i3 cycle
+[BOOTLOADER] Retrieve and unwrap iKEK if necessary
+
+Trusted OS
+----------------
+[TOS] Temporary disable the suspend call to SMU to enable SDU with GFX Driver
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi Cosmetics.
+[TOS] RN: Enable MP0 power features
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi New requirement for resetting the new DMUB IP FW after testing in DAL.
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi Additional requirement for resetting the new DMUB IP FW.
+PLAT-48444: SPI settings for normal/fast read speed and test mode
+PLAT-48284: [RN] TMR Setup fixes and redesign Fix a TMR leaking issue during S4 restore FW. Check if the TMR region is already set with the same addresses. If so then return back already occupied slot number. That logic was applied on RV and works fine.
+PLAT-49208: Soft-Monotonic-Counter APIs implementation (phase-1)
+
+Release Version 0.11.0.1C
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Enable Unconditional Unlock
+[BOOTLOADER] PLAT-48891 Skip MP2 load if already executing
+[BOOTLOADER] PLAT-46883 Add GPE wake event for eDP early screen-on during S0i3
+[BOOTLOADER] update binary Makefiles
+[BOOTLOADER] Remove crypto function call debug prints
+[BOOTLOADER] PLAT-49055 Solving PSP BL failure updating HMAC key
+[BOOTLOADER] Stage1 BL fixes from emulation testing.
+[BOOTLOADER] Add security policy header validation
+
+Trusted OS
+----------------
+[TOS] RN: Fix to skip applying GFX security policy on unlocked part
+PLAT-48284: [RN] TMR Setup fixes and redesign
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi
+SWDEV-196883: Bug fix for TMZ enablement on GFXOFF exit.
+
+Release Version 0.11.0.1A
+-----------------------------------
+NOT Included in Release Version 0.11.0.1A
+-----------------------------------------
+-Secure Debug Unlock
+-RPMC
+-MP2 FW Loading Disable
+
+BootLoader
+----------------
+[BOOTLOADER] Enable PMU/KeyDb FW validation
+[BOOTLOADER] PLAT-47866 Fix CF9-06 reset
+[BOOTLOADER] Change UMC key index from 0 to 15
+[BOOTLOADER] Remove PSP BL Port 80 Accesses during ABL execution
+[BOOTLOADER] Enable TMZ on non-secure parts
+[BOOTLOADER] Store TMR restore data in crypto global buffer
+[BOOTLOADER] GPU Host Translation Cache add VM_IOMMU enable
+[BOOTLOADER] Fix GPU Host Translation Cache enablement from syscall
+[BOOTLOADER] Fix Softfuse for controlling MP2 loading bug
+[BOOTLOADER] Add runtime emulation detection
+[BOOTLOADER]PLAT-47570: Fix IP harvesting
+[BOOTLOADER] eSPI configure cherry pick from rn-bringup
+[BOOTLOADER] Check return code of call to kdb_getKey
+
+Trusted OS
+----------------
+SWDEV-197248: Revert commit [ea882fa] as VCN team dropped their debug request.
+PLAT-46883: [Renoir-MS]Add GPE wake event support for eDP early screen-on
+[TOS] RN: Disable Power Gating on Non-secure parts
+SWDEV-197248: VCN firmware front-door loading not working due to TMR settings
+Fix Unit ID of DMUB and typo in the code for reset it.
+SWDEV-197248: Return GPU Virtual Address of VCN firmware in SRIOV mode for VF.
+SWDEV-197248: Return FB Physical Address of VCN firmware to the Gfx driver.
+Support to handle external abort in Secure OS
+[tOS] Add comments to make it easier to analyse exception data in registers.
+PLAT-48284: [RN] TMR Setup fixes and redesign
+SWDEV-196436 Corrected PCRU PUBLIC structure
+Porting rn-bringup branch commit [a42dde2] to the amd-staging: [TOS] PLAT-47550 Fixed SMN blocking duo to WLAN access
+[tOS]: Sanitize modulus and exponent sizes in CcpModExp().
+[TOS] Clean up LoadModule function from redundant operation.
+[TOS] Correct PSP FW STATUS format description in the comment header of DiagnosticMessage() function
+Porting rn-bringup branch commit [9cfcfb1] to the amd-staging: "[TOS] Enable MPCLK SOCCLK SHUBCLK deep sleep allow"
+PLAT-48284: [RN] TMR Setup fixes and redesign
+[TOS] PLAT-47882 Fix USB FW sometimes failing validation.
+[SWDEV-194505] TOS: Signing drv_sys.bin using KDS fails
+PLAT-47405: Fix security issue caused by inadequate protection of C2PMSG_91
+DEREM-299: Bug fix for USB-PHY FW loading.
+PSP-3520: Do not allow using TestKey on secure parts.
+PLAT-47833: [RN] Fix MMHUB Base address and AXI address computation
+SWDEV-181915: System Hard Hang when resume from sleep and Netflix app open
+PSP-3520: Use KeyDb loaded by Boot Loader.
+[SWDEV-194045] TOS: Add missing header binary file for PSP OS
+[SWDEV-193018]: Fix compile warnings in BUILD_RN configuration
+PSP-3521: Fix permissions check bug for IPC (inter-process calls) handling in SysDrv.
+SWDEV-190741: Move SRIOV dynamic register writes from PSP OS to sysdrv.
+
+Release Version 00.17.00.17
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+[SWDEV-193018]- MI100: Enable dGPU specific sequences in PSP OS
+Add BUILD flag for MI100 to enable functionality in PSP OS
+Update hw_reg, smn_reg and rsmu_header files.
+
+Release Version 0.11.0.16
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] LPC port init clean up
+
+Trusted OS
+----------------
+NA
+
+Release Version 0.11.0.15
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Update application of security policy
+[BOOTLOADER] PLAT-32123 Enable eSPI for 3F8h
+
+Trusted OS
+----------------
+PLAT-38975: Fix to allow test keys on non secure part
+PLAT-38975: Add RN 2K test key in global Key permission array
+PLAT-46586: [RN] Enable graphics security policy in tOS
+PLAT-38975: RN Load USBC Phy firmware. USB/DP PHY FW Unified binary and each image inside validation.
+PSP-3520: Use KeyDb loaded by Boot Loader.
+PSP-3505: Update Visual Studio project files.
+PSP-3505: Update Visual Studio project files.
+PLAT-46586: Refactoring of rsmu.c file
+
+Release Version 0.11.0.14
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-47178 Add SVC call to set iGPU is disabled.
+[BOOTLOADER]PLAT-47358: Fix BIOS load error reporting
+
+Trusted OS
+----------------
+NA
+
+Release Version 0.11.0.13
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Add thermal trip bit check to S5 boot
+
+Trusted OS
+----------------
+PLAT-46190: [RN] Update PSP Authentication for PROM19 Variants
+FEAT-26870: [Navi1x][tOS] Translate PS_DIRECTORY_ENTRY_TYPE_BIST_DATA to SPI Address
+[SWDEV-190382]- MI100: Add Product Number and Build Flag
+[SWDEV-190381] - Add GFX9 Enablement
+Clean up power feature code in TOS
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi
+PSP-3520: Add validation of KeyUsageFlag for IP FWs.
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi
+
+Release Version 0.11.0.12
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] SWDEV-190975 Implement CS-seed checking
+[BOOTLOADER] PLAT-46947: Add SVC Input Validation
+[BOOTLOADER] PLAT-46260 Skip L3 in MBAT when downcored
+[BOOTLOADER] PLAT-46390 Enable ABL verification with key database
+[BOOTLOADER] PLAT-46829/44597 Load/Verify SMU(MP1) without PSP image header
+[BOOTLOADER] PLAT-46746 Set C2PMSG97-99 attribute
+[BOOTLOADER] PLAT-41678 Check CCP TRNG numbers are valid
+[BOOTLOADER] PLAT-46520 PSB support for RN
+[BOOTLOADER] Stage 1 bootloader initial commit:
+[BOOTLOADER] Fix Coverity warnings
+{BOOTLOADER] SWDEV-188588 Fixed scanning for Embedded FW Signature
+[BOOTLOADER] PLAT-46786 Bypass VBL in S0i3 mode
+[BOOTLOADER] Fix HMAC comparison function
+[BOOTLOADER] Fix LogBLPostCode "hang" condition
+
+Trusted OS
+----------------
+DEREM-192: [RN] Enable MPCLK deep sleep
+PLAT-47110: Address NCC issue "Inspection-006-097".
+DESPCPPSP-56 - Navi1x - Remove TMR fences on Unlock
+RTGPLAT-1155: Navi 1x: Restore harvesting registers before ATC invalidation
+FEAT-26869: [Renoir] Update and Verify CS-SEED-based KDF and Key Unwrapping SWDEV-190959: Promontory Device Pre-Shared Key Authentication Key SWDEV-190961: Knoll Device Pre-Shared Authentication Key
+FEAT-26175: [Navi1x] Add SPI write support for GD25Q80C SPI model. Add SPI init support for NV14 as well as NV10
+PLAT-33045: [PSP Phase II] The shared DLM buffer can be abused to corrupt TEE OS memory
+PLAT-45572: Merge Gfx 9 IP FW loading for Renoir with Gfx 10 implementation for Navi
+
+Release Version 0.11.0.11
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-42929 Authenicate BIOS PEI in S3/S0i3 mode
+[BOOTLOADER] PLAT-46735 Disallow non-MP0 to access MP2 SRAM1
+[BOOTLOADER] PLAT-46096 Correct S2PMSG register init
+
+Trusted OS
+----------------
+SWDEV-188549 [Renoir] Implement PSP virtual mode
+FEAT-26175: [Navi1x] Add SPI write support for GD25Q80C SPI model
+RTGPLAT-1217: Navi1x: fix DMCU firmware start address for ERAM and ISR
+RTGPLAT-1153: Enable DfCstate after debug unlock
+RTGPLAT-1217: Navi1x: fix DMCU firmware size for ERAM and ISR
+PSP-3520: Bug fix in IP FW validation.
+RTGPLAT-1201: Navi 1x: Fix applying security policy on gfx off exit.
+RTGPLAT-1201: Navi 1x: Fix applying security policy on gfx off exit
+PLAT-43193: Disable SureStart feature for Renoir.
+RTGPLAT-1155: Save/Restore harvesting registers before invalidation in mode 2 reset
+RTGPLAT-1187: Navi10/14 fix mode 2 reset incorrect SMN address
+PLAT-46066: New Gfx-to-PSP command for programming VM default address
+RTGPLAT-1179:[Navi14]:Fix build break
+SWDEV-188857 Add support for CCP power features.
+RTGPLAT-1175: [Navi14]: Fix display pipe count
+RTGPLAT-1154: do not clean the display as DCN is not resetted in Mode 2 reset
+RTGPLAT-1174: [Navi14]:Disable XGMI init
+RTGPLAT-1154: Remove DCN Reset as part of mode 2 reset
+PLAT-43197: [DRTM] PSP controlled shared memory buffer.
+
+Release Version 0.11.0.F
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-39850 Add support for CCP HMAC engine
+[BOOTLOADER] PLAT-42522 Change APOB signing key
+[BOOTLOADER] PLAT-42924 Add RPMC support
+[BOOTLOADER] PLAT-42917 Key Database [3/3]
+
+Trusted OS
+----------------
+RTGPLAT-1138: [Navi14]:Enable Mode1 and Mode2 reset
+RTGPLAT-1137:[Navi14]: Update register headers
+RTGPLAT-1130:[Navi14]:Enable Secure Debug Unlock in Secure OS
+RTGPLAT-960: [Navi14]: Add SOC family Id in header of Sys-Driver image
+RTGPLAT-1149:[Navi1X]: Use common flag for Navi1X features
+RTGPLAT-928: Disable VCPU instruction fetch monitoring.
+PLAT-42922: [RN] PlayReady: TMZ in System Memory & LFB
+FEAT-25098 - NV10 SRIOV: Re-enable Periodic VCN FW Validation
+
+Release Version 0.11.0.E
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-46260 Disabled MBAT as part of the release to unblock PEMU
+[BOOTLOADER] PLAT-46290 Skip GC RSMU configuration
+[BOOTLOADER] PLAT-45821 Fix Windows BSOD in SimNow
+[BOOTLOADER] PLAT-46029 Enable postcode buffer
+[BOOTLOADER] PLAT-46061 Fix firmware size and location
+[BOOTLOADER] PLAT-42917: Key Database [2/N]
+[BOOTLOADER] PLAT-44423 Load IP discovery binary
+[BOOTLOADER] PLAT-45940 Fix section names, zero-init BSS
+
+Trusted OS
+----------------
+PLAT-36079: Navi10: Fix register address and offsets for Mode 1
+RTGPLAT-1015: during mode2 reset update bios scratch 6 register
+RTGPLAT-640: temp-hack: disable PSP going to low power state
+FEAT-24956: Navi 10: Fix UMC COLD RESETB SMN address
+RTGPLAT-960: Add register headers for Navi14
+FEAT-26164: Add Gfx-to-PSP APIs for passing parameters for GDDR6 from KMD.
+PLAT-46066: New Gfx-to-PSP command for programming VM default address
+PLAT-45692: Skip complete frame for vm_switch
+SWDEV-185449: Prevent programming VM table for base address zero
+PLAT-46130: Renoir: Update PSP message codes
+DEREM-182: C2P registers not being updated for SLVERRs on PCIE0 RSMU MMIO register accesses
+RTGPLAT-960: Add PSP FW image header for Navi14
+RTGPLAT-960: Update Makfiles for signing function and help for Navi14
+RTGPLAT-960: Add separate product number for Navi14
+RTGPLAT-386: [VCN RAM]: Program GPU Physical Address into VCN RAM buffer.
+RTGPLAT-651: drv_sys: setup_tmr should not fail when already setup
+RTGPLAT-386: [VCN RAM]: Program GPU Physical Address into VCN RAM buffer.
+PLAT-46066: New Gfx-to-PSP command for programming VM default address
+FEAT-26164: Update data structure for handling GDDR6 training parameters.
+RTGPLAT-386: [VCN RAM]: Program UVD_LMI_SPACE_INTERNAL3 register by PSP.
+Store TOS data abort information into new firmware status registers.
+
+Release Version 0.11.0.C
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-32123 Add eSPI support
+[BOOTLOADER] PLAT-38153 32MB SBIOS Support
+[BOOTLOADER] PLAT-42917: Key Database [1/N]
+
+Trusted OS
+----------------
+PLAT-45827: Add new cmd in TEE interface
+RTGPLAT-960: Use common ccp lib for Navi1x platform
+RTGPLAT-386: VCN RAM loading - FW case in Reset IP FW
+RTGPLAT-960: Make SMU interface header common for Navi1x platform
+RTGPLAT-960: Introduce common flag for Navi1x platform
+RTGPLAT-977: Implement TOC fw size multiplier to accomodate larger fw in TMR
+FEAT-26164: Implementation of save/invalidate of GDDR6 training parameters in SPI.
+PLAT-44810: drv_sys: Clear TMZ key data while debug unlock
+RTGPLAT-386: [VCN IP monitoring]: Implementation of VCN RAM loading.
+FEAT-26164: Add data structures and API for handling GDDR6 training parameters.
+PLAT-44359: PSP FW to support Pro SKU detection by reading fuse bit
+RTGPLAT-928: Disable VCPU instruction fetch monitoring
+RTGPLAT-535: DrvSys: Apply UMC unlock policy for MPV feature
+FEAT-24472: DMCU Firmware front-door Loading in system driver
+RTGPLAT-427: Enable TMR configuration for VCN ucode memory
+PLAT-45708: [RN] Fix a bug in RSMU security interrupt clearing
+
+Release Version 0.11.0.B
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-38153 32MB SBIOS Support
+[BOOTLOADER] PLAT-42917: Key Database [1/N]
+[BOOTLOADER] Implemented MBAT programming and SVC_REMAP_MBAT_ENTRY
+[BOOTLOADER] PLAT-42932: Added GPU Host Translation Cache Feature
+[BOOTLOADER] PLAT-43208 SVCcall for Reserved DRAM memory
+[BOOTLOADER] PLAT-43946 Load Diag bootloader only when soft-fuse bit5 is set
+[BOOTLOADER] Pass zero-padded exponent in CCP mod exp command
+[BOOTLOADER] Add support for hardware PC sniffer
+[BOOTLOADER] PLAT-41898 VBL loading by iGFX fuse
+
+Trusted OS
+----------------
+NA
+
+Release Version 0.11.0.A
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-42936 S3 Entry/Exit in Simnow
+[BOOTLOADER] PLAT-43310/PLAT-43443 Port changes from Raven to Renior 4/X
+[BOOTLOADER] PLAT-44281 Allocate 0x29 to KVM binary
+[BOOTLOADER] HW-IP-Discovery feature implementation
+[BOOTLOADER] PLAT-44395 DEREM-168 MP2 support
+
+Trusted OS
+----------------
+NA
+
+Release Version 0.11.0.9
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-43698 SVC call "SVC_SEARCH_BIOS_DIR_V2"
+[BOOTLOADER] Add build flags to Makefile's "help"
+[BOOTLOADER] Remove SKIP_ERROR
+[BOOTLOADER] PLAT-38344/PLAT-43443 Port changes from Raven to Renior 3/X
+[BOOTLOADER] PLAT-44006 Headerless FW loading
+[BOOTLOADER] S0i3 feature implementation
+
+Trusted OS
+----------------
+PLAT-43197: PSP FW Version Manifest Generation
+PLAT-42720: Enable TMZ for Navi10
+Skip SMU FW reload only on dGPU
+PLAT-37871: Navi10 - Enable GC violation logging
+RTGPLAT-591: Fix secureOS debug unlock sequence to unlock GC
+SWDEV-183202: RV2 and RV1 S3 failure after 25 cycles
+FEAT-25096: NV10 SRIOV - Update Load Vector Value and Destination
+PSP-3521: Add support for IPC in SysDrv
+SWDEV-185623: NV10 SRIOV - RLC Autoload Failure on VF
+FEAT-26140: MES/MES_STACK FW Loading Case in Reset IP FW
+Add MP0 Power Features to trustedOS
+Remove compilation warning in tOS
+SWDEV-184767: Save/restore VCN FW size over S4 cycle
+FEAT-25091: NV10 SRIOV - Remove SDMA Jump Table Copy
+PLAT-42918: Fix S0i2 support in tOS
+RTGPLAT-433: Update product code in firmware version
+PLAT-44359: PSP FW to support Pro SKU detection by reading fuse bit
+Add support for PC Sniffer in tOS kernel
+RTGPLAT-552: TMR - Disable write enable for read only TMRs
+PLAT-45138: Fix encrypted TA load failure
+PLAT-43197: PSP controlled shared memory buffer
+PLAT-45469: BIOS-PSP SMI Mutex C2PMSG_23 Attribute Bug
+Disable PC Sniffer when changing timeouts
+FEAT-24957: Navi10 - Add Mode2 Reset Support
+FEAT-25096: NV10 SRIOV - L1 Policy Apply and Revert Sections
+FEAT-25098: NV10 SRIOV - Periodic VCN FW Validation for VFs
+SWDEV-184767: Reorganize IP FW Loading Code
+RTGPLAT-386: Implementation of VCN RAM Loading
+PLAT-45596: Bug introduced by moving virtual interrupts beyond max physical interrupts
+PLAT-32090: Race condition leads to memory corruption in BIOS2PSP command dispatcher
+FEAT-25098: NV10 SRIOV - Temporarily Disable Periodic VCN FW Validation
+RTGPLAT-760: Add support to blanking active display pipe in Mode2 reset
+RTGPLAT-814: Skip EA and UTCL2 reset in Mode2
+RTGPLAT-760: Refactor "32. Add support to blanking active display pipe in Mode2 reset"
+FEAT-24956: Navi10 - Add Mode1 Reset Support
+RTGPLAT-540: Restore APCC tuning registers on PnP and Mode2 reset
+SWDEV-185391: Configure cold/hard reset in SMUIO_GFX_MISC_CNTL
+RTGPLAT-464: Add support to apply GRBM CAM settings in Mode2 reset
+Revert "FEAT-25091 : NV10 Baremetal - Add SDMA Jump Table Copy"
+
+Release Version 0.11.0.8
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] PLAT-38351 Increase ABL SRAM SIZE
+[BOOTLOADER] PLAT-43604 Error return of MapUserStack()
+[BOOTLOADER] Fixed bug introduced in code cleanup CL 60132
+[BOOTLOADER] PLAT-43443 Port changes from Raven to Renoir 2/X
+
+Trusted OS
+----------------
+PSP-3520: Support multi-level FW headers for IP FW
+PLAT-42376: RPMC support needed in trustedOS
+PSP-3520: Fix TOCTOCU security issue in IP FW validation
+FEAT-25091: NV10 SRIOV - VF GFX FW Loading in TMR
+SWDEV-182169: VCN FW Restore Fix
+FEAT-25094: NV10 SRIOV - RLC Autoload for VF
+PLAT-42113: NV10 GFX Security Policy Update
+PLAT-43743: Driver Syscall API Update to Differentiate Error and Valid Return Code
+PLAT-41792: DRTM Address Mapping API in System Driver
+FEAT-25097: NV10 SRIOV - VCN FW Loading in VMR
+PLAT-43580: Set status bit in BIOS-to-PSP command register for A/B recovery
+PSP-3505: Add synchronization barrier to SMN write service
+SWDEV-181915: Fix PlayReady playback issue after S3 resume
+PLAT-43197: PSP FW version Manifest Generation
+FEAT-25091: NV10 SRIOV - Remove SDMA Jump Table Copy
+PLAT-43719: Change fTPM signing key from root key to AMDTEE TA key
+FEAT-25096: NV10 SRIOV - VF ID Update to Load GFX FW and TOC in PF Memory
+PSP-3521: Initial coding for IPC implementation
+PLAT-44084: Bug check when resume from sleep and Netflix app open
+PLAT-44089: Port P4 CL#62884 - SMU RAS Fatal Error During FW Loading
+
+Release Version 0.11.0.7
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] S0i3 feature implementation
+[BOOTLOADER] Fix FW version print
+[BOOTLOADER] PLAT-43443 Port changes from Raven to Renoir
+[BOOTLOADER] PLAT-37728 Add Combo Bios Directory Support
+
+Trusted OS
+----------------
+FEAT-25098: Enable MMSCH FW Front Door Loading on Navi 10.
+PLAT-41793: APIs for dynamic allocation of TMR regions.
+PLAT-41792: DRTM Address Mapping API.
+FEAT-25098: Port SDMA Jump Table 4K alignment from Navi 10 repo.
+
+Release Version 0.11.0.6
+-----------------------------------
+BootLoader
+----------------
+[BOOTLOADER] Update RN fuse file
+[BOOTLOADER] Removed HSTI support
+[BOOTLOADER] Update PSP BL Crypto functions to use CCP_HAL layer which supports RN CCP12
+[BOOTLOADER] PLAT-41423 Implement USB-C PHY (FW type: 0x44) loading in PSP bootloader
+[BOOTLOADER] SWDEV-176482 Clear a TLB busy bit early in smnif
+[BOOTLOADER] Change crLsb algorithm to support double slot allocations
+[BOOTLOADER] PLAT-42113 Implement Renoir L0 security policy loading and execution
+[BOOTLOADER] PLAT-42482 Implement Renoir L1 security policy loading to DRAM
+[BOOTLOADER] Fixed DC.String_Buffer error in file kdf.c function DeriveKeyUsingPRF
+[BOOTLOADER] PLAT-37433 Enhancement in white-list feature
+[BOOTLOADER] Add error log when PSP BL enters into recovery mode
+[BOOTLOADER] SWDEV-175419 TMR s0i3 restore cleanup
+[BOOTLOADER] Fixed MP2 SRAM1 layout overlap with BootRom
+[BOOTLOADER] Eliminated MP2 SRAM1 data save/restore authentication
+[BOOTLOADER] Add RAM cookie check in AddEntryToMP2RAM1()
+[BOOTLOADER] Fix CCP zlib argument order
+[BOOTLOADER] PMFW-1072 Workaround for BootRom bug by programming MP0_ROMBIST_BYPASS to 0
+[BOOTLOADER] Update RN register files with CL#1027599
+[BOOTLOADER] Fix a bug in PutVcnInReset()
+[BOOTLOADER] PSP-3505 Remove the ASIC TYPE from commom_defs.h
+
+Trusted OS
+----------------
+Port Gfx FW loading functionality from Navi 10 repo.
+Initial implementation of USBC FW loading.
+Use latest CCP HAL build which includes Renoir specific register definitions.
+SWDEV-175419: refactor TMR handling functionality (use index/data access to TMR registers).
+Multiple updates to Security Policy definitions (including section ID refactoring).
+Remove periodic MEC FW validation code.
+Implement DRTM specific SysDrv services for register access.
+Implement DRTM specific SysDrv services for TMR handling (not completed yet).
+Clean up SMU message handler.
+Updated GFXOFF exit sequence (support multiple SMU messages).
+PLAT-38975: Refactor FW validation function to support 2KB and 4KB signatures.
+FEAT-25092: PSP detects SR-IOV Capability.
+Add support for Customer Key enablement (Key Database). Not completed yet.
+PMFW-1071: Set MP2_FW_OVERRIDE.MP0_ROMBIST_BYPASS = 1 before entering S0i3.
+PLAT-42376: RPMC support in Trusted OS.
+Update BootLoader-to-tOS mailbox location and size across all builds (NV10/RN).
+Add PSP (MP0) activity counter.
+SWDEV-175419: Add mutex for protection for TMR modification.
+DEIPCSMU11-3418: Increase SysDrv SRAM buffer from 4 KB to 8 KB to solve CCP issues with ECC.
+SWDEV-178153: Implement PSP Virtual Mode.
+
+Release Version 0.11.0.5
+-----------------------------------
+BootLoader
+----------------
+NA
+
+Trusted OS
+----------------
+Remove SimNow debug code.
+Reserve DRAM buffer for DRTM TA.
+Fix SimNow Data Abort caused by overlap of temporary L1 page table with tOS code.
diff --git a/cezanne/PSP/PspNvramCZN.bin b/cezanne/PSP/PspNvramCZN.bin
new file mode 100644
index 0000000..4d45d9b
--- /dev/null
+++ b/cezanne/PSP/PspNvramCZN.bin
@@ -0,0 +1 @@
+ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
\ No newline at end of file
diff --git a/cezanne/PSP/SmuReleaseNotesCZN.txt b/cezanne/PSP/SmuReleaseNotesCZN.txt
new file mode 100644
index 0000000..8af5cf7
--- /dev/null
+++ b/cezanne/PSP/SmuReleaseNotesCZN.txt
@@ -0,0 +1,805 @@
++---------------------------------------+
+| SMU Firmware Release Notes - CEZANNE |
++---------------------------------------+
+
++---------------------------+
+| Version 64.31.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 27/10/20
+|
+| * Changelist
+| - DXIO v55.759
+| - PMFW Kernel v21
+| - aeaa11405 [PLAT-71484] [ETB] Hardlock occurred with PC: EF003342/ B0000CB6 while running 3DMark_Timespy in DC mode
+| - 1602d3939 [PLAT-70957] [IMP] 35W Run to run and Part to Part Variance due to EDC --L3 EDC Floor
+| - abc9fdc17 [PMFW-5929] [IMP] Change DID delta on CZN AM4
+| - 6a3a73f44 [PMFW-5880] [IMP] Apply settings based on BIOS Interface Table values on S0i3 Resume
+| - 5a1a274b5 [PMFW-5876] [IMP] Integrate DXIO-FW version 55.759.0 into SMU
+| - 72c81591b [PLAT-67666] [WKA] Kernel debugger does not work via USB3 until late in the boot process
+| - decd40980 [PLAT-70957] [IMP] 35W Run to run and Part to Part Variance due to EDC
+| - e77cac9e6 [PMFW-5838] [IMP] CZN FP6 TmonNumAcq=0x2 and Curtemp Filtering (AlphaUp=0.001)
+| - c8e482533 [PLAT-71037] [ETB]MI-A18S fails to enter S0I3 with NVMe KIOXIA (DC only)
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.31.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.31.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.30.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 16/10/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 5ec51c2ae [PMFW-5841] [IMP] New PHYCLK Lookup Table for HBR3 to DPM3
+| - f31b3368e [PLAT-71136] [ETB] [AM4] System auto resume from S4 on S0i3 OS
+| - a6c3b9259 [PMFW-5826] [ETB] Incorrect fuse read for unsigned AVFS Core Freq Offset fuse
+| - 168d1dc14 [PMFW-5817] [IMP] Remove Message structure from RAI
+| - a9b00ee2b [PLAT-70663] [IMP] VR PSI Control issue with single phase over-current
+| - 1efbcaf3a [PMFW-5795] [IMP] Add patch generation support for test_package
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.30.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.30.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.29.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 08/10/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 12877ae40 [PMFW-4810] [ETB] CZN Add limiters to PPT, TDC and EDC - Update AM4 Unauthenticated default
+| - 6d06db575 [PMFW-5780] [OPT] EDC Optimization to Improve CZN performance at 70A EDC Limit
+| - c9f689765 [PMFW-5628] [IMP] Extend FidDid Table to support Overclocking Range to DDR8000 (4000MHz)
+| - 83aaddd51 [PMFW-5732] [WKA] DPPCLK WKA for DENTIST_WDIVIDER field mismatch
+| - fd5a4480b [PMFW-5701] [IMP] Lower DCN clock and Vmin if panel is in PSR
+| - 4f7d05519 [PMFW-5738] [IMP] Coverity Scan For Cezanne 092020
+| - 6d6556d19 [PMFW-5720] [OPT] CAC weights Minor Tuning
+| - 2483a7d08 [PLAT-68974] [WKA] No PME_Turn_Off in the end of entering S3/S4/S5
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.29.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.29.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.28.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 29/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 7f1f7f366 [PMFW-4902] [NEW] Reset OC mode to default when entering DC Mode
+| - e6debfab8 [PLAT-67499] [ETB] [CZN FP6] [Level3] SUT fails to automatically wake up from S0i3 AMDsuspend, fail rate 1/100 loops
+| - 6d3aa8142 [PMFW-5531] [IMP] CZN FP6: Retain Memory / DF Pstates functionality during Memory Overclock
+| - e9fbe2410 [PMFW-5712] [IMP] GTSC workaround optimization
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.28.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.28.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.27.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 25/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 67358c47b [PMFW-5702] [IMP] Allow debug version override in test FW creation
+| - 36ee30457 [PMFW-5708] [OPT] CAC weights update to Rev15 - Updated for AVX discrepancy issue
+| - 048c49e9a [PMFW-5666] [ETB] External Pcie FSDL coverity failure
+| - 7865602b5 [PLAT-70083] [IMP] [AM4] Overclock setting is cleared after resume from S0i3
+| - 15a9652da [PLAT-70223] [ITB] set combophystaticconfig to USB only mode fail
+| - 11007ead6 [PMFW-5209] [WKA] New sequence in SetCoreLdo to ensure P-State change - part 2
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.27.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.27.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.26.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 21/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 6712f1bc8 [PMFW-5662] [WKA] 15W iDVT needs to match final DVT 2.1GHz GB
+| - bc0a8ee98 [PLAT-69947] [OPT] CZN FP6 15W DVT low yield issue with Core DLDO enabled
+| - aab3ebeb0 [PLAT-69969] [IMP] Setup option for CC1 Disable has no effect - Add CC1Dis check during enable
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.26.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.26.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.25.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 18/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - 847048b2d [PMFW-4810] [ETB] CZN Add limiters to PPT, TDC and EDC - Update
+| - 2abd9e421 [PMFW-5613] [IMP] VDDCR Startup Voltage Sequence Optimization
+| - f38be37a2 [PMFW-5617] [OPT] [CZN] Update PriorityDeltaGain for STAPM, PPT and TDC Controllers
+| - 3595e76b8 [PLAT-69969] [IMP] Setup option for CC1 Disable has no effect
+| - f2e6d6c83 [PLAT-69695] [IMP] Boot at 1.2V instead of startup vid
+| - 0b6808f02 [PMFW-5623] [IMP] CZN FP6 PPT, EDC, TDC Limit Adjustment for 45W Ryzen 7 and 5
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.25.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.25.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.24.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 14/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v21
+| - f579b6dd7 [PMFW-4841] [IMP] [CZN AM4] Alpha filter implementation for SBTSI filtering
+| - 99da4ebfc [PLAT-67479] [IMP] disable/enable CLKB port at GFXOFF entry/exit
+| - 50f58f74c [PMFW-5184] [IMP] SetArbiterHardMax_SOC for DcfclkDpm
+| - 1e68b9b8b [PMFW-5620] [IMP] Integrate PMFW Kernel v21
+| - 766e1f5c9 [PLAT-69752] [ETB] Customer LPDDR System Cannot Resume from S0i3 Modem standby
+| - c23ebe7a8 [PMFW-5594] [WKA] Modify WKA for SOC voltages in SMU FW for Fast CLDO Bypass
+| - 478c4a8ed [PLAT-69041] [ETB] [WHQL][CZN-FP6][Device][HLK 19041][20H2] Regression: D3D12 - SingleCommandListTimestampsDecode test fails.
+| - 6c38af67a [PMFW-4783] [IMP] Adjust STT limit for SMU FW message PPSMC_MSG_SetPowerLimitPercentage when STT is in use
+| - e0f3478f2 [PMFW-5596] [OPT] CZN EDC Parameter Update
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.24.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.24.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.23.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 03/09/20
+|
+| * Changelist
+| - DXIO v55.757
+| - PMFW Kernel v19
+| - 7bee54b98 [PMFW-5564] [UTB] EDC GFX Iddmax needs to use target voltage when GFXDLDO in BYPASS
+| - 8c1bd8fa2 [PMFW-5551] [IMP] Integrate dxio_fw v 55.757 into CZN PMFW release
+| - 178dc62ce [PMFW-4794] [IMP] Gfxclk Overdrive need to set max EDC threshold
+| - 303b06b64 [PMFW-5572] [ETB] Incorrect default sPPT time constant when BiosInterfaceTable.SLOW_PPT_TIME_CONSTANT is 0
+| - da2b0f3b3 [PMFW-5200] [NEW] Overclocking state does not restore after S0i3 - Fix function prototype
+| - e36df73fa [PMFW-5202] [NEW] CZN: Support LN2 mode on APU
+| - cc73d0dee [PMFW-4840] [IMP] GFXVoltage does not get set after applying SOCVoltage
+| - b8d839f19 [PMFW-4810] [IMP] CZN Add limiters to PPT, TDC and EDC - Add SmartShift Support
+| - 456d6d292 [PMFW-5200] [NEW] Overclocking state does not restore after S0i3
+| - 5bfe93943 [PMFW-4810] [ETB] CZN Add limiters to PPT, TDC and EDC - Fix FitLimitScalar MOC disabled case
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.23.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.23.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.22.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 28/08/20
+|
+| * Changelist
+| - DXIO v55.755
+| - PMFW Kernel v19
+| - e44430407 [PLAT-68470] [IMP] Save/Restore the PMCSR of all external PCIE devices (except NVME) in the process of entering and exiting S0i3
+| - 53d72d6e8 [PMFW-5451] [UTB] [CZN] Update Core C-States Timers (IRM) for AC Mode
+| - 3749df7d0 [PMFW-5316] [UTB] DF P state 0 (1600/1067/2133) is not triggered in Cezanne 45W LPDDR4
+| - 79bd34b78 [PLAT-68458] [ETB] Temperature turns to -49C while AC switch to DC immediately
+| - d7cc6cb25 [PMFW-4810] [ETB] CZN Add limiters to PPT, TDC and EDC - Fix PBO disabled FP6 default
+| - 387ca8627 [PMFW-5385] [ETB] RN-AM4 correct 10ms delay for DSM_B function
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.22.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.22.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.21.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 24/08/20
+|
+| * Changelist
+| - DXIO v55.755
+| - PMFW Kernel v19
+| - 0e27fb8e8 [PLAT-67685] [ETB] Fix hang at ChangeCorePll due to VdciLowPwrDis
+| - 2d19fd8f2 [PLAT-67825] [ETB] GFX FDD BTC tiles with incorrect -64 calibration value
+| - 7c04529d9 [PMFW-4838] [NEW] Request to implement BTC for core mafdd - Update VR WKA
+| - 89a2dbbe9 [PMFW-5397] [IMP] CZN GfxDEM optimization
+| - 413503782 [PMFW-5377] [IMP] Shift function to EXT to make space in TEXT section
+| - 0b373e4d4 [PMFW-5398] [IMP] Core DLDO parameter tuning
+| - 155ee4a75 [PMFW-5411] [WKA] Apply 0.65V as minimum allowed SOC voltage
+| - 4b81ca8b2 [PMFW-4408] [WKA] BSOD 0x20001 occured when running S4 with VBS
+| - 2f315083f [PMFW-5199] [IMP] Update rule descriptions in PM log headers
+| - 718ba8e9a [PMFW-5362] [ETB] [RyzenMaster][CZN-FP6] SMU does not allow to set Slow PPT to 100W in 45W OPN
+| - 029798775 [PLAT-64297] [IMP] TSC counter stability on some platforms is sometimes not to expectations
+| - f3ace50ab [PMFW-5006] [IMP] VoltageController - FMax Override Causes VoltageLimiters Problems
+| - 51ebf543e [PMFW-4810] [ETB] CZN Add limiters to PPT, TDC and EDC - Fix PBO disabled default value
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.21.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.21.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.20.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 14/08/20
+|
+| * Changelist
+| - DXIO v55.755
+| - PMFW Kernel v19
+| - b37235cec [PLAT-67656] [NEW] Increment SPL value to support firmware anti rollback feature for production
+| - fa9f9cb46 [PMFW-5246] [NEW] Core CstateBoost PSM Adder
+| - b8603fce5 [PMFW-5310] [IMP] Update Preferred Core ordering algorithm
+| - 424a51817 [PMFW-5271] [IMP] Smartshift Incorrect SmuMetrics_StapmOriginalLimit
+| - 47ea11375 [PLAT-67911] [ITB] IC_ENABLE bit doesn't disable when config USB only and DP mode
+| - f163eebfc [PMFW-5317] [IMP] Integrate DXIO-FW version 55.755.0 into SMU
+| - 6b5a94c78 [PMFW-5302] [IMP] FDDBTC not resetting dldo_fdd_config for each core
+| - 9d46c376c [PMFW-5292] [IMP] Refactor InitSystemConfig to be used during BIOS override
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.20.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.20.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.19.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 10/08/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - bd38f9423 [PMFW-5281] [IMP] Add FLLBTC to S0i3 save and restore
+| - 5acf7b2e2 [PMFW-5284] [ETB] 45W EVT Sec OPNs fail to boot (AC95)
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.19.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.19.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.18.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 07/08/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - 17bd6f0d3 [PMFW-4810] [IMP] CZN Add limiters to PPT TDC and EDC
+| - 2ea7054fd PLAT-65470] [IMP] After S0I3 resume + DMAr enable will BSOD_0x101 sometimes - Fix spacing
+| - a1bae3cd4 [PMFW-5248] [OPT] EDC CAC Weight Update
+| - 5ea785446 [PLAT-67010] [ETB] FllEnable is not set on S0i3Resume
+| - 0200792d6 [PLAT-67080] [ETB] B000A921 observed running s3 test in loop
+| - 686693b57 [PLAT-65927] [IMP] System hang at Black Screen when run Restart+MSC w/ Hook (HVCI enable)
+| - b12e98534 [PLAT-66428] [WKA] System hang when resume from S0i3 with Post Code Code: EA00E099
+| - 396d6df1a [PLAT-66012] [IMP] Without GFX_OFF to cause CRB cannot enter MSC
+| - 213272ace [PLAT-65780] [IMP] USB XHCI port0 can't disable on Type A Phy config
+| - 6b40d167a [PLAT-65470] [IMP] After S0I3 resume + DMAr enable will BSOD_0x101 sometimes
+| - c4417f4a1 [PMFW-4826] [IMP] PPT measured value is 0 when OS in P&D OC mode
+| - a0f415593 [PLAT-65982] [WKA] CZN FP6 Processor power management test fail
+| - d3ef561a3 [PMFW-4222] [IMP] Flush cache to SRAM on FwError, Updated SMU_SIZE usage
+| - 321c5540f [PMFW-5241] [NEW] Add DXIO EXT Data Section
+| - 8cd189e24 [PMFW-5209] [WKA] New sequence in SetCoreLdo to ensure P-State change
+| - e769cf340 [PMFW-4947] [NEW] Add GFX HT Fmax Controller
+| - 62e64b41e [PMFW-5239] [IMP] Shift more memory space from DATA to S0i3
+| - a4a2bb0a8 Revert "[PMFW-4499] [IMP] Fix Makefile to accommodate Jenkins parallel build"
+| - 29763edc3 [PMFW-5241] [NEW] Add DXIO EXT Data Section
+| - fd16d42cf Revert "[PMFW-4027] [IMP] RN FP6: Memory OC Fusing diabled not being enforced"
+| - 3c4f4f142 [PMFW-5195] [WKA] CPPC register values need to be restored after S0i3 resume
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.18.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.18.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.17.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 30/07/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - 4ef62dbb4 [PLAT-67323] [WKA] SMU stuck at 20D0 when running S5/S4 on Majolica board - Revert dxio_fw v55.754
+| - 5aa4a3ea2 [PMFW-5196] [IMP] FCH doesn't assert SLP_S3# in the end of S0i3 entry
+| - 58564929e [PMFW-5021] [IMP] FCLK DPM Should Update L3FasterThanDF on CLK Change
+| - 85d2277c9 [PMFW-5197] [ETB] PCR1 shadow copy incorrect with CPUOFF
+| - 824e8ea18 [PMFW-5181] [IMP] Port the bugcheck EF and unsafe shutdown fixes from Winston
+| - 9d9fa6944 [PLAT-67084] [IMP] L3 frequency is stuck at 4.125G on B6 proto part
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.17.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.17.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.16.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 28/07/20
+|
+| * Changelist
+| - DXIO v55.754
+| - PMFW Kernel v19
+| - f7905ae56 [PMFW-5174] [UTB] Use the FddBTC calibrated value in Core FDD calculation
+| - 5145c8aa5 [PMFW-4469] [UTB] CZN AM4 ConfigID swap
+| - a0bb670e8 [PLAT-66600] [ETB] CZN SMU feature enable message takes longer time than RN
+| - 1fe789108 [PMFW-5026] [NEW] Cezanne SmartShift with Navi14 Navi22 Navi23 DGPU
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.16.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.16.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.15.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 27/07/20
+|
+| * Changelist
+| - DXIO v55.754
+| - PMFW Kernel v19
+| - 506bcaef0 [PMFW-4947] [NEW] Add GFX HT Fmax Controller -Add GFX HTFmax fuses and Core HTFmax slope fuse
+| - ebcef5c5f [PMFW-5053] [IMP] CZN GfxDEM optimization
+| - 35327481e [PMFW-5113] [IMP] CZN Core DLDO Tweaks For EVT
+| - a7eaa1141 [PMFW-5084] [IMP] CZN TESTSMC Message Audit
+| - de7e9b05a Revert "[PMFW-4912] [IVB] Port GN B0 SetCoreLdo Change"
+| - ddd953f42 [PLAT-65353] [WKA] Tdiode-Tmon offset is violating spec on PlatSi/Proto
+| - 91f3472ce [PMFW-5073][IMP] Change the function fSMC_MSG_SetGfxDldoFddScalar to include FDD Offset
+| - 0f1cda96e [PMFW-5047] Integrate dxio_fw v55.754 into CZN PMFW release
+| - 5eed8d23d [PLAT-64158] [WKA] System cannot entry S0i3 after S4 w/ dGPU config
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.15.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.15.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.14.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 23/07/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - 3d778086c [PLAT-66763] [WKA] EVT 100-000000300-41/40 OPNs fail to boot running @ max FCLK/Mem Speed
+| - 4550044a3 [PMFW-5074] [ETB] CZN RLC checking incorrect message mask
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.14.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.14.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.13.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 17/07/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - 9d105cd26 [PMFW-4838] [NEW] Request to implement BTC for core mafdd
+| - 261d532e0 [PLAT-64929] [WKA] Max MEMCLK over 1600Mhz needs to MemoryTrain 800Mhz states at 0.75v Dacref
+| - 02dd86449 [PLAT-64929] [NEW] Update FastCldoBypass sequence
+| - cd4fd5703 [PMFW-4845] [NEW] SVI2 Phase Shedding implementation in the PMFW
+| - 7fc87cc9d [PMFW-4823] [UTB] DC BTC: SetVoltage
+| - 770ea63e7 [PMFW-4983][IMP] ROC constant reduction
+| - 79a60379b [PMFW-4821] [UTB] DC BTC: Change of operating voltage
+| - fe1ce5308 [PMFW-4573] [IMP] Cleanup AM4 AC CPR0 Hyst workaround
+| - 3470e8084 [PMFW-4997] [IMP] Cleanup VddioMemVoltage override in ConfigSocRail
+| - 5ba587f67 [PMFW-4980] [IMP] FastDMA SMU RLC sequence update - Improvement
+| - 9bc676c72 [PMFW-4912][IVB]Port GN B0 SetCoreLdo Change
+| - 413f86fba [PMFW-4973] [IMP] Ignore SLVERR on SMN write
+| - d0637b7b3 [PMFW-4977] [NEW] Port ACTON changes from RN to CZN
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.13.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.13.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.12.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 10/07/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - fa38f268e [PMFW-4980] [IMP] FastDMA SMU RLC sequence update
+| - f8f1ae09e [PLAT-63682] [IMP] [CZN AM4] Update STT parameters in AGM/AMD SystemDeck
+| - 98de26faf [PMFW-4976] [UTB] STAPM Controller needs to use the MIN limit of OPN and MOC override
+| - d317d1304 [PMFW-4942] [IMP] BIOSSMC_MSG_GetSustainedPowerAndThmLimit does not return SustainedPower correctly
+| - 1fc759097 [PMFW-4974] [IMP] GFXDEM sensitivity model calculation
+| - 20923b8bd [PLAT-66262] [ETB] [CZN] Unexpected Pstates when using 45W
+| - e75bfd6d7 [PMFW-4869][IMP]Change bit definitions for CPUPWROK and CPUPWROKRAW
+| - 13ce6c387 [PMFW-4968] [OPT] DDR Phy SIDD Area Scalar Update
+| - a96612ff1 [PMFW-4877] [OPT] Update FIT COEFF_A To Match CZN Value
+| - eb5866bc9 [PMFW-4963] [IMP] Test message to flush cache to SRAM
+| - 6b26ffe28 [PMFW-4955] [IMP] FCLK DPM Should Update L3FasterThanDF on CLK Change
+| - 1200a851f [PMFW-4628] [OPT] Update Cezanne FP6 Fan Policy and Alphaup Value
+| - 0a832465d [PMFW-4869][IMP]PwrMgt_Status[0] should reflect CpuPwrOkRaw
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.12.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.12.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.11.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 26/06/20
+|
+| * Changelist
+| - DXIO v55.749
+| - PMFW Kernel v19
+| - 4a217cec7 [PMFW-4532] [WKA] CZN AM4 and FP6: VDCI not being tuned after PC6 exit if fixed frequency
+| - 1dcebfb1d [PMFW-4909] [IMP] Update PMC_PCR usage with union structures
+| - 73a743b9d [PMFW-4903] [OPT] Alpha Filter Tuning for Metrics Table
+| - 7673af76a [PLAT-65419] [IMP] NVME shutdown sequence improvement for S0i3 Unsafe Shutdown issue
+| - fbb41e9fb [PLAT-65421] [WKA] PCIe Clock turn on after PERST# de-assert during S0i3 resume
+| - 5d8c52486 [PMFW-4893] [UTB] Error in HARD_RESETB_COMING in all RSMU instances
+| - cb002abcf [PMFW-4856] [IMP] Actually memory speed over target memory speed in AGM tool
+| - 88d3ad456 [PMFW-4697] [IMP] Integrate DXIO-FW version 55.749.0 into SMU
+| - 6bf04dc52 [PMFW-4900] [UTB] Update BandGap programming sequence
+| - 067a74129 [PMFW-4890] [NEW] Update fuse header to add Enable_PRO_Check fuse
+| - 9fb9485f7 [PMFW-4854] [ETB] [CZN] BIOSSMC_MSG_GetSustainedPowerAndThmLimit not returning SustainedPower correctly
+| - 8bf10ed07 Revert "[PMFW-4862] [OPT] CZN Core DLDO Settings Rev3 Take1"
+| - 6ce29038f [PMFW-4822] [IVB] DC BTC Failure of PSM range check not exiting with default output
+| - 9a8795daf [PLAT-63797] [ETB] [CZN] System hangs at PC:B000AC95 on Majolica when enabled Fast CLDO Bypass
+| - c37c2c5ca [PMFW-4866] [IMP] Save/Restore CPPC enable register as part of S0i3
+| - 9b74e07bf [PMFW-4443] [IMP] Make package not copying Kernel src and DXIO header properly
+| - dd8d5251f [PMFW-4779] [IMP] Remove PSR/1 reset to 0 on PC6 exit
+| - 1d96f569e [PMFW-4847] [IMP] [CZN] Expose SMU Internal Registers for Core C-States
+| - 69d9fe495 [PMFW-4871] [IVB] Allow Prochot Entry at S0i3 Resume
+| - 371cceb38 [PMFW-4435] [IMP] Initial Coverity Scan For Cezanne
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.11.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.11.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.10.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 19/06/20
+|
+| * Changelist
+| - DXIO v55.747
+| - PMFW Kernel v19
+| - 15b964135 [PMFW-4862] [OPT] CZN Core DLDO Settings Rev3 Take1
+| - 0c6b0da55 [PMFW-4628] [OPT] Update Cezanne FP6 Fan Policy and Alphaup Value
+| - af1f8588b [PMFW-4837] [WKA] Modify SmuMetrics_t table needs to be the same for Renoir and Cezanne
+| - a1bfbed35 [PMFW-4686] [IMP] Remove Peak Temperature from AMD System Deck
+| - 27dae9ce1 [PMFW-4818] [IMP] Wait for voltage decreases in DCBTC
+| - 6aff8a2d9 [PMFW-4256] [NEW] Add VCN residency to AGM - Add back VcnBusy residency
+| - 442f233fa [PLAT-64758] [IMP] ULV Voltage Offset Being Overwritten
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.10.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.10.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.9.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 12/06/20
+|
+| * Changelist
+| - DXIO v55.747
+| - PMFW Kernel v19
+| - 326719822 [PMFW-4808] [UTB] SuperVminmaxProg fuse is not being read with DLDO disabled
+| - cb45da326 [PMFW-4802] [ETB] Update FT_rev for FP6 secure part
+| - 3ed47b1e3 [PLAT-64634] [IMP] Fast PC6 restore(aka Divideby1) configuration issue
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.9.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.9.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.8.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 10/06/20
+|
+| * Changelist
+| - DXIO v55.747
+| - PMFW Kernel v19
+| - 173aa825f [PMFW-4561] [IMP] Considering floorplan thermals for preferred core feature
+| - f4c25430d [PMFW-4588] [OPT] FLLDD residency is too high with current L3_FLL_SCALAR value
+| - 8cb6f6893 [PMFW-4788] [IMP] Update FP6 EDC limits
+| - 0d436ee80 [PMFW-4775] [IMP] Remove ReadGfxOffSavedState test message
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.8.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.8.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.7.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 05/06/20
+|
+| * Changelist
+| - DXIO v55.747
+| - PMFW Kernel v19
+| - dbdf639b9 [PLAT-63073] [IMP] Add SMU message to identify S0i3 resume state before unlock HDD password
+| - 5f50ea26a [PMFW-4576] [IMP] Remove PC6 Postcodes from STB
+| - 19d0532fd [PMFW-4552] [IMP] Add a DXIO API for PHY FW Transfer using DMA
+| - 60411360f [PMFW-4696] [OPT] CZN Core DLDO Settings v2
+| - b0e9a0f75 [PMFW-4685] [ETB] Correctly Send All GC RM Related Fuses During GFXOFF Exit
+| - 28da33c06 [PLAT-64457] [ETB] Type-C functional fail on CZN FP6
+| - 155b7616d [PMFW-4564] [WKA] Add 5 PSM to AC Guardband on PlatSi for CPPC battery saver stability
+| - 1b54e6838 [PMFW-4480] [IMP] Add Interrupt Rate Monitor (IRM) to AGM
+| - 5c51628c1 [PMFW-4544] [IMP] GfxDEM Changes and code cleanup for feature enablement - Update AGM header
+| - de88b9f6a [PMFW-4625] [UTB] Update Temperature Alpha Filter - Remove thermal trip override sequence
+| - 7d78ee33e [PMFW-4625] [UTB] Update Temperature Alpha Filter
+| - fb1ad9115 [PMFW-4626] [ETB] CpbDisable paging error on bootup
+| - 27296181c [PMFW-4589] [ETB] Core and L3 power calculation under reporting
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.7.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.7.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.6.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 29/05/20
+|
+| * Changelist
+| - DXIO v55.747
+| - PMFW Kernel v19
+| - f42a8b863 [PMFW-4569] [ETB] [CZN-AM4] Core C-state Timers Initialized to FP6 Values on AM4 Bootup
+| - 5904a8396 [PMFW-4544] [IMP] GfxDEM changes and code cleanup for feature enablement
+| - 563897a85 [PMFW-4469] [OPT] [CZN] Create a new OPN config for 65W AM4
+| - ecb6a2ef7 [PMFW-4537] [UTB] Integrate DXIO-FW version 55.747.0 into SMU
+| - 45a79cb93 [PMFW-4188] [WKA] Change MemClk to 667MHz for Wifi OTA
+| - 3e2a6eae0 [PMFW-4409] [UTB] Add BypassCLDO to s0i3 exit
+| - 6fe1d6495 [PLAT-63964][WKA]NVME Abrupt shutdown sequence improvement for S0i3 Unsafe Shutdown issue
+| - 2cb76b45d [PMFW-4508] [NEW] Add PostCode Parser Script
+| - 6a4711b5a [PMFW-4410] [NEW] Log error if a new message is sent to a busy message port
+| - 456b5ac3c [PMFW-1833] [IMP] GfxClk Bypass Optimization
+| - c6a2c157d [VMR Port] 0df568e8e [PMFW-4534] [IMP] APML static analysis bug fixes and improvements
+| - 670fa09ab [VMR Port] 176327641 [PMFW-4487] [UTB] Initialize DroopSyncSelect settings
+| - f95ad17c4 [PMFW-4563] [IMP] [AM4] Set VDDOFF voltage to 0V
+| - aff90b06e [PLAT-63613] [OPT] [CZN] Disable Loadstep and Loadrelease in DF
+| - 855de9726 [PMFW-4543] [OPT] CZN DC BTC: Upper bound to 100mV
+| - 84bd91161 [PLAT-63493] [IMP] BIOS message to enable Walle-Lite dpm handler
+| - 7145dbf4b [PMFW-4263] [UTB] Effective Frequency over reporting with PC6 enabled
+| - 6984e2c0b [PMFW-4533] [ETB] AGM Reports High CPPC Max Values with default OS setting
+| - 0d97cfc70 [PMFW-4505] [OPT] Update Cezanne Core EDC parameters to values from Vermeer
+| - 6a85c4368 [PMFW-4524] [OPT] Update DC BTC PSM range
+| - ae26d2405 [PLAT-63370] [WKA] New FSDL for external xHCI device to force enter to D3 during S0i3
+| - 9098036c9 [PMFW-4432] [UTB] Integrate DXIO-FW version 55.745.0 into SMU
+| - c497713a8 [PMFW-4119] [IMP] Add spi registers to s0i3 save/restore sequence
+| - 22bd043c0 [PMFW-4403] [IMP] Cumulative SourceID update for RN
+| - 1e7806ee4 [PMFW-4399] [IMP] Update fSMC_MSG_SetPptAndSplSoftMaxLimit limit from unit32_t to float
+| - 0fba224e6 [PMFW-3875] [IMP] VDDOFF Entry and Exit sequence optimizing
+| - 2e74661f7 [PMFW-4379] [UTB] Reset DCFCLK SoftMin 0 when monitor is off
+| - 0b4e3eaf2 [PMFW-4245] [UTB] SocLevelToFclkDpmLookup initialize error
+| - 93e4fa254 [VMR Port] 6c87854d6 [PMFW-4472] [IVB] Add core check for UpdateCoreCstates
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.6.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.6.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.5.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 22/05/20
+|
+| * Changelist
+| - DXIO v55.741
+| - PMFW Kernel v19
+| - 17d650593 [PMFW-4453] [OPT] Set VDDOFF voltage to 0V for FP6
+| - aebf7fe5e [PMFW-4211] [IMP] Move few functions from TEXT to EXT1 section
+| - d68a1ba1b [PMFW-4499] [IMP] Fix Makefile to accommodate Jenkins parallel build
+| - d020765b2 [PMFW-4256] [NEW] Add VCN residency to AGM
+| - a4637e018 [PMFW-4489] [IMP] Cleanup Cclk controller - Cleanup VminFrequency
+| - 3fe333561 [PMFW-4489] [IMP] Cleanup Cclk controller - Move L3 check earlier in FLLBTC sequence
+| - 053cede79 [PMFW-4489] [IMP] Cleanup Cclk controller - Move InitWLBAndL2SuperVmin to EnableDLDO
+| - 819d6547f [PMFW-4489] [IMP] Cleanup Cclk controller - Remove WKA PLAT-52009 and unused variables
+| - 19d8a7192 [PMFW-4489] [IMP] Cleanup Cclk controller - Remove CoreDis
+| - c8e4445ee [PMFW-4441] [IMP] GFX FLL Vref should be overridden to 0V in OC mode
+| - addbdf311 [PLAT-63844] [ETB] VDCI3 min_sync_depth must be 4 at low voltage
+| - 7262d4e07 [PMFW-4474] [WKA] Set Per Core Vmin Based on FT_Rev Fuse
+| - 1699989d7 [PMFW-4470] [ETB] Fix hardcored core mask values
+| - 0e6f25389 [PMFW-4476] [IMP] Link SMU Versioning with AutoSMU
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.5.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.5.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.4.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 15/05/20
+|
+| * Changelist
+| - DXIO v55.741
+| - PMFW Kernel v19
+| - Update SOC header to CL#1211045
+| - Port Renoir changes upto v55.63.0
+| - Port Vermeer changes upto v56.22.0
+| - [PMFW-4370] [UTB] Add CPPC registers to PC6 save/restore
+| - [PMFW-4367] [IMP] Poll for OS Boost requests instead of interrupts
+| - [PLAT-62729] [NEW] Add CBS option to override Fmin for Core and GFX
+| - [PMFW-4174] [UTB] EDC SOC Iddmax Vcn Cac value too large
+| - [PMFW-4123] [NEW] Program BG with CCX_BG_SlopeTrim during InitCldo
+| - [PMFW-4213] [IMP] Tweaks to CZN Core DLDO Settings Based on RN Tuning
+| - [PMFW-4434] [UTB] Add core enable check during UpdateOsCclkRequest
+| - [PMFW-4357] [IMP] Implement stall when MP1 sees SLVERRs
+| - [PMFW-4394] [IMP] Disable router ports for disabled cores
+| - [PMFW-4454] [UTB] Adjust VDCI rounding
+| - [PMFW-4439] [IMP] Update PPA owners for tuned parameters
+| - [PMFW-4412] [OPT] [CZN] Update Core C-States Timers for DC Mode
+| - [PMFW-4146] [IMP] Enable Thermal Test Mode for GFX
+| - [PMFW-4413] [OPT] [CZN] Update IRM Tuning Settings for AC Mode
+| - [PMFW-4446] [IMP] Adjust CPPC lowest non-linear performance calculation
+| - [PMFW-4440] [IMP] Add FllBtcCompleted variable for L3
+| - [PMFW-4447] [UTB] CPPC_SCALE_TO_FREQ needs to use CPPC_MAX_PERF
+| - [PMFW-4461] [IMP] Enable DLDO Pseudo Bypass
+| - [PLAT-63275] [ITB] CZN AM4 Memory OC stuck at post code E090 - Move Vddp and Vddm back to ucode0
+| - [PMFW-4459] [IMP] DLDO Bypass program RVDD_PSM_PARAM_ADDR_LOW with updated ClkDiv value
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.4.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.4.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.3.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 01/05/20
+|
+| * Changelist
+| - DXIO v55.737
+| - PMFW Kernel v19
+| - Port Renoir changes upto v55.61.0
+| - [PMFW-4179] [IMP] Initialize negative peak temperature after AGM clear table
+| - [PMFW-4251] [UTB] Fix disabling of CCA throttler for A0
+| - [PMFW-4250] [OPT] Scale L3 IDDMAX when in CstateBoost
+| - [PMFW-4252] [UTB] Fix hang when OS programs CPBDis on Core7
+| - [PMFW-4259] [IMP] Remove LDO_TIMING Hard Code in ConfigSocRail
+| - Revert "[PMFW-4226] [IMP] Remove GPIO pin toggle in s0i3 resume" (Until DXIO fix is available)
+| - [PMFW-3931] [UTB] Add SuperVminmax support - Add enablement through fuse
+| - [PMFW-4271] [UTB] Change VDDM_0V sequence and go back to old LdoSel
+| - [PMFW-4353] [UTB] Properly use TargRladr value when L3 AFLL is enabled
+| - [PMFW-4253] [UTB] Restore Core PMI programming during CCXLateInit
+| - [PMFW-4359] [UTB] L3 FLL BTC fixes
+| - [PMFW-4360] [IMP] Make HTFMax limit equal FMax when disabled
+| - [PMFW-4146] [IMP] Enable Thermal Test Mode for GFX
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.3.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.3.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 64.2.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 26/04/20
+|
+| * Changelist
+| - DXIO v55.737
+| - PMFW Kernel v19
+| - [PMFW-4241] [UTB] Update CLDO LdoSel EXT_CHAIN0 and 1 mask
+| - [PMFW-4242] [IMP] Add workspace cleanup to SMU testFW building process
+| - [PMFW-4244] [UTB] Fix Cclk Effective Frequency during DataCaclulation
+| - [PLAT-54190] [WKA] SMU to configure DF_Pstate level (sets to max) based on fuse file on S0i3 resume - Pullup Voltage
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.2.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.2.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
+
++---------------------------+
+| Version 64.1.0 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 24/04/20
+|
+| * Changelist
+| - DXIO v55.737
+| - PMFW Kernel v19
+| - Port Renoir changes upto v55.59.0
+| - Port Vermeer changes upto v56.21.0
+| - [PMFW-4172] [NEW] Add CI_CORE entry to AGM table
+| - [PMFW-4173] [IMP] Map CPPC lowest-non-linear performance to IdleFreq
+| - [PMFW-4176] [OPT] EDC SOC Iddmax Vcn Cac value update
+| - [PMFW-4184] [NEW] Implement Alpha Filter for Cezanne FP6 and AM4
+| - [PMFW-4186] [OPT] Provide Initial Sidd Temperature Slope Values
+| - [PMFW-4085] [IMP] STT 2.1 on CZN AM4 Update STT parameter table in BIOS FW
+| - [PMFW-4193] [OPT] Verify and update RDI mapping for CZN
+| - [PMFW-4155] [NEW] Add Items To SLT Logging
+| - [PMFW-4199] [ETB] Write LDO_SEL Signals for CCX Chain1 During CLDO Programming
+| - [PMFW-4222] [IMP] Flush cache to SRAM on FwError
+| - [PMFW-4226] [IMP] Remove GPIO pin toggle in s0i3 resume
+| - [PMFW-4194] [IMP] Use PendingDisable/EnableMask instead of Disable during ThermalTestMode
+| - [PMFW-4239] [ETB] Fix hang when only FCLK DPM and DATA CALC are enabled
+| - Remove ChXiCfg0 programming in ccx_reset
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.1.0.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.1.0.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
diff --git a/cezanne/PSP/TypeId0x00_CezannePublicKey.tkn b/cezanne/PSP/TypeId0x00_CezannePublicKey.tkn
new file mode 100644
index 0000000..bef4038
--- /dev/null
+++ b/cezanne/PSP/TypeId0x00_CezannePublicKey.tkn
Binary files differ
diff --git a/cezanne/PSP/TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin b/cezanne/PSP/TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin
new file mode 100644
index 0000000..d585878
--- /dev/null
+++ b/cezanne/PSP/TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x01_PspBootLoader_CZN.sbin b/cezanne/PSP/TypeId0x01_PspBootLoader_CZN.sbin
new file mode 100644
index 0000000..88e0b1c
--- /dev/null
+++ b/cezanne/PSP/TypeId0x01_PspBootLoader_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x02_PspOS_CZN.sbin b/cezanne/PSP/TypeId0x02_PspOS_CZN.sbin
new file mode 100644
index 0000000..d5ce766
--- /dev/null
+++ b/cezanne/PSP/TypeId0x02_PspOS_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x03_PspRecoveryBootLoader_CZN.sbin b/cezanne/PSP/TypeId0x03_PspRecoveryBootLoader_CZN.sbin
new file mode 100644
index 0000000..dba6115
--- /dev/null
+++ b/cezanne/PSP/TypeId0x03_PspRecoveryBootLoader_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x08_SmuFirmware_CZN.csbin b/cezanne/PSP/TypeId0x08_SmuFirmware_CZN.csbin
new file mode 100644
index 0000000..8055bb5
--- /dev/null
+++ b/cezanne/PSP/TypeId0x08_SmuFirmware_CZN.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x09_SecureDebugUnlockKey_CZN.stkn b/cezanne/PSP/TypeId0x09_SecureDebugUnlockKey_CZN.stkn
new file mode 100644
index 0000000..a7720b4
--- /dev/null
+++ b/cezanne/PSP/TypeId0x09_SecureDebugUnlockKey_CZN.stkn
Binary files differ
diff --git a/cezanne/PSP/TypeId0x0C_FtpmDrv_CZN.csbin b/cezanne/PSP/TypeId0x0C_FtpmDrv_CZN.csbin
new file mode 100644
index 0000000..adcf035
--- /dev/null
+++ b/cezanne/PSP/TypeId0x0C_FtpmDrv_CZN.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x12_SmuFirmware2_CZN.csbin b/cezanne/PSP/TypeId0x12_SmuFirmware2_CZN.csbin
new file mode 100644
index 0000000..6df38e3
--- /dev/null
+++ b/cezanne/PSP/TypeId0x12_SmuFirmware2_CZN.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x13_PspEarlyUnlock_CZN.sbin b/cezanne/PSP/TypeId0x13_PspEarlyUnlock_CZN.sbin
new file mode 100644
index 0000000..ab892ad
--- /dev/null
+++ b/cezanne/PSP/TypeId0x13_PspEarlyUnlock_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x20_HwIpCfg_CZN_A0.sbin b/cezanne/PSP/TypeId0x20_HwIpCfg_CZN_A0.sbin
new file mode 100644
index 0000000..1716272
--- /dev/null
+++ b/cezanne/PSP/TypeId0x20_HwIpCfg_CZN_A0.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x21_PspIkek_CZN.bin b/cezanne/PSP/TypeId0x21_PspIkek_CZN.bin
new file mode 100644
index 0000000..3275407
--- /dev/null
+++ b/cezanne/PSP/TypeId0x21_PspIkek_CZN.bin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x22_SecureEmptyToken.bin b/cezanne/PSP/TypeId0x22_SecureEmptyToken.bin
new file mode 100644
index 0000000..7de9e36
--- /dev/null
+++ b/cezanne/PSP/TypeId0x22_SecureEmptyToken.bin
@@ -0,0 +1 @@
+ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
\ No newline at end of file
diff --git a/cezanne/PSP/TypeId0x24_SecurePolicyL0_CZN.sbin b/cezanne/PSP/TypeId0x24_SecurePolicyL0_CZN.sbin
new file mode 100644
index 0000000..321b6f7
--- /dev/null
+++ b/cezanne/PSP/TypeId0x24_SecurePolicyL0_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x25_Mp2Fw_CZN.sbin b/cezanne/PSP/TypeId0x25_Mp2Fw_CZN.sbin
new file mode 100644
index 0000000..9c909ff
--- /dev/null
+++ b/cezanne/PSP/TypeId0x25_Mp2Fw_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x28_PspSystemDriver_CZN.sbin b/cezanne/PSP/TypeId0x28_PspSystemDriver_CZN.sbin
new file mode 100644
index 0000000..bfeeb11
--- /dev/null
+++ b/cezanne/PSP/TypeId0x28_PspSystemDriver_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x29_KvmEngineDummy.csbin b/cezanne/PSP/TypeId0x29_KvmEngineDummy.csbin
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/cezanne/PSP/TypeId0x29_KvmEngineDummy.csbin
diff --git a/cezanne/PSP/TypeId0x2D_AgesaRunTimeDrv_CZN.sbin b/cezanne/PSP/TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
new file mode 100644
index 0000000..2789120
--- /dev/null
+++ b/cezanne/PSP/TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN.csbin b/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN.csbin
new file mode 100644
index 0000000..2410580
--- /dev/null
+++ b/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin b/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
new file mode 100644
index 0000000..eaad0b2
--- /dev/null
+++ b/cezanne/PSP/TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x3C_VbiosBootLoader_CZN.sbin b/cezanne/PSP/TypeId0x3C_VbiosBootLoader_CZN.sbin
new file mode 100644
index 0000000..a8c8fb6
--- /dev/null
+++ b/cezanne/PSP/TypeId0x3C_VbiosBootLoader_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x44_UnifiedUsb_CZN.sbin b/cezanne/PSP/TypeId0x44_UnifiedUsb_CZN.sbin
new file mode 100644
index 0000000..f36e7ed
--- /dev/null
+++ b/cezanne/PSP/TypeId0x44_UnifiedUsb_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x45_SecurePolicyL1_CZN.sbin b/cezanne/PSP/TypeId0x45_SecurePolicyL1_CZN.sbin
new file mode 100644
index 0000000..1e28e50
--- /dev/null
+++ b/cezanne/PSP/TypeId0x45_SecurePolicyL1_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x47_DrtmTA_CZN.sbin b/cezanne/PSP/TypeId0x47_DrtmTA_CZN.sbin
new file mode 100644
index 0000000..7f2924a
--- /dev/null
+++ b/cezanne/PSP/TypeId0x47_DrtmTA_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x50_KeyDbBl_CZN.sbin b/cezanne/PSP/TypeId0x50_KeyDbBl_CZN.sbin
new file mode 100644
index 0000000..77b8ad7
--- /dev/null
+++ b/cezanne/PSP/TypeId0x50_KeyDbBl_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x51_KeyDbTos_CZN.sbin b/cezanne/PSP/TypeId0x51_KeyDbTos_CZN.sbin
new file mode 100644
index 0000000..0f515f1
--- /dev/null
+++ b/cezanne/PSP/TypeId0x51_KeyDbTos_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin b/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin
new file mode 100644
index 0000000..e20bd0c
--- /dev/null
+++ b/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x58_DmcuEramDcn21.sbin b/cezanne/PSP/TypeId0x58_DmcuEramDcn21.sbin
new file mode 100644
index 0000000..6643e54
--- /dev/null
+++ b/cezanne/PSP/TypeId0x58_DmcuEramDcn21.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x59_DmcuIntvectorsDcn21.sbin b/cezanne/PSP/TypeId0x59_DmcuIntvectorsDcn21.sbin
new file mode 100644
index 0000000..d2c1007
--- /dev/null
+++ b/cezanne/PSP/TypeId0x59_DmcuIntvectorsDcn21.sbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin b/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
new file mode 100644
index 0000000..afd8917
--- /dev/null
+++ b/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin b/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
new file mode 100644
index 0000000..1a7d4e7
--- /dev/null
+++ b/cezanne/PSP/TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin b/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
new file mode 100644
index 0000000..b1e217b
--- /dev/null
+++ b/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin b/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
new file mode 100644
index 0000000..ef5fc73
--- /dev/null
+++ b/cezanne/PSP/TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin b/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
new file mode 100644
index 0000000..448d457
--- /dev/null
+++ b/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin b/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
new file mode 100644
index 0000000..69ce19e
--- /dev/null
+++ b/cezanne/PSP/TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin b/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
new file mode 100644
index 0000000..2fbb5c6
--- /dev/null
+++ b/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin b/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
new file mode 100644
index 0000000..ff5e574
--- /dev/null
+++ b/cezanne/PSP/TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
Binary files differ
diff --git a/cezanne/PSP/TypeId0x73_PspBootLoader_AB_CZN.sbin b/cezanne/PSP/TypeId0x73_PspBootLoader_AB_CZN.sbin
new file mode 100644
index 0000000..ab435fa
--- /dev/null
+++ b/cezanne/PSP/TypeId0x73_PspBootLoader_AB_CZN.sbin
Binary files differ
diff --git a/cezanne/PSP/UcodePatch_CZN_A0.bin b/cezanne/PSP/UcodePatch_CZN_A0.bin
new file mode 100644
index 0000000..2d1dff2
--- /dev/null
+++ b/cezanne/PSP/UcodePatch_CZN_A0.bin
Binary files differ
diff --git a/cezanne/PSP/release_notes.txt b/cezanne/PSP/release_notes.txt
new file mode 100644
index 0000000..d079a2c
--- /dev/null
+++ b/cezanne/PSP/release_notes.txt
@@ -0,0 +1,215 @@
++---------------------------------------+
+| SMU Firmware Release Notes - CEZANNE |
++---------------------------------------+
+
++---------------------------+
+| Version 12 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 09/01/20
+|
+| * Changelist
+| - DXIO v55.715
+| - Upgrade Cezanne SOC header to Pre-LSF (SOC fusedoc v1.09)
+| - Port all Renoir changes upto v55.31.0
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.12.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.12.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 11 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 13/12/19
+|
+| * Changelist
+| - DXIO v55.713
+| - Add placeholder for NVME trap to match Renoir BIOSSMC
+| - Remove MTFmax
+| - Port all Vermeer changes upto v56.13.0
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.11.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.11.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 10 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 23/11/19
+|
+| * Changelist
+| - DXIO v55.713
+| - Upgrade Cezanne SOC header to LSD (SOC fusedoc v1.08)
+| - Add new fuses for CKS and DLDO fuses
+| - Update smu12_bios_if.h to sync with Renoir
+| - Port all Vermeer changes upto v56.11.0
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.10.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.10.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 9 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 25/10/19
+|
+| * Changelist
+| - DXIO v55.713
+| - PMFW Kernel v17
+| - Upgrade Cezanne SOC header to LSD (SOC fusedoc v1.04)
+| - Port all Renoir changes upto v55.28.0
+| - [WKA] Add RSMU core interrupt unit_id mapping
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.9.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.9.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 8 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 16/10/19
+|
+| * Changelist
+| - DXIO v55.712
+| - [DECZNEMU-32] MP1 initiates access to non-existing cores. Fix ccx component checker.
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.8.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.8.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 7 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 07/10/19
+|
+| * Changelist
+| - DXIO v55.712
+| - Port Vermeer changes selectively upto v56.9.0
+| - Add MP1 fuses for MTFmax and HTFmax
+|
+| * Issues
+| - Core CKS and DLDO are disabled due to missing fuses
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.7.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.7.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 6 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 22/09/19
+|
+| * Changelist
+| - DXIO v55.709
+| - Kernel v16
+| - Update fuses.h using soc_fusedoc.csv v1.04
+| - Port all Renoir changes upto v55.22.0
+|
+| * Issues
+| - Core CKS and DLDO are disabled due to missing fuses
+| - Latest SOC reg header file still contains duplicate pmreg_initkg struct
+|
+| * Files
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne.rev64.0.6.zip
+| - \\atlvsmb1\smu_rel\smu12\cezanne\cezanne_sources.rev64.0.6.tar.gz
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 5 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 27/08/19
+|
+| * Changelist
+| - DXIO v55.701
+| - Porting PMFW-2034 - COH timer updates.
+| - Remove RestoreCcxInterruptRegisters function. Not needed in CZN.
+| - Porting PMFW-1120 - Add SMU message for "on the fly" CPU FMax Override and BIOS Fmax Override.
+| - Remove hardcoded CCX mask.
+|
+| * Files
+| -
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 4 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 26/08/19
+|
+| * Changelist
+| - DXIO v55.701
+| - Porting PMFW-2076 - Improve accuracy of pow_slow in core DLDO CI LUT calculations.
+| - Porting PMFW-2061 - L3CLK AFLL. Remove L3 CKS.
+| - Porting PMFW-2060 - EDC controller update to account for 50% core CKS.
+| - Release 0.64.0.4. Porting PMFW-2402 - Add 16 new core DPM CAC weights to fill in the new reserved weights registers. Cleanup files.
+|
+| * Files
+| -
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 3 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 19/08/19
+|
+| * Changelist
+| - DXIO v55.701
+| - Update CPU_EXT_FAMILY to 0x0A
+|
+| * Files
+| -
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 2 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 16/08/19
+|
+| * Changelist
+| - DXIO v55.701
+| - Temporary workaround for simulation. Remove CCX1 content from RsmuJobTable.
+|
+| * Files
+| -
+|
++-----------------------------------------------------------------------------------------------------------
+
++---------------------------+
+| Version 1 |
++---------------------------+-------------------------------------------------------------------------------
+| * Date (dd/mm/yy)
+| 14/08/19
+|
+| * Changelist
+| - DXIO v55.701
+| - Cezanne Initial Delivery
+|
+| * Files
+| -
+|
++-----------------------------------------------------------------------------------------------------------
