commit cf0d24a4e9f87d0bdea4dfb6c4681fbed951f37a
author Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Wed Mar 01 03:56:34 2023
committer Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> Fri Mar 03 02:05:25 2023
tree 452dd3aae16116b38b890783cb6ec503f4d0716a
parent 3c52c6e895c5f40387755c9adab04c4288201282

soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit

This version adds scramble switch to support both production build and
serial build, and also fixes fast-k single rank wrong register bit.

BUG=b:269049451,b:267590318
TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass

(cherry picked from commit 65c8e9a26b25324b2f2239a25f82b5aef8b30029)

Original-Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Original-Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
GitOrigin-RevId: 65c8e9a26b25324b2f2239a25f82b5aef8b30029
Change-Id: I8223b5dd1a9abca80a9437f731450ceffc3842cd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/blobs/+/4303031
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Commit-Queue: Reka Norman <rekanorman@chromium.org>