flashchips.c: resync MX25U6435E/F with upstream
Upstream/cros have the same erase block sizes, but they are
expressed differently. Use the expressions from upstream since
they make the size in MiB easy to read.
Use spi_disable_blockprotect_bp3_srwd as the unlock function:
Table 6 in the MX25U6435E datasheet (rev 1.5) lists bit 7 of
the status register as status register write protect, so
spi_disable_blockprotect_bp3_srwd should be used to disable it.
Syncs the chip with upstream at
`commit b05c9b18452e3c73e80d0abd5194928d224c3d1b`
BUG=b:166294558
BRANCH=none
TEST=builds
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Change-Id: I610643ad006263b7de69360e3e3f7bb30c39ab02
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2725869
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
1 file changed