tree 6bd3d8d3129295b515d48defafafbc72aca9e736
parent db95fa971a115361f91db8fd78fb11d8d5c1ec45
author Sergii Dmytruk <sergii.dmytruk@3mdeb.com> 1636322712 +0200
committer Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> 1652650462 +0000

UPSTREAM: dummyflasher: add SR2 and SR3 emulation harness

Prepare everything for emulating SR2 and SR3 for chips that have it.

This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.

BUG=none
BRANCH=none
TEST=check how input value affects status registers of emulated chip

flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
        grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
        grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
        grep 'Initial status register'

Mind that at this point there are no chips that emulate more than one
status register.

Original-Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Original-Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
(cherry picked from commit fa2cf255ec587f02baf987f21ab6d01de5db8c8e)

Change-Id: I129105822a2da2f6318a24ce333f9cf67f9f4135
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3641347
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>