tree 03ff3ec5f2aab6d2de7e512c6b8f14cf7750c99d
parent b5dee7a32f8542df1f08f45527816d63d631ba93
author Edward O'Callaghan <quasisec@chromium.org> 1551760073 +1100
committer chrome-bot <chrome-bot@chromium.org> 1551915227 -0800

Partial backport of 'dummyflasher: Add a status register to SPI chips'

Here we renames 'JEDEC_RDSR_BIT_WIP' bit flag to 'SPI_SR_WIP' as well
as introduce the flags:

```
 /* Status Register Bits */
 #define SPI_SR_WIP	(0x01 << 0)
 #define SPI_SR_WEL	(0x01 << 1)
 #define SPI_SR_AAI	(0x01 << 6)
```
to spi.h for latter use in follow up resync commits.

This is a partial backport of the upstream `commit 5e695ab`.

There should be no semantic changes resulting from this at
runtime!

BUG=chromium:478356
BRANCH=none
TEST=still builds

Change-Id: Ifd917f25c9ddecaae938487218077b07206cec77
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1502473
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Sam McNally <sammc@chromium.org>