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chromium / chromiumos / third_party / flashrom / refs/heads/stabilize-7134.B
commited32d7b83865cf45a4f566608601c06368c16c72[log] [tgz]
authorDuncan Laurie <dlaurie@chromium.org>Wed May 27 18:28:18 2015
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>Wed May 27 23:18:32 2015
treee46477b0906e38cdcb498e4a686719d00a7b36ba
parent6e15a5341ed3f5c623fbd493db764fe2e448b1f4 [diff]
w25q128: Support write protect ranges for normal SPI access

This adds the write protect ranges to the W25Q128FV and W25Q128FW
in the "normal" chip definition so it can be used over servo with a
real SPI interface instead of the irritatingly limited hwseq interface.

Also add the set of write protect ranges that are used if the complement
protect bit is set in SR2 which was not accounted for in the original
commit adding ranges to this chip.

Also mark the W25Q128FV chip as tested now that I have been able to
verify read/write/erase/protect functionality via servo.

BUG=chrome-os-partner:37711
BRANCH=none
TEST=test read/write/erase/protect of W25Q128FV over servo

Change-Id: Iadd103ad924d79b80061e958a79bee022e9db71d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273551
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2 files changed
tree: e46477b0906e38cdcb498e4a686719d00a7b36ba
  1. Documentation/
  2. tests/
  3. util/
  4. .gitignore
  5. 82802ab.c
  6. a25.c
  7. arch.h
  8. at25.c
  9. atahpt.c
  10. big_lock.c
  11. big_lock.h
  12. bitbang_spi.c
  13. board_enable.c
  14. buspirate_spi.c
  15. cbtable.c
  16. check.h
  17. chipdrivers.h
  18. chipset_enable.c
  19. cli_classic.c
  20. cli_mfg.c
  21. cli_output.c
  22. COPYING
  23. coreboot_tables.h
  24. cros_ec.c
  25. cros_ec.h
  26. cros_ec_commands.h
  27. cros_ec_dev.c
  28. cros_ec_dev.h
  29. cros_ec_i2c.c
  30. cros_ec_lock.c
  31. cros_ec_lock.h
  32. cros_ec_lpc.c
  33. csem.c
  34. csem.h
  35. dediprog.c
  36. dmi.c
  37. drkaiser.c
  38. dummyflasher.c
  39. ene_lpc.c
  40. fdtmap.c
  41. fdtmap.h
  42. file.c
  43. file.h
  44. flash.h
  45. flashchips.c
  46. flashchips.h
  47. flashrom.8
  48. flashrom.c
  49. fmap.c
  50. fmap.h
  51. ft2232_spi.c
  52. gfxnvidia.c
  53. hwaccess.c
  54. hwaccess.h
  55. ich_descriptors.c
  56. ich_descriptors.h
  57. ichspi.c
  58. internal.c
  59. ipc_lock.c
  60. ipc_lock.h
  61. it85spi.c
  62. it87spi.c
  63. jedec.c
  64. layout.c
  65. layout.h
  66. linux_i2c.c
  67. linux_spi.c
  68. locks.h
  69. m29f400bt.c
  70. Makefile
  71. mcp6x_spi.c
  72. mec1308.c
  73. nic3com.c
  74. nicintel.c
  75. nicintel_spi.c
  76. nicnatsemi.c
  77. nicrealtek.c
  78. ogp_spi.c
  79. opaque.c
  80. pcidev.c
  81. physmap.c
  82. pm49fl00x.c
  83. power.c
  84. power.h
  85. PRESUBMIT.cfg
  86. print.c
  87. print_wiki.c
  88. processor_enable.c
  89. programmer.c
  90. programmer.h
  91. raiden_debug_spi.c
  92. rayer_spi.c
  93. README
  94. README.chromiumos
  95. s25f.c
  96. satamv.c
  97. satasii.c
  98. sb600spi.c
  99. search.c
  100. search.h
  101. serial.c
  102. serprog.c
  103. sharplhf00l04.c
  104. spi.c
  105. spi.h
  106. spi25.c
  107. sst28sf040.c
  108. sst49lfxxxc.c
  109. sst_fwhub.c
  110. stm50flw0x0x.c
  111. udelay.c
  112. usb_device.c
  113. usb_device.h
  114. w29ee011.c
  115. w39.c
  116. wbsio_spi.c
  117. wpce775x.c
  118. writeprotect.c
  119. writeprotect.h