Google Git
Sign in
chromium / chromiumos / third_party / kernel-rebase-patches / 497b093e4daae2ab94921af7eaf51b3397e9d7f0 / . / ca72562aef88a8e0c4191d384ce9f427014e58c6383854aca022c52d.patch
blob: a21f1457c4a4069fa638467a9708d4d2f30322a9 [file] [log] [blame]
From 07afe52858da6956f73f58653f16a53120daf782 Mon Sep 17 00:00:00 2001
From: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Date: Wed, 11 May 2022 20:39:57 +0800
Subject: [PATCH] CHROMIUM: arm64: dts: mt8186: Add display device nodes
Add add display nodes for mt8186 SoC.
BUG=b:213000788
TEST=emerge-corsola sys-kernel/chromeos-kernel-5_15
Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Change-Id: If0ab31160f48e83dc12a9b6818c8bf5059c18bb8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3316136
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 132 +++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 36d512fb79e5ec98ccaacd7be67d45a8efdd4283..362482181cb15c7a945197141637885c34e096fa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include <dt-bindings/clock/mt8186-clk.h>
+#include <dt-bindings/gce/mt8186-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8186-memory-port.h>
@@ -19,6 +20,10 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -610,6 +615,16 @@ systimer: timer@10017000 {
clocks = <&clk13m>;
};
+ gce: mailbox@1022c000 {
+ compatible = "mediatek,mt8186-gce",
+ "mediatek,mt8192-gce";
+ reg = <0 0X1022c000 0 0x4000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ clock-names = "gce";
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8186-scp";
reg = <0 0x10500000 0 0x40000>,
@@ -1080,6 +1095,20 @@ mmsys: syscon@14000000 {
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8186-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
smi_common: smi@14002000 {
@@ -1113,6 +1142,49 @@ larb1: smi@14004000 {
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8186-disp-ovl",
+ "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
+ };
+
+ ovl0_2l: ovl@14006000 {
+ compatible = "mediatek,mt8186-disp-ovl-2l",
+ "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8186-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dpi0: dpi@1400a000 {
compatible = "mediatek,mt8186-dpi";
reg = <0 0x1400a000 0 0x1000>;
@@ -1131,6 +1203,56 @@ port {
};
};
+ ccorr0: ccorr@1400b000 {
+ compatible = "mediatek,mt8186-disp-ccorr",
+ "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ aal0: aal@1400c000 {
+ compatible = "mediatek,mt8186-disp-aal",
+ "mediatek,mt8183-disp-aal";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ gamma0: gamma@1400d000 {
+ compatible = "mediatek,mt8186-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ postmask0: postmask@1400e000 {
+ compatible = "mediatek,mt8186-disp-postmask",
+ "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ dither0: dither@1400f000 {
+ compatible = "mediatek,mt8186-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
@@ -1164,6 +1286,16 @@ &larb13 &larb14 &larb16 &larb17
#iommu-cells = <1>;
};
+ rdma1: rdma@1401f000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1401f000 0 0x1000>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
+ };
+
wpesys: clock-controller@14020000 {
compatible = "mediatek,mt8186-wpesys";
reg = <0 0x14020000 0 0x1000>;
--
2.38.3