FROMGIT: pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type

From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
write to the debounce registers of *any* gpio will block wake/interrupt
status generation for *all* gpios for a length of time that depends on
WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the Interrupt
Delivery bit (INTERRUPT_ENABLE) will read as 0.

In commit 4c1de0414a1340 ("pinctrl/amd: poll InterruptEnable bits in
enable_irq") we tried to fix this same "gpio Interrupts are blocked
immediately after writing debounce registers" problem, but incorrectly
assumed it only affected the gpio whose debounce was being configured
and not ALL gpios.

To solve this for all gpios, we move the polling loop from
amd_gpio_irq_enable() to amd_gpio_irq_set_type(), while holding the gpio
spinlock.  This ensures that another gpio operation (e.g.
amd_gpio_irq_unmask()) can read a temporarily disabled IRQ and
incorrectly disable it while trying to modify some other register bits.

Fixes: 4c1de0414a1340 pinctrl/amd: poll InterruptEnable bits in enable_irq
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit b85bfa246efd24ea3fdb5ee949c28e3110c6d299)

BUG=b:115610841
TEST=On grunt: Reboot while touching trackpad
     continue touching for > 15 seconds after boot
     Repeat at least 25 times
 => trackpad always continues to respond

Change-Id: I41b93faee9e2d7636e18864010ca12cebc8d40cd
Reviewed-on: https://chromium-review.googlesource.com/1239587
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Yu Zhao <yuzhao@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
1 file changed