FROMGIT: drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
receiver capabilities. For panels that use this new feature wait interval
would be increased by 512 ms, when spec is max 16 ms. This behavior is
described in table 2-158 of DP 1.4 spec address 0000eh.

With the introduction of DP 1.4 spec main link clock recovery was
standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.

To avoid breaking panels that are not spec compiant we now warn on
invalid values.

V2: commit title/message, masking all 7 bits, warn on out of spec values.
V3: commit message, make link train clock recovery follow DP 1.4 spec.
V4: style changes
V5: typo
V6: print statement revisions, DP_REV to DPCD_REV, comment correction
V7: typo
V8: Style
V9: Strip out DPCD_REV_XX into seperate patch

Signed-off-by: Matt Atwood <>
Reviewed-by: Rodrigo Vivi <>
Signed-off-by: Rodrigo Vivi <>
(cherry picked from commit 2f065d8ae918159791474049ab67a0cb85723b81 drm-tip)
Signed-off-by: Matt Atwood <>

TEST=Boot Meowth to Graphics

Change-Id: If900f0328553977746c48cab353fcb360443819d
Commit-Ready: Matthew S Atwood <>
Tested-by: Benson Leung <>
Reviewed-by: Dominik Behr <>
Reviewed-by: St├ęphane Marchesin <>
2 files changed