Revert "CHROMIUM: phy/mediatek: phy-mtk-dp: Adjust SSC delta HBR value setting for DP"

This reverts commit 0ddee78614246c7a0e7f0643166f84df8fab09eb.

Reason for revert: See b/326025335#comment26

Original change's description:
> CHROMIUM: phy/mediatek: phy-mtk-dp: Adjust SSC delta HBR value setting for DP
>
> Through reduce SSC delta HBR value to DP
>
> BUG=b:317314527
> Test=Use the single port Type-C to HDMI dongle connect to the 4K monitor is not garbage.
> UPSTREAM-TASK=b:326878753
>
> Change-Id: I3d2d53bbba0d4e1a62e0f81188d80f17bf1be618
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.corp-partner.google.com>
> Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5268741
> Commit-Queue: Fei Shao <fshao@chromium.org>
> Reviewed-by: Fei Shao <fshao@chromium.org>
> Tested-by: Fei Shao <fshao@chromium.org>

BUG=b:317314527, b:326025335

Change-Id: I579229da52a73055d93bb7f244efc5243d0ffe4a
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/6065288
Reviewed-by: Fei Shao <fshao@chromium.org>
Commit-Queue: Fei Shao <fshao@chromium.org>
Tested-by: Fei Shao <fshao@chromium.org>
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index a03579d6..d7024a1 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -78,9 +78,6 @@
 #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
 				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
 
-#define MTK_DP_PHY_DIG_DA_REG_14		(PHY_OFFSET + 0xd8)
-#define RG_XTP_glb_txpll_ssc_delta1_hbr         0x01fe02b0
-
 struct mtk_dp_phy {
 	struct regmap *regs;
 };
@@ -140,8 +137,6 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
 	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
 			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
 
-	regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_DA_REG_14,
-			   RG_XTP_glb_txpll_ssc_delta1_hbr);
 	return 0;
 }