UPSTREAM: mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset

There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spurious power IRQ which results in system instability.

Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

BUG=chromium:795946
TEST=Build kernel for Cheza

Change-Id: Id0a3f8d5232f9b7a767103a57386bff2d6c46850
Signed-off-by: Evan Green <evgreen@chromium.org>
(cherry picked from commit 401b2d06c4ed69f5d491f9297651bed3fbbfe69b)
Reviewed-on: https://chromium-review.googlesource.com/917604
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>