FROMLIST: x86/paravirt: Dont patch flush_tlb_single

native_flush_tlb_single() is not just INLVPG anymore. With
X86_FEATURE_INVPCID_SINGLE and KAISER enabled it flushes also the shadow
mapping. But even with KAISER disabled flushing the particular ASID is
the right thing to do.

Remove the paravirt patching for it.

Fixes: 1fde25dc8ef4 ("x86/mm/kaiser: Use PCID feature to make user and
kernel switches faster")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

(am from https://patchwork.kernel.org/patch/10078031/)

BUG=b:70026651
TEST=tryjob

Change-Id: Ieb9f9c4a449038ef43eb220228f4160478cd554f
Reviewed-on: https://chromium-review.googlesource.com/803863
Commit-Ready: Ke Wu <mikewu@google.com>
Tested-by: Ke Wu <mikewu@google.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Hugh Dickins <hughd@google.com>
(cherry picked from commit 3ff450a8697d3d52c38ade1f25b119d8ed24a448)
Reviewed-on: https://chromium-review.googlesource.com/820719
Trybot-Ready: Xuewei Zhang <xueweiz@google.com>
Commit-Queue: Xuewei Zhang <xueweiz@google.com>
Tested-by: Xuewei Zhang <xueweiz@google.com>
diff --git a/arch/x86/kernel/paravirt_patch_64.c b/arch/x86/kernel/paravirt_patch_64.c
index 8aa0558..0677bf8 100644
--- a/arch/x86/kernel/paravirt_patch_64.c
+++ b/arch/x86/kernel/paravirt_patch_64.c
@@ -9,7 +9,6 @@
 DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
 DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
 DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
-DEF_NATIVE(pv_mmu_ops, flush_tlb_single, "invlpg (%rdi)");
 DEF_NATIVE(pv_cpu_ops, clts, "clts");
 DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
 
@@ -62,7 +61,6 @@
 		PATCH_SITE(pv_mmu_ops, read_cr3);
 		PATCH_SITE(pv_mmu_ops, write_cr3);
 		PATCH_SITE(pv_cpu_ops, clts);
-		PATCH_SITE(pv_mmu_ops, flush_tlb_single);
 		PATCH_SITE(pv_cpu_ops, wbinvd);
 #if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUED_SPINLOCKS)
 		case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):