CHROMIUM: arm64: dts: rockchip: scarlet: Fix fw_wp polarity and pull

The firmware write-protect pin was (correctly) moved to a different GPIO
for Scarlet, but the polairty and pull-up were just copied from Gru. The
polarity actually switched for Scarlet and providing an internal pull-up
overpowers the signal with Scarlet's layout (because hardware engineers
apparently hate consistency, and also something something BOM cost).
This patch puts the correct settings in the device tree.

BUG=b:73356326
TEST=Booted Scarlet, confirmed crossystem wpsw_cur now always reports
the correct value.

Change-Id: Id272963d91f16e2fa8d5ecdd1ebba2c257e7d942
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/920774
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
(cherry picked from commit bc81de31661d4f56a7a4cc5eda6939c728ce3827)
Reviewed-on: https://chromium-review.googlesource.com/927184
Tested-by: Brian Norris <briannorris@chromium.org>
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index 94494f5..52d8088 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -436,7 +436,7 @@
 
 &firmware {
 	chromeos {
-		write-protect-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		write-protect-gpio = <&gpio0 13 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -632,7 +632,7 @@
 
 /* PINCTRL OVERRIDES */
 &ap_fw_wp {
-	rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
+	rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 };
 
 &bl_en {