BACKPORT: xhci: Workaround to get Intel xHCI reset working more reliably
Existing Intel xHCI controllers require a delay of 1 mS,
after setting the CMD_RESET bit in command register, before
accessing any HC registers. This allows the HC to complete
the reset operation and be ready for HC register access.
Without this delay, the subsequent HC register access,
may result in a system hang, very rarely.
Verified CherryView / Braswell platforms go through over
5000 warm reboot cycles (which was not possible without
this patch), without any xHCI reset hang.
This is based on the change done by
Rajmohan Mani <rajmohan.mani@intel.com>
(git am from http://article.gmane.org/gmane.linux.usb.general/132236)
BRANCH=None
BUG=chrome-os-partner:43921,chrome-os-partner:46294
TEST=Verified CherryView / Braswell platforms go through over
5000 warm reboot cycles, without any xHCI reset hang.
Change-Id: I27e167f4fca9c72d62b4c3f3f775f6a55f34a75f
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/306840
Commit-Ready: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 75b4d3105f382096d929b45a03fb7d84504658fd)
Reviewed-on: https://chromium-review.googlesource.com/308982
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
1 file changed
