CHROMIUM: phy: rockchip-typec: enable usb3 host after pipe ready
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.
Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume
Change-Id: I5bd6f53c57e876cc2e4cabf06433056683181f98
Signed-off-by: Wlliam wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
(cherry picked from commit dae9bb23976c07e31b611cbbd3d001ba2c77c99d)
Reviewed-on: https://chromium-review.googlesource.com/910248
1 file changed
