Intel BT 7265: optimize settling timer in wakeup flow.
This is firmware patch for Intel Bluetooth 7265 (StP D1)
StP D1 FW Patch Version: 0x39(57)
This patch contains the following fixes on previous 0x38(56):
- Relax the oscillator settling timer configuration (PLL Settling time: 330us to 1ms and OSC Settling time: 5ms to 7ms)
- Optimize LPM/ULPM threshold logic (LPM:18 to 24 slots, ULPM: 24 to 30 slots)
- Optimize patches in BC transaction interrupt handlers
BUG=b:64035404
TEST=the last bytes output by the command "hcitool cmd 3f 05" change:
- ......... 50 19 14 0F 38
+ ......... 50 19 14 0F 39
TEST=P0 and P1 sanity test cases and all are passed on Eve
Change-Id: Icca1bed0b2b8e0e473ce97524b55010dc29788ff
Signed-off-by: Amit K Bag <amit.k.bag@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/1332487
Reviewed-by: Dan Jaklich <djaklich@chromium.org>
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Andrew de los Reyes <adlr@chromium.org>
Commit-Queue: Dan Jaklich <djaklich@chromium.org>
Commit-Queue: Andrew de los Reyes <adlr@chromium.org>
Tested-by: Dan Jaklich <djaklich@chromium.org>
Tested-by: Andrew de los Reyes <adlr@chromium.org>
Trybot-Ready: Andrew de los Reyes <adlr@chromium.org>
2 files changed