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| .IX Title "LLC 1" |
| .TH LLC 1 "2006-03-13" "CVS" "LLVM Command Guide" |
| .SH "NAME" |
| llc \- LLVM static compiler |
| .SH "SYNOPSIS" |
| .IX Header "SYNOPSIS" |
| \&\fBllc\fR [\fIoptions\fR] [\fIfilename\fR] |
| .SH "DESCRIPTION" |
| .IX Header "DESCRIPTION" |
| The \fBllc\fR command compiles \s-1LLVM\s0 bytecode into assembly language for a |
| specified architecture. The assembly language output can then be passed through |
| a native assembler and linker to generate a native executable. |
| .PP |
| The choice of architecture for the output assembly code is automatically |
| determined from the input bytecode file, unless the \fB\-march\fR option is used to |
| override the default. |
| .SH "OPTIONS" |
| .IX Header "OPTIONS" |
| If \fIfilename\fR is \- or omitted, \fBllc\fR reads \s-1LLVM\s0 bytecode from standard input. |
| Otherwise, it will read \s-1LLVM\s0 bytecode from \fIfilename\fR. |
| .PP |
| If the \fB\-o\fR option is omitted, then \fBllc\fR will send its output to standard |
| output if the input is from standard input. If the \fB\-o\fR option specifies \-, |
| then the output will also be sent to standard output. |
| .PP |
| If no \fB\-o\fR option is specified and an input file other than \- is specified, |
| then \fBllc\fR creates the output filename by taking the input filename, |
| removing any existing \fI.bc\fR extension, and adding a \fI.s\fR suffix. |
| .PP |
| Other \fBllc\fR options are as follows: |
| .Sh "End-user Options" |
| .IX Subsection "End-user Options" |
| .IP "\fB\-\-help\fR" 4 |
| .IX Item "--help" |
| Print a summary of command line options. |
| .IP "\fB\-f\fR" 4 |
| .IX Item "-f" |
| Overwrite output files. By default, \fBllc\fR will refuse to overwrite |
| an output file which already exists. |
| .IP "\fB\-mtriple\fR=\fItarget triple\fR" 4 |
| .IX Item "-mtriple=target triple" |
| Override the target triple specified in the input bytecode file with the |
| specified string. |
| .IP "\fB\-march\fR=\fIarch\fR" 4 |
| .IX Item "-march=arch" |
| Specify the architecture for which to generate assembly, overriding the target |
| encoded in the bytecode file. See the output of \fBllc \-\-help\fR for a list of |
| valid architectures. By default this is inferred from the target triple or |
| autodetected to the current architecture. |
| .IP "\fB\-mcpu\fR=\fIcpuname\fR" 4 |
| .IX Item "-mcpu=cpuname" |
| Specify a specific chip in the current architecture to generate code for. |
| By default this is inferred from the target triple and autodetected to |
| the current architecture. For a list of available CPUs, use: |
| \&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR |
| .IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4 |
| .IX Item "-mattr=a1,+a2,-a3,..." |
| Override or control specific attributes of the target, such as whether \s-1SIMD\s0 |
| operations are enabled or not. The default set of attributes is set by the |
| current \s-1CPU\s0. For a list of available attributes, use: |
| \&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR |
| .IP "\fB\-\-disable\-fp\-elim\fR" 4 |
| .IX Item "--disable-fp-elim" |
| Disable frame pointer elimination optimization. |
| .IP "\fB\-\-disable\-excess\-fp\-precision\fR" 4 |
| .IX Item "--disable-excess-fp-precision" |
| Disable optimizations that may produce excess precision for floating point. |
| Note that this option can dramatically slow down code on some systems |
| (e.g. X86). |
| .IP "\fB\-\-enable\-unsafe\-fp\-math\fR" 4 |
| .IX Item "--enable-unsafe-fp-math" |
| Enable optimizations that make unsafe assumptions about \s-1IEEE\s0 math (e.g. that |
| addition is associative) or may not work for all input ranges. These |
| optimizations allow the code generator to make use of some instructions which |
| would otherwise not be usable (such as fsin on X86). |
| .IP "\fB\-\-enable\-correct\-eh\-support\fR" 4 |
| .IX Item "--enable-correct-eh-support" |
| Instruct the \fBlowerinvoke\fR pass to insert code for correct exception handling |
| support. This is expensive and is by default omitted for efficiency. |
| .IP "\fB\-\-stats\fR" 4 |
| .IX Item "--stats" |
| Print statistics recorded by code-generation passes. |
| .IP "\fB\-\-time\-passes\fR" 4 |
| .IX Item "--time-passes" |
| Record the amount of time needed for each pass and print a report to standard |
| error. |
| .IP "\fB\-\-load\fR=\fIdso_path\fR" 4 |
| .IX Item "--load=dso_path" |
| Dynamically load \fIdso_path\fR (a path to a dynamically shared object) that |
| implements an \s-1LLVM\s0 target. This will permit the target name to be used with the |
| \&\fB\-march\fR option so that code can be generated for that target. |
| .Sh "Tuning/Configuration Options" |
| .IX Subsection "Tuning/Configuration Options" |
| .IP "\fB\-\-print\-machineinstrs\fR" 4 |
| .IX Item "--print-machineinstrs" |
| Print generated machine code between compilation phases (useful for debugging). |
| .IP "\fB\-\-regalloc\fR=\fIallocator\fR" 4 |
| .IX Item "--regalloc=allocator" |
| Specify the register allocator to use. The default \fIallocator\fR is \fIlocal\fR. |
| Valid register allocators are: |
| .RS 4 |
| .IP "\fIsimple\fR" 4 |
| .IX Item "simple" |
| Very simple \*(L"always spill\*(R" register allocator |
| .IP "\fIlocal\fR" 4 |
| .IX Item "local" |
| Local register allocator |
| .IP "\fIlinearscan\fR" 4 |
| .IX Item "linearscan" |
| Linear scan global register allocator |
| .IP "\fIiterativescan\fR" 4 |
| .IX Item "iterativescan" |
| Iterative scan global register allocator |
| .RE |
| .RS 4 |
| .RE |
| .IP "\fB\-\-spiller\fR=\fIspiller\fR" 4 |
| .IX Item "--spiller=spiller" |
| Specify the spiller to use for register allocators that support it. Currently |
| this option is used only by the linear scan register allocator. The default |
| \&\fIspiller\fR is \fIlocal\fR. Valid spillers are: |
| .RS 4 |
| .IP "\fIsimple\fR" 4 |
| .IX Item "simple" |
| Simple spiller |
| .IP "\fIlocal\fR" 4 |
| .IX Item "local" |
| Local spiller |
| .RE |
| .RS 4 |
| .RE |
| .Sh "Intel IA\-32\-specific Options" |
| .IX Subsection "Intel IA-32-specific Options" |
| .IP "\fB\-\-x86\-asm\-syntax=att|intel\fR" 4 |
| .IX Item "--x86-asm-syntax=att|intel" |
| Specify whether to emit assembly code in \s-1AT&T\s0 syntax (the default) or intel |
| syntax. |
| .SH "EXIT STATUS" |
| .IX Header "EXIT STATUS" |
| If \fBllc\fR succeeds, it will exit with 0. Otherwise, if an error occurs, |
| it will exit with a non-zero value. |
| .SH "SEE ALSO" |
| .IX Header "SEE ALSO" |
| lli |
| .SH "AUTHORS" |
| .IX Header "AUTHORS" |
| Maintained by the \s-1LLVM\s0 Team (<http://llvm.org>). |