blob: ccef381be8e12355247545ce67483ebbe9719a77 [file] [log] [blame]
/*
* i386 translation
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include "cpu.h"
#include "disas.h"
#include "tcg-op.h"
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"
#define PREFIX_REPZ 0x01
#define PREFIX_REPNZ 0x02
#define PREFIX_LOCK 0x04
#define PREFIX_DATA 0x08
#define PREFIX_ADR 0x10
#ifdef TARGET_X86_64
#define X86_64_ONLY(x) x
#define X86_64_DEF(...) __VA_ARGS__
#define CODE64(s) ((s)->code64)
#define REX_X(s) ((s)->rex_x)
#define REX_B(s) ((s)->rex_b)
/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
#if 1
#define BUGGY_64(x) NULL
#endif
#else
#define X86_64_ONLY(x) NULL
#define X86_64_DEF(...)
#define CODE64(s) 0
#define REX_X(s) 0
#define REX_B(s) 0
#endif
//#define MACRO_TEST 1
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
static TCGv_i32 cpu_cc_op;
static TCGv cpu_regs[CPU_NB_REGS];
/* local temps */
static TCGv cpu_T[2], cpu_T3;
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp4;
static TCGv_ptr cpu_ptr0, cpu_ptr1;
static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
static TCGv_i64 cpu_tmp1_i64;
static TCGv cpu_tmp5;
static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
#include "gen-icount.h"
#ifdef TARGET_X86_64
static int x86_64_hregs;
#endif
typedef struct DisasContext {
/* current insn context */
int override; /* -1 if no override */
int prefix;
int aflag, dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
/* current block context */
target_ulong cs_base; /* base of CS segment */
int pe; /* protected mode */
int code32; /* 32 bit code segment */
#ifdef TARGET_X86_64
int lma; /* long mode active */
int code64; /* 64 bit code segment */
int rex_x, rex_b;
#endif
int ss32; /* 32 bit stack segment */
int cc_op; /* current CC operation */
int addseg; /* non zero if either DS/ES/SS have a non zero base */
int f_st; /* currently unused */
int vm86; /* vm86 mode */
int cpl;
int iopl;
int tf; /* TF cpu flag */
int singlestep_enabled; /* "hardware" single step enabled */
int jmp_opt; /* use direct block chaining for direct jumps */
int mem_index; /* select memory access functions */
uint64_t flags; /* all execution flags */
struct TranslationBlock *tb;
int popl_esp_hack; /* for correct popl with esp base handling */
int rip_offset; /* only used in x86_64, but left for simplicity */
int cpuid_features;
int cpuid_ext_features;
int cpuid_ext2_features;
int cpuid_ext3_features;
} DisasContext;
static void gen_eob(DisasContext *s);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
/* i386 arith/logic operations */
enum {
OP_ADDL,
OP_ORL,
OP_ADCL,
OP_SBBL,
OP_ANDL,
OP_SUBL,
OP_XORL,
OP_CMPL,
};
/* i386 shift ops */
enum {
OP_ROL,
OP_ROR,
OP_RCL,
OP_RCR,
OP_SHL,
OP_SHR,
OP_SHL1, /* undocumented */
OP_SAR = 7,
};
enum {
JCC_O,
JCC_B,
JCC_Z,
JCC_BE,
JCC_S,
JCC_P,
JCC_L,
JCC_LE,
};
/* operand size */
enum {
OT_BYTE = 0,
OT_WORD,
OT_LONG,
OT_QUAD,
};
enum {
/* I386 int registers */
OR_EAX, /* MUST be even numbered */
OR_ECX,
OR_EDX,
OR_EBX,
OR_ESP,
OR_EBP,
OR_ESI,
OR_EDI,
OR_TMP0 = 16, /* temporary operand register */
OR_TMP1,
OR_A0, /* temporary register used when doing address evaluation */
};
static inline void gen_op_movl_T0_0(void)
{
tcg_gen_movi_tl(cpu_T[0], 0);
}
static inline void gen_op_movl_T0_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_op_movl_T0_imu(uint32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_op_movl_T1_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_movl_T1_imu(uint32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_movl_A0_im(uint32_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
}
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_im(int64_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
}
#endif
static inline void gen_movtl_T0_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_movtl_T1_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_andl_T0_ffff(void)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
}
static inline void gen_op_andl_T0_im(uint32_t val)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
}
static inline void gen_op_movl_T0_T1(void)
{
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
}
static inline void gen_op_andl_A0_ffff(void)
{
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
}
#ifdef TARGET_X86_64
#define NB_OP_SIZES 4
#else /* !TARGET_X86_64 */
#define NB_OP_SIZES 3
#endif /* !TARGET_X86_64 */
#if defined(HOST_WORDS_BIGENDIAN)
#define REG_B_OFFSET (sizeof(target_ulong) - 1)
#define REG_H_OFFSET (sizeof(target_ulong) - 2)
#define REG_W_OFFSET (sizeof(target_ulong) - 2)
#define REG_L_OFFSET (sizeof(target_ulong) - 4)
#define REG_LH_OFFSET (sizeof(target_ulong) - 8)
#else
#define REG_B_OFFSET 0
#define REG_H_OFFSET 1
#define REG_W_OFFSET 0
#define REG_L_OFFSET 0
#define REG_LH_OFFSET 4
#endif
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
{
switch(ot) {
case OT_BYTE:
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
} else {
tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
}
break;
case OT_WORD:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
case OT_LONG:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], t0);
break;
#ifdef TARGET_X86_64
case OT_QUAD:
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
}
}
static inline void gen_op_mov_reg_T0(int ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
static inline void gen_op_mov_reg_T1(int ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
static inline void gen_op_mov_reg_A0(int size, int reg)
{
switch(size) {
case 0:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
case 1:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
}
}
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
{
switch(ot) {
case OT_BYTE:
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
goto std_case;
} else {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
tcg_gen_ext8u_tl(t0, t0);
}
break;
default:
std_case:
tcg_gen_mov_tl(t0, cpu_regs[reg]);
break;
}
}
static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
{
gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
}
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
}
static inline void gen_op_addl_A0_im(int32_t val)
{
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
#ifdef TARGET_X86_64
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
#endif
}
#ifdef TARGET_X86_64
static inline void gen_op_addq_A0_im(int64_t val)
{
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
}
#endif
static void gen_add_A0_im(DisasContext *s, int val)
{
#ifdef TARGET_X86_64
if (CODE64(s))
gen_op_addq_A0_im(val);
else
#endif
gen_op_addl_A0_im(val);
}
static inline void gen_op_addl_T0_T1(void)
{
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
static inline void gen_op_jmp_T0(void)
{
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
}
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
{
switch(size) {
case 0:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
case 1:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
break;
#endif
}
}
static inline void gen_op_add_reg_T0(int size, int reg)
{
switch(size) {
case 0:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
case 1:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
break;
#endif
}
}
static inline void gen_op_set_cc_op(int32_t val)
{
tcg_gen_movi_i32(cpu_cc_op, val);
}
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
static inline void gen_op_movl_A0_seg(int reg)
{
tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
}
static inline void gen_op_addl_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
#ifdef TARGET_X86_64
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
#endif
}
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
}
static inline void gen_op_addq_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
static inline void gen_op_movq_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
}
static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
#endif
static inline void gen_op_lds_T0_A0(int idx)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
break;
case 1:
tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
break;
default:
case 2:
tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
break;
}
}
static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
break;
case 1:
tcg_gen_qemu_ld16u(t0, a0, mem_index);
break;
case 2:
tcg_gen_qemu_ld32u(t0, a0, mem_index);
break;
default:
case 3:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_ld64(t0, a0, mem_index);
#endif
break;
}
}
/* XXX: always use ldu or lds */
static inline void gen_op_ld_T0_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_ldu_T0_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_ld_T1_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[1], cpu_A0);
}
static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_st8(t0, a0, mem_index);
break;
case 1:
tcg_gen_qemu_st16(t0, a0, mem_index);
break;
case 2:
tcg_gen_qemu_st32(t0, a0, mem_index);
break;
default:
case 3:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_st64(t0, a0, mem_index);
#endif
break;
}
}
static inline void gen_op_st_T0_A0(int idx)
{
gen_op_st_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_st_T1_A0(int idx)
{
gen_op_st_v(idx, cpu_T[1], cpu_A0);
}
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
{
int override;
override = s->override;
#ifdef TARGET_X86_64
if (s->aflag == 2) {
if (override >= 0) {
gen_op_movq_A0_seg(override);
gen_op_addq_A0_reg_sN(0, R_ESI);
} else {
gen_op_movq_A0_reg(R_ESI);
}
} else
#endif
if (s->aflag) {
/* 32 bit address */
if (s->addseg && override < 0)
override = R_DS;
if (override >= 0) {
gen_op_movl_A0_seg(override);
gen_op_addl_A0_reg_sN(0, R_ESI);
} else {
gen_op_movl_A0_reg(R_ESI);
}
} else {
/* 16 address, always override */
if (override < 0)
override = R_DS;
gen_op_movl_A0_reg(R_ESI);
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(override);
}
}
static inline void gen_string_movl_A0_EDI(DisasContext *s)
{
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_reg(R_EDI);
} else
#endif
if (s->aflag) {
if (s->addseg) {
gen_op_movl_A0_seg(R_ES);
gen_op_addl_A0_reg_sN(0, R_EDI);
} else {
gen_op_movl_A0_reg(R_EDI);
}
} else {
gen_op_movl_A0_reg(R_EDI);
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(R_ES);
}
}
static inline void gen_op_movl_T0_Dshift(int ot)
{
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
};
static void gen_extu(int ot, TCGv reg)
{
switch(ot) {
case OT_BYTE:
tcg_gen_ext8u_tl(reg, reg);
break;
case OT_WORD:
tcg_gen_ext16u_tl(reg, reg);
break;
case OT_LONG:
tcg_gen_ext32u_tl(reg, reg);
break;
default:
break;
}
}
static void gen_exts(int ot, TCGv reg)
{
switch(ot) {
case OT_BYTE:
tcg_gen_ext8s_tl(reg, reg);
break;
case OT_WORD:
tcg_gen_ext16s_tl(reg, reg);
break;
case OT_LONG:
tcg_gen_ext32s_tl(reg, reg);
break;
default:
break;
}
}
static inline void gen_op_jnz_ecx(int size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size + 1, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
}
static inline void gen_op_jz_ecx(int size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size + 1, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
case 0: gen_helper_inb(v, n); break;
case 1: gen_helper_inw(v, n); break;
case 2: gen_helper_inl(v, n); break;
}
}
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
case 0: gen_helper_outb(v, n); break;
case 1: gen_helper_outw(v, n); break;
case 2: gen_helper_outl(v, n); break;
}
}
static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
uint32_t svm_flags)
{
int state_saved;
target_ulong next_eip;
state_saved = 0;
if (s->pe && (s->cpl > s->iopl || s->vm86)) {
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
}
}
if(s->flags & HF_SVMI_MASK) {
if (!state_saved) {
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
}
svm_flags |= (1 << (4 + ot));
next_eip = s->pc - s->cs_base;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
tcg_const_i32(next_eip - cur_eip));
}
}
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(ot + s->mem_index);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(ot + s->mem_index);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_update_cc_op(DisasContext *s)
{
if (s->cc_op != CC_OP_DYNAMIC) {
gen_op_set_cc_op(s->cc_op);
s->cc_op = CC_OP_DYNAMIC;
}
}
static void gen_op_update1_cc(void)
{
tcg_gen_discard_tl(cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static void gen_op_update2_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static inline void gen_op_cmpl_T0_T1_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
}
static inline void gen_op_testl_T0_T1_cc(void)
{
tcg_gen_discard_tl(cpu_cc_src);
tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
}
static void gen_op_update_neg_cc(void)
{
tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
/* compute eflags.C to reg */
static void gen_compute_eflags_c(TCGv reg)
{
gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
}
/* compute all eflags to cc_src */
static void gen_compute_eflags(TCGv reg)
{
gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
}
static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
switch(jcc_op) {
case JCC_O:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_B:
gen_compute_eflags_c(cpu_T[0]);
break;
case JCC_Z:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_BE:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_S:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_P:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_L:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
default:
case JCC_LE:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
}
}
/* return true if setcc_slow is not needed (WARNING: must be kept in
sync with gen_jcc1) */
static int is_fast_jcc_case(DisasContext *s, int b)
{
int jcc_op;
jcc_op = (b >> 1) & 7;
switch(s->cc_op) {
/* we optimize the cmp/jcc case */
case CC_OP_SUBB:
case CC_OP_SUBW:
case CC_OP_SUBL:
case CC_OP_SUBQ:
if (jcc_op == JCC_O || jcc_op == JCC_P)
goto slow_jcc;
break;
/* some jumps are easy to compute */
case CC_OP_ADDB:
case CC_OP_ADDW:
case CC_OP_ADDL:
case CC_OP_ADDQ:
case CC_OP_LOGICB:
case CC_OP_LOGICW:
case CC_OP_LOGICL:
case CC_OP_LOGICQ:
case CC_OP_INCB:
case CC_OP_INCW:
case CC_OP_INCL:
case CC_OP_INCQ:
case CC_OP_DECB:
case CC_OP_DECW:
case CC_OP_DECL:
case CC_OP_DECQ:
case CC_OP_SHLB:
case CC_OP_SHLW:
case CC_OP_SHLL:
case CC_OP_SHLQ:
if (jcc_op != JCC_Z && jcc_op != JCC_S)
goto slow_jcc;
break;
default:
slow_jcc:
return 0;
}
return 1;
}
/* generate a conditional jump to label 'l1' according to jump opcode
value 'b'. In the fast case, T0 is guaranted not to be used. */
static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
{
int inv, jcc_op, size, cond;
TCGv t0;
inv = b & 1;
jcc_op = (b >> 1) & 7;
switch(cc_op) {
/* we optimize the cmp/jcc case */
case CC_OP_SUBB:
case CC_OP_SUBW:
case CC_OP_SUBL:
case CC_OP_SUBQ:
size = cc_op - CC_OP_SUBB;
switch(jcc_op) {
case JCC_Z:
fast_jcc_z:
switch(size) {
case 0:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
t0 = cpu_tmp0;
break;
case 1:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
t0 = cpu_tmp0;
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
t0 = cpu_tmp0;
break;
#endif
default:
t0 = cpu_cc_dst;
break;
}
tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
break;
case JCC_S:
fast_jcc_s:
switch(size) {
case 0:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
0, l1);
break;
case 1:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
0, l1);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
0, l1);
break;
#endif
default:
tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
0, l1);
break;
}
break;
case JCC_B:
cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
goto fast_jcc_b;
case JCC_BE:
cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
fast_jcc_b:
tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
switch(size) {
case 0:
t0 = cpu_tmp0;
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
break;
case 1:
t0 = cpu_tmp0;
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
break;
#ifdef TARGET_X86_64
case 2:
t0 = cpu_tmp0;
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
break;
#endif
default:
t0 = cpu_cc_src;
break;
}
tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
break;
case JCC_L:
cond = inv ? TCG_COND_GE : TCG_COND_LT;
goto fast_jcc_l;
case JCC_LE:
cond = inv ? TCG_COND_GT : TCG_COND_LE;
fast_jcc_l:
tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
switch(size) {
case 0:
t0 = cpu_tmp0;
tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
tcg_gen_ext8s_tl(t0, cpu_cc_src);
break;
case 1:
t0 = cpu_tmp0;
tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
tcg_gen_ext16s_tl(t0, cpu_cc_src);
break;
#ifdef TARGET_X86_64
case 2:
t0 = cpu_tmp0;
tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
tcg_gen_ext32s_tl(t0, cpu_cc_src);
break;
#endif
default:
t0 = cpu_cc_src;
break;
}
tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
break;
default:
goto slow_jcc;
}
break;
/* some jumps are easy to compute */
case CC_OP_ADDB:
case CC_OP_ADDW:
case CC_OP_ADDL:
case CC_OP_ADDQ:
case CC_OP_ADCB:
case CC_OP_ADCW:
case CC_OP_ADCL:
case CC_OP_ADCQ:
case CC_OP_SBBB:
case CC_OP_SBBW:
case CC_OP_SBBL:
case CC_OP_SBBQ:
case CC_OP_LOGICB:
case CC_OP_LOGICW:
case CC_OP_LOGICL:
case CC_OP_LOGICQ:
case CC_OP_INCB:
case CC_OP_INCW:
case CC_OP_INCL:
case CC_OP_INCQ:
case CC_OP_DECB:
case CC_OP_DECW:
case CC_OP_DECL:
case CC_OP_DECQ:
case CC_OP_SHLB:
case CC_OP_SHLW:
case CC_OP_SHLL:
case CC_OP_SHLQ:
case CC_OP_SARB:
case CC_OP_SARW:
case CC_OP_SARL:
case CC_OP_SARQ:
switch(jcc_op) {
case JCC_Z:
size = (cc_op - CC_OP_ADDB) & 3;
goto fast_jcc_z;
case JCC_S:
size = (cc_op - CC_OP_ADDB) & 3;
goto fast_jcc_s;
default:
goto slow_jcc;
}
break;
default:
slow_jcc:
gen_setcc_slow_T0(s, jcc_op);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
cpu_T[0], 0, l1);
break;
}
}
/* XXX: does not work with gdbstub "ice" single step - not a
serious problem */
static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
{
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
gen_op_jnz_ecx(s->aflag, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
gen_set_label(l1);
return l2;
}
static inline void gen_stos(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(ot + s->mem_index);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_lods(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(ot + s->mem_index);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
static inline void gen_scas(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_ld_T1_A0(ot + s->mem_index);
gen_op_cmpl_T0_T1_cc();
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_cmps(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(ot + s->mem_index);
gen_string_movl_A0_EDI(s);
gen_op_ld_T1_A0(ot + s->mem_index);
gen_op_cmpl_T0_T1_cc();
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_ins(DisasContext *s, int ot)
{
if (use_icount)
gen_io_start();
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
gen_op_movl_T0_0();
gen_op_st_T0_A0(ot + s->mem_index);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_T0_A0(ot + s->mem_index);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
gen_io_end();
}
static inline void gen_outs(DisasContext *s, int ot)
{
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(ot + s->mem_index);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
if (use_icount)
gen_io_end();
}
/* same method as Valgrind : we generate jumps to current or next
instruction */
#define GEN_REPZ(op) \
static inline void gen_repz_ ## op(DisasContext *s, int ot, \
target_ulong cur_eip, target_ulong next_eip) \
{ \
int l2;\
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
gen_op_add_reg_im(s->aflag, R_ECX, -1); \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
#define GEN_REPZ2(op) \
static inline void gen_repz_ ## op(DisasContext *s, int ot, \
target_ulong cur_eip, \
target_ulong next_eip, \
int nz) \
{ \
int l2;\
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
gen_op_add_reg_im(s->aflag, R_ECX, -1); \
gen_op_set_cc_op(CC_OP_SUBB + ot); \
gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
GEN_REPZ(movs)
GEN_REPZ(stos)
GEN_REPZ(lods)
GEN_REPZ(ins)
GEN_REPZ(outs)
GEN_REPZ2(scas)
GEN_REPZ2(cmps)
static void gen_helper_fp_arith_ST0_FT0(int op)
{
switch (op) {
case 0: gen_helper_fadd_ST0_FT0(); break;
case 1: gen_helper_fmul_ST0_FT0(); break;
case 2: gen_helper_fcom_ST0_FT0(); break;
case 3: gen_helper_fcom_ST0_FT0(); break;
case 4: gen_helper_fsub_ST0_FT0(); break;
case 5: gen_helper_fsubr_ST0_FT0(); break;
case 6: gen_helper_fdiv_ST0_FT0(); break;
case 7: gen_helper_fdivr_ST0_FT0(); break;
}
}
/* NOTE the exception in "r" op ordering */
static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
{
TCGv_i32 tmp = tcg_const_i32(opreg);
switch (op) {
case 0: gen_helper_fadd_STN_ST0(tmp); break;
case 1: gen_helper_fmul_STN_ST0(tmp); break;
case 4: gen_helper_fsubr_STN_ST0(tmp); break;
case 5: gen_helper_fsub_STN_ST0(tmp); break;
case 6: gen_helper_fdivr_STN_ST0(tmp); break;
case 7: gen_helper_fdiv_STN_ST0(tmp); break;
}
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_op(DisasContext *s1, int op, int ot, int d)
{
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
} else {
gen_op_ld_T0_A0(ot + s1->mem_index);
}
switch(op) {
case OP_ADCL:
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
gen_compute_eflags_c(cpu_tmp4);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
s1->cc_op = CC_OP_DYNAMIC;
break;
case OP_SBBL:
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
gen_compute_eflags_c(cpu_tmp4);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
s1->cc_op = CC_OP_DYNAMIC;
break;
case OP_ADDL:
gen_op_addl_T0_T1();
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_op_update2_cc();
s1->cc_op = CC_OP_ADDB + ot;
break;
case OP_SUBL:
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_op_update2_cc();
s1->cc_op = CC_OP_SUBB + ot;
break;
default:
case OP_ANDL:
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_op_update1_cc();
s1->cc_op = CC_OP_LOGICB + ot;
break;
case OP_ORL:
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_op_update1_cc();
s1->cc_op = CC_OP_LOGICB + ot;
break;
case OP_XORL:
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_op_update1_cc();
s1->cc_op = CC_OP_LOGICB + ot;
break;
case OP_CMPL:
gen_op_cmpl_T0_T1_cc();
s1->cc_op = CC_OP_SUBB + ot;
break;
}
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_inc(DisasContext *s1, int ot, int d, int c)
{
if (d != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, d);
else
gen_op_ld_T0_A0(ot + s1->mem_index);
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
if (c > 0) {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
s1->cc_op = CC_OP_INCB + ot;
} else {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
s1->cc_op = CC_OP_DECB + ot;
}
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
gen_compute_eflags_c(cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
int is_right, int is_arith)
{
target_ulong mask;
int shift_label;
TCGv t0, t1;
if (ot == OT_QUAD)
mask = 0x3f;
else
mask = 0x1f;
/* load */
if (op1 == OR_TMP0)
gen_op_ld_T0_A0(ot + s->mem_index);
else
gen_op_mov_TN_reg(ot, 0, op1);
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
if (is_right) {
if (is_arith) {
gen_exts(ot, cpu_T[0]);
tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
} else {
gen_extu(ot, cpu_T[0]);
tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
} else {
tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
/* store */
if (op1 == OR_TMP0)
gen_op_st_T0_A0(ot + s->mem_index);
else
gen_op_mov_reg_T0(ot, op1);
/* update eflags if non zero shift */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
/* XXX: inefficient */
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
tcg_gen_mov_tl(t0, cpu_T[0]);
tcg_gen_mov_tl(t1, cpu_T3);
shift_label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
tcg_gen_mov_tl(cpu_cc_src, t1);
tcg_gen_mov_tl(cpu_cc_dst, t0);
if (is_right)
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
else
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
gen_set_label(shift_label);
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right, int is_arith)
{
int mask;
if (ot == OT_QUAD)
mask = 0x3f;
else
mask = 0x1f;
/* load */
if (op1 == OR_TMP0)
gen_op_ld_T0_A0(ot + s->mem_index);
else
gen_op_mov_TN_reg(ot, 0, op1);
op2 &= mask;
if (op2 != 0) {
if (is_right) {
if (is_arith) {
gen_exts(ot, cpu_T[0]);
tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
} else {
gen_extu(ot, cpu_T[0]);
tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
}
} else {
tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
}
}
/* store */
if (op1 == OR_TMP0)
gen_op_st_T0_A0(ot + s->mem_index);
else
gen_op_mov_reg_T0(ot, op1);
/* update eflags if non zero shift */
if (op2 != 0) {
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
if (is_right)
s->cc_op = CC_OP_SARB + ot;
else
s->cc_op = CC_OP_SHLB + ot;
}
}
static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
{
if (arg2 >= 0)
tcg_gen_shli_tl(ret, arg1, arg2);
else
tcg_gen_shri_tl(ret, arg1, -arg2);
}
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
int is_right)
{
target_ulong mask;
int label1, label2, data_bits;
TCGv t0, t1, t2, a0;
/* XXX: inefficient, but we must use local temps */
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t2 = tcg_temp_local_new();
a0 = tcg_temp_local_new();
if (ot == OT_QUAD)
mask = 0x3f;
else
mask = 0x1f;
/* load */
if (op1 == OR_TMP0) {
tcg_gen_mov_tl(a0, cpu_A0);
gen_op_ld_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_v_reg(ot, t0, op1);
}
tcg_gen_mov_tl(t1, cpu_T[1]);
tcg_gen_andi_tl(t1, t1, mask);
/* Must test zero case to avoid using undefined behaviour in TCG
shifts. */
label1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
if (ot <= OT_WORD)
tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
else
tcg_gen_mov_tl(cpu_tmp0, t1);
gen_extu(ot, t0);
tcg_gen_mov_tl(t2, t0);
data_bits = 8 << ot;
/* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
fix TCG definition) */
if (is_right) {
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
tcg_gen_shl_tl(t0, t0, cpu_tmp0);
} else {
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
tcg_gen_shr_tl(t0, t0, cpu_tmp0);
}
tcg_gen_or_tl(t0, t0, cpu_tmp4);
gen_set_label(label1);
/* store */
if (op1 == OR_TMP0) {
gen_op_st_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_reg_v(ot, op1, t0);
}
/* update eflags */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
label2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
gen_compute_eflags(cpu_cc_src);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
tcg_gen_xor_tl(cpu_tmp0, t2, t0);
tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
if (is_right) {
tcg_gen_shri_tl(t0, t0, data_bits - 1);
}
tcg_gen_andi_tl(t0, t0, CC_C);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
tcg_gen_discard_tl(cpu_cc_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
gen_set_label(label2);
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(a0);
}
static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right)
{
int mask;
int data_bits;
TCGv t0, t1, a0;
/* XXX: inefficient, but we must use local temps */
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
a0 = tcg_temp_local_new();
if (ot == OT_QUAD)
mask = 0x3f;
else
mask = 0x1f;
/* load */
if (op1 == OR_TMP0) {
tcg_gen_mov_tl(a0, cpu_A0);
gen_op_ld_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_v_reg(ot, t0, op1);
}
gen_extu(ot, t0);
tcg_gen_mov_tl(t1, t0);
op2 &= mask;
data_bits = 8 << ot;
if (op2 != 0) {
int shift = op2 & ((1 << (3 + ot)) - 1);
if (is_right) {
tcg_gen_shri_tl(cpu_tmp4, t0, shift);
tcg_gen_shli_tl(t0, t0, data_bits - shift);
}
else {
tcg_gen_shli_tl(cpu_tmp4, t0, shift);
tcg_gen_shri_tl(t0, t0, data_bits - shift);
}
tcg_gen_or_tl(t0, t0, cpu_tmp4);
}
/* store */
if (op1 == OR_TMP0) {
gen_op_st_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_reg_v(ot, op1, t0);
}
if (op2 != 0) {
/* update eflags */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_compute_eflags(cpu_cc_src);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
tcg_gen_xor_tl(cpu_tmp0, t1, t0);
tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
if (is_right) {
tcg_gen_shri_tl(t0, t0, data_bits - 1);
}
tcg_gen_andi_tl(t0, t0, CC_C);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
tcg_gen_discard_tl(cpu_cc_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
s->cc_op = CC_OP_EFLAGS;
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(a0);
}
/* XXX: add faster immediate = 1 case */
static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
int is_right)
{
int label1;
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
/* load */
if (op1 == OR_TMP0)
gen_op_ld_T0_A0(ot + s->mem_index);
else
gen_op_mov_TN_reg(ot, 0, op1);
if (is_right) {
switch (ot) {
case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
#ifdef TARGET_X86_64
case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
#endif
}
} else {
switch (ot) {
case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
#ifdef TARGET_X86_64
case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
#endif
}
}
/* store */
if (op1 == OR_TMP0)
gen_op_st_T0_A0(ot + s->mem_index);
else
gen_op_mov_reg_T0(ot, op1);
/* update eflags */
label1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
tcg_gen_discard_tl(cpu_cc_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
gen_set_label(label1);
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
}
/* XXX: add faster immediate case */
static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
int is_right)
{
int label1, label2, data_bits;
target_ulong mask;
TCGv t0, t1, t2, a0;
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t2 = tcg_temp_local_new();
a0 = tcg_temp_local_new();
if (ot == OT_QUAD)
mask = 0x3f;
else
mask = 0x1f;
/* load */
if (op1 == OR_TMP0) {
tcg_gen_mov_tl(a0, cpu_A0);
gen_op_ld_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_v_reg(ot, t0, op1);
}
tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
tcg_gen_mov_tl(t1, cpu_T[1]);
tcg_gen_mov_tl(t2, cpu_T3);
/* Must test zero case to avoid using undefined behaviour in TCG
shifts. */
label1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
tcg_gen_addi_tl(cpu_tmp5, t2, -1);
if (ot == OT_WORD) {
/* Note: we implement the Intel behaviour for shift count > 16 */
if (is_right) {
tcg_gen_andi_tl(t0, t0, 0xffff);
tcg_gen_shli_tl(cpu_tmp0, t1, 16);
tcg_gen_or_tl(t0, t0, cpu_tmp0);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
/* only needed if count > 16, but a test would complicate */
tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
tcg_gen_shr_tl(t0, t0, t2);
tcg_gen_or_tl(t0, t0, cpu_tmp0);
} else {
/* XXX: not optimal */
tcg_gen_andi_tl(t0, t0, 0xffff);
tcg_gen_shli_tl(t1, t1, 16);
tcg_gen_or_tl(t1, t1, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
tcg_gen_shl_tl(t0, t0, t2);
tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
tcg_gen_shr_tl(t1, t1, cpu_tmp5);
tcg_gen_or_tl(t0, t0, t1);
}
} else {
data_bits = 8 << ot;
if (is_right) {
if (ot == OT_LONG)
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
tcg_gen_shr_tl(t0, t0, t2);
tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
tcg_gen_shl_tl(t1, t1, cpu_tmp5);
tcg_gen_or_tl(t0, t0, t1);
} else {
if (ot == OT_LONG)
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
tcg_gen_shl_tl(t0, t0, t2);
tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
tcg_gen_shr_tl(t1, t1, cpu_tmp5);
tcg_gen_or_tl(t0, t0, t1);
}
}
tcg_gen_mov_tl(t1, cpu_tmp4);
gen_set_label(label1);
/* store */
if (op1 == OR_TMP0) {
gen_op_st_v(ot + s->mem_index, t0, a0);
} else {
gen_op_mov_reg_v(ot, op1, t0);
}
/* update eflags */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
label2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
tcg_gen_mov_tl(cpu_cc_src, t1);
tcg_gen_mov_tl(cpu_cc_dst, t0);
if (is_right) {
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
} else {
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
}
gen_set_label(label2);
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(a0);
}
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
{
if (s != OR_TMP1)
gen_op_mov_TN_reg(ot, 1, s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
break;
case OP_ROR:
gen_rot_rm_T1(s1, ot, d, 1);
break;
case OP_SHL:
case OP_SHL1:
gen_shift_rm_T1(s1, ot, d, 0, 0);
break;
case OP_SHR:
gen_shift_rm_T1(s1, ot, d, 1, 0);
break;
case OP_SAR:
gen_shift_rm_T1(s1, ot, d, 1, 1);
break;
case OP_RCL:
gen_rotc_rm_T1(s1, ot, d, 0);
break;
case OP_RCR:
gen_rotc_rm_T1(s1, ot, d, 1);
break;
}
}
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
{
switch(op) {
case OP_ROL:
gen_rot_rm_im(s1, ot, d, c, 0);
break;
case OP_ROR:
gen_rot_rm_im(s1, ot, d, c, 1);
break;
case OP_SHL:
case OP_SHL1:
gen_shift_rm_im(s1, ot, d, c, 0, 0);
break;
case OP_SHR:
gen_shift_rm_im(s1, ot, d, c, 1, 0);
break;
case OP_SAR:
gen_shift_rm_im(s1, ot, d, c, 1, 1);
break;
default:
/* currently not optimized */
gen_op_movl_T1_im(c);
gen_shift(s1, op, ot, d, OR_TMP1);
break;
}
}
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
{
target_long disp;
int havesib;
int base;
int index;
int scale;
int opreg;
int mod, rm, code, override, must_add_seg;
override = s->override;
must_add_seg = s->addseg;
if (override >= 0)
must_add_seg = 1;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (s->aflag) {
havesib = 0;
base = rm;
index = 0;
scale = 0;
if (base == 4) {
havesib = 1;
code = ldub_code(s->pc++);
scale = (code >> 6) & 3;
index = ((code >> 3) & 7) | REX_X(s);
base = (code & 7);
}
base |= REX_B(s);
switch (mod) {
case 0:
if ((base & 7) == 5) {
base = -1;
disp = (int32_t)ldl_code(s->pc);
s->pc += 4;
if (CODE64(s) && !havesib) {
disp += s->pc + s->rip_offset;
}
} else {
disp = 0;
}
break;
case 1:
disp = (int8_t)ldub_code(s->pc++);
break;
default:
case 2:
disp = (int32_t)ldl_code(s->pc);
s->pc += 4;
break;
}
if (base >= 0) {
/* for correct popl handling with esp */
if (base == 4 && s->popl_esp_hack)
disp += s->popl_esp_hack;
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_reg(base);
if (disp != 0) {
gen_op_addq_A0_im(disp);
}
} else
#endif
{
gen_op_movl_A0_reg(base);
if (disp != 0)
gen_op_addl_A0_im(disp);
}
} else {
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_im(disp);
} else
#endif
{
gen_op_movl_A0_im(disp);
}
}
/* index == 4 means no index */
if (havesib && (index != 4)) {
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_addq_A0_reg_sN(scale, index);
} else
#endif
{
gen_op_addl_A0_reg_sN(scale, index);
}
}
if (must_add_seg) {
if (override < 0) {
if (base == R_EBP || base == R_ESP)
override = R_SS;
else
override = R_DS;
}
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_addq_A0_seg(override);
} else
#endif
{
gen_op_addl_A0_seg(override);
}
}
} else {
switch (mod) {
case 0:
if (rm == 6) {
disp = lduw_code(s->pc);
s->pc += 2;
gen_op_movl_A0_im(disp);
rm = 0; /* avoid SS override */
goto no_rm;
} else {
disp = 0;
}
break;
case 1:
disp = (int8_t)ldub_code(s->pc++);
break;
default:
case 2:
disp = lduw_code(s->pc);
s->pc += 2;
break;
}
switch(rm) {
case 0:
gen_op_movl_A0_reg(R_EBX);
gen_op_addl_A0_reg_sN(0, R_ESI);
break;
case 1:
gen_op_movl_A0_reg(R_EBX);
gen_op_addl_A0_reg_sN(0, R_EDI);
break;
case 2:
gen_op_movl_A0_reg(R_EBP);
gen_op_addl_A0_reg_sN(0, R_ESI);
break;
case 3:
gen_op_movl_A0_reg(R_EBP);
gen_op_addl_A0_reg_sN(0, R_EDI);
break;
case 4:
gen_op_movl_A0_reg(R_ESI);
break;
case 5:
gen_op_movl_A0_reg(R_EDI);
break;
case 6:
gen_op_movl_A0_reg(R_EBP);
break;
default:
case 7:
gen_op_movl_A0_reg(R_EBX);
break;
}
if (disp != 0)
gen_op_addl_A0_im(disp);
gen_op_andl_A0_ffff();
no_rm:
if (must_add_seg) {
if (override < 0) {
if (rm == 2 || rm == 3 || rm == 6)
override = R_SS;
else
override = R_DS;
}
gen_op_addl_A0_seg(override);
}
}
opreg = OR_A0;
disp = 0;
*reg_ptr = opreg;
*offset_ptr = disp;
}
static void gen_nop_modrm(DisasContext *s, int modrm)
{
int mod, rm, base, code;
mod = (modrm >> 6) & 3;
if (mod == 3)
return;
rm = modrm & 7;
if (s->aflag) {
base = rm;
if (base == 4) {
code = ldub_code(s->pc++);
base = (code & 7);
}
switch (mod) {
case 0:
if (base == 5) {
s->pc += 4;
}
break;
case 1:
s->pc++;
break;
default:
case 2:
s->pc += 4;
break;
}
} else {
switch (mod) {
case 0:
if (rm == 6) {
s->pc += 2;
}
break;
case 1:
s->pc++;
break;
default:
case 2:
s->pc += 2;
break;
}
}
}
/* used for LEA and MOV AX, mem */
static void gen_add_A0_ds_seg(DisasContext *s)
{
int override, must_add_seg;
must_add_seg = s->addseg;
override = R_DS;
if (s->override >= 0) {
override = s->override;
must_add_seg = 1;
}
if (must_add_seg) {
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_addq_A0_seg(override);
} else
#endif
{
gen_op_addl_A0_seg(override);
}
}
}
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
OR_TMP0 */
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
{
int mod, rm, opreg, disp;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_reg_T0(ot, rm);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
} else {
gen_lea_modrm(s, modrm, &opreg, &disp);
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_st_T0_A0(ot + s->mem_index);
} else {
gen_op_ld_T0_A0(ot + s->mem_index);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
}
}
static inline uint32_t insn_get(DisasContext *s, int ot)
{
uint32_t ret;
switch(ot) {
case OT_BYTE:
ret = ldub_code(s->pc);
s->pc++;
break;
case OT_WORD:
ret = lduw_code(s->pc);
s->pc += 2;
break;
default:
case OT_LONG:
ret = ldl_code(s->pc);
s->pc += 4;
break;
}
return ret;
}
static inline int insn_const_size(unsigned int ot)
{
if (ot <= OT_LONG)
return 1 << ot;
else
return 4;
}
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
{
TranslationBlock *tb;
target_ulong pc;
pc = s->cs_base + eip;
tb = s->tb;
/* NOTE: we handle the case where the TB spans two pages here */
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
(pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
gen_jmp_im(eip);
tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
} else {
/* jump to another page: currently not optimized */
gen_jmp_im(eip);
gen_eob(s);
}
}
static inline void gen_jcc(DisasContext *s, int b,
target_ulong val, target_ulong next_eip)
{
int l1, l2, cc_op;
cc_op = s->cc_op;
gen_update_cc_op(s);
if (s->jmp_opt) {
l1 = gen_new_label();
gen_jcc1(s, cc_op, b, l1);
gen_goto_tb(s, 0, next_eip);
gen_set_label(l1);
gen_goto_tb(s, 1, val);
s->is_jmp = DISAS_TB_JUMP;
} else {
l1 = gen_new_label();
l2 = gen_new_label();
gen_jcc1(s, cc_op, b, l1);
gen_jmp_im(next_eip);
tcg_gen_br(l2);
gen_set_label(l1);
gen_jmp_im(val);
gen_set_label(l2);
gen_eob(s);
}
}
static void gen_setcc(DisasContext *s, int b)
{
int inv, jcc_op, l1;
TCGv t0;
if (is_fast_jcc_case(s, b)) {
/* nominal case: we use a jump */
/* XXX: make it faster by adding new instructions in TCG */
t0 = tcg_temp_local_new();
tcg_gen_movi_tl(t0, 0);
l1 = gen_new_label();
gen_jcc1(s, s->cc_op, b ^ 1, l1);
tcg_gen_movi_tl(t0, 1);
gen_set_label(l1);
tcg_gen_mov_tl(cpu_T[0], t0);
tcg_temp_free(t0);
} else {
/* slow case: it is more efficient not to generate a jump,
although it is questionnable whether this optimization is
worth to */
inv = b & 1;
jcc_op = (b >> 1) & 7;
gen_setcc_slow_T0(s, jcc_op);
if (inv) {
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
}
}
}
static inline void gen_op_movl_T0_seg(int seg_reg)
{
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,segs[seg_reg].selector));
}
static inline void gen_op_movl_seg_T0_vm(int seg_reg)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
tcg_gen_st32_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,segs[seg_reg].selector));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
tcg_gen_st_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,segs[seg_reg].base));
}
/* move T0 to seg_reg and compute if the CPU state may change. Never
call this function with seg_reg == R_CS */
static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
{
if (s->pe && !s->vm86) {
/* XXX: optimize by finding processor state dynamically */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware
interrupts for the next instruction */
if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
s->is_jmp = DISAS_TB_JUMP;
} else {
gen_op_movl_seg_T0_vm(seg_reg);
if (seg_reg == R_SS)
s->is_jmp = DISAS_TB_JUMP;
}
}
static inline int svm_is_rep(int prefixes)
{
return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
}
static inline void
gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
uint32_t type, uint64_t param)
{
/* no SVM activated; fast case */
if (likely(!(s->flags & HF_SVMI_MASK)))
return;
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_svm_check_intercept_param(tcg_const_i32(type),
tcg_const_i64(param));
}
static inline void
gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
{
gen_svm_check_intercept_param(s, pc_start, type, 0);
}
static inline void gen_stack_update(DisasContext *s, int addend)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_add_reg_im(2, R_ESP, addend);
} else
#endif
if (s->ss32) {
gen_op_add_reg_im(1, R_ESP, addend);
} else {
gen_op_add_reg_im(0, R_ESP, addend);
}
}
/* generate a push. It depends on ss32, addseg and dflag */
static void gen_push_T0(DisasContext *s)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
gen_op_st_T0_A0(OT_QUAD + s->mem_index);
} else {
gen_op_addq_A0_im(-2);
gen_op_st_T0_A0(OT_WORD + s->mem_index);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
#endif
{
gen_op_movl_A0_reg(R_ESP);
if (!s->dflag)
gen_op_addl_A0_im(-2);
else
gen_op_addl_A0_im(-4);
if (s->ss32) {
if (s->addseg) {
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(R_SS);
}
} else {
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(R_SS);
}
gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
}
}
/* generate a push. It depends on ss32, addseg and dflag */
/* slower version for T1, only used for call Ev */
static void gen_push_T1(DisasContext *s)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
gen_op_st_T1_A0(OT_QUAD + s->mem_index);
} else {
gen_op_addq_A0_im(-2);
gen_op_st_T0_A0(OT_WORD + s->mem_index);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
#endif
{
gen_op_movl_A0_reg(R_ESP);
if (!s->dflag)
gen_op_addl_A0_im(-2);
else
gen_op_addl_A0_im(-4);
if (s->ss32) {
if (s->addseg) {
gen_op_addl_A0_seg(R_SS);
}
} else {
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(R_SS);
}
gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
gen_stack_update(s, (-2) << s->dflag);
}
}
/* two step pop is necessary for precise exceptions */
static void gen_pop_T0(DisasContext *s)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
} else
#endif
{
gen_op_movl_A0_reg(R_ESP);
if (s->ss32) {
if (s->addseg)
gen_op_addl_A0_seg(R_SS);
} else {
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(R_SS);
}
gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
}
}
static void gen_pop_update(DisasContext *s)
{
#ifdef TARGET_X86_64
if (CODE64(s) && s->dflag) {
gen_stack_update(s, 8);
} else
#endif
{
gen_stack_update(s, 2 << s->dflag);
}
}
static void gen_stack_A0(DisasContext *s)
{
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(R_SS);
}
/* NOTE: wrap around in 16 bit not fully handled */
static void gen_pusha(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-16 << s->dflag);
if (!s->ss32)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
}
/* NOTE: wrap around in 16 bit not fully handled */
static void gen_popa(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
if (s->addseg)
gen_op_addl_A0_seg(R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
int ot, opsize;
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
ot = s->dflag ? OT_QUAD : OT_WORD;
opsize = 1 << ot;
gen_op_movl_A0_reg(R_ESP);
gen_op_addq_A0_im(-opsize);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
gen_op_st_T0_A0(ot + s->mem_index);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(tcg_const_i32(level),
tcg_const_i32((ot == OT_QUAD)),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
gen_op_mov_reg_T1(OT_QUAD, R_ESP);
} else
#endif
{
ot = s->dflag + OT_WORD;
opsize = 2 << s->dflag;
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
gen_op_andl_A0_ffff();
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(R_SS);
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
gen_op_st_T0_A0(ot + s->mem_index);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(tcg_const_i32(level),
tcg_const_i32(s->dflag),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
}
}
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_raise_exception(tcg_const_i32(trapno));
s->is_jmp = DISAS_TB_JUMP;
}
/* an interrupt is different from an exception because of the
privilege checks */
static void gen_interrupt(DisasContext *s, int intno,
target_ulong cur_eip, target_ulong next_eip)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_raise_interrupt(tcg_const_i32(intno),
tcg_const_i32(next_eip - cur_eip));
s->is_jmp = DISAS_TB_JUMP;
}
static void gen_debug(DisasContext *s, target_ulong cur_eip)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_debug();
s->is_jmp = DISAS_TB_JUMP;
}
/* generate a generic end of block. Trace exception is also generated
if needed */
static void gen_eob(DisasContext *s)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
gen_helper_reset_inhibit_irq();
}
if (s->tb->flags & HF_RF_MASK) {
gen_helper_reset_rf();
}
if (s->singlestep_enabled) {
gen_helper_debug();
} else if (s->tf) {
gen_helper_single_step();
} else {
tcg_gen_exit_tb(0);
}
s->is_jmp = DISAS_TB_JUMP;
}
/* generate a jump to eip. No segment change must happen before as a
direct call to the next block may occur */
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
{
if (s->jmp_opt) {
gen_update_cc_op(s);
gen_goto_tb(s, tb_num, eip);
s->is_jmp = DISAS_TB_JUMP;
} else {
gen_jmp_im(eip);
gen_eob(s);
}
}
static void gen_jmp(DisasContext *s, target_ulong eip)
{
gen_jmp_tb(s, eip, 0);
}
static inline void gen_ldq_env_A0(int idx, int offset)
{
int mem_index = (idx >> 2) - 1;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
static inline void gen_stq_env_A0(int idx, int offset)
{
int mem_index = (idx >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset