Decrease SRC pipeline buffers RAM size and update PCM configuration
This patch decreases pipeline buffers usage from 5x or 4x periods to 3x
to avoid DAI error in APL platform when allocating buffers. The smaller
buffers are sufficient since the test topology pipelines are scheduled
every 1ms (earlier assumption was every 5 ms).
The PCM capability is updated to 8 channels similarly as with low delay
pipeline. The highest sample rate is increased from 96 kHz to 192 kHz.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
1 file changed
