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commit3110373eb3d2482e0d96f7a359cdd1cfc319364e[log][tgz]
authorDuncan Laurie <dlaurie@chromium.org>Tue Jan 13 18:36:01 2015
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>Tue Jan 13 20:49:03 2015
treeb9907bf043acc9fc4c02bf3d6ae81fb5f119f051
parentbf05d82b2132acbfed47e8bb3c616bb929fbfa39[diff]
ivybridge: Enable 2x refresh in memory controller

RW BIOS update to enable 2x refresh mode in the ivybridge
memory controller.

Since this is done in an RW update it needs to happen in
U-boot and it needs to be persistent across suspend/resume.

To accomplish this:
- on boot, enable 2x refresh in MCHBAR if it is not already
eanbled
- update the RW_MRC_CACHE to enable the same bit in the
saved MRC training data so it is applied on resume
- enable a protected range register to cover the RW_MRC_CACHE
region so it cannot be modified once booted.  (only done if
the SPI flash is write protected)

BUG=chrome-os-partner:35208
BRANCH=link
TEST=manual testing to build this into an RW update, load it
on a machine, and verify that 2x refresh is enabled and that
it persists across reboots and suspend/resume cycles.  Also
verify that the protected range register is enabled if the
SPI flash is write protected.

Change-Id: I357d49910bb95a32e141b7ef5648309f6f87c13a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240432
Reviewed-by: Kees Cook <keescook@chromium.org>
4 files changed
tree: b9907bf043acc9fc4c02bf3d6ae81fb5f119f051
  1. .checkpatch.conf
  2. .gitignore
  3. COPYING
  4. CREDITS
  5. MAINTAINERS
  6. MAKEALL
  7. Makefile
  8. PRESUBMIT.cfg
  9. README
  10. api/
  11. arch/
  12. board/
  13. boards.cfg
  14. common/
  15. config.mk
  16. cros/
  17. disk/
  18. doc/
  19. drivers/
  20. dts/
  21. examples/
  22. fs/
  23. include/
  24. lib/
  25. mkconfig
  26. nand_spl/
  27. net/
  28. onenand_ipl/
  29. post/
  30. rules.mk
  31. snapshot.commit
  32. spl/
  33. test/
  34. tools/