ivybridge: Enable 2x refresh in memory controller

RW BIOS update to enable 2x refresh mode in the ivybridge
memory controller.

Since this is done in an RW update it needs to happen in
U-boot and it needs to be persistent across suspend/resume.

To accomplish this:
- on boot, enable 2x refresh in MCHBAR if it is not already
eanbled
- update the RW_MRC_CACHE to enable the same bit in the
saved MRC training data so it is applied on resume
- enable a protected range register to cover the RW_MRC_CACHE
region so it cannot be modified once booted.  (only done if
the SPI flash is write protected)

BUG=chrome-os-partner:35208
BRANCH=firmware-stout-2817.B
TEST=manual testing to build this into an RW update, load it
on a machine, and verify that 2x refresh is enabled and that
it persists across reboots and suspend/resume cycles.  Also
verify that the protected range register is enabled if the
SPI flash is write protected.

Reviewed-on: https://chromium-review.googlesource.com/240432
Reviewed-by: Kees Cook <keescook@chromium.org>
(cherry picked from commit 3110373eb3d2482e0d96f7a359cdd1cfc319364e)

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I357d49910bb95a32e141b7ef5648309f6f87c13a
Reviewed-on: https://chromium-review.googlesource.com/255930
Reviewed-by: Shawn N <shawnn@chromium.org>
4 files changed