Merge remote-tracking branch cros/main into firmware-geralt-15842.B
Generated by: util/update_release_branch.py -r -z --board geralt --relevant_paths_file
util/corsola-relevant-paths.txt firmware-geralt-15842.B-main
TEST=`make -j buildall`
Cq-Depend: chromium:5806098
Force-Relevant-Builds: all
Change-Id: I74d11cf87fc734834eb55a01c268dc329634ed3f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5806099
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Knox Chiou <knoxchiou@chromium.org>
diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml
index 584bf61..09168ab 100644
--- a/.github/workflows/compliance.yml
+++ b/.github/workflows/compliance.yml
@@ -38,7 +38,7 @@
run: |
pip3 install setuptools
pip3 install wheel
- pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint
+ pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff
pip3 install west
- name: west setup
@@ -94,16 +94,23 @@
exit 1;
fi
+ warns=("ClangFormat")
files=($(./scripts/ci/check_compliance.py -l))
+
for file in "${files[@]}"; do
f="${file}.txt"
if [[ -s $f ]]; then
- errors=$(cat $f)
- errors="${errors//'%'/'%25'}"
- errors="${errors//$'\n'/'%0A'}"
- errors="${errors//$'\r'/'%0D'}"
- echo "::error file=${f}::$errors"
- exit=1
+ results=$(cat $f)
+ results="${results//'%'/'%25'}"
+ results="${results//$'\n'/'%0A'}"
+ results="${results//$'\r'/'%0D'}"
+
+ if [[ "${warns[@]}" =~ "${file}" ]]; then
+ echo "::warning file=${f}::$results"
+ else
+ echo "::error file=${f}::$results"
+ exit=1
+ fi
fi
done
diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml
index eb3d37d..d5be259 100644
--- a/.github/workflows/doc-build.yml
+++ b/.github/workflows/doc-build.yml
@@ -17,7 +17,7 @@
# The latest CMake available directly with apt is 3.18, but we need >=3.20
# so we fetch that through pip.
CMAKE_VERSION: 3.20.5
- DOXYGEN_VERSION: 1.9.6
+ DOXYGEN_VERSION: 1.12.0
# Job count is set to 2 less than the vCPU count of 16 because the total available RAM is 32GiB
# and each sphinx-build process may use more than 2GiB of RAM.
JOB_COUNT: 14
diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml
index bbcce51..08fd42d 100644
--- a/.github/workflows/hello_world_multiplatform.yaml
+++ b/.github/workflows/hello_world_multiplatform.yaml
@@ -26,7 +26,7 @@
strategy:
fail-fast: false
matrix:
- os: [ubuntu-22.04, macos-13, macos-14, windows-2022]
+ os: [ubuntu-22.04, ubuntu-24.04, macos-13, macos-14, windows-2022]
runs-on: ${{ matrix.os }}
steps:
- name: Checkout
diff --git a/.gitignore b/.gitignore
index 6644111..f590a8a3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -76,6 +76,7 @@
BinaryFiles.txt
BoardYml.txt
Checkpatch.txt
+ClangFormat.txt
DevicetreeBindings.txt
GitDiffCheck.txt
Gitlint.txt
diff --git a/CODEOWNERS b/CODEOWNERS
index 1ec0f1f..b867a24 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -188,6 +188,7 @@
/drivers/dai/intel/ssp/ @kv2019i @marcinszkudlinski @abonislawski
/drivers/dai/intel/dmic/ @marcinszkudlinski @abonislawski
/drivers/dai/intel/alh/ @abonislawski
+/drivers/dma/dma_dw_axi.c @pbalsundar
/drivers/dma/*dw* @tbursztyka
/drivers/dma/*dw_common* @abonislawski
/drivers/dma/*sam0* @Sizurka
@@ -367,7 +368,6 @@
/drivers/timer/*rcar_cmt* @aaillet
/drivers/timer/*esp32_sys* @uLipe
/drivers/timer/*sam0_rtc* @bendiscz
-/drivers/timer/*arcv2* @ruuddw
/drivers/timer/*xtensa* @dcpleung
/drivers/timer/*rv32m1_lptmr* @mbolivar
/drivers/timer/*nrf_rtc* @anangl
@@ -395,7 +395,6 @@
/drivers/wifi/eswifi/ @loicpoulain @nandojve
/drivers/wifi/winc1500/ @kludentwo
/drivers/virtualization/ @tbursztyka
-/dts/arc/ @abrodkin @ruuddw @iriszzw @evgeniy-paltsev
/dts/arm/acsip/ @NorthernDean
/dts/arm/aspeed/ @aspeeddylan
/dts/arm/atmel/ @galak @nandojve
diff --git a/Kconfig.zephyr b/Kconfig.zephyr
index 3b689ec..0e5c665 100644
--- a/Kconfig.zephyr
+++ b/Kconfig.zephyr
@@ -949,6 +949,8 @@
help
Symbol that must be selected by a feature or module if it is
considered to be deprecated.
+ When adding this to an option, remember to follow the instructions in
+ https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated
config WARN_DEPRECATED
bool
diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml
index 7cdf9b8..d99b41a 100644
--- a/MAINTAINERS.yml
+++ b/MAINTAINERS.yml
@@ -120,6 +120,7 @@
- include/zephyr/acpi/
- tests/lib/acpi/
- dts/bindings/acpi/
+ - include/zephyr/dt-bindings/acpi/
labels:
- "area: ACPI"
tests:
@@ -129,14 +130,16 @@
status: maintained
maintainers:
- ruuddw
+ - evgeniy-paltsev
collaborators:
- abrodkin
- - evgeniy-paltsev
files:
- arch/arc/
- include/zephyr/arch/arc/
+ - drivers/timer/*arcv2*
+ - drivers/interrupt_controller/*arcv2*
- tests/arch/arc/
- - dts/arc/synopsys/
+ - dts/arc/
- dts/bindings/arc/
- doc/hardware/arch/arc-support-status.rst
labels:
@@ -202,6 +205,7 @@
- soc/arm/fvp_aemv8*/
- dts/arm/armv*.dtsi
- dts/bindings/arm/arm*.yaml
+ - drivers/interrupt_controller/intc_gic*
labels:
- "platform: ARM"
@@ -314,6 +318,7 @@
- drivers/bluetooth/
- samples/bluetooth/hci_*/
- tests/bsim/bluetooth/hci_uart/
+ - dts/bindings/bluetooth/
labels:
- "area: Bluetooth Host"
- "area: Bluetooth"
@@ -382,7 +387,7 @@
- subsys/bluetooth/host/classic/
- include/zephyr/bluetooth/audio/
- include/zephyr/bluetooth/classic/
- - include/zephyr/bluetooth/audio/
+ - include/zephyr/bluetooth/mesh/
- include/zephyr/bluetooth/iso.h
- include/zephyr/bluetooth/controller.h
- include/zephyr/bluetooth/mesh.h
@@ -803,6 +808,18 @@
tests:
- debug
+"Debug: Profiling: Perf":
+ status: odd fixes
+ files:
+ - doc/services/profiling/perf.rst
+ - samples/subsys/profiling/perf/
+ - scripts/profiling/stackcollapse.py
+ - subsys/profiling/perf/
+ labels:
+ - "area: Profiling / Perf"
+ tests:
+ - debug.profiling.perf
+
"Debug: Symtab":
status: maintained
maintainers:
@@ -871,6 +888,8 @@
collaborators:
- decsny
- galak
+ files-regex:
+ - dts/bindings/.*zephyr.*
files:
- scripts/dts/
- dts/common/
@@ -880,6 +899,9 @@
- scripts/kconfig/kconfigfunctions.py
- doc/build/kconfig/preprocessor-functions.rst
- include/zephyr/devicetree.h
+ - include/zephyr/dt-bindings/dt-util.h
+ - dts/binding-template.yaml
+ - dts/bindings/base/
files-exclude:
- dts/common/nordic/
labels:
@@ -887,17 +909,6 @@
tests:
- libraries.devicetree
-Devicetree Bindings:
- status: odd fixes
- collaborators:
- - decsny
- - galak
- files:
- - include/zephyr/dt-bindings/
- - dts/binding-template.yaml
- labels:
- - "area: Devicetree Binding"
-
Disk:
status: maintained
maintainers:
@@ -914,6 +925,9 @@
- tests/subsys/sd/
- tests/drivers/disk/
- include/zephyr/sd/
+ - dts/bindings/sd/
+ - dts/bindings/mmc/
+ - dts/bindings/disk/
labels:
- "area: Disk Access"
tests:
@@ -927,6 +941,7 @@
files:
- drivers/display/
- dts/bindings/display/
+ - include/zephyr/dt-bindings/display/
- include/zephyr/drivers/display.h
- include/zephyr/display/
- include/zephyr/drivers/display.h
@@ -965,7 +980,6 @@
- doc/index-tex.rst
- doc/index.rst
- doc/kconfig.rst
- - doc/known-warnings.txt
- doc/templates/sample.tmpl
- doc/templates/board.tmpl
- boards/index.rst
@@ -1137,6 +1151,7 @@
files:
- drivers/clock_control/
- dts/bindings/clock/
+ - include/zephyr/dt-bindings/clock/
- include/zephyr/drivers/clock_control.h
- include/zephyr/dt-bindings/clock/
- tests/drivers/clock_control/
@@ -1213,6 +1228,8 @@
files:
- drivers/dac/
- include/zephyr/drivers/dac.h
+ - dts/bindings/dac/
+ - include/zephyr/dt-bindings/dac/
- tests/drivers/dac/
- samples/drivers/dac/
- doc/hardware/peripherals/dac.rst
@@ -1236,6 +1253,8 @@
- drivers/dai/
- doc/hardware/peripherals/audio/dai.rst
- include/zephyr/drivers/dai.h
+ - include/zephyr/dt-bindings/dai/
+ - dts/bindings/dai/
labels:
- "area: DAI"
@@ -1260,6 +1279,8 @@
- drivers/dma/
- tests/drivers/dma/
- include/zephyr/drivers/dma/
+ - dts/bindings/dma/
+ - include/zephyr/dt-bindings/dma/
- doc/hardware/peripherals/dma.rst
- include/zephyr/drivers/dma.h
- include/zephyr/dt-bindings/dma/
@@ -1306,6 +1327,8 @@
status: maintained
maintainers:
- ceolin
+ collaborators:
+ - tomi-font
files:
- drivers/entropy/
- include/zephyr/drivers/entropy.h
@@ -1363,6 +1386,7 @@
files:
- drivers/flash/
- dts/bindings/flash_controller/
+ - include/zephyr/dt-bindings/flash_controller/
- include/zephyr/drivers/flash.h
- samples/drivers/flash_shell/
- samples/drivers/soc_flash_nrf/
@@ -1418,6 +1442,7 @@
files:
- doc/hardware/peripherals/gpio.rst
- drivers/gpio/
+ - dts/bindings/gpio/
- include/zephyr/drivers/gpio/
- include/zephyr/drivers/gpio.h
- include/zephyr/dt-bindings/gpio/
@@ -1440,6 +1465,8 @@
- drivers/gnss/
- include/zephyr/drivers/gnss.h
- include/zephyr/drivers/gnss/
+ - dts/bindings/gnss/
+ - include/zephyr/dt-bindings/gnss/
- tests/drivers/build_all/gnss/
- tests/drivers/gnss/
labels:
@@ -1581,6 +1608,8 @@
- drivers/memc/
- samples/drivers/memc/
- tests/drivers/memc/
+ - include/zephyr/dt-bindings/memory-controller/
+ - dts/bindings/memory-controllers/
labels:
- "area: MEMC"
tests:
@@ -1645,6 +1674,7 @@
- drivers/reset/
- include/zephyr/drivers/reset.h
- dts/bindings/reset/
+ - include/zephyr/dt-bindings/reset/
"Interrupt Handling":
status: odd fixes
@@ -1715,6 +1745,7 @@
- doc/hardware/peripherals/led.rst
- tests/drivers/build_all/led/
- dts/bindings/led/
+ - include/zephyr/dt-bindings/led/
labels:
- "area: LED"
tests:
@@ -1771,10 +1802,10 @@
"Drivers: Regulators":
status: maintained
maintainers:
- - aasinclair
+ - gmarull
collaborators:
- danieldegrasse
- - gmarull
+ - aasinclair
files:
- drivers/regulator/
- include/zephyr/drivers/regulator/
@@ -1831,6 +1862,7 @@
- include/zephyr/drivers/pcie/
- doc/hardware/peripherals/pcie.rst
- dts/bindings/pcie/
+ - include/zephyr/dt-bindings/pcie/
labels:
- "area: PCI"
@@ -1916,6 +1948,7 @@
files:
- drivers/pwm/
- dts/bindings/pwm/
+ - include/zephyr/dt-bindings/pwm/
- tests/drivers/pwm/
- include/zephyr/*/pwms.h
- doc/hardware/peripherals/pwm.rst
@@ -2016,6 +2049,7 @@
- include/zephyr/drivers/spi.h
- tests/drivers/spi/
- dts/bindings/spi/
+ - include/zephyr/dt-bindings/spi/
- doc/hardware/peripherals/spi.rst
labels:
- "area: SPI"
@@ -2032,6 +2066,7 @@
- drivers/timer/
- include/zephyr/drivers/timer/
- dts/bindings/timer/
+ - include/zephyr/dt-bindings/timer/
labels:
- "area: Timer"
@@ -2119,6 +2154,8 @@
maintainers:
- krish2718
- jukkar
+ collaborators:
+ - sachinthegreen
files:
- drivers/wifi/nrfwifi/
- dts/bindings/wifi/nordic,nrf70.yaml
@@ -2158,6 +2195,7 @@
files:
- drivers/mipi_dbi/
- dts/bindings/mipi-dbi/
+ - include/zephyr/dt-bindings/mipi_dbi/
labels:
- "area: Display Controller"
@@ -2263,6 +2301,8 @@
maintainers:
- fabiobaltieri
- keith-zephyr
+ collaborators:
+ - duda-patryk
files:
- boards/google/
- samples/boards/google_*/
@@ -2321,6 +2361,7 @@
- tests/subsys/ipc/
- doc/services/ipc/
- dts/bindings/ipc/
+ - include/zephyr/dt-bindings/ipc_service/
description: >-
Inter-Processor Communication
labels:
@@ -2487,6 +2528,7 @@
- tests/lib/mem_blocks/
- doc/services/mem_mgmt/
- include/zephyr/mem_mgmt/mem_attr.h
+ - include/zephyr/dt-bindings/memory-attr/
- tests/lib/mem_blocks_stats/
- tests/drivers/mm/
tests:
@@ -2568,6 +2610,8 @@
- include/zephyr/lorawan/
- subsys/lorawan/
- samples/subsys/lorawan/
+ - include/zephyr/dt-bindings/lora/
+ - dts/bindings/lora/
- doc/connectivity/lora_lorawan/index.rst
labels:
- "area: LoRa"
@@ -2589,25 +2633,6 @@
description: >-
Zephyr Maintainers File
-Mbed TLS:
- status: maintained
- maintainers:
- - d3zd3z
- - ceolin
- collaborators:
- - ithinuel
- - valeriosetti
- files:
- - tests/crypto/mbedtls/
- - tests/benchmarks/mbedtls/
- labels:
- - "area: Crypto / RNG"
- description: >-
- Mbed TLS module implementing the PSA Crypto API and TLS.
- tests:
- - benchmark.crypto.mbedtls
- - crypto.mbedtls
-
MCU Manager:
status: maintained
maintainers:
@@ -3095,6 +3120,8 @@
- tests/subsys/pm/
- doc/services/pm/
- drivers/power_domain/
+ - dts/bindings/power/
+ - include/zephyr/dt-bindings/power/
labels:
- "area: Power Management"
tests:
@@ -3322,6 +3349,7 @@
- microbuilder
files:
- boards/adi/
+ - boards/shields/pmod_acl/
- drivers/*/*max*
- drivers/*/*max*/
- drivers/dac/dac_ltc*
@@ -3369,9 +3397,9 @@
status: maintained
maintainers:
- ruuddw
+ - evgeniy-paltsev
collaborators:
- abrodkin
- - evgeniy-paltsev
files:
- soc/snps/
- boards/snps/
@@ -3425,6 +3453,19 @@
labels:
- "platform: Nuvoton Numicro Numaker"
+Nuvoton NPCM Platforms:
+ status: maintained
+ maintainers:
+ - maxdog988
+ - warp5tw
+ - jc849
+ files:
+ - soc/nuvoton/npcm/
+ - boards/nuvoton/npcm*/
+ - dts/arm/nuvoton/
+ labels:
+ - "platform: Nuvoton NPCM"
+
Raspberry Pi Pico Platforms:
status: maintained
maintainers:
@@ -3568,6 +3609,8 @@
- drivers/misc/*/nxp*
- include/zephyr/dt-bindings/*/*nxp*
- include/zephyr/dt-bindings/*/*mcux*
+ - include/zephyr/dt-bindings/inputmux/
+ - include/zephyr/dt-bindings/rdc/
- include/zephyr/drivers/*/*nxp*
- include/zephyr/drivers/*/*mcux*
- arch/arm/core/mpu/nxp_mpu.c
@@ -3789,7 +3832,7 @@
- thaoluonguw
files:
- boards/arduino/uno_r4/
- - boards/renesas/*ra8*/
+ - boards/renesas/*ra*/
- drivers/*/*renesas_ra*
- drivers/pinctrl/renesas/ra/
- dts/arm/renesas/ra/
@@ -4120,24 +4163,6 @@
tests:
- sample.drivers.misc.timeaware_gpio
-TF-M Integration:
- status: maintained
- maintainers:
- - d3zd3z
- collaborators:
- - Vge0rge
- - ithinuel
- - valeriosetti
- files:
- - samples/tfm_integration/
- - modules/trusted-firmware-m/
- - doc/services/tfm/
- labels:
- - "area: TF-M"
- tests:
- - trusted-firmware-m
-
-
"Toolchain Integration":
status: maintained
maintainers:
@@ -4217,6 +4242,7 @@
files:
- drivers/usb/
- dts/bindings/usb/
+ - include/zephyr/dt-bindings/usb/
- include/zephyr/*/usb/
- include/zephyr/usb/
- samples/subsys/usb/
@@ -4240,6 +4266,7 @@
files:
- drivers/usb_c/
- dts/bindings/usb-c/
+ - include/zephyr/dt-bindings/usb-c/
- include/zephyr/*/usb_c/
- include/zephyr/usb_c/
- samples/subsys/usb_c/
@@ -4303,6 +4330,7 @@
- mbolivar-ampere
- carlescufi
- swinslow
+ - pdgendt
files:
- scripts/west-commands.yml
- scripts/west_commands/
@@ -4611,6 +4639,11 @@
collaborators:
- hubertmis
- nordic-krch
+ - krish2718
+ - sachinthegreen
+ - udaynordic
+ - rajb9
+ - srkanordic
files:
- modules/hal_nordic/
labels:
@@ -4819,6 +4852,7 @@
files:
- modules/lvgl/
- tests/lib/gui/lvgl/
+ - include/zephyr/dt-bindings/lvgl/
labels:
- "area: LVGL"
@@ -4840,10 +4874,16 @@
collaborators:
- ithinuel
- valeriosetti
+ - tomi-font
files:
- modules/mbedtls/
+ - tests/crypto/mbedtls/
+ - tests/benchmarks/mbedtls/
labels:
- - "area: Crypto / RNG"
+ - "area: mbedTLS / PSA Crypto"
+ tests:
+ - benchmark.crypto.mbedtls
+ - crypto.mbedtls
"West project: mcuboot":
status: maintained
@@ -5007,10 +5047,16 @@
collaborators:
- Vge0rge
- ithinuel
+ - valeriosetti
+ - tomi-font
files:
- modules/trusted-firmware-m/
+ - samples/tfm_integration/
+ - doc/services/tfm/
labels:
- "area: TF-M"
+ tests:
+ - trusted-firmware-m
"West project: tf-m-tests":
status: maintained
@@ -5194,6 +5240,8 @@
status: maintained
maintainers:
- ceolin
+ collaborators:
+ - tomi-font
files:
- subsys/random/
- include/zephyr/random/
diff --git a/arch/arm/core/cortex_a_r/boot.h b/arch/arm/core/cortex_a_r/boot.h
index 7eeba8b..8930679 100644
--- a/arch/arm/core/cortex_a_r/boot.h
+++ b/arch/arm/core/cortex_a_r/boot.h
@@ -26,5 +26,6 @@
#define BOOT_PARAM_UDF_SP_OFFSET 16
#define BOOT_PARAM_SVC_SP_OFFSET 20
#define BOOT_PARAM_SYS_SP_OFFSET 24
+#define BOOT_PARAM_VOTING_OFFSET 28
#endif /* _BOOT_H_ */
diff --git a/arch/arm/core/cortex_a_r/isr_wrapper.S b/arch/arm/core/cortex_a_r/isr_wrapper.S
index 2e2256f..3dd678c 100644
--- a/arch/arm/core/cortex_a_r/isr_wrapper.S
+++ b/arch/arm/core/cortex_a_r/isr_wrapper.S
@@ -339,6 +339,15 @@
str r0, [r2, #___cpu_t_nested_OFFSET]
/* Do not context switch if exiting a nested interrupt */
cmp r0, #0
+ /* Note that this function is only called from `z_arm_svc`,
+ * while handling irq_offload, with below modes set:
+ * ```
+ * if (cpu interrupts are nested)
+ * mode=MODE_SYS
+ * else
+ * mode=MODE_IRQ
+ * ```
+ */
bhi __EXIT_INT
/* retrieve pointer to the current thread */
diff --git a/arch/arm/core/cortex_a_r/macro_priv.inc b/arch/arm/core/cortex_a_r/macro_priv.inc
index e024336..aafa87c 100644
--- a/arch/arm/core/cortex_a_r/macro_priv.inc
+++ b/arch/arm/core/cortex_a_r/macro_priv.inc
@@ -18,6 +18,27 @@
ubfx \rreg0, \rreg0, #0, #24
.endm
+/*
+ * Get CPU logic id by looking up cpu_node_list
+ * returns
+ * reg0: MPID
+ * reg1: logic id (0 ~ CONFIG_MP_MAX_NUM_CPUS - 1)
+ * clobbers: reg0, reg1, reg2, reg3
+ */
+.macro get_cpu_logic_id reg0, reg1, reg2, reg3
+ get_cpu_id \reg0
+ ldr \reg3, =cpu_node_list
+ mov \reg1, #0
+1: ldr \reg2, [\reg3, \reg1, lsl #2]
+ cmp \reg2, \reg0
+ beq 2f
+ add \reg1, \reg1, #1
+ cmp \reg1, #CONFIG_MP_MAX_NUM_CPUS
+ bne 1b
+ b .
+2:
+.endm
+
.macro get_cpu rreg0
/*
* Get CPU pointer.
@@ -33,8 +54,7 @@
*/
srsdb sp!, #MODE_SYS
cps #MODE_SYS
- stmdb sp, {r0-r3, r12, lr}^
- sub sp, #24
+ push {r0-r3, r12, lr}
/* TODO: EXTRA_EXCEPTION_INFO */
mov r0, sp
diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S
index 0b107fb..5cba6cb 100644
--- a/arch/arm/core/cortex_a_r/reset.S
+++ b/arch/arm/core/cortex_a_r/reset.S
@@ -200,23 +200,62 @@
#endif /* CONFIG_DCLS */
ldr r0, =arm_cpu_boot_params
+
#if CONFIG_MP_MAX_NUM_CPUS > 1
- get_cpu_id r1
+ /*
+ * This code uses voting locks, like arch/arm64/core/reset.S, to determine primary CPU.
+ */
- ldrex r2, [r0, #BOOT_PARAM_MPID_OFFSET]
- cmp r2, #-1
- bne 1f
- strex r3, r1, [r0, #BOOT_PARAM_MPID_OFFSET]
- cmp r3, #0
+ /*
+ * Get the "logic" id defined by cpu_node_list statically for voting lock self-identify.
+ * It is worth noting that this is NOT the final logic id (arch_curr_cpu()->id)
+ */
+ get_cpu_logic_id r1, r2, r3, r4 // r1: MPID, r2: logic id
+
+ add r4, r0, #BOOT_PARAM_VOTING_OFFSET
+
+ /* signal our desire to vote */
+ mov r5, #1
+ strb r5, [r4, r2]
+ ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET]
+ cmn r3, #1
+ beq 1f
+
+ /* some core already won, release */
+ mov r7, #0
+ strb r7, [r4, r2]
+ b _secondary_core
+
+ /* suggest current core then release */
+1: str r1, [r0, #BOOT_PARAM_MPID_OFFSET]
+ strb r7, [r4, r2]
+ dmb
+
+ /* then wait until every core else is done voting */
+ mov r5, #0
+2: ldrb r3, [r4, r5]
+ tst r3, #255
+ /* wait */
+ bne 2b
+ add r5, r5, #1
+ cmp r5, #CONFIG_MP_MAX_NUM_CPUS
+ bne 2b
+
+ /* check if current core won */
+ dmb
+ ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET]
+ cmp r3, r1
beq _primary_core
+ /* fallthrough secondary */
-1:
- dmb ld
+ /* loop until our turn comes */
+_secondary_core:
+ dmb
ldr r2, [r0, #BOOT_PARAM_MPID_OFFSET]
cmp r1, r2
- bne 1b
+ bne _secondary_core
- /* we can now move on */
+ /* we can now load our stack pointer values and move on */
ldr r4, =arch_secondary_cpu_init
ldr r5, [r0, #BOOT_PARAM_FIQ_SP_OFFSET]
ldr r6, [r0, #BOOT_PARAM_IRQ_SP_OFFSET]
diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c
index 0214b47..6579cb4 100644
--- a/arch/arm/core/cortex_a_r/smp.c
+++ b/arch/arm/core/cortex_a_r/smp.c
@@ -51,6 +51,7 @@
char *udf_sp;
char *svc_sp;
char *sys_sp;
+ uint8_t voting[CONFIG_MP_MAX_NUM_CPUS];
arch_cpustart_t fn;
void *arg;
int cpu_num;
@@ -64,6 +65,7 @@
BUILD_ASSERT(offsetof(struct boot_params, udf_sp) == BOOT_PARAM_UDF_SP_OFFSET);
BUILD_ASSERT(offsetof(struct boot_params, svc_sp) == BOOT_PARAM_SVC_SP_OFFSET);
BUILD_ASSERT(offsetof(struct boot_params, sys_sp) == BOOT_PARAM_SYS_SP_OFFSET);
+BUILD_ASSERT(offsetof(struct boot_params, voting) == BOOT_PARAM_VOTING_OFFSET);
volatile struct boot_params arm_cpu_boot_params = {
.mpid = -1,
@@ -75,7 +77,7 @@
.sys_sp = (char *)(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE),
};
-static const uint32_t cpu_node_list[] = {
+const uint32_t cpu_node_list[] = {
DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,))};
/* cpu_map saves the maping of core id and mpid */
diff --git a/arch/arm/core/cortex_a_r/vector_table.S b/arch/arm/core/cortex_a_r/vector_table.S
index 8c1060e..e74b6a4 100644
--- a/arch/arm/core/cortex_a_r/vector_table.S
+++ b/arch/arm/core/cortex_a_r/vector_table.S
@@ -41,6 +41,11 @@
GTEXT(z_arm_cortex_ar_exit_exc)
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
+ /* Note:
+ * This function is expected to be *always* called with
+ * processor mode set to MODE_SYS.
+ */
+
/* decrement exception depth */
get_cpu r2
ldrb r1, [r2, #_cpu_offset_to_exc_depth]
@@ -51,7 +56,6 @@
* Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack
* and return to the current thread.
*/
- ldmia sp, {r0-r3, r12, lr}^
- add sp, #24
+ pop {r0-r3, r12, lr}
rfeia sp!
#endif
diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S
index 1e5bca0..f9c82b4 100644
--- a/arch/arm/core/cortex_m/pm_s2ram.S
+++ b/arch/arm/core/cortex_m/pm_s2ram.S
@@ -27,6 +27,11 @@
* r0: address of the system_off function
*/
push {r4-r12, lr}
+
+ /* Move system_off to protected register. */
+ mov r4, r0
+
+ /* Store CPU context */
ldr r1, =_cpu_context
mrs r2, msp
@@ -71,7 +76,7 @@
* Call the system_off function passed as parameter. This should never
* return.
*/
- blx r0
+ blx r4
/*
* The system_off function returns here only when the powering off was
@@ -81,9 +86,10 @@
/*
* Reset the marking of suspend to RAM, return is ignored.
*/
- push {r0}
bl pm_s2ram_mark_check_and_clear
- pop {r0}
+
+ /* Move system_off back to r0 as return value */
+ mov r0, r4
pop {r4-r12, lr}
bx lr
@@ -93,11 +99,14 @@
SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
/*
* Check if reset occurred after suspending to RAM.
+ * Store LR to ensure we can continue boot when we are not suspended
+ * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0",
+ * as stated by ARM rule 6.2.1.2 for AAPCS32.
*/
- push {lr}
+ push {r0, lr}
bl pm_s2ram_mark_check_and_clear
cmp r0, #0x1
- pop {lr}
+ pop {r0, lr}
beq resume
bx lr
diff --git a/arch/posix/core/CMakeLists.txt b/arch/posix/core/CMakeLists.txt
index 12ec526..8c46147 100644
--- a/arch/posix/core/CMakeLists.txt
+++ b/arch/posix/core/CMakeLists.txt
@@ -21,10 +21,12 @@
if(CONFIG_NATIVE_APPLICATION)
zephyr_include_directories(
nsi_compat/
+ ${ZEPHYR_BASE}/scripts/native_simulator/common/src/include/
)
zephyr_library_sources(
- posix_core.c
+ posix_core_nsi.c
nsi_compat/nsi_compat.c
+ ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nct.c
${ZEPHYR_BASE}/scripts/native_simulator/common/src/nce.c
${ZEPHYR_BASE}/scripts/native_simulator/common/src/nsi_host_trampolines.c
)
diff --git a/arch/posix/core/nsi_compat/nce_if.h b/arch/posix/core/nsi_compat/nce_if.h
deleted file mode 100644
index be5772a..0000000
--- a/arch/posix/core/nsi_compat/nce_if.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef NSI_COMMON_SRC_INCL_NCE_IF_H
-#define NSI_COMMON_SRC_INCL_NCE_IF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Native simulator CPU start/stop emulation module interface */
-
-void *nce_init(void);
-void nce_terminate(void *this);
-void nce_boot_cpu(void *this, void (*start_routine)(void));
-void nce_halt_cpu(void *this);
-void nce_wake_cpu(void *this);
-int nce_is_cpu_running(void *this);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* NSI_COMMON_SRC_INCL_NCE_IF_H */
diff --git a/arch/posix/core/nsi_compat/nsi_host_trampolines.h b/arch/posix/core/nsi_compat/nsi_host_trampolines.h
deleted file mode 100644
index f0a2e06..0000000
--- a/arch/posix/core/nsi_compat/nsi_host_trampolines.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Note: This is a provisional header which exists to allow
- * old POSIX arch based boards (i.e. native_posix) to provide access
- * to the host C library as if the native simulator trampolines
- * existed.
- *
- * Boards based on the native simulator do NOT use this file
- */
-
-#ifndef ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H
-#define ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H
-
-#include "../scripts/native_simulator/common/src/include/nsi_host_trampolines.h"
-
-#endif /* ARCH_POSIX_CORE_NSI_COMPAT_NSI_HOST_TRAMPOLINES_H */
diff --git a/arch/posix/core/nsi_compat/nsi_safe_call.h b/arch/posix/core/nsi_compat/nsi_safe_call.h
deleted file mode 100644
index 6227cb1..0000000
--- a/arch/posix/core/nsi_compat/nsi_safe_call.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ARCH_POSIX_CORE_NSI_SAFE_CALLL_H
-#define ARCH_POSIX_CORE_NSI_SAFE_CALLL_H
-
-#include "nsi_tracing.h"
-#include "posix_arch_internal.h"
-
-#define NSI_SAFE_CALL PC_SAFE_CALL
-
-#endif /* ARCH_POSIX_CORE_NSI_SAFE_CALLL_H */
diff --git a/arch/posix/core/nsi_compat/nsi_tracing.h b/arch/posix/core/nsi_compat/nsi_tracing.h
deleted file mode 100644
index 854873b..0000000
--- a/arch/posix/core/nsi_compat/nsi_tracing.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ARCH_POSIX_CORE_NSI_TRACING_H
-#define ARCH_POSIX_CORE_NSI_TRACING_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void nsi_print_error_and_exit(const char *format, ...);
-void nsi_print_warning(const char *format, ...);
-void nsi_print_trace(const char *format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ARCH_POSIX_CORE_NSI_TRACING_H */
diff --git a/arch/posix/core/posix_core.c b/arch/posix/core/posix_core.c
deleted file mode 100644
index 89310f1..0000000
--- a/arch/posix/core/posix_core.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * Here is where things actually happen for the POSIX arch
- *
- * We isolate all functions here, to ensure they can be compiled as
- * independently as possible to the remainder of Zephyr to avoid name clashes
- * as Zephyr does provide functions with the same names as the POSIX threads
- * functions
- */
-/**
- * Principle of operation:
- *
- * The Zephyr OS and its app run as a set of native pthreads.
- * The Zephyr OS only sees one of this thread executing at a time.
- * Which is running is controlled using {cond|mtx}_threads and
- * currently_allowed_thread.
- *
- * The main part of the execution of each thread will occur in a fully
- * synchronous and deterministic manner, and only when commanded by the Zephyr
- * kernel.
- * But the creation of a thread will spawn a new pthread whose start
- * is asynchronous to the rest, until synchronized in posix_wait_until_allowed()
- * below.
- * Similarly aborting and canceling threads execute a tail in a quite
- * asynchronous manner.
- *
- * This implementation is meant to be portable in between POSIX systems.
- * A table (threads_table) is used to abstract the native pthreads.
- * And index in this table is used to identify threads in the IF to the kernel.
- *
- */
-
-#include <pthread.h>
-#include <stdbool.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "posix_core.h"
-#include "posix_arch_internal.h"
-
-#define PREFIX "POSIX arch core: "
-#define ERPREFIX PREFIX"error on "
-#define NO_MEM_ERR PREFIX"Can't allocate memory\n"
-
-#define PC_ENABLE_CANCEL 0 /* See Note.c1 */
-#define PC_ALLOC_CHUNK_SIZE 64
-#define PC_REUSE_ABORTED_ENTRIES 0
-/* tests/kernel/threads/scheduling/schedule_api fails when setting
- * PC_REUSE_ABORTED_ENTRIES => don't set it by now
- */
-
-static int threads_table_size;
-struct threads_table_el {
- enum {NOTUSED = 0, USED, ABORTING, ABORTED, FAILED} state;
- bool running; /* Is this the currently running thread */
- pthread_t thread; /* Actual pthread_t as returned by native kernel */
- int thead_cnt; /* For debugging: Unique, consecutive, thread number */
- /* Pointer to the status kept in the Zephyr thread stack */
- posix_thread_status_t *t_status;
-};
-
-static struct threads_table_el *threads_table;
-
-static int thread_create_count; /* For debugging. Thread creation counter */
-
-/*
- * Conditional variable to block/awake all threads during swaps()
- * (we only need 1 mutex and 1 cond variable for all threads)
- */
-static pthread_cond_t cond_threads = PTHREAD_COND_INITIALIZER;
-/* Mutex for the conditional variable posix_core_cond_threads */
-static pthread_mutex_t mtx_threads = PTHREAD_MUTEX_INITIALIZER;
-/* Token which tells which process is allowed to run now */
-static int currently_allowed_thread;
-
-static bool terminate; /* Are we terminating the program == cleaning up */
-
-static void posix_wait_until_allowed(int this_th_nbr);
-static void *posix_thread_starter(void *arg);
-static void posix_preexit_cleanup(void);
-extern void posix_arch_thread_entry(void *pa_thread_status);
-
-/**
- * Helper function, run by a thread is being aborted
- */
-static void abort_tail(int this_th_nbr)
-{
- PC_DEBUG("Thread [%i] %i: %s: Aborting (exiting) (rel mut)\n",
- threads_table[this_th_nbr].thead_cnt,
- this_th_nbr,
- __func__);
-
- threads_table[this_th_nbr].running = false;
- threads_table[this_th_nbr].state = ABORTED;
- posix_preexit_cleanup();
- pthread_exit(NULL);
-}
-
-/**
- * Helper function to block this thread until it is allowed again
- * (somebody calls posix_let_run() with this thread number
- *
- * Note that we go out of this function (the while loop below)
- * with the mutex locked by this particular thread.
- * In normal circumstances, the mutex is only unlocked internally in
- * pthread_cond_wait() while waiting for cond_threads to be signaled
- */
-static void posix_wait_until_allowed(int this_th_nbr)
-{
- threads_table[this_th_nbr].running = false;
-
- PC_DEBUG("Thread [%i] %i: %s: Waiting to be allowed to run (rel mut)\n",
- threads_table[this_th_nbr].thead_cnt,
- this_th_nbr,
- __func__);
-
- while (this_th_nbr != currently_allowed_thread) {
- pthread_cond_wait(&cond_threads, &mtx_threads);
-
- if (threads_table &&
- (threads_table[this_th_nbr].state == ABORTING)) {
- abort_tail(this_th_nbr);
- }
- }
-
- threads_table[this_th_nbr].running = true;
-
- PC_DEBUG("Thread [%i] %i: %s(): I'm allowed to run! (hav mut)\n",
- threads_table[this_th_nbr].thead_cnt,
- this_th_nbr,
- __func__);
-}
-
-
-/**
- * Helper function to let the thread <next_allowed_th> run
- * Note: posix_let_run() can only be called with the mutex locked
- */
-static void posix_let_run(int next_allowed_th)
-{
- PC_DEBUG("%s: We let thread [%i] %i run\n",
- __func__,
- threads_table[next_allowed_th].thead_cnt,
- next_allowed_th);
-
-
- currently_allowed_thread = next_allowed_th;
-
- /*
- * We let all threads know one is able to run now (it may even be us
- * again if fancied)
- * Note that as we hold the mutex, they are going to be blocked until
- * we reach our own posix_wait_until_allowed() while loop
- */
- PC_SAFE_CALL(pthread_cond_broadcast(&cond_threads));
-}
-
-
-static void posix_preexit_cleanup(void)
-{
- /*
- * Release the mutex so the next allowed thread can run
- */
- PC_SAFE_CALL(pthread_mutex_unlock(&mtx_threads));
-
- /* We detach ourselves so nobody needs to join to us */
- pthread_detach(pthread_self());
-}
-
-
-/**
- * Let the ready thread run and block this thread until it is allowed again
- *
- * called from arch_swap() which does the picking from the kernel structures
- */
-void posix_swap(int next_allowed_thread_nbr, int this_th_nbr)
-{
- posix_let_run(next_allowed_thread_nbr);
-
- if (threads_table[this_th_nbr].state == ABORTING) {
- PC_DEBUG("Thread [%i] %i: %s: Aborting curr.\n",
- threads_table[this_th_nbr].thead_cnt,
- this_th_nbr,
- __func__);
- abort_tail(this_th_nbr);
- } else {
- posix_wait_until_allowed(this_th_nbr);
- }
-}
-
-/**
- * Let the ready thread (main) run, and exit this thread (init)
- *
- * Called from arch_switch_to_main_thread() which does the picking from the
- * kernel structures
- *
- * Note that we could have just done a swap(), but that would have left the
- * init thread lingering. Instead here we exit the init thread after enabling
- * the new one
- */
-void posix_main_thread_start(int next_allowed_thread_nbr)
-{
- posix_let_run(next_allowed_thread_nbr);
- PC_DEBUG("%s: Init thread dying now (rel mut)\n",
- __func__);
- posix_preexit_cleanup();
- pthread_exit(NULL);
-}
-
-/**
- * Handler called when any thread is cancelled or exits
- */
-static void posix_cleanup_handler(void *arg)
-{
- /*
- * If we are not terminating, this is just an aborted thread,
- * and the mutex was already released
- * Otherwise, release the mutex so other threads which may be
- * caught waiting for it could terminate
- */
-
- if (!terminate) {
- return;
- }
-
-#if POSIX_ARCH_DEBUG_PRINTS
- posix_thread_status_t *ptr = (posix_thread_status_t *) arg;
-
- PC_DEBUG("Thread %i: %s: Canceling (rel mut)\n",
- ptr->thread_idx,
- __func__);
-#endif
-
-
- PC_SAFE_CALL(pthread_mutex_unlock(&mtx_threads));
-
- /* We detach ourselves so nobody needs to join to us */
- pthread_detach(pthread_self());
-}
-
-/**
- * Helper function to start a Zephyr thread as a POSIX thread:
- * It will block the thread until a arch_swap() is called for it
- *
- * Spawned from posix_new_thread() below
- */
-static void *posix_thread_starter(void *arg)
-{
- int thread_idx = (intptr_t)arg;
-
- PC_DEBUG("Thread [%i] %i: %s: Starting\n",
- threads_table[thread_idx].thead_cnt,
- thread_idx,
- __func__);
-
- /*
- * We block until all other running threads reach the while loop
- * in posix_wait_until_allowed() and they release the mutex
- */
- PC_SAFE_CALL(pthread_mutex_lock(&mtx_threads));
-
- /*
- * The program may have been finished before this thread ever got to run
- */
- /* LCOV_EXCL_START */ /* See Note1 */
- if (!threads_table) {
- posix_cleanup_handler(arg);
- pthread_exit(NULL);
- }
- /* LCOV_EXCL_STOP */
-
- pthread_cleanup_push(posix_cleanup_handler, arg);
-
- PC_DEBUG("Thread [%i] %i: %s: After start mutex (hav mut)\n",
- threads_table[thread_idx].thead_cnt,
- thread_idx,
- __func__);
-
- /*
- * The thread would try to execute immediately, so we block it
- * until allowed
- */
- posix_wait_until_allowed(thread_idx);
-
- posix_thread_status_t *ptr = threads_table[thread_idx].t_status;
-
- posix_arch_thread_entry(ptr);
-
- /*
- * We only reach this point if the thread actually returns which should
- * not happen. But we handle it gracefully just in case
- */
- /* LCOV_EXCL_START */
- posix_print_trace(PREFIX"Thread [%i] %i [%lu] ended!?!\n",
- threads_table[thread_idx].thead_cnt,
- thread_idx,
- pthread_self());
-
-
- threads_table[thread_idx].running = false;
- threads_table[thread_idx].state = FAILED;
-
- pthread_cleanup_pop(1);
-
- return NULL;
- /* LCOV_EXCL_STOP */
-}
-
-/**
- * Return the first free entry index in the threads table
- */
-static int ttable_get_empty_slot(void)
-{
-
- for (int i = 0; i < threads_table_size; i++) {
- if ((threads_table[i].state == NOTUSED)
- || (PC_REUSE_ABORTED_ENTRIES
- && (threads_table[i].state == ABORTED))) {
- return i;
- }
- }
-
- /*
- * else, we run out table without finding an index
- * => we expand the table
- */
-
- threads_table = realloc(threads_table,
- (threads_table_size + PC_ALLOC_CHUNK_SIZE)
- * sizeof(struct threads_table_el));
- if (threads_table == NULL) { /* LCOV_EXCL_BR_LINE */
- posix_print_error_and_exit(NO_MEM_ERR); /* LCOV_EXCL_LINE */
- }
-
- /* Clear new piece of table */
- (void)memset(&threads_table[threads_table_size], 0,
- PC_ALLOC_CHUNK_SIZE * sizeof(struct threads_table_el));
-
- threads_table_size += PC_ALLOC_CHUNK_SIZE;
-
- /* The first newly created entry is good: */
- return threads_table_size - PC_ALLOC_CHUNK_SIZE;
-}
-
-/**
- * Called from arch_new_thread(),
- * Create a new POSIX thread for the new Zephyr thread.
- * arch_new_thread() picks from the kernel structures what it is that we need
- * to call with what parameters
- */
-int posix_new_thread(void *ptr)
-{
- int t_slot;
-
- t_slot = ttable_get_empty_slot();
- threads_table[t_slot].state = USED;
- threads_table[t_slot].running = false;
- threads_table[t_slot].thead_cnt = thread_create_count++;
- threads_table[t_slot].t_status = ptr;
-
- /*
- * Note: If you are here due to a valgrind reported memory leak in
- * pthread_create() please use the provided valgrind.supp suppression file.
- */
- PC_SAFE_CALL(pthread_create(&threads_table[t_slot].thread,
- NULL,
- posix_thread_starter,
- (void *)(intptr_t)t_slot));
-
- PC_DEBUG("%s created thread [%i] %i [%lu]\n",
- __func__,
- threads_table[t_slot].thead_cnt,
- t_slot,
- threads_table[t_slot].thread);
-
- return t_slot;
-}
-
-/*
- * Initialize the posix architecture
- *
- * Prepare whatever needs to be prepared to be able to start threads
- */
-void posix_arch_init(void)
-{
- thread_create_count = 0;
-
- currently_allowed_thread = -1;
-
- threads_table = calloc(PC_ALLOC_CHUNK_SIZE,
- sizeof(struct threads_table_el));
- if (threads_table == NULL) { /* LCOV_EXCL_BR_LINE */
- posix_print_error_and_exit(NO_MEM_ERR); /* LCOV_EXCL_LINE */
- }
-
- threads_table_size = PC_ALLOC_CHUNK_SIZE;
-
-
- PC_SAFE_CALL(pthread_mutex_lock(&mtx_threads));
-}
-
-/*
- * Free any allocated memory by the posix core and clean up.
- * Note that this function cannot be called from a SW thread
- * (the CPU is assumed halted. Otherwise we will cancel ourselves)
- *
- * This function cannot guarantee the threads will be cancelled before the HW
- * thread exists. The only way to do that, would be to wait for each of them in
- * a join (without detaching them, but that could lead to locks in some
- * convoluted cases. As a call to this function can come from an ASSERT or other
- * error termination, we better do not assume things are working fine.
- * => we prefer the supposed memory leak report from valgrind, and ensure we
- * will not hang
- */
-void posix_arch_clean_up(void)
-{
-
- if (!threads_table) { /* LCOV_EXCL_BR_LINE */
- return; /* LCOV_EXCL_LINE */
- }
-
- terminate = true;
-
-#if (PC_ENABLE_CANCEL)
- for (int i = 0; i < threads_table_size; i++) {
- if (threads_table[i].state != USED) {
- continue;
- }
-
- /* LCOV_EXCL_START */
- if (pthread_cancel(threads_table[i].thread)) {
- posix_print_warning(
- PREFIX"cleanup: could not stop thread %i\n",
- i);
- }
- /* LCOV_EXCL_STOP */
- }
-#endif
-
- free(threads_table);
- threads_table = NULL;
-}
-
-void posix_abort_thread(int thread_idx)
-{
- if (thread_idx == currently_allowed_thread) {
- PC_DEBUG("Thread [%i] %i: %s Marked myself "
- "as aborting\n",
- threads_table[thread_idx].thead_cnt,
- thread_idx,
- __func__);
- } else {
- if (threads_table[thread_idx].state != USED) { /* LCOV_EXCL_BR_LINE */
- /* The thread may have been already aborted before */
- return; /* LCOV_EXCL_LINE */
- }
-
- PC_DEBUG("Aborting not scheduled thread [%i] %i\n",
- threads_table[thread_idx].thead_cnt,
- thread_idx);
- }
-
- threads_table[thread_idx].state = ABORTING;
- /*
- * Note: the native thread will linger in RAM until it catches the
- * mutex or awakes on the condition.
- * Note that even if we would pthread_cancel() the thread here, that
- * would be the case, but with a pthread_cancel() the mutex state would
- * be uncontrolled
- */
-
-}
-
-int posix_arch_get_unique_thread_id(int thread_idx)
-{
- return threads_table[thread_idx].thead_cnt;
-}
-
-/*
- * Notes about coverage:
- *
- * Note1:
- *
- * This condition will only be triggered in very unlikely cases
- * (once every few full regression runs).
- * It is therefore excluded from the coverage report to avoid confusing
- * developers.
- *
- * Background: This arch creates a pthread as soon as the Zephyr kernel creates
- * a Zephyr thread. A pthread creation is an asynchronous process handled by the
- * host kernel.
- *
- * This architecture normally keeps only 1 thread executing at a time.
- * But part of the pre-initialization during creation of a new thread
- * and some cleanup at the tail of the thread termination are executed
- * in parallel to other threads.
- * That is, the execution of those code paths is a bit indeterministic.
- *
- * Only when the Zephyr kernel attempts to swap to a new thread does this
- * architecture need to wait until its pthread is ready and initialized
- * (has reached posix_wait_until_allowed())
- *
- * In some cases (tests) threads are created which are never actually needed
- * (typically the idle thread). That means the test may finish before this
- * thread's underlying pthread has reached posix_wait_until_allowed().
- *
- * In this unlikely cases the initialization or cleanup of the thread follows
- * non-typical code paths.
- * This code paths are there to ensure things work always, no matter
- * the load of the host. Without them, very rare & mysterious segfault crashes
- * would occur.
- * But as they are very atypical and only triggered with some host loads,
- * they will be covered in the coverage reports only rarely.
- *
- * Note2:
- *
- * Some other code will never or only very rarely trigger and is therefore
- * excluded with LCOV_EXCL_LINE
- *
- *
- * Notes about (memory) cleanup:
- *
- * Note.c1:
- *
- * In some very rare cases in very loaded machines, a race in the glibc pthread_cancel()
- * seems to be triggered.
- * In this, the cancelled thread cleanup overtakes the pthread_cancel() code, and frees the
- * pthread structure before pthread_cancel() has finished, resulting in a dereference into already
- * free'd memory, and therefore a segfault.
- * Calling pthread_cancel() during cleanup is not required beyond preventing a valgrind
- * memory leak report (all threads will be canceled immediately on exit).
- * Therefore we do not do this, to avoid this very rare crashes.
- */
diff --git a/arch/x86/core/ia32/intstub.S b/arch/x86/core/ia32/intstub.S
index 4cd5c0b..dd45467 100644
--- a/arch/x86/core/ia32/intstub.S
+++ b/arch/x86/core/ia32/intstub.S
@@ -112,11 +112,12 @@
* EAX = isr_param, EDX = isr
*/
- /* Push EDI as we will use it for scratch space.
+ /* Push EBP as we will use it for scratch space.
+ * Also it helps in stack unwinding
* Rest of the callee-saved regs get saved by invocation of C
* functions (isr handler, arch_swap(), etc)
*/
- pushl %edi
+ pushl %ebp
/* load %ecx with &_kernel */
@@ -131,17 +132,17 @@
jne alreadyOnIntStack
/*
- * switch to base of the interrupt stack: save esp in edi, then load
+ * switch to base of the interrupt stack: save esp in ebp, then load
* irq_stack pointer
*/
- movl %esp, %edi
+ movl %esp, %ebp
movl _kernel_offset_to_irq_stack(%ecx), %esp
/* save thread's stack pointer onto base of interrupt stack */
- pushl %edi /* Save stack pointer */
+ pushl %ebp /* Save stack pointer */
#ifdef CONFIG_PM
cmpl $0, _kernel_offset_to_idle(%ecx)
@@ -265,7 +266,7 @@
#endif /* CONFIG_LAZY_FPU_SHARING */
/* Restore volatile registers and return to the interrupted thread */
- popl %edi
+ popl %ebp
popl %ecx
popl %edx
popl %eax
@@ -298,7 +299,7 @@
*/
nestedInterrupt:
- popl %edi
+ popl %ebp
popl %ecx /* pop volatile registers in reverse order */
popl %edx
popl %eax
diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c
index 675949c..c02ecc6 100644
--- a/arch/xtensa/core/ptables.c
+++ b/arch/xtensa/core/ptables.c
@@ -267,6 +267,12 @@
static void xtensa_init_page_tables(void)
{
volatile uint8_t entry;
+ static bool already_inited;
+
+ if (already_inited) {
+ return;
+ }
+ already_inited = true;
init_page_table(xtensa_kernel_ptables, XTENSA_L1_PAGE_TABLE_ENTRIES);
atomic_set_bit(l1_page_table_track, 0);
@@ -305,15 +311,7 @@
void xtensa_mmu_init(void)
{
- if (_current_cpu->id == 0) {
- /* This is normally done via arch_kernel_init() inside z_cstart().
- * However, before that is called, we go through the sys_init of
- * INIT_LEVEL_EARLY, which is going to result in TLB misses.
- * So setup whatever necessary so the exception handler can work
- * properly.
- */
- xtensa_init_page_tables();
- }
+ xtensa_init_page_tables();
xtensa_init_paging(xtensa_kernel_ptables);
diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c
index 505ad00..fa58b9c 100644
--- a/arch/xtensa/core/vector_handlers.c
+++ b/arch/xtensa/core/vector_handlers.c
@@ -363,9 +363,13 @@
switch (cause) {
case EXCCAUSE_LEVEL1_INTERRUPT:
+#ifdef CONFIG_XTENSA_MMU
if (!is_dblexc) {
return xtensa_int1_c(interrupted_stack);
}
+#else
+ return xtensa_int1_c(interrupted_stack);
+#endif /* CONFIG_XTENSA_MMU */
break;
#ifndef CONFIG_USERSPACE
/* Syscalls are handled earlier in assembly if MMU is enabled.
diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h
index f06dff0..d5593d7 100644
--- a/arch/xtensa/include/xtensa_asm2_context.h
+++ b/arch/xtensa/include/xtensa_asm2_context.h
@@ -6,6 +6,10 @@
#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_
#define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_
+#if defined(__XT_CLANG__)
+#include <xtensa/xtensa-types.h>
+#endif
+
#include <xtensa/corebits.h>
#include <xtensa/config/core-isa.h>
#include <xtensa/config/tie.h>
diff --git a/boards/Kconfig b/boards/Kconfig
index 1359925..6eb9ca5 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -37,6 +37,8 @@
the Zephyr release that the board configuration will be removed.
When set, any build for that board will generate a clearly visible
deprecation warning.
+ When adding this to a BOARD, remember to follow the instructions in
+ https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated
config QEMU_TARGET
bool
diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts
index 2cca9b6..793a717 100644
--- a/boards/adi/apard32690/apard32690_max32690_m4.dts
+++ b/boards/adi/apard32690/apard32690_max32690_m4.dts
@@ -110,6 +110,28 @@
pinctrl-names = "default";
};
+&spi4a_miso_p1_2 {
+ power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi4a_mosi_p1_1 {
+ power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi4a_sck_p1_3 {
+ power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi4a_ss0_p1_0 {
+ power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+pmod_spi: &spi4 {
+ pinctrl-0 = <&spi4a_miso_p1_2 &spi4a_mosi_p1_1 &spi4a_sck_p1_3
+ &spi4a_ss0_p1_0>;
+ pinctrl-names = "default";
+};
+
&spi3a_miso_p0_20 {
power-source = <MAX32_VSEL_VDDIOH>;
};
diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml
index 28aea2c..3649ee4 100644
--- a/boards/adi/apard32690/apard32690_max32690_m4.yaml
+++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml
@@ -10,6 +10,7 @@
supported:
- arduino_serial
- arduino_spi
+ - pmod_spi
- gpio
- serial
- spi
diff --git a/boards/adi/max32655evkit/doc/index.rst b/boards/adi/max32655evkit/doc/index.rst
index db0d714..1e9bd85 100644
--- a/boards/adi/max32655evkit/doc/index.rst
+++ b/boards/adi/max32655evkit/doc/index.rst
@@ -95,6 +95,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
index ca78ea9..eea6c9e 100644
--- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
+++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
@@ -111,3 +111,9 @@
&wdt0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
index b863939..4bda583 100644
--- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
+++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 128
flash: 512
diff --git a/boards/adi/max32655fthr/doc/index.rst b/boards/adi/max32655fthr/doc/index.rst
index 7e05306..d101493 100644
--- a/boards/adi/max32655fthr/doc/index.rst
+++ b/boards/adi/max32655fthr/doc/index.rst
@@ -108,6 +108,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Push Buttons
************
diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
index 0632916..f5df5e5 100644
--- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
+++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
@@ -145,3 +145,9 @@
&wdt0 {
status = "okay";
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_mosi_p0_21 &spi1_miso_p0_22 &spi1_sck_p0_23 &spi1_ss0_p0_20>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
index 9bd8701..1b61f6a 100644
--- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
+++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 128
flash: 512
diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst
index c0b4b67..8ddef5d 100644
--- a/boards/adi/max32662evkit/doc/index.rst
+++ b/boards/adi/max32662evkit/doc/index.rst
@@ -101,7 +101,12 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
-
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
+| DMA | on-chip | dma controller |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts
index 08472da..e458a8d 100644
--- a/boards/adi/max32662evkit/max32662evkit.dts
+++ b/boards/adi/max32662evkit/max32662evkit.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32662-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/dma/max32662_dma.h>
/ {
model = "Analog Devices MAX32662EVKIT";
@@ -61,10 +62,20 @@
status = "okay";
};
+&dma0 {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1a_scl_p0_6 &i2c1a_sda_p0_9>;
+ pinctrl-names = "default";
+};
+
&trng {
status = "okay";
};
@@ -72,3 +83,9 @@
&wdt0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0a_copi_p0_3 &spi0a_cito_p0_2 &spi0a_sck_p0_4 &spi0a_ts0_p0_5>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml
index d9d589a..a15733c 100644
--- a/boards/adi/max32662evkit/max32662evkit.yaml
+++ b/boards/adi/max32662evkit/max32662evkit.yaml
@@ -8,9 +8,12 @@
- gnuarmemb
- xtools
supported:
+ - dma
- gpio
+ - i2c
- serial
- trng
- watchdog
+ - spi
ram: 80
flash: 256
diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst
index ff9f386..b6025de 100644
--- a/boards/adi/max32666evkit/doc/index.rst
+++ b/boards/adi/max32666evkit/doc/index.rst
@@ -114,6 +114,10 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| DMA | on-chip | dma controller |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
Connections and IOs
diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts
index 47f8cce..a87658d 100644
--- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts
+++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32666-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/dma/max32666_dma.h>
/ {
model = "Analog Devices MAX32666EVKIT";
@@ -73,6 +74,10 @@
status = "okay";
};
+&dma0 {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
@@ -81,6 +86,18 @@
status = "okay";
};
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_scl_p0_14 &i2c1_sda_p0_15>;
+ pinctrl-names = "default";
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_scl_p1_14 &i2c2_sda_p1_15>;
+ pinctrl-names = "default";
+};
+
&trng {
status = "okay";
};
diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
index 8ee86ca..d4301d8 100644
--- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
+++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
@@ -8,6 +8,8 @@
- gnuarmemb
- xtools
supported:
+ - dma
+ - i2c
- gpio
- serial
- trng
diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst
index 7455433..a2fb626 100644
--- a/boards/adi/max32666fthr/doc/index.rst
+++ b/boards/adi/max32666fthr/doc/index.rst
@@ -113,6 +113,12 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
+| DMA | on-chip | dma controller |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
index da88e72..95597c4 100644
--- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
+++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32666-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/dma/max32666_dma.h>
/ {
model = "Analog Devices MAX32666FTHR";
@@ -99,6 +100,10 @@
status = "okay";
};
+&dma0 {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
@@ -114,3 +119,9 @@
&wdt0 {
status = "okay";
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_mosi_p0_17 &spi1_miso_p0_18 &spi1_sck_p0_19 &spi1_ss0_p0_16>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
index c0eea77..282a6c9 100644
--- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
+++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
@@ -8,9 +8,12 @@
- gnuarmemb
- xtools
supported:
+ - dma
+ - i2c
- gpio
- serial
- trng
- watchdog
+ - spi
ram: 560
flash: 1024
diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst
index 614ab59..a27915d 100644
--- a/boards/adi/max32670evkit/doc/index.rst
+++ b/boards/adi/max32670evkit/doc/index.rst
@@ -114,6 +114,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32670evkit/max32670evkit.dts b/boards/adi/max32670evkit/max32670evkit.dts
index bc3d8f8..98c6076 100644
--- a/boards/adi/max32670evkit/max32670evkit.dts
+++ b/boards/adi/max32670evkit/max32670evkit.dts
@@ -90,3 +90,9 @@
&wdt0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0_mosi_p0_3 &spi0_miso_p0_2 &spi0_sck_p0_4 &spi0_ss0_p0_5>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32670evkit/max32670evkit.yaml b/boards/adi/max32670evkit/max32670evkit.yaml
index 619d727..d4b49d1 100644
--- a/boards/adi/max32670evkit/max32670evkit.yaml
+++ b/boards/adi/max32670evkit/max32670evkit.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 160
flash: 384
diff --git a/boards/adi/max32672evkit/Kconfig.defconfig b/boards/adi/max32672evkit/Kconfig.defconfig
new file mode 100644
index 0000000..cb74c02
--- /dev/null
+++ b/boards/adi/max32672evkit/Kconfig.defconfig
@@ -0,0 +1,29 @@
+# MAX32672EVKIT boards configuration
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MAX32672EVKIT
+
+if DISPLAY
+
+config MIPI_DBI_SPI_3WIRE
+ default y
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+ default 16
+
+choice LV_COLOR_DEPTH
+ default LV_COLOR_DEPTH_16 # 16 bit per pixel
+endchoice
+
+config LV_COLOR_16_SWAP
+ default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_MAX32672EVKIT
diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst
index f3b84ae..800511b 100644
--- a/boards/adi/max32672evkit/doc/index.rst
+++ b/boards/adi/max32672evkit/doc/index.rst
@@ -107,6 +107,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Connections and IOs
diff --git a/boards/adi/max32672evkit/max32672evkit.dts b/boards/adi/max32672evkit/max32672evkit.dts
index ee91dce..d1d97f7 100644
--- a/boards/adi/max32672evkit/max32672evkit.dts
+++ b/boards/adi/max32672evkit/max32672evkit.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32672-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
model = "Analog Devices MAX32672EVKIT";
@@ -20,6 +21,7 @@
zephyr,shell-uart = &uart0;
zephyr,sram = &sram3;
zephyr,flash = &flash0;
+ zephyr,display = &st7735;
};
leds {
@@ -50,6 +52,42 @@
sw0 = &pb1;
watchdog0 = &wdt0;
};
+
+ mipi_dbi {
+ compatible = "zephyr,mipi-dbi-spi";
+ /* Enable D/C line for 4wire mode */
+ /* dc-gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; */
+ spi-dev = <&spi0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ st7735: st7735@0 {
+ compatible = "sitronix,st7735r";
+ mipi-max-frequency = <DT_FREQ_M(6)>;
+ mipi-mode = <MIPI_DBI_MODE_SPI_3WIRE>;
+
+ reg = <0>;
+ width = <130>;
+ height = <132>;
+ x-offset = <0>;
+ y-offset = <0>;
+ madctl = <0xc0>;
+ colmod = <0x05>;
+ vmctr1 = <0x51>;
+ pwctr1 = [02 02];
+ pwctr2 = [c5];
+ pwctr3 = [0d 00];
+ pwctr4 = [8d 1a];
+ pwctr5 = [8d ee];
+ frmctr1 = [02 35 36];
+ frmctr2 = [02 35 36];
+ frmctr3 = [02 35 36 02 35 36];
+ gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
+ gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
+ };
+ };
};
&uart0 {
@@ -90,3 +128,24 @@
&wdt0 {
status = "okay";
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>;
+ pinctrl-names = "default";
+};
+
+&spi0a_mosi_p0_3 {
+ power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&spi0a_sck_p0_4 {
+ power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0a_mosi_p0_3 &spi0a_miso_p0_2 &spi0a_sck_p0_4>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
+};
diff --git a/boards/adi/max32672evkit/max32672evkit.yaml b/boards/adi/max32672evkit/max32672evkit.yaml
index 46237f2..ffe7191 100644
--- a/boards/adi/max32672evkit/max32672evkit.yaml
+++ b/boards/adi/max32672evkit/max32672evkit.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 200
flash: 1024
diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst
index 3d542b8..4ab52e3 100644
--- a/boards/adi/max32672fthr/doc/index.rst
+++ b/boards/adi/max32672fthr/doc/index.rst
@@ -109,6 +109,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Connections and IOs
diff --git a/boards/adi/max32672fthr/max32672fthr.dts b/boards/adi/max32672fthr/max32672fthr.dts
index 4c0eca3..b2287cf 100644
--- a/boards/adi/max32672fthr/max32672fthr.dts
+++ b/boards/adi/max32672fthr/max32672fthr.dts
@@ -142,3 +142,9 @@
&wdt0 {
status = "okay";
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32672fthr/max32672fthr.yaml b/boards/adi/max32672fthr/max32672fthr.yaml
index 50c89a8..03c9222 100644
--- a/boards/adi/max32672fthr/max32672fthr.yaml
+++ b/boards/adi/max32672fthr/max32672fthr.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 200
flash: 1024
diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst
index 1ed63d4..c4cb514 100644
--- a/boards/adi/max32675evkit/doc/index.rst
+++ b/boards/adi/max32675evkit/doc/index.rst
@@ -92,6 +92,12 @@
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
+| DMA | on-chip | dma controller |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32675evkit/max32675evkit.dts b/boards/adi/max32675evkit/max32675evkit.dts
index b3b5b9d..3c5bfcc 100644
--- a/boards/adi/max32675evkit/max32675evkit.dts
+++ b/boards/adi/max32675evkit/max32675evkit.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32675-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/dma/max32675_dma.h>
/ {
model = "Analog Devices MAX32675EVKIT";
@@ -72,6 +73,10 @@
status = "okay";
};
+&dma0 {
+ status = "okay";
+};
+
&gpio0 {
status = "okay";
};
@@ -80,6 +85,18 @@
status = "okay";
};
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2a_scl_p0_18 &i2c2a_sda_p0_19>;
+ pinctrl-names = "default";
+};
+
&trng {
status = "okay";
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml
index 3ec1641..b16eefc 100644
--- a/boards/adi/max32675evkit/max32675evkit.yaml
+++ b/boards/adi/max32675evkit/max32675evkit.yaml
@@ -8,8 +8,11 @@
- gnuarmemb
- xtools
supported:
+ - dma
- gpio
+ - i2c
- serial
- trng
+ - spi
ram: 160
flash: 384
diff --git a/boards/adi/max32680evkit/Kconfig.defconfig b/boards/adi/max32680evkit/Kconfig.defconfig
new file mode 100644
index 0000000..9970293
--- /dev/null
+++ b/boards/adi/max32680evkit/Kconfig.defconfig
@@ -0,0 +1,29 @@
+# MAX32680EVKIT boards configuration
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MAX32680EVKIT
+
+if DISPLAY
+
+config MIPI_DBI_SPI_3WIRE
+ default y
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+ default 16
+
+choice LV_COLOR_DEPTH
+ default LV_COLOR_DEPTH_16 # 16 bit per pixel
+endchoice
+
+config LV_COLOR_16_SWAP
+ default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_MAX32680EVKIT
diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst
index 20511e7..081be14 100644
--- a/boards/adi/max32680evkit/doc/index.rst
+++ b/boards/adi/max32680evkit/doc/index.rst
@@ -118,6 +118,8 @@
+-----------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
Connections and IOs
===================
diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
index b2e460b..3e42696 100644
--- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
+++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32680-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
model = "Analog Devices MAX32680EVKIT";
@@ -20,6 +21,7 @@
zephyr,shell-uart = &uart1;
zephyr,sram = &sram2;
zephyr,flash = &flash0;
+ zephyr,display = &st7735;
};
leds {
@@ -56,6 +58,42 @@
sw1 = &pb2;
watchdog0 = &wdt0;
};
+
+ mipi_dbi {
+ compatible = "zephyr,mipi-dbi-spi";
+ /* Enable D/C line for 4wire mode */
+ /* dc-gpios = <&gpio1 7 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; */
+ spi-dev = <&spi0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ st7735: st7735@0 {
+ compatible = "sitronix,st7735r";
+ mipi-max-frequency = <DT_FREQ_M(6)>;
+ mipi-mode = <MIPI_DBI_MODE_SPI_3WIRE>;
+
+ reg = <0>;
+ width = <130>;
+ height = <132>;
+ x-offset = <0>;
+ y-offset = <0>;
+ madctl = <0xc0>;
+ colmod = <0x05>;
+ vmctr1 = <0x51>;
+ pwctr1 = [02 02];
+ pwctr2 = [c5];
+ pwctr3 = [0d 00];
+ pwctr4 = [8d 1a];
+ pwctr5 = [8d ee];
+ frmctr1 = [02 35 36];
+ frmctr2 = [02 35 36];
+ frmctr3 = [02 35 36 02 35 36];
+ gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
+ gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
+ };
+ };
};
&uart1 {
@@ -106,3 +144,24 @@
&wdt0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7 &spi0a_ss0_p0_4>;
+ pinctrl-names = "default";
+};
+
+&spi0a_mosi_p0_5 {
+ power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&spi0a_sck_p0_7 {
+ power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
+};
diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
index 0c0ec5e..4b4d513 100644
--- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
+++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
@@ -14,5 +14,6 @@
- i2c
- dma
- watchdog
+ - spi
ram: 128
flash: 512
diff --git a/boards/adi/max32690evkit/Kconfig.defconfig b/boards/adi/max32690evkit/Kconfig.defconfig
new file mode 100644
index 0000000..342cc0c
--- /dev/null
+++ b/boards/adi/max32690evkit/Kconfig.defconfig
@@ -0,0 +1,29 @@
+# MAX32690EVKIT boards configuration
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MAX32690EVKIT
+
+if DISPLAY
+
+config MIPI_DBI_SPI_3WIRE
+ default y
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+ default 16
+
+choice LV_COLOR_DEPTH
+ default LV_COLOR_DEPTH_16 # 16 bit per pixel
+endchoice
+
+config LV_COLOR_16_SWAP
+ default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_MAX32690EVKIT
diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
index cc30a44..85b9d25 100644
--- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
+++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
@@ -10,6 +10,7 @@
#include <adi/max32/max32690-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
model = "Analog Devices MAX32690EVKIT";
@@ -20,6 +21,7 @@
zephyr,shell-uart = &uart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
+ zephyr,display = &st7735;
};
leds {
@@ -49,6 +51,50 @@
sw0 = &pb0;
watchdog0 = &wdt0;
};
+
+ mipi_dbi {
+ compatible = "zephyr,mipi-dbi-spi";
+ spi-dev = <&spibb0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ st7735: st7735@0 {
+ compatible = "sitronix,st7735r";
+ mipi-max-frequency = <DT_FREQ_M(6)>;
+ mipi-mode = <MIPI_DBI_MODE_SPI_3WIRE>;
+
+ reg = <0>;
+ width = <130>;
+ height = <132>;
+ x-offset = <0>;
+ y-offset = <0>;
+ madctl = <0xc0>;
+ colmod = <0x05>;
+ vmctr1 = <0x51>;
+ pwctr1 = [02 02];
+ pwctr2 = [c5];
+ pwctr3 = [0d 00];
+ pwctr4 = [8d 1a];
+ pwctr5 = [8d ee];
+ frmctr1 = [02 35 36];
+ frmctr2 = [02 35 36];
+ frmctr3 = [02 35 36 02 35 36];
+ gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
+ gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
+ };
+ };
+
+ spibb0: spibb0 {
+ compatible = "zephyr,spi-bitbang";
+ status="okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clk-gpios = <&gpio2 25 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+ mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+ cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+ };
};
&clk_ipo {
@@ -106,3 +152,9 @@
&wdt0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29 &spi0b_ss1_p2_26>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32690fthr/Kconfig.max32690fthr b/boards/adi/max32690fthr/Kconfig.max32690fthr
new file mode 100644
index 0000000..95bc3a9
--- /dev/null
+++ b/boards/adi/max32690fthr/Kconfig.max32690fthr
@@ -0,0 +1,7 @@
+# MAX32690 board configuration
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX32690FTHR
+ select SOC_MAX32690_M4 if BOARD_MAX32690FTHR_MAX32690_M4
diff --git a/boards/adi/max32690fthr/board.cmake b/boards/adi/max32690fthr/board.cmake
new file mode 100644
index 0000000..443c84c
--- /dev/null
+++ b/boards/adi/max32690fthr/board.cmake
@@ -0,0 +1,9 @@
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
+board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]")
+board_runner_args(jlink "--device=MAX32690" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32690fthr/board.yml b/boards/adi/max32690fthr/board.yml
new file mode 100644
index 0000000..328035b
--- /dev/null
+++ b/boards/adi/max32690fthr/board.yml
@@ -0,0 +1,8 @@
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+ name: max32690fthr
+ vendor: adi
+ socs:
+ - name: max32690
diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst
new file mode 100644
index 0000000..714adb8
--- /dev/null
+++ b/boards/adi/max32690fthr/doc/index.rst
@@ -0,0 +1,134 @@
+.. _max32690_fthr:
+
+MAX32690FTHR
+############
+
+Overview
+********
+
+The MAX32690FTHR is a rapid development platform to help engineers quickly
+implement ultra low-power wireless solutions using MAX32690 Arm© Cortex®-M4F
+and Bluetooth® 5.2 Low Energy (LE). The board also includes the MAX77654 PMIC
+for battery and power management. The form factor is a small 0.9in x 2.6in
+dual-row header footprint that is compatible with Adafruit Feather Wing
+peripheral expansion boards.
+
+Hardware
+********
+
+- MAX32690 MCU:
+
+ - Ultra-Efficient Microcontroller for Battery-Powered Applications
+
+ - 120MHz Arm Cortex-M4 Processor with FPU
+ - 7.3728MHz and 60MHz Low-Power Oscillators
+ - External Crystal Support (32MHz required for BLE)
+ - 32.768kHz RTC Clock (Requires External Crystal)
+ - 8kHz Always-On Ultra-Low Power Oscillator
+ - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON)
+ - 85 μW/MHz ACTIVE mode at 1.1V
+ - 1.8V and 3.3V I/O with No Level Translators
+ - External Flash & SRAM Expansion Interfaces
+
+ - Bluetooth 5.2 LE Radio
+
+ - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload
+ Timing-Critical Bluetooth Processing
+ - Fully Open-Source Bluetooth 5.2 Stack Available
+ - Supports AoA, AoD, LE Audio, and Mesh
+ - High-Throughput (2Mbps) Mode
+ - Long-Range (125kbps and 500kbps) Modes
+ - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm
+ - Single-Ended Antenna Connection (50Ω)
+
+ - Multiple Peripherals for System Control
+
+ - 16-Channel DMA
+ - Up To Five Quad SPI Master (60MHz)/Slave (48MHz)
+ - Up To Four 1Mbaud UARTs with Flow Control
+ - Up To Two 1MHz I2C Master/Slave
+ - I2S Master/Slave
+ - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor
+ - USB 2.0 Hi-Speed Device
+ - 16 Pulse Train Engines
+ - Up To Six 32-Bit Timers with 8mA High Drive
+ - Up To Two CAN 2.0 Controllers
+ - Up To Four Micro-Power Comparators
+ - 1-Wire Master
+
+ - Security and Integrity​
+
+ - ChipDNA Physically Un-clonable Function (PUF)
+ - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG)
+ - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256
+ - Secure Boot ROM
+
+Supported Features
+==================
+
+Below interfaces are supported by Zephyr on MAX32690FTHR.
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+-------------------------------------+
+| CLOCK | on-chip | clock and reset control |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++--------------------------------------------------------------+
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+The MAX32690 MCU can be flashed by connecting an external debug probe to the
+SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J4.
+Logic levels are fixed to VDDIO (1.8V).
+
+Once the debug probe is connected to your host computer, then you can run the
+``west flash`` command to write a firmware image into flash. Here is an example
+for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: max32690fthr/max32690/m4
+ :goals: flash
+
+.. note::
+
+ This board uses OpenOCD as the default debug interface. You can also use a
+ Segger J-Link with Segger's native tooling by overriding the runner,
+ appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+ be connected to the standard 2*5 pin debug connector (J4) using an
+ appropriate adapter board and cable.
+
+Debugging
+=========
+
+Once the debug probe is connected to your host computer, then you can run the
+``west debug`` command to write a firmware image into flash and start a debug
+session. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: max32690fthr/max32690/m4
+ :goals: debug
+
+References
+**********
+
+- `MAX32690 product page`_
+
+.. _MAX32690 product page:
+ https://www.analog.com/en/products/max32690.html
diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts
new file mode 100644
index 0000000..0ee5bb8
--- /dev/null
+++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32690.dtsi>
+#include <adi/max32/max32690-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "Analog Devices MAX32690FTHR";
+ compatible = "adi,max32690fthr";
+
+ chosen {
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red_led: led_0 {
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ label = "LED0";
+ };
+ green_led: led_1 {
+ gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ label = "LED1";
+ };
+ blue_led: led_2 {
+ gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+ label = "LED2";
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+ pb1: pb1 {
+ gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "SW3";
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ pb2: pb2 {
+ gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "SW4";
+ zephyr,code = <INPUT_KEY_1>;
+ };
+ };
+
+ aliases {
+ led0 = &red_led;
+ led1 = &green_led;
+ led2 = &blue_led;
+ sw0 = &pb1;
+ sw1 = &pb2;
+ };
+
+ feather_header: feather_connector {
+ compatible = "adafruit-feather-header";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <0 0 &gpio3 0 0>, /* A0 */
+ <1 0 &gpio3 1 0>, /* A1 */
+ <2 0 &gpio3 4 0>, /* A2 */
+ <3 0 &gpio0 9 0>, /* A3 */
+ <4 0 &gpio0 10 0>, /* A4 */
+ <5 0 &gpio0 7 0>, /* A5 */
+ <6 0 &gpio2 29 0>, /* SCK */
+ <7 0 &gpio2 28 0>, /* MOSI */
+ <8 0 &gpio2 27 0>, /* MISO */
+ <9 0 &gpio1 9 0>, /* RXD */
+ <10 0 &gpio1 10 0>, /* TXD */
+ /* 11 (D2) not connected */
+ <12 0 &gpio2 7 0>, /* SDA */
+ <13 0 &gpio2 8 0>, /* SCL */
+ <14 0 &gpio1 7 0>, /* D5 */
+ <15 0 &gpio1 8 0>, /* D6 */
+ <16 0 &gpio2 26 0>, /* D9 */
+ <17 0 &gpio0 23 0>, /* D10 */
+ <18 0 &gpio1 12 0>, /* D11 */
+ <19 0 &gpio1 11 0>, /* D12 */
+ <20 0 &gpio0 8 0>; /* D13 */
+ };
+};
+
+&clk_ibro {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&uart0 {
+ clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+ pinctrl-0 = <&uart0a_tx_p2_12 &uart0a_rx_p2_11>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ data-bits = <8>;
+ parity = "none";
+ status = "okay";
+};
+
+feather_serial: &uart2 {
+ clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+ pinctrl-0 = <&uart2a_tx_p1_10 &uart2a_rx_p1_9>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ data-bits = <8>;
+ parity = "none";
+ status = "okay";
+};
+
+feather_i2c: &i2c0 {
+ status = "okay";
+ pinctrl-0 = <&i2c0a_scl_p2_8 &i2c0a_sda_p2_7>;
+ pinctrl-names = "default";
+};
+
+feather_spi: &spi0 {
+ status = "okay";
+ pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29>;
+ pinctrl-names = "default";
+};
diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml
new file mode 100644
index 0000000..bbf1af6
--- /dev/null
+++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml
@@ -0,0 +1,19 @@
+identifier: max32690fthr/max32690/m4
+name: max32690fthr m4
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+supported:
+ - gpio
+ - serial
+ - i2c
+ - spi
+ - feather_serial
+ - feather_i2c
+ - feather_spi
+ram: 1024
+flash: 3072
diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig b/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig
new file mode 100644
index 0000000..4fa0a46
--- /dev/null
+++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4_defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
index 9158dcf..fcde064 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
@@ -96,6 +96,13 @@
};
};
+ adc0_default: adc0_default{
+ group1 {
+ pinmux = <ADCSE4_P32>, <ADCSE7_P35>;
+ drive-strength = "0.1";
+ };
+ };
+
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P22>,
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts
index 22f8b14..a47b97f 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb.dts
+++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts
@@ -151,6 +151,13 @@
status = "okay";
};
+&adc0 {
+ compatible = "ambiq,adc";
+ pinctrl-0 = <&adc0_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
&gpio0_31 {
status = "okay";
};
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.yaml b/boards/ambiq/apollo3_evb/apollo3_evb.yaml
index 18327a6..048f2ed 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb.yaml
+++ b/boards/ambiq/apollo3_evb/apollo3_evb.yaml
@@ -9,6 +9,7 @@
- gnuarmemb
supported:
- uart
+ - adc
- watchdog
- counter
- gpio
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
index 4c2ba97..67241cc 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
@@ -96,6 +96,13 @@
};
};
+ adc0_default: adc0_default{
+ group1 {
+ pinmux = <ADCSE4_P32>, <ADCSE7_P35>;
+ drive-strength = "0.1";
+ };
+ };
+
mspi0_default: mspi0_default{
group1 {
pinmux = <MSPI0_0_P22>,
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
index 6f09137..75d61cb 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
@@ -151,6 +151,13 @@
status = "okay";
};
+&adc0 {
+ compatible = "ambiq,adc";
+ pinctrl-0 = <&adc0_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
&gpio0_31 {
status = "okay";
};
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml
index 3a43a32..2a49061 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml
@@ -9,6 +9,7 @@
- gnuarmemb
supported:
- uart
+ - adc
- watchdog
- counter
- gpio
diff --git a/boards/beagle/beaglev_fire/doc/index.rst b/boards/beagle/beaglev_fire/doc/index.rst
index 8880814..23d63f4 100644
--- a/boards/beagle/beaglev_fire/doc/index.rst
+++ b/boards/beagle/beaglev_fire/doc/index.rst
@@ -57,7 +57,7 @@
.. code-block:: bash
- <softconsole_path>/openocd/bin/openocd --file \
+ <softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake
index 922e4aa..5238a02 100644
--- a/boards/deprecated.cmake
+++ b/boards/deprecated.cmake
@@ -1,12 +1,17 @@
# SPDX-License-Identifier: Apache-2.0
-# This file contains boards in Zephyr which has been replaced with a new board
+# This file contains boards in Zephyr which have been replaced with a new board
# name.
# This allows the system to automatically change the board while at the same
# time prints a warning to the user, that the board name is deprecated.
#
# To add a board rename, add a line in following format:
# set(<old_board_name>_DEPRECATED <new_board_name>)
+#
+# When adding board aliases here, remember to add a mention in the corresponding GitHub issue
+# tracking the removal of API/options
+# https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated,
+# so these aliases are eventually removed
set(96b_carbon_DEPRECATED
96b_carbon/stm32f401xe
diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
index 6eb8c2e..19f56f8 100644
--- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
+++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
@@ -17,6 +17,10 @@
zephyr,sram = &ram0;
};
+ aliases {
+ watchdog0 = &wdt0;
+ };
+
ram0: memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x10000000>;
@@ -36,6 +40,10 @@
status = "okay";
};
+&wdt0 {
+ status = "okay";
+};
+
&mdio0 {
status = "okay";
};
diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml
index 6d96923..b0dcc5b 100644
--- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml
+++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml
@@ -12,8 +12,12 @@
- zephyr
ram: 262144
supported:
+ - gpio
+ - uart
- spi
- i2s
+ - i2c
+ - watchdog
testing:
ignore_tags:
- bluetooth
diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig
index a704e9f..374b423 100644
--- a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig
+++ b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig
index 92553e3..c56c404 100644
--- a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig
+++ b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig
index 87bd018..75b0cc9 100644
--- a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig
+++ b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig
@@ -14,7 +14,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.defconfig b/boards/espressif/esp32c3_devkitc/Kconfig.defconfig
new file mode 100644
index 0000000..2e71f23
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# ESP32C3 devkitc board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+ int
+ default 65535 if WIFI && BT
+ default 51200 if WIFI
+ default 40960 if BT
+ default 4096
diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc b/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc
new file mode 100644
index 0000000..7e57441
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/Kconfig.esp32c3_devkitc
@@ -0,0 +1,7 @@
+# ESP32C3 devkitc board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ESP32C3_DEVKITC
+ select SOC_ESP32C3_WROOM_02_N4
diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild b/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild
new file mode 100644
index 0000000..8d3acb9
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+ default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+ default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/espressif/esp32c3_devkitc/board.cmake b/boards/espressif/esp32c3_devkitc/board.cmake
new file mode 100644
index 0000000..2f04d1f
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+ set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/espressif/esp32c3_devkitc/board.yml b/boards/espressif/esp32c3_devkitc/board.yml
new file mode 100644
index 0000000..22db88f
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: esp32c3_devkitc
+ vendor: espressif
+ socs:
+ - name: esp32c3
diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst
new file mode 100644
index 0000000..02c7d75
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/doc/index.rst
@@ -0,0 +1,244 @@
+.. _esp32c3_devkitc:
+
+ESP32-C3
+########
+
+Overview
+********
+
+ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC,
+based on the open-source RISC-V architecture. It strikes the right balance of power,
+I/O capabilities and security, thus offering the optimal cost-effective
+solution for connected devices.
+The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy,
+but it also facilitates a variety of use-cases based on dual connectivity. [1]_
+
+The features include the following:
+
+- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz
+- 400 KB of internal RAM
+- 802.11b/g/n/e/i
+- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh
+- Various peripherals:
+
+ - 12-bit ADC with up to 6 channels
+ - TWAI compatible with CAN bus 2.0
+ - Temperature sensor
+ - 3x SPI
+ - 1x I2S
+ - 1x I2C
+ - 2x UART
+ - LED PWM with up to 6 channels
+
+- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES)
+
+Supported Features
+==================
+
+Current Zephyr's ESP32-C3-Devkitc board supports the following features:
+
++------------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++============+============+=====================================+
+| UART | on-chip | serial port |
++------------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++------------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++------------+------------+-------------------------------------+
+| USB-JTAG | on-chip | hardware interface |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip | spi |
++------------+------------+-------------------------------------+
+| Timers | on-chip | counter |
++------------+------------+-------------------------------------+
+| Watchdog | on-chip | watchdog |
++------------+------------+-------------------------------------+
+| TRNG | on-chip | entropy |
++------------+------------+-------------------------------------+
+| LEDC | on-chip | pwm |
++------------+------------+-------------------------------------+
+| SPI DMA | on-chip | spi |
++------------+------------+-------------------------------------+
+| TWAI | on-chip | can |
++------------+------------+-------------------------------------+
+| USB-CDC | on-chip | serial |
++------------+------------+-------------------------------------+
+| ADC | on-chip | adc |
++------------+------------+-------------------------------------+
+| Wi-Fi | on-chip | |
++------------+------------+-------------------------------------+
+| Bluetooth | on-chip | |
++------------+------------+-------------------------------------+
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+ west blobs fetch hal_espressif
+
+.. note::
+
+ It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+ Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+ User can select the MCUboot bootloader by adding the following line
+ to the board default configuration file.
+
+ .. code:: cfg
+
+ CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+ :tool: west
+ :app: samples/hello_world
+ :board: esp32c3_devkitc
+ :goals: build
+ :west-args: --sysbuild
+ :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+ build/
+ ├── hello_world
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ ├── mcuboot
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ └── domains.yaml
+
+.. note::
+
+ With ``--sysbuild`` option the bootloader will be re-build and re-flash
+ every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be build one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+ Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_devkitc
+ :goals: build
+
+The usual ``flash`` target will work with the ``esp32c3_devkitc`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_devkitc
+ :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+ west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+ ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+ Hello World! esp32c3_devkitc
+
+Debugging
+*********
+
+As with much custom hardware, the ESP32-C3 modules require patches to
+OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
+the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
+``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
+parameter when building.
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_devkitc
+ :goals: build flash
+ :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
+
+You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_devkitc
+ :goals: debug
+
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
+
+References
+**********
+
+.. [1] https://www.espressif.com/en/products/socs/esp32-c3
+.. _ESP32C3 Devkitc User Guide: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02
+.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi
new file mode 100644
index 0000000..f6add95
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc-pinctrl.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
+
+&pinctrl {
+
+ uart0_default: uart0_default {
+ group1 {
+ pinmux = <UART0_TX_GPIO21>;
+ output-high;
+ };
+ group2 {
+ pinmux = <UART0_RX_GPIO20>;
+ bias-pull-up;
+ };
+ };
+
+ spim2_default: spim2_default {
+ group1 {
+ pinmux = <SPIM2_MISO_GPIO2>,
+ <SPIM2_SCLK_GPIO6>,
+ <SPIM2_CSEL_GPIO10>;
+ };
+ group2 {
+ pinmux = <SPIM2_MOSI_GPIO7>;
+ output-low;
+ };
+ };
+
+ i2c0_default: i2c0_default {
+ group1 {
+ pinmux = <I2C0_SDA_GPIO1>,
+ <I2C0_SCL_GPIO3>;
+ bias-pull-up;
+ drive-open-drain;
+ output-high;
+ };
+ };
+
+ twai_default: twai_default {
+ group1 {
+ pinmux = <TWAI_TX_GPIO4>,
+ <TWAI_RX_GPIO5>;
+ };
+ };
+};
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts
new file mode 100644
index 0000000..50803e3
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c3/esp32c3_wroom_n4.dtsi>
+#include "esp32c3_devkitc-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "Espressif ESP32C3-DevkitC";
+ compatible = "espressif,esp32c3";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,bt-hci = &esp32_bt_hci;
+ };
+
+ aliases {
+ sw0 = &user_button1;
+ i2c-0 = &i2c0;
+ watchdog0 = &wdt0;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button1: button_1 {
+ label = "User SW1";
+ gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-names = "default";
+};
+
+&usb_serial {
+ /* requires resoldering of resistors on the board */
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ pinctrl-0 = <&i2c0_default>;
+ pinctrl-names = "default";
+};
+
+&trng0 {
+ status = "okay";
+};
+
+&spi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-0 = <&spim2_default>;
+ pinctrl-names = "default";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&timer0 {
+ status = "disabled";
+};
+
+&timer1 {
+ status = "disabled";
+};
+
+&twai {
+ /* requires external CAN transceiver or jumper on RX and TX pins for loopback testing */
+ status = "disabled";
+ pinctrl-0 = <&twai_default>;
+ pinctrl-names = "default";
+};
+
+&flash0 {
+ status = "okay";
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Reserve 60kB for the bootloader */
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 0x0000F000>;
+ read-only;
+ };
+
+ /* Reserve 1024kB for the application in slot 0 */
+ slot0_partition: partition@10000 {
+ label = "image-0";
+ reg = <0x00010000 0x00100000>;
+ };
+
+ /* Reserve 1024kB for the application in slot 1 */
+ slot1_partition: partition@110000 {
+ label = "image-1";
+ reg = <0x00110000 0x00100000>;
+ };
+
+ /* Reserve 256kB for the scratch partition */
+ scratch_partition: partition@210000 {
+ label = "image-scratch";
+ reg = <0x00210000 0x00040000>;
+ };
+
+ storage_partition: partition@250000 {
+ label = "storage";
+ reg = <0x00250000 0x00006000>;
+ };
+ };
+};
+
+&esp32_bt_hci {
+ status = "okay";
+};
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml
new file mode 100644
index 0000000..876ee78
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml
@@ -0,0 +1,22 @@
+identifier: esp32c3_devkitc
+name: ESP32-C3
+type: mcu
+arch: riscv
+toolchain:
+ - zephyr
+supported:
+ - adc
+ - gpio
+ - i2c
+ - watchdog
+ - uart
+ - dma
+ - pwm
+ - spi
+ - counter
+ - entropy
+testing:
+ ignore_tags:
+ - net
+ - bluetooth
+vendor: espressif
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig
new file mode 100644
index 0000000..ef633ce
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/espressif/esp32c3_devkitc/support/openocd.cfg b/boards/espressif/esp32c3_devkitc/support/openocd.cfg
new file mode 100644
index 0000000..92a792f
--- /dev/null
+++ b/boards/espressif/esp32c3_devkitc/support/openocd.cfg
@@ -0,0 +1,11 @@
+set ESP_RTOS none
+
+# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+).
+# Uncomment the line below to enable USB debugging.
+# source [find interface/esp_usb_jtag.cfg]
+
+# Otherwise, use external JTAG programmer as ESP-Prog
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+
+source [find target/esp32c3.cfg]
+adapter speed 5000
diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig
index 9b39e76..cf5aeac 100644
--- a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig
+++ b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32c3_rust/Kconfig.defconfig b/boards/espressif/esp32c3_rust/Kconfig.defconfig
new file mode 100644
index 0000000..7741852
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+ int
+ default 65535 if WIFI && BT
+ default 51200 if WIFI
+ default 40960 if BT
+ default 4096
diff --git a/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust b/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust
new file mode 100644
index 0000000..1b5be57
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/Kconfig.esp32c3_rust
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ESP32C3_RUST
+ select SOC_ESP32C3_MINI_N4
diff --git a/boards/espressif/esp32c3_rust/Kconfig.sysbuild b/boards/espressif/esp32c3_rust/Kconfig.sysbuild
new file mode 100644
index 0000000..8d3acb9
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+ default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+ default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/espressif/esp32c3_rust/board.cmake b/boards/espressif/esp32c3_rust/board.cmake
new file mode 100644
index 0000000..91581df
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/board.cmake
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+ set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/espressif/esp32c3_rust/board.yml b/boards/espressif/esp32c3_rust/board.yml
new file mode 100644
index 0000000..36dd9b5
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/board.yml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+ name: esp32c3_rust
+ vendor: espressif
+ socs:
+ - name: esp32c3
diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst
new file mode 100644
index 0000000..32ba714
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/doc/index.rst
@@ -0,0 +1,289 @@
+.. _esp32c3_rust:
+
+ESP32-C3-DevKit-RUST-1
+######################
+
+Overview
+********
+
+This board is based on the ESP32-C3 [1]_ and includes sensors, LEDs, buttons, a battery charger, and USB type-C connector.
+
+SoC Features:
+
+- IEEE 802.11 b/g/n-compliant
+- Bluetooth 5, Bluetooth mesh
+- 32-bit RISC-V single-core processor, up to 160MHz
+- 384 KB ROM
+- 400 KB SRAM (16 KB for cache)
+- 8 KB SRAM in RTC
+- 22 x programmable GPIOs
+- 3 x SPI
+- 2 x UART
+- 1 x I2C
+- 1 x I2S
+- 2 x 54-bit general-purpose timers
+- 3 x watchdog timers
+- 1 x 52-bit system timer
+- Remote Control Peripheral (RMT)
+- LED PWM controller (LEDC)
+- Full-speed USB Serial/JTAG controller
+- General DMA controller (GDMA)
+- 1 x TWAI®
+- 2 x 12-bit SAR ADCs, up to 6 channels
+- 1 x temperature sensor
+
+Supported Features
+==================
+
+Current Zephyr's ESP32-C3-DevKit-RUST-1 board supports the following features:
+
++------------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++============+============+=====================================+
+| UART | on-chip | serial port |
++------------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++------------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++------------+------------+-------------------------------------+
+| USB-JTAG | on-chip | hardware interface |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip | spi |
++------------+------------+-------------------------------------+
+| Timers | on-chip | counter |
++------------+------------+-------------------------------------+
+| Watchdog | on-chip | watchdog |
++------------+------------+-------------------------------------+
+| TRNG | on-chip | entropy |
++------------+------------+-------------------------------------+
+| LEDC | on-chip | pwm |
++------------+------------+-------------------------------------+
+| SPI DMA | on-chip | spi |
++------------+------------+-------------------------------------+
+| TWAI | on-chip | can |
++------------+------------+-------------------------------------+
+| USB-CDC | on-chip | serial |
++------------+------------+-------------------------------------+
+| ADC | on-chip | adc |
++------------+------------+-------------------------------------+
+| Wi-Fi | on-chip | |
++------------+------------+-------------------------------------+
+| Bluetooth | on-chip | |
++------------+------------+-------------------------------------+
+
+I2C Peripherals
+===============
+
+This board includes the following peripherals over the I2C bus:
+
++---------------------------+--------------+---------+
+| Peripheral | Part number | Address |
++===========================+==============+=========+
+| IMU | ICM-42670-P | 0x68 |
++---------------------------+--------------+---------+
+| Temperature and Humidity | SHTC3 | 0x70 |
++---------------------------+--------------+---------+
+
+I2C Bus Connection
+==================
+
++---------+--------+
+| Signal | GPIO |
++=========+========+
+| SDA | GPIO10 |
++---------+--------+
+| SCL | GPIO8 |
++---------+--------+
+
+I/Os
+====
+
+The following devices are connected through GPIO:
+
++--------------+--------+
+| I/O Devices | GPIO |
++==============+========+
+| WS2812 LED | GPIO2 |
++--------------+--------+
+| LED | GPIO7 |
++--------------+--------+
+| Button/Boot | GPIO9 |
++--------------+--------+
+
+Power
+=====
+
+* USB type-C (*no PD compatibility*).
+* Li-Ion battery charger.
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+ west blobs fetch hal_espressif
+
+.. note::
+
+ It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+ Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+ User can select the MCUboot bootloader by adding the following line
+ to the board default configuration file.
+
+ .. code:: cfg
+
+ CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+ :tool: west
+ :app: samples/hello_world
+ :board: esp32c3_rust
+ :goals: build
+ :west-args: --sysbuild
+ :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+ build/
+ ├── hello_world
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ ├── mcuboot
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ └── domains.yaml
+
+.. note::
+
+ With ``--sysbuild`` option the bootloader will be re-build and re-flash
+ every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be build one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+ Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_rust
+ :goals: build
+
+The usual ``flash`` target will work with the ``esp32c3_rust`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_rust
+ :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+ west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+ ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+ Hello World! esp32c3_rust
+
+Debugging
+*********
+
+As with much custom hardware, the ESP32-C3 modules require patches to
+OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
+the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
+``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
+parameter when building.
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_rust
+ :goals: build flash
+ :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
+
+You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp32c3_rust
+ :goals: debug
+
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
+
+References
+**********
+
+.. [1] https://www.espressif.com/en/products/socs/esp32-c3
+.. _ESP32-C3-DevKit-RUST-1: https://github.com/esp-rs/esp-rust-board/tree/v1.2
+.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi b/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi
new file mode 100644
index 0000000..b1e14c2
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust-pinctrl.dtsi
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
+
+&pinctrl {
+
+ uart0_default: uart0_default {
+ group1 {
+ pinmux = <UART0_TX_GPIO21>;
+ output-high;
+ };
+ group2 {
+ pinmux = <UART0_RX_GPIO20>;
+ bias-pull-up;
+ };
+ };
+
+ spim2_default: spim2_default {
+ group1 {
+ pinmux = <SPIM2_MISO_GPIO5>,
+ <SPIM2_SCLK_GPIO6>,
+ <SPIM2_CSEL_GPIO9>;
+ };
+ group2 {
+ pinmux = <SPIM2_MOSI_GPIO2>;
+ output-low;
+ };
+ };
+
+ i2c0_default: i2c0_default {
+ group1 {
+ pinmux = <I2C0_SDA_GPIO10>,
+ <I2C0_SCL_GPIO8>;
+ bias-pull-up;
+ drive-open-drain;
+ output-high;
+ };
+ };
+};
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.dts b/boards/espressif/esp32c3_rust/esp32c3_rust.dts
new file mode 100644
index 0000000..553d821
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c3/esp32c3_mini_n4.dtsi>
+#include "esp32c3_rust-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/led/led.h>
+
+/ {
+ model = "Espressif ESP32C3-RUST";
+ compatible = "espressif,esp32c3_rust";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,console = &usb_serial;
+ zephyr,shell-uart = &usb_serial;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_partition;
+ };
+
+ aliases {
+ led0 = &red_led_0;
+ sw0 = &user_button1;
+ i2c-0 = &i2c0;
+ watchdog0 = &wdt0;
+ led-strip = &led_strip;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button1: button_1 {
+ label = "User SW1";
+ gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red_led_0: led_0 {
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ label = "User LD0";
+ };
+ };
+
+};
+
+&spi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-0 = <&spim2_default>;
+ pinctrl-names = "default";
+
+ /* Workaround to support WS2812 driver */
+ line-idle-low;
+ status = "okay";
+
+ led_strip: ws2812@0 {
+ compatible = "worldsemi,ws2812-spi";
+
+ /* SPI */
+ reg = <0>; /* ignored, but necessary for SPI bindings */
+ spi-max-frequency = <6400000>;
+
+ /* WS2812 */
+ chain-length = <1>; /* arbitrary; change at will */
+ spi-cpha;
+ spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */
+ spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */
+ color-mapping = <LED_COLOR_ID_GREEN
+ LED_COLOR_ID_RED
+ LED_COLOR_ID_BLUE>;
+ };
+};
+
+&usb_serial {
+ status = "okay";
+};
+
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ pinctrl-0 = <&i2c0_default>;
+ pinctrl-names = "default";
+
+ icm42670@68 {
+ compatible = "invensense,icm42670";
+ reg = <0x68>;
+ status = "okay";
+ accel-hz = <800>;
+ accel-fs = <16>;
+ gyro-hz = <800>;
+ gyro-fs = <2000>;
+ };
+
+ shtc3@70 {
+ compatible = "sensirion,shtc3", "sensirion,shtcx";
+ reg = <0x70>;
+ measure-mode = "normal";
+ clock-stretching;
+ };
+};
+
+&trng0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "disabled";
+};
+
+&flash0 {
+ status = "okay";
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Reserve 60kB for the bootloader */
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 0x0000F000>;
+ read-only;
+ };
+
+ /* Reserve 1024kB for the application in slot 0 */
+ slot0_partition: partition@10000 {
+ label = "image-0";
+ reg = <0x00010000 0x00100000>;
+ };
+
+ /* Reserve 1024kB for the application in slot 1 */
+ slot1_partition: partition@110000 {
+ label = "image-1";
+ reg = <0x00110000 0x00100000>;
+ };
+
+ /* Reserve 256kB for the scratch partition */
+ scratch_partition: partition@210000 {
+ label = "image-scratch";
+ reg = <0x00210000 0x00040000>;
+ };
+
+ storage_partition: partition@250000 {
+ label = "storage";
+ reg = <0x00250000 0x00006000>;
+ };
+ };
+};
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.yaml b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml
new file mode 100644
index 0000000..fedd017
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: esp32c3_rust
+name: ESP32-C3-DevKit-RUST-1
+type: mcu
+arch: riscv
+toolchain:
+ - zephyr
+supported:
+ - adc
+ - gpio
+ - i2c
+ - watchdog
+ - uart
+ - dma
+ - pwm
+ - spi
+ - counter
+ - entropy
+testing:
+ ignore_tags:
+ - net
+ - bluetooth
+vendor: espressif
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig
new file mode 100644
index 0000000..a0483fa
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_I2C=y
+CONFIG_LED_STRIP=y
+CONFIG_SENSOR=y
diff --git a/boards/espressif/esp32c3_rust/support/openocd.cfg b/boards/espressif/esp32c3_rust/support/openocd.cfg
new file mode 100644
index 0000000..e846c96
--- /dev/null
+++ b/boards/espressif/esp32c3_rust/support/openocd.cfg
@@ -0,0 +1,11 @@
+set ESP_RTOS none
+
+# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+).
+# Uncomment the line below to enable USB debugging.
+source [find interface/esp_usb_jtag.cfg]
+
+# Otherwise, use external JTAG programmer as ESP-Prog
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+
+source [find target/esp32c3.cfg]
+adapter speed 5000
diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.defconfig b/boards/espressif/esp32c6_devkitc/Kconfig.defconfig
index f14ec8f..fccfb36 100644
--- a/boards/espressif/esp32c6_devkitc/Kconfig.defconfig
+++ b/boards/espressif/esp32c6_devkitc/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml
index 392116d..0e0b2e7 100644
--- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml
@@ -15,5 +15,4 @@
ignore_tags:
- net
- bluetooth
- - pm
- tracing
diff --git a/boards/espressif/esp32s3_devkitc/Kconfig.defconfig b/boards/espressif/esp32s3_devkitc/Kconfig.defconfig
index 266a4ed..d539cd6 100644
--- a/boards/espressif/esp32s3_devkitc/Kconfig.defconfig
+++ b/boards/espressif/esp32s3_devkitc/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig
index 69f8b4d..2633959 100644
--- a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig
+++ b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/espressif/esp8684_devkitm/Kconfig.defconfig b/boards/espressif/esp8684_devkitm/Kconfig.defconfig
new file mode 100644
index 0000000..60266dd
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# ESP8684 devkitm board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+ int
+ default 65535 if WIFI && BT
+ default 51200 if WIFI
+ default 40960 if BT
+ default 4096
diff --git a/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm b/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm
new file mode 100644
index 0000000..5dddf33
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/Kconfig.esp8684_devkitm
@@ -0,0 +1,7 @@
+# ESP8684 devkitm board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ESP8684_DEVKITM
+ select SOC_ESP8684_MINI_H4
diff --git a/boards/espressif/esp8684_devkitm/Kconfig.sysbuild b/boards/espressif/esp8684_devkitm/Kconfig.sysbuild
new file mode 100644
index 0000000..8d3acb9
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+ default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+ default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/espressif/esp8684_devkitm/board.cmake b/boards/espressif/esp8684_devkitm/board.cmake
new file mode 100644
index 0000000..2f04d1f
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+ set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/espressif/esp8684_devkitm/board.yml b/boards/espressif/esp8684_devkitm/board.yml
new file mode 100644
index 0000000..5173f52
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: esp8684_devkitm
+ vendor: espressif
+ socs:
+ - name: esp32c2
diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst
new file mode 100644
index 0000000..4b68552
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/doc/index.rst
@@ -0,0 +1,235 @@
+.. _esp8684_devkitm:
+
+ESP32-C2
+########
+
+Overview
+********
+
+ESP32-C2 (ESP8684 core) is a low-cost, Wi-Fi 4 & Bluetooth 5 (LE) chip. Its unique design
+makes the chip smaller and yet more powerful than ESP8266. ESP32-C2 is built around a RISC-V
+32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM.
+ESP32-C2 has been designed to target simple, high-volume, and low-data-rate IoT applications,
+such as smart plugs and smart light bulbs. ESP32-C2 offers easy and robust wireless connectivity,
+which makes it the go-to solution for developing simple, user-friendly and reliable
+smart-home devices [1]_.
+
+Features include the following (`ESP8684 Datasheet`_):
+
+- 32-bit core RISC-V microcontroller with a maximum clock speed of 120 MHz
+- 2 MB or 4 MB in chip (ESP8684) or in package (ESP32-C2) flash
+- 272 KB of internal RAM
+- 802.11b/g/n
+- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh
+- Various peripherals:
+
+ - 14 programmable GPIOs
+ - 3 SPI
+ - 2 UART
+ - 1 I2C Master
+ - LED PWM controller, with up to 6 channels
+ - General DMA controller (GDMA)
+ - 1 12-bit SAR ADC, up to 5 channels
+ - 1 temperature sensor
+ - 1 54-bit general-purpose timer
+ - 2 watchdog timers
+ - 1 52-bit system timer
+
+- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES)
+
+For detailed information check `ESP8684 Technical Reference Manual`_.
+
+Supported Features
+==================
+
+Current Zephyr's ESP8684-Devkitm board supports the following features:
+
++------------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++============+============+=====================================+
+| UART | on-chip | serial port |
++------------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++------------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++------------+------------+-------------------------------------+
+| Watchdog | on-chip | watchdog |
++------------+------------+-------------------------------------+
+| TRNG | on-chip | entropy |
++------------+------------+-------------------------------------+
+| Timers | on-chip | counter |
++------------+------------+-------------------------------------+
+
+For a getting started user guide, please check `ESP8684 Devkitm User Guide`_.
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+ west blobs fetch hal_espressif
+
+.. note::
+
+ It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+ Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+ User can select the MCUboot bootloader by adding the following line
+ to the board default configuration file.
+
+ .. code:: cfg
+
+ CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+ :tool: west
+ :app: samples/hello_world
+ :board: esp8684_devkitm
+ :goals: build
+ :west-args: --sysbuild
+ :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+ build/
+ ├── hello_world
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ ├── mcuboot
+ │ └── zephyr
+ │ ├── zephyr.elf
+ │ └── zephyr.bin
+ └── domains.yaml
+
+.. note::
+
+ With ``--sysbuild`` option the bootloader will be re-build and re-flash
+ every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be build one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+ Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp8684_devkitm
+ :goals: build
+
+The usual ``flash`` target will work with the ``esp8684_devkitm`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp8684_devkitm
+ :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+ west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+ ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+ Hello World! esp8684_devkitm
+
+Debugging
+*********
+
+As with much custom hardware, the ESP8684 modules require patches to
+OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
+the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
+``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
+parameter when building.
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp8684_devkitm
+ :goals: build flash
+ :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
+
+You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: esp8684_devkitm
+ :goals: debug
+
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
+
+References
+**********
+
+.. [1] https://www.espressif.com/en/products/socs/esp8684
+.. _ESP8684 Devkitm User Guide: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp8684/esp8684-devkitm-1/user_guide.html
+.. _ESP8684 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf
+.. _ESP8684 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi b/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi
new file mode 100644
index 0000000..dda91ad
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm-pinctrl.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c2-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h>
+
+&pinctrl {
+
+ uart0_default: uart0_default {
+ group1 {
+ pinmux = <UART0_TX_GPIO20>;
+ output-high;
+ };
+ group2 {
+ pinmux = <UART0_RX_GPIO19>;
+ bias-pull-up;
+ };
+ };
+};
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts
new file mode 100644
index 0000000..e5f82c7
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c2/esp8684_mini_h4.dtsi>
+#include "esp8684_devkitm-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "Espressif ESP8684-DevkitM";
+ compatible = "espressif,esp32c2";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_partition;
+ };
+
+ aliases {
+ sw0 = &user_button1;
+ watchdog0 = &wdt0;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button1: button_1 {
+ label = "User SW1";
+ gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ current-speed = <74880>;
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-names = "default";
+};
+
+&trng0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&timer0 {
+ status = "disabled";
+};
+
+&flash0 {
+ status = "okay";
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Reserve 60kB for the bootloader */
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 0x0000F000>;
+ read-only;
+ };
+
+ /* Reserve 1024kB for the application in slot 0 */
+ slot0_partition: partition@10000 {
+ label = "image-0";
+ reg = <0x00010000 0x00100000>;
+ };
+
+ /* Reserve 1024kB for the application in slot 1 */
+ slot1_partition: partition@110000 {
+ label = "image-1";
+ reg = <0x00110000 0x00100000>;
+ };
+
+ /* Reserve 256kB for the scratch partition */
+ scratch_partition: partition@210000 {
+ label = "image-scratch";
+ reg = <0x00210000 0x00040000>;
+ };
+
+ storage_partition: partition@250000 {
+ label = "storage";
+ reg = <0x00250000 0x00006000>;
+ };
+ };
+};
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml
new file mode 100644
index 0000000..a8b6eaa
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml
@@ -0,0 +1,17 @@
+identifier: esp8684_devkitm
+name: ESP8684
+type: mcu
+arch: riscv
+toolchain:
+ - zephyr
+supported:
+ - gpio
+ - watchdog
+ - uart
+ - counter
+ - entropy
+testing:
+ ignore_tags:
+ - net
+ - bluetooth
+vendor: espressif
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig
new file mode 100644
index 0000000..ef633ce
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/espressif/esp8684_devkitm/support/openocd.cfg b/boards/espressif/esp8684_devkitm/support/openocd.cfg
new file mode 100644
index 0000000..9320970
--- /dev/null
+++ b/boards/espressif/esp8684_devkitm/support/openocd.cfg
@@ -0,0 +1,5 @@
+set ESP_RTOS none
+
+# Use external JTAG interface, such as ESP-Prog
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+source [find target/esp32c2.cfg]
diff --git a/boards/espressif/esp_wrover_kit/Kconfig.defconfig b/boards/espressif/esp_wrover_kit/Kconfig.defconfig
index 3cbb535..adf8cd7 100644
--- a/boards/espressif/esp_wrover_kit/Kconfig.defconfig
+++ b/boards/espressif/esp_wrover_kit/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/ezurio/bl5340_dvk/Kconfig.defconfig b/boards/ezurio/bl5340_dvk/Kconfig.defconfig
index ece5d8d..d90d051 100644
--- a/boards/ezurio/bl5340_dvk/Kconfig.defconfig
+++ b/boards/ezurio/bl5340_dvk/Kconfig.defconfig
@@ -99,12 +99,6 @@
endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
-config IPM_NRFX
- default IPM
-
-config MBOX_NRFX_IPC
- default MBOX
-
if BOARD_BL5340_DVK_NRF5340_CPUNET
# BT_CTLR depends on BT. When BT is enabled we should default to also
diff --git a/boards/hardkernel/odroid_go/Kconfig.defconfig b/boards/hardkernel/odroid_go/Kconfig.defconfig
index 5c9710a..121f6e6 100644
--- a/boards/hardkernel/odroid_go/Kconfig.defconfig
+++ b/boards/hardkernel/odroid_go/Kconfig.defconfig
@@ -20,7 +20,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig
index e1531cb..a297949 100644
--- a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig
+++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig
index 2efc7d1..c1aa6f0 100644
--- a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig
+++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig
@@ -8,7 +8,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig
index 865f2d0..4d4613b 100644
--- a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig
+++ b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/lilygo/ttgo_lora32/Kconfig.defconfig b/boards/lilygo/ttgo_lora32/Kconfig.defconfig
index 64e75a5..d77a95c 100644
--- a/boards/lilygo/ttgo_lora32/Kconfig.defconfig
+++ b/boards/lilygo/ttgo_lora32/Kconfig.defconfig
@@ -10,7 +10,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.defconfig b/boards/lilygo/ttgo_t8c3/Kconfig.defconfig
index 13e40a1..eb2f107 100644
--- a/boards/lilygo/ttgo_t8c3/Kconfig.defconfig
+++ b/boards/lilygo/ttgo_t8c3/Kconfig.defconfig
@@ -3,7 +3,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig
index 62d1871..f6ad1ad 100644
--- a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig
+++ b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig
index f79ddb5..a14482e 100644
--- a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig
+++ b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig
index beb26dc..2b223f5 100644
--- a/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig
index 25ab101..f3b5917 100644
--- a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig
@@ -9,7 +9,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig
index c2f1681..f0f262c 100644
--- a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig
@@ -6,7 +6,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig
index 84827d2..fd9614d 100644
--- a/boards/m5stack/m5stack_core2/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 65536 if BT
default 4096
diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig
index 3616814..903059d 100644
--- a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig
@@ -6,7 +6,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig
index b103f44..a6b9572 100644
--- a/boards/m5stack/m5stickc_plus/Kconfig.defconfig
+++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/m5stack/stamp_c3/Kconfig.defconfig b/boards/m5stack/stamp_c3/Kconfig.defconfig
index 7984df0..dcc3a42 100644
--- a/boards/m5stack/stamp_c3/Kconfig.defconfig
+++ b/boards/m5stack/stamp_c3/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/microchip/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst
index 203745d..10ab696 100644
--- a/boards/microchip/mpfs_icicle/doc/index.rst
+++ b/boards/microchip/mpfs_icicle/doc/index.rst
@@ -45,7 +45,7 @@
.. code-block:: bash
sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
- <softconsole_path>/openocd/bin/openocd --file \
+ <softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
diff --git a/boards/native/doc/Port_vs_QEMU_vs.svg b/boards/native/doc/Port_vs_QEMU_vs.svg
index 923b0df..20f8abb 100644
--- a/boards/native/doc/Port_vs_QEMU_vs.svg
+++ b/boards/native/doc/Port_vs_QEMU_vs.svg
@@ -365,19 +365,19 @@
<text x="6.39" y="301.76" class="st17" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>QEMU</text> </g>
<g id="shape88-174" v:mID="88" v:groupContext="shape" transform="translate(646.299,-127.559)">
<title>Sheet.88</title>
- <desc>native_ posix</desc>
+ <desc>native _sim</desc>
<v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
<v:textRect cx="32.3082" cy="291.969" width="64.62" height="28.3465"/>
<rect x="0" y="277.795" width="64.6164" height="28.3465" class="st3"/>
- <text x="16.19" y="288.97" class="st9" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native_<v:lf/><tspan
- x="20.64" dy="1.2em" class="st6">posix</tspan></text> </g>
+ <text x="16.19" y="288.97" class="st9" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native<v:lf/><tspan
+ x="20.64" dy="1.2em" class="st6">_sim</tspan></text> </g>
<g id="shape89-178" v:mID="89" v:groupContext="shape" transform="translate(302.18,-259.795)">
<title>Sheet.89</title>
- <desc>native_posix</desc>
+ <desc>native_sim</desc>
<v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
<v:textRect cx="32.3082" cy="291.969" width="64.62" height="28.3465"/>
<rect x="0" y="277.795" width="64.6164" height="28.3465" class="st3"/>
- <text x="4.51" y="294.97" class="st9" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native_posix</text> </g>
+ <text x="4.51" y="294.97" class="st9" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native_sim</text> </g>
<g id="shape90-181" v:mID="90" v:groupContext="shape" transform="translate(287.819,-267.874)">
<title>Sheet.90</title>
<v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst
index 09edd47..36fd1b0 100644
--- a/boards/native/doc/arch_soc.rst
+++ b/boards/native/doc/arch_soc.rst
@@ -33,9 +33,9 @@
Types of POSIX arch based boards
================================
-Today there are two types of POSIX boards: The native boards, :ref:`native_posix<native_posix>`
-and :ref:`native_sim<native_sim>`, and the :ref:`bsim boards<bsim boards>`.
-While they share the main objectives and principles, the first are intended as
+Today there are two types of POSIX boards:
+:ref:`native_sim<native_sim>`, and the :ref:`bsim boards<bsim boards>`.
+While they share the main objectives and principles, the first is intended as
a HW agnostic test platform which in some cases utilizes the host OS
peripherals, while the second intend to simulate a particular HW platform,
with focus on their radio (e.g. BT LE) and utilize the `BabbleSim`_ physical layer
diff --git a/boards/native/doc/layering.svg b/boards/native/doc/layering.svg
index c85357d..5467719 100644
--- a/boards/native/doc/layering.svg
+++ b/boards/native/doc/layering.svg
@@ -129,11 +129,11 @@
x="42.81" dy="1.2em" class="st4">layering</tspan></text> </g>
<g id="shape14-47" v:mID="14" v:groupContext="shape" transform="translate(244.319,-226.677)">
<title>Sheet.14</title>
- <desc>native_posix/sim & _bsim boards Zephyr layering</desc>
+ <desc>native_sim & _bsim boards Zephyr layering</desc>
<v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
<v:textRect cx="92.126" cy="250.866" width="184.26" height="28.3465"/>
<rect x="0" y="236.693" width="184.252" height="28.3465" class="st7"/>
- <text x="42.05" y="238.27" class="st8" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native_posix/sim <v:newlineChar/><tspan
+ <text x="60.05" y="238.27" class="st8" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>native_sim <v:newlineChar/><tspan
x="43.49" dy="1.2em" class="st4">& _bsim boards <v:lf/></tspan><tspan x="43.88" dy="1.2em" class="st4">Zephyr layering</tspan></text> </g>
</g>
</svg>
diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig
index 70d597b..2d89606 100644
--- a/boards/native/native_posix/Kconfig.defconfig
+++ b/boards/native/native_posix/Kconfig.defconfig
@@ -3,6 +3,9 @@
if BOARD_NATIVE_POSIX
+config BOARD_DEPRECATED_RELEASE
+ default "v4.2.0"
+
config BUILD_OUTPUT_BIN
default n
diff --git a/boards/native/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst
index 950f681..ea53463 100644
--- a/boards/native/native_posix/doc/index.rst
+++ b/boards/native/native_posix/doc/index.rst
@@ -11,6 +11,15 @@
Overview
********
+.. warning::
+ ``native_posix`` is deprecated in favour of :ref:`native_sim<native_sim>`, and will be removed
+ in the 4.2 release.
+
+.. note::
+ For native_posix users, if needed, :ref:`native_sim<native_sim>` includes a compatibility mode
+ :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT`,
+ which will set its configuration to mimic a native_posix-like configuration.
+
``native_posix`` is the predecessor of :ref:`native_sim<native_sim>`.
Just like with :ref:`native_sim<native_sim>` you can build your Zephyr application
with the Zephyr kernel, creating a normal Linux executable with your host tooling,
@@ -19,15 +28,6 @@
But unlike with :ref:`native_sim<native_sim>` you are limited to only using the host C library.
:ref:`native_sim<native_sim>` supports all ``native_posix`` use cases.
-.. note::
-
- | If you are a new user, you are encouraged to use :ref:`native_sim<native_sim>` directly.
- | If you have been using native_posix you are recommended to start using
- :ref:`native_sim<native_sim>` instead.
- | If needed, :ref:`native_sim<native_sim>` includes a compatibility mode
- :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT`,
- which will set its configuration to mimic a native_posix's like configuration.
-
This board does not intend to simulate any particular HW, but it provides
a few peripherals such as an Ethernet driver, display, UART, etc., to enable
developing and testing application code which would require them.
diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts
index 073d5fe..1f1b11a 100644
--- a/boards/native/native_sim/native_sim.dts
+++ b/boards/native/native_sim/native_sim.dts
@@ -114,6 +114,7 @@
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
+ #forward-cells = <1>;
reg = <0x100 4>;
};
diff --git a/boards/native/nrf_bsim/Kconfig.defconfig b/boards/native/nrf_bsim/Kconfig.defconfig
index 2ff1780..629372e 100644
--- a/boards/native/nrf_bsim/Kconfig.defconfig
+++ b/boards/native/nrf_bsim/Kconfig.defconfig
@@ -48,13 +48,6 @@
default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP
default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET
-if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET
-
-config MBOX_NRFX_IPC
- default MBOX
-
-endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET
-
if BOARD_NRF5340BSIM_NRF5340_CPUAPP
config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET
diff --git a/boards/native/nrf_bsim/common/cmdline.h b/boards/native/nrf_bsim/common/cmdline.h
index ec65800..004d620 100644
--- a/boards/native/nrf_bsim/common/cmdline.h
+++ b/boards/native/nrf_bsim/common/cmdline.h
@@ -5,20 +5,20 @@
*/
/**
- * This header exists solely to allow drivers meant for the native_posix board
- * to be used directly in the nrf52_bsim board.
+ * This header exists solely to allow drivers meant for the native_sim board
+ * to be used directly in the nrf5*_bsim boards.
* Note that such reuse should be done with great care.
*
- * The command line arguments parsing logic from native_posix was born as a copy
+ * The command line arguments parsing logic from native_sim was born as a copy
* of the one from the BabbleSim's libUtil library
* They are therefore mostly equal except for types and functions names.
*
- * This header converts these so the native_posix call to dynamically register
- * command line arguments is passed to the nrf52_bsim one
+ * This header converts these so the native_sim call to dynamically register
+ * command line arguments is passed to the nrf*_bsim one
*/
-#ifndef BOARDS_POSIX_NRF52_BSIM_CMDLINE_H
-#define BOARDS_POSIX_NRF52_BSIM_CMDLINE_H
+#ifndef BOARDS_POSIX_NRF_BSIM_CMDLINE_H
+#define BOARDS_POSIX_NRF_BSIM_CMDLINE_H
#include "../../native_posix/cmdline_common.h"
@@ -36,4 +36,4 @@
}
#endif
-#endif /* BOARDS_POSIX_NRF52_BSIM_CMDLINE_H */
+#endif /* BOARDS_POSIX_NRF_BSIM_CMDLINE_H */
diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig
index 62316a2..f8315be 100644
--- a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig
+++ b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig
@@ -62,12 +62,6 @@
endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS
-config IPM_NRFX
- default IPM
-
-config MBOX_NRFX_IPC
- default MBOX
-
if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET
config BT_CTLR
diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig
index 972d843..1c10b3e 100644
--- a/boards/nordic/nrf5340dk/Kconfig.defconfig
+++ b/boards/nordic/nrf5340dk/Kconfig.defconfig
@@ -53,13 +53,6 @@
endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS
-endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS
-
-config MBOX_NRFX_IPC
- default MBOX
-
-if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS
-
config BT_HCI_IPC
default y if BT
diff --git a/boards/nordic/nrf54l15pdk/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake
index 0eea21c..4a6a86a 100644
--- a/boards/nordic/nrf54l15pdk/board.cmake
+++ b/boards/nordic/nrf54l15pdk/board.cmake
@@ -7,6 +7,6 @@
board_runner_args(jlink "--speed=4000")
endif()
-include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml
index 9213c49..4b90073 100644
--- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml
+++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml
@@ -18,6 +18,7 @@
- gpio
- i2c
- pwm
+ - retained_mem
- spi
- watchdog
- i2s
diff --git a/boards/nordic/nrf7002dk/CMakeLists.txt b/boards/nordic/nrf7002dk/CMakeLists.txt
new file mode 100644
index 0000000..db20255
--- /dev/null
+++ b/boards/nordic/nrf7002dk/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if((CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS) AND
+ CONFIG_BOARD_ENABLE_CPUNET)
+ zephyr_library()
+ zephyr_library_sources(nrf5340_cpunet_reset.c)
+endif()
diff --git a/boards/nordic/nrf7002dk/Kconfig b/boards/nordic/nrf7002dk/Kconfig
new file mode 100644
index 0000000..4bd8461
--- /dev/null
+++ b/boards/nordic/nrf7002dk/Kconfig
@@ -0,0 +1,71 @@
+# nRF5340 DK board configuration
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config IPM_NRFX
+ default IPM
+
+config MBOX_NRFX_IPC
+ default MBOX
+
+if BOARD_NRF7002DK_NRF5340_CPUAPP || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
+
+config BT_HCI_IPC
+ default y if BT
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+ int
+ default 4096 if BT_HCI_IPC
+
+config BOARD_ENABLE_CPUNET
+ bool "nRF53 Network MCU"
+ select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \
+ $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
+ help
+ This option enables releasing the Network 'force off' signal, which
+ as a consequence will power up the Network MCU during system boot.
+ Additionally, the option allocates GPIO pins that will be used by UARTE
+ of the Network MCU.
+ Note: GPIO pin allocation can only be configured by the secure Application
+ MCU firmware, so when this option is used with the non-secure version of
+ the board, the application needs to take into consideration, that the
+ secure firmware image must already have configured GPIO allocation for the
+ Network MCU.
+ default y if (BT || NRF_802154_SER_HOST)
+
+config DOMAIN_CPUNET_BOARD
+ string
+ default "nrf7002dk/nrf5340/cpunet"
+ depends on BOARD_ENABLE_CPUNET
+ help
+ The board which will be used for CPUNET domain when creating a multi
+ image application where one or more images should be located on
+ another board. For example hci_ipc on the nRF5340_cpunet for
+ Bluetooth applications.
+
+endif
+
+if BOARD_NRF7002DK_NRF5340_CPUNET
+
+config BT_CTLR
+ default y if BT
+
+config BT_ECC
+ default y if BT
+
+config DOMAIN_CPUAPP_BOARD
+ string
+ default "nrf7002dk/nrf5340/cpuapp" if BOARD_NRF7002DK_NRF5340_CPUAPP
+ default "nrf7002dk/nrf5340/cpuapp/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NS
+ default "nrf7002dk/nrf5340/cpuapp/nrf7001" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001
+ default "nrf7002dk/nrf5340/cpuapp/nrf7001/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
+ help
+ The board which will be used for CPUAPP domain when creating a multi
+ image application where one or more images should be located on
+ another board.
+
+endif
diff --git a/boards/nordic/nrf7002dk/Kconfig.defconfig b/boards/nordic/nrf7002dk/Kconfig.defconfig
new file mode 100644
index 0000000..a6357ae
--- /dev/null
+++ b/boards/nordic/nrf7002dk/Kconfig.defconfig
@@ -0,0 +1,76 @@
+# nRF5340 DK nRF5340 board configuration
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF7002DK_NRF5340_CPUAPP || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
+
+# By default, if we build for a Non-Secure version of the board,
+# force building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+ default y if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
+
+if BUILD_WITH_TFM
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+ bool
+ default y
+
+endif # BUILD_WITH_TFM
+
+# Code Partition:
+#
+# For the secure version of the board the firmware is linked at the beginning
+# of the flash, or into the code-partition defined in DT if it is intended to
+# be loaded by MCUboot. If the secure firmware is to be combined with a non-
+# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
+# be restricted to the size of its code partition.
+#
+# For the non-secure version of the board, the firmware
+# must be linked into the code-partition (non-secure) defined in DT, regardless.
+# Apply this configuration below by setting the Kconfig symbols used by
+# the linker according to the information extracted from DT partitions.
+
+# SRAM Partition:
+#
+# If the secure firmware is to be combined with a non-secure image
+# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
+# be restricted to the secure image SRAM partition (sram-secure-partition).
+# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
+# may be used by the image.
+#
+# For the non-secure version of the board, the firmware image SRAM is
+# always restricted to the allocated non-secure SRAM partition.
+#
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if (BOARD_NRF7002DK_NRF5340_CPUAPP || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001) && \
+ TRUSTED_EXECUTION_SECURE
+
+config FLASH_LOAD_SIZE
+ default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config SRAM_SIZE
+ default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
+
+endif
+
+if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
+
+config FLASH_LOAD_OFFSET
+ default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+ default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+endif
+
+endif
diff --git a/boards/nordic/nrf7002dk/Kconfig.nrf7002dk b/boards/nordic/nrf7002dk/Kconfig.nrf7002dk
new file mode 100644
index 0000000..91f52ee
--- /dev/null
+++ b/boards/nordic/nrf7002dk/Kconfig.nrf7002dk
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF7002DK
+ select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF7002DK_NRF5340_CPUNET
+ select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF7002DK_NRF5340_CPUAPP || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
+ BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
diff --git a/boards/nordic/nrf7002dk/board.cmake b/boards/nordic/nrf7002dk/board.cmake
new file mode 100644
index 0000000..bea0dc9
--- /dev/null
+++ b/boards/nordic/nrf7002dk/board.cmake
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS)
+ set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR
+ CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS)
+ board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+ set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
+endif()
+
+if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUNET)
+ board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nordic/nrf7002dk/board.yml b/boards/nordic/nrf7002dk/board.yml
new file mode 100644
index 0000000..ca94d73
--- /dev/null
+++ b/boards/nordic/nrf7002dk/board.yml
@@ -0,0 +1,12 @@
+board:
+ name: nrf7002dk
+ vendor: nordic
+ socs:
+ - name: nrf5340
+ variants:
+ - name: ns
+ cpucluster: cpuapp
+ - name: nrf7001
+ cpucluster: cpuapp
+ variants:
+ - name: ns
diff --git a/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg b/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg
new file mode 100644
index 0000000..51d5572
--- /dev/null
+++ b/boards/nordic/nrf7002dk/doc/img/nrf7002dk.jpg
Binary files differ
diff --git a/boards/nordic/nrf7002dk/doc/index.rst b/boards/nordic/nrf7002dk/doc/index.rst
new file mode 100644
index 0000000..5b25a7a
--- /dev/null
+++ b/boards/nordic/nrf7002dk/doc/index.rst
@@ -0,0 +1,341 @@
+.. _nrf7002dk_nrf5340:
+
+nRF7002 DK
+##########
+
+Overview
+********
+
+The nRF7002 DK (PCA10143) is a single-board development kit for evaluation and development on
+the nRF7002, a Wi-Fi companion IC to Nordic Semiconductor's nRF5340 System-on-Chip (SoC) host
+processor. It is certified for the Wi-Fi Alliance® `Wi-Fi Certification program`_ in the
+Connectivity, Security, and Optimization categories. See `UG Wi-Fi certification`_ for detailed
+information.
+
+The nRF7002 is an IEEE 802.11ax (Wi-Fi 6) compliant solution that implements the Wi-Fi physical
+layer and Medium Access Control (MAC) layer protocols. It implements the nRF Wi-Fi driver
+software on the nRF5340 host processor communicating over the QSPI bus.
+
+The nRF5340 host is a dual-core SoC based on the Arm® Cortex®-M33 architecture.
+It has the following features:
+
+* A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension,
+ running at up to 128 MHz, referred to as the application core.
+* A secondary Arm Cortex-M33 core, with a reduced feature set, running at a fixed 64 MHz,
+ referred to as the network core.
+
+The ``nrf7002dk/nrf5340/cpuapp`` board target provides support for the application core on the
+nRF5340 SoC. The ``nrf7002dk/nrf5340/cpunet`` board target provides support for the network
+core on the nRF5340 SoC.
+
+.. figure:: img/nrf7002dk.jpg
+ :align: center
+ :alt: nRF7002 DK
+
+ nRF7002 DK (Credit: Nordic Semiconductor)
+
+More information about the board can be found at the
+`nRF7002 DK website`_.
+The `nRF7002 DK Product Specification`_
+contains the processor's information and the datasheet.
+
+Hardware
+========
+
+* nRF7002 DK:
+ The nRF7002 DK has two external oscillators.
+
+ * The frequency of the slow clock is 32.768 kHz.
+ * The frequency of the main clock is 32 MHz.
+
+* Micro-USB 2.0 cable
+
+Supported features
+------------------
+
+The ``nrf7002dk/nrf5340/cpuapp`` board configuration supports the following hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| ADC | on-chip | adc |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock_control |
++-----------+------------+----------------------+
+| FLASH | on-chip | flash |
++-----------+------------+----------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| I2C(M) | on-chip | i2c |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| PWM | on-chip | pwm |
++-----------+------------+----------------------+
+| RTC | on-chip | system clock |
++-----------+------------+----------------------+
+| RTT | Segger | console |
++-----------+------------+----------------------+
+| RADIO | nrf7002 | Wi-Fi 6 (802.11ax) |
++-----------+------------+----------------------+
+| QSPI | on-chip | qspi |
++-----------+------------+----------------------+
+| SPI(M/S) | on-chip | spi |
++-----------+------------+----------------------+
+| SPU | on-chip | system protection |
++-----------+------------+----------------------+
+| UARTE | on-chip | serial |
++-----------+------------+----------------------+
+| USB | on-chip | usb |
++-----------+------------+----------------------+
+| WDT | on-chip | watchdog |
++-----------+------------+----------------------+
+
+The ``nrf7002dk/nrf5340/cpunet`` board configuration supports the following hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| CLOCK | on-chip | clock_control |
++-----------+------------+----------------------+
+| FLASH | on-chip | flash |
++-----------+------------+----------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| I2C(M) | on-chip | i2c |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| RADIO | on-chip | Bluetooth, |
+| | | ieee802154 |
++-----------+------------+----------------------+
+| RTC | on-chip | system clock |
++-----------+------------+----------------------+
+| RTT | Segger | console |
++-----------+------------+----------------------+
+| SPI(M/S) | on-chip | spi |
++-----------+------------+----------------------+
+| UARTE | on-chip | serial |
++-----------+------------+----------------------+
+| WDT | on-chip | watchdog |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+See `nRF7002 DK Product Specification`_
+for a complete list of nRF7002 DK board hardware features.
+
+Connections and IOs
+-------------------
+
+The connections and IOs supported by the development kit are listed in this section.
+
+LED
+^^^
+
+* **LED 1** (green) = **P1.06**
+* **LED 2** (green) = **P1.07**
+
+Push buttons
+^^^^^^^^^^^^
+
+* **Button 1** = **SW1** = **P1.08**
+* **Button 2** = **SW2** = **P1.09**
+* **BOOT** = **SW5** = boot/reset
+
+Wi-Fi control
+^^^^^^^^^^^^^
+
+* BUCKEN = **P0.12**
+* IOVDD CONTROL = **P0.31**
+* HOST IRQ = **P0.23**
+* COEX_REQ = **P0.28**
+* COEX_STATUS0 = **P0.30**
+* COEX_STATUS1 = **P0.29**
+* COEX_GRANT = **P0.24**
+
+Security components
+-------------------
+
+The following security components are available:
+
+* Implementation Defined Attribution Unit (`IDAU`_) on the application core.
+
+ The IDAU is implemented with the System Protection Unit and is used to define
+ secure and non-secure memory maps. By default, the entire memory space
+ (Flash, SRAM, and peripheral address space) is defined to be secure-accessible only.
+
+* Secure boot.
+
+Programming and Debugging
+*************************
+
+The nRF5340 application core supports the Armv8-M Security Extension.
+Applications built for the ``nrf7002dk/nrf5340/cpuapp`` board boot by default in the
+secure state.
+
+The nRF5340 network core does not support the Armv8-M Security Extension.
+nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure
+attribute set. This allows to build and run secure-only applications on the nRF5340 SoC.
+
+Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
+=============================================================================
+
+Applications on the nRF5340 may contain a Secure and a Non-Secure firmware
+image for the application core. The Secure image can be built using either
+Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware
+images are always built using Zephyr. The two alternatives are described below.
+
+.. note::
+
+ By default, SPE for the nRF5340 application core is built using TF-M.
+
+Building the Secure firmware with TF-M
+--------------------------------------
+
+The process to build the Secure firmware image using TF-M and the Non-Secure
+firmware image using Zephyr requires the following steps:
+
+1. Build the Non-Secure Zephyr application
+ for the application core using ``-DBOARD=nrf7002dk/nrf5340/cpuapp/ns``.
+ To invoke the building of TF-M the Zephyr build system requires the
+ Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by
+ default when building Zephyr as a Non-Secure application.
+ The Zephyr build system will perform the following steps automatically:
+
+ * Build the Non-Secure firmware image as a regular Zephyr application
+ * Build a TF-M (secure) firmware image
+ * Merge the output image binaries together
+ * Optionally build a bootloader image (MCUboot)
+
+.. note::
+
+ Depending on the TF-M configuration, an application DTS overlay may be
+ required, to adjust the Non-Secure image Flash and SRAM starting address
+ and sizes.
+
+2. Build the application firmware for the network core using
+ ``-DBOARD=nrf7002dk/nrf5340/cpunet``.
+
+Building the Secure firmware using Zephyr
+-----------------------------------------
+
+The process to build the Secure and the Non-Secure firmware images
+using Zephyr requires the following steps:
+
+1. Build the Secure Zephyr application for the application core
+ using ``-DBOARD=nrf7002dk/nrf5340/cpuapp`` and
+ ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n``
+ in the application project configuration file.
+2. Build the Non-Secure Zephyr application for the application core
+ using ``-DBOARD=nrf7002dk/nrf5340/cpuapp/ns``.
+3. Merge the two binaries together.
+4. Build the application firmware for the network core using
+ ``-DBOARD=nrf7002dk/nrf5340/cpunet``.
+
+When building a Secure/Non-Secure application for the nRF5340 application core,
+the Secure application will have to set the IDAU (SPU) configuration to allow
+Non-Secure access to all CPU resources utilized by the Non-Secure application
+firmware. SPU configuration shall take place before jumping to the Non-Secure
+application.
+
+Building a Secure only application
+==================================
+
+Build the Zephyr app in the usual way (see :ref:`build_an_application`
+and :ref:`application_run`), using ``-DBOARD=nrf7002dk/nrf5340/cpuapp`` for
+the firmware running on the nRF5340 application core, and using
+``-DBOARD=nrf7002dk/nrf5340/cpunet`` for the firmware running
+on the nRF5340 network core.
+
+Flashing
+========
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`. Then you can build and flash
+applications as usual (:ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. warning::
+
+ The nRF5340 has a flash read-back protection feature. When flash read-back
+ protection is active, you will need to recover the chip before reflashing.
+ If you are flashing with :ref:`west <west-build-flash-debug>`, run
+ this command for more details on the related ``--recover`` option:
+
+ .. code-block:: console
+
+ west flash -H -r nrfjprog --skip-rebuild
+
+.. note::
+
+ Flashing and debugging applications on the nRF5340 DK requires
+ upgrading the nRF Command Line Tools to version 10.12.0. Further
+ information on how to install the nRF Command Line Tools can be
+ found in :ref:`nordic_segger_flashing`.
+
+Here is an example for the :ref:`hello_world` application running on the
+nRF5340 application core.
+
+First, run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+ $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the board nRF7002 DK
+can be found. For example, under Linux, :code:`/dev/ttyACM0`.
+
+Then build and flash the application in the usual way.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: nrf7002dk/nrf5340/cpuapp
+ :goals: build flash
+
+Debugging
+=========
+
+Refer to the :ref:`nordic_segger` page to learn about debugging Nordic
+boards with a Segger IC.
+
+Next steps
+**********
+
+You have now completed getting started with the nRF7002 DK.
+See the following links for where to go next:
+
+* `Installation`_ and `Configuring and Building`_ documentation to install the
+ nRF Connect SDK and learn more about its development environment.
+* `Developing with nRF70`_ documentation for more advanced topics related to the nRF70 Series.
+* `Wi-Fi`_ documentation for information related to Wi-Fi protocol and Wi-Fi modes of operation.
+
+References
+**********
+
+.. target-notes::
+
+.. _Wi-Fi Certification program:
+ https://www.wi-fi.org/certification
+.. _UG Wi-Fi certification:
+ https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/wifi_certification.html#ug-wifi-certification
+.. _IDAU:
+ https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
+.. _nRF7002 DK website:
+ https://www.nordicsemi.com/Products/Development-hardware/nrf7002-dk
+.. _nRF7002 DK Product Specification:
+ https://docs.nordicsemi.com/bundle/ps_nrf5340/page/keyfeatures_html5.html
+.. _Trusted Firmware M:
+ https://www.trustedfirmware.org/projects/tf-m/
+.. _Installation:
+ https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/installation.html#installation
+.. _Configuring and Building:
+ https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/config_and_build/index.html#configuration-and-build
+.. _Developing with nRF70:
+ https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf70/index.html#ug-nrf70-developing
+.. _Wi-Fi:
+ https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/index.html#ug-wifi
diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi
new file mode 100644
index 0000000..c571d4b
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "nrf5340_cpuapp_common_pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ chosen {
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ zephyr,uart-mcumgr = &uart0;
+ zephyr,bt-mon-uart = &uart0;
+ zephyr,bt-c2h-uart = &uart0;
+ zephyr,bt-hci = &bt_hci_ipc0;
+ nordic,802154-spinel-ipc = &ipc0;
+ zephyr,ieee802154 = &ieee802154;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0: led_0 {
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 0";
+ };
+ led1: led_1 {
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 1";
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+ pwm_led0: pwm_led_0 {
+ pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+ button0: button_0 {
+ gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 1";
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ button1: button_1 {
+ gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 2";
+ zephyr,code = <INPUT_KEY_1>;
+ };
+ };
+
+ arduino_header: connector {
+ compatible = "arduino-header-r3";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <0 0 &gpio0 4 0>, /* A0 */
+ <1 0 &gpio0 5 0>, /* A1 */
+ <2 0 &gpio0 6 0>, /* A2 */
+ <3 0 &gpio0 7 0>, /* A3 */
+ <4 0 &gpio0 25 0>, /* A4 */
+ <5 0 &gpio0 26 0>, /* A5 */
+ <6 0 &gpio1 0 0>, /* D0 */
+ <7 0 &gpio1 1 0>, /* D1 */
+ <8 0 &gpio1 4 0>, /* D2 */
+ <9 0 &gpio1 5 0>, /* D3 */
+ <10 0 &gpio1 6 0>, /* D4 */
+ <11 0 &gpio1 7 0>, /* D5 */
+ <12 0 &gpio1 8 0>, /* D6 */
+ <13 0 &gpio1 9 0>, /* D7 */
+ <14 0 &gpio1 10 0>, /* D8 */
+ <15 0 &gpio1 11 0>, /* D9 */
+ <16 0 &gpio1 12 0>, /* D10 */
+ <17 0 &gpio1 13 0>, /* D11 */
+ <18 0 &gpio1 14 0>, /* D12 */
+ <19 0 &gpio1 15 0>, /* D13 */
+ <20 0 &gpio1 2 0>, /* D14 */
+ <21 0 &gpio1 3 0>; /* D15 */
+ };
+
+ arduino_adc: analog-connector {
+ compatible = "arduino,uno-adc";
+ #io-channel-cells = <1>;
+ io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */
+ <1 &adc 1>, /* A1 = P0.5 = AIN1 */
+ <2 &adc 2>, /* A2 = P0.6 = AIN2 */
+ <3 &adc 3>, /* A3 = P0.7 = AIN3 */
+ <4 &adc 4>, /* A4 = P0.25 = AIN4 */
+ <5 &adc 5>; /* A5 = P0.26 = AIN5 */
+ };
+
+ gpio_fwd: nrf-gpio-forwarder {
+ compatible = "nordic,nrf-gpio-forwarder";
+ status = "okay";
+ uart {
+ gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>;
+ };
+ };
+
+ /* These aliases are provided for compatibility with samples */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ pwm-led0 = &pwm_led0;
+ sw0 = &button0;
+ sw1 = &button1;
+ bootloader-led0 = &led0;
+ mcuboot-button0 = &button0;
+ mcuboot-led0 = &led0;
+ watchdog0 = &wdt0;
+ };
+};
+
+&vregmain {
+ regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&vregradio {
+ regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&vregh {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
+
+&gpiote {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+arduino_i2c: &i2c1 {
+ compatible = "nordic,nrf-twim";
+ status = "okay";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&uart0 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-1 = <&uart0_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&pwm0 {
+ status = "okay";
+ pinctrl-0 = <&pwm0_default>;
+ pinctrl-1 = <&pwm0_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&spi4 {
+ compatible = "nordic,nrf-spim";
+ status = "okay";
+ pinctrl-0 = <&spi4_default>;
+ pinctrl-1 = <&spi4_sleep>;
+ pinctrl-names = "default", "sleep";
+ cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ mx25r64: mx25r6435f@0 {
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ reg = <0>;
+ spi-max-frequency = <33000000>;
+ jedec-id = [c2 28 17];
+ sfdp-bfp = [
+ e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
+ ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
+ 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
+ 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
+ ];
+ size = <67108864>;
+ has-dpd;
+ t-enter-dpd = <10000>;
+ t-exit-dpd = <5000>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-0 = <&qspi_default>;
+ pinctrl-1 = <&qspi_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+arduino_serial: &uart1 {
+ compatible = "nordic,nrf-uarte";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart1_default>;
+ pinctrl-1 = <&uart1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+arduino_spi: &spi3 {
+ compatible = "nordic,nrf-spim";
+ cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
+ pinctrl-0 = <&spi3_default>;
+ pinctrl-1 = <&spi3_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&flash0 {
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 0x00010000>;
+ };
+ slot0_partition: partition@10000 {
+ label = "image-0";
+ };
+ slot0_ns_partition: partition@50000 {
+ label = "image-0-nonsecure";
+ };
+ slot1_partition: partition@80000 {
+ label = "image-1";
+ };
+ slot1_ns_partition: partition@c0000 {
+ label = "image-1-nonsecure";
+ };
+ /* 0xf0000 to 0xf7fff reserved for TF-M partitions */
+ storage_partition: partition@f8000 {
+ label = "storage";
+ reg = <0x000f8000 0x00008000>;
+ };
+ };
+};
+
+&ieee802154 {
+ status = "okay";
+};
+
+zephyr_udc0: &usbd {
+ compatible = "nordic,nrf-usbd";
+ status = "okay";
+};
+
+/ {
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram0_image: image@20000000 {
+ /* Zephyr image(s) memory */
+ };
+
+ sram0_s: image_s@20000000 {
+ /* Secure image memory */
+ };
+
+ sram0_ns: image_ns@20040000 {
+ /* Non-Secure image memory */
+ };
+ };
+};
+
+/* Include partition configuration file */
+#include "nrf5340_cpuapp_common_partition_conf.dts"
diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_partition_conf.dts b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_partition_conf.dts
new file mode 100644
index 0000000..b4fa353
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_partition_conf.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Default Flash planning for nrf7002dk_nrf5340 CPUAPP (Application MCU).
+ *
+ * Zephyr build for nRF5340 with ARM TrustZone-M support,
+ * implies building Secure and Non-Secure Zephyr images.
+ *
+ * Secure image will be placed, by default, in flash0
+ * (or in slot0, if MCUboot is present).
+ * Secure image will use sram0 for system memory.
+ *
+ * Non-Secure image will be placed in slot0_ns, and use
+ * sram0_ns for system memory.
+ *
+ * Note that the Secure image only requires knowledge of
+ * the beginning of the Non-Secure image (not its size).
+ */
+
+&slot0_partition {
+ reg = <0x00010000 0x40000>;
+};
+
+&slot0_ns_partition {
+ reg = <0x00050000 0x30000>;
+};
+
+&slot1_partition {
+ reg = <0x00080000 0x40000>;
+};
+
+&slot1_ns_partition {
+ reg = <0x000c0000 0x30000>;
+};
+
+/* Default SRAM planning when building for nRF5340 with
+ * ARM TrustZone-M support
+ * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
+ * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
+ * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
+ * (see nrf5340_shared_sram_planning_conf.dts)
+ */
+&sram0_image {
+ reg = <0x20000000 DT_SIZE_K(448)>;
+};
+
+&sram0_s {
+ reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&sram0_ns {
+ reg = <0x20040000 DT_SIZE_K(192)>;
+};
+
+/* Include shared RAM configuration file */
+#include "nrf5340_shared_sram_planning_conf.dts"
diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi
new file mode 100644
index 0000000..f04075f
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi
@@ -0,0 +1,126 @@
+&pinctrl {
+ i2c1_default: i2c1_default {
+ group1 {
+ psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+ <NRF_PSEL(TWIM_SCL, 1, 3)>;
+ };
+ };
+
+ i2c1_sleep: i2c1_sleep {
+ group1 {
+ psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+ <NRF_PSEL(TWIM_SCL, 1, 3)>;
+ low-power-enable;
+ };
+ };
+
+ uart0_default: uart0_default {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 0, 20)>,
+ <NRF_PSEL(UART_RTS, 0, 19)>;
+ };
+ group2 {
+ psels = <NRF_PSEL(UART_RX, 0, 22)>,
+ <NRF_PSEL(UART_CTS, 0, 21)>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_sleep: uart0_sleep {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 0, 20)>,
+ <NRF_PSEL(UART_RX, 0, 22)>,
+ <NRF_PSEL(UART_RTS, 0, 19)>,
+ <NRF_PSEL(UART_CTS, 0, 21)>;
+ low-power-enable;
+ };
+ };
+
+ pwm0_default: pwm0_default {
+ group1 {
+ psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
+ };
+ };
+
+ pwm0_sleep: pwm0_sleep {
+ group1 {
+ psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
+ low-power-enable;
+ };
+ };
+
+ qspi_default: qspi_default {
+ group1 {
+ psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+ <NRF_PSEL(QSPI_IO0, 0, 13)>,
+ <NRF_PSEL(QSPI_IO1, 0, 14)>,
+ <NRF_PSEL(QSPI_IO2, 0, 15)>,
+ <NRF_PSEL(QSPI_IO3, 0, 16)>,
+ <NRF_PSEL(QSPI_CSN, 0, 18)>;
+ };
+ };
+
+ qspi_sleep: qspi_sleep {
+ group1 {
+ psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+ <NRF_PSEL(QSPI_IO0, 0, 13)>,
+ <NRF_PSEL(QSPI_IO1, 0, 14)>,
+ <NRF_PSEL(QSPI_IO2, 0, 15)>,
+ <NRF_PSEL(QSPI_IO3, 0, 16)>,
+ <NRF_PSEL(QSPI_CSN, 0, 18)>;
+ low-power-enable;
+ };
+ };
+
+ uart1_default: uart1_default {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 1, 1)>;
+ };
+ group2 {
+ psels = <NRF_PSEL(UART_RX, 1, 0)>;
+ bias-pull-up;
+ };
+ };
+
+ uart1_sleep: uart1_sleep {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 1, 1)>,
+ <NRF_PSEL(UART_RX, 1, 0)>;
+ low-power-enable;
+ };
+ };
+
+ spi3_default: spi3_default {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ };
+ };
+
+ spi3_sleep: spi3_sleep {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ low-power-enable;
+ };
+ };
+
+ spi4_default: spi4_default {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+ <NRF_PSEL(SPIM_MISO, 0, 10)>,
+ <NRF_PSEL(SPIM_MOSI, 0, 9)>;
+ };
+ };
+
+ spi4_sleep: spi4_sleep {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+ <NRF_PSEL(SPIM_MISO, 0, 10)>,
+ <NRF_PSEL(SPIM_MOSI, 0, 9)>;
+ low-power-enable;
+ };
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c b/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c
new file mode 100644
index 0000000..b86b571
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+#include <hal/nrf_reset.h>
+
+LOG_MODULE_REGISTER(nrf7002dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL);
+
+#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP)
+#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h>
+#endif
+
+static void remoteproc_mgr_config(void)
+{
+#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) && \
+ (!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM))
+ /* Route Bluetooth Controller Debug Pins */
+ DEBUG_SETUP();
+#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */
+
+#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
+ /* Retain nRF5340 Network MCU in Secure domain (bus
+ * accesses by Network MCU will have Secure attribute set).
+ */
+ NRF_SPU->EXTDOMAIN[0].PERM = BIT(4);
+#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
+}
+
+static int remoteproc_mgr_boot(void)
+{
+
+ /* Secure domain may configure permissions for the Network MCU. */
+ remoteproc_mgr_config();
+
+#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE)
+ /*
+ * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies
+ * building also a Non-Secure image. The Non-Secure image will, in
+ * this case do the remainder of actions to properly configure and
+ * boot the Network MCU.
+ */
+
+ /* Release the Network MCU, 'Release force off signal' */
+ nrf_reset_network_force_off(NRF_RESET, false);
+
+ LOG_DBG("Network MCU released.");
+#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */
+
+ return 0;
+}
+
+SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
diff --git a/boards/nordic/nrf7002dk/nrf5340_shared_sram_planning_conf.dts b/boards/nordic/nrf7002dk/nrf5340_shared_sram_planning_conf.dts
new file mode 100644
index 0000000..d009959
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf5340_shared_sram_planning_conf.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Default shared SRAM planning when building for nRF5340.
+ * This file is included by both nRF5340 CPUAPP (Application MCU)
+ * and nRF5340 CPUNET (Network MCU).
+ * - 64 kB SRAM allocated as Shared memory (sram0_shared)
+ * - Region defined after the image SRAM of Application MCU
+ */
+
+/ {
+ chosen {
+ /* shared memory reserved for the inter-processor communication */
+ zephyr,ipc_shm = &sram0_shared;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram0_shared: memory@20070000 {
+ /* SRAM allocated to shared memory */
+ reg = <0x20070000 0x10000>;
+ };
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts
new file mode 100644
index 0000000..fbe74a8
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
+#include "nrf5340_cpuapp_common.dtsi"
+#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi"
+
+/ {
+ model = "Nordic NRF7002 DK NRF5340 Application";
+ compatible = "nordic,nrf7002-dk-nrf5340-cpuapp";
+
+ chosen {
+ zephyr,sram = &sram0_image;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,sram-secure-partition = &sram0_s;
+ zephyr,sram-non-secure-partition = &sram0_ns;
+ zephyr,wifi = &wlan0;
+ };
+};
+
+&qspi {
+ nrf70: nrf7002@1 {
+ compatible = "nordic,nrf7002-qspi";
+ status = "okay";
+ reg = <1>;
+ qspi-frequency = <24000000>;
+ qspi-quad-mode;
+
+ #include "nrf70_common.dtsi"
+ #include "nrf70_common_coex.dtsi"
+ #include "nrf70_common_5g.dtsi"
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml
new file mode 100644
index 0000000..9a6c653
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml
@@ -0,0 +1,20 @@
+identifier: nrf7002dk/nrf5340/cpuapp
+name: NRF7002-DK-NRF5340-application-MCU
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+ram: 448
+flash: 1024
+supported:
+ - gpio
+ - i2c
+ - i2s
+ - pwm
+ - watchdog
+ - usbd
+ - usb_device
+ - netif:openthread
+vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig
new file mode 100644
index 0000000..24eee28
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable PINCTRL
+CONFIG_PINCTRL=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts
new file mode 100644
index 0000000..1d78ddd
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
+#include "nrf5340_cpuapp_common.dtsi"
+#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi"
+
+/ {
+ model = "Nordic NRF7002 DK NRF5340 Application";
+ compatible = "nordic,nrf7002-dk-nrf5340-cpuapp";
+
+ chosen {
+ zephyr,sram = &sram0_image;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,sram-secure-partition = &sram0_s;
+ zephyr,sram-non-secure-partition = &sram0_ns;
+ zephyr,wifi = &wlan0;
+ };
+};
+
+&qspi {
+ nrf70: nrf7001@1 {
+ compatible = "nordic,nrf7001-qspi";
+ status = "okay";
+ reg = <1>;
+ qspi-frequency = <24000000>;
+ qspi-quad-mode;
+
+ #include "nrf70_common.dtsi"
+ #include "nrf70_common_coex.dtsi"
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml
new file mode 100644
index 0000000..e74ba06
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml
@@ -0,0 +1,20 @@
+identifier: nrf7002dk/nrf5340/cpuapp/nrf7001
+name: NRF7002-DK-NRF7001-NRF5340-application-MCU
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+ram: 448
+flash: 1024
+supported:
+ - gpio
+ - i2c
+ - i2s
+ - pwm
+ - watchdog
+ - usbd
+ - usb_device
+ - netif:openthread
+vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig
new file mode 100644
index 0000000..870fdf3
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# enable PINCTRL
+CONFIG_PINCTRL=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts
new file mode 100644
index 0000000..cbbd46d
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include "nrf5340_cpuapp_common.dtsi"
+
+/ {
+ model = "Nordic NRF5340 DK NRF5340 Application";
+ compatible = "nordic,nrf5340-dk-nrf5340-cpuapp";
+
+ chosen {
+ zephyr,sram = &sram0_ns;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_ns_partition;
+ zephyr,entropy = &psa_rng;
+ zephyr,wifi = &wlan0;
+ };
+
+ psa_rng: psa-rng {
+ compatible = "zephyr,psa-crypto-rng";
+ status = "okay";
+ };
+};
+
+&qspi {
+ nrf70: nrf7001@1 {
+ compatible = "nordic,nrf7001-qspi";
+ status = "okay";
+ reg = <1>;
+ qspi-frequency = <24000000>;
+ qspi-quad-mode;
+
+ #include "nrf70_common.dtsi"
+ #include "nrf70_common_coex.dtsi"
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml
new file mode 100644
index 0000000..1657596
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml
@@ -0,0 +1,19 @@
+identifier: nrf7002dk/nrf5340/cpuapp/nrf7001/ns
+name: NRF7002-DK-NRF7001-NRF5340-application-MCU-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+ram: 192
+flash: 192
+supported:
+ - gpio
+ - i2c
+ - pwm
+ - watchdog
+ - usbd
+ - usb_device
+ - netif:openthread
+vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig
new file mode 100644
index 0000000..c536aae
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig
@@ -0,0 +1,27 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# enable PINCTRL
+CONFIG_PINCTRL=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts
new file mode 100644
index 0000000..26ef521
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include "nrf5340_cpuapp_common.dtsi"
+
+/ {
+ model = "Nordic NRF5340 DK NRF5340 Application";
+ compatible = "nordic,nrf5340-dk-nrf5340-cpuapp";
+
+ chosen {
+ zephyr,sram = &sram0_ns;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &slot0_ns_partition;
+ zephyr,entropy = &psa_rng;
+ zephyr,wifi = &wlan0;
+ };
+
+ psa_rng: psa-rng {
+ compatible = "zephyr,psa-crypto-rng";
+ status = "okay";
+ };
+};
+
+&qspi {
+ nrf70: nrf7002@1 {
+ compatible = "nordic,nrf7002-qspi";
+ status = "okay";
+ reg = <1>;
+ qspi-frequency = <24000000>;
+ qspi-quad-mode;
+
+ #include "nrf70_common.dtsi"
+ #include "nrf70_common_coex.dtsi"
+ #include "nrf70_common_5g.dtsi"
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml
new file mode 100644
index 0000000..ea43785
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml
@@ -0,0 +1,19 @@
+identifier: nrf7002dk/nrf5340/cpuapp/ns
+name: NRF7002-DK-NRF5340-application-MCU-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+ram: 192
+flash: 192
+supported:
+ - gpio
+ - i2c
+ - pwm
+ - watchdog
+ - usbd
+ - usb_device
+ - netif:openthread
+vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig
new file mode 100644
index 0000000..c5b2eaa
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# enable PINCTRL
+CONFIG_PINCTRL=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi
new file mode 100644
index 0000000..a7cde72
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi
@@ -0,0 +1,18 @@
+&pinctrl {
+ spi2_default: spi2_default {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ };
+ };
+
+ spi2_sleep: spi2_sleep {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ low-power-enable;
+ };
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts
new file mode 100644
index 0000000..bf5a066
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpunet_qkaa.dtsi>
+#include "nrf7002dk_nrf5340_cpunet_pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "Nordic NRF7002 DK NRF5340 Network";
+ compatible = "nordic,nrf7002-dk-nrf5340-cpunet";
+
+ chosen {
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ zephyr,uart-mcumgr = &uart0;
+ zephyr,bt-mon-uart = &uart0;
+ zephyr,bt-c2h-uart = &uart0;
+ zephyr,bt-hci-ipc = &ipc0;
+ nordic,802154-spinel-ipc = &ipc0;
+ zephyr,sram = &sram1;
+ zephyr,flash = &flash1;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,ieee802154 = &ieee802154;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0: led_0 {
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 0";
+ };
+ led1: led_1 {
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 1";
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+ button0: button_0 {
+ gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 1";
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ button1: button_1 {
+ gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 2";
+ zephyr,code = <INPUT_KEY_1>;
+ };
+ };
+
+ arduino_header: connector {
+ compatible = "arduino-header-r3";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <0 0 &gpio0 4 0>, /* A0 */
+ <1 0 &gpio0 5 0>, /* A1 */
+ <2 0 &gpio0 6 0>, /* A2 */
+ <3 0 &gpio0 7 0>, /* A3 */
+ <4 0 &gpio0 25 0>, /* A4 */
+ <5 0 &gpio0 26 0>, /* A5 */
+ <6 0 &gpio1 0 0>, /* D0 */
+ <7 0 &gpio1 1 0>, /* D1 */
+ <8 0 &gpio1 4 0>, /* D2 */
+ <9 0 &gpio1 5 0>, /* D3 */
+ <10 0 &gpio1 6 0>, /* D4 */
+ <11 0 &gpio1 7 0>, /* D5 */
+ <12 0 &gpio1 8 0>, /* D6 */
+ <13 0 &gpio1 9 0>, /* D7 */
+ <14 0 &gpio1 10 0>, /* D8 */
+ <15 0 &gpio1 11 0>, /* D9 */
+ <16 0 &gpio1 12 0>, /* D10 */
+ <17 0 &gpio1 13 0>, /* D11 */
+ <18 0 &gpio1 14 0>, /* D12 */
+ <19 0 &gpio1 15 0>, /* D13 */
+ <20 0 &gpio1 2 0>, /* D14 */
+ <21 0 &gpio1 3 0>; /* D15 */
+ };
+
+ nrf70: coex {
+ status = "okay";
+ compatible = "nordic,nrf70-coex";
+
+ #include "nrf70_common_coex.dtsi"
+ };
+
+ /* These aliases are provided for compatibility with samples */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ sw0 = &button0;
+ sw1 = &button1;
+ bootloader-led0 = &led0;
+ mcuboot-button0 = &button0;
+ mcuboot-led0 = &led0;
+ watchdog0 = &wdt0;
+ };
+};
+
+&gpiote {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-1 = <&uart0_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+arduino_serial: &uart0{};
+
+arduino_i2c: &i2c0 {
+ compatible = "nordic,nrf-twim";
+ /* Cannot be used together with uart0. */
+ /* status = "okay"; */
+ pinctrl-0 = <&i2c0_default>;
+ pinctrl-1 = <&i2c0_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+arduino_spi: &spi0 {
+ compatible = "nordic,nrf-spim";
+ /* Cannot be used together with uart0. */
+ /* status = "okay"; */
+ cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
+ pinctrl-0 = <&spi0_default>;
+ pinctrl-1 = <&spi0_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&flash1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 0xc000>;
+ };
+ slot0_partition: partition@c000 {
+ label = "image-0";
+ reg = <0x0000C000 0x17000>;
+ };
+ slot1_partition: partition@23000 {
+ label = "image-1";
+ reg = <0x00023000 0x17000>;
+ };
+ storage_partition: partition@3a000 {
+ label = "storage";
+ reg = <0x0003a000 0x6000>;
+ };
+ };
+};
+
+&ieee802154 {
+ status = "okay";
+};
+
+/* Include shared RAM configuration file */
+#include "nrf5340_shared_sram_planning_conf.dts"
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml
new file mode 100644
index 0000000..f04ef6c
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml
@@ -0,0 +1,14 @@
+identifier: nrf7002dk/nrf5340/cpunet
+name: NRF7002-DK-NRF5340-network-MCU
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+ram: 64
+flash: 256
+supported:
+ - gpio
+ - watchdog
+vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig
new file mode 100644
index 0000000..ec4a0ac
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# enable PINCTRL
+CONFIG_PINCTRL=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi
new file mode 100644
index 0000000..2e19d95
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi
@@ -0,0 +1,55 @@
+&pinctrl {
+ uart0_default: uart0_default {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 1, 1)>,
+ <NRF_PSEL(UART_RTS, 1, 5)>;
+ };
+ group2 {
+ psels = <NRF_PSEL(UART_RX, 1, 0)>,
+ <NRF_PSEL(UART_CTS, 1, 4)>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_sleep: uart0_sleep {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 1, 1)>,
+ <NRF_PSEL(UART_RX, 1, 0)>,
+ <NRF_PSEL(UART_RTS, 1, 5)>,
+ <NRF_PSEL(UART_CTS, 1, 4)>;
+ low-power-enable;
+ };
+ };
+
+ i2c0_default: i2c0_default {
+ group1 {
+ psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+ <NRF_PSEL(TWIM_SCL, 1, 3)>;
+ };
+ };
+
+ i2c0_sleep: i2c0_sleep {
+ group1 {
+ psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+ <NRF_PSEL(TWIM_SCL, 1, 3)>;
+ low-power-enable;
+ };
+ };
+
+ spi0_default: spi0_default {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ };
+ };
+
+ spi0_sleep: spi0_sleep {
+ group1 {
+ psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+ <NRF_PSEL(SPIM_MISO, 1, 14)>,
+ <NRF_PSEL(SPIM_MOSI, 1, 13)>;
+ low-power-enable;
+ };
+ };
+};
diff --git a/boards/nordic/nrf7002dk/nrf70_common.dtsi b/boards/nordic/nrf7002dk/nrf70_common.dtsi
new file mode 100644
index 0000000..f40f8ad
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf70_common.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+iovdd-ctrl-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+bucken-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+host-irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+
+wifi-max-tx-pwr-2g-dsss = <21>;
+wifi-max-tx-pwr-2g-mcs0 = <16>;
+wifi-max-tx-pwr-2g-mcs7 = <16>;
+
+wlan0: wlan {
+ compatible = "nordic,wlan";
+};
diff --git a/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi b/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi
new file mode 100644
index 0000000..8be559c
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf70_common_5g.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+wifi-max-tx-pwr-5g-low-mcs0 = <9>;
+wifi-max-tx-pwr-5g-low-mcs7 = <9>;
+wifi-max-tx-pwr-5g-mid-mcs0 = <11>;
+wifi-max-tx-pwr-5g-mid-mcs7 = <11>;
+wifi-max-tx-pwr-5g-high-mcs0 = <13>;
+wifi-max-tx-pwr-5g-high-mcs7 = <13>;
diff --git a/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi b/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi
new file mode 100644
index 0000000..03f22c3
--- /dev/null
+++ b/boards/nordic/nrf7002dk/nrf70_common_coex.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
+swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+srrf-switch-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
diff --git a/boards/nordic/nrf7002dk/pre_dt_board.cmake b/boards/nordic/nrf7002dk/pre_dt_board.cmake
new file mode 100644
index 0000000..5db1310
--- /dev/null
+++ b/boards/nordic/nrf7002dk/pre_dt_board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - flash-controller@39000 & kmu@39000
+# - power@5000 & clock@5000
+# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
diff --git a/boards/nordic/nrf9280pdk/Kconfig.defconfig b/boards/nordic/nrf9280pdk/Kconfig.defconfig
new file mode 100644
index 0000000..c5c3576
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF9280PDK_NRF9280_CPUAPP
+
+config BT_HCI_IPC
+ default y if BT
+
+endif # BOARD_NRF9280PDK_NRF9280_CPUAPP
+
+if BOARD_NRF9280PDK_NRF9280_CPURAD
+
+config BT_CTLR
+ default y if BT
+
+endif # BOARD_NRF9280PDK_NRF9280_CPURAD
+
+if BOARD_NRF9280PDK_NRF9280_CPUPPR
+
+# As PPR has limited memory most of tests does not fit with asserts enabled.
+config ASSERT
+ default n if ZTEST
+
+endif # BOARD_NRF9280PDK_NRF9280_CPUPPR
diff --git a/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk b/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk
new file mode 100644
index 0000000..54865a1
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF9280PDK
+ select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP
+ select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD
+ select SOC_NRF9280_CPUPPR if BOARD_NRF9280PDK_NRF9280_CPUPPR || \
+ BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP
diff --git a/boards/nordic/nrf9280pdk/board.cmake b/boards/nordic/nrf9280pdk/board.cmake
new file mode 100644
index 0000000..0690bf3
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/board.cmake
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+
+if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP OR CONFIG_BOARD_NRF9280PDK_NRF9280_CPURAD)
+ if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP)
+ set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpuapp.JLinkScript)
+ else()
+ set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpurad.JLinkScript)
+ endif()
+
+ board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
+ include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+endif()
diff --git a/boards/nordic/nrf9280pdk/board.yml b/boards/nordic/nrf9280pdk/board.yml
new file mode 100644
index 0000000..450ef9d
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/board.yml
@@ -0,0 +1,8 @@
+board:
+ name: nrf9280pdk
+ vendor: nordic
+ socs:
+ - name: nrf9280
+ variants:
+ - name: xip
+ cpucluster: cpuppr
diff --git a/boards/nordic/nrf9280pdk/doc/index.rst b/boards/nordic/nrf9280pdk/doc/index.rst
new file mode 100644
index 0000000..ef23014
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/doc/index.rst
@@ -0,0 +1,175 @@
+.. _nrf9280pdk_nrf9280:
+
+nRF9280 PDK
+###########
+
+Overview
+********
+
+.. note::
+
+ All software for the nRF9280 SiP is experimental and hardware availability
+ is restricted to the participants in the limited sampling program.
+
+The nRF9280 DK is a single-board development kit for evaluation and development
+on the Nordic nRF9280 System-in-Package (SiP).
+
+The nRF9280 is a multicore SiP with:
+
+* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
+ Extensions, running at up to 320 MHz, referred to as the **application core**
+* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
+ Extensions, running at up to 256 MHz, referred to as the **radio core**.
+
+The ``nrf9280pdk/nrf9280/cpuapp`` board target provides support for
+the application core on the nRF9280 SiP.
+The ``nrf9280pdk/nrf9280/cpurad`` board target provides support for
+the radio core on the nRF9280 SiP.
+The ``nrf9280pdk/nrf9280/cpuppr`` board target provides support for
+the PPR core on the nRF9280 SiP.
+
+nRF9280 SiP provides support for the following devices:
+
+* :abbr:`ADC (Analog to Digital Converter)`
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`GRTC (Global real-time counter)`
+* :abbr:`I2C (Inter-Integrated Circuit)`
+* MRAM
+* :abbr:`PWM (Pulse Width Modulation)`
+* RADIO (Bluetooth Low Energy and 802.15.4)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UART (Universal asynchronous receiver-transmitter)`
+* :abbr:`USB (Universal Serial Bus)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+nRF9280 DK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+Supported Features
+==================
+
+The ``nrf9280pdk/nrf9280/cpuapp`` board target supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| GRTC | on-chip | system clock |
++-----------+------------+----------------------+
+| I2C(M) | on-chip | i2c |
++-----------+------------+----------------------+
+| PWM | on-chip | pwm |
++-----------+------------+----------------------+
+| SPI(M/S) | on-chip | spi |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| WDT | on-chip | watchdog |
++-----------+------------+----------------------+
+
+The ``nrf9280pdk/nrf9280/cpurad`` board target supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| GRTC | on-chip | system clock |
++-----------+------------+----------------------+
+| I2C(M) | on-chip | i2c |
++-----------+------------+----------------------+
+| SPI(M/S) | on-chip | spi |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| WDT | on-chip | watchdog |
++-----------+------------+----------------------+
+
+The ``nrf9280pdk/nrf9280/cpuppr`` board target supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| GRTC | on-chip | system clock |
++-----------+------------+----------------------+
+| I2C(M) | on-chip | i2c |
++-----------+------------+----------------------+
+| SPI(M/S) | on-chip | spi |
++-----------+------------+----------------------+
+| PWM | on-chip | pwm |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+Connections and IOs
+===================
+
+LEDs
+----
+
+* LED1 (green) = P9.02
+* LED2 (green) = P9.03
+* LED3 (green) = P9.04
+* LED4 (green) = P9.05
+
+Push buttons
+------------
+
+* BUTTON1 = P0.8
+* BUTTON2 = P0.9
+* BUTTON3 = P0.10
+* BUTTON4 = P0.11
+* RESET (SW1)
+
+Programming and Debugging
+*************************
+
+Applications for both the ``nrf9280pdk/nrf9280/cpuapp`` and
+``nrf9280pdk/nrf9280/cpurad`` board targets can be built, flashed,
+and debugged in the usual way. See :ref:`build_an_application`
+and :ref:`application_run` for more details on building and running.
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :ref:`hello_world`
+application.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the nRF9280 DK, complete the following steps:
+
+1. Connect the nRF9280 DK to your computer using the IMCU USB port on the DK.
+#. Build the sample by running the following command:
+
+ .. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: nrf9280pdk/nrf9280/cpuapp
+ :goals: build flash
+
+Testing the LEDs and buttons in the nRF9280 DK
+***********************************************
+
+There are 2 samples that allow you to test that the buttons (switches) and LEDs
+on the board are working properly with Zephyr:
+
+* :zephyr:code-sample:`blinky`
+* :zephyr:code-sample:`button`
+
+You can build and flash the examples to make sure Zephyr is running correctly on
+your board. The button and LED definitions can be found in
+:zephyr_file:`boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts`.
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi
new file mode 100644
index 0000000..944dd7f
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ ipc {
+ cpusec_cpuapp_ipc: ipc-1-2 {
+ compatible = "zephyr,ipc-icmsg";
+ status = "disabled";
+ mboxes = <&cpusec_bellboard 12>,
+ <&cpuapp_bellboard 0>;
+ };
+
+ cpusec_cpurad_ipc: ipc-1-3 {
+ compatible = "zephyr,ipc-icmsg";
+ status = "disabled";
+ mboxes = <&cpusec_bellboard 18>,
+ <&cpurad_bellboard 0>;
+ };
+
+ cpuapp_cpurad_ipc: ipc-2-3 {
+ compatible = "zephyr,ipc-icbmsg";
+ status = "disabled";
+ mboxes = <&cpuapp_bellboard 18>,
+ <&cpurad_bellboard 12>;
+ };
+
+ cpuapp_cpusys_ipc: ipc-2-12 {
+ compatible = "zephyr,ipc-icmsg";
+ status = "disabled";
+ mboxes = <&cpuapp_bellboard 6>,
+ <&cpusys_vevif 12>;
+ };
+
+ cpuapp_cpuppr_ipc: ipc-2-13 {
+ compatible = "zephyr,ipc-icmsg";
+ status = "disabled";
+ mboxes = <&cpuapp_bellboard 13>,
+ <&cpuppr_vevif 12>;
+ };
+
+ cpurad_cpusys_ipc: ipc-3-12 {
+ compatible = "zephyr,ipc-icmsg";
+ status = "disabled";
+ mboxes = <&cpurad_bellboard 6>,
+ <&cpusys_vevif 18>;
+ };
+ };
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi
new file mode 100644
index 0000000..78e3be8
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
+
+/ {
+ reserved-memory {
+ /* The first 64kb are reserved for SecDom.
+ * The next 4kb are reserved for IPC between SecDom and Cellcore.
+ */
+
+ cpurad_ram0x_region: memory@2f011000 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2f011000 DT_SIZE_K(4)>;
+ status = "disabled";
+ perm-read;
+ perm-write;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f011000 0x1000>;
+
+ cpusec_cpurad_ipc_shm: memory@0 {
+ reg = <0x0 DT_SIZE_K(2)>;
+ };
+
+ cpurad_cpusec_ipc_shm: memory@800 {
+ reg = <0x800 DT_SIZE_K(2)>;
+ };
+ };
+
+ cpuapp_ram0x_region: memory@2f012000 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2f012000 DT_SIZE_K(516)>;
+ status = "disabled";
+ perm-read;
+ perm-write;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f012000 0x81000>;
+
+ cpusec_cpuapp_ipc_shm: memory@0 {
+ reg = <0x0 DT_SIZE_K(2)>;
+ };
+
+ cpuapp_cpusec_ipc_shm: memory@800 {
+ reg = <0x800 DT_SIZE_K(2)>;
+ };
+
+ cpuapp_data: memory@1000 {
+ reg = <0x1000 DT_SIZE_K(512)>;
+ };
+ };
+
+ cpuapp_cpurad_ram0x_region: memory@2f0cf000 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2f0cf000 DT_SIZE_K(4)>;
+ status = "disabled";
+ perm-read;
+ perm-write;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f0cf000 0x1000>;
+
+ cpuapp_cpurad_ipc_shm: memory@0 {
+ reg = <0x0 DT_SIZE_K(2)>;
+ };
+
+ cpurad_cpuapp_ipc_shm: memory@800 {
+ reg = <0x800 DT_SIZE_K(2)>;
+ };
+ };
+
+ cpuapp_cpucell_ram0x_region: memory@2f0d0000 {
+ reg = <0x2f0d0000 DT_SIZE_K(36)>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f0d0000 0x9000>;
+
+ /* Control region, with ICmsg buffers.
+ * Size is fixed.
+ */
+ cpuapp_cpucell_ipc_shm_ctrl: memory@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ /* TX heap, user defined */
+ cpuapp_cpucell_ipc_shm_heap: memory@1000 {
+ reg = <0x1000 0x4000>;
+ };
+
+ /* RX heap, user defined */
+ cpucell_cpuapp_ipc_shm_heap: memory@5000 {
+ reg = <0x5000 0x4000>;
+ };
+ };
+
+ /* Shared memory ownership.
+ * TODO:
+ * remove these two after https://github.com/zephyrproject-rtos/zephyr/pull/72273
+ * and let cpuapp_cpucell_ram0x_region use the `access` binding to describe
+ * the shared memory ownership.
+ */
+
+ cpuapp_cpucell_ipc_shm: memory@2 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2f0d0000 DT_SIZE_K(36)>;
+ owner-id = <2>;
+ perm-read;
+ perm-write;
+ status = "disabled";
+ };
+
+ cpucell_cpuapp_ipc_shm: memory@4 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2f0d0000 DT_SIZE_K(36)>;
+ owner-id = <4>;
+ perm-read;
+ perm-write;
+ status = "disabled";
+ };
+
+ shared_ram20_region: memory@2f88f000 {
+ reg = <0x2f88f000 DT_SIZE_K(4)>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f88f000 0x1000>;
+
+ cpuapp_cpusys_ipc_shm: memory@ce0 {
+ reg = <0xce0 0x80>;
+ };
+
+ cpusys_cpuapp_ipc_shm: memory@d60 {
+ reg = <0xd60 0x80>;
+ };
+
+ cpurad_cpusys_ipc_shm: memory@e00 {
+ reg = <0xe00 0x80>;
+ };
+
+ cpusys_cpurad_ipc_shm: memory@e80 {
+ reg = <0xe80 0x80>;
+ };
+ };
+
+ ram21_region: memory@2f890000 {
+ compatible = "nordic,owned-memory";
+ status = "disabled";
+ reg = <0x2f890000 DT_SIZE_K(32)>;
+ perm-read;
+ perm-write;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2f890000 0x8000>;
+
+ dma_fast_region: memory@4000 {
+ compatible = "zephyr,memory-region";
+ reg = <0x4000 DT_SIZE_K(16)>;
+ status = "disabled";
+ #memory-region-cells = <0>;
+ zephyr,memory-region = "DMA_RAM21";
+ zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
+ };
+ };
+
+ cpuppr_ram3x_region: memory@2fc00000 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2fc00000 DT_SIZE_K(24)>;
+ status = "disabled";
+ perm-read;
+ perm-write;
+ perm-execute;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2fc00000 0x6000>;
+
+ cpuppr_code_data: memory@0 {
+ reg = <0x0 DT_SIZE_K(22)>;
+ };
+
+ cpuapp_cpuppr_ipc_shm: memory@5800 {
+ reg = <0x5800 DT_SIZE_K(1)>;
+ };
+
+ cpuppr_cpuapp_ipc_shm: memory@5c00 {
+ reg = <0x5c00 DT_SIZE_K(1)>;
+ };
+ };
+
+ shared_ram3x_region: memory@2fc06000 {
+ compatible = "nordic,owned-memory";
+ reg = <0x2fc06000 DT_SIZE_K(8)>;
+ status = "disabled";
+ perm-read;
+ perm-write;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2fc06000 0x4000>;
+
+ cpuapp_dma_region: memory@0 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0 DT_SIZE_K(4)>;
+ status = "disabled";
+ #memory-region-cells = <0>;
+ zephyr,memory-region = "DMA_RAM3x_APP";
+ zephyr,memory-attr = <( DT_MEM_DMA )>;
+ };
+
+ cpurad_dma_region: memory@1000 {
+ compatible = "zephyr,memory-region";
+ reg = <0x1000 0x80>;
+ status = "disabled";
+ #memory-region-cells = <0>;
+ zephyr,memory-region = "DMA_RAM3x_RAD";
+ zephyr,memory-attr = <( DT_MEM_DMA )>;
+ };
+ };
+ };
+};
+
+&mram1x {
+ cpurad_rx_partitions: cpurad-rx-partitions {
+ compatible = "nordic,owned-partitions", "fixed-partitions";
+ status = "disabled";
+ perm-read;
+ perm-execute;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpurad_slot0_partition: partition@402000 {
+ reg = <0x402000 DT_SIZE_K(256)>;
+ };
+ };
+
+ cpuapp_rx_partitions: cpuapp-rx-partitions {
+ compatible = "nordic,owned-partitions", "fixed-partitions";
+ status = "disabled";
+ perm-read;
+ perm-execute;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpuapp_slot0_partition: partition@442000 {
+ reg = <0x442000 DT_SIZE_K(1024)>;
+ };
+
+ cpuppr_code_partition: partition@542000 {
+ reg = <0x542000 DT_SIZE_K(64)>;
+ };
+ };
+
+ cpuapp_rw_partitions: cpuapp-rw-partitions {
+ compatible = "nordic,owned-partitions", "fixed-partitions";
+ status = "disabled";
+ perm-read;
+ perm-write;
+ perm-secure;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dfu_partition: partition@600000 {
+ reg = <0x600000 DT_SIZE_K(512)>;
+ };
+
+ storage_partition: partition@680000 {
+ reg = <0x680000 DT_SIZE_K(24)>;
+ };
+ };
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi
new file mode 100644
index 0000000..48067a7
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ /omit-if-no-ref/ uart135_default: uart135_default {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 1, 4)>,
+ <NRF_PSEL(UART_RTS, 1, 0)>;
+ };
+
+ group3 {
+ bias-pull-up;
+ psels = <NRF_PSEL(UART_RX, 1, 5)>,
+ <NRF_PSEL(UART_CTS, 1, 6)>;
+ };
+ };
+
+ /omit-if-no-ref/ uart135_sleep: uart135_sleep {
+ group1 {
+ low-power-enable;
+ psels = <NRF_PSEL(UART_TX, 1, 4)>,
+ <NRF_PSEL(UART_RX, 1, 5)>,
+ <NRF_PSEL(UART_RTS, 1, 0)>,
+ <NRF_PSEL(UART_CTS, 1, 6)>;
+ };
+ };
+
+ /omit-if-no-ref/ uart136_default: uart136_default {
+ group1 {
+ psels = <NRF_PSEL(UART_TX, 0, 4)>,
+ <NRF_PSEL(UART_RTS, 0, 0)>;
+ };
+
+ group3 {
+ bias-pull-up;
+ psels = <NRF_PSEL(UART_RX, 0, 5)>,
+ <NRF_PSEL(UART_CTS, 0, 6)>;
+ };
+ };
+
+ /omit-if-no-ref/ uart136_sleep: uart136_sleep {
+ group1 {
+ low-power-enable;
+ psels = <NRF_PSEL(UART_TX, 0, 4)>,
+ <NRF_PSEL(UART_RX, 0, 5)>,
+ <NRF_PSEL(UART_RTS, 0, 0)>,
+ <NRF_PSEL(UART_CTS, 0, 6)>;
+ };
+ };
+
+ /omit-if-no-ref/ exmif_default: exmif_default {
+ group1 {
+ psels = <NRF_PSEL(EXMIF_CK, 6, 0)>,
+ <NRF_PSEL(EXMIF_DQ0, 6, 7)>,
+ <NRF_PSEL(EXMIF_DQ1, 6, 5)>;
+ nordic,drive-mode = <NRF_DRIVE_H0H1>;
+ };
+ };
+
+ /omit-if-no-ref/ can120_default: can120_default {
+ group1 {
+ psels = <NRF_PSEL(CAN_RX, 9, 4)>,
+ <NRF_PSEL(CAN_TX, 9, 5)>;
+ };
+ };
+
+ /omit-if-no-ref/ pwm130_default: pwm130_default {
+ group1 {
+ psels = <NRF_PSEL(PWM_OUT0, 9, 2)>;
+ };
+ };
+
+ /omit-if-no-ref/ pwm130_sleep: pwm130_sleep {
+ group1 {
+ psels = <NRF_PSEL(PWM_OUT0, 9, 2)>;
+ low-power-enable;
+ };
+ };
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts
new file mode 100644
index 0000000..ceb4ddc
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf9280_cpuapp.dtsi>
+#include "nrf9280pdk_nrf9280-memory_map.dtsi"
+#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
+#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
+
+/delete-node/ &cpurad_cpusys_ipc;
+/delete-node/ &cpusec_cpurad_ipc;
+
+/ {
+ compatible = "nordic,nrf9280pdk_nrf9280-cpuapp";
+ model = "Nordic nRF9280 DK nRF9280 Application MCU";
+
+ chosen {
+ zephyr,console = &uart136;
+ zephyr,code-partition = &cpuapp_slot0_partition;
+ zephyr,flash = &mram1x;
+ zephyr,sram = &cpuapp_data;
+ zephyr,shell-uart = &uart136;
+ zephyr,ieee802154 = &cpuapp_ieee802154;
+ zephyr,bt-hci = &bt_hci_ipc0;
+ nordic,802154-spinel-ipc = &ipc0;
+ zephyr,canbus = &can120;
+ };
+
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ led3 = &led3;
+ resetinfo = &cpuapp_resetinfo;
+ pwm-led0 = &pwm_led0;
+ sw0 = &button0;
+ sw1 = &button1;
+ sw2 = &button2;
+ sw3 = &button3;
+ ipc-to-cpusys = &cpuapp_cpusys_ipc;
+ watchdog0 = &wdt010;
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ button0: button_0 {
+ gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 0";
+ zephyr,code = <INPUT_KEY_0>;
+ };
+
+ button1: button_1 {
+ gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 1";
+ zephyr,code = <INPUT_KEY_1>;
+ };
+
+ button2: button_2 {
+ gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 2";
+ zephyr,code = <INPUT_KEY_2>;
+ };
+
+ button3: button_3 {
+ gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ label = "Push button 3";
+ zephyr,code = <INPUT_KEY_3>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0: led_0 {
+ gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 0";
+ };
+
+ led1: led_1 {
+ gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 1";
+ };
+
+ led2: led_2 {
+ gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 2";
+ };
+
+ led3: led_3 {
+ gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
+ label = "Green LED 3";
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+ /*
+ * LEDs are connected to GPIO Port 9 - pins 2-5. There is no valid hardware
+ * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
+ * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2.
+ */
+ pwm_led0: pwm_led_0 {
+ pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+ };
+ };
+};
+
+&cpuapp_ram0x_region {
+ status = "okay";
+};
+
+&cpuapp_cpurad_ram0x_region {
+ status = "okay";
+};
+
+&cpuapp_cpucell_ipc_shm {
+ status = "okay";
+};
+
+&cpucell_cpuapp_ipc_shm {
+ status = "okay";
+};
+
+&shared_ram3x_region {
+ status = "okay";
+};
+
+&ram21_region {
+ status = "okay";
+};
+
+&cpuapp_bellboard {
+ status = "okay";
+ interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
+ interrupt-names = "irq0";
+ /* The following bells on this bellboard are rang by these cores
+ * - Bell 0: cpusec
+ * - Bell 6: cpusys
+ * - Bell 13: cpuppr
+ * - Bell 18: cpurad
+ * - Bells 24, 25, 29, 31: cpucell
+ */
+ nordic,interrupt-mapping = <0xA3042041 0>;
+};
+
+&cpurad_bellboard {
+ status = "okay";
+};
+
+&cpucell_bellboard {
+ status = "okay";
+};
+
+&cpusys_vevif {
+ status = "okay";
+};
+
+&cpusec_cpuapp_ipc {
+ mbox-names = "tx", "rx";
+ tx-region = <&cpuapp_cpusec_ipc_shm>;
+ rx-region = <&cpusec_cpuapp_ipc_shm>;
+};
+
+ipc0: &cpuapp_cpurad_ipc {
+ status = "okay";
+ mbox-names = "rx", "tx";
+ tx-region = <&cpuapp_cpurad_ipc_shm>;
+ rx-region = <&cpurad_cpuapp_ipc_shm>;
+ tx-blocks = <32>;
+ rx-blocks = <32>;
+
+ bt_hci_ipc0: bt_hci_ipc0 {
+ compatible = "zephyr,bt-hci-ipc";
+ status = "okay";
+ };
+};
+
+&cpuapp_cpusys_ipc {
+ status = "okay";
+ mbox-names = "rx", "tx";
+ tx-region = <&cpuapp_cpusys_ipc_shm>;
+ rx-region = <&cpusys_cpuapp_ipc_shm>;
+};
+
+&cpuapp_cpuppr_ipc {
+ mbox-names = "rx", "tx";
+ tx-region = <&cpuapp_cpuppr_ipc_shm>;
+ rx-region = <&cpuppr_cpuapp_ipc_shm>;
+};
+
+&cpuapp_dma_region {
+ status = "okay";
+};
+
+&dma_fast_region {
+ status = "okay";
+};
+
+&cpuapp_rx_partitions {
+ status = "okay";
+};
+
+&cpuapp_rw_partitions {
+ status = "okay";
+};
+
+&cpuppr_vpr {
+ execution-memory = <&cpuppr_code_data>;
+ source-memory = <&cpuppr_code_partition>;
+};
+
+&gpiote130 {
+ status = "okay";
+ owned-channels = <0 1 2 3 4 5 6 7>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio9 {
+ status = "okay";
+};
+
+&grtc {
+ status = "okay";
+ child-owned-channels = <5 6>;
+ nonsecure-channels = <5 6>;
+ owned-channels = <4 5 6>;
+};
+
+&uart135 {
+ current-speed = <115200>;
+ pinctrl-0 = <&uart135_default>;
+ pinctrl-1 = <&uart135_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&uart136 {
+ status = "okay";
+ memory-regions = <&cpuapp_dma_region>;
+ current-speed = <115200>;
+ pinctrl-0 = <&uart136_default>;
+ pinctrl-1 = <&uart136_sleep>;
+ pinctrl-names = "default", "sleep";
+ hw-flow-control;
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&exmif {
+ cs-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&exmif_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ mx25uw63: mx25uw6345g@0 {
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ reg = <0>;
+ spi-max-frequency = <DT_FREQ_M(48)>;
+ jedec-id = [c2 84 37];
+ sfdp-bfp = [
+ e5 20 8a ff ff ff ff 03 00 ff 00 ff 00 ff 00 ff
+ ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 10 d8
+ 00 ff 00 ff 87 79 01 00 84 12 00 c4 cc 04 67 46
+ 30 b0 30 b0 f4 bd d5 5c 00 00 00 ff 10 10 00 20
+ 00 00 00 00 00 00 7c 23 48 00 00 00 00 00 88 88
+ ];
+ size = <67108864>;
+ has-dpd;
+ t-enter-dpd = <10000>;
+ t-exit-dpd = <30000>;
+ };
+};
+
+&cpuapp_ieee802154 {
+ status = "okay";
+};
+
+zephyr_udc0: &usbhs {
+ status = "okay";
+};
+
+&canpll {
+ status = "okay";
+};
+
+&can120 {
+ status = "okay";
+ pinctrl-0 = <&can120_default>;
+ pinctrl-names = "default";
+};
+
+&pwm130 {
+ status = "okay";
+ pinctrl-0 = <&pwm130_default>;
+ pinctrl-1 = <&pwm130_sleep>;
+ pinctrl-names = "default", "sleep";
+ memory-regions = <&cpuapp_dma_region>;
+};
+
+&adc {
+ memory-regions = <&cpuapp_dma_region>;
+ status = "okay";
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml
new file mode 100644
index 0000000..9c2aff8
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf9280pdk/nrf9280/cpuapp
+name: nRF9280-DK-nRF9280-Application
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+sysbuild: true
+ram: 512
+flash: 1024
+supported:
+ - adc
+ - can
+ - counter
+ - gpio
+ - i2c
+ - pwm
+ - spi
+ - watchdog
+ - usbd
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig
new file mode 100644
index 0000000..e1ba596
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig
@@ -0,0 +1,28 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot be applied
+# as the (0x0 - 0x400) region is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts
new file mode 100644
index 0000000..5da976e
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf9280_cpuppr.dtsi>
+#include "nrf9280pdk_nrf9280-memory_map.dtsi"
+#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
+#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
+
+/delete-node/ &cpuapp_cpurad_ipc;
+/delete-node/ &cpuapp_cpusys_ipc;
+/delete-node/ &cpurad_cpusys_ipc;
+/delete-node/ &cpusec_cpuapp_ipc;
+/delete-node/ &cpusec_cpurad_ipc;
+
+/ {
+ compatible = "nordic,nrf9280pdk_nrf9280-cpuppr";
+ model = "Nordic nRF9280 DK nRF9280 Peripheral Processor MCU";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ zephyr,console = &uart135;
+ zephyr,code-partition = &cpuppr_code_partition;
+ zephyr,flash = &mram1x;
+ zephyr,sram = &cpuppr_code_data;
+ zephyr,shell-uart = &uart135;
+ };
+};
+
+&cpuapp_cpuppr_ipc {
+ mbox-names = "tx", "rx";
+ tx-region = <&cpuppr_cpuapp_ipc_shm>;
+ rx-region = <&cpuapp_cpuppr_ipc_shm>;
+};
+
+&grtc {
+ status = "okay";
+ owned-channels = <5>;
+};
+
+&uart135 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart135_default>;
+ pinctrl-1 = <&uart135_sleep>;
+ pinctrl-names = "default", "sleep";
+ hw-flow-control;
+};
+
+&uart136 {
+ current-speed = <115200>;
+ pinctrl-0 = <&uart136_default>;
+ pinctrl-1 = <&uart136_sleep>;
+ pinctrl-names = "default", "sleep";
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml
new file mode 100644
index 0000000..958b5d4
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf9280pdk/nrf9280/cpuppr
+name: nRF9280-DK-nRF9280-PPR
+type: mcu
+arch: riscv
+toolchain:
+ - zephyr
+sysbuild: true
+ram: 22
+flash: 22
+supported:
+ - counter
+ - gpio
+ - i2c
+ - pwm
+ - spi
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig
new file mode 100644
index 0000000..b6ee610
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from RAM
+CONFIG_XIP=n
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts
new file mode 100644
index 0000000..30034d2
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf9280pdk_nrf9280_cpuppr.dts"
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml
new file mode 100644
index 0000000..d57f9c8
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf9280pdk/nrf9280/cpuppr/xip
+name: nRF9280-DK-nRF9280-PPR (MRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+ - zephyr
+sysbuild: true
+ram: 22
+flash: 64
+supported:
+ - gpio
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig
new file mode 100644
index 0000000..d73f271
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+CONFIG_XIP=y
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts
new file mode 100644
index 0000000..1235f53
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf9280_cpurad.dtsi>
+#include "nrf9280pdk_nrf9280-memory_map.dtsi"
+#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
+#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
+
+/delete-node/ &cpuapp_cpuppr_ipc;
+/delete-node/ &cpuapp_cpusys_ipc;
+/delete-node/ &cpusec_cpuapp_ipc;
+
+/ {
+ compatible = "nordic,nrf9280pdk_nrf9280-cpurad";
+ model = "Nordic nRF9280 DK nRF9280 Radio MCU";
+
+ chosen {
+ zephyr,console = &uart135;
+ zephyr,code-partition = &cpurad_slot0_partition;
+ zephyr,flash = &mram1x;
+ zephyr,sram = &cpurad_ram0;
+ zephyr,shell-uart = &uart135;
+ zephyr,ieee802154 = &cpurad_ieee802154;
+ zephyr,bt-hci-ipc = &ipc0;
+ nordic,802154-spinel-ipc = &ipc0;
+ };
+ aliases {
+ ipc-to-cpusys = &cpurad_cpusys_ipc;
+ resetinfo = &cpurad_resetinfo;
+ };
+};
+
+&shared_ram3x_region {
+ status = "okay";
+};
+
+&cpuapp_cpurad_ram0x_region {
+ status = "okay";
+};
+
+&cpurad_bellboard {
+ status = "okay";
+ interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
+ interrupt-names = "irq0";
+ /* The following bells on this bellboard are rang by these cores
+ * - Bell 0: cpusec
+ * - Bell 6: cpusys
+ * - Bell 12: cpuapp
+ */
+ nordic,interrupt-mapping = <0x00001041 0>;
+};
+
+&cpuapp_bellboard {
+ status = "okay";
+};
+
+&cpusys_vevif {
+ status = "okay";
+};
+
+&cpusec_cpurad_ipc {
+ mbox-names = "tx", "rx";
+ tx-region = <&cpurad_cpusec_ipc_shm>;
+ rx-region = <&cpusec_cpurad_ipc_shm>;
+};
+
+ipc0: &cpuapp_cpurad_ipc {
+ status = "okay";
+ mbox-names = "tx", "rx";
+ tx-region = <&cpurad_cpuapp_ipc_shm>;
+ rx-region = <&cpuapp_cpurad_ipc_shm>;
+ tx-blocks = <32>;
+ rx-blocks = <32>;
+};
+
+&cpurad_cpusys_ipc {
+ status = "okay";
+ mbox-names = "rx", "tx";
+ tx-region = <&cpurad_cpusys_ipc_shm>;
+ rx-region = <&cpusys_cpurad_ipc_shm>;
+};
+
+&cpurad_dma_region {
+ status = "okay";
+};
+
+&cpurad_rx_partitions {
+ status = "okay";
+};
+
+&grtc {
+ status = "okay";
+};
+
+&uart135 {
+ status = "okay";
+ memory-regions = <&cpurad_dma_region>;
+ current-speed = <115200>;
+ pinctrl-0 = <&uart135_default>;
+ pinctrl-1 = <&uart135_sleep>;
+ pinctrl-names = "default", "sleep";
+ hw-flow-control;
+};
+
+&uart136 {
+ current-speed = <115200>;
+ pinctrl-0 = <&uart136_default>;
+ pinctrl-1 = <&uart136_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&cpurad_ieee802154 {
+ status = "okay";
+};
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml
new file mode 100644
index 0000000..543a737
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf9280pdk/nrf9280/cpurad
+name: nRF9280-DK-nRF9280-Radio
+type: mcu
+arch: arm
+toolchain:
+ - gnuarmemb
+ - xtools
+ - zephyr
+sysbuild: true
+ram: 32
+flash: 256
+supported:
+ - counter
+ - gpio
+ - pwm
+ - spi
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig
new file mode 100644
index 0000000..27df01d
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot be applied
+# as the (0x0 - 0x400) region is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript
new file mode 100644
index 0000000..ffa1bee
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript
@@ -0,0 +1,41 @@
+// Debug Halting Control and Status Register
+__constant U32 _DHCSR_ADDR = 0xE000EDF0;
+__constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
+__constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
+__constant U32 _DHCSR_C_HALT = (1 << 1);
+
+// Debug Exception and Monitor Control Register
+__constant U32 _DEMCR_ADDR = 0xE000EDFC;
+__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
+__constant U32 _DEMCR_TRCENA = (1 << 24);
+
+// CPU wait enable register
+__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5201150C;
+
+int ResetTarget(void) {
+ // ADAC reset
+ JLINK_CORESIGHT_WriteDP(2, 0x04000010);
+ JLINK_CORESIGHT_WriteAP(0, 0xA3030000);
+ JLINK_CORESIGHT_WriteAP(0, 0x00000004);
+ JLINK_CORESIGHT_WriteAP(0, 0x01020000);
+
+ JLINK_SYS_Sleep(100);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+
+ // Halt the CPU
+ JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
+
+ // Set vector catch on reset (to halt the CPU immediately after reset)
+ JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
+
+ // Disable CPU wait
+ JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0);
+
+ // Clear vector catch stuff
+ JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
+
+ return 0;
+}
diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript
new file mode 100644
index 0000000..2f18028
--- /dev/null
+++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript
@@ -0,0 +1,48 @@
+// Debug Halting Control and Status Register
+__constant U32 _DHCSR_ADDR = 0xE000EDF0;
+__constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
+__constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
+__constant U32 _DHCSR_C_HALT = (1 << 1);
+
+// Debug Exception and Monitor Control Register
+__constant U32 _DEMCR_ADDR = 0xE000EDFC;
+__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
+__constant U32 _DEMCR_TRCENA = (1 << 24);
+
+// CPU wait enable register
+__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5301150C;
+
+int ConfigTargetSettings(void) {
+ JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP");
+ CORESIGHT_IndexAHBAPToUse = 1;
+
+ return 0;
+}
+
+int ResetTarget(void) {
+ // ADAC reset
+ JLINK_CORESIGHT_WriteDP(2, 0x04000010);
+ JLINK_CORESIGHT_WriteAP(0, 0xA3030000);
+ JLINK_CORESIGHT_WriteAP(0, 0x00000004);
+ JLINK_CORESIGHT_WriteAP(0, 0x01030000);
+
+ JLINK_SYS_Sleep(100);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+ JLINK_CORESIGHT_ReadAP(2);
+
+ // Halt the CPU
+ JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
+
+ // Set vector catch on reset (to halt the CPU immediately after reset)
+ JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
+
+ // Disable CPU wait
+ JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0);
+
+ // Clear vector catch stuff
+ JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
+
+ return 0;
+}
diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig
index 8700f3d..01b2ee7 100644
--- a/boards/nordic/thingy53/Kconfig
+++ b/boards/nordic/thingy53/Kconfig
@@ -9,9 +9,6 @@
help
Initialization priority of the Thingy:53.
-config MBOX_NRFX_IPC
- default MBOX
-
if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS
config BOARD_SERIAL_BACKEND_CDC_ACM
diff --git a/boards/nuvoton/npcm400_evb/Kconfig.defconfig b/boards/nuvoton/npcm400_evb/Kconfig.defconfig
new file mode 100644
index 0000000..058d1ef
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/Kconfig.defconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SYS_CLOCK_TICKS_PER_SEC
+ default 1000
diff --git a/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb b/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb
new file mode 100644
index 0000000..068f536
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/Kconfig.npcm400_evb
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NPCM400_EVB
+ select SOC_NPCM400
diff --git a/boards/nuvoton/npcm400_evb/board.cmake b/boards/nuvoton/npcm400_evb/board.cmake
new file mode 100644
index 0000000..1b63186
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=npcm400" "--speed=4000")
+board_runner_args(jlink "--file=./build/zephyr/${CONFIG_KERNEL_BIN_NAME}.npcm.bin")
+board_runner_args(jlink "--reset-after-load")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nuvoton/npcm400_evb/board.yml b/boards/nuvoton/npcm400_evb/board.yml
new file mode 100644
index 0000000..1a428cc
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: npcm400_evb
+ vendor: nuvoton
+ socs:
+ - name: npcm400
diff --git a/boards/nuvoton/npcm400_evb/doc/index.rst b/boards/nuvoton/npcm400_evb/doc/index.rst
new file mode 100644
index 0000000..930ac3d
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/doc/index.rst
@@ -0,0 +1,108 @@
+.. _npcm400_evb:
+
+Nuvoton NPCM400_EVB
+####################
+
+Overview
+********
+
+The NPCM400_EVB kit is a development platform to evaluate the
+Nuvoton NPCM4 series microcontrollers. This board needs to be mated with
+part number NPCM400 Satellite Management Controller (SMC).
+
+.. image:: npcm400_evb.webp
+ :align: center
+ :alt: NPCM400 Evaluation Board
+
+Hardware
+********
+
+- ARM Cortex-M4F Processor
+- Core clock up to 100 MHz
+- 1MB Integrated Flash
+- 32KB cache for XIP and Data
+- 768 KB RAM and 64 KB boot ROM
+- ADC & GPIO headers
+- UART0 and UART1
+- I2C/I3C
+- RMII
+- USB2.0 Device
+- USB1.1 Host
+- Secure Boot is supported
+
+Supported Features
+==================
+
+The following features are supported:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| ADC | on-chip | adc controller |
++-----------+------------+-------------------------------------+
+| CLOCK | on-chip | reset and clock control |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c port/controller |
++-----------+------------+-------------------------------------+
+| I3C | on-chip | i3c port/controller |
++-----------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+-------------------------------------+
+| WDT | on-chip | watchdog |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+:zephyr_file:`boards/nuvoton/npcm400_evb/npcm400_evb_defconfig`
+
+Connections and IOs
+===================
+
+Nuvoton to provide the schematic for this board.
+
+Serial Port
+===========
+
+UART0 is configured for serial logs. The default serial setup is 115200 8N1.
+
+Programming and Debugging
+*************************
+
+This board comes with a Cortex ETM port which facilitates tracing and debugging
+using a single physical connection. In addition, it comes with sockets for
+JTAG-only sessions.
+
+Flashing
+========
+
+If the correct headers are installed, this board supports J-TAG.
+
+To flash with J-TAG, install the drivers for your programmer, for example:
+SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: npcm400_evb
+ :goals: flash
+
+Open a serial terminal, and you should see the following message in the terminal:
+
+.. code-block:: console
+
+ Hello World! npcm400_evb/npcm400
+
+Debugging
+=========
+
+Use JTAG/SWD with a J-Link
+
+References
+**********
diff --git a/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp b/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp
new file mode 100644
index 0000000..479e7c5
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/doc/npcm400_evb.webp
Binary files differ
diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb.dts b/boards/nuvoton/npcm400_evb/npcm400_evb.dts
new file mode 100644
index 0000000..2211799
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/npcm400_evb.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nuvoton/npcm400.dtsi>
+
+/ {
+ model = "Nuvoton NPCM400 evaluation board";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ };
+
+ aliases {
+ };
+
+};
diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb.yaml b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml
new file mode 100644
index 0000000..c9628e4
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: npcm400_evb
+name: Nuvoton NPCM400 EVB
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ram: 768
+flash: 1024
+vendor: nuvoton
diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig b/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig
new file mode 100644
index 0000000..687f322
--- /dev/null
+++ b/boards/nuvoton/npcm400_evb/npcm400_evb_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SRAM_VECTOR_TABLE=y
+
+# General Kernel Options
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
+CONFIG_XIP=y
+
+# UART Driver
+CONFIG_SERIAL=n
+
+# Console Driver
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts
index b877b19..bd849f0 100644
--- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts
+++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts
@@ -65,8 +65,6 @@
};
&scc {
- /* For USB 1.1 Host/Device/OTG, configure to 192MHz, which can generate necessary 48MHz. */
- /* For USB 2.0 Host/Device/OTG or no USB application, comment out to use default. */
core-clock = <192000000>;
};
@@ -122,7 +120,7 @@
status = "okay";
};
-/* On enabled, 'core-clock', as above, is required to be 192MHz. */
+/* On enabled, usbd is required to be clocked in 48MHz. */
zephyr_udc0: &usbd {
pinctrl-0 = <&usbd_default>;
pinctrl-names = "default";
diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
index d668f51..a7e2696 100644
--- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
+++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
@@ -13,4 +13,5 @@
flash: 1024
supported:
- gpio
+ - usbd
vendor: nuvoton
diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst
index 73cb76b..7fb9f29 100644
--- a/boards/nxp/frdm_ke17z/doc/index.rst
+++ b/boards/nxp/frdm_ke17z/doc/index.rst
@@ -59,6 +59,8 @@
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
+| LPTMR | on-chip | counter |
++-----------+------------+-------------------------------------+
| UART | on-chip | uart |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
@@ -71,6 +73,8 @@
+-----------+------------+-------------------------------------+
| ACMP | on-chip | sensor |
+-----------+------------+-------------------------------------+
+| WATCHDOG | on-chip | watchdog |
++-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/frdm_ke17z/frdm_ke17z_defconfig`.
diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts
index 87f1798..802c1a0 100644
--- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts
+++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts
@@ -16,6 +16,7 @@
compatible = "nxp,frdm-ke17z", "nxp,ke17z", "nxp,mke17z7";
aliases {
+ watchdog0 = &wdog;
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
@@ -80,6 +81,15 @@
};
};
+&idle {
+ min-residency-us = <1>;
+};
+
+&stop {
+ min-residency-us = <20000>;
+ exit-latency-us = <13>;
+};
+
&lpuart0 {
dmas = <&edma 1 2>, <&edma 2 3>;
dma-names = "rx", "tx";
@@ -160,3 +170,7 @@
&edma {
status = "okay";
};
+
+&wdog {
+ status = "okay";
+};
diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
index 3ef4c75..f406935 100644
--- a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
+++ b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
@@ -9,6 +9,7 @@
- gnuarmemb
- xtools
supported:
+ - counter
- gpio
- adc
- uart
@@ -16,4 +17,5 @@
- i2c
- spi
- dma
+ - watchdog
vendor: nxp
diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig
index 5d3e6d7..90637181 100644
--- a/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig
+++ b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig
@@ -14,7 +14,6 @@
# Clock Control
CONFIG_CLOCK_CONTROL=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# Enable pin controller
CONFIG_PINCTRL=y
diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst
index f727ae1..3e5be80 100644
--- a/boards/nxp/frdm_ke17z512/doc/index.rst
+++ b/boards/nxp/frdm_ke17z512/doc/index.rst
@@ -58,6 +58,8 @@
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
+| LPTMR | on-chip | counter |
++-----------+------------+-------------------------------------+
| UART | on-chip | uart polling; |
| | | uart interrupt |
+-----------+------------+-------------------------------------+
@@ -73,6 +75,8 @@
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
+| WATCHDOG | on-chip | watchdog |
++-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig``.
diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
index 7273431..a2910a7 100644
--- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
+++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
@@ -23,6 +23,7 @@
};
aliases {
+ watchdog0 = &wdog;
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
@@ -80,6 +81,15 @@
};
};
+&idle {
+ min-residency-us = <1>;
+};
+
+&stop {
+ min-residency-us = <20000>;
+ exit-latency-us = <13>;
+};
+
&lpuart2 {
dmas = <&edma 5 6>, <&edma 6 7>;
dma-names = "rx", "tx";
@@ -100,6 +110,12 @@
status = "okay";
};
+&scg {
+ bus_clk {
+ clock-div = <2>;
+ };
+};
+
&gpioe {
status = "okay";
};
@@ -172,3 +188,7 @@
&edma {
status = "okay";
};
+
+&wdog {
+ status = "okay";
+};
diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
index 3c32347..6b817b1 100644
--- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
+++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
@@ -23,4 +23,5 @@
- i2c
- spi
- dma
+ - watchdog
vendor: nxp
diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig
index d1237a3..508db6d 100644
--- a/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig
+++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig
@@ -8,5 +8,4 @@
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_PINCTRL=y
diff --git a/boards/nxp/frdm_mcxn236/CMakeLists.txt b/boards/nxp/frdm_mcxn236/CMakeLists.txt
new file mode 100644
index 0000000..df4c393
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/frdm_mcxn236/Kconfig b/boards/nxp/frdm_mcxn236/Kconfig
new file mode 100644
index 0000000..23271bc
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/Kconfig
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+ int "Board initialization priority"
+ default 1
+ help
+ Board initialization priority.
diff --git a/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 b/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236
new file mode 100644
index 0000000..f77e46f
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236
@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXN236
+ select SOC_MCXN236
+ select SOC_PART_NUMBER_MCXN236VDF
diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c
new file mode 100644
index 0000000..8f0d1fd
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/board.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Board xtal frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ 24000000U
+/* Core clock frequency: 150MHz */
+#define CLOCK_INIT_CORE_CLOCK 150000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+static void enable_lpcac(void)
+{
+ SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
+ SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
+ SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
+}
+
+/* Update Active mode voltage for OverDrive mode. */
+void power_mode_od(void)
+{
+ /* Set the DCDC VDD regulator to 1.2 V voltage level */
+ spc_active_mode_dcdc_option_t opt = {
+ .DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
+ .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
+ };
+ SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
+
+ /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
+ spc_active_mode_core_ldo_option_t ldo_opt = {
+ .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
+ .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
+ };
+ SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
+
+ /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
+ spc_sram_voltage_config_t cfg = {
+ .operateVoltage = kSPC_sramOperateAt1P2V,
+ .requestVoltageUpdate = true,
+ };
+ SPC_SetSRAMOperateVoltage(SPC0, &cfg);
+}
+
+static int frdm_mcxn236_init(void)
+{
+ enable_lpcac();
+
+ power_mode_od();
+
+ /* Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ /* FRO OSC setup - begin, enable the FRO for safety switching */
+
+ /* Switch to FRO 12M first to ensure we can change the clock setting */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+ /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
+ FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
+
+ /* Enable FRO HF(48MHz) output */
+ CLOCK_SetupFROHFClocking(48000000U);
+
+ /* Set up PLL0 */
+ const pll_setup_t pll0Setup = {
+ .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
+ SCG_APLLCTRL_SELP(13U),
+ .pllndiv = SCG_APLLNDIV_NDIV(8U),
+ .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+ .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+ .pllRate = 150000000U
+ };
+ /* Configure PLL0 to the desired values */
+ CLOCK_SetPLL0Freq(&pll0Setup);
+ /* PLL0 Monitor is disabled */
+ CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
+
+ /* Switch MAIN_CLK to PLL0 */
+ CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
+
+ /* Set AHBCLKDIV divider to value 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
+ CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
+ CLOCK_EnableClock(kCLOCK_Gpio5);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
+ CLOCK_AttachClk(kPLL0_to_CTIMER0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
+ CLOCK_AttachClk(kPLL0_to_CTIMER1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
+ CLOCK_AttachClk(kPLL0_to_CTIMER2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
+ CLOCK_AttachClk(kPLL0_to_CTIMER3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
+ CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
+ CLOCK_AttachClk(kPLL0_to_CTIMER4);
+#endif
+
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+
+ return 0;
+}
+
+SYS_INIT(frdm_mcxn236_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/frdm_mcxn236/board.cmake b/boards/nxp/frdm_mcxn236/board.cmake
new file mode 100644
index 0000000..705a644
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/board.cmake
@@ -0,0 +1,25 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXN236" "--reset-after-load")
+board_runner_args(linkserver "--device=MCXN236:FRDM-MCXN236")
+board_runner_args(linkserver "--core=cm33_core0")
+board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXNxxx_S.cfx")
+board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000")
+# Linkserver v1.4.85 and earlier do not include the secure regions in the
+# MCXN236 memory map, so we add them here
+board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
+ \"size\":\"0x00040000\",\"type\":\"RAM\"\}")
+# Define region for peripherals
+board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
+ \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
+
+# Pyocd support added with the NXP.MCXN236_DFP.17.0.0.pack CMSIS Pack
+board_runner_args(pyocd "--target=mcxn236")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/frdm_mcxn236/board.yml b/boards/nxp/frdm_mcxn236/board.yml
new file mode 100644
index 0000000..0bd2d39
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: frdm_mcxn236
+ vendor: nxp
+ socs:
+ - name: mcxn236
diff --git a/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp b/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp
new file mode 100644
index 0000000..8e7516c
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/doc/frdm_mcxn236.webp
Binary files differ
diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst
new file mode 100644
index 0000000..0793d68
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/doc/index.rst
@@ -0,0 +1,211 @@
+.. _frdm_mcxn236:
+
+NXP FRDM-MCXN236
+################
+
+Overview
+********
+
+FRDM-MCXN236 are compact and scalable development boards for rapid prototyping of
+MCX N23X MCUs. They offer industry standard headers for easy access to the
+MCUs I/Os, integrated open-standard serial interfaces, external flash memory and
+an on-board MCU-Link debugger. MCX N Series are high-performance, low-power
+microcontrollers with intelligent peripherals and accelerators providing multi-tasking
+capabilities and performance efficiency.
+
+.. image:: frdm_mcxn236.webp
+ :align: center
+ :alt: FRDM-MCXN236
+
+Hardware
+********
+
+- MCX-N236 Arm Cortex-M33 microcontroller running at 150 MHz
+- 1MB dual-bank on chip Flash
+- 352 KB RAM
+- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors
+- 8x LP Flexcomms each supporting SPI, I2C, UART
+- 2x FlexCAN with FD, 2x I3Cs, 2x SAI
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS
+
+For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see:
+
+- `MCX-N236 SoC Website`_
+- `MCX-N236 Datasheet`_
+- `MCX-N236 Reference Manual`_
+- `FRDM-MCXN236 Website`_
+- `FRDM-MCXN236 User Guide`_
+- `FRDM-MCXN236 Board User Manual`_
+- `FRDM-MCXN236 Schematics`_
+
+Supported Features
+==================
+
+The FRDM-MCXN236 board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
+| CLOCK | on-chip | clock_control |
++-----------+------------+-------------------------------------+
+| FLASH | on-chip | soc flash |
++-----------+------------+-------------------------------------+
+| WATCHDOG | on-chip | watchdog |
++-----------+------------+-------------------------------------+
+
+Targets available
+==================
+
+The default configuration file
+:zephyr_file:`boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig`
+
+Other hardware features are not currently supported by the port.
+
+Connections and IOs
+===================
+
+The MCX-N236 SoC has 6 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name | Function | Usage |
++============+=================+============================+
+| P0_PIO1_8 | UART | UART RX |
++------------+-----------------+----------------------------+
+| P1_PIO1_9 | UART | UART TX |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-N236 SoC is configured to use PLL0 running at 150MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXN236 SoC has 8 FLEXCOMM interfaces for serial communication.
+Flexcomm 4 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``DFU mode`` to program the firmware,
+short jumper JP5.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``DFU mode``
+by shortening the jumper JP5.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J12) of the board. Additionally, the jumper JP7 must
+be shortened.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+ west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J10, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: frdm_mcxn236
+ :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+ *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+ Hello World! frdm_mcxn236/mcxn236
+
+Debugging
+=========
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: frdm_mcxn236/mcxn236
+ :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+ *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+ Hello World! frdm_mcxn236/mcxn236
+
+.. _MCX-N236 SoC Website:
+ https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X
+
+.. _MCX-N236 Datasheet:
+ https://www.nxp.com/docs/en/data-sheet/MCXN23x.pdf
+
+.. _MCX-N236 Reference Manual:
+ https://www.nxp.com/docs/en/reference-manual/MCXN23xRM.pdf
+
+.. _FRDM-MCXN236 Website:
+ https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-n23x-mcus:FRDM-MCXN236
+
+.. _FRDM-MCXN236 User Guide:
+ https://www.nxp.com/document/guide/getting-started-with-frdm-mcxn236:GS-FRDM-MCXN236
+
+.. _FRDM-MCXN236 Board User Manual:
+ https://www.nxp.com/docs/en/user-manual/UM12041.pdf
+
+.. _FRDM-MCXN236 Schematics:
+ https://www.nxp.com/webapp/Download?colCode=SPF-90828
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi
new file mode 100644
index 0000000..7e587aa
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXN236VDF-pinctrl.h>
+
+&pinctrl {
+ pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
+ group0 {
+ pinmux = <FC2_P2_PIO4_2>,
+ <FC2_P3_PIO4_3>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ };
+ };
+
+ pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
+ group0 {
+ pinmux = <FC2_P0_PIO4_0>,
+ <FC2_P1_PIO4_1>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ bias-pull-up;
+ drive-open-drain;
+ };
+ };
+
+ pinmux_flexcomm3_lpspi: pinmux_flexcomm3_lpspi {
+ group0 {
+ pinmux = <FC3_P0_PIO1_0>,
+ <FC3_P1_PIO1_1>,
+ <FC3_P2_PIO1_2>,
+ <FC3_P3_PIO1_3>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ };
+ };
+
+ pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
+ group0 {
+ pinmux = <FC4_P0_PIO1_8>,
+ <FC4_P1_PIO1_9>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ };
+ };
+
+ pinmux_flexcomm5_lpi2c: pinmux_flexcomm5_lpi2c {
+ group0 {
+ pinmux = <FC5_P0_PIO1_16>,
+ <FC5_P1_PIO1_17>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ bias-pull-up;
+ drive-open-drain;
+ };
+ };
+
+ pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
+ group0 {
+ pinmux = <PWM1_A0_PIO3_12>,
+ <PWM1_B0_PIO2_7>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ };
+ };
+
+ pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
+ group0 {
+ pinmux = <PWM1_A1_PIO3_14>,
+ <PWM1_B1_PIO3_15>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ };
+ };
+
+ pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
+ group0 {
+ pinmux = <PWM1_A2_PIO3_16>,
+ <PWM1_B2_PIO3_17>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ };
+ };
+
+};
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts
new file mode 100644
index 0000000..6b2f7bd
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxn23x.dtsi>
+#include "frdm_mcxn236.dtsi"
+
+/ {
+ model = "NXP FRDM_N236 board";
+ compatible = "nxp,mcxn236", "nxp,mcx";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash;
+ zephyr,flash-controller = &fmu;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,console = &flexcomm4_lpuart4;
+ zephyr,shell-uart = &flexcomm4_lpuart4;
+ };
+
+ aliases{
+ watchdog0 = &wwdt0;
+ pwm-0 = &flexpwm1_pwm0;
+ };
+};
+
+&sram0 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(192)>;
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&green_led {
+ status = "okay";
+};
+
+&red_led {
+ status = "okay";
+};
+
+&user_button_2 {
+ status = "okay";
+};
+
+&edma0 {
+ status = "okay";
+};
+
+&flexcomm2 {
+ status = "okay";
+};
+
+/*
+ * LPFLEXCOMM supports UART and I2C on the same instance, enable this for
+ * LFLEXCOMM2
+ */
+&flexcomm2_lpuart2 {
+ status = "okay";
+};
+
+&flexcomm2_lpi2c2 {
+ status = "okay";
+};
+
+&flexcomm3 {
+ status = "okay";
+};
+
+&flexcomm3_lpspi3 {
+ status = "okay";
+};
+
+&flexcomm4 {
+ status = "okay";
+};
+
+&flexcomm4_lpuart4 {
+ status = "okay";
+};
+
+&flexcomm5 {
+ status = "okay";
+};
+
+&flexcomm5_lpi2c5 {
+ status = "okay";
+};
+
+&wwdt0 {
+ status = "okay";
+};
+
+&flexpwm1_pwm0 {
+ status = "okay";
+};
+
+&ctimer0 {
+ status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi
new file mode 100644
index 0000000..a108bd2
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "frdm_mcxn236-pinctrl.dtsi"
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ aliases{
+ led0 = &red_led;
+ led1 = &green_led;
+ led2 = &blue_led;
+ sw0 = &user_button_2;
+ sw1 = &user_button_3;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ green_led: led_1 {
+ gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ label = "Green LED";
+ };
+ blue_led: led_2 {
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ label = "Blue LED";
+ };
+ red_led: led_3 {
+ gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ label = "Red LED";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button_2: button_0 {
+ label = "User SW2";
+ gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ zephyr,code = <INPUT_KEY_WAKEUP>;
+ };
+ user_button_3: button_1 {
+ label = "User SW3";
+ gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+&flexcomm2_lpuart2 {
+ current-speed = <115200>;
+ pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
+ pinctrl-names = "default";
+};
+
+&flexcomm2_lpi2c2 {
+ pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
+ pinctrl-names = "default";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&flexcomm3_lpspi3 {
+ pinctrl-0 = <&pinmux_flexcomm3_lpspi>;
+ pinctrl-names = "default";
+};
+
+&flexcomm4_lpuart4 {
+ current-speed = <115200>;
+ pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
+ pinctrl-names = "default";
+};
+
+&flexcomm5_lpi2c5 {
+ pinctrl-0 = <&pinmux_flexcomm5_lpi2c>;
+ pinctrl-names = "default";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+/*
+ * MCXN236 board uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer {
+ status = "disabled";
+};
+
+&systick {
+ status = "okay";
+};
+
+&flash {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 DT_SIZE_K(64)>;
+ };
+ /* Note slot 0 has one additional sector,
+ * this is intended for use with the swap move algorithm
+ */
+ slot0_partition: partition@10000 {
+ label = "image-0";
+ reg = <0x00010000 DT_SIZE_K(480)>;
+ };
+ slot1_partition: partition@80000 {
+ label = "image-1";
+ reg = <0x0088000 DT_SIZE_K(472)>;
+ };
+ };
+};
+
+&flexpwm1_pwm0 {
+ pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
+ pinctrl-names = "default";
+};
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml
new file mode 100644
index 0000000..ea8cdb1
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml
@@ -0,0 +1,25 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxn236
+name: NXP FRDM MCXN236
+type: mcu
+arch: arm
+ram: 256
+flash: 1024
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+supported:
+ - dma
+ - gpio
+ - spi
+ - i2c
+ - watchdog
+ - pwm
+ - counter
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig
new file mode 100644
index 0000000..41ce437
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig
@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c
index ab41600..a98c236 100644
--- a/boards/nxp/frdm_mcxn947/board.c
+++ b/boards/nxp/frdm_mcxn947/board.c
@@ -299,8 +299,28 @@
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr0), okay)
+
+/*
+ * Clock Select Decides what input source the lptmr will clock from
+ *
+ * 0 <- 12MHz FRO
+ * 1 <- 16K FRO
+ * 2 <- 32K OSC
+ * 3 <- Output from the OSC_SYS
+ */
+#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x0
+ CLOCK_SetupClockCtrl(kCLOCK_FRO12MHZ_ENA);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1
CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys);
-#endif
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x2
+ CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVsys);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3
+ /* Value here should not exceed 25MHZ when using lptmr */
+ CLOCK_SetupExtClocking(MHZ(24));
+ CLOCK_SetupClockCtrl(kCLOCK_CLKIN_ENA_FM_USBH_LPT);
+#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */
+
+#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr0), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio0), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u);
diff --git a/boards/nxp/frdm_rw612/board.cmake b/boards/nxp/frdm_rw612/board.cmake
index c7b1d7d..26f7241 100644
--- a/boards/nxp/frdm_rw612/board.cmake
+++ b/boards/nxp/frdm_rw612/board.cmake
@@ -3,7 +3,7 @@
board_runner_args(jlink "--device=RW612" "--reset-after-load")
-board_runner_args(linkserver "--device=RW612:RDRW612")
+board_runner_args(linkserver "--device=RW612:FRDM-RW612")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
diff --git a/boards/nxp/imx93_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt
index 9881313..218a060 100644
--- a/boards/nxp/imx93_evk/CMakeLists.txt
+++ b/boards/nxp/imx93_evk/CMakeLists.txt
@@ -1 +1,4 @@
# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/imx93_evk/Kconfig b/boards/nxp/imx93_evk/Kconfig
new file mode 100644
index 0000000..78598d2
--- /dev/null
+++ b/boards/nxp/imx93_evk/Kconfig
@@ -0,0 +1,16 @@
+# i.MX 93 EVK board configuration
+
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMX93_EVK_EXP_SEL_INIT
+ bool "Configure i.MX 93 EVK board mux control during init"
+ default n
+
+config BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO
+ int "i.MX 93 EVK board mux control init priority"
+ default 60
+
+module = BOARD_MIMX93_EVK
+module-str = Board Control
+source "subsys/logging/Kconfig.template.log_config"
diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig
index 560c053..a2aeac0 100644
--- a/boards/nxp/imx93_evk/Kconfig.defconfig
+++ b/boards/nxp/imx93_evk/Kconfig.defconfig
@@ -5,6 +5,20 @@
if BOARD_IMX93_EVK_MIMX9352_A55
+if BOARD_MIMX93_EVK_EXP_SEL_INIT
+
+# Enable I2C, MFD, MFD_APD5585 and GPIO_ADP5585
+config GPIO
+ default y
+
+config MFD_ADP5585_INIT_PRIORITY
+ default 55
+
+config GPIO_ADP5585_INIT_PRIORITY
+ default 56
+
+endif # BOARD_MIMX93_EVK_EXP_SEL_INIT
+
if NETWORKING
config NET_L2_ETHERNET
diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk
index 0115518..412da58 100644
--- a/boards/nxp/imx93_evk/Kconfig.imx93_evk
+++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk
@@ -3,4 +3,5 @@
config BOARD_IMX93_EVK
select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55
- select SOC_PART_NUMBER_MIMX9352CVUXK
+ select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33
+ select SOC_PART_NUMBER_MIMX9352DVVXM
diff --git a/boards/nxp/imx93_evk/board.c b/boards/nxp/imx93_evk/board.c
new file mode 100644
index 0000000..169b689
--- /dev/null
+++ b/boards/nxp/imx93_evk/board.c
@@ -0,0 +1,56 @@
+/**
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+LOG_MODULE_REGISTER(board_control, CONFIG_BOARD_MIMX93_EVK_LOG_LEVEL);
+
+#if DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT)
+
+#define BOARD_EXP_SEL_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(imx93evk_exp_sel)
+
+#define BOARD_EXP_SEL_MUX_A (0U)
+#define BOARD_EXP_SEL_MUX_B (1U)
+
+static int board_init_exp_sel(void)
+{
+ int rc = 0;
+ const struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(BOARD_EXP_SEL_NODE, mux_gpios);
+ uint32_t pin_state = DT_ENUM_IDX(BOARD_EXP_SEL_NODE, mux);
+
+ if (!gpio_is_ready_dt(&mux)) {
+ LOG_ERR("EXP_SEL Pin port is not ready");
+ return -ENODEV;
+ }
+
+#if defined(CONFIG_CAN)
+ if (pin_state != BOARD_EXP_SEL_MUX_A) {
+ LOG_WRN("CAN is enabled, EXP_SEL overrides to A");
+ pin_state = BOARD_EXP_SEL_MUX_A;
+ }
+#endif /* CONFIG_CAN */
+
+ rc = gpio_pin_configure_dt(&mux, pin_state);
+ if (rc) {
+ LOG_ERR("Write EXP_SEL Pin error %d", rc);
+ return rc;
+ }
+ LOG_INF("EXP_SEL mux %c with priority %d", pin_state ? 'B' : 'A',
+ CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO);
+
+ return 0;
+}
+
+SYS_INIT(board_init_exp_sel, POST_KERNEL, CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO);
+
+#endif
+/*
+ * DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && \
+ * IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT)
+ */
diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst
index dd08869..6e6d453 100644
--- a/boards/nxp/imx93_evk/doc/index.rst
+++ b/boards/nxp/imx93_evk/doc/index.rst
@@ -1,7 +1,7 @@
.. _imx93_evk:
-NXP i.MX93 EVK (Cortex-A55)
-############################
+NXP i.MX93 EVK
+##############
Overview
********
@@ -71,6 +71,25 @@
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
+The Zephyr imx93_evk board Cortex-M33 configuration supports the following
+hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | interrupt controller |
++-----------+------------+-------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+-------------------------------------+
+| CLOCK | on-chip | clock_control |
++-----------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | GPIO |
++-----------+------------+-------------------------------------+
+
Devices
========
System Clock
@@ -78,15 +97,45 @@
This board configuration uses a system clock frequency of 24 MHz.
Cortex-A55 Core runs up to 1.7 GHz.
+Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
-CPU's UART4.
+CPU's UART2 for A55 core and M33 core.
-Programming and Debugging
-*************************
+Board MUX Control
+-----------------
+
+This board configuration uses a series of digital multiplexers to switch between
+different board functions. The multiplexers are controlled by a GPIO signal called
+``EXP_SEL`` from onboard GPIO expander ADP5585. It can be configured to select
+function set "A" or "B" by dts configuration if board control module is enabled.
+The following dts node is defined:
+
+.. code-block:: dts
+
+ board_exp_sel: board-exp-sel {
+ compatible = "imx93evk-exp-sel";
+ mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>;
+ mux = "A";
+ };
+
+Following steps are required to configure the ``EXP_SEL`` signal:
+
+1. Enable Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT``.
+2. Select ``mux="A";`` or ``mux="B";`` in ``&board_exp_sel`` devicetree node.
+
+Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT`` is enabled if a board
+function that requires configuring the mux is enabled. The MUX option is
+automatically selected if certain board function is enabled, and takes precedence
+over dts config. For instance, if ``CONFIG_CAN`` is enabled, MUX A is selected
+even if ``mux="B";`` is configured in dts, and an warning would be reported in
+the log.
+
+Programming and Debugging (A55)
+*******************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
@@ -116,7 +165,7 @@
:goals: run
This will build an image with the synchronization sample app, boot it and
-display the following ram console output:
+display the following console output:
.. code-block:: console
@@ -126,6 +175,45 @@
thread_a: Hello World from cpu 0 on mimx93_evk_a55!
thread_b: Hello World from cpu 0 on mimx93_evk_a55!
+Programming and Debugging (M33)
+*******************************
+
+Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
+plug the SD card into the board. Power it up and stop the u-boot execution at
+prompt.
+
+Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core:
+
+.. code-block:: console
+
+ load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/synchronization
+ :host-os: unix
+ :board: imx93_evk/mimx9352/m33
+ :goals: run
+
+This will build an image with the synchronization sample app, boot it and
+display the following console output:
+
+.. code-block:: console
+
+ *** Booting Zephyr OS build v3.7.0-684-g71a7d05ba60a ***
+ thread_a: Hello World from cpu 0 on imx93_evk!
+ thread_b: Hello World from cpu 0 on imx93_evk!
+ thread_a: Hello World from cpu 0 on imx93_evk!
+ thread_b: Hello World from cpu 0 on imx93_evk!
+
+To make a container image flash.bin with ``zephyr.bin`` for SD/eMMC programming and booting
+from BootROM. Refer to user manual of i.MX93 `MCUX SDK release`_.
+
+.. _MCUX SDK release:
+ https://mcuxpresso.nxp.com/
+
References
==========
diff --git a/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml b/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml
new file mode 100644
index 0000000..4f30d12
--- /dev/null
+++ b/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml
@@ -0,0 +1,25 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ The i.MX 93 EVK boards has a series of MUXes that selects between 2 pin
+ functions. They are controlled by EXP_SEL signal from gpio_exp0, an
+ ADP5585 GPIO expander.
+
+compatible: "imx93evk-exp-sel"
+
+include: base.yaml
+
+properties:
+ mux-gpios:
+ type: phandle-array
+ required: true
+ description: Pin used to select the MUX
+
+ mux:
+ type: string
+ required: true
+ enum:
+ - "A"
+ - "B"
+ description: MUX choice
diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts
index 99d1628..48740a2 100644
--- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts
+++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts
@@ -64,6 +64,12 @@
gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
};
};
+
+ board_exp_sel: board-exp-sel {
+ compatible = "imx93evk-exp-sel";
+ mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>;
+ mux = "A";
+ };
};
&enet {
@@ -115,7 +121,7 @@
};
&lpi2c2 {
- status = "disabled";
+ status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c2_default>;
pinctrl-names = "default";
@@ -123,7 +129,7 @@
mfd0:adp5585@34 {
compatible = "adi,adp5585";
reg = <0x34>;
- status = "disabled";
+ status = "okay";
gpio_exp0: adp5585_gpio {
compatible = "adi,adp5585-gpio";
@@ -131,19 +137,12 @@
#gpio-cells = <2>;
ngpios = <13>;
gpio-reserved-ranges = <5 3>;
+ status = "okay";
/*
* This device has non-contiguous gpio range:
* GPIO Pin R0~R4 are gpio0~4
* GPIO Pin C0~C4 are gpio8~12
*/
-
- gpiohog_exp_sel: exp-sel-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- line-name = "exp_sel";
- output-low;
- };
- status = "disabled";
};
};
};
diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts
new file mode 100644
index 0000000..5c75e10
--- /dev/null
+++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx93_m33.dtsi>
+#include "imx93_evk-pinctrl.dtsi"
+
+/ {
+ model = "NXP i.MX93 EVK board";
+ compatible = "nxp,imx93_evk";
+
+ chosen {
+ /* TCM */
+ zephyr,flash = &itcm;
+ zephyr,sram = &dtcm;
+
+ zephyr,console = &lpuart2;
+ zephyr,shell-uart = &lpuart2;
+ };
+
+ aliases {
+ led0 = &led_r;
+ led1 = &led_g;
+ sw0 = &btn_1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led_r: led_r {
+ label = "LED_R";
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ };
+ led_g: led_g {
+ label = "LED_G";
+ gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ };
+ led_b: led_b {
+ label = "LED_B";
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ btn_1: btn_1{
+ label = "BTN1";
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ };
+
+ btn_2: btn_2{
+ label = "BTN2";
+ gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&lpuart2 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart2_default>;
+ pinctrl-names = "default";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml
new file mode 100644
index 0000000..b450925
--- /dev/null
+++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml
@@ -0,0 +1,16 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: imx93_evk/mimx9352/m33
+name: NXP i.MX93 EVK M33
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - cross-compile
+ram: 128
+flash: 128
+supported:
+ - gpio
+ - uart
+vendor: nxp
diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig
new file mode 100644
index 0000000..028b1fc
--- /dev/null
+++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig
@@ -0,0 +1,10 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CLOCK_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+CONFIG_XIP=y
diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi
index 27b025a..4ff94aa 100644
--- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi
+++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi
@@ -43,11 +43,11 @@
};
};
- /* Conflicts with lpspi1 pin routing. SDA: J17 pin 3, SCL: J17 pin 6 */
+ /* LPI2C3 SDA: J33 pin 6, LPI2C3 SCL: J33 pin 5 */
pinmux_lpi2c3: pinmux_lpi2c3 {
group0 {
- pinmux = <&iomuxc_gpio_sd_b0_00_lpi2c3_scl>,
- <&iomuxc_gpio_sd_b0_01_lpi2c3_sda>;
+ pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>,
+ <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts
index 9b0be26..e506ce1 100644
--- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts
+++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts
@@ -18,6 +18,7 @@
led0 = &green_led;
sw0 = &user_button;
pwm-0 = &flexpwm1_pwm3;
+ accel0 = &fxls8974;
};
chosen {
@@ -198,10 +199,24 @@
pinctrl-names = "default";
};
-/* Leave LPI2C3 disabled by default, since it conflicts with LPSPI1 pins */
-&lpi2c3 {
+lpi2c3: &lpi2c3 {
pinctrl-0 = <&pinmux_lpi2c3>;
pinctrl-names = "default";
+ status = "okay";
+
+ fxls8974: fxls8974@18 {
+ compatible = "nxp,fxls8974";
+ reg = <0x18>;
+ status = "okay";
+
+ /* Two zero ohm resistors (R115 and R122) isolate sensor
+ * interrupt gpios from the soc and are unpopulated by default.
+ * Note that if you populate them, they conflict with JTAG_TDO and
+ * ethernet PHY interrupt signals.
+ * int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ * int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ */
+ };
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
index 3408781..d4743f1 100644
--- a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
@@ -31,15 +31,6 @@
default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK
default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK
-if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
- default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
-endchoice
-
-endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
if NETWORKING
config NET_L2_ETHERNET
diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
index a54b1b8..3dcd484 100644
--- a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
@@ -34,15 +34,6 @@
endif # DISK_DRIVERS
-if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
- default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
-endchoice
-
-endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
if NETWORKING
config NET_L2_ETHERNET
diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt
new file mode 100644
index 0000000..8c36a25
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt
@@ -0,0 +1,27 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_NXP_IMXRT_BOOT_HEADER)
+ zephyr_library()
+ if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33)
+ OR (DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7)))
+ message(WARNING "It appears you are using the board definition for "
+ "the MIMXRT1180-EVK, but targeting a custom board. You may need to "
+ "update your flash configuration or device configuration data blocks")
+ endif()
+ set(RT1180_BOARD_DIR
+ "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180")
+ if(CONFIG_BOOT_FLEXSPI_NOR)
+ # Include flash configuration block for RT1180 EVK from NXP's HAL.
+ # This configuration block may need modification if another flash chip is
+ # used on your custom board.
+ zephyr_compile_definitions(XIP_EXTERNAL_FLASH=1)
+ zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)
+ zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c)
+ zephyr_library_include_directories(${RT1180_BOARD_DIR}/xip)
+ zephyr_library_include_directories(${RT1180_BOARD_DIR})
+ endif()
+endif()
diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig
new file mode 100644
index 0000000..d514be1
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig
@@ -0,0 +1,8 @@
+# MIMXRT1180-EVK board
+
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MIMXRT1180_EVK
+
+endif # BOARD_MIMXRT1180_EVK
diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk b/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk
new file mode 100644
index 0000000..4d44fd9
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk
@@ -0,0 +1,10 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MIMXRT1180_EVK
+ select SOC_PART_NUMBER_MIMXRT1189CVM8B
+ select SOC_MIMXRT1189_CM33 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33
+ select SOC_MIMXRT1189_CM7 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7
diff --git a/boards/nxp/mimxrt1180_evk/board.cmake b/boards/nxp/mimxrt1180_evk/board.cmake
new file mode 100644
index 0000000..36f76d8
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/board.cmake
@@ -0,0 +1,23 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(RT1180_BOARD_DIR
+"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180")
+# Note1: Suggest developers use Secure Provisioning Tool(SPT) to download RT1180 image
+# SPT can be downloaded on NXP web: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING
+# Details about the usage of SPT on MIMXRT1180-EVK board can be referred on chapter 7 of getting start with Mcuxpresso SDK for MIMXRT1180-EVK doc in SDK package.
+if(CONFIG_SOC_MIMXRT1189_CM33)
+board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK")
+board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm33.jlinkscript")
+elseif(CONFIG_SOC_MIMXRT1189_CM7)
+# Note: Only support run cm7 image when debugging due to default boot core on board is cm33 core
+board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK")
+board_runner_args(linkserver "--core=cm7")
+board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
diff --git a/boards/nxp/mimxrt1180_evk/board.yml b/boards/nxp/mimxrt1180_evk/board.yml
new file mode 100644
index 0000000..0153cf4
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: mimxrt1180_evk
+ vendor: nxp
+ socs:
+ - name: mimxrt1189
diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst
new file mode 100644
index 0000000..b0828c8
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/doc/index.rst
@@ -0,0 +1,253 @@
+.. _mimxrt1180_evk:
+
+NXP MIMXRT1180-EVK
+##################
+
+Overview
+********
+
+The dual core i.MX RT1180 runs on the Cortex-M33 core at 240 MHz and on the
+Cortex-M7 at 792 MHz. The i.MX RT1180 MCU offers support over a wide
+temperature range and is qualified for consumer, industrial and automotive
+markets.
+
+.. image:: mimxrt1180_evk.webp
+ :align: center
+ :alt: MIMXRT1180-EVK
+
+Hardware
+********
+
+- MIMXRT1189CVM8B MCU
+
+ - 240MHz Cortex-M33 & 792Mhz Cortex-M7
+ - 1.5MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
+
+- Memory
+
+ - 512 Mbit SDRAM
+ - 128 Mbit QSPI Flash
+ - 512 Mbit HYPER RAM
+ - TF socket for SD card
+
+- Ethernet
+
+ - 1000 Mbit/s Ethernet PHY
+
+- USB
+
+ - 2* USB 2.0 OTG connector
+
+- Audio
+
+ - 3.5 mm audio stereo headphone jack
+ - Board-mounted microphone
+ - Left and right speaker out connectors
+
+- Power
+
+ - 5 V DC jack
+
+- Debug
+
+ - JTAG 20-pin connector
+ - MCU-Link with DAPLink
+
+- Expansion port
+
+ - Arduino interface
+
+- CAN bus connector
+
+For more information about the MIMXRT1180 SoC and MIMXRT1180-EVK board, see
+these references:
+
+- `i.MX RT1180 Website`_
+- `MIMXRT1180-EVK Website`_
+
+External Memory
+===============
+
+This platform has the following external memories:
+
++--------------------+------------+-------------------------------------+
+| Device | Controller | Status |
++====================+============+=====================================+
+| W9825G6KH | SEMC | Enabled via device configuration |
+| | | data block, which sets up SEMC at |
+| | | boot time |
++--------------------+------------+-------------------------------------+
+| W25Q128JWSIQ | FLEXSPI | Enabled via flash configurationn |
+| | | block, which sets up FLEXSPI at |
+| | | boot time. |
++--------------------+------------+-------------------------------------+
+
+Supported Features
+==================
+
+The mimxrt1180_evk board configuration supports the hardware features listed
+below. For additional features not yet supported, please also refer to the
+:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family.
+NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+Zephyr. Therefore, the mimxrt1170_evk board may have additional features
+already supported, which can also be re-used on this mimxrt1180_evk board:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| COUNTER | on-chip | counter |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`
+
+Other hardware features are not currently supported by the port.
+
+
+Connections and I/Os
+====================
+
+The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
+
++---------------+-----------------+---------------------------+
+| Name | Function | Usage |
++===============+=================+===========================+
+| GPIO_AON_04 | GPIO | SW8 |
++---------------+-----------------+---------------------------+
+| GPIO_AD_27 | GPIO | LED |
++---------------+-----------------+---------------------------+
+| GPIO_AON_08 | LPUART1_TX | UART Console |
++---------------+-----------------+---------------------------+
+| GPIO_AON_09 | LPUART1_RX | UART Console |
++---------------+-----------------+---------------------------+
+
+System Clock
+============
+
+The MIMXRT1180 SoC is configured to use SysTick as the system clock source,
+running at 240MHz. When targeting the M7 core, SysTick will also be used,
+running at 792MHz
+
+Serial Port
+===========
+
+The MIMXRT1180 SoC has 12 UARTs. One is configured for the console and the
+remaining are not used.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`,
+however the :ref:`pyocd-debug-host-tools` do not yet support programming the
+external flashes on this board so you must reconfigure the board for one of the
+following debug probes instead.
+
+.. _Using J-Link RT1180:
+
+Using J-Link
+------------
+
+Please ensure used JLINK above V7.94g and jumper JP5 installed if using
+external jlink plus on J37 as debugger.
+
+When debugging cm33 core, need to ensure the SW5 on "0100" mode.
+When debugging cm7 core, need to ensure the SW5 on "0001" mode.
+(Only support run cm7 image when debugging due to default boot core on board is cm33 core)
+
+Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
+path.
+
+There are two options: the onboard debug circuit can be updated with Segger
+J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the
+EVK.
+
+
+Using Linkserver
+----------------
+
+Please ensure used linkserver above V1.5.30 and jumper JP5 uninstalled.
+
+When debugging cm33 core, need to ensure the SW5 on "0100" mode.
+When debugging cm7 core, need to ensure the SW5 on "0001" mode.
+(Only support run cm7 image when debugging due to default boot core on board is cm33 core)
+
+Configuring a Console
+=====================
+
+Regardless of your choice in debug probe, we will use the MCU-Link
+microcontroller as a usb-to-serial adapter for the serial console. Check that
+jumpers JP5 and JP3 are **on** (they are on by default when boards ship from
+the factory) to connect UART signals to the MCU-Link microcontroller.
+
+Connect a USB cable from your PC to J53.
+
+Use the following settings with your serial terminal of choice (minicom, putty,
+etc.):
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :ref:`hello_world` application on cm33 core.
+
+Before power on the board, make sure SW5 is set to 0100b
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: mimxrt1180_evk/mimxrt1189/cm33
+ :goals: flash
+
+Power off the board, then power on the board and
+open a serial terminal, reset the board (press the SW3 button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+ ***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
+ Hello World! mimxrt1180_evk/mimxrt1189/cm33
+
+Debugging
+=========
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: mimxrt1180_evk/mimxrt1189/cm33
+ :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+ ***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
+ Hello World! mimxrt1180_evk/mimxrt1189/cm33
+
+.. _MIMXRT1180-EVK Website:
+ https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1180-evaluation-kit:MIMXRT1180-EVK
+
+.. _i.MX RT1180 Website:
+ https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1180-crossover-mcu-with-tsn-switch-and-edgelock:i.MX-RT1180
diff --git a/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp b/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp
new file mode 100644
index 0000000..6039fa3
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/doc/mimxrt1180_evk.webp
Binary files differ
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
new file mode 100644
index 0000000..5b2eba4
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <nxp/nxp_imx/rt/mimxrt1189cvm8b-pinctrl.dtsi>
+
+&pinctrl {
+ pinmux_lpspi3: pinmux_lpspi3 {
+ group0 {
+ pinmux = <&iomuxc_gpio_sd_b1_00_lpspi3_pcs0>,
+ <&iomuxc_gpio_sd_b1_01_lpspi3_sck>,
+ <&iomuxc_gpio_sd_b1_02_lpspi3_sout>,
+ <&iomuxc_gpio_sd_b1_03_lpspi3_sin>;
+ drive-strength = "high";
+ slew-rate = "fast";
+ };
+ };
+
+ pinmux_lpuart1: pinmux_lpuart1 {
+ group0 {
+ pinmux = <&iomuxc_aon_gpio_aon_09_lpuart1_rxd>,
+ <&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
+ drive-strength = "high";
+ slew-rate = "fast";
+ };
+ };
+
+ pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
+ group0 {
+ pinmux = <&iomuxc_aon_gpio_aon_09_gpio1_io09>;
+ drive-strength = "high";
+ bias-pull-up;
+ slew-rate = "fast";
+ };
+ group1 {
+ pinmux = <&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
+ drive-strength = "high";
+ slew-rate = "fast";
+ };
+ };
+
+ /* Connected to FXLS8974 */
+ pinmux_lpi2c2: pinmux_lpi2c2 {
+ group0 {
+ pinmux = <&iomuxc_aon_gpio_aon_15_lpi2c2_sda>,
+ <&iomuxc_aon_gpio_aon_16_lpi2c2_scl>;
+ drive-strength = "normal";
+ drive-open-drain;
+ slew-rate = "fast";
+ input-enable;
+ };
+ };
+
+ pinmux_lpi2c3: pinmux_lpi2c3 {
+ group0 {
+ pinmux = <&iomuxc_gpio_ad_18_lpi2c3_scl>,
+ <&iomuxc_gpio_ad_19_lpi2c3_sda>;
+ drive-strength = "normal";
+ drive-open-drain;
+ slew-rate = "fast";
+ input-enable;
+ };
+ };
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
new file mode 100644
index 0000000..a6b51df
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "mimxrt1180_evk-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ aliases {
+ led0 = &green_led;
+ sw0 = &user_button;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ green_led: led-1 {
+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ label = "User LED D6";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button: button-1 {
+ label = "User SW8";
+ gpios = <&gpio1 4 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+&lpuart1 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&pinmux_lpuart1>;
+ pinctrl-1 = <&pinmux_lpuart1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&user_button {
+ status = "okay";
+};
+
+&green_led {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&flexspi1 {
+ status = "okay";
+ ahb-prefetch;
+ ahb-read-addr-opt;
+ rx-clock-source = <1>;
+ w25q128jw: w25q128jw@0 {
+ compatible = "nxp,imx-flexspi-nor";
+ size = <134217728>;
+ reg = <0>;
+ spi-max-frequency = <133000000>;
+ status = "okay";
+ jedec-id = [ef 80 18];
+ erase-block-size = <4096>;
+ write-block-size = <1>;
+ };
+};
+
+&lpi2c2 {
+ pinctrl-0 = <&pinmux_lpi2c2>;
+ pinctrl-names = "default";
+};
+
+&lpi2c3 {
+ pinctrl-0 = <&pinmux_lpi2c3>;
+ pinctrl-names = "default";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
new file mode 100644
index 0000000..e721ddd
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt118x_cm33.dtsi>
+#include "mimxrt1180_evk.dtsi"
+
+/ {
+ model = "NXP MIMXRT1180-EVK board";
+ compatible = "nxp,mimxrt1189";
+
+ chosen {
+ zephyr,sram = &dtcm;
+ zephyr,flash-controller = &w25q128jw;
+ zephyr,flash = &w25q128jw;
+ zephyr,console = &lpuart1;
+ zephyr,shell-uart = &lpuart1;
+ };
+};
+
+&lpuart1 {
+ status = "okay";
+ current-speed = <115200>;
+};
+
+
+&systick {
+ status = "okay";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
new file mode 100644
index 0000000..aeffa09
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1180_evk/mimxrt1189/cm33
+name: NXP MIMXRT1180-EVK CM33
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+ram: 128
+flash: 16384
+supported:
+ - gpio
+ - uart
+ - i2c
+vendor: nxp
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig
new file mode 100644
index 0000000..d5b8dbd
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig
@@ -0,0 +1,15 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
new file mode 100644
index 0000000..8c75060
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt118x_cm7.dtsi>
+#include "mimxrt1180_evk.dtsi"
+
+/ {
+ model = "NXP MIMXRT1180-EVK board";
+ compatible = "nxp,mimxrt1189";
+
+ chosen {
+ zephyr,sram = &dtcm;
+ zephyr,flash-controller = &w25q128jw;
+ zephyr,flash = &itcm;
+ zephyr,console = &lpuart1;
+ zephyr,shell-uart = &lpuart1;
+ };
+};
+
+&lpuart1 {
+ status = "okay";
+ current-speed = <115200>;
+};
+
+
+&systick {
+ status = "okay";
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
new file mode 100644
index 0000000..d6b8ad5
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1180_evk/mimxrt1189/cm7
+name: NXP MIMXRT1180-EVK CM7
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+ram: 256
+flash: 256
+supported:
+ - gpio
+ - uart
+ - i2c
+vendor: nxp
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig
new file mode 100644
index 0000000..89be0a5
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig
@@ -0,0 +1,14 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y
+CONFIG_NXP_IMXRT_BOOT_HEADER=n
diff --git a/boards/nxp/mimxrt595_evk/Kconfig.defconfig b/boards/nxp/mimxrt595_evk/Kconfig.defconfig
index 9813fb6..f5061f5 100644
--- a/boards/nxp/mimxrt595_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt595_evk/Kconfig.defconfig
@@ -8,10 +8,6 @@
config FLASH_MCUX_FLEXSPI_MX25UM51345G
default y if FLASH
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
-endchoice
-
config FXOS8700_DRDY_INT1
default y
depends on FXOS8700_TRIGGER
diff --git a/boards/nxp/mimxrt685_evk/Kconfig.defconfig b/boards/nxp/mimxrt685_evk/Kconfig.defconfig
index 02a6918..6802302 100644
--- a/boards/nxp/mimxrt685_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt685_evk/Kconfig.defconfig
@@ -18,10 +18,6 @@
default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR
endchoice
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
-endchoice
-
config FXOS8700_DRDY_INT1
default y
depends on FXOS8700_TRIGGER
diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
index 7260dd4..c671e64 100644
--- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
+++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
@@ -282,3 +282,8 @@
status = "okay";
wakeup-source;
};
+
+&pin1 {
+ status = "okay";
+ wakeup-level = "low";
+};
diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig
index f54f3ca..2b5dffc 100644
--- a/boards/nxp/s32z2xxdc2/Kconfig.defconfig
+++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig
@@ -23,4 +23,11 @@
endif # SHELL
+if NETWORKING
+
+config NET_L2_ETHERNET
+ default y if !NET_LOOPBACK && !NET_TEST
+
+endif # NETWORKING
+
endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
index 18660e2..4efafdf 100644
--- a/boards/nxp/s32z2xxdc2/doc/index.rst
+++ b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -53,6 +53,8 @@
+-----------+------------+-------------------------------------+
| CANEXCEL | on-chip | can |
+-----------+------------+-------------------------------------+
+| FLEXCAN | on-chip | can |
++-----------+------------+-------------------------------------+
Other hardware features are not currently supported by the port.
@@ -106,7 +108,7 @@
System Clock
============
-The Cortex-R52 cores are configured to run at 800 MHz.
+The Cortex-R52 cores are configured to run at 1 GHz.
Serial Port
===========
@@ -129,15 +131,24 @@
cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to
configure the Ethernet network controller.
-Controller Area Network (CAN)
-=============================
+Controller Area Network
+=======================
-Currently, the CANXL transceiver is not populated in this board. So CAN transceiver
-connection is required for running external traffic. We can use any CAN transceiver,
-which supports CAN 2.0 and CAN FD protocol.
+CANEXCEL
+--------
-CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is
-not supported as this feature is not available on NXP S32 CANXL HAL.
+CANEXCEL supports CAN Classic (CAN 2.0) and CAN FD modes. Remote transmission
+request is not supported.
+
+Note that this board does not currently come with CAN transceivers installed for
+the CANEXCEL ports. To facilitate external traffic, you will need to add a CAN
+transceiver. Any transceiver pin-compatible with CAN 2.0 and CAN FD protocols
+can be used.
+
+FlexCAN
+-------
+
+FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes.
Programming and Debugging
*************************
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
index 1270676..6cd0c45 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
@@ -31,13 +31,22 @@
status = "okay";
};
-&can0 {
- pinctrl-0 = <&can0_default>;
+&canxl0 {
+ pinctrl-0 = <&canxl0_default>;
pinctrl-names = "default";
- status = "okay";
};
-&can1 {
- pinctrl-0 = <&can1_default>;
+&canxl1 {
+ pinctrl-0 = <&canxl1_default>;
+ pinctrl-names = "default";
+};
+
+&flexcan0 {
+ pinctrl-0 = <&flexcan0_default>;
+ pinctrl-names = "default";
+};
+
+&flexcan1 {
+ pinctrl-0 = <&flexcan1_default>;
pinctrl-names = "default";
};
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
index 482b43d..291e92e 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
@@ -64,7 +64,7 @@
};
};
- can0_default: can0_default {
+ canxl0_default: canxl0_default {
group1 {
pinmux = <PN2_CANXL_0_RX>;
input-enable;
@@ -75,7 +75,7 @@
};
};
- can1_default: can1_default {
+ canxl1_default: canxl1_default {
group1 {
pinmux = <PM11_CANXL_1_RX>;
input-enable;
@@ -85,4 +85,26 @@
output-enable;
};
};
+
+ flexcan0_default: flexcan0_default {
+ group1 {
+ pinmux = <PA5_CAN_0_RX>;
+ input-enable;
+ };
+ group2 {
+ pinmux = <PA4_CAN_0_TX>;
+ output-enable;
+ };
+ };
+
+ flexcan1_default: flexcan1_default {
+ group1 {
+ pinmux = <PB7_CAN_1_RX>;
+ input-enable;
+ };
+ group2 {
+ pinmux = <PB6_CAN_1_TX>;
+ output-enable;
+ };
+ };
};
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
index 37c2f6b..3db4df0 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
@@ -14,7 +14,7 @@
chosen {
zephyr,sram = &sram0;
- zephyr,canbus = &can0;
+ zephyr,canbus = &canxl0;
};
aliases {
@@ -31,3 +31,7 @@
mboxes = <&mru0 0>;
mbox-names = "rx";
};
+
+&canxl0 {
+ status = "okay";
+};
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
index ce5d162..4aadfbe 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
@@ -16,7 +16,7 @@
zephyr,sram = &sram1;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
- zephyr,canbus = &can0;
+ zephyr,canbus = &flexcan0;
};
aliases {
@@ -33,3 +33,7 @@
mboxes = <&mru4 0>;
mbox-names = "rx";
};
+
+&flexcan0 {
+ status = "okay";
+};
diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig
index 4bf5b36..7c62ad7 100644
--- a/boards/nxp/vmu_rt1170/Kconfig.defconfig
+++ b/boards/nxp/vmu_rt1170/Kconfig.defconfig
@@ -12,15 +12,6 @@
endif # DISK_DRIVERS
-if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
- default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
-endchoice
-
-endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
if NETWORKING
config NET_L2_ETHERNET
diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig
index dda9be1..e326963 100644
--- a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig
+++ b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/others/icev_wireless/Kconfig.defconfig b/boards/others/icev_wireless/Kconfig.defconfig
index d2c6cca..b7c8209 100644
--- a/boards/others/icev_wireless/Kconfig.defconfig
+++ b/boards/others/icev_wireless/Kconfig.defconfig
@@ -3,7 +3,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/panasonic/pan1783/Kconfig.defconfig b/boards/panasonic/pan1783/Kconfig.defconfig
index 6c70d44..9f69518 100644
--- a/boards/panasonic/pan1783/Kconfig.defconfig
+++ b/boards/panasonic/pan1783/Kconfig.defconfig
@@ -3,9 +3,6 @@
# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH
# SPDX-License-Identifier: Apache-2.0
-config MBOX_NRFX_IPC
- default MBOX
-
if SOC_NRF5340_CPUAPP_QKAA
config BT_HCI_IPC
diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst
index 4611248..b9643a3 100644
--- a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst
+++ b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst
@@ -47,8 +47,7 @@
:height: 405px
:alt: PhyBOARD Pollux
-More information about the board can be found at the
-`PHYTEC website`_.
+More information about the board can be found at the `PHYTEC website`_.
Supported Features
==================
@@ -56,32 +55,30 @@
The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware
features:
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+=====================================+
-| NVIC | on-chip | nested vector interrupt controller |
-+-----------+------------+-------------------------------------+
-| SYSTICK | on-chip | systick |
-+-----------+------------+-------------------------------------+
-| CLOCK | on-chip | clock_control |
-+-----------+------------+-------------------------------------+
-| PINMUX | on-chip | pinmux |
-+-----------+------------+-------------------------------------+
-| UART | on-chip | serial port-polling; |
-| | | serial port-interrupt |
-+-----------+------------+-------------------------------------+
-| GPIO | on-chip | GPIO output |
-| | | GPIO input |
-+-----------+------------+-------------------------------------+
++-----------+------------+------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+------------------------------------+
+| CLOCK | on-chip | clock_control |
++-----------+------------+------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+------------------------------------+
+| GPIO | on-chip | GPIO output |
+| | | GPIO input |
++-----------+------------+------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`.
It's recommended to disable peripherals used by the M7-Core on the host running
-on the Linux host.
-
-Other hardware features are not currently supported with Zephyr on the
-M7-Core.
+on the Linux host. Other hardware features are not currently supported with
+Zephyr on the M7-Core.
Connections and IOs
===================
@@ -91,32 +88,27 @@
UART
----
-+---------------+-----------------+-----------------------------------+
-| Board Name | SoM Name | Usage |
-+===============+=================+===================================+
-| Debug USB(A53)| UART1 | UART Debug Console via USB |
-+---------------+-----------------+-----------------------------------+
-| Wo WiFi Module| UART3 | UART to WiFi/BLE Module |
-+---------------+-----------------+-----------------------------------+
-| Debug USB(M4) | UART4 | UART Debug Console via USB |
-+---------------+-----------------+-----------------------------------+
++-----------------+----------+----------------------------+
+| Board Name | SoM Name | Usage |
++=================+==========+============================+
+| Debug USB (A53) | UART1 | UART Debug Console via USB |
++-----------------+----------+----------------------------+
+| Wo WiFi Module | UART3 | UART to WiFi/BLE Module |
++-----------------+----------+----------------------------+
+| Debug USB (M7) | UART4 | UART Debug Console via USB |
++-----------------+----------+----------------------------+
.. note::
- Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with
- Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the
- X6 Connector.
+ The WiFi/BLE Module connected to UART3 isn't working with Zephyr yet. UART3
+ can also be used through pin 31(RX) and 33(TX) of connector X6.
GPIO
----
The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree
-created by NXP. You can find it here:
-
-:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`.
-
-The Pinout of the PhyBOARD Polis can be found here:
-
-`PHYTEC website`_
+created by NXP and can be found at
+:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the PhyBOARD Polis
+can be found at the `PHYTEC website`_.
Programming and Debugging
*************************
@@ -124,25 +116,23 @@
The i.MX8MP does not have a separate flash for the M7-Core. Because of this
the A53-Core has to load the program for the M7-Core to the right memory
address, set the PC and start the processor.
-This can only by done with u-boot at the moment. We are working on our BSP to
-enable remoteproc support.
The M7 can use up to 3 different RAMs (currently, only two configurations are
supported: ITCM and DDR). These are the memory mapping for A53 and M7:
-+------------+-------------------------+------------------------+-----------------------+----------------------+
-| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
-+============+=========================+========================+=======================+======================+
-| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
-+------------+-------------------------+------------------------+-----------------------+----------------------+
-| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
-+------------+-------------------------+------------------------+-----------------------+----------------------+
-| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
-+------------+-------------------------+------------------------+-----------------------+----------------------+
-| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
-+------------+-------------------------+------------------------+-----------------------+----------------------+
-| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
-+------------+-------------------------+------------------------+-----------------------+----------------------+
++---------+-----------------------+------------------------+-----------------------+-------+
+| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
++=========+=======================+========================+=======================+=======+
+| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
++---------+-----------------------+------------------------+-----------------------+-------+
+| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
++---------+-----------------------+------------------------+-----------------------+-------+
+| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
++---------+-----------------------+------------------------+-----------------------+-------+
+| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
++---------+-----------------------+------------------------+-----------------------+-------+
+| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
++---------+-----------------------+------------------------+-----------------------+-------+
For more information about memory mapping see the
`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3)
@@ -151,20 +141,17 @@
configuration is done in the devicetree and the defconfig / the config of your
program.
-**By default Zephyr will use the TCM memory region.** You can configure it like
-this for the DDR region:
-
-In the devicetree overwrite the following nodes like this:
+**By default Zephyr will use the TCM memory region.** You can configure it
+to use the DDR region. In the devicetree overwrite you can select both options.
.. code-block:: DTS
chosen {
/* TCM */
zephyr,flash = &itcm;
- zephyr,sram = &dtcm;
+ zephyr,sram = &dtcm;
};
-change it to
.. code-block:: DTS
@@ -175,55 +162,45 @@
};
-In your prj.conf overwrite the configuration like this for the **DDR** memory
-region:
+And in the prj.conf the configuration to the **DDR** memory region:
.. code-block:: cfg
CONFIG_CODE_DDR=y
CONFIG_CODE_ITCM=n
+Connecting to the Serial Console
+================================
-Starting the M7-Core via U-Boot
+A serial console for both the application CPU and the Cortex M7 coprocessor are
+available via the onboard dual USB-to-UART converter. If you use Linux, create a
+udev rule (as ``root``) to fix a permission issue when not using root for
+flashing.
+
+.. code-block:: console
+
+ # echo 'ATTR{idProduct}=="0a70", ATTR{idVendor}=="10c4", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-usb-uart.rules
+
+Reload the rules and replug the device.
+
+.. code-block:: console
+
+ $ sudo udevadm control --reload-rules
+
+Finally, unplug and plug the board again for the rules to take effect.
+
+Connect to the console via your favorite terminal program. For example:
+
+.. code-block:: console
+
+ $ minicom -D /dev/ttyUSB1 -b 115200
+
+Flashing and Debugging via JTAG
===============================
-Load the compiled zephyr.bin to memory address 0x4800000.
-This should output something like this:
-
-.. code-block:: console
-
- u-boot=> tftp 0x48000000 192.168.3.10:zephyr.bin
- Using ethernet@30be0000 device
- TFTP from server 192.168.3.10; our IP address is 192.168.3.11
- Filename 'zephyr.bin'.
- Load address: 0x48000000
- Loading: ##
- 2 KiB/s
- done
- Bytes transferred = 27240 (6a68 hex)
-
-Because it's not possible to load directly to the TCM memory area you have to
-copy the binaries. The last argument given is the size of the file in bytes,
-you can copy it from the output of the last command.
-
-.. code-block:: console
-
- u-boot=> cp.b 0x48000000 0x7e0000 27240
-
-And finaly starting the M7-Core at the right memory address:
-
-.. code-block:: console
-
- u-boot=> bootaux 0x7e0000
- ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905...
-
-Debugging
-=========
-
-The PhyBOARD Polis can be debugged using a JTAG Debugger.
-The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's
-``PEB-EVAL-01`` Shield, which can be directly connected to the JLink.
-You can find the JLink Software package here: `JLink Software`_
+The PhyBOARD-Pollux can be debugged using a JTAG or SWD debug adapter. A Segger
+JLink can be connected to the compatible JTAG connector on Phytec's
+``PEB-EVAL-01`` shield.
.. figure:: img/PEB-EVAL-01.jpg
:alt: PEB-EVAL-01
@@ -231,37 +208,47 @@
PEB-EVAL-01
-To debug efficiently you have to use multiple terminals:
-
-After connecting everything and building with west use this command while in
-the directory of the program you build earlier to start a debug server:
+Before flashing or debugging via a JTAG debug adapter,
+the M7 core has to be switched on:
.. code-block:: console
- host$ west debugserver
+ u-boot=> bootaux 0x7e0000
-West automatically connects via the JLink to the Target and keeps open a
-debug server.
+Here is an example for the :ref:`hello_world` application:
-Use another terminal, start gdb, connect to target and load Zephyr on the
-target:
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: mimx8mp_phyboard_pollux/mimx8ml8/m7
+ :goals: flash
+
+The console should now show the output of the application:
.. code-block:: console
- host$ gdb-multiarch build/zephyr/zephyr.elf -tui
- (gdb) targ rem :2331
- Remote debugging using :2331
- 0x1ffe0008 in _vector_table ()
- (gdb) mon halt
- (gdb) mon reset
- (gdb) c
- Continuing.
+ *** Booting Zephyr OS build v3.7.0 ***
+ Hello World! mimx8mp_phyboard_pollux/mimx8ml8/m7
-The program can be debugged using standard gdb techniques.
+Starting a debug session is similar to flashing:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: mimx8mp_phyboard_pollux/mimx8ml8/m7
+ :goals: debug
+
+Starting the M7-Core from U-Boot and Linux
+==========================================
+
+Loading binaries and starting the M7-Core is supported from Linux via remoteproc
+or from U-boot by directly copying the firmware binary. Please check the
+`phyCORE-i.MX 8M Plus BSP Manual`_ for more information.
References
==========
+- `i.MX 8M Plus Applications Processor Reference Manual`_
+- `phyCORE-i.MX 8M Plus BSP Manual`_
+
.. _PHYTEC website:
https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/
@@ -270,3 +257,6 @@
.. _JLink Software:
https://www.segger.com/downloads/jlink/
+
+.. _phyCORE-i.MX 8M Plus BSP Manual:
+ https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/imx8mp.html
diff --git a/boards/raytac/mdbt53_db_40/Kconfig.defconfig b/boards/raytac/mdbt53_db_40/Kconfig.defconfig
index bb53d3a..dbbe13d 100644
--- a/boards/raytac/mdbt53_db_40/Kconfig.defconfig
+++ b/boards/raytac/mdbt53_db_40/Kconfig.defconfig
@@ -62,12 +62,6 @@
endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS
-config IPM_NRFX
- default IPM
-
-config MBOX_NRFX_IPC
- default MBOX
-
if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET
config BT_CTLR
diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig
index 9573720..b3f4fb7 100644
--- a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig
+++ b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig
@@ -62,12 +62,6 @@
endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
-config IPM_NRFX
- default IPM
-
-config MBOX_NRFX_IPC
- default MBOX
-
if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET
config BT_CTLR
diff --git a/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1 b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1
new file mode 100644
index 0000000..5eaad77
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/Kconfig.ek_ra2a1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA2A1
+ select SOC_R7FA2A1AB3CFM
diff --git a/boards/renesas/ek_ra2a1/board.cmake b/boards/renesas/ek_ra2a1/board.cmake
new file mode 100644
index 0000000..98ad18a
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/board.cmake
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA2A1AB")
+
+board_runner_args(pyocd "--target=r7fa2a1ab")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/renesas/ek_ra2a1/board.yml b/boards/renesas/ek_ra2a1/board.yml
new file mode 100644
index 0000000..82c4988
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra2a1
+ vendor: renesas
+ socs:
+ - name: r7fa2a1ab3cfm
diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst
new file mode 100644
index 0000000..060f162
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/doc/index.rst
@@ -0,0 +1,105 @@
+.. _ek_ra2a1:
+
+RA2A1 Evaluation Kit
+####################
+
+Overview
+********
+
+The EK-RA2A1 is an evaluation kit for Renesas RA2A1 Microcontroller Group.
+
+Renesas RA2A1 Microcontroller Group has following features
+
+- 48MHz, Arm Cortex-M23 core
+- 256kB Code Flash, 8kB Data Flash, 32kB SRAM
+- USB 2.0 Full-Sppeed
+- SCI x 3
+- SPI x 2
+- I2C x 2
+- CAN x 1
+- 16-bit A/D Converter
+- 24-bit Sigma-Delta A/D Converter
+- 12-bit D/A Converter
+- 8-bit D/A Converter x 2
+- High-Speed Analog Comparator
+- Low-Power Analog Comparator
+- OPAMP x 3
+- Temperature Sensor
+- General PWM Timer 32-bit x 1
+- General PWM Timer 16-bit x 6
+- Low Power Asynchronous General-Purpose Timer x 2
+- Watchdog Timer
+- 49 Input/Output pins
+
+Hardware
+********
+
+EK-RA2A1 has following features.
+
+- Native pin access through 4x 40-pin male headers
+- MCU current measurement points
+- SEGGER J-Link on-board programmer and debugger
+- Two Digilent Pmod (SPI and UART)
+- User LED
+- Mechanical user button
+- Capacitive user button
+
+Supported Features
+==================
+
+The Renesas EK-RA2A1 board configuration supports the following
+hardware features:
+
++-----------+------------+-------------------------------+
+| Interface | Controller | Driver/components |
++===========+============+===============================+
+| PINCTRL | on-chip | pinctrl |
++-----------+------------+-------------------------------+
+| CLOCK | on-chip | clock_control |
++-----------+------------+-------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------+
+| UART | on-chip | uart |
++-----------+------------+-------------------------------+
+
+The default configuration can be found in
+:zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig`
+
+
+Programming and debugging
+*************************
+
+Building & Flashing
+===================
+
+You can build and flash an application with onboard J-Link debug adapter.
+:ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for building and flashing the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/basic/blinky
+ :board: ek_ra2a1
+ :goals: build flash
+
+
+Debugging
+=========
+
+Debugging also can be done with onboard J-Link debug adapter.
+The following command is debugging the :zephyr:code-sample:`blinky` application.
+Also, see the instructions specific to the debug server that you use.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/basic/blinky
+ :board: ek_ra2a1
+ :maybe-skip-config:
+ :goals: debug
+
+
+References
+**********
+
+.. EK-RA2A1 Web site:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
new file mode 100644
index 0000000..cded3e5
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 3, 1)>;
+ };
+ group2 {
+ /* tx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 3, 2)>;
+ drive-strength = "medium";
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts
new file mode 100644
index 0000000..eb14660
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra2/r7fa2a1ab3cfm.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+#include "ek_ra2a1-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA2A1";
+ compatible = "renesas,ra2a1", "renesas,ra2";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport2 5 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(12)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&ioport2 {
+ status = "okay";
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml
new file mode 100644
index 0000000..7800082
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml
@@ -0,0 +1,12 @@
+identifier: ek_ra2a1
+name: Renesas EK-RA2A1
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
+ - uart
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
new file mode 100644
index 0000000..6058aa5
--- /dev/null
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2 b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2
new file mode 100644
index 0000000..06f6e75
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/Kconfig.ek_ra6e2
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6E2
+ select SOC_R7FA6E2BB3CFM
diff --git a/boards/renesas/ek_ra6e2/board.cmake b/boards/renesas/ek_ra6e2/board.cmake
new file mode 100644
index 0000000..368e102
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6E2BB")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6e2/board.yml b/boards/renesas/ek_ra6e2/board.yml
new file mode 100644
index 0000000..972476c
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6e2
+ vendor: renesas
+ socs:
+ - name: r7fa6e2bb3cfm
diff --git a/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp
new file mode 100644
index 0000000..56ebb4c
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst
new file mode 100644
index 0000000..aad21a9
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/doc/index.rst
@@ -0,0 +1,165 @@
+.. _ek_ra6e2:
+
+RA6E2 Evaluation Kit
+####################
+
+Overview
+********
+
+The EK-RA6E2, an Evaluation Kit for RA6E2 MCU Group, enables users to
+seamlessly evaluate the features of the RA6E2 MCU group and develop
+embedded systems applications using Flexible Software Package (FSP)
+and e2 studio IDE. The users can use rich on-board features along with
+their choice of popular ecosystems add-ons to bring their big ideas to life
+
+The key features of the EK-RA6E2 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package
+- 256 kB Code Flash, 40 kB SRAM
+- Native pin access through 2 x 14-pin and 1 x 40-pin male headers
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 20.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6E2 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+- Three 5V input sources
+
+ - USB (Debug, Full Speed)
+ - External power supply (using surface mount clamp test points and J31 through holes)
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (SWD)
+ - Debug out (JTAG, SWD)
+
+- User LEDs and buttons
+
+ - Three User LEDs (red, blue, green)
+ - Power LED (white) indicating availability of regulated power
+ - Debug LED (yellow) indicating the debug connection
+ - Two User buttons
+ - One Reset button
+
+- Five most popular ecosystems expansions
+
+ - Two Seeed Grove system (I3C/Analog) connectors
+ - One SparkFun Qwiic connector
+ - Two Digilent Pmod (SPI and UART) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- 16 Mb (128 Mb) External Quad-SPI Flash
+- CAN (3-pin header)
+
+.. figure:: ek-ra6e2-board.webp
+ :align: center
+ :alt: RA6E2 Evaluation Kit
+
+ EK-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
+
+.. figure:: ra6e2-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6E2 MCU group feature
+
+ RA6E2 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6E2 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6e2`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6E2 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6E2BB
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6E2 Website`_
+- `RA6E2 MCU group Website`_
+
+.. _EK-RA6E2 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6e2-evaluation-kit-ra6e2-mcu-group
+
+.. _RA6E2 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller
+
+.. _EK-RA6E2 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/ek-ra6e2-v1-users-manual
+
+.. _RA6E2 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp
new file mode 100644
index 0000000..7eeb1bc
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
new file mode 100644
index 0000000..851d854
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
+ <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
new file mode 100644
index 0000000..682aafc
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6e2bb3cfm.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6e2-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6E2";
+ compatible = "renesas,ra6e2", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport1 13 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport1 {
+ status = "okay";
+};
+
+&ioport2 {
+ status = "okay";
+};
+
+&ioport4 {
+ status = "okay";
+};
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "application";
+ reg = <0x00000000 DT_SIZE_K(128)>;
+ };
+
+ storage_partition: partition@20000 {
+ label = "storage";
+ reg = <0x20000 DT_SIZE_K(128)>;
+ };
+ };
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(20)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <10 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml
new file mode 100644
index 0000000..dcb71bd
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml
@@ -0,0 +1,11 @@
+identifier: ek_ra6e2
+name: Renesas EK-RA6E2
+type: mcu
+arch: arm
+ram: 40
+flash: 256
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
new file mode 100644
index 0000000..92bb425
--- /dev/null
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1
new file mode 100644
index 0000000..c21e240
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M1
+ select SOC_R7FA6M1AD3CFP
diff --git a/boards/renesas/ek_ra6m1/board.cmake b/boards/renesas/ek_ra6m1/board.cmake
new file mode 100644
index 0000000..1a34ff9
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M1AD")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m1/board.yml b/boards/renesas/ek_ra6m1/board.yml
new file mode 100644
index 0000000..db68eb8
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6m1
+ vendor: renesas
+ socs:
+ - name: r7fa6m1ad3cfp
diff --git a/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp
new file mode 100644
index 0000000..438d21d
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst
new file mode 100644
index 0000000..955c87a
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/doc/index.rst
@@ -0,0 +1,161 @@
+.. _ek_ra6m1:
+
+RA6M1 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M1 microcontroller is the entry point to the Renesas RA6 product
+series for applications that require a high-performance Arm® Cortex®-M4 core at
+a very attractive price point. The RA6M1 is built on a highly efficient 40nm process
+and is supported by an open and flexible ecosystem concept—the Flexible Software
+Package (FSP), built on FreeRTOS—and is expandable to use other RTOSes and middleware.
+The RA6M1 is suitable for IoT applications requiring security, large embedded RAM and
+low power consumption.
+
+The key features of the EK-RA6M1 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+- R7FA6M1AD3CFP
+- 100-pin LQFP package
+- 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
+- 256 KB SRAM
+- 512 KB code flash memory
+- 8 KB data flash memory
+
+**Connectivity**
+- A Device USB connector for the Main MCU
+- S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the
+RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external
+debuggers and programmers.
+- Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for
+rapid prototyping
+- Pin headers for access to power and signals for the Main MCU
+
+**Multiple clock sources**
+- Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
+clocks
+- Additional low-precision clocks are available internal to the Main MCU
+
+**General purpose I/O ports**
+- One jumper to allow measuring of Main MCU current
+- Copper jumpers on PCB bottom side for configuration and access to selected MCU signals
+**Operating voltage**
+- External 5 V input through the Debug USB connector supplies the on-board power regulator to power
+logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
+locations on the board.
+- A two-color board status LED indicating availability of regulated power and connection status of the J-Link
+interface.
+- A red User LED, controlled by the Main MCU firmware
+- A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer,
+all of which are controlled by the Main MCU firmware
+- MCU reset push-button switch
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- USB Full Speed Debug and Device (micro-AB connector)
+
+.. figure:: ek-ra6m1-board.webp
+ :align: center
+ :alt: RA6M1 Evaluation Kit
+
+ EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_
+
+.. figure:: ra6m1-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6M1 MCU group feature
+
+ RA6M1 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M1 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m1`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M1AD
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M1 Website`_
+- `RA6M1 MCU group Website`_
+
+.. _EK-RA6M1 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group
+
+.. _RA6M1 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m1-32-bit-microcontrollers-120mhz-optimized-entry-point-ra6-series
+
+.. _EK-RA6M1 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/ek-ra6m1-v1-users-manual
+
+.. _RA6M1 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/renesas-ra6m1-group-users-manual-hardware?r=1054156
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp
new file mode 100644
index 0000000..2f9511b
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
new file mode 100644
index 0000000..56fa3e2
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci8_default: sci8_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_8, 1, 5)>,
+ <RA_PSEL(RA_PSEL_SCI_8, 1, 4)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
new file mode 100644
index 0000000..013c7d4
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m1ad3cfp.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m1-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6M1";
+ compatible = "renesas,ra6m1", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart8;
+ zephyr,shell-uart = &uart8;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci8 {
+ pinctrl-0 = <&sci8_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart8: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport1 {
+ status = "okay";
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(20)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <20 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
new file mode 100644
index 0000000..92e8d56
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
@@ -0,0 +1,12 @@
+identifier: ek_ra6m1
+name: Renesas EK-RA6M1
+type: mcu
+arch: arm
+ram: 256
+flash: 512
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
+ - uart
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
new file mode 100644
index 0000000..00adc77
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2 b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2
new file mode 100644
index 0000000..106137b
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/Kconfig.ek_ra6m2
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M2
+ select SOC_R7FA6M2AF3CFB
diff --git a/boards/renesas/ek_ra6m2/board.cmake b/boards/renesas/ek_ra6m2/board.cmake
new file mode 100644
index 0000000..4ebea56
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M2AF")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m2/board.yml b/boards/renesas/ek_ra6m2/board.yml
new file mode 100644
index 0000000..325b160
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6m2
+ vendor: renesas
+ socs:
+ - name: r7fa6m2af3cfb
diff --git a/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp
new file mode 100644
index 0000000..e58a8a1
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst
new file mode 100644
index 0000000..a3cb9f0
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/doc/index.rst
@@ -0,0 +1,155 @@
+.. _ek_ra6m2:
+
+RA6M2 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M2 microcontroller is the entry point to the Renesas RA6 product series
+for applications that require a high-performance Arm® Cortex®-M4 core at a very attractive
+price point. The RA6M2 is suitable for IoT applications requiring security, large embedded
+RAM and low power consumption.
+
+The key features of the EK-RA6M2 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 120MHz Arm Cortex-M4 based RA6M2 MCU in 144 pins, LQFP package
+- Native pin access through 4 x 40-pin male headers
+- MCU and USB current measurement points for precision current consumption measurement
+- Multiple clock sources - RA6M2 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 24.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6M2 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed device
+- 5V input through USB debug
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (SWD and JTAG)
+ - Debug out (SWD)
+
+- User LEDs and buttons
+
+ - One User LEDs
+ - One User buttons
+ - One Reset button
+
+- Three most popular ecosystems expansions
+
+ - Two Digilent Pmod (SPI and UART) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+
+.. figure:: ek-ra6m2-board.webp
+ :align: center
+ :alt: RA6M2 Evaluation Kit
+
+ EK-RA6M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_
+
+.. figure:: ra6m2-block-diagram.webp
+ :width: 871px
+ :align: center
+ :alt: RA6M2 MCU group feature
+
+ RA6M2 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M2 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m2`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M2 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M2 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M2AD
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M2 Website`_
+- `RA6M2 MCU group Website`_
+
+.. _EK-RA6M2 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m2-evaluation-kit-ra6m2-mcu-group
+
+.. _RA6M2 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m2-32-bit-microcontrollers-120mhz-medium-size-memory-integration-and-ethernet
+
+.. _EK-RA6M2 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/ek-ra6m2-v1-users-manual-0
+
+.. _RA6M2 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/renesas-ra6m2-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp
new file mode 100644
index 0000000..5b72563
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
new file mode 100644
index 0000000..69d920e
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci7_default: sci7_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_7, 4, 1)>,
+ <RA_PSEL(RA_PSEL_SCI_7, 4, 2)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
new file mode 100644
index 0000000..7840735
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m2af3cfb.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m2-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6M2";
+ compatible = "renesas,ra6m2", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart7;
+ zephyr,shell-uart = &uart7;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci7 {
+ pinctrl-0 = <&sci7_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart7: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport1 {
+ status = "okay";
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(12)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <20 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml
new file mode 100644
index 0000000..3f3c049
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml
@@ -0,0 +1,11 @@
+identifier: ek_ra6m2
+name: Renesas EK-RA6M2
+type: mcu
+arch: arm
+ram: 384
+flash: 1024
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
new file mode 100644
index 0000000..00adc77
--- /dev/null
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3 b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3
new file mode 100644
index 0000000..eb3f551
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/Kconfig.ek_ra6m3
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M3
+ select SOC_R7FA6M3AH3CFC
diff --git a/boards/renesas/ek_ra6m3/board.cmake b/boards/renesas/ek_ra6m3/board.cmake
new file mode 100644
index 0000000..a395cf7
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M3AH")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m3/board.yml b/boards/renesas/ek_ra6m3/board.yml
new file mode 100644
index 0000000..2bf115b
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6m3
+ vendor: renesas
+ socs:
+ - name: r7fa6m3ah3cfc
diff --git a/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp
new file mode 100644
index 0000000..9aa1acf
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst
new file mode 100644
index 0000000..bb468d9
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/doc/index.rst
@@ -0,0 +1,163 @@
+.. _ek_ra6m3:
+
+RA6M3 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M3 group uses the high-performance Arm® Cortex®-M4 core and
+offers a TFT controller with 2D accelerator and JPEG decoder. The RA6M3 is
+suitable for IoT applications requiring TFT, Ethernet, security, large
+embedded RAM, and USB High Speed (HS).
+
+The key features of the EK-RA6M3 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package
+- Native pin access through 4 x 40-pin male headers
+- MCU and USB current measurement points for precision current consumption measurement
+- Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 24.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6M3 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro AB connector)
+- Four 5V input sources
+
+ - USB (Debug, Full Speed, High Speed)
+ - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (ETM, SWD and JTAG)
+ - Debug out (SWD)
+
+- User LEDs and buttons
+
+ - Three User LEDs (red, blue, green)
+ - Power LED (white) indicating availability of regulated power
+ - Debug LED (yellow) indicating the debug connection
+ - Two User buttons
+ - One Reset button
+
+- Four most popular ecosystems expansions
+
+ - Two Seeed Grove system (I2C) connectors
+ - Two Digilent Pmod (SPI and UART) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- Ethernet (RJ45 RMII interface)
+- USB High Speed Host and Device (micro-AB connector)
+- 32 Mb (256 Mb) External Quad-SPI Flash
+
+.. figure:: ek-ra6m3-board.webp
+ :align: center
+ :alt: RA6M3 Evaluation Kit
+
+ EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_
+
+.. figure:: ra6m3-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6M3 MCU group feature
+
+ RA6M3 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M3 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m3`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M3 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M3AH
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M3 Website`_
+- `RA6M3 MCU group Website`_
+
+.. _EK-RA6M3 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m3-evaluation-kit-ra6m3-mcu-group
+
+.. _RA6M3 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m3-32-bit-microcontrollers-120mhz-usb-high-speed-ethernet-and-tft-controller
+
+.. _EK-RA6M3 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/ek-ra6m3-v1-users-manual
+
+.. _RA6M3 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra6m3-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp
new file mode 100644
index 0000000..e95bf93
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
new file mode 100644
index 0000000..56fa3e2
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci8_default: sci8_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_8, 1, 5)>,
+ <RA_PSEL(RA_PSEL_SCI_8, 1, 4)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
new file mode 100644
index 0000000..0cd4de2
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m3ah3cfc.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m3-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6M3";
+ compatible = "renesas,ra6m3", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,console = &uart8;
+ zephyr,shell-uart = &uart8;
+ zephyr,flash = &flash0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport4 3 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport1 0 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&ioport1 {
+ status = "okay";
+};
+
+&ioport4 {
+ status = "okay";
+};
+
+&sci8 {
+ pinctrl-0 = <&sci8_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart8: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(24)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml
new file mode 100644
index 0000000..50cc873
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml
@@ -0,0 +1,11 @@
+identifier: ek_ra6m3
+name: Renesas EK-RA6M3
+type: mcu
+arch: arm
+ram: 640
+flash: 2048
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
new file mode 100644
index 0000000..31c2fa7
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4 b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4
new file mode 100644
index 0000000..28ed45f
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/Kconfig.ek_ra6m4
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M4
+ select SOC_R7FA6M4AF3CFB
diff --git a/boards/renesas/ek_ra6m4/board.cmake b/boards/renesas/ek_ra6m4/board.cmake
new file mode 100644
index 0000000..66f7982
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M4AF")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m4/board.yml b/boards/renesas/ek_ra6m4/board.yml
new file mode 100644
index 0000000..5c7e34f
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6m4
+ vendor: renesas
+ socs:
+ - name: r7fa6m4af3cfb
diff --git a/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp
new file mode 100644
index 0000000..b146b23
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst
new file mode 100644
index 0000000..8254900
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/doc/index.rst
@@ -0,0 +1,168 @@
+.. _ek_ra6m4:
+
+RA6M4 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M4 group uses the high-performance Arm® Cortex®-M33
+core with TrustZone®. Secure element functionality providing better
+performance, unlimited secure key storage, key management, and lower
+BOM cost, as well as the integrated Ethernet MAC with individual DMA
+ensures high data throughput. The RA6M4 is suitable for IoT applications
+requiring Ethernet, future proof security, large embedded RAM, and low
+active power consumption down to 99uA/MHz running the CoreMark®
+algorithm from Flash.
+
+The key features of the EK-RA6M4 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 200MHz Arm Cortex-M33 based RA6M4 MCU in 144 pins, LQFP package
+- Native pin access through 4 x 40-pin male headers
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA6M4 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 24.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6M4 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+- Three 5 V input sources
+
+ - USB (Debug, Full Speed)
+ - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (ETM, SWD and JTAG)
+ - Debug out (SWD)
+
+- User LEDs and buttons
+
+ - Three User LEDs (red, blue, green)
+ - Power LED (white) indicating availability of regulated power
+ - Debug LED (yellow) indicating the debug connection
+ - Two User buttons
+ - One Reset button
+
+- Five most popular ecosystems expansions
+
+ - Two Seeed Grove system (I2C/Analog) connectors
+ - One SparkFun Qwiic connector
+ - Two Digilent Pmod (SPI and UART) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- Ethernet (RJ45 RMII interface)
+- 32 Mb (256 Mb) External Quad-SPI Flash
+- 64 Mb (512 Mb) External Octo-SPI Flash
+
+.. figure:: ek-ra6m4-board.webp
+ :align: center
+ :alt: RA6M4 Evaluation Kit
+
+ EK-RA6M4 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_
+
+.. figure:: ra6m4-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6M4 MCU group feature
+
+ RA6M4 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M4 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m4`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M4 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M4AF
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M4 Website`_
+- `RA6M4 MCU group Website`_
+
+.. _EK-RA6M4 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m4-evaluation-kit-ra6m4-mcu-group
+
+.. _RA6M4 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m4-200mhz-arm-cortex-m33-trustzone-high-integration-ethernet-and-octaspi
+
+.. _EK-RA6M4 - User's Manual:
+ https://www.renesas.com/us/en/document/man/ek-ra6m4-v1-users-manual
+
+.. _RA6M4 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/man/ra6m4-group-user-s-manual-hardware?r=1333976
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp
new file mode 100644
index 0000000..3bf83cf
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
new file mode 100644
index 0000000..851d854
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
+ <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
new file mode 100644
index 0000000..5fcb92a
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m4af3cfb.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m4-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6M4";
+ compatible = "renesas,ra6m4", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport4 15 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport4 4 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport4 {
+ status = "okay";
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(24)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_3>;
+ mul = <25 0>;
+ status = "okay";
+};
+
+&pclka {
+ clk_src = <RA_CLOCK_SOURCE_PLL>;
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml
new file mode 100644
index 0000000..d9488b9
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml
@@ -0,0 +1,11 @@
+identifier: ek_ra6m4
+name: Renesas EK-RA6M4
+type: mcu
+arch: arm
+ram: 256
+flash: 1024
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
new file mode 100644
index 0000000..45a5a73
--- /dev/null
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5 b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5
new file mode 100644
index 0000000..fccd138
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/Kconfig.ek_ra6m5
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M5
+ select SOC_R7FA6M5BH3CFC
diff --git a/boards/renesas/ek_ra6m5/board.cmake b/boards/renesas/ek_ra6m5/board.cmake
new file mode 100644
index 0000000..5aabef8
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M5BH")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m5/board.yml b/boards/renesas/ek_ra6m5/board.yml
new file mode 100644
index 0000000..826e64f
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra6m5
+ vendor: renesas
+ socs:
+ - name: r7fa6m5bh3cfc
diff --git a/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp
new file mode 100644
index 0000000..073a049
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst
new file mode 100644
index 0000000..bc94a15
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/doc/index.rst
@@ -0,0 +1,166 @@
+.. _ek_ra6m5:
+
+RA6M5 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M5 group uses the high-performance Arm® Cortex®-M33 core with
+TrustZone®. The RA6M5 is suitable for IoT applications requiring Ethernet, future
+proof security, large embedded RAM, and low active power consumption down
+to 107uA/MHz running the CoreMark® algorithm from Flash.
+
+The key features of the EK-RA6M5 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 200MHz Arm Cortex-M33 based RA6M5 MCU in 176 pins, LQFP package
+- Native pin access through 4 x 40-pin male headers
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA6M5 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 24.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6M5 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+- Four 5V input sources
+
+ - USB (Debug, Full Speed, High Speed)
+ - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (ETM, SWD and JTAG)
+ - Debug out (SWD)
+
+- User LEDs and buttons
+
+ - Three User LEDs (red, blue, green)
+ - Power LED (white) indicating availability of regulated power
+ - Debug LED (yellow) indicating the debug connection
+ - Two User buttons
+ - One Reset button
+
+- Five most popular ecosystems expansions
+
+ - Two Seeed Grove system (I2C/Analog) connectors
+ - One SparkFun Qwiic connector
+ - Two Digilent Pmod (SPI and UART) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- Ethernet (RJ45 RMII interface)
+- USB High Speed Host and Device (micro-AB connector)
+- 32 Mb (256 Mb) External Quad-SPI Flash
+- 64 Mb (512 Mb) External Octo-SPI Flash
+- CAN (3-pin header)
+
+.. figure:: ek-ra6m5-board.webp
+ :align: center
+ :alt: RA6M5 Evaluation Kit
+
+ EK-RA6M5 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_
+
+.. figure:: ra6m5-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6M5 MCU group feature
+
+ RA6M5 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M5 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m5`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M5 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M5BH
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M5 Website`_
+- `RA6M5 MCU group Website`_
+
+.. _EK-RA6M5 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group
+
+.. _RA6M5 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m5-200mhz-arm-cortex-m33-trustzone-highest-integration-ethernet-and-can-fd
+
+.. _EK-RA6M5 - User's Manual:
+ https://www.renesas.com/us/en/document/man/ek-ra6m5-v1-users-manual
+
+.. _RA6M5 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/man/ra6m5-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp
new file mode 100644
index 0000000..456726a
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
new file mode 100644
index 0000000..851d854
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
+ <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
new file mode 100644
index 0000000..ad84e26
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m5bh3cfc.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m5-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA6M5";
+ compatible = "renesas,ra6m5", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport0 6 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport0 7 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport0 8 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport0 {
+ status = "okay";
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(24)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_3>;
+ mul = <25 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml
new file mode 100644
index 0000000..2f65bfb
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml
@@ -0,0 +1,11 @@
+identifier: ek_ra6m5
+name: Renesas EK-RA6M5
+type: mcu
+arch: arm
+ram: 512
+flash: 2048
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
new file mode 100644
index 0000000..4b5534e
--- /dev/null
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1 b/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1
new file mode 100644
index 0000000..fa18d11
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/Kconfig.ek_ra8d1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA8D1
+ select SOC_R7FA8D1BHECBD
diff --git a/boards/renesas/ek_ra8d1/board.cmake b/boards/renesas/ek_ra8d1/board.cmake
new file mode 100644
index 0000000..ee93597
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA8D1BH")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra8d1/board.yml b/boards/renesas/ek_ra8d1/board.yml
new file mode 100644
index 0000000..9b48ea9
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: ek_ra8d1
+ vendor: renesas
+ socs:
+ - name: r7fa8d1bhecbd
diff --git a/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg b/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg
new file mode 100644
index 0000000..a97d241
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg
Binary files differ
diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst
new file mode 100644
index 0000000..3105c01
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/doc/index.rst
@@ -0,0 +1,168 @@
+.. _ek_ra8d1:
+
+RA8D1 Evaluation Kit
+####################
+
+Overview
+********
+
+The EK-RA8D1 is an Evaluation Kit for Renesas RA8D1 MCU Group which are the industry’s first 32-bit
+graphics-enabled MCUs based on the Arm Cortex-M85 (CM85) core, delivering breakthrough performance
+of over 3000 Coremark points at 480 MHz and superior graphics capabilities that enable high-resolution
+displays and Vision AI applications.
+
+The key features of the EK-RA8D1 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 480MHz Arm Cortex-M85 based RA8D1 MCU in 224 pins, BGA package
+- Native pin acces througgh 2 x 50-pin, and 2 x 40-pin male headers
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA8D1 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 20.000MHz and 32,768 Hz refeence clocks.
+ Additional low precision clocks are avaialbe internal to the RA8D1 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+- Four 5V input sources
+
+ - USB (Debug, Full Speed, High Speed)
+ - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+ - Debug on-board (SWD)
+ - Debug in (ETM, SWD and JTAG)
+ - Debug out (SWD)
+
+- User LEDs and buttons
+
+ - Three User LEDs (red, blue, green)
+ - Power LED (white) indicating availability of regulated power
+ - Debug LED (yellow) indicating the debug connection
+ - Two User buttons
+ - One Reset button
+
+- Five most popular ecosystems expansions
+
+ - Two Seeed Grove system (I2C/I3C) connectors
+ - One SparkFun Qwiic connector
+ - Two Digilent Pmod (SPI, UART and I2C/I3C) connectors
+ - Arduino (Uno R3) connector
+ - MikroElektronika mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- Ethernet (RJ45 RMII interface)
+- USB High Speed Host and Device (micro-AB connector)
+- 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8D1 board)
+- CAN FD (3-pin header)
+
+.. figure:: ek-ra8d1-board.jpg
+ :align: center
+ :alt: RA8D1 Evaluation Kit
+
+ EK-RA8D1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_
+
+.. figure:: ra8d1-block-diagram.png
+ :width: 442px
+ :align: center
+ :alt: RA8D1 MCU group feature
+
+ RA8D1 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detail Hardware feature for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA8D1 board:
+
++--------------+------------+------------------+
+| Interface | Controller | Driver/Component |
++==============+============+==================+
+| GPIO | on-chip | gpio |
++--------------+------------+------------------+
+| MPU | on-chip | arch/arm |
++--------------+------------+------------------+
+| NVIC | on-chip | arch/arm |
++--------------+------------+------------------+
+| UART | on-chip | serial |
++--------------+------------+------------------+
+| CLOCK | on-chip | clock control |
++--------------+------------+------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra8d1`` board configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available.
+To build for EK-RA8M1 user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6
+
+Flashing
+========
+
+Program can be flashed to EK-RA8D1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA8D1BH
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that debug is OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA8D1 Website`_
+- `RA8D1 MCU group Website`_
+
+.. _EK-RA8D1 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8d1-evaluation-kit-ra8d1-mcu-group
+
+.. _RA8D1 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8d1-480-mhz-arm-cortex-m85-based-graphics-microcontroller-helium-and-trustzone
+
+.. _EK-RA8D1 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/ek-ra8d1-v1-user-manual
+
+.. _RA8D1 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png b/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png
new file mode 100644
index 0000000..c473987
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png
Binary files differ
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
new file mode 100644
index 0000000..1604d70
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
+ drive-strength = "medium";
+ };
+ group2 {
+ /* rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
+ };
+ };
+};
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
new file mode 100644
index 0000000..3d5876a
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra8/r7fa8d1bhecbd.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra8d1-pinctrl.dtsi"
+
+/ {
+ model = "Renesas EK-RA8D1";
+ compatible = "renesas,ra8d1", "renesas,ra8";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart9;
+ zephyr,shell-uart = &uart9;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport4 14 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport1 7 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(20)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <96 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(480)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(480)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(480)>;
+ status = "okay";
+};
+
+&sciclk {
+ clk_src = <RA_CLOCK_SOURCE_PLL1P>;
+ clk_div = <RA_SCI_CLOCK_DIV_4>;
+ status = "okay";
+};
+
+&ioport1 {
+ status = "okay";
+};
+
+&ioport4 {
+ status = "okay";
+};
+
+&ioport6 {
+ status = "okay";
+};
+
+&sci0 {
+ /* sci0 and spi0 cannot be enabled together */
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart9: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml
new file mode 100644
index 0000000..2432f8e
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml
@@ -0,0 +1,12 @@
+identifier: ek_ra8d1
+name: Renesas EK-RA8D1
+type: mcu
+arch: arm
+ram: 1024
+flash: 2048
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
+ - uart
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
new file mode 100644
index 0000000..02195f3
--- /dev/null
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+CONFIG_CLOCK_CONTROL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst
index 013839f..b58f513 100644
--- a/boards/renesas/ek_ra8m1/doc/index.rst
+++ b/boards/renesas/ek_ra8m1/doc/index.rst
@@ -98,6 +98,10 @@
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
+| I2C | on-chip | i2c |
++-----------+------------+----------------------+
+| ENTROPY | on-chip | entropy |
++-----------+------------+----------------------+
Other hardware features are currently not supported by the port.
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
index 88f3624..8fc5744 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
@@ -27,4 +27,20 @@
psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
};
};
+
+ iic1_default: iic1_default {
+ group1 {
+ /* SCL1 SDA1*/
+ psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+ drive-strength = "medium";
+ };
+ };
+
+ adc0_default: adc0_default {
+ group1 {
+ /* input */
+ psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
+ renesas,analog-enable;
+ };
+ };
};
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
index 18136ef..ac29d19 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
@@ -7,7 +7,7 @@
#include <renesas/ra/ra8/r7fa8m1ahecbd.dtsi>
#include <dt-bindings/gpio/gpio.h>
-
+#include <zephyr/dt-bindings/adc/adc.h>
#include "ek_ra8m1-pinctrl.dtsi"
/ {
@@ -19,6 +19,7 @@
zephyr,flash = &flash0;
zephyr,console = &uart9;
zephyr,shell-uart = &uart9;
+ zephyr,entropy = &trng;
};
leds {
@@ -144,3 +145,21 @@
};
mikrobus_serial: &uart3 {};
+
+&iic1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <DT_FREQ_M(1)>;
+ pinctrl-0 = <&iic1_default>;
+ pinctrl-names = "default";
+};
+
+&adc0 {
+ status = "okay";
+ pinctrl-0 = <&adc0_default>;
+ pinctrl-names = "default";
+};
+
+&trng {
+ status = "okay";
+};
diff --git a/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1 b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1
new file mode 100644
index 0000000..03c2ffd
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/Kconfig.fpb_ra6e1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FPB_RA6E1
+ select SOC_R7FA6E10F2CFP
diff --git a/boards/renesas/fpb_ra6e1/board.cmake b/boards/renesas/fpb_ra6e1/board.cmake
new file mode 100644
index 0000000..f4e7c16
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6E10F")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/fpb_ra6e1/board.yml b/boards/renesas/fpb_ra6e1/board.yml
new file mode 100644
index 0000000..ed1e0a1
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: fpb_ra6e1
+ vendor: renesas
+ socs:
+ - name: r7fa6e10f2cfp
diff --git a/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp
new file mode 100644
index 0000000..f11bcf1
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp
Binary files differ
diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst
new file mode 100644
index 0000000..17332f0
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/doc/index.rst
@@ -0,0 +1,150 @@
+.. _fpb_ra6e1:
+
+RA6E1 Fast Prototyping Board
+############################
+
+Overview
+********
+
+The Renesas RA6E1 group uses the high-performance Arm® Cortex®-M33 core with
+TrustZone®. The RA6E1 is suitable for entry IoT applications requiring streamlined
+feature and connectivity integration including Ethernet, and unprecedented performance
+with 790.75 CoreMark, which are 3.95CoreMark / Mhz.
+
+The key features of the FPB-RA6E1 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 200MHz Arm Cortex-M33 based RA6E1 MCU in 100 pins, LQFP package
+- Native pin access through 2 x 50-pin male headers (not fitted)
+- MCU current measurement point for precision current consumption measurement
+- Multiple clock sources - Low-precision (~1%) clocks are available internal to
+ the RA MCU. RA MCU oscillator and sub-clock oscillator crystals, providing
+ precision 24.000 MHz (not fitted) and 32,768 Hz reference clocks are also available
+
+**System Control and Ecosystem Access**
+
+- Two 5V input sources
+
+ - USB (Debug, Full Speed, High Speed)
+ - External power supply (using 2-pin header) (not fitted)
+
+- Built-in SEGGER J-Link Emulator On-Board programmer/debugger (SWD)
+
+- User LEDs and buttons
+
+ - Two User LEDs (green)
+ - Power LED (green) (not fitted) indicating availability of regulated power
+ - Debug/power LED (yellow) indicating power and the debug connection
+ - One User button
+ - One Reset button
+
+- Two popular ecosystems expansions
+
+ - Two Digilent PmodTM (SPI, UART) connectors (not fitted)
+ - Arduino (Uno R3) connector
+
+- MCU boot configuration jumper
+
+.. figure:: fpb-ra6e1-board.webp
+ :align: center
+ :alt: RA6E1 Evaluation Kit
+
+ FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_
+
+.. figure:: ra6e1-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6E1 MCU group feature
+
+ RA6E1 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for FPB-RA6E1 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+| FLASH | on-chip | flash |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``fpb_ra6e1`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to FPB-RA6E1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6E10F
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `FPB-RA6E1 Website`_
+- `RA6E1 MCU group Website`_
+
+.. _FPB-RA6E1 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e1-fast-prototyping-board-ra6e1-mcu-group#overview
+
+.. _RA6E1 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e1-200mhz-arm-cortex-m33-entry-line-high-performance-streamlined-connectivity
+
+.. _FPB-RA6E1 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/fpb-ra6e1-users-manual
+
+.. _RA6E1 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra6e1-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp
new file mode 100644
index 0000000..b6f70e6
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
new file mode 100644
index 0000000..3c01cb6
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 1, 1)>,
+ <RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
+ };
+ };
+};
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
new file mode 100644
index 0000000..6f73498
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6e10f2cfp.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "fpb_ra6e1-pinctrl.dtsi"
+
+/ {
+ model = "Renesas FPB-RA6E1";
+ compatible = "renesas,ra6e1", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport4 {
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_HOCO>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "okay";
+};
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "application";
+ reg = <0x00000000 DT_SIZE_K(512)>;
+ };
+
+ storage_partition: partition@80000 {
+ label = "storage";
+ reg = <0x80000 DT_SIZE_K(512)>;
+ };
+ };
+};
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml
new file mode 100644
index 0000000..8942834
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml
@@ -0,0 +1,11 @@
+identifier: fpb_ra6e1
+name: Renesas FPB-RA6E1
+type: mcu
+arch: arm
+ram: 256
+flash: 1024
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
new file mode 100644
index 0000000..fa7ef71
--- /dev/null
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2 b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2
new file mode 100644
index 0000000..d23cc0e
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/Kconfig.fpb_ra6e2
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FPB_RA6E2
+ select SOC_R7FA6E2BB3CFM
diff --git a/boards/renesas/fpb_ra6e2/board.cmake b/boards/renesas/fpb_ra6e2/board.cmake
new file mode 100644
index 0000000..368e102
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6E2BB")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/fpb_ra6e2/board.yml b/boards/renesas/fpb_ra6e2/board.yml
new file mode 100644
index 0000000..0d28094
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: fpb_ra6e2
+ vendor: renesas
+ socs:
+ - name: r7fa6e2bb3cfm
diff --git a/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp
new file mode 100644
index 0000000..705203f
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp
Binary files differ
diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst
new file mode 100644
index 0000000..21acb93
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/doc/index.rst
@@ -0,0 +1,152 @@
+.. _fpb_ra6e2:
+
+RA6E2 Fast Prototyping Board
+############################
+
+Overview
+********
+
+The FPB-RA6E2, a Fast Prototyping Board for RA6E2 MCU Group, based on
+the 200 MHz Arm® Cortex®-M33 core with TrustZone, enables users to
+seamlessly evaluate the features of the RA6E2 MCU group and develop
+embedded systems applications using Flexible Software Package (FSP)
+and e2 studio IDE. The users can use rich on-board features along with
+their choice of popular ecosystems add-ons to bring their big ideas to life.
+
+The key features of the FPB-RA6E2 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+
+- 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package
+- 256 kB Code Flash, 40 kB SRAM
+- Native pin access through 2 x 32-pin male headers
+- MCU current measurement point for precision current consumption measurement
+- Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals,
+ providing precision 24.000 MHz and 32,768 Hz reference clock.
+ Additional low precision clocks are avaialbe internal to the RA6E2 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (micro-AB connector)
+- Two 5V input sources
+
+ - USB (Debug, Full Speed)
+ - External power supply (using 2-pin header)
+
+- On-board debugger (SWD)
+
+- User LEDs and buttons
+
+ - Two User LEDs (green)
+ - Power LED (green) indicating availability of regulated power
+ - Debug/power LED (yellow) indicating power and the debug connection
+ - One User button
+ - One Reset button
+
+- Two popular ecosystem expansions
+
+ - Two Digilent PmodTM (SPI, UART and I3C) connectors
+ - Arduino (Uno R3) connectors
+
+- MCU boot configuration jumper
+
+.. figure:: fpb-ra6e2-board.webp
+ :align: center
+ :alt: RA6E2 Fast Prototyping Board
+
+ FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
+
+.. figure:: ra6e2-block-diagram.webp
+ :width: 442px
+ :align: center
+ :alt: RA6E2 MCU group feature
+
+ RA6E2 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for FPB-RA6E2 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++===========+============+======================+
+| GPIO | on-chip | gpio |
++-----------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++-----------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++-----------+------------+----------------------+
+| UART | on-chip | serial |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``fpb_ra6e2`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to fpb-RA6E2 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6E2BB
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `FPB-RA6E2 Website`_
+- `RA6E2 MCU group Website`_
+
+.. _FPB-RA6E2 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra6e2-fast-prototyping-board-ra6e2-mcu-group
+
+.. _RA6E2 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-general-purpose-microcontroller
+
+.. _FPB-RA6E2 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/fpb-ra6e2-v1-users-manual
+
+.. _RA6E2 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra6e2-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp
new file mode 100644
index 0000000..7eeb1bc
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp
Binary files differ
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
new file mode 100644
index 0000000..851d854
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci0_default: sci0_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
+ <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+ };
+ };
+};
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
new file mode 100644
index 0000000..bc7baa6
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6e2bb3cfm.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "fpb_ra6e2-pinctrl.dtsi"
+
+/ {
+ model = "Renesas FPB-RA6E2";
+ compatible = "renesas,ra6e2", "renesas,ra";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart0;
+ zephyr,shell-uart = &uart0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioport2 6 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ led1 = &led2;
+ };
+};
+
+&sci0 {
+ pinctrl-0 = <&sci0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart0: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
+
+&ioport2 {
+ status = "okay";
+};
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "application";
+ reg = <0x00000000 DT_SIZE_K(128)>;
+ };
+
+ storage_partition: partition@20000 {
+ label = "storage";
+ reg = <0x20000 DT_SIZE_K(128)>;
+ };
+ };
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_HOCO>;
+ div = <RA_PLL_DIV_1>;
+ mul = <10 0>;
+ status = "okay";
+};
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml
new file mode 100644
index 0000000..edd2002
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml
@@ -0,0 +1,11 @@
+identifier: fpb_ra6e2
+name: Renesas FPB-RA6E2
+type: mcu
+arch: arm
+ram: 40
+flash: 256
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
new file mode 100644
index 0000000..92bb425
--- /dev/null
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1 b/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1
new file mode 100644
index 0000000..49674f3
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/Kconfig.mck_ra8t1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCK_RA8T1
+ select SOC_R7FA8T1AHECBD
diff --git a/boards/renesas/mck_ra8t1/board.cmake b/boards/renesas/mck_ra8t1/board.cmake
new file mode 100644
index 0000000..17d45a2
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA8T1AH")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/mck_ra8t1/board.yml b/boards/renesas/mck_ra8t1/board.yml
new file mode 100644
index 0000000..d722716
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: mck_ra8t1
+ vendor: renesas
+ socs:
+ - name: r7fa8t1ahecbd
diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst
new file mode 100644
index 0000000..0afab1c
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/doc/index.rst
@@ -0,0 +1,178 @@
+.. _mcb_ra8t1:
+
+RA8T1 Evaluation Kit
+####################
+
+Overview
+********
+
+The **MCK-RA8T1** is a development kit that enables easy evaluation of motor control using permanent magnet synchronous
+motors (brushless DC motors). More detailed information about the features of this toolkit and it's applications can be
+found here: `MCK-RA8T1 Website`_
+
+MCK-RA8T1 kit includes the items below:
+
+- RA8T1 CPU board (`MCB-RA8T1`_)
+- Inverter board (`MCI-LV-1`_)
+- Communication board (`MC-COM`_)
+- Permanent magnet synchronous motors
+- Accessories (cables, standoffs, etc.)
+
+.. figure:: mck-ra8t1-product-contents.jpg
+ :align: center
+ :alt: RA8T1 Evaluation Kit
+
+ MCK-RA8T1 product contents (Credit: Renesas Electronics Corporation)
+
+**MCB-RA8T1** is a CPU board for motor control equipped with RA8T1. Motor control using RA8T1 can be easily realized by
+using it in combination with a supported inverter board. The RA8T1 MCU can be evaluated using this board alone.
+
+By using a supported communication board, the CPU board can be electrically isolated from the PC for safe motor control
+evaluation and debugging.
+
+The specifications of the CPU board are shown below:
+
+**MCU specifications**
+
+- 480MHz Arm Cortex-M85 based RA8T1 MCU in 224 pins, BGA package
+- ROM/RAM size: 2MB/1MB
+- MCU input clock: 24MHz (Generate with external crystal oscillator)
+- Power supply: DC 5V, select one way automatically from the below:
+
+ - Power is supplied from compatible inverter board
+ - Power is supplied from USB connector
+
+**Connector**
+
+- Inverter board connector (2 pair)
+- USB connector for J-Link OB
+- USB connector for RA8T1
+- SCI connector for Renesas Motor Workbench communication
+- Through hole for CAN communication
+- 20 pin through hole for Arm debugger
+- Pmod connectors (Type6A + Type2A/3A)
+- Ethrnet connector
+- microSD card connector
+
+.. figure:: ra8t1-cpu-board-block-diagram.jpg
+ :align: center
+ :alt: RA8T1 Evaluation Kit
+
+ CPU Board Layout (Credit: Renesas Electronics Corporation)
+
+**Onboard debugger**
+
+This product has the onboard debugger circuit, J-Link On-Board (hereinafter called “J-Link-OB”). You can
+write a program (firmware) of RA8T1 with it.
+
+Hardware
+********
+Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_
+
+.. figure:: ra8t1-block-diagram.png
+ :width: 442px
+ :align: center
+ :alt: RA8T1 MCU group feature
+
+ RA8T1 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detail Hardware feature for the MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for MCB-RA8T1 board:
+
++--------------+------------+----------------------+
+| Interface | Controller | Driver/Component |
++==============+============+======================+
+| GPIO | on-chip | gpio |
++--------------+------------+----------------------+
+| MPU | on-chip | arch/arm |
++--------------+------------+----------------------+
+| NVIC | on-chip | arch/arm |
++--------------+------------+----------------------+
+| UART | on-chip | serial |
++--------------+------------+----------------------+
+| CLOCK | on-chip | clock control |
++--------------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``mcb_ra8t1`` board configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available.
+To build for EK-RA8M1 user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6
+
+Flashing
+========
+
+Program can be flashed to MCB-RA8T1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+ 1. Connect to J-Link OB via USB port to host PC
+
+ 2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_
+
+ 3. Execute west command
+
+ .. code-block:: console
+
+ west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA8T1AH
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that debug is OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `MCB-RA8T1 Website`_
+- `RA8T1 MCU group Website`_
+
+.. _MCB-RA8T1 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0c00000bj-mcb-ra8t1-cpu-board-ra8t1-mcu-group
+
+.. _RA8T1 MCU group Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8t1-480-mhz-arm-cortex-m85-based-motor-control-microcontroller-helium-and-trustzone
+
+.. _MCB-RA8T1 - User's Manual:
+ https://www.renesas.com/us/en/document/mat/mcb-ra8t1-users-manual?r=25466356
+
+.. _RA8T1 Group User's Manual Hardware:
+ https://www.renesas.com/us/en/document/mah/ra8t1-group-users-manual-hardware?r=25463106
+
+.. _Segger Ozone Download:
+ https://www.segger.com/downloads/jlink#Ozone
+
+.. _MCK-RA8T1 Website:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0s00020bj-mck-ra8t1-renesas-flexible-motor-control-kit-ra8t1-mcu-group
+
+.. _MCB-RA8T1:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0c00000bj-mcb-ra8t1-cpu-board-ra8t1-mcu-group
+
+.. _MCI-LV-1:
+ https://www.renesas.com/us/en/products/power-power-management/fet-motor-drivers/rtk0em0000s04020bj-mci-lv-1-renesas-flexible-motor-control-inverter-board-low-voltage-48v10a-three-phase-bldcpmsm-motor
+
+.. _MC-COM:
+ https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk0emxc90s00000bj-mc-com-renesas-flexible-motor-control-communication-board
diff --git a/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg b/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg
new file mode 100644
index 0000000..987f43a
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg
Binary files differ
diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png b/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png
new file mode 100644
index 0000000..65cc7e5
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png
Binary files differ
diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg b/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg
new file mode 100644
index 0000000..9e16a73
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg
Binary files differ
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
new file mode 100644
index 0000000..f2ac078
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci3_default: sci3_default {
+ group1 {
+ /* tx */
+ psels = <RA_PSEL(RA_PSEL_SCI_3, 3, 10)>;
+ drive-strength = "medium";
+ };
+ group2 {
+ /* rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_3, 3, 9)>;
+ };
+ };
+};
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
new file mode 100644
index 0000000..af069c8
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra8/r7fa8t1ahecbd.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mck_ra8t1-pinctrl.dtsi"
+
+/ {
+ model = "Renesas MCK-RA8T1";
+ compatible = "renesas,ra8t1", "renesas,ra8";
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,console = &uart3;
+ zephyr,shell-uart = &uart3;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1: led1 {
+ gpios = <&ioporta 12 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+ led2: led2 {
+ gpios = <&ioporta 14 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+ led3: led3 {
+ gpios = <&ioport6 6 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ led4: led4 {
+ gpios = <&ioporta 6 GPIO_ACTIVE_HIGH>;
+ label = "LED4";
+ };
+ };
+
+ aliases {
+ led0 = &led1;
+ };
+};
+
+&xtal {
+ clock-frequency = <DT_FREQ_M(24)>;
+ mosel = <0>;
+ #clock-cells = <0>;
+ status = "okay";
+};
+
+&subclk {
+ status = "okay";
+};
+
+&pll {
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <80 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(480)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(480)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(480)>;
+ status = "okay";
+};
+
+&sciclk {
+ clk_src = <RA_CLOCK_SOURCE_PLL1P>;
+ clk_div = <RA_SCI_CLOCK_DIV_4>;
+ status = "okay";
+};
+
+&ioport6 {
+ status = "okay";
+};
+
+&ioporta {
+ status = "okay";
+};
+
+&sci3 {
+ pinctrl-0 = <&sci3_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ uart3: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml
new file mode 100644
index 0000000..52ef233
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml
@@ -0,0 +1,12 @@
+identifier: mck_ra8t1
+name: Renesas MCK-RA8T1
+type: mcu
+arch: arm
+ram: 1024
+flash: 2048
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - gpio
+ - uart
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
new file mode 100644
index 0000000..5cd13d1
--- /dev/null
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
diff --git a/boards/seeed/xiao_esp32c3/Kconfig.defconfig b/boards/seeed/xiao_esp32c3/Kconfig.defconfig
index b313859..4171bb0 100644
--- a/boards/seeed/xiao_esp32c3/Kconfig.defconfig
+++ b/boards/seeed/xiao_esp32c3/Kconfig.defconfig
@@ -3,7 +3,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/seeed/xiao_esp32s3/Kconfig.defconfig b/boards/seeed/xiao_esp32s3/Kconfig.defconfig
index 661f575..b922298 100644
--- a/boards/seeed/xiao_esp32s3/Kconfig.defconfig
+++ b/boards/seeed/xiao_esp32s3/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/shields/pmod_acl/Kconfig.shield b/boards/shields/pmod_acl/Kconfig.shield
new file mode 100644
index 0000000..033dffd
--- /dev/null
+++ b/boards/shields/pmod_acl/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_PMOD_ACL
+ def_bool $(shields_list_contains,pmod_acl)
diff --git a/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay b/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay
new file mode 100644
index 0000000..283feab
--- /dev/null
+++ b/boards/shields/pmod_acl/boards/apard32690_max32690_m4.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ aliases {
+ accel0 = &adxl345_pmod_acl;
+ };
+};
diff --git a/boards/shields/pmod_acl/doc/index.rst b/boards/shields/pmod_acl/doc/index.rst
new file mode 100644
index 0000000..7a635f4
--- /dev/null
+++ b/boards/shields/pmod_acl/doc/index.rst
@@ -0,0 +1,52 @@
+.. pmod_acl:
+
+Digilent Pmod ACL
+#################
+
+Overview
+********
+
+The Digilent Pmod ACL is a 3-axis digital accelerometer module powered by the
+Analog Devices ADXL345.
+
+Programming
+***********
+
+Set ``--shield pmod_acl`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/sensor/sensor_shell
+ :board: apard32690/max32690/m4
+ :shield: pmod_acl
+ :goals: build
+
+Requirements
+************
+
+This shield can only be used with a board which provides a configuration
+for Pmod connectors and defines node aliases for SPI and GPIO interfaces
+(see :ref:`shields` for more details).
+
+References
+**********
+
+- `Pmod ACL product page`_
+- `Pmod ACL reference manual`_
+- `Pmod ACL schematic`_
+- `ADXL345 product page`_
+- `ADXL345 data sheet`_
+
+.. _Pmod ACL product page:
+ https://digilent.com/shop/pmod-acl-3-axis-accelerometer/
+
+.. _Pmod ACL reference manual:
+ https://digilent.com/reference/pmod/pmodacl/reference-manual
+
+.. _Pmod ACL schematic:
+ https://digilent.com/reference/_media/reference/pmod/pmodacl/pmodacl_sch.pdf
+
+.. _ADXL345 product page:
+ https://www.analog.com/en/products/adxl345.html
+
+.. _ADXL345 data sheet:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/adxl345.pdf
diff --git a/boards/shields/pmod_acl/pmod_acl.overlay b/boards/shields/pmod_acl/pmod_acl.overlay
new file mode 100644
index 0000000..935655b
--- /dev/null
+++ b/boards/shields/pmod_acl/pmod_acl.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pmod_spi {
+ status = "okay";
+
+ adxl345_pmod_acl: adxl345@0 {
+ compatible = "adi,adxl345";
+ reg = <0x0>;
+ spi-max-frequency = <DT_FREQ_M(1)>;
+ status = "okay";
+ };
+};
diff --git a/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig
new file mode 100644
index 0000000..9ca3447
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_X_NUCLEO_WB05KN1_UART || SHIELD_X_NUCLEO_WB05KN1_SPI
+
+if BT
+
+config SPI
+ default y
+ depends on SHIELD_X_NUCLEO_WB05KN1_SPI
+
+config SPI_STM32_INTERRUPT
+ default y
+ depends on SPI
+
+config BT_SPI
+ default y
+ depends on DT_HAS_ST_HCI_SPI_V2_ENABLED
+
+config BT_H4
+ default y
+ depends on DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED
+
+config BT_BLUENRG_ACI
+ default y
+
+# Disable Flow control
+config BT_HCI_ACL_FLOW_CONTROL
+ default n
+
+endif # BT
+
+endif # SHIELD_X_NUCLEO_WB05KN1_UART || SHIELD_X_NUCLEO_WB05KN1_SPI
diff --git a/boards/shields/x_nucleo_wb05kn1/Kconfig.shield b/boards/shields/x_nucleo_wb05kn1/Kconfig.shield
new file mode 100644
index 0000000..2beed10
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/Kconfig.shield
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_X_NUCLEO_WB05KN1_UART
+ def_bool $(shields_list_contains,x_nucleo_wb05kn1_uart)
+
+config SHIELD_X_NUCLEO_WB05KN1_SPI
+ def_bool $(shields_list_contains,x_nucleo_wb05kn1_spi)
diff --git a/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay
new file mode 100644
index 0000000..3c16686
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_h563zi.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1_sck_pa5 {
+ /delete-property/ bias-pull-down;
+ bias-pull-up;
+};
+
+&spi1_miso_pg9 {
+ slew-rate = "high-speed";
+};
+
+&spi1_mosi_pb5 {
+ slew-rate = "high-speed";
+};
+
+/ {
+ chosen {
+ zephyr,bt-c2h-uart = &usart3;
+ };
+};
diff --git a/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay
new file mode 100644
index 0000000..f6ff77a
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/boards/nucleo_u575zi_q.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1_sck_pa5 {
+ /delete-property/ bias-pull-down;
+ bias-pull-up;
+};
+
+&spi1_miso_pa6 {
+ slew-rate = "high-speed";
+};
+
+&spi1_mosi_pa7 {
+ slew-rate = "high-speed";
+};
+
+&arduino_spi {
+ pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
+};
+
+/ {
+ chosen {
+ zephyr,bt-c2h-uart = &usart1;
+ };
+};
diff --git a/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp b/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp
new file mode 100644
index 0000000..a9e5883
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/doc/img/x-nucleo-wb05kn1.webp
Binary files differ
diff --git a/boards/shields/x_nucleo_wb05kn1/doc/index.rst b/boards/shields/x_nucleo_wb05kn1/doc/index.rst
new file mode 100644
index 0000000..04f8bb5
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/doc/index.rst
@@ -0,0 +1,99 @@
+.. _x-nucleo-wb05kn1:
+
+X-NUCLEO-WB05KN1: BLE expansion board
+#####################################
+
+Overview
+********
+The X-NUCLEO-WB05KN1 is a Bluetooth Low Energy evaluation board which allows the
+expansion of the STM32 Nucleo boards.
+The RF module is FCC (FCC ID: YCP-MB203202) and IC certified (IC: 8976A-MB203202).
+
+The X-NUCLEO-WB05KN1 is compatible out of the box with the Arduino UNO R3 connector.
+The board interfaces with the host microcontroller via UART (default) or SPI peripheral.
+
+.. image:: img/x-nucleo-wb05kn1.webp
+ :align: center
+ :alt: X-NUCLEO-WB05KN1
+
+More information about the board can be found at the
+`X-NUCLEO-WB05KN1 website`_.
+
+Configurations
+**************
+
+X-NUCLEO-WB05KN1 can be utilized as a Bluetooth Low-Energy controller shield
+with a UART or SPI host controller interface (HCI-UART/HCI-SPI).
+
+The UART default settings are:
+
+* Baudrate: 921600 bps
+* 8 bits, no parity, 1 stop bit
+
++----------+-----------------------+
+| UART Pin | Arduino Connector Pin |
++==========+=======================+
+| RX | D0 |
++----------+-----------------------+
+| TX | D1 |
++----------+-----------------------+
+
+.. note::
+ Please, bear in mind in order to use SPI interface you need to change the shield firmware
+ to ``DTM_SPI_WITH_UPDATER_CONTROLLER`` according to the SDK provided by ST at `X-CUBE-WB05N`_.
+
+IRQ and reset pins are also necessary in addition to SPI pins.
+
++----------------+-----------------------+
+| SPI Config Pin | Arduino Connector Pin |
++================+=======================+
+| SCK | D13 |
++----------------+-----------------------+
+| MISO | D12 |
++----------------+-----------------------+
+| MOSI | D11 |
++----------------+-----------------------+
+| CS | D10 |
++----------------+-----------------------+
+| IRQ | A0 |
++----------------+-----------------------+
+| RESET | D7 |
++----------------+-----------------------+
+
+More information about X-NUCLEO-WB05KN1 can be found here:
+ - `X-NUCLEO-WB05KN1 datasheet`_
+
+Programming
+***********
+
+Activate the presence of the shield for the project build by adding the
+``--shield x_nucleo_wb05kn1_uart`` or ``--shield x_nucleo_wb05kn1_spi`` when you invoke
+``west build`` based on UART or SPI interface:
+
+ .. zephyr-app-commands::
+ :zephyr-app: your_app
+ :board: your_board_name
+ :shield: x_nucleo_wb05kn1_uart
+ :goals: build
+
+or
+
+ .. zephyr-app-commands::
+ :zephyr-app: your_app
+ :board: your_board_name
+ :shield: x_nucleo_wb05kn1_spi
+ :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _X-NUCLEO-WB05KN1 website:
+ https://www.st.com/en/evaluation-tools/x-nucleo-wb05kn1.html
+
+.. _X-CUBE-WB05N:
+ https://www.st.com/en/embedded-software/x-cube-wb05n.html
+
+.. _X-NUCLEO-WB05KN1 datasheet:
+ https://www.st.com/resource/en/datasheet/stm32wb05kn.pdf
diff --git a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay
new file mode 100644
index 0000000..43cf2be
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ chosen {
+ zephyr,bt-hci = &hci_spi;
+ };
+};
+
+&arduino_spi {
+ cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
+
+ hci_spi: wb05n@0 {
+ compatible = "st,hci-spi-v2";
+ reg = <0>;
+ reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
+ irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
+ spi-cpol; /* CPOL=1 */
+ spi-cpha; /* CPHA=1 */
+ spi-hold-cs;
+ spi-max-frequency = <DT_FREQ_M(8)>; /* the maximum supported SPI speed */
+ reset-assert-duration-ms = <6>;
+ status = "okay";
+ };
+};
diff --git a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay
new file mode 100644
index 0000000..a0ae0ca
--- /dev/null
+++ b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_uart.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ chosen {
+ zephyr,bt-hci = &bt_hci_uart;
+ };
+};
+
+&arduino_serial {
+ current-speed = <921600>;
+
+ bt_hci_uart: bt_hci_uart {
+ compatible = "zephyr,bt-hci-uart";
+ status = "okay";
+ };
+};
diff --git a/boards/silabs/dev_kits/sltb010a/board.c b/boards/silabs/dev_kits/sltb010a/board.c
index e4dc2c3..7572f0f 100644
--- a/boards/silabs/dev_kits/sltb010a/board.c
+++ b/boards/silabs/dev_kits/sltb010a/board.c
@@ -33,8 +33,9 @@
return -ENODEV;
}
ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE);
- if (ret < 0)
+ if (ret < 0) {
return ret;
+ }
return 0;
}
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.c b/boards/silabs/dev_kits/xg24_dk2601b/board.c
index 5b138e8..601b759 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/board.c
+++ b/boards/silabs/dev_kits/xg24_dk2601b/board.c
@@ -33,8 +33,9 @@
return -ENODEV;
}
ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE);
- if (ret < 0)
+ if (ret < 0) {
return ret;
+ }
return 0;
}
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.c b/boards/silabs/dev_kits/xg27_dk2602a/board.c
index fcdcab0..f26befc 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/board.c
+++ b/boards/silabs/dev_kits/xg27_dk2602a/board.c
@@ -33,8 +33,9 @@
return -ENODEV;
}
ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE);
- if (ret < 0)
+ if (ret < 0) {
return ret;
+ }
return 0;
}
diff --git a/boards/st/nucleo_h755zi_q/Kconfig.defconfig b/boards/st/nucleo_h755zi_q/Kconfig.defconfig
new file mode 100644
index 0000000..2b0f2ca
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# STM32H755ZI Nucleo board configuration
+
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_H755ZI_Q
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+ default y
+
+endif # NETWORKING
+
+endif # BOARD_NUCLEO_H755ZI_Q
diff --git a/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q b/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q
new file mode 100644
index 0000000..57d7263
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q
@@ -0,0 +1,8 @@
+# STM32H755ZI Nucleo board configuration
+
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_H755ZI_Q
+ select SOC_STM32H755XX_M7 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7
+ select SOC_STM32H755XX_M4 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4
diff --git a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi
new file mode 100644
index 0000000..aaa4cec
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ arduino_header: connector {
+ compatible = "arduino-header-r3";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <0 0 &gpioa 3 0>, /* A0 */
+ <1 0 &gpioc 0 0>, /* A1 */
+ <2 0 &gpioc 3 0>, /* A2 */
+ <3 0 &gpiob 1 0>, /* A3 */
+ <4 0 &gpioc 2 0>, /* A4 */
+ <5 0 &gpiof 11 0>, /* A5 */
+ <6 0 &gpiob 7 0>, /* D0 */
+ <7 0 &gpiob 6 0>, /* D1 */
+ <8 0 &gpiog 14 0>, /* D2 */
+ <9 0 &gpioe 13 0>, /* D3 */
+ <10 0 &gpioe 14 0>, /* D4 */
+ <11 0 &gpioe 11 0>, /* D5 */
+ <12 0 &gpioa 8 0>, /* D6 */
+ <13 0 &gpiog 12 0>, /* D7 */
+ <14 0 &gpiog 9 0>, /* D8 */
+ <15 0 &gpiod 15 0>, /* D9 */
+ <16 0 &gpiod 14 0>, /* D10 */
+ <17 0 &gpiob 5 0>, /* D11 */
+ <18 0 &gpioa 6 0>, /* D12 */
+ <19 0 &gpioa 5 0>, /* D13 */
+ <20 0 &gpiob 9 0>, /* D14 */
+ <21 0 &gpiob 8 0>; /* D15 */
+ };
+};
+
+arduino_i2c: &i2c1 {};
+
+arduino_serial: &uart8 {};
diff --git a/boards/st/nucleo_h755zi_q/board.cmake b/boards/st/nucleo_h755zi_q/board.cmake
new file mode 100644
index 0000000..8268107
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/board.cmake
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32H755ZI" "--speed=3300")
+if(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7)
+ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
+elseif(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4)
+ board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_h755zi_q/board.yml b/boards/st/nucleo_h755zi_q/board.yml
new file mode 100644
index 0000000..ecffd3b
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: nucleo_h755zi_q
+ vendor: st
+ socs:
+ - name: stm32h755xx
diff --git a/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp b/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp
new file mode 100644
index 0000000..4202c63
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/doc/img/nucleo_h755zi_q.webp
Binary files differ
diff --git a/boards/st/nucleo_h755zi_q/doc/index.rst b/boards/st/nucleo_h755zi_q/doc/index.rst
new file mode 100644
index 0000000..2b5aecf
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/doc/index.rst
@@ -0,0 +1,295 @@
+.. _nucleo_h755zi_q_board:
+
+ST Nucleo H755ZI-Q
+###################
+
+Overview
+********
+
+The NUCLEO-H755ZI-Q board, based on the MB1363 reference board, provides an affordable and
+flexible way for users to try out new concepts and build prototypes on the STM32H755ZIT6
+microcontroller.
+
+The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and
+the ST morpho headers provide an easy means of expanding the functionality of the Nucleo
+open development platform with a wide choice of specialized shields.
+The NUCLEO-H755ZI-Q board does not require any separate probe as it integrates
+the ST-LINK V3 debugger/programmer.
+
+Key Features
+
+- STM32H755ZIT6 microcontroller in LQFP144 package
+- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
+- USB OTG or full-speed device (depending on STM32 support)
+- 3 user LEDs
+- 2 user and reset push-buttons
+- 32.768 kHz crystal oscillator
+- Board connectors:
+
+ - USB with Micro-AB
+ - Ethernet RJ45 (depending on STM32 support)
+ - SWDST Zio connector including Arduino* Uno V3ST
+ - ST morpho expansion
+
+- Flexible power-supply options: ST-LINK USB VBUS or external sources
+- External or internal SMPS to generate Vcore logic supply
+- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
+- capability: mass storage, virtual COM port and debug port
+- USB OTG full speed or device only
+
+.. image:: img/nucleo_h755zi_q.webp
+ :align: center
+ :alt: Nucleo H755ZI-Q
+
+More information about the board can be found at the `Nucleo H755ZI-Q website`_.
+
+Hardware
+********
+
+Nucleo H755ZI-Q provides the following hardware components:
+
+- STM32H755ZI in LQFP144 package
+- ARM 32-bit Cortex-M7 CPU with FPU
+- ARM 32-bit Cortex-M4 CPU with FPU
+- Chrom-ART Accelerator
+- Hardware JPEG Codec
+- 480 MHz max CPU frequency
+- VDD from 1.62 V to 3.6 V
+- 2 MB Flash
+- 1 MB SRAM
+- High-resolution timer (2.1 ns)
+- 32-bit timers(2)
+- 16-bit timers(12)
+- SPI(6)
+- I2C(4)
+- I2S (3)
+- USART(4)
+- UART(4)
+- USB OTG Full Speed and High Speed(1)
+- USB OTG Full Speed(1)
+- CAN-FD(2)
+- SAI(2)
+- SPDIF_Rx(4)
+- HDMI_CEC(1)
+- Dual Mode Quad SPI(1)
+- Camera Interface
+- GPIO (up to 114) with external interrupt capability
+- 16-bit ADC(3) with 36 channels / 3.6 MSPS
+- 12-bit DAC with 2 channels(2)
+- True Random Number Generator (RNG)
+- 16-channel DMA
+- LCD-TFT Controller with XGA resolution
+- CRYPT and HASH peripherals
+
+Supported Features
+==================
+
+The Zephyr nucleo_h755zi_q board configuration supports the following hardware
+features:
+
++-------------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++=============+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-------------+------------+-------------------------------------+
+| UART/USART | on-chip | serial port |
++-------------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-------------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-------------+------------+-------------------------------------+
+| RTC | on-chip | counter |
++-------------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-------------+------------+-------------------------------------+
+| PWM | on-chip | pwm |
++-------------+------------+-------------------------------------+
+| ETHERNET | on-chip | ethernet |
++-------------+------------+-------------------------------------+
+| RNG | on-chip | True Random number generator |
++-------------+------------+-------------------------------------+
+| USB OTG FS | on-chip | USB device |
++-------------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration per core can be found in the defconfig files:
+:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig` and
+:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig`
+
+For mode details please refer to `STM32 Nucleo-144 board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The Nucleo H755ZI board features a ST Zio connector (extended Arduino Uno V3)
+and a ST morpho connector. Board is configured as follows:
+
+- USART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
+- USER_PB : PC13
+- LD1 : PA5
+- LD2 : PE1
+- LD3 : PB14
+- I2C : PB8, PB9
+
+System Clock
+------------
+
+Nucleo H755ZI-Q System Clock can be driven by an internal or external
+oscillator, as well as the main PLL clock. By default, the System clock is
+driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock.
+
+Serial Port
+-----------
+
+Nucleo H755ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is
+assigned to USART3. Default settings are 115200 8N1.
+
+Resources sharing
+-----------------
+
+The dual core nature of STM32H755 SoC requires sharing HW resources between the
+two cores. This is done in 3 ways:
+
+- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
+ has access to bus clock activation and deactivation.
+- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
+ devicetree before compilation. The user must ensure peripherals are not assigned
+ to both cores at the same time.
+- **Run time protection**: Interrupt-controller and GPIO configurations could be
+ accessed by both cores at run time. Accesses are protected by a hardware semaphore
+ to avoid potential concurrent access issues.
+
+Programming and Debugging
+*************************
+
+Applications for the ``nucleo_h755zi_q`` board should be built per core target,
+using either ``nucleo_h755zi_q/stm32h755xx/m7`` or ``nucleo_h755zi_q/stm32h755xx/m4``
+as the target (see :ref:`build_an_application` and :ref:`application_run` for more
+details).
+
+.. note::
+
+ Check if the board's ST-LINK V3 has the newest firmware version. It can be
+ updated with `STM32CubeIDE`_
+
+Flashing
+========
+
+Nucleo H755ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner
+for both cores, so its installation is required to be able to flash the board.
+The target core is detected automatically.
+
+It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
+configuration and flash ``nucleo_h755zi_q/stm32h755xx/m7`` and
+``nucleo_h755zi_q/stm32h755xx/m4`` board targets.
+
+By default:
+
+ - CPU0 (Cortex-M7) boot address is set to 0x08000000 (OB: BOOT_CM7_ADD0)
+ - CPU1 (Cortex-M4) boot address is set to 0x08100000 (OB: BOOT_CM4_ADD0)
+
+Also, default out of the box board configuration enables CM7 and CM4 boot when
+board is powered (Option bytes BCM7 and BCM4 are checked).
+In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected.
+Zephyr flash configuration has been set to meet these default settings.
+
+Alternatively, openocd or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+ $ west flash --runner openocd
+ $ west flash --runner jlink
+
+Flashing an application to STM32H755ZI M7 Core
+----------------------------------------------
+First, connect the NUCLEO-H755ZI-Q to your host computer using
+the USB port to prepare it for flashing. Then build and flash your application.
+
+Here is an example for the :ref:`hello_world` application.
+
+Run a serial host program to connect with your NUCLEO-H755ZI-Q board.
+
+.. code-block:: console
+
+ $ minicom -b 115200 -D /dev/ttyACM0
+
+or use screen:
+
+.. code-block:: console
+
+ $ screen /dev/ttyACM0 115200
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: nucleo_h755zi_q/stm32h755xx/m7
+ :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+ $ Hello World! nucleo_h755zi_q/stm32h755xx/m7
+
+.. note::
+ Sometimes, flashing via OpenOCD does not work. It is necessary to erase the flash
+ (with STM32CubeProgrammer for example) to make it work again.
+
+Similarly, you can build and flash samples on the M4 target. For this, please
+take care of the resource sharing (UART port used for console for instance).
+
+Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/basic/blinky
+ :board: nucleo_h755zi_q/stm32h755xx/m4
+ :goals: build flash
+
+.. note::
+
+ Flashing both M4 and M7 and pushing RESTART button on the board leads
+ to LD1 and LD2 flashing simultaneously.
+
+Debugging
+=========
+
+You can debug an application on the Cortex M7 core in the usual way.
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: nucleo_h755zi_q/stm32h755xx/m7
+ :maybe-skip-config:
+ :goals: debug
+
+Debugging a Zephyr application on Cortex M4 side with west is currently not
+available. As a workaround, `STM32CubeIDE`_ can be used.
+
+.. _Nucleo H755ZI-Q website:
+ https://www.st.com/en/evaluation-tools/nucleo-h755zi-q.html
+
+.. _STM32 Nucleo-144 board User Manual:
+ https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf
+
+.. _STM32H755ZI on www.st.com:
+ https://www.st.com/en/microcontrollers-microprocessors/stm32h755zi.html
+
+.. _STM32H755 reference manual:
+ https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _OpenOCD installing Debug Version:
+ https://github.com/zephyrproject-rtos/openocd
+
+.. _OpenOCD installing with ST-LINK V3 support:
+ https://mbd.kleier.net/integrating-st-link-v3.html
+
+.. _STM32CubeIDE:
+ https://www.st.com/en/development-tools/stm32cubeide.html
+
+.. _STM32CubeProgrammer:
+ https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi
new file mode 100644
index 0000000..235b1f2
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h755zitx-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ leds: leds {
+ compatible = "gpio-leds";
+ green_led: led_1 {
+ gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+ label = "User LD1";
+ };
+ yellow_led: led_2 {
+ gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>;
+ label = "User LD2";
+ };
+ red_led: led_3 {
+ gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
+ label = "User LD3";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button: button_0 {
+ gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+ label = "User SB1";
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+&rcc {
+ d1cpre = <1>;
+ hpre = <2>;
+ d1ppre = <2>;
+ d2ppre1 = <2>;
+ d2ppre2 = <2>;
+ d3ppre = <2>;
+};
+
+&mailbox {
+ status = "okay";
+};
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts
new file mode 100644
index 0000000..71501da
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h755Xi_m4.dtsi>
+#include "nucleo_h755zi_q.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
+ compatible = "st,stm32h755zi-q-nucleo";
+
+ /* HW resources belonging to CM4 */
+ chosen {
+ zephyr,console = &uart8;
+ zephyr,shell-uart = &uart8;
+ zephyr,sram = &sram1;
+ zephyr,flash = &flash1;
+ };
+
+ aliases {
+ led0 = &yellow_led;
+ };
+};
+
+&uart8 {
+ pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&rcc {
+ clock-frequency = <DT_FREQ_M(240)>;
+};
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml
new file mode 100644
index 0000000..b29de5b
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml
@@ -0,0 +1,18 @@
+identifier: nucleo_h755zi_q/stm32h755xx/m4
+name: ST Nucleo H755ZI-Q (M4)
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ram: 288
+flash: 1024
+supported:
+ - arduino_gpio
+ - gpio
+ - netif:eth
+testing:
+ ignore_tags:
+ - mpu
+ - nfc
+vendor: st
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig
new file mode 100644
index 0000000..632f31e
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable clock
+CONFIG_CLOCK_CONTROL=y
+
+# By default SERIAL peripherals are assigned to m7
+
+# Enable uart driver
+#CONFIG_SERIAL=y
+
+# Console
+#CONFIG_CONSOLE=y
+#CONFIG_UART_CONSOLE=y
+
+# Enable pin controller
+CONFIG_PINCTRL=y
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
new file mode 100644
index 0000000..d565297
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h755Xi_m7.dtsi>
+#include "nucleo_h755zi_q.dtsi"
+
+/*
+ * WARNING:
+ * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
+ * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
+ * avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
+ */
+
+/ {
+ model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
+ compatible = "st,stm32h755zi-q-nucleo";
+
+ /* HW resources belonging to CM7 */
+ chosen {
+ zephyr,console = &usart3;
+ zephyr,shell-uart = &usart3;
+ zephyr,dtcm = &dtcm;
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ red_pwm_led: red_pwm_led {
+ pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+ label = "User LD3 - PWM12";
+ };
+ };
+
+ aliases {
+ led0 = &green_led;
+ pwm-led0 = &red_pwm_led;
+ sw0 = &user_button;
+ };
+};
+
+&clk_lsi {
+ status = "okay";
+};
+
+&clk_hsi48 {
+ status = "okay";
+};
+
+&clk_hse {
+ hse-bypass;
+ clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+ status = "okay";
+};
+
+&pll {
+ div-m = <1>;
+ mul-n = <120>;
+ div-p = <2>;
+ div-q = <8>;
+ div-r = <2>;
+ clocks = <&clk_hse>;
+ status = "okay";
+};
+
+&rcc {
+ clocks = <&pll>;
+ clock-frequency = <DT_FREQ_M(480)>;
+};
+
+&usart3 {
+ pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
+ <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+ pinctrl-names = "default";
+ status = "okay";
+ clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&timers12 {
+ st,prescaler = <10000>;
+ status = "okay";
+
+ pwm12: pwm {
+ status = "okay";
+ pinctrl-0 = <&tim12_ch1_pb14>;
+ pinctrl-names = "default";
+ };
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ð_ref_clk_pa1
+ ð_crs_dv_pa7
+ ð_rxd0_pc4
+ ð_rxd1_pc5
+ ð_tx_en_pg11
+ ð_txd0_pg13
+ ð_txd1_pb13>;
+ pinctrl-names = "default";
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
+ pinctrl-names = "default";
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy";
+ reg = <0x00>;
+ status = "okay";
+ };
+};
+
+&rng {
+ status = "okay";
+};
+
+zephyr_udc0: &usbotg_fs {
+ pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml
new file mode 100644
index 0000000..63739df
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml
@@ -0,0 +1,20 @@
+identifier: nucleo_h755zi_q/stm32h755xx/m7
+name: ST Nucleo H755ZI-Q (M7)
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ram: 512
+flash: 1024
+supported:
+ - arduino_gpio
+ - arduino_i2c
+ - uart
+ - gpio
+ - counter
+ - i2c
+ - pwm
+ - netif:eth
+ - usb_device
+vendor: st
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig
new file mode 100644
index 0000000..712afba
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART (disable to assign to M4 core)
+CONFIG_SERIAL=y
+
+# Console (disable to assign to M4 core)
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Clock
+CONFIG_CLOCK_CONTROL=y
+
+# Enable pin controller
+CONFIG_PINCTRL=y
diff --git a/boards/st/nucleo_h755zi_q/support/openocd.cfg b/boards/st/nucleo_h755zi_q/support/openocd.cfg
new file mode 100644
index 0000000..719125f
--- /dev/null
+++ b/boards/st/nucleo_h755zi_q/support/openocd.cfg
@@ -0,0 +1,30 @@
+# STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration
+#
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# Borrow the nucleo_h745zi openocd configuration as no config exists for the h755 yet.
+source [find board/st_nucleo_h745zi.cfg]
+
+# Use connect_assert_srst here to be able to program
+# even when core is in sleep mode
+reset_config srst_only srst_nogate connect_assert_srst
+
+$_CHIPNAME.cpu0 configure -event gdb-attach {
+ echo "Debugger attaching: halting execution"
+ gdb_breakpoint_override hard
+}
+
+$_CHIPNAME.cpu0 configure -event gdb-detach {
+ echo "Debugger detaching: resuming execution"
+ resume
+}
+
+# Due to the use of connect_assert_srst, running gdb requires
+# to reset halt just after openocd init.
+rename init old_init
+proc init {} {
+ old_init
+ reset halt
+}
diff --git a/boards/st/steval_stwinbx1/doc/index.rst b/boards/st/steval_stwinbx1/doc/index.rst
index 9027db1..0008f6d 100644
--- a/boards/st/steval_stwinbx1/doc/index.rst
+++ b/boards/st/steval_stwinbx1/doc/index.rst
@@ -361,10 +361,9 @@
usb 3-1: Manufacturer: STMicroelectronics
usb 3-1: SerialNumber: 207136863530
-.. You can build and flash the provided sample application
-.. (:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs
-.. values on the console.
-
+You can build and flash the provided sample application
+(:ref:`steval_stwinbx1_sample_sensors`) that reads sensors data and outputs
+values on the console.
.. _STEVAL-STWINBX1 Development kit website:
https://www.st.com/en/evaluation-tools/steval-stwinbx1.html
diff --git a/boards/st/steval_stwinbx1/steval_stwinbx1.dts b/boards/st/steval_stwinbx1/steval_stwinbx1.dts
index d8c3586..040452e 100644
--- a/boards/st/steval_stwinbx1/steval_stwinbx1.dts
+++ b/boards/st/steval_stwinbx1/steval_stwinbx1.dts
@@ -149,6 +149,39 @@
status = "okay";
};
+&spi2 {
+ pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pd3 &spi2_mosi_pi3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ cs-gpios = <&gpioh 6 GPIO_ACTIVE_LOW>,
+ <&gpioh 15 GPIO_ACTIVE_LOW>,
+ <&gpioi 7 GPIO_ACTIVE_LOW>;
+ iis2dlpc: iis2dlpc@0 {
+ compatible = "st,iis2dlpc";
+ spi-max-frequency = <DT_FREQ_M(10)>;
+ reg = <0>;
+ drdy-gpios = <&gpiof 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+ drdy-int = <1>;
+ };
+
+ ism330dhcx: ism330dhcx@1 {
+ compatible = "st,ism330dhcx";
+ spi-max-frequency = <DT_FREQ_M(10)>;
+ reg = <1>;
+ drdy-gpios = <&gpiob 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+ int-pin = <1>;
+ };
+
+ iis2iclx: iis2iclx@2 {
+ compatible = "st,iis2iclx";
+ spi-max-frequency = <DT_FREQ_M(10)>;
+ reg = <2>;
+ drdy-gpios = <&gpiof 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+ int-pin = <2>;
+ };
+};
+
&spi3 {
pinctrl-0 = <&spi3_sck_pg9 &spi3_miso_pb4 &spi3_mosi_pb5>;
pinctrl-names = "default";
@@ -178,6 +211,13 @@
int-gpios = <&gpiof 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ iis2mdc@1e {
+ compatible = "st,iis2mdc";
+ reg = <0x1e>;
+ drdy-gpios = <&gpiof 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
};
&timers5 {
diff --git a/boards/st/stm32f429i_disc1/board.cmake b/boards/st/stm32f429i_disc1/board.cmake
index bc72082..a175073 100644
--- a/boards/st/stm32f429i_disc1/board.cmake
+++ b/boards/st/stm32f429i_disc1/board.cmake
@@ -2,7 +2,11 @@
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(jlink "--device=STM32F429ZI" "--speed=4000")
+board_runner_args(pyocd "--target=stm32f429xi")
+board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
+board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
index 09b8177..ba2f771 100644
--- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
+++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
@@ -184,6 +184,7 @@
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
+ reset-cmd;
status = "okay";
partitions {
diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
index f1de878..9feb49e 100644
--- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
+++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
@@ -255,6 +255,7 @@
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
+ reset-cmd;
status = "okay";
partitions {
diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts
index 946c832..88d1be6 100644
--- a/boards/st/stm32h750b_dk/stm32h750b_dk.dts
+++ b/boards/st/stm32h750b_dk/stm32h750b_dk.dts
@@ -168,6 +168,7 @@
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
+ reset-cmd;
status = "okay";
partitions {
diff --git a/boards/st/stm32l562e_dk/Kconfig.defconfig b/boards/st/stm32l562e_dk/Kconfig.defconfig
index ed9a04e..b0dc8f3b 100644
--- a/boards/st/stm32l562e_dk/Kconfig.defconfig
+++ b/boards/st/stm32l562e_dk/Kconfig.defconfig
@@ -25,4 +25,15 @@
endif # BT
+config MIPI_DBI_STM32_FMC_MEM_BARRIER
+ default n if MIPI_DBI_STM32_FMC
+
+if DISPLAY
+
+choice ST7789V_PIXEL_FORMAT
+ default ST7789V_BGR565
+endchoice
+
+endif # DISPLAY
+
endif # BOARD_STM32L562E_DK
diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk.dts b/boards/st/stm32l562e_dk/stm32l562e_dk.dts
index 2083e93..9489e8d 100644
--- a/boards/st/stm32l562e_dk/stm32l562e_dk.dts
+++ b/boards/st/stm32l562e_dk/stm32l562e_dk.dts
@@ -20,6 +20,7 @@
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,bt-c2h-uart = &usart1;
+ zephyr,display = &st7789v;
};
aliases {
diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
index d0929a6..f801591 100644
--- a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
+++ b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
@@ -8,6 +8,8 @@
#include <st/l5/stm32l562qeixq-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
leds {
@@ -42,6 +44,76 @@
};
};
+&fmc {
+ pinctrl-0 = <&fmc_a0_pf0 &fmc_nce_pd7 &fmc_nwe_pd5 &fmc_noe_pd4
+ &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
+ &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
+ &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
+ &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ sram {
+ compatible = "st,stm32-fmc-nor-psram";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bank@0 {
+ reg = <0x0>;
+ st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
+ STM32_FMC_MEMORY_TYPE_SRAM
+ STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
+ STM32_FMC_BURST_ACCESS_MODE_DISABLE
+ STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
+ STM32_FMC_WAIT_TIMING_BEFORE_WS
+ STM32_FMC_WRITE_OPERATION_ENABLE
+ STM32_FMC_WAIT_SIGNAL_DISABLE
+ STM32_FMC_EXTENDED_MODE_DISABLE
+ STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
+ STM32_FMC_WRITE_BURST_DISABLE
+ STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
+ STM32_FMC_WRITE_FIFO_DISABLE
+ STM32_FMC_PAGE_SIZE_NONE>;
+ st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
+
+ fmc-mipi-dbi {
+ compatible = "st,stm32-fmc-mipi-dbi";
+ reset-gpios = <&gpiof 14 GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpioh 0 GPIO_ACTIVE_LOW>;
+ register-select-pin = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ st7789v: lcd-panel@0 {
+ compatible = "sitronix,st7789v";
+ reg = <0>;
+ mipi-mode = <MIPI_DBI_MODE_8080_BUS_16_BIT>;
+ /* A write cycle should be 68ns */
+ mipi-max-frequency = <14705882>;
+ width = <240>;
+ height = <240>;
+ x-offset = <0>;
+ y-offset = <0>;
+ vcom = <0x1F>;
+ gctrl = <0x35>;
+ vdvs = <0x20>;
+ mdac = <0x00>;
+ gamma = <0x01>;
+ colmod = <0x05>;
+ lcm = <0x2c>;
+ porch-param = [0c 0c 00 33 33];
+ cmd2en-param = [5a 69 02 00];
+ pwctrl1-param = [a4 a1];
+ pvgam-param = [D0 08 11 08 0C 15 39 33 50 36 13 14 29 2D];
+ nvgam-param = [D0 08 10 08 06 06 39 44 51 0B 16 14 2F 31];
+ ram-param = [00 F0];
+ rgb-param = [40 02 14];
+ };
+ };
+ };
+ };
+};
+
&clk_hsi48 {
status = "okay";
};
diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig
index 1f6ec27..2ca1ba1 100644
--- a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig
+++ b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig
@@ -7,7 +7,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig
index dc1a6f0..06c61c8 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig
@@ -5,7 +5,7 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
- default $(UINT16_MAX) if WIFI && BT
+ default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
diff --git a/boards/witte/index.rst b/boards/witte/index.rst
new file mode 100644
index 0000000..c7c0d91
--- /dev/null
+++ b/boards/witte/index.rst
@@ -0,0 +1,10 @@
+.. _boards-witte:
+
+Witte
+#####
+
+.. toctree::
+ :maxdepth: 1
+ :glob:
+
+ **/*
diff --git a/boards/witte/linum/Kconfig.defconfig b/boards/witte/linum/Kconfig.defconfig
new file mode 100644
index 0000000..af3bbba
--- /dev/null
+++ b/boards/witte/linum/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# STM32H753ZI Linum board configuration
+
+# Copyright (c) 2024 Felipe Neves
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_LINUM
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+ default y
+
+endif # NETWORKING
+
+endif # BOARD_LINUM
diff --git a/boards/witte/linum/Kconfig.linum b/boards/witte/linum/Kconfig.linum
new file mode 100644
index 0000000..447e3e7
--- /dev/null
+++ b/boards/witte/linum/Kconfig.linum
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Felipe Neves
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LINUM
+ select SOC_STM32H753XX
diff --git a/boards/witte/linum/board.cmake b/boards/witte/linum/board.cmake
new file mode 100644
index 0000000..8b78b09
--- /dev/null
+++ b/boards/witte/linum/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=STM32H753BI" "--speed=4000")
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
diff --git a/boards/witte/linum/board.yml b/boards/witte/linum/board.yml
new file mode 100644
index 0000000..e9ae2c0
--- /dev/null
+++ b/boards/witte/linum/board.yml
@@ -0,0 +1,5 @@
+board:
+ name: linum
+ vendor: witte
+ socs:
+ - name: stm32h753xx
diff --git a/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg b/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg
new file mode 100644
index 0000000..df465c7
--- /dev/null
+++ b/boards/witte/linum/doc/img/linum-stm32h753bi-top.jpg
Binary files differ
diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst
new file mode 100644
index 0000000..86fbbea
--- /dev/null
+++ b/boards/witte/linum/doc/index.rst
@@ -0,0 +1,406 @@
+.. _linum:
+
+Witte Technology Linum Board
+############################
+
+Overview
+********
+Linum is a development board released by Witte Tenology in 2023, and it was developed around the
+STM32H753BI microcontroller. The board has 2 expansion connectors used by the LCD display with
+touchscreen and another for access to other peripherals of microcontroller. Also it brings plenty
+of communications interfaces like UART with RS232 and RS485 capabillities, CAN bus compatible to
+FD standard, and networking over Ethernet.
+
+.. image:: img/linum-stm32h753bi-top.jpg
+ :align: center
+ :alt: Linum development board
+
+Hardware
+********
+
+The board features:
+ - 8 to 52V power supply
+ - SWD Pins for use as STLink (Pin header) and TC2030-IDC 6-Pin Tag-Connect Plug-of-Nails™ Connector
+ - Crystal for HS 25MHz
+ - Crystal for RTC 32.768KHz
+ - 1 UART serial for debug
+ - 1 Led RGB
+ - 1 Buzzer without internal oscillator
+ - 1 Mono audio up to 3W
+ - 1 Ethernet 10/100
+ - 1 MicroSD connector supporting 1 or 4-bit bus
+ - 1 USB 2.0 Host/Device
+ - 1 EEPROM memory with 512K bits
+ - 1 External SRAM memory with 8MB
+ - 1 NOR memory with 16MB
+ - 2 On-board RS232 Transceiver with RTS/CTS
+ - 2 On-board RS485 Transceiver
+ - 2 On-board CAN-FD Transceiver
+
+Expansion connector 1 features:
+ - 1 Display RBG 888
+ - 1 Capacitive Touchscreen sensor
+
+Expansion connector 2 features.
+ - 1 SPI
+ - 1 I2C
+ - 1 One Wire
+ - 2 DACs
+ - 6 PWM Channels
+ - 10 ADCs
+
+Supported Features
+==================
+
+The Zephyr Linum board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port |
++-----------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| RTC | on-chip | counter |
++-----------+------------+-------------------------------------+
+| I2C | on-chip | i2c |
++-----------+------------+-------------------------------------+
+| PWM | on-chip | pwm |
++-----------+------------+-------------------------------------+
+| ADC | on-chip | adc |
++-----------+------------+-------------------------------------+
+| RNG | on-chip | True Random number generator |
++-----------+------------+-------------------------------------+
+| ETHERNET | on-chip | ethernet |
++-----------+------------+-------------------------------------+
+| SPI | on-chip | spi |
++-----------+------------+-------------------------------------+
+| USB | on-chip | usb_device |
++-----------+------------+-------------------------------------+
+| CAN/CANFD | on-chip | canbus |
++-----------+------------+-------------------------------------+
+| LTDC | on-chip | LCD Interface |
++-----------+------------+-------------------------------------+
+| FMC | on-chip | memc (SDRAM) |
++-----------+------------+-------------------------------------+
+| SDMMC | on-chip | disk access |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+:zephyr_file:`boards/witte_technology/linum/linum_defconfig`
+
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+
+BOARD-LEDs
+----------
+
+The LINUM-STM32H753BI has 3 software controllable LEDs.
+
+ ======= =====
+ LED RGB PINS
+ ======= =====
+ LED_R PG2
+ LED_G PG3
+ LED_B PB2
+ ======= =====
+
+UART/USART
+----------
+
+The LINUM-STM32H753BI used the USART1 for serial console.
+
+USART1
+------
+
+ ====== =====
+ USART1 PINS
+ ====== =====
+ TX PB14
+ RX PB15
+ ====== =====
+
+The LINUM-STM32H753BI board has two on-board RS-232 transceiver connected to USART2 and USART3.
+
+ ====== =====
+ USART2 PINS
+ ====== =====
+ TXD PD5
+ RXD PD6
+ CTS PD3
+ RTS PD4
+ ====== =====
+
+ ====== =====
+ USART3 PINS
+ ====== =====
+ TXD PB10
+ RXD PB11
+ CTS PD11
+ RTS PD12
+ ====== =====
+
+The LINUM-STM32H753BI board has two on-board RS-485 transceiver connected to USART4 and USART6.
+
+ ====== =====
+ UART4 PINS
+ ====== =====
+ TXD PB9
+ RXD PB8
+ DE PA15
+ ====== =====
+
+ ====== =====
+ USART6 PINS
+ ====== =====
+ TXD PC6
+ RXD PC7
+ DE PG12
+ ====== =====
+
+SDMMC
+-----
+
+The LINUM-STM32H753BI has one SDCard slot connected as below:
+
+ ========== =====
+ SDMMC1 PINS
+ ========== =====
+ SDMMC_D0 PC8
+ SDMMC_D1 PC9
+ SDMMC_D2 PC10
+ SDMMC_D3 PC11
+ SDMMC_DK PC12
+ ========== =====
+
+ =============== =====
+ GPIO PINS
+ =============== =====
+ SDCARD_DETECTED PG7
+ SDCARD_PWR_EN PD7
+ =============== =====
+
+ETHERNET
+--------
+
+The LINUM-STM32H753BI has a ethernet connection using the transceiver KSZ8081RNACA.
+
+ ============ =====
+ ETH PINS
+ ============ =====
+ ETH_REF_CLK PA1
+ ETH_MDIO PA2
+ ETH_CRS_DV PA7
+ ETH_MDC PC1
+ ETH_RXD0 PC4
+ ETH_RXD1 PC5
+ ETH_TX_EN PG11
+ ETH_TXD0 PG13
+ ETH_TXD1 PG14
+ ETH_CLK PA8
+ ETH_RESET PI4
+ ============ =====
+
+CAN-FD
+------
+
+The LINUM-STM32H753BI board has two on-board CAN-FD transceiver connected to FDCAN1 and FDCAN2.
+
+ ====== =====
+ FDCAN1 PINS
+ ====== =====
+ TXD PH13
+ RXD PH14
+ STD PI2
+ ====== =====
+
+ ====== =====
+ FDCAN2 PINS
+ ====== =====
+ TXD PB13
+ RXD PB12
+ STD PE3
+ ====== =====
+
+USB
+---
+
+The LINUM-STM32H753BI has one usb port.
+
+ ========= =====
+ USB PINS
+ ========= =====
+ USB_VBUS PA9
+ USB_N PA11
+ USB_P PA12
+ USB_EN PI12
+ USB_FLT PI13
+ ========= =====
+
+I2C3
+----
+The LINUM-STM32H753BI connects the EEPROM memory and the touchscreen sensor to I2C3.
+
+ ====== =====
+ I2C3 PINS
+ ====== =====
+ SCL PH7
+ SDA PH8
+ ====== =====
+
+External SDRAM
+--------------
+The LINUM-STM32H753BI has a external SDRAM with 8Mbytes connected to FMC peripheral.
+
+ =========== =====
+ FMC PINS
+ =========== =====
+ FMC_A0 PF0
+ FMC_A1 PF1
+ FMC_A2 PF2
+ FMC_A3 PF3
+ FMC_A4 PF4
+ FMC_A5 PF5
+ FMC_A6 PF12
+ FMC_A7 PF13
+ FMC_A8 PF14
+ FMC_A9 PF15
+ FMC_A10 PG0
+ FMC_A11 PG1
+ FMC_BA0 PG4
+ FMC_BA1 PG5
+ FMC_D0 PD14
+ FMC_D1 PD15
+ FMC_D2 PD0
+ FMC_D3 PD1
+ FMC_D4 PE7
+ FMC_D5 PE8
+ FMC_D6 PE9
+ FMC_D7 PE10
+ FMC_D8 PE11
+ FMC_D9 PE12
+ FMC_D10 PE13
+ FMC_D11 PE14
+ FMC_D12 PE15
+ FMC_D13 PD8
+ FMC_D14 PD9
+ FMC_D15 PD10
+ FMC_NBL0 PE0
+ FMC_NBL1 PE1
+ FMC_SDCKE0 PC3
+ FMC_SDCLK PG8
+ FMC_SDNCAS PG15
+ FMC_SDNEO PC2
+ FMC_SDNRAS PF11
+ FMC_SDNWE PC0
+ =========== =====
+
+LCD
+---
+The LINUM-STM32H753BI use the LTDC to support one LCD with RGB connection.
+
+ ============= =====
+ LTDC PINS
+ ============= =====
+ LTDC_B0 PJ12
+ LTDC_B1 PJ13
+ LTDC_B2 PJ14
+ LTDC_B3 PJ15
+ LTDC_B4 PK3
+ LTDC_B5 PK4
+ LTDC_B6 PK5
+ LTDC_B7 PK6
+ LTDC_CLK PI14
+ LTDC_DE PK7
+ LTDC_G0 PJ7
+ LTDC_G1 PJ8
+ LTDC_G2 PJ9
+ LTDC_G3 PJ10
+ LTDC_G4 PJ11
+ LTDC_G5 PK0
+ LTDC_G6 PK1
+ LTDC_G7 PK2
+ LTDC_HSYNC PI10
+ LTDC_R0 PI15
+ LTDC_R1 PJ0
+ LTDC_R2 PJ1
+ LTDC_R3 PJ2
+ LTDC_R4 PJ3
+ LTDC_R5 PJ4
+ LTDC_R6 PJ5
+ LTDC_R7 PJ6
+ LTDC_VSYNC PI9
+ PWM_BACKLIGHT PH6
+ ============= =====
+
+System Clock
+------------
+
+Linum H753ZI System Clock could be driven by an internal or external
+oscillator, as well as the main PLL clock. By default, the System clock is
+driven by the PLL clock at 480MHz, driven by an 25MHz high-speed external clock.
+
+
+Programming and Debugging
+*************************
+
+Applications for the ``linum`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. note::
+
+ For debugging or programming Linum you will need to use an external debug
+ debug or flash tool and connect it to the SWD Connnector. JLink or ST-Link
+ probes are examples of out of the box compatible tools.
+
+Flashing
+========
+
+Flashing an application to the Linum board
+-------------------------------------------
+
+Here is an example for the :ref:`hello_world` application.
+
+Run a serial host program to connect with your Nucleo board.
+
+.. code-block:: console
+
+ $ minicom -b 115200 -D /dev/ttyACM0
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: linum
+ :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+ $ Hello World! linum
+
+Debugging
+=========
+
+You can debug an application in the usual way. Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: linum
+ :maybe-skip-config:
+ :goals: debug
+
+.. _Witte Linum website:
+ https://wittetech.com/
diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts
new file mode 100644
index 0000000..d4846f3
--- /dev/null
+++ b/boards/witte/linum/linum.dts
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2024 Felipe Neves
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h753Xi.dtsi>
+#include <st/h7/stm32h753bitx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "Witte Technology STM32H753ZI Linum board";
+ compatible = "witte,linum";
+
+ chosen {
+ zephyr,console = &usart1;
+ zephyr,shell-uart = &usart1;
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,dtcm = &dtcm;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,canbus = &fdcan1;
+ };
+
+ sdram1: sdram@c0000000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ device_type = "memory";
+ reg = <0xc0000000 DT_SIZE_M(8)>;
+ zephyr,memory-region = "SDRAM1";
+ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ green_led: led_0 {
+ gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+ label = "User LD1";
+ };
+ red_led: led_1 {
+ gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
+ label = "User LD2";
+ };
+ blue_led: led_2 {
+ gpios = <&gpiog 3 GPIO_ACTIVE_LOW>;
+ label = "User LD3";
+ };
+
+ };
+
+ aliases {
+ led0 = &green_led;
+ led1 = &blue_led;
+ };
+};
+
+&gpiod {
+ status = "okay";
+
+ /* power the SD card */
+ mcu-sel-gpios {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
+&gpioi {
+ status = "okay";
+ /* power the ETH PHY , and FDCAN1 XVCR*/
+ mcu-sel-gpios {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>,
+ <4 GPIO_ACTIVE_HIGH>;
+
+ output-high;
+ };
+};
+
+&gpioe {
+ status = "okay";
+
+ /* power FDCAN2 XVCR*/
+ mcu-sel-gpios {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>,
+ <4 GPIO_ACTIVE_HIGH>;
+
+ output-high;
+ };
+};
+
+&clk_lsi {
+ status = "okay";
+};
+
+&clk_hsi48 {
+ status = "okay";
+};
+
+&clk_hse {
+ /delete-property/ hse-bypass;
+ clock-frequency = <DT_FREQ_M(25)>;
+ status = "okay";
+};
+
+&pll {
+ div-m = <5>;
+ mul-n = <192>;
+ div-p = <2>;
+ div-q = <4>;
+ div-r = <4>;
+ clocks = <&clk_hse>;
+ status = "okay";
+};
+
+&pll2 {
+ div-m = <2>;
+ mul-n = <48>;
+ div-p = <8>;
+ div-q = <40>;
+ div-r = <3>;
+ clocks = <&clk_hse>;
+ status = "okay";
+};
+
+&rcc {
+ clocks = <&pll>;
+ clock-frequency = <DT_FREQ_M(480)>;
+ d1cpre = <1>;
+ hpre = <2>;
+ d1ppre = <2>;
+ d2ppre1 = <2>;
+ d2ppre2 = <2>;
+ d3ppre = <2>;
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&usart3 {
+ pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&usart6 {
+ pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
+ pinctrl-names = "default";
+ current-speed = <115200>;
+ status = "okay";
+};
+
+zephyr_udc0: &usbotg_fs {
+ pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
+ <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
+ pinctrl-names = "default";
+ status = "okay";
+ clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&timers12 {
+ st,prescaler = <10000>;
+ status = "okay";
+
+ pwm12: pwm {
+ status = "okay";
+ pinctrl-0 = <&tim12_ch1_pb14>;
+ pinctrl-names = "default";
+ };
+};
+
+&adc1 {
+ pinctrl-0 = <&adc1_inp15_pa3>;
+ pinctrl-names = "default";
+ st,adc-clock-source = <SYNC>;
+ st,adc-prescaler = <4>;
+ status = "okay";
+};
+
+&rng {
+ status = "okay";
+};
+
+&fdcan1 {
+ clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+ <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
+ pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&fdcan2 {
+ clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+ <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
+ pinctrl-0 = <&fdcan2_rx_pb12 &fdcan2_tx_pb13>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ð_rxd0_pc4
+ ð_rxd1_pc5
+ ð_ref_clk_pa1
+ ð_crs_dv_pa7
+ ð_tx_en_pg11
+ ð_txd0_pg13
+ ð_txd1_pg14>;
+ pinctrl-names = "default";
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
+ pinctrl-names = "default";
+
+ ethernet-phy@0 {
+ compatible = "microchip,ksz8081";
+ reg = <0x00>;
+ status = "okay";
+ microchip,interface-type = "rmii-25MHz";
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+};
+
+&fmc {
+ pinctrl-0 = <&fmc_nbl0_pe0
+ &fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
+ &fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15
+ &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
+ &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
+ &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
+ &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
+ &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
+ &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
+ &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
+ &fmc_d15_pd10>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ sdram {
+ status = "okay";
+ power-up-delay = <100>;
+ num-auto-refresh = <8>;
+ mode-register = <0x220>;
+ refresh-rate = <0x603>;
+ bank@1 {
+ reg = <1>;
+ st,sdram-control = <STM32_FMC_SDRAM_NC_8
+ STM32_FMC_SDRAM_NR_12
+ STM32_FMC_SDRAM_MWID_16
+ STM32_FMC_SDRAM_NB_4
+ STM32_FMC_SDRAM_CAS_3
+ STM32_FMC_SDRAM_SDCLK_PERIOD_2
+ STM32_FMC_SDRAM_RBURST_ENABLE
+ STM32_FMC_SDRAM_RPIPE_0>;
+ st,sdram-timing = <2 7 4 7 2 2 2>;
+ };
+ };
+};
+
+<dc {
+ pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2
+ <dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6
+ <dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10
+ <dc_g4_pj11 <dc_g5_pk0 <dc_g6_pk1 <dc_g7_pk2
+ <dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15
+ <dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6
+ <dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi10 <dc_vsync_pi9>;
+ pinctrl-names = "default";
+
+ disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
+
+ ext-sdram = <&sdram1>;
+ status = "okay";
+
+ clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
+ <&rcc STM32_SRC_PLL3_R NO_SEL>;
+
+ width = <480>;
+ height = <272>;
+ pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+ display-timings {
+ compatible = "zephyr,panel-timing";
+ de-active = <1>;
+ pixelclk-active = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ hsync-len = <1>;
+ vsync-len = <10>;
+ hback-porch = <43>;
+ vback-porch = <12>;
+ hfront-porch = <8>;
+ vfront-porch = <4>;
+ };
+ def-back-color-red = <0xFF>;
+ def-back-color-green = <0xFF>;
+ def-back-color-blue = <0xFF>;
+};
+
+&sdmmc1 {
+ pinctrl-0 = <&sdmmc1_d0_pc8
+ &sdmmc1_d1_pc9
+ &sdmmc1_d2_pc10
+ &sdmmc1_d3_pc11
+ &sdmmc1_ck_pc12
+ &sdmmc1_cmd_pd2>;
+ pinctrl-names = "default";
+ cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ disk {
+ status = "okay";
+ };
+};
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* 128KB for bootloader */
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 DT_SIZE_K(128)>;
+ read-only;
+ };
+
+ /* storage: 128KB for settings */
+ storage_partition: partition@20000 {
+ label = "storage";
+ reg = <0x00020000 DT_SIZE_K(128)>;
+ };
+
+ /* application image slot: 256KB */
+ slot0_partition: partition@40000 {
+ label = "image-0";
+ reg = <0x00040000 DT_SIZE_K(256)>;
+ };
+
+ /* backup slot: 256KB */
+ slot1_partition: partition@80000 {
+ label = "image-1";
+ reg = <0x00080000 DT_SIZE_K(256)>;
+ };
+
+ /* swap slot: 128KB */
+ scratch_partition: partition@c0000 {
+ label = "image-scratch";
+ reg = <0x000c0000 DT_SIZE_K(128)>;
+ };
+
+ };
+};
diff --git a/boards/witte/linum/linum.yaml b/boards/witte/linum/linum.yaml
new file mode 100644
index 0000000..3242d57
--- /dev/null
+++ b/boards/witte/linum/linum.yaml
@@ -0,0 +1,21 @@
+identifier: linum
+name: Linum
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+ram: 512
+flash: 2048
+supported:
+ - uart
+ - gpio
+ - counter
+ - i2c
+ - pwm
+ - netif:eth
+ - spi
+ - usb_device
+ - can
+vendor: witte
diff --git a/boards/witte/linum/linum_defconfig b/boards/witte/linum/linum_defconfig
new file mode 100644
index 0000000..8dcaab6
--- /dev/null
+++ b/boards/witte/linum/linum_defconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART
+CONFIG_SERIAL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable clocks
+CONFIG_CLOCK_CONTROL=y
+
+# enable pin controller
+CONFIG_PINCTRL=y
diff --git a/boards/witte/linum/support/openocd.cfg b/boards/witte/linum/support/openocd.cfg
new file mode 100644
index 0000000..89d4f7a
--- /dev/null
+++ b/boards/witte/linum/support/openocd.cfg
@@ -0,0 +1,21 @@
+source [find board/st_nucleo_h743zi.cfg]
+
+reset_config srst_only srst_nogate connect_assert_srst
+
+$_CHIPNAME.cpu0 configure -event gdb-attach {
+ echo "Debugger attaching: halting execution"
+ gdb_breakpoint_override hard
+}
+
+$_CHIPNAME.cpu0 configure -event gdb-detach {
+ echo "Debugger detaching: resuming execution"
+ resume
+}
+
+# Due to the use of connect_assert_srst, running gdb requires
+# to reset halt just after openocd init.
+rename init old_init
+proc init {} {
+ old_init
+ reset halt
+}
diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake
index 6a3dd40..091da6f 100644
--- a/cmake/linker_script/common/common-ram.cmake
+++ b/cmake/linker_script/common/common-ram.cmake
@@ -55,6 +55,10 @@
zephyr_iterable_section(NAME eth_bridge GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN)
endif()
+if(CONFIG_ARM_SCMI)
+ zephyr_iterable_section(NAME scmi_protocol GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN)
+endif()
+
if(CONFIG_SENSING)
zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN)
endif()
diff --git a/cmake/modules/FindZephyr-sdk.cmake b/cmake/modules/FindZephyr-sdk.cmake
index dae75f2..b1c1c8c 100644
--- a/cmake/modules/FindZephyr-sdk.cmake
+++ b/cmake/modules/FindZephyr-sdk.cmake
@@ -4,29 +4,51 @@
# FindZephyr-sdk module for supporting module search mode of Zephyr SDK.
#
-# Its purpose is to allow the find_package basic signature mode to lookup Zephyr
-# SDK and based on user / environment settings of selected toolchain decide if
-# the Zephyr SDK CMake package should be loaded.
+# It is possible to control the behavior of the Zephyr-SDK package using
+# COMPONENTS.
+# The Zephyr-SDK package supports the components:
+# - LOAD: Load a Zephyr-SDK. This is the default behavior if no COMPONENTS is specified.
+# Its purpose is to allow the find_package basic signature mode to lookup Zephyr
+# SDK and based on user / environment settings of selected toolchain decide if
+# the Zephyr SDK CMake package should be loaded.
#
-# It extends the Zephyr-sdk CMake package by providing more flexibility in when
-# the Zephyr SDK is loaded and loads additional host tools from the Zephyr SDK.
+# It extends the Zephyr-sdk CMake package by providing more flexibility in when
+# the Zephyr SDK is loaded and loads additional host tools from the Zephyr SDK.
#
-# The module defines the following variables:
+# The module defines the following variables when used in normal search and load mode:
+# 'ZEPHYR_SDK_INSTALL_DIR'
+# Install location of the Zephyr SDK
#
-# 'ZEPHYR_SDK_INSTALL_DIR'
-# Install location of the Zephyr SDK
+# 'ZEPHYR_TOOLCHAIN_VARIANT'
+# Zephyr toolchain variant to use if not defined already.
#
-# 'ZEPHYR_TOOLCHAIN_VARIANT'
-# Zephyr toolchain variant to use if not defined already.
+# 'Zephyr-sdk_FOUND'
+# True if the Zephyr SDK was found.
+
+# - LIST: Will list all available Zephyr SDKs found in the system but not load
+# any Sdk. This can be used to fetch available Zephyr-SDKs before doing
+# an actual load.
+# LIST component will define the following lists:
+# - Zephyr-sdk : Version of a Zephyr-SDK
+# - Zephyr-sdk_DIRS : Install dir of the Zephyr-SDK
+# Each entry in Zephyr-SDK has a corresponding entry in Zephyr-SDK_DIRS.
+# For example:
+# index: Zephyr-sdk: Zephyr-sdk_DIRS:
+# 0 0.15.0 /opt/zephyr-sdk-0.15.0
+# 1 0.16.0 /home/<user>/zephyr-sdk-0.16.0
#
-# 'Zephyr-sdk_FOUND'
-# True if the Zephyr SDK was found.
+
+include(extensions)
# Set internal variables if set in environment.
zephyr_get(ZEPHYR_TOOLCHAIN_VARIANT)
zephyr_get(ZEPHYR_SDK_INSTALL_DIR)
+if("${Zephyr-sdk_FIND_COMPONENTS}" STREQUAL "")
+ set(Zephyr-sdk_FIND_COMPONENTS LOAD)
+endif()
+
# Load Zephyr SDK Toolchain.
# There are three scenarios where Zephyr SDK should be looked up:
# 1) Zephyr specified as toolchain (ZEPHYR_SDK_INSTALL_DIR still used if defined)
@@ -38,7 +60,8 @@
(Zephyr-sdk_FIND_REQUIRED))
# No toolchain was specified, so inform user that we will be searching.
- if (NOT DEFINED ZEPHYR_SDK_INSTALL_DIR AND
+ if (NOT Zephyr-sdk_FIND_QUIETLY AND
+ NOT DEFINED ZEPHYR_SDK_INSTALL_DIR AND
NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT)
message(STATUS "ZEPHYR_TOOLCHAIN_VARIANT not set, trying to locate Zephyr SDK")
endif()
@@ -49,7 +72,7 @@
SET(CMAKE_FIND_PACKAGE_SORT_DIRECTION DEC)
SET(CMAKE_FIND_PACKAGE_SORT_ORDER NATURAL)
- if(DEFINED ZEPHYR_SDK_INSTALL_DIR)
+ if(DEFINED ZEPHYR_SDK_INSTALL_DIR AND LOAD IN_LIST Zephyr-sdk_FIND_COMPONENTS)
# The Zephyr SDK will automatically set the toolchain variant.
# To support Zephyr SDK tools (DTC, and other tools) with 3rd party toolchains
# then we keep track of current toolchain variant.
@@ -77,36 +100,53 @@
find_package(Zephyr-sdk 0.0.0 EXACT QUIET CONFIG PATHS ${zephyr_sdk_search_paths})
# Remove duplicate entries and sort naturally in descending order.
- set(zephyr_sdk_found_versions ${Zephyr-sdk_CONSIDERED_VERSIONS})
- set(zephyr_sdk_found_configs ${Zephyr-sdk_CONSIDERED_CONFIGS})
+ foreach(version config IN ZIP_LISTS Zephyr-sdk_CONSIDERED_VERSIONS Zephyr-sdk_CONSIDERED_CONFIGS)
+ if(NOT DEFINED Zephyr-sdk-${version}_DIR)
+ set(Zephyr-sdk-${version}_DIR ${config})
+ endif()
+ endforeach()
list(REMOVE_DUPLICATES Zephyr-sdk_CONSIDERED_VERSIONS)
list(SORT Zephyr-sdk_CONSIDERED_VERSIONS COMPARE NATURAL ORDER DESCENDING)
- # Loop over each found Zepher SDK version until one is found that is compatible.
- foreach(zephyr_sdk_candidate ${Zephyr-sdk_CONSIDERED_VERSIONS})
- if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}")
- # Find the path for the current version being checked and get the directory
- # of the Zephyr SDK so it can be checked.
- list(FIND zephyr_sdk_found_versions ${zephyr_sdk_candidate} zephyr_sdk_current_index)
- list(GET zephyr_sdk_found_configs ${zephyr_sdk_current_index} zephyr_sdk_current_check_path)
- get_filename_component(zephyr_sdk_current_check_path ${zephyr_sdk_current_check_path} DIRECTORY)
-
- # Then see if this version is compatible.
- find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH)
-
- if (${Zephyr-sdk_FOUND})
- # A compatible version of the Zephyr SDK has been found which is the highest
- # supported version, exit.
- break()
+ if(LIST IN_LIST Zephyr-sdk_FIND_COMPONENTS)
+ set(Zephyr-sdk)
+ set(Zephyr-sdk_DIRS)
+ # Only list the Zephyr SDKs installed in the system.
+ foreach(version ${Zephyr-sdk_CONSIDERED_VERSIONS})
+ cmake_path(GET Zephyr-sdk-${version}_DIR PARENT_PATH dir)
+ cmake_path(GET dir PARENT_PATH dir)
+ list(APPEND Zephyr-sdk ${version})
+ list(APPEND Zephyr-sdk_DIRS ${dir})
+ if (NOT Zephyr-sdk_FIND_QUIETLY)
+ message(STATUS "Zephyr-sdk, version=${version}, dir=${dir}")
endif()
- endif()
- endforeach()
+ endforeach()
+ else()
+ # Loop over each found Zepher SDK version until one is found that is compatible.
+ foreach(zephyr_sdk_candidate ${Zephyr-sdk_CONSIDERED_VERSIONS})
+ if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}")
+ # Find the path for the current version being checked and get the directory
+ # of the Zephyr SDK so it can be checked.
+ cmake_path(GET Zephyr-sdk-${zephyr_sdk_candidate}_DIR PARENT_PATH zephyr_sdk_current_check_path)
+ cmake_path(GET zephyr_sdk_current_check_path PARENT_PATH zephyr_sdk_current_check_path)
- if (NOT ${Zephyr-sdk_FOUND})
- # This means no compatible Zephyr SDK versions were found, set the version
- # back to the minimum version so that it is displayed in the error text.
- find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths})
+ # Then see if this version is compatible.
+ find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH)
+
+ if (${Zephyr-sdk_FOUND})
+ # A compatible version of the Zephyr SDK has been found which is the highest
+ # supported version, exit.
+ break()
+ endif()
+ endif()
+ endforeach()
+
+ if (NOT ${Zephyr-sdk_FOUND})
+ # This means no compatible Zephyr SDK versions were found, set the version
+ # back to the minimum version so that it is displayed in the error text.
+ find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths})
+ endif()
endif()
endif()
@@ -121,13 +161,17 @@
set(zephyr_sdk_current_index)
set(zephyr_sdk_current_check_path)
-if(DEFINED ZEPHYR_SDK_INSTALL_DIR)
- # Cache the Zephyr SDK install dir.
- set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory")
-endif()
+if(LOAD IN_LIST Zephyr-sdk_FIND_COMPONENTS)
+ if(DEFINED ZEPHYR_SDK_INSTALL_DIR)
+ # Cache the Zephyr SDK install dir.
+ set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory")
+ endif()
-if(Zephyr-sdk_FOUND)
- include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake)
+ if(Zephyr-sdk_FOUND)
+ include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake)
- message(STATUS "Found host-tools: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})")
+ if (NOT Zephyr-sdk_FIND_QUIETLY)
+ message(STATUS "Found host-tools: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})")
+ endif()
+ endif()
endif()
diff --git a/doc/_doxygen/doxygen-awesome-sidebar-only-darkmode-toggle.css b/doc/_doxygen/doxygen-awesome-sidebar-only-darkmode-toggle.css
index 7114a03..d207446 100644
--- a/doc/_doxygen/doxygen-awesome-sidebar-only-darkmode-toggle.css
+++ b/doc/_doxygen/doxygen-awesome-sidebar-only-darkmode-toggle.css
@@ -1,3 +1,4 @@
+
/**
Doxygen Awesome
diff --git a/doc/_doxygen/doxygen-awesome.css b/doc/_doxygen/doxygen-awesome.css
index 05ecbfe..98b835c 100644
--- a/doc/_doxygen/doxygen-awesome.css
+++ b/doc/_doxygen/doxygen-awesome.css
@@ -313,7 +313,7 @@
body, table, div, p, dl, #nav-tree .label, .title,
.sm-dox a, .sm-dox a:hover, .sm-dox a:focus, #projectname,
.SelectItem, #MSearchField, .navpath li.navelem a,
-.navpath li.navelem a:hover, p.reference, p.definition {
+.navpath li.navelem a:hover, p.reference, p.definition, div.toc li, div.toc h3 {
font-family: var(--font-family);
}
@@ -334,6 +334,7 @@
a:link, a:visited, a:hover, a:focus, a:active {
color: var(--primary-color) !important;
font-weight: 500;
+ background: none;
}
a.anchor {
@@ -806,6 +807,10 @@
line-height: var(--tree-item-height);
}
+#nav-tree .item > a:focus {
+ outline: none;
+}
+
#nav-sync {
bottom: 12px;
right: 12px;
@@ -843,6 +848,7 @@
#nav-tree .arrow {
opacity: var(--side-nav-arrow-opacity);
+ background: none;
}
.arrow {
@@ -1040,7 +1046,7 @@
blockquote p {
margin: var(--spacing-small) 0 var(--spacing-medium) 0;
}
-.paramname {
+.paramname, .paramname em {
font-weight: 600;
color: var(--primary-dark-color);
}
@@ -1090,7 +1096,7 @@
border: 0;
border-left: 1px solid var(--separator-color);
border-radius: 0;
- background-color: transparent;
+ background-color: var(--page-background-color);
box-shadow: none;
position: sticky;
top: var(--toc-sticky-top);
@@ -1982,14 +1988,16 @@
}
.contents hr {
- box-shadow: 100px 0 0 var(--separator-color),
- -100px 0 0 var(--separator-color),
- 500px 0 0 var(--separator-color),
- -500px 0 0 var(--separator-color),
- 1500px 0 0 var(--separator-color),
- -1500px 0 0 var(--separator-color),
- 2000px 0 0 var(--separator-color),
- -2000px 0 0 var(--separator-color);
+ box-shadow: 100px 0 var(--separator-color),
+ -100px 0 var(--separator-color),
+ 500px 0 var(--separator-color),
+ -500px 0 var(--separator-color),
+ 900px 0 var(--separator-color),
+ -900px 0 var(--separator-color),
+ 1400px 0 var(--separator-color),
+ -1400px 0 var(--separator-color),
+ 1900px 0 var(--separator-color),
+ -1900px 0 var(--separator-color);
}
.contents img, .contents .center, .contents center, .contents div.image object {
@@ -2460,17 +2468,17 @@
Optional tab feature
*/
-.tabbed ul {
+.tabbed > ul {
padding-inline-start: 0px;
margin: 0;
padding: var(--spacing-small) 0;
}
-.tabbed li {
+.tabbed > ul > li {
display: none;
}
-.tabbed li.selected {
+.tabbed > ul > li.selected {
display: block;
}
diff --git a/doc/_doxygen/footer.html b/doc/_doxygen/footer.html
deleted file mode 100644
index efa3357..0000000
--- a/doc/_doxygen/footer.html
+++ /dev/null
@@ -1,17 +0,0 @@
-<!-- HTML footer for doxygen 1.9.1-->
-<!-- start footer part -->
-<!--BEGIN GENERATE_TREEVIEW-->
-<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
- <ul>
- $navpath
- <li class="footer">$generatedby <a href="https://www.doxygen.org/index.html"><img class="footer" src="$relpath^doxygen.svg" width="104" height="31" alt="doxygen"/></a> $doxygenversion </li>
- </ul>
-</div>
-<!--END GENERATE_TREEVIEW-->
-<!--BEGIN !GENERATE_TREEVIEW-->
-<hr class="footer"/><address class="footer"><small>
-$generatedby <a href="https://www.doxygen.org/index.html"><img class="footer" src="$relpath^doxygen.svg" width="104" height="31" alt="doxygen"/></a> $doxygenversion
-</small></address>
-<!--END !GENERATE_TREEVIEW-->
-</body>
-</html>
diff --git a/doc/_doxygen/header.html b/doc/_doxygen/header.html
index 06be6c6..e5e914e 100644
--- a/doc/_doxygen/header.html
+++ b/doc/_doxygen/header.html
@@ -1,16 +1,27 @@
-<!-- HTML header for doxygen 1.9.1-->
+<!-- HTML header for doxygen 1.12.0-->
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-<html xmlns="http://www.w3.org/1999/xhtml">
+<html xmlns="http://www.w3.org/1999/xhtml" lang="$langISO">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
-<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta http-equiv="X-UA-Compatible" content="IE=11"/>
<meta name="generator" content="Doxygen $doxygenversion"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<!--BEGIN PROJECT_NAME--><title>$projectname: $title</title><!--END PROJECT_NAME-->
<!--BEGIN !PROJECT_NAME--><title>$title</title><!--END !PROJECT_NAME-->
+<!--BEGIN PROJECT_ICON-->
+<link rel="icon" href="$relpath^$projecticon" type="image/x-icon" />
+<!--END PROJECT_ICON-->
<link href="$relpath^tabs.css" rel="stylesheet" type="text/css"/>
+<!--BEGIN DISABLE_INDEX-->
+ <!--BEGIN FULL_SIDEBAR-->
+<script type="text/javascript">var page_layout=1;</script>
+ <!--END FULL_SIDEBAR-->
+<!--END DISABLE_INDEX-->
<script type="text/javascript" src="$relpath^jquery.js"></script>
<script type="text/javascript" src="$relpath^dynsections.js"></script>
+<!--BEGIN COPY_CLIPBOARD-->
+<script type="text/javascript" src="$relpath^clipboard.js"></script>
+<!--END COPY_CLIPBOARD-->
<script type="text/javascript" src="$relpath^doxygen-awesome-darkmode-toggle.js"></script>
<script type="text/javascript" src="$relpath^doxygen-awesome-zephyr.js"></script>
<script type="text/javascript">
@@ -19,41 +30,54 @@
$treeview
$search
$mathjax
+$darkmode
<link href="$relpath^$stylesheet" rel="stylesheet" type="text/css" />
$extrastylesheet
</head>
<body>
+<!--BEGIN DISABLE_INDEX-->
+ <!--BEGIN FULL_SIDEBAR-->
+<div id="side-nav" class="ui-resizable side-nav-resizable"><!-- do not remove this div, it is closed by doxygen! -->
+ <!--END FULL_SIDEBAR-->
+<!--END DISABLE_INDEX-->
+
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<!--BEGIN TITLEAREA-->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
<tbody>
- <tr style="height: 56px;">
+ <tr id="projectrow">
<!--BEGIN PROJECT_LOGO-->
- <td id="projectlogo"><img alt="Logo" src="$relpath^$projectlogo"/></td>
+ <td id="projectlogo"><img alt="Logo" src="$relpath^$projectlogo"$logosize/></td>
<!--END PROJECT_LOGO-->
<!--BEGIN PROJECT_NAME-->
- <td id="projectalign" style="padding-left: 0.5em;">
- <div id="projectname">$projectname
- <!--BEGIN PROJECT_NUMBER--> <span id="projectnumber">$projectnumber</span><!--END PROJECT_NUMBER-->
+ <td id="projectalign">
+ <div id="projectname">$projectname<!--BEGIN PROJECT_NUMBER--><span id="projectnumber"> $projectnumber</span><!--END PROJECT_NUMBER-->
</div>
<!--BEGIN PROJECT_BRIEF--><div id="projectbrief">$projectbrief</div><!--END PROJECT_BRIEF-->
</td>
<!--END PROJECT_NAME-->
<!--BEGIN !PROJECT_NAME-->
<!--BEGIN PROJECT_BRIEF-->
- <td style="padding-left: 0.5em;">
+ <td>
<div id="projectbrief">$projectbrief</div>
</td>
<!--END PROJECT_BRIEF-->
<!--END !PROJECT_NAME-->
<!--BEGIN DISABLE_INDEX-->
<!--BEGIN SEARCHENGINE-->
- <td>$searchbox</td>
+ <!--BEGIN !FULL_SIDEBAR-->
+ <td>$searchbox</td>
+ <!--END !FULL_SIDEBAR-->
<!--END SEARCHENGINE-->
<!--END DISABLE_INDEX-->
</tr>
+ <!--BEGIN SEARCHENGINE-->
+ <!--BEGIN FULL_SIDEBAR-->
+ <tr><td colspan="2">$searchbox</td></tr>
+ <!--END FULL_SIDEBAR-->
+ <!--END SEARCHENGINE-->
</tbody>
</table>
</div>
diff --git a/doc/_extensions/zephyr/domain.py b/doc/_extensions/zephyr/domain.py
index 92bb50c..df79951 100644
--- a/doc/_extensions/zephyr/domain.py
+++ b/doc/_extensions/zephyr/domain.py
@@ -88,8 +88,11 @@
"""
Transforms a `CodeSampleNode` into a `nodes.section` named after the code sample name.
- Moves all sibling nodes that are after the `CodeSampleNode` in the documement under this new
+ Moves all sibling nodes that are after the `CodeSampleNode` in the document under this new
section.
+
+ Adds a "See Also" section at the end with links to all relevant APIs as per the samples's
+ `relevant-api` attribute.
"""
parent = node.parent
siblings_to_move = []
@@ -111,6 +114,31 @@
for sibling in siblings_to_move:
parent.remove(sibling)
+ # Add a "See Also" section at the end with links to relevant APIs
+ if node["relevant-api"]:
+ see_also_section = nodes.section(ids=["see-also"])
+ see_also_section += nodes.title(text="See also")
+
+ for api in node["relevant-api"]:
+ desc_node = addnodes.desc()
+ desc_node["domain"] = "c"
+ desc_node["objtype"] = "group"
+
+ title_signode = addnodes.desc_signature()
+ api_xref = addnodes.pending_xref(
+ "",
+ refdomain="c",
+ reftype="group",
+ reftarget=api,
+ refwarn=True,
+ )
+ api_xref += nodes.Text(api)
+ title_signode += api_xref
+ desc_node += title_signode
+ see_also_section += desc_node
+
+ new_section += see_also_section
+
# Set sample description as the meta description of the document for improved SEO
meta_description = nodes.meta()
meta_description["name"] = "description"
@@ -231,6 +259,7 @@
code_sample_node = CodeSampleNode()
code_sample_node["id"] = code_sample_id
code_sample_node["name"] = name
+ code_sample_node["relevant-api"] = relevant_api_list
code_sample_node += description_node
return [code_sample_node]
diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py
index 337685e..6052db6 100644
--- a/doc/_extensions/zephyr/kconfig/__init__.py
+++ b/doc/_extensions/zephyr/kconfig/__init__.py
@@ -231,14 +231,14 @@
object_types = {"option": ObjType("option", "option")}
roles = {"option": XRefRole()}
directives = {"search": KconfigSearch}
- initial_data: Dict[str, Any] = {"options": []}
+ initial_data: Dict[str, Any] = {"options": set()}
def get_objects(self) -> Iterable[Tuple[str, str, str, str, str, int]]:
for obj in self.data["options"]:
yield obj
def merge_domaindata(self, docnames: List[str], otherdata: Dict) -> None:
- self.data["options"] += otherdata["options"]
+ self.data["options"].update(otherdata["options"])
def resolve_xref(
self,
@@ -268,7 +268,7 @@
def add_option(self, option):
"""Register a new Kconfig option to the domain."""
- self.data["options"].append(
+ self.data["options"].add(
(option, option, "option", self.env.docname, option, 1)
)
diff --git a/doc/_extensions/zephyr/warnings_filter.py b/doc/_extensions/zephyr/warnings_filter.py
deleted file mode 100644
index 9239776..0000000
--- a/doc/_extensions/zephyr/warnings_filter.py
+++ /dev/null
@@ -1,133 +0,0 @@
-"""
-Warnings filter extension
-#########################
-
-Copyright (c) 2021 Nordic Semiconductor ASA
-SPDX-License-Identifier: Apache-2.0
-
-Introduction
-============
-
-This Sphinx plugin can be used to filter out warnings that are known to be false
-positives. The warnings are filtered out based on a set of regular expressions
-given via an configuration file. The format of the configuration file is a
-plain-text file where each line consists of a regular expression. Any lines
-starting with ``#`` will be ignored.
-
-Configuration options
-=====================
-
-- ``warnings_filter_config``: Configuration file.
-- ``warnings_filter_silent``: Silent flag. If True, warning is hidden. If False
- the warning is converted to an information message and displayed.
-"""
-
-import logging
-import re
-from typing import Dict, Any, List, Optional
-
-from sphinx.application import Sphinx
-from sphinx.util.logging import NAMESPACE
-
-
-__version__ = "0.1.0"
-
-
-class WarningsFilter(logging.Filter):
- """Warnings filter.
-
- Args:
- expressions: List of regular expressions.
- silent: If true, warning is hidden, otherwise it is shown as INFO.
- name: Filter name.
- """
-
- def __init__(self, expressions: List[str], silent: bool, name: str = "") -> None:
- super().__init__(name)
-
- self._expressions = expressions
- self._silent = silent
-
- def filter(self, record: logging.LogRecord) -> bool:
- if record.levelno != logging.WARNING:
- return True
-
- for expression in self._expressions:
- # The message isn't always a string so we convert it before regexing as we can only regex strings
- if expression.match(str(record.msg)):
- if self._silent:
- return False
- else:
- record.levelno = logging.INFO
- record.msg = f"Filtered warning: {record.msg}"
- return True
-
- return True
-
-
-class Expression:
- """
- Encapsulate a log filter pattern and track if it ever matches a log line.
- """
-
- def __init__(self, pattern):
- self.pattern = pattern
- self.matched = False
-
- def match(self, str):
- matches = bool(re.match(self.pattern, str))
- self.matched = matches or self.matched
- return matches
-
-
-def configure(app: Sphinx) -> None:
- """Entry point.
-
- Args:
- app: Sphinx application instance.
- """
-
- # load expressions from configuration file
- with open(app.config.warnings_filter_config) as f:
- expressions = list()
- for line in f.readlines():
- if line.strip() and not line.startswith("#"):
- expressions.append(Expression(line.rstrip()))
-
- app.env.warnings_filter_expressions = expressions
-
- # install warnings filter to all the Sphinx logger handlers
- filter = WarningsFilter(expressions, app.config.warnings_filter_silent)
- logger = logging.getLogger(NAMESPACE)
- for handler in logger.handlers:
- handler.filters.insert(0, filter)
-
-
-def finished(app: Sphinx, exception: Optional[Exception]):
- """
- Prints out any patterns that have not matched a log line to allow us to clean up any that are not used.
- """
- if exception:
- # Early exit if there has been an exception as matching data is only
- # valid for complete builds
- return
-
- expressions = app.env.warnings_filter_expressions
-
- for expression in expressions:
- if not expression.matched:
- logging.warning(f"Unused expression: {expression.pattern}")
-
-
-def setup(app: Sphinx) -> Dict[str, Any]:
- app.add_config_value("warnings_filter_config", "", "")
- app.add_config_value("warnings_filter_silent", True, "")
-
- app.connect("builder-inited", configure)
- app.connect("build-finished", finished)
-
- return {
- "version": __version__,
- "parallel_read_safe": True,
- "parallel_write_safe": True,
- }
diff --git a/doc/conf.py b/doc/conf.py
index d0280fb..fdfdc2c 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -86,7 +86,6 @@
"zephyr.link-roles",
"sphinx_tabs.tabs",
"sphinx_sitemap",
- "zephyr.warnings_filter",
"zephyr.doxyrunner",
"zephyr.doxybridge",
"zephyr.gh_utils",
@@ -257,10 +256,6 @@
html_redirect_pages = redirects.REDIRECTS
-# -- Options for zephyr.warnings_filter -----------------------------------
-
-warnings_filter_config = str(ZEPHYR_BASE / "doc" / "known-warnings.txt")
-
# -- Options for zephyr.link-roles ----------------------------------------
link_roles_manifest_project = "zephyr"
diff --git a/doc/connectivity/bluetooth/autopts/autopts-linux.rst b/doc/connectivity/bluetooth/autopts/autopts-linux.rst
index 465d9c0..5977b20 100644
--- a/doc/connectivity/bluetooth/autopts/autopts-linux.rst
+++ b/doc/connectivity/bluetooth/autopts/autopts-linux.rst
@@ -234,7 +234,7 @@
.. code-block::
- git clone https://github.com/intel/auto-pts.git
+ git clone https://github.com/auto-pts/auto-pts.git
Install socat, that is used to transfer BTP data stream from UART's tty file:
@@ -257,7 +257,7 @@
.. code-block::
- git clone https://github.com/intel/auto-pts.git
+ git clone https://github.com/auto-pts/auto-pts.git
Install required python modules:
diff --git a/doc/connectivity/bluetooth/autopts/autopts-win10.rst b/doc/connectivity/bluetooth/autopts/autopts-win10.rst
index 0c63590..4420943 100644
--- a/doc/connectivity/bluetooth/autopts/autopts-win10.rst
+++ b/doc/connectivity/bluetooth/autopts/autopts-win10.rst
@@ -141,7 +141,7 @@
.. code-block::
- git clone https://github.com/intel/auto-pts.git
+ git clone https://github.com/auto-pts/auto-pts.git
Go into the project folder:
diff --git a/doc/connectivity/bluetooth/bluetooth-qual.rst b/doc/connectivity/bluetooth/bluetooth-qual.rst
index 867173b..23d1a0a 100644
--- a/doc/connectivity/bluetooth/bluetooth-qual.rst
+++ b/doc/connectivity/bluetooth/bluetooth-qual.rst
@@ -6,12 +6,12 @@
Qualification setup
*******************
-.. _auto_pts_repository:
+.. _AutoPTS automation software:
https://github.com/auto-pts/auto-pts
The Zephyr Bluetooth host can be qualified using Bluetooth's PTS (Profile Tuning
Suite) software. It is originally a manual process, but is automated by using
-the `AutoPTS automation software <auto_pts_repository>`_.
+the `AutoPTS automation software`_.
The setup is described in more details in the pages linked below.
@@ -24,11 +24,11 @@
ICS Features
************
-.. _bluetooth_qualification_website:
+.. _Bluetooth Qualification website:
https://qualification.bluetooth.com/
The Zephyr ICS file for the Host features can be downloaded here:
:download:`ICS_Zephyr_Bluetooth_Host.pts
</tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts>`.
-Use the `Bluetooth Qualification website <bluetooth_qualification_website>`_ to view and edit the ICS.
+Use the `Bluetooth Qualification website`_ to view and edit the ICS.
diff --git a/doc/connectivity/networking/api/net_buf.rst b/doc/connectivity/networking/api/net_buf.rst
index 1210fbc..88948ac 100644
--- a/doc/connectivity/networking/api/net_buf.rst
+++ b/doc/connectivity/networking/api/net_buf.rst
@@ -50,14 +50,11 @@
compile-time defined when declaring the buffer pool.
The buffers have native support for being passed through k_fifo kernel
-objects. This is a very practical feature when the buffers need to be
-passed from one thread to another. However, since a net_buf may have a
-fragment chain attached to it, instead of using the :c:func:`k_fifo_put`
-and :c:func:`k_fifo_get` APIs, special :c:func:`net_buf_put` and
-:c:func:`net_buf_get` APIs must be used when passing buffers through
-FIFOs. These APIs ensure that the buffer chains stay intact. The same
-applies for passing buffers through a singly linked list, in which case
-the :c:func:`net_buf_slist_put` and :c:func:`net_buf_slist_get`
+objects. Use :c:func:`k_fifo_put` and :c:func:`k_fifo_get` to pass buffer
+from one thread to another.
+
+Special functions exist for dealing with buffers in single linked lists,
+where the :c:func:`net_buf_slist_put` and :c:func:`net_buf_slist_get`
functions must be used instead of :c:func:`sys_slist_append` and
:c:func:`sys_slist_get`.
diff --git a/doc/connectivity/networking/api/wifi.rst b/doc/connectivity/networking/api/wifi.rst
index be29d9f..9ae9b8c 100644
--- a/doc/connectivity/networking/api/wifi.rst
+++ b/doc/connectivity/networking/api/wifi.rst
@@ -24,6 +24,39 @@
* Networking or socket offloaded drivers
* Native L2 Ethernet drivers
+Wi-Fi Enterprise test: X.509 Certificate header generation
+**********************************************************
+
+Wi-Fi enterprise security requires use of X.509 certificates, test certificates
+in PEM format are committed to the repo at :zephyr_file:`samples/net/wifi/test_certs` and the during the
+build process the certificates are converted to a `C` header file that is included by the Wi-Fi shell
+module.
+
+.. code-block:: bash
+
+ $ cp client.pem samples/net/wifi/test_certs/
+ $ cp client-key.pem samples/net/wifi/test_certs/
+ $ cp ca.pem samples/net/wifi/test_certs/
+ $ west build -p -b <board> samples/net/wifi
+
+To initiate Wi-Fi connection, the following command can be used:
+
+.. code-block:: console
+
+ uart:~$ wifi connect -s <SSID> -k 5 -a anon -K whatever
+
+Server certificate is also provided in the same directory for testing purposes.
+Any `AAA` server can be used for testing purposes, for example, `FreeRADIUS` or `hostapd`.
+
+.. important::
+
+ The passphrase for the client-key.pem and the server-key.pem is `whatever`.
+
+.. note::
+
+ The certificates are for testing purposes only and should not be used in production.
+ The certificates are generated using `FreeRADIUS raddb <https://github.com/FreeRADIUS/freeradius-server/tree/master/raddb/certs> _` scripts.
+
API Reference
*************
diff --git a/doc/connectivity/networking/index.rst b/doc/connectivity/networking/index.rst
index 26dfbb1..2a34c13 100644
--- a/doc/connectivity/networking/index.rst
+++ b/doc/connectivity/networking/index.rst
@@ -15,5 +15,6 @@
net_config_guide.rst
networking_with_host.rst
network_monitoring.rst
+ network_tracing.rst
api/index.rst
conn_mgr/index.rst
diff --git a/doc/connectivity/networking/network_tracing.rst b/doc/connectivity/networking/network_tracing.rst
new file mode 100644
index 0000000..d3655ee
--- /dev/null
+++ b/doc/connectivity/networking/network_tracing.rst
@@ -0,0 +1,26 @@
+.. _network_tracing:
+
+Network Tracing
+###############
+
+.. contents::
+ :local:
+ :depth: 2
+
+User can enable network core stack and socket API calls tracing.
+
+The :kconfig:option:`CONFIG_TRACING_NET_CORE` option contols the core network
+stack tracing. This option is enabled by default if tracing and networking
+are enabled. The system will start to collect the receiving and sending call
+verdicts i.e., whether the network packet was successfully sent or received.
+It will also collect packet sending or receiving timings i.e., how long
+it took to deliver the network packet, and the network interface, priority
+and traffic class used.
+
+The :kconfig:option:`CONFIG_TRACING_NET_SOCKETS` option can be used to track
+BSD socket call usage in the system. It is enabled if tracing and BSD socket
+API support are enabled. The system will start to collect what BSD socket
+API calls are made and what parameters the API calls are using and returning.
+
+See the :ref:`tracing documentation <tracing>` for how to use the tracing
+service.
diff --git a/doc/contribute/coding_guidelines/index.rst b/doc/contribute/coding_guidelines/index.rst
index caadffc..3c74ee2 100644
--- a/doc/contribute/coding_guidelines/index.rst
+++ b/doc/contribute/coding_guidelines/index.rst
@@ -43,7 +43,7 @@
Main rules
**********
-The coding guideline rules are based on MISRA-C 2012 and are a subset of MISRA-C.
+The coding guideline rules are based on MISRA-C 2012 and are a **subset** of MISRA-C.
The subset is listed in the table below with a summary of the rules, its
severity and the equivalent rules from other standards for reference.
@@ -59,1053 +59,1052 @@
.. list-table:: Main rules
:header-rows: 1
- :widths: 17 14 43 12 14
+ :widths: 12 45 15 14 12
- * - MISRA C 2012
- - Severity
+ * - Zephyr rule
- Description
- - CERT C
- - Example
+ - MISRA-C 2012 rule
+ - MISRA-C severity
+ - CERT C reference
.. _MisraC_Dir_1_1:
- * - Dir 1.1
- - Required
+ * - 1
- Any implementation-defined behaviour on which the output of the program depends shall be documented and understood
- - `MSC09-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC09-C.+Character+encoding%3A+Use+subset+of+ASCII+for+safety>`_
- `Dir 1.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_01_01.c>`_
+ - Required
+ - `MSC09-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC09-C.+Character+encoding%3A+Use+subset+of+ASCII+for+safety>`_
.. _MisraC_Dir_2_1:
- * - Dir 2.1
- - Required
+ * - 2
- All source files shall compile without any compilation errors
- - N/A
- `Dir 2.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_02_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Dir_3_1:
- * - Dir 3.1
- - Required
+ * - 3
- All code shall be traceable to documented requirements
- - N/A
- `Dir 3.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_03_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Dir_4_1:
- * - Dir 4.1
- - Required
+ * - 4
- Run-time failures shall be minimized
- - N/A
- `Dir 4.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Dir_4_2:
- * - Dir 4.2
- - Advisory
+ * - 5
- All usage of assembly language should be documented
- - N/A
- `Dir 4.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_02.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Dir_4_4:
- * - Dir 4.4
- - Advisory
+ * - 6
- Sections of code should not be “commented out”
- - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
- `Dir 4.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_04.c>`_
+ - Advisory
+ - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
.. _MisraC_Dir_4_5:
- * - Dir 4.5
- - Advisory
+ * - 7
- Identifiers in the same name space with overlapping visibility should be typographically unambiguous
- - `DCL02-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL02-C.+Use+visually+distinct+identifiers>`_
- `Dir 4.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_05.c>`_
+ - Advisory
+ - `DCL02-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL02-C.+Use+visually+distinct+identifiers>`_
.. _MisraC_Dir_4_6:
- * - Dir 4.6
- - Advisory
+ * - 8
- typedefs that indicate size and signedness should be used in place of the basic numerical types
- - N/A
- `Dir 4.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_06.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Dir_4_7:
- * - Dir 4.7
- - Required
+ * - 9
- If a function returns error information, then that error information shall be tested
- - N/A
- `Dir 4.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Dir_4_8:
- * - Dir 4.8
- - Advisory
+ * - 10
- If a pointer to a structure or union is never dereferenced within a translation unit, then the implementation of the object should be hidden
- - `DCL12-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL12-C.+Implement+abstract+data+types+using+opaque+types>`_
- | `Dir 4.8 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_08_1.c>`_
| `Dir 4.8 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_08_2.c>`_
+ - Advisory
+ - `DCL12-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL12-C.+Implement+abstract+data+types+using+opaque+types>`_
.. _MisraC_Dir_4_9:
- * - Dir 4.9
- - Advisory
+ * - 11
- A function should be used in preference to a function-like macro where they are interchangeable
- - `PRE00-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE00-C.+Prefer+inline+or+static+functions+to+function-like+macros>`_
- `Dir 4.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_09.c>`_
+ - Advisory
+ - `PRE00-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE00-C.+Prefer+inline+or+static+functions+to+function-like+macros>`_
.. _MisraC_Dir_4_10:
- * - Dir 4.10
- - Required
+ * - 12
- Precautions shall be taken in order to prevent the contents of a header file being included more than once
- - `PRE06-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE06-C.+Enclose+header+files+in+an+include+guard>`_
- `Dir 4.10 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_10.c>`_
+ - Required
+ - `PRE06-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE06-C.+Enclose+header+files+in+an+include+guard>`_
.. _MisraC_Dir_4_11:
- * - Dir 4.11
- - Required
+ * - 13
- The validity of values passed to library functions shall be checked
- - N/A
- `Dir 4.11 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_11.c>`_
+ - Required
+ - N/A
.. _MisraC_Dir_4_12:
- * - Dir 4.12
- - Required
+ * - 14
- Dynamic memory allocation shall not be used
- - `STR01-C <https://wiki.sei.cmu.edu/confluence/display/c/STR01-C.+Adopt+and+implement+a+consistent+plan+for+managing+strings>`_
- `Dir 4.12 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_12.c>`_
+ - Required
+ - `STR01-C <https://wiki.sei.cmu.edu/confluence/display/c/STR01-C.+Adopt+and+implement+a+consistent+plan+for+managing+strings>`_
.. _MisraC_Dir_4_13:
- * - Dir 4.13
- - Advisory
+ * - 15
- Functions which are designed to provide operations on a resource should be called in an appropriate sequence
- - N/A
- `Dir 4.13 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_13.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Dir_4_14:
- * - Dir 4.14
- - Required
+ * - 16
- The validity of values received from external sources shall be checked
-
- - N/A
- `Dir 4.14 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_14.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_1_2:
- * - Rule 1.2
- - Advisory
+ * - 17
- Language extensions should not be used
- - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
- `Rule 1.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_01_02.c>`_
+ - Advisory
+ - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
.. _MisraC_Rule_1_3:
- * - Rule 1.3
- - Required
+ * - 18
- There shall be no occurrence of undefined or critical unspecified behaviour
- - N/A
- `Rule 1.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_01_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_2_1:
- * - Rule 2.1
- - Required
+ * - 19
- A project shall not contain unreachable code
- - `MSC07-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC07-C.+Detect+and+remove+dead+code>`_
- | `Rule 2.1 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_01_1.c>`_
| `Rule 2.1 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_01_2.c>`_
+ - Required
+ - `MSC07-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC07-C.+Detect+and+remove+dead+code>`_
.. _MisraC_Rule_2_2:
- * - Rule 2.2
- - Required
+ * - 20
- There shall be no dead code
- - `MSC12-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC12-C.+Detect+and+remove+code+that+has+no+effect+or+is+never+executed>`_
- `Rule 2.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_02.c>`_
+ - Required
+ - `MSC12-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC12-C.+Detect+and+remove+code+that+has+no+effect+or+is+never+executed>`_
.. _MisraC_Rule_2_3:
- * - Rule 2.3
- - Advisory
+ * - 21
- A project should not contain unused type declarations
- - N/A
- `Rule 2.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_03.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_2_6:
- * - Rule 2.6
- - Advisory
+ * - 22
- A function should not contain unused label declarations
- - N/A
- `Rule 2.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_06.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_2_7:
- * - Rule 2.7
- - Advisory
+ * - 23
- There should be no unused parameters in functions
- - N/A
- `Rule 2.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_02_07.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_3_1:
- * - Rule 3.1
- - Required
+ * - 24
- The character sequences /* and // shall not be used within a comment
- - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
- `Rule 3.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_03_01.c>`_
+ - Required
+ - `MSC04-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC04-C.+Use+comments+consistently+and+in+a+readable+fashion>`_
.. _MisraC_Rule_3_2:
- * - Rule 3.2
- - Required
+ * - 25
- Line-splicing shall not be used in // comments
- - N/A
- `Rule 3.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_03_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_4_1:
- * - Rule 4.1
- - Required
+ * - 26
- Octal and hexadecimal escape sequences shall be terminated
- - `MSC09-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC09-C.+Character+encoding%3A+Use+subset+of+ASCII+for+safety>`_
- `Rule 4.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_04_01.c>`_
+ - Required
+ - `MSC09-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC09-C.+Character+encoding%3A+Use+subset+of+ASCII+for+safety>`_
.. _MisraC_Rule_4_2:
- * - Rule 4.2
- - Advisory
+ * - 27
- Trigraphs should not be used
- - `PRE07-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE07-C.+Avoid+using+repeated+question+marks>`_
- `Rule 4.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_04_02.c>`_
+ - Advisory
+ - `PRE07-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE07-C.+Avoid+using+repeated+question+marks>`_
.. _MisraC_Rule_5_1:
- * - Rule 5.1
- - Required
+ * - 28
- External identifiers shall be distinct
- - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
- | `Rule 5.1 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_01_1.c>`_
| `Rule 5.1 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_01_2.c>`_
+ - Required
+ - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
.. _MisraC_Rule_5_2:
- * - Rule 5.2
- - Required
+ * - 29
- Identifiers declared in the same scope and name space shall be distinct
- - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
- `Rule 5.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_02.c>`_
+ - Required
+ - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
.. _MisraC_Rule_5_3:
- * - Rule 5.3
- - Required
+ * - 30
- An identifier declared in an inner scope shall not hide an identifier declared in an outer scope
- - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
- `Rule 5.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_03.c>`_
+ - Required
+ - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
.. _MisraC_Rule_5_4:
- * - Rule 5.4
- - Required
+ * - 31
- Macro identifiers shall be distinct
- - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
- `Rule 5.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_04.c>`_
+ - Required
+ - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
.. _MisraC_Rule_5_5:
- * - Rule 5.5
- - Required
+ * - 32
- Identifiers shall be distinct from macro names
- - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
- `Rule 5.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_05.c>`_
+ - Required
+ - `DCL23-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL23-C.+Guarantee+that+mutually+visible+identifiers+are+unique>`_
.. _MisraC_Rule_5_6:
- * - Rule 5.6
- - Required
+ * - 33
- A typedef name shall be a unique identifier
- - N/A
- `Rule 5.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_06.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_5_7:
- * - Rule 5.7
- - Required
+ * - 34
- A tag name shall be a unique identifier
- - N/A
- `Rule 5.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_5_8:
- * - Rule 5.8
- - Required
+ * - 35
- Identifiers that define objects or functions with external linkage shall be unique
- - N/A
- | `Rule 5.8 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_08_1.c>`_
| `Rule 5.8 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_08_2.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_5_9:
- * - Rule 5.9
- - Advisory
+ * - 36
- Identifiers that define objects or functions with internal linkage should be unique
- - N/A
- | `Rule 5.9 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_09_1.c>`_
| `Rule 5.9 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_09_2.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_6_1:
- * - Rule 6.1
- - Required
+ * - 37
- Bit-fields shall only be declared with an appropriate type
- - `INT14-C <https://wiki.sei.cmu.edu/confluence/display/c/INT14-C.+Avoid+performing+bitwise+and+arithmetic+operations+on+the+same+data>`_
- `Rule 6.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_06_01.c>`_
+ - Required
+ - `INT14-C <https://wiki.sei.cmu.edu/confluence/display/c/INT14-C.+Avoid+performing+bitwise+and+arithmetic+operations+on+the+same+data>`_
.. _MisraC_Rule_6_2:
- * - Rule 6.2
- - Required
+ * - 38
- Single-bit named bit fields shall not be of a signed type
- - `INT14-C <https://wiki.sei.cmu.edu/confluence/display/c/INT14-C.+Avoid+performing+bitwise+and+arithmetic+operations+on+the+same+data>`_
- `Rule 6.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_06_02.c>`_
+ - Required
+ - `INT14-C <https://wiki.sei.cmu.edu/confluence/display/c/INT14-C.+Avoid+performing+bitwise+and+arithmetic+operations+on+the+same+data>`_
.. _MisraC_Rule_7_1:
- * - Rule 7.1
- - Required
+ * - 39
- Octal constants shall not be used
- - `DCL18-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL18-C.+Do+not+begin+integer+constants+with+0+when+specifying+a+decimal+value>`_
- `Rule 7.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_07_01.c>`_
+ - Required
+ - `DCL18-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL18-C.+Do+not+begin+integer+constants+with+0+when+specifying+a+decimal+value>`_
.. _MisraC_Rule_7_2:
- * - Rule 7.2
- - Required
+ * - 40
- A u or U suffix shall be applied to all integer constants that are represented in an unsigned type
- - N/A
- `Rule 7.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_07_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_7_3:
- * - Rule 7.3
- - Required
+ * - 41
- The lowercase character l shall not be used in a literal suffix
- - `DCL16-C <https://wiki.sei.cmu.edu/confluence/pages/viewpage.action?pageId=87152241>`_
- `Rule 7.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_07_03.c>`_
+ - Required
+ - `DCL16-C <https://wiki.sei.cmu.edu/confluence/pages/viewpage.action?pageId=87152241>`_
.. _MisraC_Rule_7_4:
- * - Rule 7.4
- - Required
+ * - 42
- A string literal shall not be assigned to an object unless the objects type is pointer to const-qualified char
- - N/A
- `Rule 7.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_07_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_1:
- * - Rule 8.1
- - Required
+ * - 43
- Types shall be explicitly specified
- - N/A
- `Rule 8.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_2:
- * - Rule 8.2
- - Required
+ * - 44
- Function types shall be in prototype form with named parameters
- - `DCL20-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL20-C.+Explicitly+specify+void+when+a+function+accepts+no+arguments>`_
- `Rule 8.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_02.c>`_
+ - Required
+ - `DCL20-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL20-C.+Explicitly+specify+void+when+a+function+accepts+no+arguments>`_
.. _MisraC_Rule_8_3:
- * - Rule 8.3
- - Required
+ * - 45
- All declarations of an object or function shall use the same names and type qualifiers
- - N/A
- `Rule 8.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_4:
- * - Rule 8.4
- - Required
+ * - 46
- A compatible declaration shall be visible when an object or function with external linkage is defined
- - N/A
- `Rule 8.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_5:
- * - Rule 8.5
- - Required
+ * - 47
- An external object or function shall be declared once in one and only one file
- - N/A
- | `Rule 8.5 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_05_1.c>`_
| `Rule 8.5 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_05_2.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_6:
- * - Rule 8.6
- - Required
+ * - 48
- An identifier with external linkage shall have exactly one external definition
- - N/A
- | `Rule 8.6 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_06_1.c>`_
| `Rule 8.6 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_06_2.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_8:
- * - Rule 8.8
- - Required
+ * - 49
- The static storage class specifier shall be used in all declarations of objects and functions that have internal linkage
- - `DCL15-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL15-C.+Declare+file-scope+objects+or+functions+that+do+not+need+external+linkage+as+static>`_
- `Rule 8.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_08.c>`_
+ - Required
+ - `DCL15-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL15-C.+Declare+file-scope+objects+or+functions+that+do+not+need+external+linkage+as+static>`_
.. _MisraC_Rule_8_9:
- * - Rule 8.9
- - Advisory
+ * - 50
- An object should be defined at block scope if its identifier only appears in a single function
- - `DCL19-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL19-C.+Minimize+the+scope+of+variables+and+functions>`_
- `Rule 8.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_09.c>`_
+ - Advisory
+ - `DCL19-C <https://wiki.sei.cmu.edu/confluence/display/c/DCL19-C.+Minimize+the+scope+of+variables+and+functions>`_
.. _MisraC_Rule_8_10:
- * - Rule 8.10
- - Required
+ * - 51
- An inline function shall be declared with the static storage class
- - N/A
- `Rule 8.10 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_10.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_8_12:
- * - Rule 8.12
- - Required
+ * - 52
- Within an enumerator list, the value of an implicitly-specified enumeration constant shall be unique
- - `INT09-C <https://wiki.sei.cmu.edu/confluence/display/c/INT09-C.+Ensure+enumeration+constants+map+to+unique+values>`_
- `Rule 8.12 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_12.c>`_
+ - Required
+ - `INT09-C <https://wiki.sei.cmu.edu/confluence/display/c/INT09-C.+Ensure+enumeration+constants+map+to+unique+values>`_
.. _MisraC_Rule_8_14:
- * - Rule 8.14
- - Required
+ * - 53
- The restrict type qualifier shall not be used
- - N/A
- `Rule 8.14 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_08_14.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_9_1:
- * - Rule 9.1
- - Mandatory
+ * - 54
- The value of an object with automatic storage duration shall not be read before it has been set
- - N/A
- `Rule 9.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_09_01.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_9_2:
- * - Rule 9.2
- - Required
+ * - 55
- The initializer for an aggregate or union shall be enclosed in braces
- - N/A
- `Rule 9.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_09_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_9_3:
- * - Rule 9.3
- - Required
+ * - 56
- Arrays shall not be partially initialized
- - N/A
- `Rule 9.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_09_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_9_4:
- * - Rule 9.4
- - Required
+ * - 57
- An element of an object shall not be initialized more than once
- - N/A
- `Rule 9.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_09_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_9_5:
- * - Rule 9.5
- - Required
+ * - 58
- Where designated initializers are used to initialize an array object the size of the array shall be specified explicitly
- - N/A
- `Rule 9.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_09_05.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_10_1:
- * - Rule 10.1
- - Required
+ * - 59
- Operands shall not be of an inappropriate essential type
- - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
- `Rule 10.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_01.c>`_
+ - Required
+ - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
.. _MisraC_Rule_10_2:
- * - Rule 10.2
- - Required
+ * - 60
- Expressions of essentially character type shall not be used inappropriately in addition and subtraction operations
- - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
- `Rule 10.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_02.c>`_
+ - Required
+ - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
.. _MisraC_Rule_10_3:
- * - Rule 10.3
- - Required
+ * - 61
- The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category
- - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
- `Rule 10.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_03.c>`_
+ - Required
+ - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
.. _MisraC_Rule_10_4:
- * - Rule 10.4
- - Required
+ * - 62
- Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category
- - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
- `Rule 10.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_04.c>`_
+ - Required
+ - `STR04-C <https://wiki.sei.cmu.edu/confluence/display/c/STR04-C.+Use+plain+char+for+characters+in+the+basic+character+set>`_
.. _MisraC_Rule_10_5:
- * - Rule 10.5
- - Advisory
+ * - 63
- The value of an expression should not be cast to an inappropriate essential type
- - N/A
- `Rule 10.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_05.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_10_6:
- * - Rule 10.6
- - Required
+ * - 64
- The value of a composite expression shall not be assigned to an object with wider essential type
- - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
- `Rule 10.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_06.c>`_
+ - Required
+ - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
.. _MisraC_Rule_10_7:
- * - Rule 10.7
- - Required
+ * - 65
- If a composite expression is used as one operand of an operator in which the usual arithmetic conversions are performed then the other operand shall not have wider essential type
- - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
- `Rule 10.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_07.c>`_
+ - Required
+ - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
.. _MisraC_Rule_10_8:
- * - Rule 10.8
- - Required
+ * - 66
- The value of a composite expression shall not be cast to a different essential type category or a wider essential type
- - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
- `Rule 10.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_10_08.c>`_
+ - Required
+ - `INT02-C <https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules>`_
.. _MisraC_Rule_11_2:
- * - Rule 11.2
- - Required
+ * - 67
- Conversions shall not be performed between a pointer to an incomplete type and any other type
- - N/A
- `Rule 11.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_11_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_11_6:
- * - Rule 11.6
- - Required
+ * - 68
- A cast shall not be performed between pointer to void and an arithmetic type
- - N/A
- `Rule 11.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_11_06.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_11_7:
- * - Rule 11.7
- - Required
+ * - 69
- A cast shall not be performed between pointer to object and a noninteger arithmetic type
- - N/A
- `Rule 11.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_11_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_11_8:
- * - Rule 11.8
- - Required
+ * - 70
- A cast shall not remove any const or volatile qualification from the type pointed to by a pointer
- - `EXP05-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP05-C.+Do+not+cast+away+a+const+qualification>`_
- `Rule 11.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_11_08.c>`_
+ - Required
+ - `EXP05-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP05-C.+Do+not+cast+away+a+const+qualification>`_
.. _MisraC_Rule_11_9:
- * - Rule 11.9
- - Required
+ * - 71
- The macro NULL shall be the only permitted form of integer null pointer constant
- - N/A
- `Rule 11.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_11_09.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_12_1:
- * - Rule 12.1
- - Advisory
+ * - 72
- The precedence of operators within expressions should be made explicit
- - `EXP00-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP00-C.+Use+parentheses+for+precedence+of+operation>`_
- `Rule 12.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_12_01.c>`_
+ - Advisory
+ - `EXP00-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP00-C.+Use+parentheses+for+precedence+of+operation>`_
.. _MisraC_Rule_12_2:
- * - Rule 12.2
- - Required
+ * - 73
- The right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand
- - N/A
- `Rule 12.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_12_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_12_4:
- * - Rule 12.4
- - Advisory
+ * - 74
- Evaluation of constant expressions should not lead to unsigned integer wrap-around
- - N/A
- `Rule 12.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_12_04.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_12_5:
- * - Rule 12.5
- - Mandatory
+ * - 75
- The sizeof operator shall not have an operand which is a function parameter declared as “array of type”
- - N/A
- `Rule 12.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_12_05.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_13_1:
- * - Rule 13.1
- - Required
+ * - 76
- Initializer lists shall not contain persistent side effects
- - N/A
- | `Rule 13.1 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_01_1.c>`_
| `Rule 13.1 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_01_2.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_13_2:
- * - Rule 13.2
- - Required
+ * - 77
- The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders
- - N/A
- `Rule 13.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_13_3:
- * - Rule 13.3
- - Advisory
+ * - 78
- A full expression containing an increment (++) or decrement (--) operator should have no other potential side effects other than that caused by the increment or decrement operator
- - N/A
- `Rule 13.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_03.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_13_4:
- * - Rule 13.4
- - Advisory
+ * - 79
- The result of an assignment operator should not be used
- - N/A
- `Rule 13.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_04.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_13_5:
- * - Rule 13.5
- - Required
+ * - 80
- The right hand operand of a logical && or || operator shall not contain persistent side effects
- - `EXP10-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP10-C.+Do+not+depend+on+the+order+of+evaluation+of+subexpressions+or+the+order+in+which+side+effects+take+place>`_
- | `Rule 13.5 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_05_1.c>`_
| `Rule 13.5 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_05_2.c>`_
+ - Required
+ - `EXP10-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP10-C.+Do+not+depend+on+the+order+of+evaluation+of+subexpressions+or+the+order+in+which+side+effects+take+place>`_
.. _MisraC_Rule_13_6:
- * - Rule 13.6
- - Mandatory
+ * - 81
- The operand of the sizeof operator shall not contain any expression which has potential side effects
- - N/A
- `Rule 13.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_13_06.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_14_1:
- * - Rule 14.1
- - Required
+ * - 82
- A loop counter shall not have essentially floating type
- - N/A
- `Rule 14.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_14_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_14_2:
- * - Rule 14.2
- - Required
+ * - 83
- A for loop shall be well-formed
- - N/A
- `Rule 14.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_14_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_14_3:
- * - Rule 14.3
- - Required
+ * - 84
- Controlling expressions shall not be invariant
- - N/A
- `Rule 14.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_14_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_14_4:
- * - Rule 14.4
- - Required
+ * - 85
- The controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type
- - N/A
- `Rule 14.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_14_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_15_2:
- * - Rule 15.2
- - Required
+ * - 86
- The goto statement shall jump to a label declared later in the same function
- - N/A
- `Rule 15.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_15_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_15_3:
- * - Rule 15.3
- - Required
+ * - 87
- Any label referenced by a goto statement shall be declared in the same block, or in any block enclosing the goto statement
- - N/A
- `Rule 15.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_15_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_15_6:
- * - Rule 15.6
- - Required
+ * - 88
- The body of an iteration-statement or a selection-statement shall be a compound-statement
- - `EXP19-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP19-C.+Use+braces+for+the+body+of+an+if%2C+for%2C+or+while+statement>`_
- `Rule 15.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_15_06.c>`_
+ - Required
+ - `EXP19-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP19-C.+Use+braces+for+the+body+of+an+if%2C+for%2C+or+while+statement>`_
.. _MisraC_Rule_15_7:
- * - Rule 15.7
- - Required
+ * - 89
- All if else if constructs shall be terminated with an else statement
- - N/A
- `Rule 15.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_15_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_1:
- * - Rule 16.1
- - Required
+ * - 90
- All switch statements shall be well-formed
- - N/A
- `Rule 16.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_2:
- * - Rule 16.2
- - Required
+ * - 91
- A switch label shall only be used when the most closely-enclosing compound statement is the body of a switch statement
- - `MSC20-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC20-C.+Do+not+use+a+switch+statement+to+transfer+control+into+a+complex+block>`_
- `Rule 16.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_02.c>`_
+ - Required
+ - `MSC20-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC20-C.+Do+not+use+a+switch+statement+to+transfer+control+into+a+complex+block>`_
.. _MisraC_Rule_16_3:
- * - Rule 16.3
- - Required
+ * - 92
- An unconditional break statement shall terminate every switch-clause
- - N/A
- `Rule 16.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_4:
- * - Rule 16.4
- - Required
+ * - 93
- Every switch statement shall have a default label
- - N/A
- `Rule 16.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_5:
- * - Rule 16.5
- - Required
+ * - 94
- A default label shall appear as either the first or the last switch label of a switch statement
- - N/A
- `Rule 16.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_05.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_6:
- * - Rule 16.6
- - Required
+ * - 95
- Every switch statement shall have at least two switch-clauses
- - N/A
- `Rule 16.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_06.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_16_7:
- * - Rule 16.7
- - Required
+ * - 96
- A switch-expression shall not have essentially Boolean type
- - N/A
- `Rule 16.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_16_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_17_1:
- * - Rule 17.1
- - Required
+ * - 97
- The features of <stdarg.h> shall not be used
- - `ERR00-C <https://wiki.sei.cmu.edu/confluence/display/c/ERR00-C.+Adopt+and+implement+a+consistent+and+comprehensive+error-handling+policy>`_
- `Rule 17.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_01.c>`_
+ - Required
+ - `ERR00-C <https://wiki.sei.cmu.edu/confluence/display/c/ERR00-C.+Adopt+and+implement+a+consistent+and+comprehensive+error-handling+policy>`_
.. _MisraC_Rule_17_2:
- * - Rule 17.2
- - Required
+ * - 98
- Functions shall not call themselves, either directly or indirectly
- - `MEM05-C <https://wiki.sei.cmu.edu/confluence/display/c/MEM05-C.+Avoid+large+stack+allocations>`_
- `Rule 17.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_02.c>`_
+ - Required
+ - `MEM05-C <https://wiki.sei.cmu.edu/confluence/display/c/MEM05-C.+Avoid+large+stack+allocations>`_
.. _MisraC_Rule_17_3:
- * - Rule 17.3
- - Mandatory
+ * - 99
- A function shall not be declared implicitly
- - N/A
- `Rule 17.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_03.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_17_4:
- * - Rule 17.4
- - Mandatory
+ * - 100
- All exit paths from a function with non-void return type shall have an explicit return statement with an expression
- - N/A
- `Rule 17.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_04.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_17_5:
- * - Rule 17.5
- - Advisory
+ * - 101
- The function argument corresponding to a parameter declared to have an array type shall have an appropriate number of elements
- - N/A
- `Rule 17.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_05.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_17_6:
- * - Rule 17.6
- - Mandatory
+ * - 102
- The declaration of an array parameter shall not contain the static keyword between the [ ]
- - N/A
- `Rule 17.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_06.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_17_7:
- * - Rule 17.7
- - Required
+ * - 103
- The value returned by a function having non-void return type shall be used
- - N/A
- `Rule 17.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_17_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_18_1:
- * - Rule 18.1
- - Required
+ * - 104
- A pointer resulting from arithmetic on a pointer operand shall address an element of the same array as that pointer operand
- - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
- `Rule 18.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_01.c>`_
+ - Required
+ - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
.. _MisraC_Rule_18_2:
- * - Rule 18.2
- - Required
+ * - 105
- Subtraction between pointers shall only be applied to pointers that address elements of the same array
- - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
- `Rule 18.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_02.c>`_
+ - Required
+ - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
.. _MisraC_Rule_18_3:
- * - Rule 18.3
- - Required
+ * - 106
- The relational operators >, >=, < and <= shall not be applied to objects of pointer type except where they point into the same object
- - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
- `Rule 18.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_03.c>`_
+ - Required
+ - `EXP08-C <https://wiki.sei.cmu.edu/confluence/display/c/EXP08-C.+Ensure+pointer+arithmetic+is+used+correctly>`_
.. _MisraC_Rule_18_5:
- * - Rule 18.5
- - Advisory
+ * - 107
- Declarations should contain no more than two levels of pointer nesting
- - N/A
- `Rule 18.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_05.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_18_6:
- * - Rule 18.6
- - Required
+ * - 108
- The address of an object with automatic storage shall not be copied to another object that persists after the first object has ceased to exist
- - N/A
- | `Rule 18.6 example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_06_1.c>`_
| `Rule 18.6 example 2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_06_2.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_18_8:
- * - Rule 18.8
- - Required
+ * - 109
- Variable-length array types shall not be used
- - N/A
- `Rule 18.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_18_08.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_19_1:
- * - Rule 19.1
- - Mandatory
+ * - 110
- An object shall not be assigned or copied to an overlapping object
- - N/A
- `Rule 19.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_19_01.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_20_2:
- * - Rule 20.2
- - Required
+ * - 111
- The ', or \ characters and the /* or // character sequences shall not occur in a header file name"
- - N/A
- `Rule 20.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_3:
- * - Rule 20.3
- - Required
+ * - 112
- The #include directive shall be followed by either a <filename> or "filename" sequence
- - N/A
- `Rule 20.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_4:
- * - Rule 20.4
- - Required
+ * - 113
- A macro shall not be defined with the same name as a keyword
- - N/A
- `Rule 20.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_7:
- * - Rule 20.7
- - Required
+ * - 114
- Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses
- - `PRE01-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE01-C.+Use+parentheses+within+macros+around+parameter+names>`_
- `Rule 20.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_07.c>`_
+ - Required
+ - `PRE01-C <https://wiki.sei.cmu.edu/confluence/display/c/PRE01-C.+Use+parentheses+within+macros+around+parameter+names>`_
.. _MisraC_Rule_20_8:
- * - Rule 20.8
- - Required
+ * - 115
- The controlling expression of a #if or #elif preprocessing directive shall evaluate to 0 or 1
- - N/A
- `Rule 20.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_08.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_9:
- * - Rule 20.9
- - Required
+ * - 116
- All identifiers used in the controlling expression of #if or #elif preprocessing directives shall be #defined before evaluation
- - N/A
- `Rule 20.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_09.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_11:
- * - Rule 20.11
- - Required
+ * - 117
- A macro parameter immediately following a # operator shall not immediately be followed by a ## operator
- - N/A
- `Rule 20.11 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_11.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_12:
- * - Rule 20.12
- - Required
+ * - 118
- A macro parameter used as an operand to the # or ## operators, which is itself subject to further macro replacement, shall only be used as an operand to these operators
- - N/A
- `Rule 20.12 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_12.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_13:
- * - Rule 20.13
- - Required
+ * - 119
- A line whose first token is # shall be a valid preprocessing directive
- - N/A
- `Rule 20.13 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_13.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_20_14:
- * - Rule 20.14
- - Required
+ * - 120
- All #else, #elif and #endif preprocessor directives shall reside in the same file as the #if, #ifdef or #ifndef directive to which they are related
- - N/A
- `Rule 20.14 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_14.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_1:
- * - Rule 21.1
- - Required
+ * - 121
- #define and #undef shall not be used on a reserved identifier or reserved macro name
- - N/A
- `Rule 21.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_2:
- * - Rule 21.2
- - Required
+ * - 122
- A reserved identifier or macro name shall not be declared
- - N/A
- `Rule 21.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_02.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_3:
- * - Rule 21.3
- - Required
+ * - 123
- The memory allocation and deallocation functions of <stdlib.h> shall not be used
- - `MSC24-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC24-C.+Do+not+use+deprecated+or+obsolescent+functions>`_
- `Rule 21.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_03.c>`_
+ - Required
+ - `MSC24-C <https://wiki.sei.cmu.edu/confluence/display/c/MSC24-C.+Do+not+use+deprecated+or+obsolescent+functions>`_
.. _MisraC_Rule_21_4:
- * - Rule 21.4
- - Required
+ * - 124
- The standard header file <setjmp.h> shall not be used
- - N/A
- `Rule 21.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_04.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_6:
- * - Rule 21.6
- - Required
+ * - 125
- The Standard Library input/output functions shall not be used
- - N/A
- `Rule 21.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_06.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_7:
- * - Rule 21.7
- - Required
+ * - 126
- The atof, atoi, atol and atoll functions of <stdlib.h> shall not be used
- - N/A
- `Rule 21.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_9:
- * - Rule 21.9
- - Required
+ * - 127
- The library functions bsearch and qsort of <stdlib.h> shall not be used
- - N/A
- `Rule 21.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_09.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_11:
- * - Rule 21.11
- - Required
+ * - 128
- The standard header file <tgmath.h> shall not be used
- - N/A
- `Rule 21.11 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_11.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_12:
- * - Rule 21.12
- - Advisory
+ * - 129
- The exception handling features of <fenv.h> should not be used
- - N/A
- `Rule 21.12 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_12.c>`_
+ - Advisory
+ - N/A
.. _MisraC_Rule_21_13:
- * - Rule 21.13
- - Mandatory
+ * - 130
- Any value passed to a function in <ctype.h> shall be representable as an unsigned char or be the value EO
- - N/A
- `Rule 21.13 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_13.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_21_14:
- * - Rule 21.14
- - Required
+ * - 131
- The Standard Library function memcmp shall not be used to compare null terminated strings
- - N/A
- `Rule 21.14 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_14.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_15:
- * - Rule 21.15
- - Required
+ * - 132
- The pointer arguments to the Standard Library functions memcpy, memmove and memcmp shall be pointers to qualified or unqualified versions of compatible types
- - N/A
- `Rule 21.15 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_15.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_16:
- * - Rule 21.16
- - Required
+ * - 133
- The pointer arguments to the Standard Library function memcmp shall point to either a pointer type, an essentially signed type, an essentially unsigned type, an essentially Boolean type or an essentially enum type
- - N/A
- `Rule 21.16 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_16.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_21_17:
- * - Rule 21.17
- - Mandatory
+ * - 134
- Use of the string handling functions from <string.h> shall not result in accesses beyond the bounds of the objects referenced by their pointer parameters
- - N/A
- `Rule 21.17 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_17.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_21_18:
- * - Rule 21.18
- - Mandatory
+ * - 135
- The size_t argument passed to any function in <string.h> shall have an appropriate value
- - N/A
- `Rule 21.18 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_18.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_21_19:
- * - Rule 21.19
- - Mandatory
+ * - 136
- The pointers returned by the Standard Library functions localeconv, getenv, setlocale or, strerror shall only be used as if they have pointer to const-qualified type
- - N/A
- `Rule 21.19 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_19.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_21_20:
- * - Rule 21.20
- - Mandatory
+ * - 137
- The pointer returned by the Standard Library functions asctime, ctime, gmtime, localtime, localeconv, getenv, setlocale or strerror shall not be used following a subsequent call to the same function
- - N/A
- `Rule 21.20 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_20.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_22_1:
- * - Rule 22.1
- - Required
+ * - 138
- All resources obtained dynamically by means of Standard Library functions shall be explicitly released
- - N/A
- `Rule 22.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_01.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_22_2:
- * - Rule 22.2
- - Mandatory
+ * - 139
- A block of memory shall only be freed if it was allocated by means of a Standard Library function
- - N/A
- `Rule 22.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_02.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_22_3:
- * - Rule 22.3
- - Required
+ * - 140
- The same file shall not be open for read and write access at the same time on different streams
- - N/A
- `Rule 22.3 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_03.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_22_4:
- * - Rule 22.4
- - Mandatory
+ * - 141
- There shall be no attempt to write to a stream which has been opened as read-only
- - N/A
- `Rule 22.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_04.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_22_5:
- * - Rule 22.5
- - Mandatory
+ * - 142
- A pointer to a FILE object shall not be dereferenced
- - N/A
- `Rule 22.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_05.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_22_6:
- * - Rule 22.6
- - Mandatory
+ * - 143
- The value of a pointer to a FILE shall not be used after the associated stream has been closed
- - N/A
- `Rule 22.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_06.c>`_
+ - Mandatory
+ - N/A
.. _MisraC_Rule_22_7:
- * - Rule 22.7
- - Required
+ * - 144
- The macro EOF shall only be compared with the unmodified return value from any Standard Library function capable of returning EOF
- - N/A
- `Rule 22.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_07.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_22_8:
- * - Rule 22.8
- - Required
+ * - 145
- The value of errno shall be set to zero prior to a call to an errno-setting-function
- - N/A
- `Rule 22.8 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_08.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_22_9:
- * - Rule 22.9
- - Required
+ * - 146
- The value of errno shall be tested against zero after calling an errno-setting-function
- - N/A
- `Rule 22.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_09.c>`_
+ - Required
+ - N/A
.. _MisraC_Rule_22_10:
- * - Rule 22.10
- - Required
+ * - 147
- The value of errno shall only be tested when the last function to be called was an errno-setting-function
- - N/A
- `Rule 22.10 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_22_10.c>`_
+ - Required
+ - N/A
Additional rules
****************
@@ -1208,7 +1207,7 @@
- Selected Replacements
- Status
- * - :ref:`bluetooth_api`
+ * - :ref:`Bluetooth <bluetooth_api>`
- See `Bluetooth Appropriate Language Mapping Tables`_
-
diff --git a/doc/contribute/documentation/generation.rst b/doc/contribute/documentation/generation.rst
index f51eb59..013decd 100644
--- a/doc/contribute/documentation/generation.rst
+++ b/doc/contribute/documentation/generation.rst
@@ -52,7 +52,7 @@
header [shape="rectangle" label="c header\ncomments"]
xml [shape="rectangle" label="XML"]
html [shape="rectangle" label="HTML\nweb site"]
- sphinx[shape="ellipse" label="sphinx +\nbreathe,\ndocutils"]
+ sphinx[shape="ellipse" label="sphinx +\ndocutils"]
images -> sphinx
rst -> sphinx
conf -> sphinx
@@ -65,8 +65,8 @@
The reStructuredText files are processed by the Sphinx documentation system,
-and make use of the breathe extension for including the doxygen-generated API
-material. Additional tools are required to generate the
+and make use of the doxygen-generated API material.
+Additional tools are required to generate the
documentation locally, as described in the following sections.
.. _documentation-processors:
@@ -242,24 +242,6 @@
# To generate PDF output
make pdf
-Filtering expected warnings
-***************************
-
-There are some known issues with Sphinx/Breathe that generate Sphinx warnings
-even though the input is valid C code. While these issues are being considered
-for fixing we have created a Sphinx extension that allows to filter them out
-based on a set of regular expressions. The extension is named
-``zephyr.warnings_filter`` and it is located at
-``doc/_extensions/zephyr/warnings_filter.py``. The warnings to be filtered out
-can be added to the ``doc/known-warnings.txt`` file.
-
-The most common warning reported by Sphinx/Breathe is related to duplicate C
-declarations. This warning may be caused by different Sphinx/Breathe issues:
-
-- Multiple declarations of the same object are not supported
-- Different objects (e.g. a struct and a function) can not share the same name
-- Nested elements (e.g. in a struct or union) can not share the same name
-
Developer-mode Document Building
********************************
diff --git a/doc/develop/api/api_lifecycle.rst b/doc/develop/api/api_lifecycle.rst
index 112c9d3..be7b8b9 100644
--- a/doc/develop/api/api_lifecycle.rst
+++ b/doc/develop/api/api_lifecycle.rst
@@ -219,8 +219,8 @@
- Deprecation Time (stable APIs): 2 Releases
The API needs to be marked as deprecated in at least two full releases.
- For example, if an API was first deprecated in release 1.14,
- it will be ready to be removed in 1.16 at the earliest.
+ For example, if an API was first deprecated in release 4.0,
+ it will be ready to be removed in 4.2 at the earliest.
There may be special circumstances, determined by the Architecture working group,
where an API is deprecated sooner.
- What is required when deprecating:
@@ -236,9 +236,10 @@
- Code using the deprecated API needs to be modified to remove usage of said
API
- The change needs to be atomic and bisectable
- - Create a GitHub issue to track the removal of the deprecated API, and
- add it to the roadmap targeting the appropriate release
- (in the example above, 1.16).
+ - Add an entry in the corresponding release
+ `GitHub issue <https://github.com/zephyrproject-rtos/zephyr/labels/deprecation_tracker>`_
+ tracking removal of deprecated APIs.
+ In this example in the one corresponding to the 4.2 release.
During the deprecation waiting period, the API will be in the ``deprecated``
state. The Zephyr maintainers will track usage of deprecated APIs on
diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst
index 0eaef93..0332c98 100644
--- a/doc/develop/getting_started/index.rst
+++ b/doc/develop/getting_started/index.rst
@@ -132,7 +132,7 @@
.. code-block:: bash
- brew install cmake ninja gperf python3 ccache qemu dtc libmagic wget openocd
+ brew install cmake ninja gperf python3 python-tk ccache qemu dtc libmagic wget openocd
#. Add the Homebrew Python folder to the path, in order to be able to
execute ``python`` and ``pip`` as well ``python3`` and ``pip3``.
diff --git a/doc/develop/test/pytest.rst b/doc/develop/test/pytest.rst
index 9691343..3b8d1de 100644
--- a/doc/develop/test/pytest.rst
+++ b/doc/develop/test/pytest.rst
@@ -97,6 +97,8 @@
-s samples/subsys/testsuite/pytest/shell/sample.pytest.shell \
--pytest-args='-k test_shell_print_version'
+ The command line arguments will extend those from the .yaml file. If the same argument is
+ present in both places, the one from the command line will take precedence.
Fixtures
********
@@ -166,6 +168,22 @@
mcumgr.reset_device()
# continue test scenario, check version etc.
+
+unlauched_dut
+=============
+
+Similar to the ``dut`` fixture, but it does not initialize the device. It can be used when a finer
+control over the build process is needed. It becomes responsibility of the test to initialize the
+device.
+
+.. code-block:: python
+
+ from twister_harness import DeviceAdapter
+
+ def test_sample(unlauched_dut: DeviceAdapter):
+ unlaunched_dut.launch()
+ unlaunched_dut.readlines_until('Hello world')
+
Classes
*******
diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst
index a65c559..2b3b896 100644
--- a/doc/develop/test/twister.rst
+++ b/doc/develop/test/twister.rst
@@ -186,6 +186,8 @@
testing relating keywords to provide best coverage for the features of this
board.
+.. _twister_default_testing_board:
+
default: [True|False]:
This is a default board, it will tested with the highest priority and is
covered when invoking the simplified twister without any additional
@@ -316,6 +318,8 @@
Each test scenario entry in the test application configuration can define the
following key/value pairs:
+.. _test_config_args:
+
tags: <list of tags> (required)
A set of string tags for the test scenario. Usually pertains to
functional domains but can be anything. Command line invocations
@@ -823,6 +827,37 @@
Most everyday users will run with no arguments.
+Selecting platform scope
+************************
+
+One of the key features of Twister is its ability to decide on which platforms a given
+test scenario should run. This behavior has its roots in Twister being developed as
+a test runner for Zephyr's CI. With hundreds of available platforms and thousands of
+tests, the testing tools should be able to adapt the scope and select/filter out what
+is relevant and what is not.
+
+Twister always prepares an initial list of platforms in scope for a given test,
+based on command line arguments and the :ref:`test's configuration <test_config_args>`. Then,
+platforms that don't fulfill the conditions required in the configuration yaml
+(e.g. minimum ram) are filtered out from the scope.
+Using ``--force-platform`` allows to override filtering caused by ``platform_allow``,
+``platform_exclude``, ``arch_allow`` and ``arch_exclude`` keys in test configuration
+files.
+
+Command line arguments define the initial scope in the following way:
+
+* ``-p/--platform <platform_name>`` (can be used multiple times): only platforms
+ passed with this argument;
+* ``-l/--all``: all available platforms;
+* ``-G/--integration``: all platforms from an ``integration_platforms`` list in
+ a given test configuration file. If a test has no ``integration_platforms``
+ `"scope presumption"` will happen;
+* No scope argument: `"scope presumption"` will happen.
+
+`"Scope presumption"`: A list of Twister's :ref:`default platforms <twister_default_testing_board>`
+is used as the initial list. If nothing is left after the filtration, the ``platform_allow`` list
+is used as the initial scope.
+
Managing tests timeouts
***********************
diff --git a/doc/hardware/arch/arm-scmi.rst b/doc/hardware/arch/arm-scmi.rst
new file mode 100644
index 0000000..6d62599
--- /dev/null
+++ b/doc/hardware/arch/arm-scmi.rst
@@ -0,0 +1,234 @@
+.. _arm_scmi:
+
+ARM System Control and Management Interface
+###########################################
+
+Overview
+********
+
+What is SCMI?
+*************
+
+System Control and Management Interface (SCMI) is a specification developed by
+ARM, which describes a set of OS-agnostic software interfaces used to perform
+system management (e.g: clock control, pinctrl, etc...).
+
+
+Agent, platform, protocol and transport
+***************************************
+
+The SCMI specification defines **four** key terms, which will also be used throughout
+this documentation:
+
+ #. Agent
+ Entity that performs SCMI requests (e.g: gating a clock or configuring
+ a pin). In this context, Zephyr itself is an agent.
+ #. Platform
+ This refers to a set of hardware components that handle the requests from
+ agents and provide the necessary functionality. In some cases, the requests
+ are handled by a firmware, running on a core dedicated to performing system
+ management tasks.
+ #. Protocol
+ A protocol is a set of messages grouped by functionality. Intuitively, a message
+ can be thought of as a remote procedure call.
+
+ The SCMI specification defines ten standard protocols:
+
+ #. **Base** (0x10)
+ #. **Power domain management** (0x11)
+ #. **System power management** (0x12)
+ #. **Performance domain management** (0x13)
+ #. **Clock management** (0x14)
+ #. **Sensor management** (0x15)
+ #. **Reset domain management** (0x16)
+ #. **Voltage domain management** (0x17)
+ #. **Power capping and monitoring** (0x18)
+ #. **Pin Control** (0x19)
+
+ where each of these protocols is identified by an unique protocol ID
+ (listed between brackets).
+
+ Apart from the standard protocols, the SCMI specification reserves the
+ **0x80-0xFF** protocol ID range for vendor-specific protocols.
+
+
+ #. Transport
+ This describes how messages are exchanged between agents and the platform.
+ The communication itself happens through channels.
+
+.. note::
+ A system may have more than one agent.
+
+Channels
+********
+
+A **channel** is the medium through which agents and the platform exchange messages.
+The structure of a channel and the way it works is solely dependent on the transport.
+
+Each agent has its own distinct set of channels, meaning some channel A cannot be used
+by two different agents for example.
+
+Channels are **bidirectional** (exception: FastChannels), and, depending on which entity
+initiates the communication, can be one of **two** types:
+
+ #. A2P (agent to platform)
+ The agent is the initiator/requester. The messages passed through these
+ channels are known as **commands**.
+ #. P2A (platform to agent)
+ The platform is the initiator/requester.
+
+Messages
+********
+
+The SCMI specification defines **four** types of messages:
+
+ #. Synchronous
+ These are commands that block until the platform has completed the
+ requested work and are sent over A2P channels.
+ #. Asynchronous
+ For these commands, the platform schedules the requested work to
+ be performed at a later time. As such, they return almost immediately.
+ These commands are sent over A2P channels.
+ #. Delayed response
+ These messages indicate the completion of the work associated
+ with an asynchronous command. These are sent over P2A channels.
+
+ #. Notification
+ These messages are used to notify agents of events that take place on
+ the platform. These are sent over P2A channels.
+
+The Zephyr support for SCMI is based on the documentation provided by ARM:
+`DEN0056E <https://developer.arm.com/documentation/den0056/latest/>`_. For more details
+on the specification, the readers are encouraged to have a look at it.
+
+SCMI support in Zephyr
+**********************
+
+Shared memory and doorbell-based transport
+******************************************
+
+This form of transport uses shared memory for reading/writing messages
+and doorbells for signaling. The interaction with the shared
+memory area is performed using a driver (:file:`drivers/firmware/scmi/shmem.c`),
+which offers a set of functions for this exact purpose. Furthermore,
+signaling is performed using the Zephyr MBOX API (signaling mode only, no message passing).
+
+Interacting with the shared memory area and signaling are abstracted by the
+transport API, which is implemented by the shared memory and doorbell-based
+transport driver (:file:`drivers/firmware/scmi/mailbox.c`).
+
+The steps below exemplify how the communication between the Zephyr agent
+and the platform may happen using this transport:
+
+ #. Write message to the shared memory area.
+ #. Zephyr rings request doorbell. If in ``PRE_KERNEL_1`` or ``PRE_KERNEL_2`` phase start polling for reply, otherwise wait for reply doorbell ring.
+ #. Platform reads message from shared memory area, processes it, writes the reply back to the same area and rings the reply doorbell.
+ #. Zephyr reads reply from the shared memory area.
+
+In the context of this transport, a channel is comprised of a **single** shared
+memory area and one or more mailbox channels. This is because users may need/want
+to use different mailbox channels for the request/reply doorbells.
+
+
+Protocols
+*********
+
+Currently, Zephyr has support for the following standard protocols:
+
+ #. **Clock management**
+ #. **Pin Control**
+
+
+Clock management protocol
+*************************
+
+This protocol is used to perfrom clock management operations. This is done
+via a driver (:file:`drivers/clock_control/clock_control_arm_scmi.c`), which
+implements the Zephyr clock control subsytem API. As such, from the user's
+perspective, using this driver is no different than using any other clock
+management driver.
+
+.. note::
+ This driver is vendor-agnostic. As such, it may be used on any
+ system that uses SCMI for clock management operations.
+
+Pin Control protocol
+********************
+
+This protocol is used to perform pin configuration operations. This is done
+via a set of functions implementing various commands. Currently, the only
+supported command is ``PINCTRL_SETTINGS_CONFIGURE``.
+
+.. note::
+ The support for this protocol **does not** include a definition for
+ the :code:`pinctrl_configure_pins` function. Each vendor should use
+ their own definition of :code:`pinctrl_configure_pins`, which should
+ call into the SCMI pin control protocol function implementing the
+ ``PINCTRL_SETTINGS_CONFIGURE`` command.
+
+
+Enabling the SCMI support
+*************************
+
+To use the SCMI support, each vendor is required to add an ``scmi`` DT
+node (used for transport driver binding) and a ``protocol`` node under the ``scmi``
+node for each supported protocol.
+
+.. note::
+ Zephyr has no support for protocol discovery. As such, if users
+ add a DT node for a certain protocol it's assumed the platform
+ supports said protocol.
+
+The example below shows how a DT may be configured in order to use the
+SCMI support. It's assumed that the only protocol required is the clock
+management protocol.
+
+.. code-block:: devicetree
+
+ #include <mem.h>
+
+ #define MY_CLOCK_CONSUMER_CLK_ID 123
+
+ scmi_res0: memory@cafebabe {
+ /* mandatory to use shared memory driver */
+ compatible = "arm,scmi-shmem";
+ reg = <0xcafebabe DT_SIZE_K(1)>;
+ };
+
+ scmi {
+ /* compatible for shared memory and doorbell-based transport */
+ compatible = "arm,scmi";
+
+ /* one SCMI channel => A2P/transmit channel */
+ shmem = <&scmi_res0>;
+
+ /* two mailbox channels */
+ mboxes = <&my_mbox_ip 0>, <&my_mbox_ip 1>;
+ mbox-names = "tx", "tx_reply";
+
+ scmi_clk: protocol@14 {
+ compatible = "arm,scmi-clock";
+
+ /* matches the clock management protocol ID */
+ reg = <0x14>;
+
+ /* vendor-agnostic - always 1 */
+ #clock-cells = <1>;
+ };
+ };
+
+ my_mbox_ip: mailbox@deadbeef {
+ compatible = "vnd,mbox-ip";
+ reg = <0xdeadbeef DT_SIZE_K(1)>;
+ #mbox-cells = <1>;
+ };
+
+ my_clock_consumer_ip: serial@12345678 {
+ compatible = "vnd,consumer-ip";
+ reg = <0x12345678 DT_SIZE_K(1)>;
+ /* clock ID is vendor specific */
+ clocks = <&scmi_clk MY_CLOCK_CONSUMER_CLK_ID>;
+ };
+
+
+Finally, all that's left to do is enable :kconfig:option:`CONFIG_ARM_SCMI`.
diff --git a/doc/hardware/arch/index.rst b/doc/hardware/arch/index.rst
index da33dff..61ee33d 100644
--- a/doc/hardware/arch/index.rst
+++ b/doc/hardware/arch/index.rst
@@ -12,3 +12,4 @@
semihost.rst
x86.rst
xtensa.rst
+ arm-scmi.rst
diff --git a/doc/hardware/emulator/bus_emulators.rst b/doc/hardware/emulator/bus_emulators.rst
index 76250b4..87e18fe 100644
--- a/doc/hardware/emulator/bus_emulators.rst
+++ b/doc/hardware/emulator/bus_emulators.rst
@@ -144,6 +144,38 @@
* MSPI emulator driver, allowing drivers to be connected to an emulator so that
tests can be performed without access to the real hardware.
+I2C Emulation features
+----------------------
+
+In the binding of the I2C emulated bus, there's a custom property for address
+based forwarding. Given the following devicetree node:
+
+.. code-block:: devicetree
+
+ i2c0: i2c@100 {
+ status = "okay";
+ compatible = "zephyr,i2c-emul-controller";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #forward-cells = <1>;
+ reg = <0x100 4>;
+ forwards = <&i2c1 0x20>;
+ };
+
+The final property, ``forwards`` indicates that any read/write requests sent to
+address ``0x20`` should be sent to ``i2c1`` with the same address. This allows
+us to test both the controller and the target end of the communication on the
+same image.
+
+.. note::
+ The ``#forward-cells`` attribute should always be 1. Each entry in the
+ ``forwards`` attribute consists of the phandle followed by the address. In
+ the example above, ``<&i2c1 0x20>`` will forward all read/write operations
+ made to ``i2c0`` at port ``0x20`` to ``i2c1`` on the same port. Since no
+ additional cells are used by the emulated controller, the number of cells
+ should remain 1.
+
Samples
=======
@@ -166,6 +198,6 @@
:gen-args: -DDTC_OVERLAY_FILE=at2x_emul.overlay -DOVERLAY_CONFIG=at2x_emul.conf
API Reference
-*************
+=============
.. doxygengroup:: io_emulators
diff --git a/doc/kernel/iterable_sections/index.rst b/doc/kernel/iterable_sections/index.rst
index 330e46b..46ef4a3 100644
--- a/doc/kernel/iterable_sections/index.rst
+++ b/doc/kernel/iterable_sections/index.rst
@@ -32,7 +32,7 @@
DEFINE_DATA(d2, 3, 4);
DEFINE_DATA(d3, 5, 6);
-Then the linker has to be setup to place the place the structure in a
+Then the linker has to be setup to place the structure in a
contiguous segment using one of the linker macros such as
:c:macro:`ITERABLE_SECTION_RAM` or :c:macro:`ITERABLE_SECTION_ROM`. Custom
linker snippets are normally declared using one of the
diff --git a/doc/known-warnings.txt b/doc/known-warnings.txt
deleted file mode 100644
index 72ad03d..0000000
--- a/doc/known-warnings.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-# Each line should contain the regular expression of a known Sphinx warning
-# that should be filtered out
diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst
index 740c38e..b8c490b 100644
--- a/doc/releases/migration-guide-4.0.rst
+++ b/doc/releases/migration-guide-4.0.rst
@@ -24,6 +24,9 @@
Boards
******
+* :ref:`native_posix<native_posix>` has been deprecated in favour of
+ :ref:`native_sim<native_sim>` (:github:`76898`).
+
Modules
*******
@@ -85,6 +88,14 @@
LED Strip
=========
+SDHC
+====
+
+* The NXP USDHC driver now assumes a card is present if no card detect method
+ is configured, instead of using the peripheral's internal card detect signal
+ to check for card presence. To use the internal card detect signal, the
+ devicetree property ``detect-cd`` should be added to the USDHC node in use.
+
Sensors
=======
@@ -147,6 +158,12 @@
Bluetooth Audio
===============
+* The Volume Renderer callback functions :code:`bt_vcp_vol_rend_cb.state` and
+ :code:`bt_vcp_vol_rend_cb.flags` for VCP now contain an additional parameter for
+ the connection.
+ This needs to be added to all instances of VCP Volume Renderer callback functions defined.
+ (:github:`76992`)
+
Bluetooth Classic
=================
@@ -165,6 +182,10 @@
:c:func:`coap_get_block2_option` now accepts an additional ``bool *has_more``
parameter, to store the value of the more flag. (:github:`76052`)
+* The Ethernet bridge shell is moved under network shell. This is done so that
+ all the network shell activities can be found under ``net`` shell command.
+ After this change the bridge shell is used by ``net bridge`` command.
+
Other Subsystems
****************
diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst
index 8e24ac17..3ec6f68 100644
--- a/doc/releases/release-notes-4.0.rst
+++ b/doc/releases/release-notes-4.0.rst
@@ -24,12 +24,26 @@
API Changes
***********
+* Removed deprecated arch-level CMSIS header files
+ ``include/zephyr/arch/arm/cortex_a_r/cmsis.h`` and
+ ``include/zephyr/arch/arm/cortex_m/cmsis.h``. ``cmsis_core.h`` needs to be
+ included now.
+
+* Removed deprecated ``ceiling_fraction`` macro. :c:macro:`DIV_ROUND_UP` needs
+ to be used now.
+
+* Deprecated ``EARLY``, ``APPLICATION`` and ``SMP`` init levels can no longer be
+ used for devices.
+
Removed APIs in this release
============================
Deprecated in this release
==========================
+* Deprecated the :c:func:`net_buf_put` and :c:func:`net_buf_get` API functions in favor of
+ :c:func:`k_fifo_put` and :c:func:`k_fifo_get`.
+
Architectures
*************
@@ -53,6 +67,9 @@
* Host
+ * Added API :c:func:`bt_gatt_get_uatt_mtu` to get current Unenhanced ATT MTU of a given
+ connection (experimental).
+
* HCI Drivers
Boards & SoC Support
@@ -62,10 +79,16 @@
* Made these changes in other SoC series:
+ * NXP S32Z270: Added support for the new silicon cut version 2.0. Note that the previous
+ versions (1.0 and 1.1) are no longer supported.
+
* Added support for these boards:
* Made these board changes:
+ * :ref:`native_posix<native_posix>` has been deprecated in favour of
+ :ref:`native_sim<native_sim>`.
+
* Added support for the following shields:
Build system and Infrastructure
diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst
index 14ba12e..27306d4 100644
--- a/doc/security/vulnerabilities.rst
+++ b/doc/security/vulnerabilities.rst
@@ -1732,7 +1732,15 @@
CVE-2024-4785
-------------
-Under embargo until 2024-08-07
+Bluetooth: Missing Check in LL_CONNECTION_UPDATE_IND Packet Leads to Division by Zero
+
+- `Zephyr project bug tracker GHSA-xcr5-5g98-mchp
+ <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-xcr5-5g98-mchp>`_
+
+This has been fixed in main for v3.7.0
+
+- `PR 72608 fix for main
+ <https://github.com/zephyrproject-rtos/zephyr/pull/72608>`_
CVE-2024-5754
-------------
diff --git a/doc/services/index.rst b/doc/services/index.rst
index b8c0534..d900f11 100644
--- a/doc/services/index.rst
+++ b/doc/services/index.rst
@@ -28,6 +28,7 @@
pm/index.rst
portability/index.rst
poweroff.rst
+ profiling/index.rst
shell/index.rst
serialization/index.rst
settings/index.rst
diff --git a/doc/services/input/index.rst b/doc/services/input/index.rst
index 111d6a0..e42af58 100644
--- a/doc/services/input/index.rst
+++ b/doc/services/input/index.rst
@@ -100,6 +100,8 @@
matrix to key events.
- :dtcompatible:`zephyr,input-longpress`: listens for key events, emits events
for short and long press.
+- :dtcompatible:`zephyr,input-double-tap`: listens for key events, emits events
+ for input double taps
- :dtcompatible:`zephyr,lvgl-button-input`
:dtcompatible:`zephyr,lvgl-encoder-input`
:dtcompatible:`zephyr,lvgl-keypad-input`
diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst
index 5526b7b..588ac90 100644
--- a/doc/services/portability/posix/option_groups/index.rst
+++ b/doc/services/portability/posix/option_groups/index.rst
@@ -242,10 +242,10 @@
opendir(), yes
pathconf(),
readdir(), yes
- remove(),
+ remove(), yes
rename(), yes
rewinddir(),
- rmdir(),
+ rmdir(), yes
stat(), yes
statvfs(),
tmpfile(),
@@ -981,8 +981,8 @@
:header: API, Supported
:widths: 50,10
- asctime_r(),
- ctime_r(),
+ asctime_r(), yes
+ ctime_r(), yes (UTC timezone only)
flockfile(),
ftrylockfile(),
funlockfile(),
@@ -993,7 +993,7 @@
getpwnam_r(),yes :ref:`†<posix_undefined_behaviour>`
getpwuid_r(),yes :ref:`†<posix_undefined_behaviour>`
gmtime_r(), yes
- localtime_r(),
+ localtime_r(), yes (UTC timezone only)
putc_unlocked(),
putchar_unlocked(),
rand_r(), yes
diff --git a/doc/services/profiling/index.rst b/doc/services/profiling/index.rst
new file mode 100644
index 0000000..a6040a4
--- /dev/null
+++ b/doc/services/profiling/index.rst
@@ -0,0 +1,11 @@
+.. _profiling:
+
+Profiling
+#########
+
+Required Kconfig: :kconfig:option:`CONFIG_PROFILING`
+
+.. toctree::
+ :maxdepth: 1
+
+ perf.rst
diff --git a/doc/services/profiling/perf.rst b/doc/services/profiling/perf.rst
new file mode 100644
index 0000000..7034db8
--- /dev/null
+++ b/doc/services/profiling/perf.rst
@@ -0,0 +1,38 @@
+.. _profiling-perf:
+
+Perf
+####
+
+Perf is a profiler tool based on stack tracing. It can be used for lightweight profiling
+with minimal code overhead.
+
+Work Principle
+**************
+
+The ``perf record`` shell command starts a timer with the perf tracer function.
+Timers are driven by interrupts, so the perf tracer function is called during an interruption.
+The Zephyr core saves the return address and frame pointer in the interrupt stack or ``callee_saved``
+structure before calling the interrupt handler. Thus, the perf trace function makes stack traces by
+using the return address and frame pointer.
+
+The :zephyr_file:`scripts/profiling/stackcollapse.py` script can be used to convert return addresses
+in the stack trace to function names using symbols from the ELF file, and to prints them in the
+format expected by `FlameGraph`_.
+
+Configuration
+*************
+
+You can configure this module using the following options:
+
+* :kconfig:option:`CONFIG_PROFILING_PERF`: Enables the module. This option adds
+ the ``perf`` command to the shell.
+
+* :kconfig:option:`CONFIG_PROFILING_PERF_BUFFER_SIZE`: Sets the size of the perf buffer
+ where samples are saved before printing.
+
+Usage
+*****
+
+Refer to the :zephyr:code-sample:`profiling-perf` sample for an example of how to use the perf tool.
+
+ .. _FlameGraph: https://github.com/brendangregg/FlameGraph/
diff --git a/doc/services/tracing/index.rst b/doc/services/tracing/index.rst
index eb32d38..51ed14e 100644
--- a/doc/services/tracing/index.rst
+++ b/doc/services/tracing/index.rst
@@ -7,7 +7,7 @@
********
The tracing feature provides hooks that permits you to collect data from
-your application and allows tools running on a host to visualize the inner-working of
+your application and allows :ref:`tools` running on a host to visualize the inner-working of
the kernel and various subsystems.
Every system has application-specific events to trace out. Historically,
@@ -92,6 +92,262 @@
:kconfig:option:`CONFIG_TRACING_CTF` and can be used with the different transport
backends both in synchronous and asynchronous modes.
+.. _tools:
+
+Tracing Tools
+*************
+
+Zephyr includes support for several popular tracing tools, presented below in alphabetical order.
+
+Percepio Tracealyzer Support
+============================
+
+Zephyr includes support for `Percepio Tracealyzer`_ that offers trace visualization for
+simplified analysis, report generation and other analysis features. Tracealyzer allows for trace
+streaming over various interfaces and also snapshot tracing, where the events are kept in a RAM
+buffer.
+
+.. _Percepio Tracealyzer: https://percepio.com/tracealyzer
+
+.. figure:: percepio_tracealyzer.png
+ :align: center
+ :alt: Percepio Tracealyzer
+ :figclass: align-center
+ :width: 80%
+
+Zephyr kernel events are captured automatically when Tracealyzer tracing is enabled.
+Tracealyzer also provides extensive support for application logging, where you call the tracing
+library from your application code. This lets you visualize kernel events and application events
+together, for example as data plots or state diagrams on logged variables.
+Learn more in the Tracealyzer User Manual provided with the application.
+
+Percepio TraceRecorder and Stream Ports
+---------------------------------------
+The tracing library for Tracealyzer (TraceRecorder) is included in the Zephyr manifest and
+provided under the same license (Apache 2.0). This is enabled by adding the following
+configuration options in your prj.conf:
+
+.. code-block:: cfg
+
+ CONFIG_TRACING=y
+ CONFIG_PERCEPIO_TRACERECORDER=y
+
+Or using menuconfig:
+
+* Enable :menuselection:`Subsystems and OS Services --> Tracing Support`
+* Under :menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Format`, select
+ :guilabel:`Percepio Tracealyzer`
+
+Some additional settings are needed to configure TraceRecorder. The most important configuration
+is to select the right "stream port". This specifies how to output the trace data.
+As of July 2024, the following stream ports are available in the Zephyr configuration system:
+
+* **Ring Buffer**: The trace data is kept in a circular RAM buffer.
+* **RTT**: Trace streaming via Segger RTT on J-Link debug probes.
+* **ITM**: Trace streaming via the ITM function on Arm Cortex-M devices.
+* **Semihost**: For tracing on QEMU. Streams the trace data to a host file.
+
+Select the stream port in menuconfig under
+:menuselection:`Modules --> percepio --> TraceRecorder --> Stream Port`.
+
+Or simply add one of the following options in your prj.conf:
+
+.. code-block:: cfg
+
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RINGBUFFER=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RTT=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_ITM=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_ZEPHYR_SEMIHOST=y
+
+Make sure to only include ONE of these configuration options.
+
+The stream port modules have individual configuration options. In menuconfig these are found
+under :menuselection:`Modules --> percepio --> TraceRecorder --> (Stream Port) Config`.
+The most important options for each stream port are described below.
+
+Tracealyzer Snapshot Tracing (Ring Buffer)
+------------------------------------------
+
+The "Ring Buffer" stream port keeps the trace data in a RAM buffer on the device.
+By default, this is a circular buffer, meaning that it always contains the most recent data.
+This is used to dump "snapshots" of the trace data, e.g. by using the debugger. This usually only
+allows for short traces, unless you have megabytes of RAM to spare, so it is not suitable for
+profiling. However, it can be quite useful for debugging in combination with breakpoints.
+For example, if you set a breakpoint in an error handler, a snapshot trace can show the sequence
+of events leading up to the error. Snapshot tracing is also easy to begin with, since it doesn't
+depend on any particular debug probe or other development tool.
+
+To use the Ring Buffer option, make sure to have the following configuration options in your
+prj.cnf:
+
+.. code-block:: cfg
+
+ CONFIG_TRACING=y
+ CONFIG_PERCEPIO_TRACERECORDER=y
+ CONFIG_PERCEPIO_TRC_START_MODE_START=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RINGBUFFER=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RINGBUFFER_SIZE=<size in bytes>
+
+Or if using menuconfig:
+
+* Enable :menuselection:`Subsystems and OS Services --> Tracing Support`
+* Under :menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Format`, select
+ :guilabel:`Percepio Tracealyzer`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Recorder Start Mode`, select
+ :guilabel:`Start`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Stream Port`, select
+ :guilabel:`Ring Buffer`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Ring Buffer Config --> Buffer Size`,
+ set the buffer size in bytes.
+
+The default buffer size can be reduced if you are tight on RAM, or increased if you have RAM to
+spare and want longer traces. You may also optimize the Tracing Configuration settings to get
+longer traces by filtering out less important events.
+In menuconfig, see
+:menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Configuration`.
+
+To view the trace data, the easiest way is to start your debugger (west debug) and run the
+following GDB command::
+
+ dump binary value trace.bin *RecorderDataPtr
+
+The resulting file is typically found in the root of the build folder, unless a different path is
+specified. Open this file in Tracealyzer by selecting :menuselection:`File --> Open --> Open File`.
+
+Tracealyzer Streaming with SEGGER RTT
+-------------------------------------
+
+Tracealyzer has built-in support for SEGGER RTT to receive trace data using a J-Link probe.
+This allows for recording very long traces. To configure Zephyr for RTT streaming to Tracealyzer,
+add the following configuration options in your prj.cnf:
+
+.. code-block:: cfg
+
+ CONFIG_TRACING=y
+ CONFIG_PERCEPIO_TRACERECORDER=y
+ CONFIG_PERCEPIO_TRC_START_MODE_START_FROM_HOST=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RTT=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_RTT_UP_BUFFER_SIZE=<size in bytes>
+
+Or if using menuconfig:
+
+* Enable :menuselection:`Subsystems and OS Services --> Tracing Support`
+* Under :menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Format`, select
+ :guilabel:`Percepio Tracealyzer`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Recorder Start Mode`, select
+ :guilabel:`Start From Host`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Stream Port`, select
+ :guilabel:`RTT`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> RTT Config`, set the size of the
+ RTT "up" buffer in bytes.
+
+The setting :guilabel:`RTT buffer size up` sets the size of the RTT transmission buffer. This is important
+for throughput. By default this buffer is quite large, 5000 bytes, to give decent performance
+also on onboard J-Link debuggers (they are not as fast as the stand-alone probes).
+If you are tight on RAM, you may consider reducing this setting. If using a regular J-Link probe
+it is often sufficient with a much smaller buffer, e.g. 1 KB or less.
+
+Learn more about RTT streaming in the Tracealyzer User Manual.
+See Creating and Loading Traces -> Percepio TraceRecorder -> Using TraceRecorder v4.6 or later ->
+Stream ports (or search for RTT).
+
+Tracealyzer Streaming with Arm ITM
+----------------------------------
+
+This stream port is for Arm Cortex-M devices featuring the ITM unit. It is recommended to use a
+fast debug probe that allows for SWO speeds of 10 MHz or higher. To use this stream port,
+apply the following configuration options:
+
+.. code-block:: cfg
+
+ CONFIG_TRACING=y
+ CONFIG_PERCEPIO_TRACERECORDER=y
+ CONFIG_PERCEPIO_TRC_START_MODE_START=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_ITM=y
+ CONFIG_PERCEPIO_TRC_CFG_ITM_PORT=1
+
+Or if using menuconfig:
+
+* Enable :menuselection:`Subsystems and OS Services --> Tracing Support`
+* Under :menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Format`, select
+ :guilabel:`Percepio Tracealyzer`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Recorder Start Mode`, select
+ :guilabel:`Start`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Stream Port`, select
+ :guilabel:`ITM`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> ITM Config`, set the ITM port to
+ 1.
+
+The main setting for the ITM stream port is the ITM port (0-31). A dedicated channel is needed
+for Tracealyzer. Port 0 is usually reserved for printf logging, so channel 1 is used by default.
+
+The option :guilabel:`Use internal buffer` should typically remain disabled. It buffers the data in RAM
+before transmission and defers the data transmission to the periodic TzCtrl thread.
+
+The host-side setup depends on what debug probe you are using. Learn more in the Tracealyzer
+User Manual.
+See :menuselection:`Creating and Loading Traces --> Percepio TraceRecorder --> Using TraceRecorder v4.6 or later --> Stream ports (or search for ITM)`.
+
+Tracealyzer Streaming from QEMU (Semihost)
+------------------------------------------
+
+This stream port is designed for Zephyr tracing in QEMU. This can be an easy way to get started
+with tracing and try out streaming trace without needing a fast debug probe. The data is streamed
+to a host file using semihosting. To use this option, apply the following configuration options:
+
+.. code-block:: cfg
+
+ CONFIG_SEMIHOST=y
+ CONFIG_TRACING=y
+ CONFIG_PERCEPIO_TRACERECORDER=y
+ CONFIG_PERCEPIO_TRC_START_MODE_START=y
+ CONFIG_PERCEPIO_TRC_CFG_STREAM_PORT_ZEPHYR_SEMIHOST=y
+
+Using menuconfig
+
+* Enable :menuselection:`General Architecture Options --> Semihosting support for Arm and RISC-V targets`
+* Enable :menuselection:`Subsystems and OS Services --> Tracing Support`
+* Under :menuselection:`Subsystems and OS Services --> Tracing Support --> Tracing Format`, select
+ :guilabel:`Percepio Tracealyzer`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Recorder Start Mode`, select
+ :guilabel:`Start`
+* Under :menuselection:`Modules --> percepio --> TraceRecorder --> Stream Port`, select
+ :guilabel:`Semihost`
+
+By default, the resulting trace file is found in :file:`./trace.psf` in the root of the build folder,
+unless a different path is specified. Open this file in `Percepio Tracealyzer`_ by selecting
+:menuselection:`File --> Open --> Open File`.
+
+Recorder Start Mode
+-------------------
+
+You may have noticed the :guilabel:`Recorder Start Mode` option in the Tracealyzer examples above.
+This decides when the tracing starts. With the option :guilabel:`Start`, the tracing begins directly
+at startup, once the TraceRecorder library has been initialized. This is recommended when using the
+Ring Buffer and Semihost stream ports.
+
+For streaming via RTT or ITM you may also use :guilabel:`Start From Host` or
+:guilabel:`Start Await Host`. Both listens for start commands from the Tracealyzer application. The
+latter option, :guilabel:`Start Await Host`, causes the TraceRecorder initialization to block until
+the start command is received from the Tracealyzer application.
+
+Custom Stream Ports for Tracealyzer
+-----------------------------------
+
+The stream ports are small modules within TraceRecorder that define what functions to call to
+output the trace data and (optionally) how to read start/stop commands from Tracealyzer.
+It is fairly easy to make custom stream ports to implement your own data transport and
+Tracealyzer can receive trace streams over various interfaces, including files, sockets,
+COM ports, named pipes and more. Note that additional stream port modules are available in the
+TraceRecorder repo (e.g. lwIP), although they might require modifications to work with Zephyr.
+
+Learning More
+-------------
+
+Learn more about how to get started in the `Tracealyzer Getting Started Guides`_.
+
+.. _Tracealyzer Getting Started Guides: https://percepio.com/tracealyzer/gettingstarted/
+
SEGGER SystemView Support
=========================
@@ -141,6 +397,18 @@
# On Linux and MacOS
cp $ZEPHYR_BASE/subsys/tracing/sysview/SYSVIEW_Zephyr.txt ~/.config/SEGGER/
+TraceCompass
+=============
+
+TraceCompass is an open source tool that visualizes CTF events such as thread
+scheduling and interrupts, and is helpful to find unintended interactions and
+resource conflicts on complex systems.
+
+See also the presentation by Ericsson,
+`Advanced Trouble-shooting Of Real-time Systems
+<https://wiki.eclipse.org/images/0/0e/TechTalkOnlineDemoFeb2017_v1.pdf>`_.
+
+
User-Defined Tracing
====================
@@ -226,22 +494,6 @@
The resulting channel0_0 file have to be placed in a directory with the ``metadata``
file like the other backend.
-Visualisation Tools
-*******************
-
-TraceCompass
-=============
-
-TraceCompass is an open source tool that visualizes CTF events such as thread
-scheduling and interrupts, and is helpful to find unintended interactions and
-resource conflicts on complex systems.
-
-See also the presentation by Ericsson,
-`Advanced Trouble-shooting Of Real-time Systems
-<https://wiki.eclipse.org/images/0/0e/TechTalkOnlineDemoFeb2017_v1.pdf>`_.
-
-
-
Future LTTng Inspiration
************************
@@ -488,3 +740,13 @@
========
.. doxygengroup:: subsys_tracing_apis_syscall
+
+Network tracing
+===============
+
+.. doxygengroup:: subsys_tracing_apis_net
+
+Network socket tracing
+======================
+
+.. doxygengroup:: subsys_tracing_apis_socket
diff --git a/doc/services/tracing/percepio_tracealyzer.png b/doc/services/tracing/percepio_tracealyzer.png
new file mode 100644
index 0000000..abda9d7
--- /dev/null
+++ b/doc/services/tracing/percepio_tracealyzer.png
Binary files differ
diff --git a/doc/zephyr.doxyfile.in b/doc/zephyr.doxyfile.in
index 47472ee..914689a 100644
--- a/doc/zephyr.doxyfile.in
+++ b/doc/zephyr.doxyfile.in
@@ -1,7 +1,7 @@
-# Doxyfile 1.9.6
+# Doxyfile 1.12.0
# This file describes the settings to be used by the documentation system
-# doxygen (www.doxygen.org) for a project.
+# Doxygen (www.doxygen.org) for a project.
#
# All text after a double hash (##) is considered a comment and is placed in
# front of the TAG it is preceding.
@@ -15,10 +15,10 @@
#
# Note:
#
-# Use doxygen to compare the used configuration file with the template
+# Use Doxygen to compare the used configuration file with the template
# configuration file:
# doxygen -x [configFile]
-# Use doxygen to compare the used configuration file with the template
+# Use Doxygen to compare the used configuration file with the template
# configuration file without replacing the environment variables or CMake type
# replacement variables:
# doxygen -x_noenv [configFile]
@@ -63,17 +63,23 @@
PROJECT_LOGO = @ZEPHYR_BASE@/doc/_doxygen/logo.svg
+# With the PROJECT_ICON tag one can specify an icon that is included in the tabs
+# when the HTML document is shown. Doxygen will copy the logo to the output
+# directory.
+
+PROJECT_ICON =
+
# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
# into which the generated documentation will be written. If a relative path is
-# entered, it will be relative to the location where doxygen was started. If
+# entered, it will be relative to the location where Doxygen was started. If
# left blank the current directory will be used.
OUTPUT_DIRECTORY = @DOXY_OUT@
-# If the CREATE_SUBDIRS tag is set to YES then doxygen will create up to 4096
+# If the CREATE_SUBDIRS tag is set to YES then Doxygen will create up to 4096
# sub-directories (in 2 levels) under the output directory of each output format
# and will distribute the generated files over these directories. Enabling this
-# option can be useful when feeding doxygen a huge amount of source files, where
+# option can be useful when feeding Doxygen a huge amount of source files, where
# putting all generated files in the same directory would otherwise causes
# performance problems for the file system. Adapt CREATE_SUBDIRS_LEVEL to
# control the number of sub-directories.
@@ -92,7 +98,7 @@
CREATE_SUBDIRS_LEVEL = 8
-# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# If the ALLOW_UNICODE_NAMES tag is set to YES, Doxygen will allow non-ASCII
# characters to appear in the names of generated files. If set to NO, non-ASCII
# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
# U+3044.
@@ -101,7 +107,7 @@
ALLOW_UNICODE_NAMES = NO
# The OUTPUT_LANGUAGE tag is used to specify the language in which all
-# documentation generated by doxygen is written. Doxygen will use this
+# documentation generated by Doxygen is written. Doxygen will use this
# information to generate all constant output in the proper language.
# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Bulgarian,
# Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, English
@@ -115,14 +121,14 @@
OUTPUT_LANGUAGE = English
-# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# If the BRIEF_MEMBER_DESC tag is set to YES, Doxygen will include brief member
# descriptions after the members that are listed in the file and class
# documentation (similar to Javadoc). Set to NO to disable this.
# The default value is: YES.
BRIEF_MEMBER_DESC = YES
-# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# If the REPEAT_BRIEF tag is set to YES, Doxygen will prepend the brief
# description of a member or function before the detailed description
#
# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
@@ -143,13 +149,13 @@
ABBREVIATE_BRIEF = YES
# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
-# doxygen will generate a detailed section even if there is only a brief
+# Doxygen will generate a detailed section even if there is only a brief
# description.
# The default value is: NO.
ALWAYS_DETAILED_SEC = YES
-# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# If the INLINE_INHERITED_MEMB tag is set to YES, Doxygen will show all
# inherited members of a class in the documentation of that class as if those
# members were ordinary class members. Constructors, destructors and assignment
# operators of the base classes will not be shown.
@@ -157,7 +163,7 @@
INLINE_INHERITED_MEMB = YES
-# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# If the FULL_PATH_NAMES tag is set to YES, Doxygen will prepend the full path
# before files name in the file list and in the header files. If set to NO the
# shortest path that makes the file name unique will be used
# The default value is: YES.
@@ -167,11 +173,11 @@
# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
# Stripping is only done if one of the specified strings matches the left-hand
# part of the path. The tag can be used to show relative paths in the file list.
-# If left blank the directory from which doxygen is run is used as the path to
+# If left blank the directory from which Doxygen is run is used as the path to
# strip.
#
# Note that you can specify absolute paths here, but also relative paths, which
-# will be relative from the directory where doxygen is started.
+# will be relative from the directory where Doxygen is started.
# This tag requires that the tag FULL_PATH_NAMES is set to YES.
STRIP_FROM_PATH = @ZEPHYR_BASE@/include
@@ -185,14 +191,14 @@
STRIP_FROM_INC_PATH =
-# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# If the SHORT_NAMES tag is set to YES, Doxygen will generate much shorter (but
# less readable) file names. This can be useful is your file systems doesn't
# support long names like on DOS, Mac, or CD-ROM.
# The default value is: NO.
SHORT_NAMES = NO
-# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen will interpret the
# first line (until the first dot) of a Javadoc-style comment as the brief
# description. If set to NO, the Javadoc-style will behave just like regular Qt-
# style comments (thus requiring an explicit @brief command for a brief
@@ -201,17 +207,17 @@
JAVADOC_AUTOBRIEF = YES
-# If the JAVADOC_BANNER tag is set to YES then doxygen will interpret a line
+# If the JAVADOC_BANNER tag is set to YES then Doxygen will interpret a line
# such as
# /***************
# as being the beginning of a Javadoc-style comment "banner". If set to NO, the
# Javadoc-style will behave just like regular comments and it will not be
-# interpreted by doxygen.
+# interpreted by Doxygen.
# The default value is: NO.
JAVADOC_BANNER = NO
-# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will interpret the first
# line (until the first dot) of a Qt-style comment as the brief description. If
# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
# requiring an explicit \brief command for a brief description.)
@@ -219,7 +225,7 @@
QT_AUTOBRIEF = YES
-# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen treat a
# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
# a brief description. This used to be the default behavior. The new default is
# to treat a multi-line C++ comment block as a detailed description. Set this
@@ -231,10 +237,10 @@
MULTILINE_CPP_IS_BRIEF = NO
-# By default Python docstrings are displayed as preformatted text and doxygen's
+# By default Python docstrings are displayed as preformatted text and Doxygen's
# special commands cannot be used. By setting PYTHON_DOCSTRING to NO the
-# doxygen's special commands can be used and the contents of the docstring
-# documentation blocks is shown as doxygen documentation.
+# Doxygen's special commands can be used and the contents of the docstring
+# documentation blocks is shown as Doxygen documentation.
# The default value is: YES.
PYTHON_DOCSTRING = YES
@@ -245,7 +251,7 @@
INHERIT_DOCS = YES
-# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then Doxygen will produce a new
# page for each member. If set to NO, the documentation of a member will be part
# of the file/class/namespace that contains it.
# The default value is: NO.
@@ -329,30 +335,30 @@
# parses. With this tag you can assign which parser to use for a given
# extension. Doxygen has a built-in mapping, but you can override or extend it
# using this tag. The format is ext=language, where ext is a file extension, and
-# language is one of the parsers supported by doxygen: IDL, Java, JavaScript,
+# language is one of the parsers supported by Doxygen: IDL, Java, JavaScript,
# Csharp (C#), C, C++, Lex, D, PHP, md (Markdown), Objective-C, Python, Slice,
# VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran:
# FortranFree, unknown formatted Fortran: Fortran. In the later case the parser
# tries to guess whether the code is fixed or free formatted code, this is the
-# default for Fortran type files). For instance to make doxygen treat .inc files
+# default for Fortran type files). For instance to make Doxygen treat .inc files
# as Fortran files (default is PHP), and .f files as C (default is Fortran),
# use: inc=Fortran f=C.
#
# Note: For files without extension you can use no_extension as a placeholder.
#
# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
-# the files are not read by doxygen. When specifying no_extension you should add
+# the files are not read by Doxygen. When specifying no_extension you should add
# * to the FILE_PATTERNS.
#
# Note see also the list of default file extension mappings.
EXTENSION_MAPPING =
-# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# If the MARKDOWN_SUPPORT tag is enabled then Doxygen pre-processes all comments
# according to the Markdown format, which allows for more readable
# documentation. See https://daringfireball.net/projects/markdown/ for details.
-# The output of markdown processing is further processed by doxygen, so you can
-# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# The output of markdown processing is further processed by Doxygen, so you can
+# mix Doxygen, HTML, and XML commands with Markdown formatting. Disable only in
# case of backward compatibilities issues.
# The default value is: YES.
@@ -362,12 +368,23 @@
# to that level are automatically included in the table of contents, even if
# they do not have an id attribute.
# Note: This feature currently applies only to Markdown headings.
-# Minimum value: 0, maximum value: 99, default value: 5.
+# Minimum value: 0, maximum value: 99, default value: 6.
# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
TOC_INCLUDE_HEADINGS = 5
-# When enabled doxygen tries to link words that correspond to documented
+# The MARKDOWN_ID_STYLE tag can be used to specify the algorithm used to
+# generate identifiers for the Markdown headings. Note: Every identifier is
+# unique.
+# Possible values are: DOXYGEN use a fixed 'autotoc_md' string followed by a
+# sequence number starting at 0 and GITHUB use the lower case version of title
+# with any whitespace replaced by '-' and punctuation characters removed.
+# The default value is: DOXYGEN.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+MARKDOWN_ID_STYLE = DOXYGEN
+
+# When enabled Doxygen tries to link words that correspond to documented
# classes, or namespaces to their corresponding documentation. Such a link can
# be prevented in individual cases by putting a % sign in front of the word or
# globally by setting AUTOLINK_SUPPORT to NO.
@@ -377,10 +394,10 @@
# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
# to include (a tag file for) the STL sources as input, then you should set this
-# tag to YES in order to let doxygen match functions declarations and
+# tag to YES in order to let Doxygen match functions declarations and
# definitions whose arguments contain STL classes (e.g. func(std::string);
-# versus func(std::string) {}). This also make the inheritance and collaboration
-# diagrams that involve STL classes more complete and accurate.
+# versus func(std::string) {}). This also makes the inheritance and
+# collaboration diagrams that involve STL classes more complete and accurate.
# The default value is: NO.
BUILTIN_STL_SUPPORT = NO
@@ -392,16 +409,16 @@
CPP_CLI_SUPPORT = YES
# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
-# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen
-# will parse them like normal C++ but will assume all classes use public instead
-# of private inheritance when no explicit protection keyword is present.
+# https://www.riverbankcomputing.com/software) sources only. Doxygen will parse
+# them like normal C++ but will assume all classes use public instead of private
+# inheritance when no explicit protection keyword is present.
# The default value is: NO.
SIP_SUPPORT = NO
# For Microsoft's IDL there are propget and propput attributes to indicate
# getter and setter methods for a property. Setting this option to YES will make
-# doxygen to replace the get and set methods by a property in the documentation.
+# Doxygen to replace the get and set methods by a property in the documentation.
# This will only work if the methods are indeed getting or setting a simple
# type. If this is not the case, or you want to show the methods anyway, you
# should set this option to NO.
@@ -410,7 +427,7 @@
IDL_PROPERTY_SUPPORT = YES
# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
-# tag is set to YES then doxygen will reuse the documentation of the first
+# tag is set to YES then Doxygen will reuse the documentation of the first
# member in the group (if any) for the other members of the group. By default
# all members of a group must be documented explicitly.
# The default value is: NO.
@@ -468,18 +485,18 @@
# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
# cache is used to resolve symbols given their name and scope. Since this can be
# an expensive process and often the same symbol appears multiple times in the
-# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
-# doxygen will become slower. If the cache is too large, memory is wasted. The
+# code, Doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# Doxygen will become slower. If the cache is too large, memory is wasted. The
# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
-# symbols. At the end of a run doxygen will report the cache usage and suggest
+# symbols. At the end of a run Doxygen will report the cache usage and suggest
# the optimal cache size from a speed point of view.
# Minimum value: 0, maximum value: 9, default value: 0.
LOOKUP_CACHE_SIZE = 9
-# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use
-# during processing. When set to 0 doxygen will based this on the number of
+# The NUM_PROC_THREADS specifies the number of threads Doxygen is allowed to use
+# during processing. When set to 0 Doxygen will based this on the number of
# cores available in the system. You can set it explicitly to a value larger
# than 0 to get more control over the balance between CPU load and processing
# speed. At this moment only the input processing can be done using multiple
@@ -491,11 +508,19 @@
NUM_PROC_THREADS = 1
+# If the TIMESTAMP tag is set different from NO then each generated page will
+# contain the date or date and time when the page was generated. Setting this to
+# NO can help when comparing the output of multiple runs.
+# Possible values are: YES, NO, DATETIME and DATE.
+# The default value is: NO.
+
+TIMESTAMP = YES
+
#---------------------------------------------------------------------------
# Build related configuration options
#---------------------------------------------------------------------------
-# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# If the EXTRACT_ALL tag is set to YES, Doxygen will assume all entities in
# documentation are documented, even if no documentation was available. Private
# class members and static file members will be hidden unless the
# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
@@ -561,7 +586,7 @@
RESOLVE_UNNAMED_PARAMS = YES
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
# undocumented members inside documented classes or files. If set to NO these
# members will be included in the various overviews, but no documentation
# section is generated. This option has no effect if EXTRACT_ALL is enabled.
@@ -569,7 +594,7 @@
HIDE_UNDOC_MEMBERS = NO
-# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
# undocumented classes that are normally visible in the class hierarchy. If set
# to NO, these classes will be included in the various overviews. This option
# will also hide undocumented C++ concepts if enabled. This option has no effect
@@ -578,14 +603,14 @@
HIDE_UNDOC_CLASSES = NO
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all friend
# declarations. If set to NO, these declarations will be included in the
# documentation.
# The default value is: NO.
HIDE_FRIEND_COMPOUNDS = NO
-# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
# documentation blocks found inside the body of a function. If set to NO, these
# blocks will be appended to the function's detailed documentation block.
# The default value is: NO.
@@ -599,7 +624,7 @@
INTERNAL_DOCS = NO
-# With the correct setting of option CASE_SENSE_NAMES doxygen will better be
+# With the correct setting of option CASE_SENSE_NAMES Doxygen will better be
# able to match the capabilities of the underlying filesystem. In case the
# filesystem is case sensitive (i.e. it supports files in the same directory
# whose names only differ in casing), the option must be set to YES to properly
@@ -608,7 +633,7 @@
# output files written for symbols that only differ in casing, such as for two
# classes, one named CLASS and the other named Class, and to also support
# references to files without having to specify the exact matching casing. On
-# Windows (including Cygwin) and MacOS, users should typically set this option
+# Windows (including Cygwin) and macOS, users should typically set this option
# to NO, whereas on Linux or other Unix flavors it should typically be set to
# YES.
# Possible values are: SYSTEM, NO and YES.
@@ -616,14 +641,14 @@
CASE_SENSE_NAMES = YES
-# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# If the HIDE_SCOPE_NAMES tag is set to NO then Doxygen will show members with
# their full class and namespace scopes in the documentation. If set to YES, the
# scope will be hidden.
# The default value is: NO.
HIDE_SCOPE_NAMES = NO
-# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then Doxygen will
# append additional text to a page's title, such as Class Reference. If set to
# YES the compound reference will be hidden.
# The default value is: NO.
@@ -636,7 +661,7 @@
SHOW_HEADERFILE = YES
-# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# If the SHOW_INCLUDE_FILES tag is set to YES then Doxygen will put a list of
# the files that are included by a file in the documentation of that file.
# The default value is: YES.
@@ -649,7 +674,7 @@
SHOW_GROUPED_MEMB_INC = YES
-# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen will list include
# files with double quotes in the documentation rather than with sharp brackets.
# The default value is: NO.
@@ -661,14 +686,14 @@
INLINE_INFO = YES
-# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# If the SORT_MEMBER_DOCS tag is set to YES then Doxygen will sort the
# (detailed) documentation of file and class members alphabetically by member
# name. If set to NO, the members will appear in declaration order.
# The default value is: YES.
SORT_MEMBER_DOCS = YES
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# If the SORT_BRIEF_DOCS tag is set to YES then Doxygen will sort the brief
# descriptions of file, namespace and class members alphabetically by member
# name. If set to NO, the members will appear in declaration order. Note that
# this will also influence the order of the classes in the class list.
@@ -676,7 +701,7 @@
SORT_BRIEF_DOCS = NO
-# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then Doxygen will sort the
# (brief and detailed) documentation of class members so that constructors and
# destructors are listed first. If set to NO the constructors will appear in the
# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
@@ -688,7 +713,7 @@
SORT_MEMBERS_CTORS_1ST = NO
-# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# If the SORT_GROUP_NAMES tag is set to YES then Doxygen will sort the hierarchy
# of group names into alphabetical order. If set to NO the group names will
# appear in their defined order.
# The default value is: NO.
@@ -705,11 +730,11 @@
SORT_BY_SCOPE_NAME = YES
-# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# If the STRICT_PROTO_MATCHING option is enabled and Doxygen fails to do proper
# type resolution of all parameters of a function it will reject a match between
# the prototype and the implementation of a member function even if there is
# only one candidate or it is obvious which candidate to choose by doing a
-# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# simple string match. By disabling STRICT_PROTO_MATCHING Doxygen will still
# accept a match between prototype and implementation in such cases.
# The default value is: NO.
@@ -779,25 +804,25 @@
SHOW_NAMESPACES = YES
# The FILE_VERSION_FILTER tag can be used to specify a program or script that
-# doxygen should invoke to get the current version for each file (typically from
+# Doxygen should invoke to get the current version for each file (typically from
# the version control system). Doxygen will invoke the program by executing (via
# popen()) the command command input-file, where command is the value of the
# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
-# by doxygen. Whatever the program writes to standard output is used as the file
+# by Doxygen. Whatever the program writes to standard output is used as the file
# version. For an example see the documentation.
FILE_VERSION_FILTER =
# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
-# by doxygen. The layout file controls the global structure of the generated
+# by Doxygen. The layout file controls the global structure of the generated
# output files in an output format independent way. To create the layout file
-# that represents doxygen's defaults, run doxygen with the -l option. You can
+# that represents Doxygen's defaults, run Doxygen with the -l option. You can
# optionally specify a file name after the option, if omitted DoxygenLayout.xml
# will be used as the name of the layout file. See also section "Changing the
# layout of pages" for information.
#
-# Note that if you run doxygen from a directory containing a file called
-# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# Note that if you run Doxygen from a directory containing a file called
+# DoxygenLayout.xml, Doxygen will parse it automatically even if the LAYOUT_FILE
# tag is left empty.
LAYOUT_FILE =
@@ -812,19 +837,35 @@
CITE_BIB_FILES =
+# The EXTERNAL_TOOL_PATH tag can be used to extend the search path (PATH
+# environment variable) so that external tools such as latex and gs can be
+# found.
+# Note: Directories specified with EXTERNAL_TOOL_PATH are added in front of the
+# path already specified by the PATH variable, and are added in the order
+# specified.
+# Note: This option is particularly useful for macOS version 14 (Sonoma) and
+# higher, when running Doxygen from Doxywizard, because in this case any user-
+# defined changes to the PATH are ignored. A typical example on macOS is to set
+# EXTERNAL_TOOL_PATH = /Library/TeX/texbin /usr/local/bin
+# together with the standard path, the full search path used by doxygen when
+# launching external tools will then become
+# PATH=/Library/TeX/texbin:/usr/local/bin:/usr/bin:/bin:/usr/sbin:/sbin
+
+EXTERNAL_TOOL_PATH =
+
#---------------------------------------------------------------------------
# Configuration options related to warning and progress messages
#---------------------------------------------------------------------------
# The QUIET tag can be used to turn on/off the messages that are generated to
-# standard output by doxygen. If QUIET is set to YES this implies that the
+# standard output by Doxygen. If QUIET is set to YES this implies that the
# messages are off.
# The default value is: NO.
QUIET = YES
# The WARNINGS tag can be used to turn on/off the warning messages that are
-# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# generated to standard error (stderr) by Doxygen. If WARNINGS is set to YES
# this implies that the warnings are on.
#
# Tip: Turn warnings on while writing the documentation.
@@ -832,14 +873,14 @@
WARNINGS = YES
-# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then Doxygen will generate
# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
# will automatically be disabled.
# The default value is: YES.
WARN_IF_UNDOCUMENTED = YES
-# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# If the WARN_IF_DOC_ERROR tag is set to YES, Doxygen will generate warnings for
# potential errors in the documentation, such as documenting some parameters in
# a documented function twice, or documenting parameters that don't exist or
# using markup commands wrongly.
@@ -847,8 +888,8 @@
WARN_IF_DOC_ERROR = YES
-# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete
-# function parameter documentation. If set to NO, doxygen will accept that some
+# If WARN_IF_INCOMPLETE_DOC is set to YES, Doxygen will warn about incomplete
+# function parameter documentation. If set to NO, Doxygen will accept that some
# parameters have no documentation without warning.
# The default value is: YES.
@@ -856,7 +897,7 @@
# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
# are documented, but have no documentation for their parameters or return
-# value. If set to NO, doxygen will only warn about wrong parameter
+# value. If set to NO, Doxygen will only warn about wrong parameter
# documentation, but not about the absence of documentation. If EXTRACT_ALL is
# set to YES then this flag will automatically be disabled. See also
# WARN_IF_INCOMPLETE_DOC
@@ -864,24 +905,31 @@
WARN_NO_PARAMDOC = NO
-# If WARN_IF_UNDOC_ENUM_VAL option is set to YES, doxygen will warn about
-# undocumented enumeration values. If set to NO, doxygen will accept
+# If WARN_IF_UNDOC_ENUM_VAL option is set to YES, Doxygen will warn about
+# undocumented enumeration values. If set to NO, Doxygen will accept
# undocumented enumeration values. If EXTRACT_ALL is set to YES then this flag
# will automatically be disabled.
# The default value is: NO.
WARN_IF_UNDOC_ENUM_VAL = NO
-# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# If the WARN_AS_ERROR tag is set to YES then Doxygen will immediately stop when
# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS
-# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but
-# at the end of the doxygen process doxygen will return with a non-zero status.
-# Possible values are: NO, YES and FAIL_ON_WARNINGS.
+# then Doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but
+# at the end of the Doxygen process Doxygen will return with a non-zero status.
+# If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS_PRINT then Doxygen behaves
+# like FAIL_ON_WARNINGS but in case no WARN_LOGFILE is defined Doxygen will not
+# write the warning messages in between other messages but write them at the end
+# of a run, in case a WARN_LOGFILE is defined the warning messages will be
+# besides being in the defined file also be shown at the end of a run, unless
+# the WARN_LOGFILE is defined as - i.e. standard output (stdout) in that case
+# the behavior will remain as with the setting FAIL_ON_WARNINGS.
+# Possible values are: NO, YES, FAIL_ON_WARNINGS and FAIL_ON_WARNINGS_PRINT.
# The default value is: NO.
WARN_AS_ERROR = NO
-# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# The WARN_FORMAT tag determines the format of the warning messages that Doxygen
# can produce. The string should contain the $file, $line, and $text tags, which
# will be replaced by the file and line number from which the warning originated
# and the warning text. Optionally the format may contain $version, which will
@@ -894,7 +942,7 @@
# In the $text part of the WARN_FORMAT command it is possible that a reference
# to a more specific place is given. To make it easier to jump to this place
-# (outside of doxygen) the user can define a custom "cut" / "paste" string.
+# (outside of Doxygen) the user can define a custom "cut" / "paste" string.
# Example:
# WARN_LINE_FORMAT = "'vi $file +$line'"
# See also: WARN_FORMAT
@@ -932,7 +980,7 @@
@ZEPHYR_BASE@/subsys/testsuite/ztest/include/
# This tag can be used to specify the character encoding of the source files
-# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# that Doxygen parses. Internally Doxygen uses the UTF-8 encoding. Doxygen uses
# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
# documentation (see:
# https://www.gnu.org/software/libiconv/) for the list of possible encodings.
@@ -942,12 +990,12 @@
INPUT_ENCODING = UTF-8
# This tag can be used to specify the character encoding of the source files
-# that doxygen parses The INPUT_FILE_ENCODING tag can be used to specify
+# that Doxygen parses The INPUT_FILE_ENCODING tag can be used to specify
# character encoding on a per file pattern basis. Doxygen will compare the file
# name with each pattern and apply the encoding instead of the default
# INPUT_ENCODING) if there is a match. The character encodings are a list of the
-# form: pattern=encoding (like *.php=ISO-8859-1). See cfg_input_encoding
-# "INPUT_ENCODING" for further information on supported encodings.
+# form: pattern=encoding (like *.php=ISO-8859-1).
+# See also: INPUT_ENCODING for further information on supported encodings.
INPUT_FILE_ENCODING =
@@ -957,17 +1005,17 @@
#
# Note that for custom extensions or not directly supported extensions you also
# need to set EXTENSION_MAPPING for the extension otherwise the files are not
-# read by doxygen.
+# read by Doxygen.
#
# Note the list of default checked file patterns might differ from the list of
# default file extension mappings.
#
-# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
-# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
-# *.hh, *.hxx, *.hpp, *.h++, *.l, *.cs, *.d, *.php, *.php4, *.php5, *.phtml,
-# *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C
-# comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd,
-# *.vhdl, *.ucf, *.qsf and *.ice.
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cxxm,
+# *.cpp, *.cppm, *.ccm, *.c++, *.c++m, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl,
+# *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp, *.h++, *.ixx, *.l, *.cs, *.d,
+# *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to
+# be provided as Doxygen C comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08,
+# *.f18, *.f, *.for, *.vhd, *.vhdl, *.ucf, *.qsf and *.ice.
FILE_PATTERNS = *.c \
*.h \
@@ -984,7 +1032,7 @@
# excluded from the INPUT source files. This way you can easily exclude a
# subdirectory from a directory tree whose root is specified with the INPUT tag.
#
-# Note that relative paths are relative to the directory from which doxygen is
+# Note that relative paths are relative to the directory from which Doxygen is
# run.
EXCLUDE = @ZEPHYR_BASE@/include/zephyr/portability/cmsis_os.h \
@@ -1011,9 +1059,6 @@
# output. The symbol name can be a fully qualified name, a word, or if the
# wildcard * is used, a substring. Examples: ANamespace, AClass,
# ANamespace::AClass, ANamespace::*Test
-#
-# Note that the wildcards are matched against the file with absolute path, so to
-# exclude all test directories use the pattern */test/*
EXCLUDE_SYMBOLS = _* \
*.__unnamed__ \
@@ -1046,7 +1091,7 @@
IMAGE_PATH =
-# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# The INPUT_FILTER tag can be used to specify a program that Doxygen should
# invoke to filter for each input file. Doxygen will invoke the filter program
# by executing (via popen()) the command:
#
@@ -1061,14 +1106,14 @@
# code is scanned, but not when the output code is generated. If lines are added
# or removed, the anchors will not be placed correctly.
#
-# Note that doxygen will use the data processed and written to standard output
+# Note that Doxygen will use the data processed and written to standard output
# for further processing, therefore nothing else, like debug statements or used
# commands (so in case of a Windows batch file always use @echo OFF), should be
# written to standard output.
#
# Note that for custom extensions or not directly supported extensions you also
# need to set EXTENSION_MAPPING for the extension otherwise the files are not
-# properly processed by doxygen.
+# properly processed by Doxygen.
INPUT_FILTER =
@@ -1081,7 +1126,7 @@
#
# Note that for custom extensions or not directly supported extensions you also
# need to set EXTENSION_MAPPING for the extension otherwise the files are not
-# properly processed by doxygen.
+# properly processed by Doxygen.
FILTER_PATTERNS =
@@ -1103,7 +1148,7 @@
# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
# is part of the input, its contents will be placed on the main page
# (index.html). This can be useful if you have a project on for instance GitHub
-# and want to reuse the introduction page also for the doxygen output.
+# and want to reuse the introduction page also for the Doxygen output.
USE_MDFILE_AS_MAINPAGE = @ZEPHYR_BASE@/doc/_doxygen/mainpage.md
@@ -1130,12 +1175,13 @@
SOURCE_BROWSER = NO
# Setting the INLINE_SOURCES tag to YES will include the body of functions,
-# classes and enums directly into the documentation.
+# multi-line macros, enums or list initialized variables directly into the
+# documentation.
# The default value is: NO.
INLINE_SOURCES = NO
-# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct Doxygen to hide any
# special comment blocks from generated source code fragments. Normal C, C++ and
# Fortran comments will always remain visible.
# The default value is: YES.
@@ -1173,7 +1219,7 @@
SOURCE_TOOLTIPS = YES
# If the USE_HTAGS tag is set to YES then the references to source code will
-# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# point to the HTML generated by the htags(1) tool instead of Doxygen built-in
# source browser. The htags tool is part of GNU's global source tagging system
# (see https://www.gnu.org/software/global/global.html). You will need version
# 4.8.6 or higher.
@@ -1187,14 +1233,14 @@
# Doxygen will invoke htags (and that will in turn invoke gtags), so these
# tools must be available from the command line (i.e. in the search path).
#
-# The result: instead of the source browser generated by doxygen, the links to
+# The result: instead of the source browser generated by Doxygen, the links to
# source code will now point to the output of htags.
# The default value is: NO.
# This tag requires that the tag SOURCE_BROWSER is set to YES.
USE_HTAGS = NO
-# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# If the VERBATIM_HEADERS tag is set the YES then Doxygen will generate a
# verbatim copy of the header file for each class for which an include is
# specified. Set to NO to disable this.
# See also: Section \class.
@@ -1202,19 +1248,19 @@
VERBATIM_HEADERS = YES
-# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# If the CLANG_ASSISTED_PARSING tag is set to YES then Doxygen will use the
# clang parser (see:
# http://clang.llvm.org/) for more accurate parsing at the cost of reduced
# performance. This can be particularly helpful with template rich C++ code for
-# which doxygen's built-in parser lacks the necessary type information.
-# Note: The availability of this option depends on whether or not doxygen was
+# which Doxygen's built-in parser lacks the necessary type information.
+# Note: The availability of this option depends on whether or not Doxygen was
# generated with the -Duse_libclang=ON option for CMake.
# The default value is: NO.
CLANG_ASSISTED_PARSING = NO
# If the CLANG_ASSISTED_PARSING tag is set to YES and the CLANG_ADD_INC_PATHS
-# tag is set to YES then doxygen will add the directory of each input to the
+# tag is set to YES then Doxygen will add the directory of each input to the
# include path.
# The default value is: YES.
# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
@@ -1223,7 +1269,7 @@
# If clang assisted parsing is enabled you can provide the compiler with command
# line options that you would normally use when invoking the compiler. Note that
-# the include paths will already be set by doxygen for the files and directories
+# the include paths will already be set by Doxygen for the files and directories
# specified with INPUT and INCLUDE_PATH.
# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
@@ -1237,7 +1283,7 @@
# specifying the -p option to a clang tool, such as clang-check. These options
# will then be passed to the parser. Any options specified with CLANG_OPTIONS
# will be added as well.
-# Note: The availability of this option depends on whether or not doxygen was
+# Note: The availability of this option depends on whether or not Doxygen was
# generated with the -Duse_libclang=ON option for CMake.
CLANG_DATABASE_PATH =
@@ -1266,7 +1312,7 @@
# Configuration options related to the HTML output
#---------------------------------------------------------------------------
-# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# If the GENERATE_HTML tag is set to YES, Doxygen will generate HTML output
# The default value is: YES.
GENERATE_HTML = YES
@@ -1287,40 +1333,40 @@
HTML_FILE_EXTENSION = .html
# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
-# each generated HTML page. If the tag is left blank doxygen will generate a
+# each generated HTML page. If the tag is left blank Doxygen will generate a
# standard header.
#
# To get valid HTML the header file that includes any scripts and style sheets
-# that doxygen needs, which is dependent on the configuration options used (e.g.
+# that Doxygen needs, which is dependent on the configuration options used (e.g.
# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
# default header using
# doxygen -w html new_header.html new_footer.html new_stylesheet.css
# YourConfigFile
# and then modify the file new_header.html. See also section "Doxygen usage"
-# for information on how to generate the default header that doxygen normally
+# for information on how to generate the default header that Doxygen normally
# uses.
# Note: The header is subject to change so you typically have to regenerate the
-# default header when upgrading to a newer version of doxygen. For a description
+# default header when upgrading to a newer version of Doxygen. For a description
# of the possible markers and block names see the documentation.
# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_HEADER = @ZEPHYR_BASE@/doc/_doxygen/header.html
# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
-# generated HTML page. If the tag is left blank doxygen will generate a standard
+# generated HTML page. If the tag is left blank Doxygen will generate a standard
# footer. See HTML_HEADER for more information on how to generate a default
# footer and what special commands can be used inside the footer. See also
# section "Doxygen usage" for information on how to generate the default footer
-# that doxygen normally uses.
+# that Doxygen normally uses.
# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_FOOTER = @ZEPHYR_BASE@/doc/_doxygen/footer.html
+HTML_FOOTER =
# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
# sheet that is used by each HTML page. It can be used to fine-tune the look of
-# the HTML output. If left blank doxygen will generate a default style sheet.
+# the HTML output. If left blank Doxygen will generate a default style sheet.
# See also section "Doxygen usage" for information on how to generate the style
-# sheet that doxygen normally uses.
+# sheet that Doxygen normally uses.
# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
# it is more robust and this tag (HTML_STYLESHEET) will in the future become
# obsolete.
@@ -1330,7 +1376,7 @@
# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# cascading style sheets that are included after the standard style sheets
-# created by doxygen. Using this option one can overrule certain style aspects.
+# created by Doxygen. Using this option one can overrule certain style aspects.
# This is preferred over using HTML_STYLESHEET since it does not replace the
# standard style sheet and is therefore more robust against future updates.
# Doxygen will copy the style sheet files to the output directory.
@@ -1362,11 +1408,11 @@
# The HTML_COLORSTYLE tag can be used to specify if the generated HTML output
# should be rendered with a dark or light theme.
-# Possible values are: LIGHT always generate light mode output, DARK always
-# generate dark mode output, AUTO_LIGHT automatically set the mode according to
-# the user preference, use light mode if no preference is set (the default),
-# AUTO_DARK automatically set the mode according to the user preference, use
-# dark mode if no preference is set and TOGGLE allow to user to switch between
+# Possible values are: LIGHT always generates light mode output, DARK always
+# generates dark mode output, AUTO_LIGHT automatically sets the mode according
+# to the user preference, uses light mode if no preference is set (the default),
+# AUTO_DARK automatically sets the mode according to the user preference, uses
+# dark mode if no preference is set and TOGGLE allows a user to switch between
# light and dark mode via a button.
# The default value is: AUTO_LIGHT.
# This tag requires that the tag GENERATE_HTML is set to YES.
@@ -1403,15 +1449,6 @@
HTML_COLORSTYLE_GAMMA = 80
-# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
-# page will contain the date and time when the page was generated. Setting this
-# to YES can help to show when doxygen was last run and thus if the
-# documentation is up to date.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_TIMESTAMP = YES
-
# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML
# documentation will contain a main index with vertical navigation menus that
# are dynamically created via JavaScript. If disabled, the navigation index will
@@ -1431,6 +1468,33 @@
HTML_DYNAMIC_SECTIONS = YES
+# If the HTML_CODE_FOLDING tag is set to YES then classes and functions can be
+# dynamically folded and expanded in the generated HTML source code.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_CODE_FOLDING = YES
+
+# If the HTML_COPY_CLIPBOARD tag is set to YES then Doxygen will show an icon in
+# the top right corner of code and text fragments that allows the user to copy
+# its content to the clipboard. Note this only works if supported by the browser
+# and the web page is served via a secure context (see:
+# https://www.w3.org/TR/secure-contexts/), i.e. using the https: or file:
+# protocol.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COPY_CLIPBOARD = YES
+
+# Doxygen stores a couple of settings persistently in the browser (via e.g.
+# cookies). By default these settings apply to all HTML pages generated by
+# Doxygen across all projects. The HTML_PROJECT_COOKIE tag can be used to store
+# the settings under a project specific key, such that the user preferences will
+# be stored separately.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_PROJECT_COOKIE =
+
# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
# shown in the various tree structured indices initially; the user can expand
# and collapse entries dynamically later on. Doxygen will expand the tree to
@@ -1448,7 +1512,7 @@
# generated that can be used as input for Apple's Xcode 3 integrated development
# environment (see:
# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To
-# create a documentation set, doxygen will generate a Makefile in the HTML
+# create a documentation set, Doxygen will generate a Makefile in the HTML
# output directory. Running make will produce the docset in that directory and
# running make install will install the docset in
# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
@@ -1496,7 +1560,7 @@
DOCSET_PUBLISHER_NAME = Publisher
-# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# If the GENERATE_HTMLHELP tag is set to YES then Doxygen generates three
# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
# on Windows. In the beginning of 2021 Microsoft took the original page, with
@@ -1507,7 +1571,7 @@
# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe).
#
# The HTML Help Workshop contains a compiler that can convert all HTML output
-# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# generated by Doxygen into a single compiled HTML file (.chm). Compiled HTML
# files are now used as the Windows 98 help format, and will replace the old
# Windows help format (.hlp) on all Windows platforms in the future. Compressed
# HTML files also contain an index, a table of contents, and you can search for
@@ -1527,7 +1591,7 @@
# The HHC_LOCATION tag can be used to specify the location (absolute path
# including file name) of the HTML help compiler (hhc.exe). If non-empty,
-# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# Doxygen will try to run the HTML help compiler on the generated index.hhp.
# The file has to be specified with full path.
# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
@@ -1561,6 +1625,16 @@
TOC_EXPAND = NO
+# The SITEMAP_URL tag is used to specify the full URL of the place where the
+# generated documentation will be placed on the server by the user during the
+# deployment of the documentation. The generated sitemap is called sitemap.xml
+# and placed on the directory specified by HTML_OUTPUT. In case no SITEMAP_URL
+# is specified no sitemap is generated. For information about the sitemap
+# protocol see https://www.sitemaps.org
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SITEMAP_URL =
+
# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
@@ -1619,7 +1693,7 @@
QHP_SECT_FILTER_ATTRS =
# The QHG_LOCATION tag can be used to specify the location (absolute path
-# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to
+# including file name) of Qt's qhelpgenerator. If non-empty Doxygen will try to
# run qhelpgenerator on the generated .qhp file.
# This tag requires that the tag GENERATE_QHP is set to YES.
@@ -1664,7 +1738,7 @@
# (i.e. any modern browser). Windows users are probably better off using the
# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
# further fine tune the look of the index (see "Fine-tuning the output"). As an
-# example, the default style sheet generated by doxygen has an example that
+# example, the default style sheet generated by Doxygen has an example that
# shows how to put an image at the root of the tree instead of the PROJECT_NAME.
# Since the tree basically has the same information as the tab index, you could
# consider setting DISABLE_INDEX to YES when enabling this option.
@@ -1686,7 +1760,7 @@
FULL_SIDEBAR = NO
# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
-# doxygen will group on one line in the generated HTML documentation.
+# Doxygen will group on one line in the generated HTML documentation.
#
# Note that a value of 0 will completely suppress the enum values from appearing
# in the overview section.
@@ -1695,6 +1769,12 @@
ENUM_VALUES_PER_LINE = 4
+# When the SHOW_ENUM_VALUES tag is set doxygen will show the specified
+# enumeration values besides the enumeration mnemonics.
+# The default value is: NO.
+
+SHOW_ENUM_VALUES = NO
+
# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
# to set the initial width (in pixels) of the frame in which the tree is shown.
# Minimum value: 0, maximum value: 1500, default value: 250.
@@ -1702,21 +1782,21 @@
TREEVIEW_WIDTH = 300
-# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# If the EXT_LINKS_IN_WINDOW option is set to YES, Doxygen will open links to
# external symbols imported via tag files in a separate window.
# The default value is: NO.
# This tag requires that the tag GENERATE_HTML is set to YES.
EXT_LINKS_IN_WINDOW = NO
-# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email
+# If the OBFUSCATE_EMAILS tag is set to YES, Doxygen will obfuscate email
# addresses.
# The default value is: YES.
# This tag requires that the tag GENERATE_HTML is set to YES.
OBFUSCATE_EMAILS = YES
-# If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg
+# If the HTML_FORMULA_FORMAT option is set to svg, Doxygen will use the pdf2svg
# tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see
# https://inkscape.org) to generate formulas as SVG images instead of PNGs for
# the HTML output. These images will generally look nicer at scaled resolutions.
@@ -1729,7 +1809,7 @@
# Use this tag to change the font size of LaTeX formulas included as images in
# the HTML documentation. When you change the font size after a successful
-# doxygen run you need to manually remove any form_*.png images from the HTML
+# Doxygen run you need to manually remove any form_*.png images from the HTML
# output directory to force them to be regenerated.
# Minimum value: 8, maximum value: 50, default value: 10.
# This tag requires that the tag GENERATE_HTML is set to YES.
@@ -1773,7 +1853,7 @@
# Possible values are: HTML-CSS (which is slower, but has the best
# compatibility. This is the name for Mathjax version 2, for MathJax version 3
# this will be translated into chtml), NativeMML (i.e. MathML. Only supported
-# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This
+# for MathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This
# is the name for Mathjax version 3, for MathJax version 2 this will be
# translated into HTML-CSS) and SVG.
# The default value is: HTML-CSS.
@@ -1797,8 +1877,8 @@
# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
# extension names that should be enabled during MathJax rendering. For example
-# for MathJax version 2 (see https://docs.mathjax.org/en/v2.7-latest/tex.html
-# #tex-and-latex-extensions):
+# for MathJax version 2 (see
+# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions):
# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
# For example for MathJax version 3 (see
# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html):
@@ -1807,7 +1887,7 @@
MATHJAX_EXTENSIONS =
-# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# The MATHJAX_CODEFILE tag can be used to specify a file with JavaScript pieces
# of code that will be used on startup of the MathJax code. See the MathJax site
# (see:
# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an
@@ -1816,12 +1896,12 @@
MATHJAX_CODEFILE =
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
-# the HTML output. The underlying search engine uses javascript and DHTML and
+# When the SEARCHENGINE tag is enabled Doxygen will generate a search box for
+# the HTML output. The underlying search engine uses JavaScript and DHTML and
# should work on any modern browser. Note that when using HTML help
# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
# there is already a search function so this one should typically be disabled.
-# For large projects the javascript based search engine can be slow, then
+# For large projects the JavaScript based search engine can be slow, then
# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
# search using the keyboard; to jump to the search box use <access key> + S
# (what the <access key> is depends on the OS and browser, but it is typically
@@ -1840,7 +1920,7 @@
# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
# implemented using a web server instead of a web client using JavaScript. There
# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
-# setting. When disabled, doxygen will generate a PHP script for searching and
+# setting. When disabled, Doxygen will generate a PHP script for searching and
# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
# and searching needs to be provided by external tools. See the section
# "External Indexing and Searching" for details.
@@ -1849,7 +1929,7 @@
SERVER_BASED_SEARCH = NO
-# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
+# When EXTERNAL_SEARCH tag is enabled Doxygen will no longer generate the PHP
# script for searching. Instead the search results are written to an XML file
# which needs to be processed by an external indexer. Doxygen will invoke an
# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
@@ -1894,7 +1974,7 @@
EXTERNAL_SEARCH_ID =
-# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through Doxygen
# projects other than the one defined by this configuration file, but that are
# all added to the same external search index. Each project needs to have a
# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
@@ -1908,7 +1988,7 @@
# Configuration options related to the LaTeX output
#---------------------------------------------------------------------------
-# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# If the GENERATE_LATEX tag is set to YES, Doxygen will generate LaTeX output.
# The default value is: YES.
GENERATE_LATEX = NO
@@ -1953,7 +2033,7 @@
LATEX_MAKEINDEX_CMD = makeindex
-# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# If the COMPACT_LATEX tag is set to YES, Doxygen generates more compact LaTeX
# documents. This may be useful for small projects and may help to save some
# trees in general.
# The default value is: NO.
@@ -1984,15 +2064,15 @@
# The LATEX_HEADER tag can be used to specify a user-defined LaTeX header for
# the generated LaTeX document. The header should contain everything until the
-# first chapter. If it is left blank doxygen will generate a standard header. It
+# first chapter. If it is left blank Doxygen will generate a standard header. It
# is highly recommended to start with a default header using
# doxygen -w latex new_header.tex new_footer.tex new_stylesheet.sty
# and then modify the file new_header.tex. See also section "Doxygen usage" for
-# information on how to generate the default header that doxygen normally uses.
+# information on how to generate the default header that Doxygen normally uses.
#
# Note: Only use a user-defined header if you know what you are doing!
# Note: The header is subject to change so you typically have to regenerate the
-# default header when upgrading to a newer version of doxygen. The following
+# default header when upgrading to a newer version of Doxygen. The following
# commands have a special meaning inside the header (and footer): For a
# description of the possible markers and block names see the documentation.
# This tag requires that the tag GENERATE_LATEX is set to YES.
@@ -2001,10 +2081,10 @@
# The LATEX_FOOTER tag can be used to specify a user-defined LaTeX footer for
# the generated LaTeX document. The footer should contain everything after the
-# last chapter. If it is left blank doxygen will generate a standard footer. See
+# last chapter. If it is left blank Doxygen will generate a standard footer. See
# LATEX_HEADER for more information on how to generate a default footer and what
# special commands can be used inside the footer. See also section "Doxygen
-# usage" for information on how to generate the default footer that doxygen
+# usage" for information on how to generate the default footer that Doxygen
# normally uses. Note: Only use a user-defined footer if you know what you are
# doing!
# This tag requires that the tag GENERATE_LATEX is set to YES.
@@ -2013,7 +2093,7 @@
# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# LaTeX style sheets that are included after the standard style sheets created
-# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# by Doxygen. Using this option one can overrule certain style aspects. Doxygen
# will copy the style sheet files to the output directory.
# Note: The order of the extra style sheet files is of importance (e.g. the last
# style sheet in the list overrules the setting of the previous ones in the
@@ -2039,7 +2119,7 @@
PDF_HYPERLINKS = YES
-# If the USE_PDFLATEX tag is set to YES, doxygen will use the engine as
+# If the USE_PDFLATEX tag is set to YES, Doxygen will use the engine as
# specified with LATEX_CMD_NAME to generate the PDF file directly from the LaTeX
# files. Set this option to YES, to get a higher quality PDF documentation.
#
@@ -2049,15 +2129,22 @@
USE_PDFLATEX = YES
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
-# command to the generated LaTeX files. This will instruct LaTeX to keep running
-# if errors occur, instead of asking the user for help.
+# The LATEX_BATCHMODE tag signals the behavior of LaTeX in case of an error.
+# Possible values are: NO same as ERROR_STOP, YES same as BATCH, BATCH In batch
+# mode nothing is printed on the terminal, errors are scrolled as if <return> is
+# hit at every error; missing files that TeX tries to input or request from
+# keyboard input (\read on a not open input stream) cause the job to abort,
+# NON_STOP In nonstop mode the diagnostic message will appear on the terminal,
+# but there is no possibility of user interaction just like in batch mode,
+# SCROLL In scroll mode, TeX will stop only for missing files to input or if
+# keyboard input is necessary and ERROR_STOP In errorstop mode, TeX will stop at
+# each error, asking for user intervention.
# The default value is: NO.
# This tag requires that the tag GENERATE_LATEX is set to YES.
LATEX_BATCHMODE = NO
-# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# If the LATEX_HIDE_INDICES tag is set to YES then Doxygen will not include the
# index chapters (such as File Index, Compound Index, etc.) in the output.
# The default value is: NO.
# This tag requires that the tag GENERATE_LATEX is set to YES.
@@ -2072,14 +2159,6 @@
LATEX_BIB_STYLE = plain
-# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated
-# page will contain the date and time when the page was generated. Setting this
-# to NO can help when comparing the output of multiple runs.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_TIMESTAMP = NO
-
# The LATEX_EMOJI_DIRECTORY tag is used to specify the (relative or absolute)
# path from which the emoji images will be read. If a relative path is entered,
# it will be relative to the LATEX_OUTPUT directory. If left blank the
@@ -2092,7 +2171,7 @@
# Configuration options related to the RTF output
#---------------------------------------------------------------------------
-# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# If the GENERATE_RTF tag is set to YES, Doxygen will generate RTF output. The
# RTF output is optimized for Word 97 and may not look too pretty with other RTF
# readers/editors.
# The default value is: NO.
@@ -2107,7 +2186,7 @@
RTF_OUTPUT = rtf
-# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# If the COMPACT_RTF tag is set to YES, Doxygen generates more compact RTF
# documents. This may be useful for small projects and may help to save some
# trees in general.
# The default value is: NO.
@@ -2127,28 +2206,36 @@
RTF_HYPERLINKS = YES
-# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# Load stylesheet definitions from file. Syntax is similar to Doxygen's
# configuration file, i.e. a series of assignments. You only have to provide
# replacements, missing definitions are set to their default value.
#
# See also section "Doxygen usage" for information on how to generate the
-# default style sheet that doxygen normally uses.
+# default style sheet that Doxygen normally uses.
# This tag requires that the tag GENERATE_RTF is set to YES.
RTF_STYLESHEET_FILE =
# Set optional variables used in the generation of an RTF document. Syntax is
-# similar to doxygen's configuration file. A template extensions file can be
+# similar to Doxygen's configuration file. A template extensions file can be
# generated using doxygen -e rtf extensionFile.
# This tag requires that the tag GENERATE_RTF is set to YES.
RTF_EXTENSIONS_FILE =
+# The RTF_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the RTF_OUTPUT output directory.
+# Note that the files will be copied as-is; there are no commands or markers
+# available.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_EXTRA_FILES =
+
#---------------------------------------------------------------------------
# Configuration options related to the man page output
#---------------------------------------------------------------------------
-# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# If the GENERATE_MAN tag is set to YES, Doxygen will generate man pages for
# classes and files.
# The default value is: NO.
@@ -2179,7 +2266,7 @@
MAN_SUBDIR =
-# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output, then it
# will generate one additional man file for each entity documented in the real
# man page(s). These additional files only source the real man page, but without
# them the man command would be unable to find the correct page.
@@ -2192,7 +2279,7 @@
# Configuration options related to the XML output
#---------------------------------------------------------------------------
-# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# If the GENERATE_XML tag is set to YES, Doxygen will generate an XML file that
# captures the structure of the code including all documentation.
# The default value is: NO.
@@ -2206,7 +2293,7 @@
XML_OUTPUT = xml
-# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program
+# If the XML_PROGRAMLISTING tag is set to YES, Doxygen will dump the program
# listings (including syntax highlighting and cross-referencing information) to
# the XML output. Note that enabling this will significantly increase the size
# of the XML output.
@@ -2215,7 +2302,7 @@
XML_PROGRAMLISTING = YES
-# If the XML_NS_MEMB_FILE_SCOPE tag is set to YES, doxygen will include
+# If the XML_NS_MEMB_FILE_SCOPE tag is set to YES, Doxygen will include
# namespace members in file scope as well, matching the HTML output.
# The default value is: NO.
# This tag requires that the tag GENERATE_XML is set to YES.
@@ -2226,7 +2313,7 @@
# Configuration options related to the DOCBOOK output
#---------------------------------------------------------------------------
-# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files
+# If the GENERATE_DOCBOOK tag is set to YES, Doxygen will generate Docbook files
# that can be used to generate PDF.
# The default value is: NO.
@@ -2244,8 +2331,8 @@
# Configuration options for the AutoGen Definitions output
#---------------------------------------------------------------------------
-# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an
-# AutoGen Definitions (see http://autogen.sourceforge.net/) file that captures
+# If the GENERATE_AUTOGEN_DEF tag is set to YES, Doxygen will generate an
+# AutoGen Definitions (see https://autogen.sourceforge.net/) file that captures
# the structure of the code including all documentation. Note that this feature
# is still experimental and incomplete at the moment.
# The default value is: NO.
@@ -2253,10 +2340,36 @@
GENERATE_AUTOGEN_DEF = NO
#---------------------------------------------------------------------------
+# Configuration options related to Sqlite3 output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_SQLITE3 tag is set to YES Doxygen will generate a Sqlite3
+# database with symbols found by Doxygen stored in tables.
+# The default value is: NO.
+
+GENERATE_SQLITE3 = NO
+
+# The SQLITE3_OUTPUT tag is used to specify where the Sqlite3 database will be
+# put. If a relative path is entered the value of OUTPUT_DIRECTORY will be put
+# in front of it.
+# The default directory is: sqlite3.
+# This tag requires that the tag GENERATE_SQLITE3 is set to YES.
+
+SQLITE3_OUTPUT = sqlite3
+
+# The SQLITE3_RECREATE_DB tag is set to YES, the existing doxygen_sqlite3.db
+# database file will be recreated with each Doxygen run. If set to NO, Doxygen
+# will warn if a database file is already found and not modify it.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_SQLITE3 is set to YES.
+
+SQLITE3_RECREATE_DB = YES
+
+#---------------------------------------------------------------------------
# Configuration options related to the Perl module output
#---------------------------------------------------------------------------
-# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module
+# If the GENERATE_PERLMOD tag is set to YES, Doxygen will generate a Perl module
# file that captures the structure of the code including all documentation.
#
# Note that this feature is still experimental and incomplete at the moment.
@@ -2264,7 +2377,7 @@
GENERATE_PERLMOD = NO
-# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary
+# If the PERLMOD_LATEX tag is set to YES, Doxygen will generate the necessary
# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
# output from the Perl module output.
# The default value is: NO.
@@ -2294,13 +2407,13 @@
# Configuration options related to the preprocessor
#---------------------------------------------------------------------------
-# If the ENABLE_PREPROCESSING tag is set to YES, doxygen will evaluate all
+# If the ENABLE_PREPROCESSING tag is set to YES, Doxygen will evaluate all
# C-preprocessor directives found in the sources and include files.
# The default value is: YES.
ENABLE_PREPROCESSING = YES
-# If the MACRO_EXPANSION tag is set to YES, doxygen will expand all macro names
+# If the MACRO_EXPANSION tag is set to YES, Doxygen will expand all macro names
# in the source code. If set to NO, only conditional compilation will be
# performed. Macro expansion can be done in a controlled way by setting
# EXPAND_ONLY_PREDEF to YES.
@@ -2395,10 +2508,10 @@
NET_MGMT_DEFINE_REQUEST_HANDLER(x)= \
DEVICE_DEFINE()= \
BUILD_ASSERT()= \
- XEN_GUEST_HANDLE_64(x)= \
+ XEN_GUEST_HANDLE_64(x)= \
_LINKER \
__deprecated= \
- __sparse_cache= \
+ __sparse_cache= \
__packed= \
__aligned(x)= \
__attribute_nonnull(...)= \
@@ -2422,7 +2535,7 @@
EXPAND_AS_DEFINED =
-# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
+# If the SKIP_FUNCTION_MACROS tag is set to YES then Doxygen's preprocessor will
# remove all references to function-like macros that are alone on a line, have
# an all uppercase name, and do not end with a semicolon. Such function macros
# are typically used for boiler-plate code, and will confuse the parser if not
@@ -2446,26 +2559,26 @@
# section "Linking to external documentation" for more information about the use
# of tag files.
# Note: Each tag file must have a unique name (where the name does NOT include
-# the path). If a tag file is not located in the directory in which doxygen is
+# the path). If a tag file is not located in the directory in which Doxygen is
# run, you must also specify the path to the tagfile here.
TAGFILES =
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
+# When a file name is specified after GENERATE_TAGFILE, Doxygen will create a
# tag file that is based on the input files it reads. See section "Linking to
# external documentation" for more information about the usage of tag files.
GENERATE_TAGFILE = @DOXY_OUT@/html/zephyr.tag
-# If the ALLEXTERNALS tag is set to YES, all external class will be listed in
-# the class index. If set to NO, only the inherited external classes will be
-# listed.
+# If the ALLEXTERNALS tag is set to YES, all external classes and namespaces
+# will be listed in the class and namespace index. If set to NO, only the
+# inherited external classes will be listed.
# The default value is: NO.
ALLEXTERNALS = NO
# If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed
-# in the modules index. If set to NO, only the current project's groups will be
+# in the topic index. If set to NO, only the current project's groups will be
# listed.
# The default value is: YES.
@@ -2479,33 +2592,26 @@
EXTERNAL_PAGES = YES
#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
+# Configuration options related to diagram generator tools
#---------------------------------------------------------------------------
-# You can include diagrams made with dia in doxygen documentation. Doxygen will
-# then run dia to produce the diagram and insert it in the documentation. The
-# DIA_PATH tag allows you to specify the directory where the dia binary resides.
-# If left empty dia is assumed to be found in the default search path.
-
-DIA_PATH =
-
# If set to YES the inheritance and collaboration graphs will hide inheritance
# and usage relations if the target is undocumented or is not a class.
# The default value is: YES.
HIDE_UNDOC_RELATIONS = YES
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# If you set the HAVE_DOT tag to YES then Doxygen will assume the dot tool is
# available from the path. This tool is part of Graphviz (see:
-# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
+# https://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
# Bell Labs. The other options in this section have no effect if this option is
# set to NO
# The default value is: NO.
HAVE_DOT = NO
-# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
-# to run in parallel. When set to 0 doxygen will base this on the number of
+# The DOT_NUM_THREADS specifies the number of dot invocations Doxygen is allowed
+# to run in parallel. When set to 0 Doxygen will base this on the number of
# processors available in the system. You can set it explicitly to a value
# larger than 0 to get control over the balance between CPU load and processing
# speed.
@@ -2516,7 +2622,7 @@
# DOT_COMMON_ATTR is common attributes for nodes, edges and labels of
# subgraphs. When you want a differently looking font in the dot files that
-# doxygen generates you can specify fontname, fontcolor and fontsize attributes.
+# Doxygen generates you can specify fontname, fontcolor and fontsize attributes.
# For details please see <a href=https://graphviz.org/doc/info/attrs.html>Node,
# Edge and Graph Attributes specification</a> You need to make sure dot is able
# to find the font, which can be done by putting it in a standard location or by
@@ -2550,35 +2656,47 @@
DOT_FONTPATH =
-# If the CLASS_GRAPH tag is set to YES (or GRAPH) then doxygen will generate a
-# graph for each documented class showing the direct and indirect inheritance
-# relations. In case HAVE_DOT is set as well dot will be used to draw the graph,
-# otherwise the built-in generator will be used. If the CLASS_GRAPH tag is set
-# to TEXT the direct and indirect inheritance relations will be shown as texts /
-# links.
-# Possible values are: NO, YES, TEXT and GRAPH.
+# If the CLASS_GRAPH tag is set to YES or GRAPH or BUILTIN then Doxygen will
+# generate a graph for each documented class showing the direct and indirect
+# inheritance relations. In case the CLASS_GRAPH tag is set to YES or GRAPH and
+# HAVE_DOT is enabled as well, then dot will be used to draw the graph. In case
+# the CLASS_GRAPH tag is set to YES and HAVE_DOT is disabled or if the
+# CLASS_GRAPH tag is set to BUILTIN, then the built-in generator will be used.
+# If the CLASS_GRAPH tag is set to TEXT the direct and indirect inheritance
+# relations will be shown as texts / links. Explicit enabling an inheritance
+# graph or choosing a different representation for an inheritance graph of a
+# specific class, can be accomplished by means of the command \inheritancegraph.
+# Disabling an inheritance graph can be accomplished by means of the command
+# \hideinheritancegraph.
+# Possible values are: NO, YES, TEXT, GRAPH and BUILTIN.
# The default value is: YES.
CLASS_GRAPH = TEXT
-# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# If the COLLABORATION_GRAPH tag is set to YES then Doxygen will generate a
# graph for each documented class showing the direct and indirect implementation
# dependencies (inheritance, containment, and class references variables) of the
-# class with other documented classes.
+# class with other documented classes. Explicit enabling a collaboration graph,
+# when COLLABORATION_GRAPH is set to NO, can be accomplished by means of the
+# command \collaborationgraph. Disabling a collaboration graph can be
+# accomplished by means of the command \hidecollaborationgraph.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
COLLABORATION_GRAPH = YES
-# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
-# groups, showing the direct groups dependencies. See also the chapter Grouping
-# in the manual.
+# If the GROUP_GRAPHS tag is set to YES then Doxygen will generate a graph for
+# groups, showing the direct groups dependencies. Explicit enabling a group
+# dependency graph, when GROUP_GRAPHS is set to NO, can be accomplished by means
+# of the command \groupgraph. Disabling a directory graph can be accomplished by
+# means of the command \hidegroupgraph. See also the chapter Grouping in the
+# manual.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
GROUP_GRAPHS = YES
-# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
+# If the UML_LOOK tag is set to YES, Doxygen will generate inheritance and
# collaboration diagrams in a style similar to the OMG's Unified Modeling
# Language.
# The default value is: NO.
@@ -2599,10 +2717,10 @@
UML_LIMIT_NUM_FIELDS = 10
-# If the DOT_UML_DETAILS tag is set to NO, doxygen will show attributes and
+# If the DOT_UML_DETAILS tag is set to NO, Doxygen will show attributes and
# methods without types and arguments in the UML graphs. If the DOT_UML_DETAILS
-# tag is set to YES, doxygen will add type and arguments for attributes and
-# methods in the UML graphs. If the DOT_UML_DETAILS tag is set to NONE, doxygen
+# tag is set to YES, Doxygen will add type and arguments for attributes and
+# methods in the UML graphs. If the DOT_UML_DETAILS tag is set to NONE, Doxygen
# will not generate fields with class member information in the UML graphs. The
# class diagrams will look similar to the default class diagrams but using UML
# notation for the relationships.
@@ -2614,8 +2732,8 @@
# The DOT_WRAP_THRESHOLD tag can be used to set the maximum number of characters
# to display on a single line. If the actual line length exceeds this threshold
-# significantly it will wrapped across multiple lines. Some heuristics are apply
-# to avoid ugly line breaks.
+# significantly it will be wrapped across multiple lines. Some heuristics are
+# applied to avoid ugly line breaks.
# Minimum value: 0, maximum value: 1000, default value: 17.
# This tag requires that the tag HAVE_DOT is set to YES.
@@ -2630,24 +2748,29 @@
TEMPLATE_RELATIONS = NO
# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
-# YES then doxygen will generate a graph for each documented file showing the
+# YES then Doxygen will generate a graph for each documented file showing the
# direct and indirect include dependencies of the file with other documented
-# files.
+# files. Explicit enabling an include graph, when INCLUDE_GRAPH is set to NO,
+# can be accomplished by means of the command \includegraph. Disabling an
+# include graph can be accomplished by means of the command \hideincludegraph.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
INCLUDE_GRAPH = YES
# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
-# set to YES then doxygen will generate a graph for each documented file showing
+# set to YES then Doxygen will generate a graph for each documented file showing
# the direct and indirect include dependencies of the file with other documented
-# files.
+# files. Explicit enabling an included by graph, when INCLUDED_BY_GRAPH is set
+# to NO, can be accomplished by means of the command \includedbygraph. Disabling
+# an included by graph can be accomplished by means of the command
+# \hideincludedbygraph.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
INCLUDED_BY_GRAPH = YES
-# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# If the CALL_GRAPH tag is set to YES then Doxygen will generate a call
# dependency graph for every global function or class method.
#
# Note that enabling this option will significantly increase the time of a run.
@@ -2659,7 +2782,7 @@
CALL_GRAPH = NO
-# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# If the CALLER_GRAPH tag is set to YES then Doxygen will generate a caller
# dependency graph for every global function or class method.
#
# Note that enabling this option will significantly increase the time of a run.
@@ -2671,17 +2794,20 @@
CALLER_GRAPH = NO
-# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical
+# If the GRAPHICAL_HIERARCHY tag is set to YES then Doxygen will graphical
# hierarchy of all classes instead of a textual one.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
GRAPHICAL_HIERARCHY = YES
-# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# If the DIRECTORY_GRAPH tag is set to YES then Doxygen will show the
# dependencies a directory has on other directories in a graphical way. The
# dependency relations are determined by the #include relations between the
-# files in the directories.
+# files in the directories. Explicit enabling a directory graph, when
+# DIRECTORY_GRAPH is set to NO, can be accomplished by means of the command
+# \directorygraph. Disabling a directory graph can be accomplished by means of
+# the command \hidedirectorygraph.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
@@ -2697,7 +2823,7 @@
# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
# generated by dot. For an explanation of the image formats see the section
# output formats in the documentation of the dot tool (Graphviz (see:
-# http://www.graphviz.org/)).
+# https://www.graphviz.org/)).
# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
# to make the SVG files visible in IE 9+ (other browsers do not have this
# requirement).
@@ -2734,11 +2860,12 @@
DOTFILE_DIRS =
-# The MSCFILE_DIRS tag can be used to specify one or more directories that
-# contain msc files that are included in the documentation (see the \mscfile
-# command).
+# You can include diagrams made with dia in Doxygen documentation. Doxygen will
+# then run dia to produce the diagram and insert it in the documentation. The
+# DIA_PATH tag allows you to specify the directory where the dia binary resides.
+# If left empty dia is assumed to be found in the default search path.
-MSCFILE_DIRS =
+DIA_PATH =
# The DIAFILE_DIRS tag can be used to specify one or more directories that
# contain dia files that are included in the documentation (see the \diafile
@@ -2746,7 +2873,7 @@
DIAFILE_DIRS =
-# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# When using PlantUML, the PLANTUML_JAR_PATH tag should be used to specify the
# path where java can find the plantuml.jar file or to the filename of jar file
# to be used. If left blank, it is assumed PlantUML is not used or called during
# a preprocessing step. Doxygen will generate a warning when it encounters a
@@ -2754,20 +2881,20 @@
PLANTUML_JAR_PATH =
-# When using plantuml, the PLANTUML_CFG_FILE tag can be used to specify a
-# configuration file for plantuml.
+# When using PlantUML, the PLANTUML_CFG_FILE tag can be used to specify a
+# configuration file for PlantUML.
PLANTUML_CFG_FILE =
-# When using plantuml, the specified paths are searched for files specified by
-# the !include statement in a plantuml block.
+# When using PlantUML, the specified paths are searched for files specified by
+# the !include statement in a PlantUML block.
PLANTUML_INCLUDE_PATH =
# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
# that will be shown in the graph. If the number of nodes in a graph becomes
-# larger than this value, doxygen will truncate the graph, which is visualized
-# by representing a node as a red box. Note that doxygen if the number of direct
+# larger than this value, Doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that if the number of direct
# children of the root node in a graph is already larger than
# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
@@ -2797,17 +2924,17 @@
DOT_MULTI_TARGETS = NO
-# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# If the GENERATE_LEGEND tag is set to YES Doxygen will generate a legend page
# explaining the meaning of the various boxes and arrows in the dot generated
# graphs.
-# Note: This tag requires that UML_LOOK isn't set, i.e. the doxygen internal
+# Note: This tag requires that UML_LOOK isn't set, i.e. the Doxygen internal
# graphical representation for inheritance and collaboration diagrams is used.
# The default value is: YES.
# This tag requires that the tag HAVE_DOT is set to YES.
GENERATE_LEGEND = YES
-# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate
+# If the DOT_CLEANUP tag is set to YES, Doxygen will remove the intermediate
# files that are used to generate the various graphs.
#
# Note: This setting is not only used for dot files but also for msc temporary
@@ -2816,4 +2943,20 @@
DOT_CLEANUP = YES
+# You can define message sequence charts within Doxygen comments using the \msc
+# command. If the MSCGEN_TOOL tag is left empty (the default), then Doxygen will
+# use a built-in version of mscgen tool to produce the charts. Alternatively,
+# the MSCGEN_TOOL tag can also specify the name an external tool. For instance,
+# specifying prog as the value, Doxygen will call the tool as prog -T
+# <outfile_format> -o <outputfile> <inputfile>. The external tool should support
+# output file formats "png", "eps", "svg", and "ismap".
+
+MSCGEN_TOOL =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
+
+MSCFILE_DIRS =
+
@INCLUDE_CUSTOM_FILE@
diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt
index a0c7d2c..0f645e9 100644
--- a/drivers/CMakeLists.txt
+++ b/drivers/CMakeLists.txt
@@ -7,6 +7,7 @@
# zephyr-keep-sorted-start
add_subdirectory(disk)
+add_subdirectory(firmware)
add_subdirectory(interrupt_controller)
add_subdirectory(misc)
add_subdirectory(pcie)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index cfa8d08..a11ede6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -30,6 +30,7 @@
source "drivers/entropy/Kconfig"
source "drivers/espi/Kconfig"
source "drivers/ethernet/Kconfig"
+source "drivers/firmware/Kconfig"
source "drivers/flash/Kconfig"
source "drivers/fpga/Kconfig"
source "drivers/fuel_gauge/Kconfig"
diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt
index cd4006b..f5750ee 100644
--- a/drivers/adc/CMakeLists.txt
+++ b/drivers/adc/CMakeLists.txt
@@ -51,3 +51,5 @@
zephyr_library_sources_ifdef(CONFIG_ADC_NUMAKER adc_numaker.c)
zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU adc_mcux_gau_adc.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA adc_renesas_ra.c)
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index 1f13203..83f033c 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -128,4 +128,8 @@
source "drivers/adc/Kconfig.ene"
+source "drivers/adc/Kconfig.ambiq"
+
+source "drivers/adc/Kconfig.renesas_ra"
+
endif # ADC
diff --git a/drivers/adc/Kconfig.ambiq b/drivers/adc/Kconfig.ambiq
new file mode 100644
index 0000000..8b0e59a
--- /dev/null
+++ b/drivers/adc/Kconfig.ambiq
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+config ADC_AMBIQ
+ bool "Ambiq Adc Driver"
+ default y
+ depends on DT_HAS_AMBIQ_ADC_ENABLED
+ select AMBIQ_HAL
+ select AMBIQ_HAL_USE_ADC
+ help
+ Enables the Adc driver for Ambiq devices.
diff --git a/drivers/adc/Kconfig.renesas_ra b/drivers/adc/Kconfig.renesas_ra
new file mode 100644
index 0000000..1027788
--- /dev/null
+++ b/drivers/adc/Kconfig.renesas_ra
@@ -0,0 +1,12 @@
+# Renesas RA Family
+
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_RENESAS_RA
+ bool "Renesas RA ADC"
+ default y
+ depends on DT_HAS_RENESAS_RA_ADC_ENABLED
+ select USE_RA_FSP_ADC
+ help
+ Enable Renesas RA ADC Driver.
diff --git a/drivers/adc/adc_ambiq.c b/drivers/adc/adc_ambiq.c
new file mode 100644
index 0000000..d7af6ad
--- /dev/null
+++ b/drivers/adc/adc_ambiq.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ambiq_adc
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
+#include <zephyr/kernel.h>
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+/* ambiq-sdk includes */
+#include <am_mcu_apollo.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(adc_ambiq, CONFIG_ADC_LOG_LEVEL);
+
+typedef int (*ambiq_adc_pwr_func_t)(void);
+#define PWRCTRL_MAX_WAIT_US 5
+/* Number of slots available. */
+#define AMBIQ_ADC_SLOT_BUMBER AM_HAL_ADC_MAX_SLOTS
+
+struct adc_ambiq_config {
+ uint32_t base;
+ int size;
+ uint8_t num_channels;
+ void (*irq_config_func)(void);
+ const struct pinctrl_dev_config *pin_cfg;
+ ambiq_adc_pwr_func_t pwr_func;
+};
+
+struct adc_ambiq_data {
+ struct adc_context ctx;
+ void *adcHandle;
+ uint16_t *buffer;
+ uint16_t *repeat_buffer;
+ uint8_t active_channels;
+};
+
+static int adc_ambiq_set_resolution(am_hal_adc_slot_prec_e *prec, uint8_t adc_resolution)
+{
+ switch (adc_resolution) {
+ case 8:
+ *prec = AM_HAL_ADC_SLOT_8BIT;
+ break;
+ case 10:
+ *prec = AM_HAL_ADC_SLOT_10BIT;
+ break;
+ case 12:
+ *prec = AM_HAL_ADC_SLOT_12BIT;
+ break;
+ case 14:
+ *prec = AM_HAL_ADC_SLOT_14BIT;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+static int adc_ambiq_slot_config(const struct device *dev, const struct adc_sequence *sequence,
+ am_hal_adc_slot_chan_e channel, uint32_t ui32SlotNumber)
+{
+ struct adc_ambiq_data *data = dev->data;
+ am_hal_adc_slot_config_t ADCSlotConfig;
+
+ if (adc_ambiq_set_resolution(&ADCSlotConfig.ePrecisionMode, sequence->resolution) != 0) {
+ LOG_ERR("unsupported resolution %d", sequence->resolution);
+ return -ENOTSUP;
+ }
+
+ /* Set up an ADC slot */
+ ADCSlotConfig.eMeasToAvg = AM_HAL_ADC_SLOT_AVG_1;
+ ADCSlotConfig.eChannel = channel;
+ ADCSlotConfig.bWindowCompare = false;
+ ADCSlotConfig.bEnabled = true;
+ if (AM_HAL_STATUS_SUCCESS !=
+ am_hal_adc_configure_slot(data->adcHandle, ui32SlotNumber, &ADCSlotConfig)) {
+ LOG_ERR("configuring ADC Slot 0 failed.\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void adc_ambiq_isr(const struct device *dev)
+{
+ struct adc_ambiq_data *data = dev->data;
+ uint32_t ui32IntMask;
+ uint32_t ui32NumSamples;
+ am_hal_adc_sample_t Sample;
+
+ /* Read the interrupt status. */
+ am_hal_adc_interrupt_status(data->adcHandle, &ui32IntMask, true);
+ /* Clear the ADC interrupt.*/
+ am_hal_adc_interrupt_clear(data->adcHandle, ui32IntMask);
+
+ /*
+ * If we got a conversion completion interrupt (which should be our only
+ * ADC interrupt), go ahead and read the data.
+ */
+ if (ui32IntMask & AM_HAL_ADC_INT_CNVCMP) {
+ for (uint32_t i = 0; i < data->active_channels; i++) {
+ /* Read the value from the FIFO. */
+ ui32NumSamples = 1;
+ am_hal_adc_samples_read(data->adcHandle, false, NULL, &ui32NumSamples,
+ &Sample);
+ *data->buffer++ = Sample.ui32Sample;
+ }
+ adc_context_on_sampling_done(&data->ctx, dev);
+ }
+}
+
+static int adc_ambiq_check_buffer_size(const struct adc_sequence *sequence, uint8_t active_channels)
+{
+ size_t needed_buffer_size;
+
+ needed_buffer_size = active_channels * sizeof(uint16_t);
+
+ if (sequence->options) {
+ needed_buffer_size *= (1 + sequence->options->extra_samplings);
+ }
+
+ if (sequence->buffer_size < needed_buffer_size) {
+ LOG_DBG("Provided buffer is too small (%u/%u)", sequence->buffer_size,
+ needed_buffer_size);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int adc_ambiq_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+ struct adc_ambiq_data *data = dev->data;
+ const struct adc_ambiq_config *cfg = dev->config;
+ uint8_t channel_id = 0;
+ uint32_t channels = 0;
+ uint8_t active_channels = 0;
+ uint8_t slot_index;
+
+ int error = 0;
+
+ if (sequence->channels & ~BIT_MASK(cfg->num_channels)) {
+ LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
+ return -EINVAL;
+ }
+
+ if (sequence->channels == 0UL) {
+ LOG_ERR("No channel selected");
+ return -EINVAL;
+ }
+ active_channels = POPCOUNT(sequence->channels);
+ if (active_channels > AMBIQ_ADC_SLOT_BUMBER) {
+ LOG_ERR("Too many channels for sequencer. Max: %d", AMBIQ_ADC_SLOT_BUMBER);
+ return -ENOTSUP;
+ }
+
+ channels = sequence->channels;
+ for (slot_index = 0; slot_index < active_channels; slot_index++) {
+ channel_id = find_lsb_set(channels) - 1;
+ error = adc_ambiq_slot_config(dev, sequence, channel_id, slot_index);
+ if (error < 0) {
+ return error;
+ }
+ channels &= ~BIT(channel_id);
+ }
+ __ASSERT_NO_MSG(channels == 0);
+
+ /* Enable the ADC. */
+ am_hal_adc_enable(data->adcHandle);
+
+ error = adc_ambiq_check_buffer_size(sequence, active_channels);
+ if (error < 0) {
+ return error;
+ }
+ data->active_channels = active_channels;
+ data->buffer = sequence->buffer;
+ /* Start ADC conversion */
+ adc_context_start_read(&data->ctx, sequence);
+ error = adc_context_wait_for_completion(&data->ctx);
+
+ return error;
+}
+
+static int adc_ambiq_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+ struct adc_ambiq_data *data = dev->data;
+ int error;
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+ error = pm_device_runtime_get(dev);
+ if (error < 0) {
+ LOG_ERR("pm_device_runtime_get failed: %d", error);
+ }
+#endif
+
+ adc_context_lock(&data->ctx, false, NULL);
+ error = adc_ambiq_start_read(dev, sequence);
+ adc_context_release(&data->ctx, error);
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+ error = pm_device_runtime_put(dev);
+ if (error < 0) {
+ LOG_ERR("pm_device_runtime_put failed: %d", error);
+ }
+#endif
+ return error;
+}
+
+static int adc_ambiq_channel_setup(const struct device *dev, const struct adc_channel_cfg *chan_cfg)
+{
+ const struct adc_ambiq_config *cfg = dev->config;
+
+ if (chan_cfg->channel_id >= cfg->num_channels) {
+ LOG_ERR("unsupported channel id '%d'", chan_cfg->channel_id);
+ return -ENOTSUP;
+ }
+
+ if (chan_cfg->gain != ADC_GAIN_1) {
+ LOG_ERR("Gain is not valid");
+ return -ENOTSUP;
+ }
+
+ if (chan_cfg->reference != ADC_REF_INTERNAL) {
+ LOG_ERR("Reference is not valid");
+ return -ENOTSUP;
+ }
+
+ if (chan_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+ LOG_ERR("unsupported acquisition_time '%d'", chan_cfg->acquisition_time);
+ return -ENOTSUP;
+ }
+
+ if (chan_cfg->differential) {
+ LOG_ERR("Differential sampling not supported");
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+ struct adc_ambiq_data *data = CONTAINER_OF(ctx, struct adc_ambiq_data, ctx);
+
+ if (repeat_sampling) {
+ data->buffer = data->repeat_buffer;
+ }
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+ struct adc_ambiq_data *data = CONTAINER_OF(ctx, struct adc_ambiq_data, ctx);
+
+ data->repeat_buffer = data->buffer;
+ /*Trigger the ADC*/
+ am_hal_adc_sw_trigger(data->adcHandle);
+}
+
+static int adc_ambiq_init(const struct device *dev)
+{
+ struct adc_ambiq_data *data = dev->data;
+ const struct adc_ambiq_config *cfg = dev->config;
+ am_hal_adc_config_t ADCConfig;
+
+ int ret;
+
+ /* Initialize the ADC and get the handle*/
+ if (AM_HAL_STATUS_SUCCESS !=
+ am_hal_adc_initialize((cfg->base - REG_ADC_BASEADDR) / (cfg->size * 4),
+ &data->adcHandle)) {
+ ret = -ENODEV;
+ LOG_ERR("Faile to initialize ADC, code:%d", ret);
+ return ret;
+ }
+
+ /* power on ADC*/
+ ret = cfg->pwr_func();
+
+ /* Set up the ADC configuration parameters. These settings are reasonable
+ * for accurate measurements at a low sample rate.
+ */
+ ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC;
+ ADCConfig.ePolarity = AM_HAL_ADC_TRIGPOL_RISING;
+ ADCConfig.eTrigger = AM_HAL_ADC_TRIGSEL_SOFTWARE;
+ ADCConfig.eReference = AM_HAL_ADC_REFSEL_INT_1P5;
+ ADCConfig.eClockMode = AM_HAL_ADC_CLKMODE_LOW_POWER;
+ ADCConfig.ePowerMode = AM_HAL_ADC_LPMODE0;
+ ADCConfig.eRepeat = AM_HAL_ADC_SINGLE_SCAN;
+ if (AM_HAL_STATUS_SUCCESS != am_hal_adc_configure(data->adcHandle, &ADCConfig)) {
+ ret = -ENODEV;
+ LOG_ERR("Configuring ADC failed, code:%d", ret);
+ return ret;
+ }
+
+ ret = pinctrl_apply_state(cfg->pin_cfg, PINCTRL_STATE_DEFAULT);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* Enable the ADC interrupts in the ADC. */
+ cfg->irq_config_func();
+ am_hal_adc_interrupt_enable(data->adcHandle, AM_HAL_ADC_INT_CNVCMP);
+
+ adc_context_unlock_unconditionally(&data->ctx);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_DEVICE
+static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
+{
+ struct adc_ambiq_data *data = dev->data;
+ uint32_t ret;
+ am_hal_sysctrl_power_state_e status;
+
+ switch (action) {
+ case PM_DEVICE_ACTION_RESUME:
+ status = AM_HAL_SYSCTRL_WAKE;
+ break;
+ case PM_DEVICE_ACTION_SUSPEND:
+ status = AM_HAL_SYSCTRL_DEEPSLEEP;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ ret = am_hal_adc_power_control(data->adcHandle, status, true);
+
+ if (ret != AM_HAL_STATUS_SUCCESS) {
+ return -EPERM;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_PM_DEVICE */
+
+#define ADC_AMBIQ_DRIVER_API(n) \
+ static const struct adc_driver_api adc_ambiq_driver_api_##n = { \
+ .channel_setup = adc_ambiq_channel_setup, \
+ .read = adc_ambiq_read, \
+ .ref_internal = DT_INST_PROP(n, internal_vref_mv), \
+ };
+
+#define ADC_AMBIQ_INIT(n) \
+ PINCTRL_DT_INST_DEFINE(n); \
+ ADC_AMBIQ_DRIVER_API(n); \
+ static int pwr_on_ambiq_adc_##n(void) \
+ { \
+ uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
+ DT_INST_PHA(n, ambiq_pwrcfg, offset); \
+ sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
+ k_busy_wait(PWRCTRL_MAX_WAIT_US); \
+ return 0; \
+ } \
+ static void adc_irq_config_func_##n(void) \
+ { \
+ IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), adc_ambiq_isr, \
+ DEVICE_DT_INST_GET(n), 0); \
+ irq_enable(DT_INST_IRQN(n)); \
+ }; \
+ static struct adc_ambiq_data adc_ambiq_data_##n = { \
+ ADC_CONTEXT_INIT_TIMER(adc_ambiq_data_##n, ctx), \
+ ADC_CONTEXT_INIT_LOCK(adc_ambiq_data_##n, ctx), \
+ ADC_CONTEXT_INIT_SYNC(adc_ambiq_data_##n, ctx), \
+ }; \
+ const static struct adc_ambiq_config adc_ambiq_config_##n = { \
+ .base = DT_INST_REG_ADDR(n), \
+ .size = DT_INST_REG_SIZE(n), \
+ .num_channels = DT_PROP(DT_DRV_INST(n), channel_count), \
+ .irq_config_func = adc_irq_config_func_##n, \
+ .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
+ .pwr_func = pwr_on_ambiq_adc_##n, \
+ }; \
+ PM_DEVICE_DT_INST_DEFINE(n, adc_ambiq_pm_action); \
+ DEVICE_DT_INST_DEFINE(n, &adc_ambiq_init, PM_DEVICE_DT_INST_GET(n), \
+ &adc_ambiq_data_##n, \
+ &adc_ambiq_config_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
+ &adc_ambiq_driver_api_##n);
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_AMBIQ_INIT)
diff --git a/drivers/adc/adc_nrfx_saadc.c b/drivers/adc/adc_nrfx_saadc.c
index ac4c87b..23ddbc2 100644
--- a/drivers/adc/adc_nrfx_saadc.c
+++ b/drivers/adc/adc_nrfx_saadc.c
@@ -19,7 +19,7 @@
#if (NRF_SAADC_HAS_AIN_AS_PIN)
-#if defined(CONFIG_SOC_NRF54H20)
+#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1),
@@ -62,9 +62,9 @@
"Definitions from nrf-adc.h do not match those from nrf_saadc.h");
#endif
-#ifdef CONFIG_SOC_NRF54H20
+#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
-/* nRF54H20 always uses bounce buffers in RAM */
+/* nRF54H20 and nRF9280 always use bounce buffers in RAM */
#define SAADC_MEMORY_SECTION \
COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(adc), memory_regions), \
@@ -76,7 +76,7 @@
#define ADC_BUFFER_IN_RAM
-#endif /* CONFIG_SOC_NRF54H20 */
+#endif /* defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) */
struct driver_data {
struct adc_context ctx;
@@ -663,7 +663,7 @@
#endif
#if defined(CONFIG_SOC_NRF54L15)
.ref_internal = 900,
-#elif defined(CONFIG_SOC_NRF54H20)
+#elif defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
.ref_internal = 1024,
#else
.ref_internal = 600,
diff --git a/drivers/adc/adc_renesas_ra.c b/drivers/adc/adc_renesas_ra.c
new file mode 100644
index 0000000..0174aaa
--- /dev/null
+++ b/drivers/adc/adc_renesas_ra.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_adc
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/logging/log.h>
+#include <instances/r_adc.h>
+
+#include <zephyr/irq.h>
+
+LOG_MODULE_REGISTER(adc_ra, CONFIG_ADC_LOG_LEVEL);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#define ADC_RA_MAX_RESOLUTION 12
+
+void adc_scan_end_isr(void);
+
+/**
+ * @brief RA ADC config
+ *
+ * This structure contains constant data for given instance of RA ADC.
+ */
+struct adc_ra_config {
+ /** Number of supported channels */
+ uint8_t num_channels;
+ /** pinctrl configs */
+ const struct pinctrl_dev_config *pcfg;
+ /** function pointer to irq setup */
+ void (*irq_configure)(void);
+};
+
+/**
+ * @brief RA ADC data
+ *
+ * This structure contains data structures used by a RA ADC.
+ */
+struct adc_ra_data {
+ /** Structure that handle state of ongoing read operation */
+ struct adc_context ctx;
+ /** Pointer to RA ADC own device structure */
+ const struct device *dev;
+ /** Structure that handle fsp ADC */
+ adc_instance_ctrl_t adc;
+ /** Structure that handle fsp ADC config */
+ struct st_adc_cfg f_config;
+ /** Structure that handle fsp ADC channel config */
+ adc_channel_cfg_t f_channel_cfg;
+ /** Pointer to memory where next sample will be written */
+ uint16_t *buf;
+ /** Mask with channels that will be sampled */
+ uint32_t channels;
+ /** Buffer id */
+ uint16_t buf_id;
+};
+
+/**
+ * @brief Setup channels before starting to scan ADC
+ *
+ * @param dev RA ADC device
+ * @param channel_cfg channel configuration
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if channel id or differential is wrong value
+ * @return -EINVAL if channel configuration is invalid
+ */
+static int adc_ra_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg)
+{
+ fsp_err_t fsp_err = FSP_SUCCESS;
+ struct adc_ra_data *data = dev->data;
+
+ if (!((channel_cfg->channel_id >= 0 && channel_cfg->channel_id <= 2) ||
+ (channel_cfg->channel_id >= 4 && channel_cfg->channel_id <= 8) ||
+ (channel_cfg->channel_id >= 16 && channel_cfg->channel_id <= 19))) {
+ LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
+ return -ENOTSUP;
+ }
+
+ if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+ LOG_ERR("Acquisition time is not valid");
+ return -EINVAL;
+ }
+
+ if (channel_cfg->differential) {
+ LOG_ERR("unsupported differential mode");
+ return -ENOTSUP;
+ }
+
+ if (channel_cfg->gain != ADC_GAIN_1) {
+ LOG_ERR("Gain is not valid");
+ return -EINVAL;
+ }
+
+ data->f_channel_cfg.scan_mask |= (1U << channel_cfg->channel_id);
+ /* Configure ADC channel specific settings */
+ fsp_err = R_ADC_ScanCfg(&data->adc, &data->f_channel_cfg);
+ if (FSP_SUCCESS != fsp_err) {
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+/**
+ * Interrupt handler
+ */
+static void adc_ra_isr(const struct device *dev)
+{
+ struct adc_ra_data *data = dev->data;
+ fsp_err_t fsp_err = FSP_SUCCESS;
+ adc_channel_t channel_id = 0;
+ uint32_t channels = 0;
+ int16_t *sample_buffer = (int16_t *)data->buf;
+
+ channels = data->channels;
+ for (channel_id = 0; channels > 0; channel_id++) {
+ /* Check if it is right channel id */
+ if ((channels & 0x01) != 0) {
+ fsp_err = R_ADC_Read(&data->adc, channel_id, &sample_buffer[data->buf_id]);
+ if (FSP_SUCCESS != fsp_err) {
+ break;
+ }
+ data->buf_id = data->buf_id + 1;
+ }
+
+ channels = channels >> 1;
+ }
+ adc_scan_end_isr();
+ adc_context_on_sampling_done(&data->ctx, dev);
+}
+
+/**
+ * @brief Check if buffer in @p sequence is big enough to hold all ADC samples
+ *
+ * @param dev RA ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOMEM if buffer is not big enough
+ */
+static int adc_ra_check_buffer_size(const struct device *dev, const struct adc_sequence *sequence)
+{
+ const struct adc_ra_config *config = dev->config;
+ uint8_t channels = 0;
+ size_t needed;
+ uint32_t mask;
+
+ for (mask = BIT(config->num_channels - 1); mask != 0; mask >>= 1) {
+ if (mask & sequence->channels) {
+ channels++;
+ }
+ }
+
+ needed = channels * sizeof(uint16_t);
+ if (sequence->options) {
+ needed *= (1 + sequence->options->extra_samplings);
+ }
+
+ if (sequence->buffer_size < needed) {
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Start processing read request
+ *
+ * @param dev RA ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ * range
+ * @return -ENOMEM if buffer is not big enough
+ * (see @ref adc_ra_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_ra_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+ const struct adc_ra_config *config = dev->config;
+ struct adc_ra_data *data = dev->data;
+ int err;
+
+ if (sequence->resolution > ADC_RA_MAX_RESOLUTION || sequence->resolution == 0) {
+ LOG_ERR("unsupported resolution %d", sequence->resolution);
+ return -ENOTSUP;
+ }
+
+ if (find_msb_set(sequence->channels) > config->num_channels) {
+ LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
+ return -ENOTSUP;
+ }
+
+ err = adc_ra_check_buffer_size(dev, sequence);
+ if (err) {
+ LOG_ERR("buffer size too small");
+ return err;
+ }
+
+ data->buf_id = 0;
+ data->buf = sequence->buffer;
+ adc_context_start_read(&data->ctx, sequence);
+
+ adc_context_wait_for_completion(&data->ctx);
+
+ return 0;
+}
+
+/**
+ * @brief Start processing read request asynchronously
+ *
+ * @param dev RA ADC device
+ * @param sequence ADC sequence description
+ * @param async async pointer to asynchronous signal
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ * range
+ * @return -ENOMEM if buffer is not big enough
+ * (see @ref adc_ra_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_ra_read_async(const struct device *dev, const struct adc_sequence *sequence,
+ struct k_poll_signal *async)
+{
+ struct adc_ra_data *data = dev->data;
+ int err;
+
+ adc_context_lock(&data->ctx, async ? true : false, async);
+ err = adc_ra_start_read(dev, sequence);
+ adc_context_release(&data->ctx, err);
+
+ return err;
+}
+
+/**
+ * @brief Start processing read request synchronously
+ *
+ * @param dev RA ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ * range
+ * @return -ENOMEM if buffer is not big enough
+ * (see @ref adc_ra_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_ra_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+ return adc_ra_read_async(dev, sequence, NULL);
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+ struct adc_ra_data *data = CONTAINER_OF(ctx, struct adc_ra_data, ctx);
+
+ data->channels = ctx->sequence.channels;
+
+ R_ADC_ScanStart(&data->adc);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+ struct adc_ra_data *data = CONTAINER_OF(ctx, struct adc_ra_data, ctx);
+
+ if (repeat_sampling) {
+ data->buf_id = 0;
+ }
+}
+
+/**
+ * @brief Function called on init for each RA ADC device. It setups all
+ * channels to return constant 0 mV and create acquisition thread.
+ *
+ * @param dev RA ADC device
+ *
+ * @return -EIO if error
+ *
+ * @return 0 on success
+ */
+static int adc_ra_init(const struct device *dev)
+{
+ const struct adc_ra_config *config = dev->config;
+ struct adc_ra_data *data = dev->data;
+ int ret;
+ fsp_err_t fsp_err = FSP_SUCCESS;
+
+ ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* Open ADC module */
+ fsp_err = R_ADC_Open(&data->adc, &data->f_config);
+ if (FSP_SUCCESS != fsp_err) {
+ return -EIO;
+ }
+
+ config->irq_configure();
+
+ adc_context_unlock_unconditionally(&data->ctx);
+ return 0;
+}
+
+const adc_extended_cfg_t g_adc_cfg_extend = {
+ .add_average_count = ADC_ADD_OFF,
+ .clearing = ADC_CLEAR_AFTER_READ_ON,
+ .trigger_group_b = ADC_START_SOURCE_DISABLED,
+ .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
+ .adc_vref_control = ADC_VREF_CONTROL_VREFH,
+ .enable_adbuf = 0,
+ .window_a_irq = FSP_INVALID_VECTOR,
+ .window_a_ipl = (1),
+ .window_b_irq = FSP_INVALID_VECTOR,
+ .window_b_ipl = (BSP_IRQ_DISABLED),
+ .trigger = ADC_START_SOURCE_DISABLED, /* Use Software trigger */
+};
+
+#define IRQ_CONFIGURE_FUNC(idx) \
+ static void adc_ra_configure_func_##idx(void) \
+ { \
+ R_ICU->IELSR[DT_INST_IRQ_BY_NAME(idx, scanend, irq)] = \
+ ELC_EVENT_ADC##idx##_SCAN_END; \
+ IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
+ DT_INST_IRQ_BY_NAME(idx, scanend, priority), adc_ra_isr, \
+ DEVICE_DT_INST_GET(idx), 0); \
+ irq_enable(DT_INST_IRQ_BY_NAME(idx, scanend, irq)); \
+ }
+
+#define IRQ_CONFIGURE_DEFINE(idx) .irq_configure = adc_ra_configure_func_##idx
+
+#define ADC_RA_INIT(idx) \
+ IRQ_CONFIGURE_FUNC(idx) \
+ PINCTRL_DT_INST_DEFINE(idx); \
+ static struct adc_driver_api adc_ra_api_##idx = { \
+ .channel_setup = adc_ra_channel_setup, \
+ .read = adc_ra_read, \
+ .ref_internal = DT_INST_PROP(idx, vref_mv), \
+ IF_ENABLED(CONFIG_ADC_ASYNC, (.read_async = adc_ra_read_async))}; \
+ static const struct adc_ra_config adc_ra_config_##idx = { \
+ .num_channels = DT_INST_PROP(idx, channels_num), \
+ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
+ IRQ_CONFIGURE_DEFINE(idx), \
+ }; \
+ static struct adc_ra_data adc_ra_data_##idx = { \
+ ADC_CONTEXT_INIT_TIMER(adc_ra_data_##idx, ctx), \
+ ADC_CONTEXT_INIT_LOCK(adc_ra_data_##idx, ctx), \
+ ADC_CONTEXT_INIT_SYNC(adc_ra_data_##idx, ctx), \
+ .dev = DEVICE_DT_INST_GET(idx), \
+ .f_config = \
+ { \
+ .unit = idx, \
+ .mode = ADC_MODE_SINGLE_SCAN, \
+ .resolution = ADC_RESOLUTION_12_BIT, \
+ .alignment = (adc_alignment_t)ADC_ALIGNMENT_RIGHT, \
+ .trigger = 0, \
+ .p_callback = NULL, \
+ .p_context = NULL, \
+ .p_extend = &g_adc_cfg_extend, \
+ .scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
+ .scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
+ .scan_end_b_irq = FSP_INVALID_VECTOR, \
+ .scan_end_b_ipl = (BSP_IRQ_DISABLED), \
+ }, \
+ .f_channel_cfg = \
+ { \
+ .scan_mask = 0, \
+ .scan_mask_group_b = 0, \
+ .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, \
+ .add_mask = 0, \
+ .sample_hold_mask = 0, \
+ .sample_hold_states = 24, \
+ .p_window_cfg = NULL, \
+ }, \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(idx, adc_ra_init, NULL, &adc_ra_data_##idx, &adc_ra_config_##idx, \
+ POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, &adc_ra_api_##idx)
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_RA_INIT);
diff --git a/drivers/adc/adc_rpi_pico.c b/drivers/adc/adc_rpi_pico.c
index 76c3a52..3f63924 100644
--- a/drivers/adc/adc_rpi_pico.c
+++ b/drivers/adc/adc_rpi_pico.c
@@ -91,8 +91,9 @@
static inline void adc_enable(void)
{
adc_hw->cs = ADC_CS_EN_BITS;
- while (!(adc_hw->cs & ADC_CS_READY_BITS))
+ while (!(adc_hw->cs & ADC_CS_READY_BITS)) {
;
+ }
}
static int adc_rpi_channel_setup(const struct device *dev,
diff --git a/drivers/adc/adc_smartbond_sdadc.c b/drivers/adc/adc_smartbond_sdadc.c
index 0b95b1f..de7b718 100644
--- a/drivers/adc/adc_smartbond_sdadc.c
+++ b/drivers/adc/adc_smartbond_sdadc.c
@@ -150,8 +150,9 @@
int current_channel = u32_count_trailing_zeros(data->channel_read_mask);
/* Wait until the SDADC LDO stabilizes */
- while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk))
+ while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk)) {
__NOP();
+ }
if (ctx->sequence.calibrate) {
/* TODO: Add calibration code */
diff --git a/drivers/bluetooth/hci/Kconfig b/drivers/bluetooth/hci/Kconfig
index 2a0f2d1..9392044 100644
--- a/drivers/bluetooth/hci/Kconfig
+++ b/drivers/bluetooth/hci/Kconfig
@@ -93,7 +93,7 @@
config BT_USERCHAN
bool "HCI User Channel based driver"
- depends on BOARD_NATIVE_POSIX
+ depends on (BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM)
default y
depends on DT_HAS_ZEPHYR_BT_HCI_USERCHAN_ENABLED
help
diff --git a/drivers/bluetooth/hci/Kconfig.nxp b/drivers/bluetooth/hci/Kconfig.nxp
index 65bbc30..5ba557e 100644
--- a/drivers/bluetooth/hci/Kconfig.nxp
+++ b/drivers/bluetooth/hci/Kconfig.nxp
@@ -23,6 +23,25 @@
If enabled, the Host will send calibration data annex 100 to the BLE Controller during HCI
init.
+if BT_NXP
+
+config BT_DIS_MANUF
+ default "NXP"
+
+config BT_HCI_ACL_FLOW_CONTROL
+ default n
+
+config BT_BUF_EVT_DISCARDABLE_SIZE
+ default 84
+
+config HEAP_MEM_POOL_SIZE
+ default 256
+
+config FLASH
+ default y
+
+endif # BT_NXP
+
if BT_H4_NXP_CTLR
config BT_NXP_NW612
diff --git a/drivers/bluetooth/hci/h4.c b/drivers/bluetooth/hci/h4.c
index 412214c..a37eb7f 100644
--- a/drivers/bluetooth/hci/h4.c
+++ b/drivers/bluetooth/hci/h4.c
@@ -252,7 +252,7 @@
/* Let the ISR continue receiving new packets */
uart_irq_rx_enable(cfg->uart);
- buf = net_buf_get(&h4->rx.fifo, K_FOREVER);
+ buf = k_fifo_get(&h4->rx.fifo, K_FOREVER);
do {
uart_irq_rx_enable(cfg->uart);
@@ -266,7 +266,7 @@
k_yield();
uart_irq_rx_disable(cfg->uart);
- buf = net_buf_get(&h4->rx.fifo, K_NO_WAIT);
+ buf = k_fifo_get(&h4->rx.fifo, K_NO_WAIT);
} while (buf);
}
}
@@ -352,7 +352,7 @@
reset_rx(h4);
LOG_DBG("Putting buf %p to rx fifo", buf);
- net_buf_put(&h4->rx.fifo, buf);
+ k_fifo_put(&h4->rx.fifo, buf);
}
static inline void read_header(const struct device *dev)
@@ -398,7 +398,7 @@
int bytes;
if (!h4->tx.buf) {
- h4->tx.buf = net_buf_get(&h4->tx.fifo, K_NO_WAIT);
+ h4->tx.buf = k_fifo_get(&h4->tx.fifo, K_NO_WAIT);
if (!h4->tx.buf) {
LOG_ERR("TX interrupt but no pending buffer!");
uart_irq_tx_disable(cfg->uart);
@@ -447,7 +447,7 @@
done:
h4->tx.type = BT_HCI_H4_NONE;
net_buf_unref(h4->tx.buf);
- h4->tx.buf = net_buf_get(&h4->tx.fifo, K_NO_WAIT);
+ h4->tx.buf = k_fifo_get(&h4->tx.fifo, K_NO_WAIT);
if (!h4->tx.buf) {
uart_irq_tx_disable(cfg->uart);
}
@@ -496,7 +496,7 @@
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
- net_buf_put(&h4->tx.fifo, buf);
+ k_fifo_put(&h4->tx.fifo, buf);
uart_irq_tx_enable(cfg->uart);
return 0;
diff --git a/drivers/bluetooth/hci/h5.c b/drivers/bluetooth/hci/h5.c
index 0be22f6..ae75088 100644
--- a/drivers/bluetooth/hci/h5.c
+++ b/drivers/bluetooth/hci/h5.c
@@ -212,7 +212,7 @@
LOG_DBG("Need to remove %u packet from the queue", number_removed);
while (number_removed) {
- struct net_buf *buf = net_buf_get(&h5->unack_queue, K_NO_WAIT);
+ struct net_buf *buf = k_fifo_get(&h5->unack_queue, K_NO_WAIT);
if (!buf) {
LOG_ERR("Unack queue is empty");
@@ -349,22 +349,22 @@
k_fifo_init(&tmp_queue);
/* Queue to temporary queue */
- while ((buf = net_buf_get(&h5->tx_queue, K_NO_WAIT))) {
- net_buf_put(&tmp_queue, buf);
+ while ((buf = k_fifo_get(&h5->tx_queue, K_NO_WAIT))) {
+ k_fifo_put(&tmp_queue, buf);
}
/* Queue unack packets to the beginning of the queue */
- while ((buf = net_buf_get(&h5->unack_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&h5->unack_queue, K_NO_WAIT))) {
/* include also packet type */
net_buf_push(buf, sizeof(uint8_t));
- net_buf_put(&h5->tx_queue, buf);
+ k_fifo_put(&h5->tx_queue, buf);
h5->tx_seq = (h5->tx_seq - 1) & 0x07;
h5->unack_queue_len--;
}
/* Queue saved packets from temp queue */
- while ((buf = net_buf_get(&tmp_queue, K_NO_WAIT))) {
- net_buf_put(&h5->tx_queue, buf);
+ while ((buf = k_fifo_get(&tmp_queue, K_NO_WAIT))) {
+ k_fifo_put(&h5->tx_queue, buf);
}
}
}
@@ -408,7 +408,7 @@
net_buf_unref(buf);
break;
case HCI_3WIRE_LINK_PKT:
- net_buf_put(&h5->rx_queue, buf);
+ k_fifo_put(&h5->rx_queue, buf);
break;
case HCI_EVENT_PKT:
case HCI_ACLDATA_PKT:
@@ -619,7 +619,7 @@
memcpy(net_buf_push(buf, sizeof(type)), &type, sizeof(type));
- net_buf_put(&h5->tx_queue, buf);
+ k_fifo_put(&h5->tx_queue, buf);
return 0;
}
@@ -653,7 +653,7 @@
k_sleep(K_MSEC(100));
break;
case ACTIVE:
- buf = net_buf_get(&h5->tx_queue, K_FOREVER);
+ buf = k_fifo_get(&h5->tx_queue, K_FOREVER);
type = h5_get_type(buf);
h5_send(dev, buf->data, type, buf->len);
@@ -661,7 +661,7 @@
/* buf is dequeued from tx_queue and queued to unack
* queue.
*/
- net_buf_put(&h5->unack_queue, buf);
+ k_fifo_put(&h5->unack_queue, buf);
h5->unack_queue_len++;
k_work_reschedule(&h5->retx_work, H5_TX_ACK_TIMEOUT);
@@ -689,7 +689,7 @@
while (true) {
struct net_buf *buf;
- buf = net_buf_get(&h5->rx_queue, K_FOREVER);
+ buf = k_fifo_get(&h5->rx_queue, K_FOREVER);
hexdump("=> ", buf->data, buf->len);
diff --git a/drivers/bluetooth/hci/hci_da1469x.c b/drivers/bluetooth/hci/hci_da1469x.c
index 18733d8..8ffbb1b 100644
--- a/drivers/bluetooth/hci/hci_da1469x.c
+++ b/drivers/bluetooth/hci/hci_da1469x.c
@@ -242,7 +242,7 @@
/* Let the ISR continue receiving new packets */
rx_isr_start();
- buf = net_buf_get(&rx.fifo, K_FOREVER);
+ buf = k_fifo_get(&rx.fifo, K_FOREVER);
do {
rx_isr_start();
@@ -257,7 +257,7 @@
rx_isr_stop();
- buf = net_buf_get(&rx.fifo, K_NO_WAIT);
+ buf = k_fifo_get(&rx.fifo, K_NO_WAIT);
} while (buf);
}
}
@@ -339,7 +339,7 @@
reset_rx();
LOG_DBG("Putting buf %p to rx fifo", buf);
- net_buf_put(&rx.fifo, buf);
+ k_fifo_put(&rx.fifo, buf);
}
static inline void read_header(void)
diff --git a/drivers/cache/Kconfig.nrf b/drivers/cache/Kconfig.nrf
index c1cfc2c..ba8d086 100644
--- a/drivers/cache/Kconfig.nrf
+++ b/drivers/cache/Kconfig.nrf
@@ -10,6 +10,6 @@
config CACHE_NRF_PATCH_LINEADDR
bool "Patch lineaddr"
- default y if SOC_NRF54H20
+ default y if SOC_NRF54H20 || SOC_NRF9280
help
Manually set 28th bit in the LINEADDR in Trustzone Secure build.
diff --git a/drivers/can/Kconfig.mcux b/drivers/can/Kconfig.mcux
index a0e3e00..e2ee5a8 100644
--- a/drivers/can/Kconfig.mcux
+++ b/drivers/can/Kconfig.mcux
@@ -31,10 +31,11 @@
config CAN_MAX_MB
int "Maximum number of message buffers for concurrent active instances"
default 16
- depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1
+ depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1 || SOC_SERIES_S32ZE
range 1 96 if SOC_SERIES_S32K3
range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
range 1 64 if SOC_S32K142W || SOC_S32K144W
+ range 1 128 if SOC_SERIES_S32ZE
help
Defines maximum number of message buffers for concurrent active instances.
@@ -47,6 +48,7 @@
range 1 96 if SOC_SERIES_S32K3
range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
range 1 64 if SOC_S32K142W || SOC_S32K144W
+ range 1 128 if SOC_SERIES_S32ZE
help
Defines maximum number of concurrent active RX filters
diff --git a/drivers/can/can_esp32_twai.c b/drivers/can/can_esp32_twai.c
index aba78ae..6cbad32 100644
--- a/drivers/can/can_esp32_twai.c
+++ b/drivers/can/can_esp32_twai.c
@@ -71,6 +71,8 @@
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
int irq_source;
+ int irq_priority;
+ int irq_flags;
#ifndef CONFIG_SOC_SERIES_ESP32
/* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
uint32_t cdr32;
@@ -202,9 +204,16 @@
can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32);
#endif /* !CONFIG_SOC_SERIES_ESP32 */
- esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL);
+ err = esp_intr_alloc(twai_config->irq_source,
+ ESP_PRIO_TO_FLAGS(twai_config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(twai_config->irq_flags) | ESP_INTR_FLAG_IRAM,
+ can_esp32_twai_isr, (void *)dev, NULL);
- return 0;
+ if (err != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", err);
+ }
+
+ return err;
}
const struct can_driver_api can_esp32_twai_driver_api = {
@@ -271,7 +280,9 @@
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, offset), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
- .irq_source = DT_INST_IRQN(inst), \
+ .irq_source = DT_INST_IRQ_BY_IDX(inst, 0, irq), \
+ .irq_priority = DT_INST_IRQ_BY_IDX(inst, 0, priority), \
+ .irq_flags = DT_INST_IRQ_BY_IDX(inst, 0, flags), \
TWAI_CDR32_INIT(inst) \
}; \
CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst); \
diff --git a/drivers/can/can_fake.c b/drivers/can/can_fake.c
index c67bfdd..88666c5 100644
--- a/drivers/can/can_fake.c
+++ b/drivers/can/can_fake.c
@@ -95,6 +95,14 @@
ZTEST_RULE(fake_can_reset_rule, fake_can_reset_rule_before, NULL);
#endif /* CONFIG_ZTEST */
+static int fake_can_init(const struct device *dev)
+{
+ /* Install default delegate for reporting the core clock */
+ fake_can_get_core_clock_fake.custom_fake = fake_can_get_core_clock_delegate;
+
+ return 0;
+}
+
static const struct can_driver_api fake_can_driver_api = {
.start = fake_can_start,
.stop = fake_can_stop,
@@ -159,7 +167,7 @@
\
static struct fake_can_data fake_can_data_##inst; \
\
- CAN_DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &fake_can_data_##inst, \
+ CAN_DEVICE_DT_INST_DEFINE(inst, fake_can_init, NULL, &fake_can_data_##inst, \
&fake_can_config_##inst, POST_KERNEL, \
CONFIG_CAN_INIT_PRIORITY, \
&fake_can_driver_api);
diff --git a/drivers/can/can_native_linux.c b/drivers/can/can_native_linux.c
index c62faa4..6d1ccf4 100644
--- a/drivers/can/can_native_linux.c
+++ b/drivers/can/can_native_linux.c
@@ -495,9 +495,9 @@
DT_INST_FOREACH_STATUS_OKAY(CAN_NATIVE_LINUX_INIT)
-static void add_native_posix_options(void)
+static void add_native_options(void)
{
- static struct args_struct_t can_native_posix_options[] = {
+ static struct args_struct_t can_native_options[] = {
{
.is_mandatory = false,
.option = "can-if",
@@ -509,7 +509,7 @@
ARG_TABLE_ENDMARKER,
};
- native_add_command_line_opts(can_native_posix_options);
+ native_add_command_line_opts(can_native_options);
}
-NATIVE_TASK(add_native_posix_options, PRE_BOOT_1, 10);
+NATIVE_TASK(add_native_options, PRE_BOOT_1, 10);
diff --git a/drivers/can/can_native_linux_adapt.h b/drivers/can/can_native_linux_adapt.h
index 8d19b34..6ad06f6 100644
--- a/drivers/can/can_native_linux_adapt.h
+++ b/drivers/can/can_native_linux_adapt.h
@@ -8,8 +8,8 @@
* @brief Private functions for native posix canbus driver.
*/
-#ifndef ZEPHYR_DRIVERS_CAN_NATIVE_POSIX_LINUX_SOCKETCAN_H_
-#define ZEPHYR_DRIVERS_CAN_NATIVE_POSIX_LINUX_SOCKETCAN_H_
+#ifndef ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_
+#define ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_
int linux_socketcan_iface_open(const char *if_name);
@@ -21,4 +21,4 @@
int linux_socketcan_set_mode_fd(int fd, bool mode_fd);
-#endif /* ZEPHYR_DRIVERS_CAN_NATIVE_POSIX_LINUX_SOCKETCAN_H_ */
+#endif /* ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_ */
diff --git a/drivers/can/can_nxp_s32_canxl.c b/drivers/can/can_nxp_s32_canxl.c
index 2f2a204..7c6f052 100644
--- a/drivers/can/can_nxp_s32_canxl.c
+++ b/drivers/can/can_nxp_s32_canxl.c
@@ -167,7 +167,7 @@
}
/* Get the RxFiFO filter matched with the received RxFIFO message queue */
-static inline int can_nxp_s32_get_rx_fifo_filter(struct can_nxp_s32_data *data)
+static inline int can_nxp_s32_get_rx_fifo_filter(struct can_nxp_s32_data *data, uint8_t queue_idx)
{
int alloc = -ENOSPC;
uint32_t mask;
@@ -179,8 +179,8 @@
continue;
}
- if ((data->rx_fifo[0].Header.Id & mask) ==
- (data->rx_fifo_filter[filter_id].idAddrFilterH & mask)) {
+ if ((data->rx_fifo[queue_idx].Header.Id & mask) ==
+ (data->rx_fifo_filter[filter_id].idAddrFilterH & mask)) {
alloc = filter_id;
break;
}
@@ -259,6 +259,17 @@
return 0;
}
+static void can_nxp_s32_set_fd_mode(CANXL_SIC_Type *base,
+ boolean enable_fd,
+ boolean enable_brs)
+{
+ base->BCFG2 = (base->BCFG2 & ~CANXL_SIC_BCFG2_FDEN_MASK) |
+ CANXL_SIC_BCFG2_FDEN(enable_fd ? 1UL : 0UL);
+ base->BCFG1 = (base->BCFG1 & ~CANXL_SIC_BCFG1_FDRSDIS_MASK) |
+ CANXL_SIC_BCFG1_FDRSDIS(enable_brs ? 0UL : 1UL);
+ base->BTDCC &= ~(CANXL_SIC_BTDCC_FTDCEN_MASK |
+ CANXL_SIC_BTDCC_FTDCOFF_MASK);
+}
static int can_nxp_s32_set_mode(const struct device *dev, can_mode_t mode)
{
@@ -304,7 +315,7 @@
Canexcel_Ip_EnterFreezeMode(config->instance);
- CanXL_SetFDEnabled(config->base_sic, canfd, brs);
+ can_nxp_s32_set_fd_mode(config->base_sic, canfd, brs);
if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
Canexcel_Ip_StatusType status;
@@ -733,7 +744,7 @@
static void can_nxp_s32_err_callback(const struct device *dev,
Canexcel_Ip_EventType eventType,
- uint32 u32SysStatus,
+ uint32_t u32SysStatus,
const Canexcel_Ip_StateType *canexcelState)
{
const struct can_nxp_s32_config *config = dev->config;
@@ -857,7 +868,7 @@
}
static void can_nxp_s32_ctrl_callback(const struct device *dev,
- Canexcel_Ip_EventType eventType, uint32 buffidx,
+ Canexcel_Ip_EventType eventType, uint32_t buffidx,
const Canexcel_Ip_StateType *canexcelState)
{
const struct can_nxp_s32_config *config = dev->config;
@@ -877,12 +888,17 @@
}
#ifdef CONFIG_CAN_NXP_S32_RX_FIFO
} else if (eventType == CANEXCEL_EVENT_RXFIFO_COMPLETE) {
- alloc = can_nxp_s32_get_rx_fifo_filter(data);
+ uint8_t queue_idx = ((config->base_rx_fifo_ctrl->RXFCSTA &
+ CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_MASK) >>
+ CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_SHIFT) -
+ 1;
+
+ alloc = can_nxp_s32_get_rx_fifo_filter(data, queue_idx);
if (alloc != -ENOSPC) {
rx_func = data->rx_cbs[alloc].function;
if (atomic_test_bit(data->rx_allocs, alloc)) {
- nxp_s32_msg_data_to_zcan_frame(data->rx_fifo[0], &frame);
+ nxp_s32_msg_data_to_zcan_frame(data->rx_fifo[queue_idx], &frame);
LOG_DBG("%s: Received %d bytes Rx FiFo %d, "
"Rx Id: 0x%x, "
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index 80b004a..caa240b 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -4,6 +4,7 @@
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_adsp.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ARM_SCMI clock_control_arm_scmi.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK clock_control_fixed_rate.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c)
diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig
index 4c03ce4..7d661a1 100644
--- a/drivers/clock_control/Kconfig
+++ b/drivers/clock_control/Kconfig
@@ -82,7 +82,7 @@
source "drivers/clock_control/Kconfig.renesas_ra"
-source "drivers/clock_control/Kconfig.renesas_ra8"
+source "drivers/clock_control/Kconfig.renesas_ra_cgc"
source "drivers/clock_control/Kconfig.max32"
@@ -94,4 +94,6 @@
source "drivers/clock_control/Kconfig.nrf_auxpll"
+source "drivers/clock_control/Kconfig.arm_scmi"
+
endif # CLOCK_CONTROL
diff --git a/drivers/clock_control/Kconfig.arm_scmi b/drivers/clock_control/Kconfig.arm_scmi
new file mode 100644
index 0000000..d8c7de0
--- /dev/null
+++ b/drivers/clock_control/Kconfig.arm_scmi
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+
+config CLOCK_CONTROL_ARM_SCMI
+ bool "SCMI clock protocol clock controller driver"
+ default y
+ depends on ARM_SCMI_CLK_HELPERS
+ help
+ Enable support for SCMI-based clock control.
diff --git a/drivers/clock_control/Kconfig.renesas_ra8 b/drivers/clock_control/Kconfig.renesas_ra_cgc
similarity index 100%
rename from drivers/clock_control/Kconfig.renesas_ra8
rename to drivers/clock_control/Kconfig.renesas_ra_cgc
diff --git a/drivers/clock_control/clock_control_arm_scmi.c b/drivers/clock_control/clock_control_arm_scmi.c
new file mode 100644
index 0000000..202f7eb
--- /dev/null
+++ b/drivers/clock_control/clock_control_arm_scmi.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/clk.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(arm_scmi_clock);
+
+#define DT_DRV_COMPAT arm_scmi_clock
+
+struct scmi_clock_data {
+ uint32_t clk_num;
+};
+
+static int scmi_clock_on_off(const struct device *dev,
+ clock_control_subsys_t clk, bool on)
+{
+ struct scmi_clock_data *data;
+ struct scmi_protocol *proto;
+ uint32_t clk_id;
+ struct scmi_clock_config cfg;
+
+ proto = dev->data;
+ data = proto->data;
+ clk_id = POINTER_TO_UINT(clk);
+
+ if (clk_id >= data->clk_num) {
+ return -EINVAL;
+ }
+
+ memset(&cfg, 0, sizeof(cfg));
+
+ cfg.attributes = SCMI_CLK_CONFIG_ENABLE_DISABLE(on);
+ cfg.clk_id = clk_id;
+
+ return scmi_clock_config_set(proto, &cfg);
+}
+
+static int scmi_clock_on(const struct device *dev, clock_control_subsys_t clk)
+{
+ return scmi_clock_on_off(dev, clk, true);
+}
+
+static int scmi_clock_off(const struct device *dev, clock_control_subsys_t clk)
+{
+ return scmi_clock_on_off(dev, clk, false);
+}
+
+static int scmi_clock_get_rate(const struct device *dev,
+ clock_control_subsys_t clk, uint32_t *rate)
+{
+ struct scmi_clock_data *data;
+ struct scmi_protocol *proto;
+ uint32_t clk_id;
+
+ proto = dev->data;
+ data = proto->data;
+ clk_id = POINTER_TO_UINT(clk);
+
+ if (clk_id >= data->clk_num) {
+ return -EINVAL;
+ }
+
+ return scmi_clock_rate_get(proto, clk_id, rate);
+}
+
+static struct clock_control_driver_api scmi_clock_api = {
+ .on = scmi_clock_on,
+ .off = scmi_clock_off,
+ .get_rate = scmi_clock_get_rate,
+};
+
+static int scmi_clock_init(const struct device *dev)
+{
+ struct scmi_protocol *proto;
+ struct scmi_clock_data *data;
+ int ret;
+ uint32_t attributes;
+
+ proto = dev->data;
+ data = proto->data;
+
+ ret = scmi_clock_protocol_attributes(proto, &attributes);
+ if (ret < 0) {
+ LOG_ERR("failed to fetch clock attributes: %d", ret);
+ return ret;
+ }
+
+ data->clk_num = SCMI_CLK_ATTRIBUTES_CLK_NUM(attributes);
+
+ return 0;
+}
+
+static struct scmi_clock_data data;
+
+DT_INST_SCMI_PROTOCOL_DEFINE(0, &scmi_clock_init, NULL, &data, NULL,
+ PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+ &scmi_clock_api);
diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c
index 7e4bc3c..74949f9 100644
--- a/drivers/clock_control/clock_control_esp32.c
+++ b/drivers/clock_control/clock_control_esp32.c
@@ -28,11 +28,15 @@
#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
#include <esp32s3/rom/rtc.h>
#include <soc/dport_reg.h>
-#elif CONFIG_SOC_SERIES_ESP32C3
+#elif defined(CONFIG_SOC_SERIES_ESP32C2)
+#define DT_CPU_COMPAT espressif_riscv
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
+#include <esp32c2/rom/rtc.h>
+#elif defined(CONFIG_SOC_SERIES_ESP32C3)
#define DT_CPU_COMPAT espressif_riscv
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
#include <esp32c3/rom/rtc.h>
-#elif CONFIG_SOC_SERIES_ESP32C6
+#elif defined(CONFIG_SOC_SERIES_ESP32C6)
#define DT_CPU_COMPAT espressif_riscv
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
#include <soc/lp_clkrst_reg.h>
@@ -42,7 +46,9 @@
#include <soc/dport_access.h>
#include <hal/clk_tree_ll.h>
#include <hal/usb_serial_jtag_ll.h>
-#endif /* CONFIG_SOC_SERIES_ESP32xx */
+#include <esp_private/esp_pmu.h>
+#include <ocode_init.h>
+#endif
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/esp32_clock_control.h>
@@ -69,7 +75,7 @@
if ((rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
rst_reason == RESET_REASON_CPU0_RTC_WDT
-#if !defined(CONFIG_SOC_SERIES_ESP32)
+#if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32C2)
|| rst_reason == RESET_REASON_CPU0_MWDT1
#endif
)) {
@@ -121,6 +127,21 @@
usb_serial_jtag_ll_enable_bus_clock(false);
}
+
+ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) ||
+ (rst_reason == RESET_REASON_CHIP_BROWN_OUT) ||
+ (rst_reason == RESET_REASON_SYS_RTC_WDT) ||
+ (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
+
+ periph_ll_disable_clk_set_rst(PERIPH_LP_I2C0_MODULE);
+
+ CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
+ CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_UART_CK_EN);
+ CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
+ CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_EXT_I2C_CK_EN);
+ CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_CPU_CK_EN);
+ WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
+ }
}
#else
static void esp32_clock_perip_init(void)
@@ -136,7 +157,9 @@
* that have been enabled before reset.
*/
if (reset_reason_is_cpu_reset()) {
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
@@ -151,7 +174,18 @@
#endif
} else {
common_perip_clk =
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ SYSTEM_SPI2_CLK_EN |
+#if ESP_CONSOLE_UART_NUM != 0
+ SYSTEM_UART_CLK_EN |
+#endif
+#if ESP_CONSOLE_UART_NUM != 1
+ SYSTEM_UART1_CLK_EN |
+#endif
+ SYSTEM_LEDC_CLK_EN |
+ SYSTEM_I2C_EXT0_CLK_EN |
+ SYSTEM_LEDC_CLK_EN;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
SYSTEM_WDG_CLK_EN |
SYSTEM_I2S0_CLK_EN |
#if ESP_CONSOLE_UART_NUM != 0
@@ -207,7 +241,7 @@
DPORT_SPI3_DMA_CLK_EN |
#endif /* CONFIG_SOC_SERIES_ESP32S2 */
DPORT_PWM3_CLK_EN;
-#endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
+#endif
#if !defined(CONFIG_SOC_SERIES_ESP32)
common_perip_clk1 = 0;
@@ -224,6 +258,9 @@
DPORT_CRYPTO_SHA_CLK_EN |
DPORT_CRYPTO_RSA_CLK_EN;
#endif /* CONFIG_SOC_SERIES_ESP32S2 */
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ SYSTEM_CRYPTO_SHA_CLK_EN;
+#endif
#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
SYSTEM_CRYPTO_AES_CLK_EN |
SYSTEM_CRYPTO_SHA_CLK_EN |
@@ -231,7 +268,12 @@
#endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
wifi_bt_sdio_clk =
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ SYSTEM_WIFI_CLK_WIFI_EN |
+ SYSTEM_WIFI_CLK_BT_EN_M |
+ SYSTEM_WIFI_CLK_UNUSED_BIT5 |
+ SYSTEM_WIFI_CLK_UNUSED_BIT12;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
SYSTEM_WIFI_CLK_WIFI_EN |
SYSTEM_WIFI_CLK_BT_EN_M |
SYSTEM_WIFI_CLK_I2C_CLK_EN |
@@ -252,7 +294,16 @@
/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
common_perip_clk |=
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ SYSTEM_SPI2_CLK_EN |
+#if ESP_CONSOLE_UART_NUM != 0
+ SYSTEM_UART_CLK_EN |
+#endif
+#if ESP_CONSOLE_UART_NUM != 1
+ SYSTEM_UART1_CLK_EN |
+#endif
+ SYSTEM_I2C_EXT0_CLK_EN;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
SYSTEM_I2S0_CLK_EN |
#if ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
@@ -337,7 +388,9 @@
#endif /* CONFIG_SOC_SERIES_ESP32S2 */
/* Disable some peripheral clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
@@ -354,7 +407,9 @@
#endif
/* Disable hardware crypto clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
#elif defined(CONFIG_SOC_SERIES_ESP32)
@@ -374,7 +429,9 @@
#endif /* CONFIG_SOC_SERIES_ESP32S3 */
/* Disable WiFi/BT/SDIO clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
#else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
@@ -386,7 +443,9 @@
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
#endif
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
@@ -401,7 +460,9 @@
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32S3)
periph_module_enable(PERIPH_TIMG0_MODULE);
#endif
}
@@ -477,6 +538,17 @@
int retry_32k_xtal = 3;
do {
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+ /* external clock needs to be connected to PIN0 before it can
+ * be used. Here we use rtc_clk_cal function to count
+ * the number of ext clk cycles in the given number of ext clk
+ * cycles. If the ext clk has not started up, calibration
+ * will time out, returning 0.
+ */
+ LOG_DBG("waiting for external clock by pin0 to start up");
+ rtc_clk_32k_enable_external();
+#else
if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) {
/* 32k XTAL oscillator needs to be enabled and running before it can
* be used. Hardware doesn't have a direct way of checking if the
@@ -491,11 +563,17 @@
} else if (slow_clk == ESP32_RTC_SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_enable_external();
}
+#endif
/* When CONFIG_RTC_CLK_CAL_CYCLES is set to 0, clock calibration will not be
* performed at startup.
*/
if (CONFIG_RTC_CLK_CAL_CYCLES > 0) {
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ cal_val = rtc_clk_cal(RTC_CAL_32K_OSC_SLOW,
+ CONFIG_RTC_CLK_CAL_CYCLES);
+#else
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, CONFIG_RTC_CLK_CAL_CYCLES);
+#endif
if (cal_val == 0) {
if (retry_32k_xtal-- > 0) {
continue;
@@ -607,7 +685,7 @@
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz /
old_config.freq_mhz);
-#if !defined(CONFIG_SOC_SERIES_ESP32C6)
+#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6)
#if ESP_ROM_UART_CLK_IS_XTAL
uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
#else
@@ -658,22 +736,29 @@
{
const struct esp32_clock_config *cfg = dev->config;
bool ret;
-#if !defined(CONFIG_SOC_SERIES_ESP32C6)
soc_reset_reason_t rst_reas;
- rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
rst_reas = esp_rom_get_reset_reason(0);
+
+#if defined(CONFIG_SOC_SERIES_ESP32C6)
+ pmu_init();
+ if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
+ esp_ocode_calib_init();
+ }
+#else /* CONFIG_SOC_SERIES_ESP32C6 */
+ rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
+
#if !defined(CONFIG_SOC_SERIES_ESP32)
if (rst_reas == RESET_REASON_CHIP_POWER_ON
#if SOC_EFUSE_HAS_EFUSE_RST_BUG
|| rst_reas == RESET_REASON_CORE_EFUSE_CRC
-#endif
+#endif /* SOC_EFUSE_HAS_EFUSE_RST_BUG */
) {
rtc_cfg.cali_ocode = 1;
}
-#endif
+#endif /* !CONFIG_SOC_SERIES_ESP32 */
rtc_init(rtc_cfg);
-#endif
+#endif /* CONFIG_SOC_SERIES_ESP32C6 */
ret = esp32_cpu_clock_configure(&cfg->cpu);
if (ret) {
diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
index 371914c..bb2fc21 100644
--- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c
+++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -25,7 +25,7 @@
switch (peripheral) {
#ifdef CONFIG_ETH_NXP_ENET
-#ifdef CONFIG_SOC_MIMX9352_A55
+#ifdef CONFIG_SOC_MIMX9352
#define ENET1G_CLOCK kCLOCK_Enet1
#else
#define ENET_CLOCK kCLOCK_Enet
@@ -63,10 +63,16 @@
instance = (clock_name & IMX_CCM_INSTANCE_MASK);
switch (peripheral) {
#ifdef CONFIG_I2C_MCUX_LPI2C
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+ case IMX_CCM_LPI2C0102_CLK:
+ clock_root = kCLOCK_Root_Lpi2c0102 + instance;
+ break;
+#else
case IMX_CCM_LPI2C1_CLK:
clock_root = kCLOCK_Root_Lpi2c1 + instance;
break;
#endif
+#endif
#ifdef CONFIG_SPI_MCUX_LPSPI
case IMX_CCM_LPSPI1_CLK:
@@ -75,11 +81,18 @@
#endif
#ifdef CONFIG_UART_MCUX_LPUART
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+ case IMX_CCM_LPUART0102_CLK:
+ case IMX_CCM_LPUART0304_CLK:
+ clock_root = kCLOCK_Root_Lpuart0102 + instance;
+ break;
+#else
case IMX_CCM_LPUART1_CLK:
case IMX_CCM_LPUART2_CLK:
clock_root = kCLOCK_Root_Lpuart1 + instance;
break;
#endif
+#endif
#if CONFIG_IMX_USDHC
case IMX_CCM_USDHC1_CLK:
@@ -133,7 +146,7 @@
#ifdef CONFIG_ETH_NXP_ENET
case IMX_CCM_ENET_CLK:
case IMX_CCM_ENET1G_CLK:
-#ifdef CONFIG_SOC_MIMX9352_A55
+#ifdef CONFIG_SOC_MIMX9352
clock_root = kCLOCK_Root_WakeupAxi;
#else
clock_root = kCLOCK_Root_Bus;
@@ -141,7 +154,7 @@
break;
#endif
-#if defined(CONFIG_SOC_MIMX9352_A55) && defined(CONFIG_DAI_NXP_SAI)
+#if defined(CONFIG_SOC_MIMX9352) && defined(CONFIG_DAI_NXP_SAI)
case IMX_CCM_SAI1_CLK:
case IMX_CCM_SAI2_CLK:
case IMX_CCM_SAI3_CLK:
@@ -196,7 +209,7 @@
default:
return -EINVAL;
}
-#ifdef CONFIG_SOC_MIMX9352_A55
+#ifdef CONFIG_SOC_MIMX9352
*rate = CLOCK_GetIpFreq(clock_root);
#else
*rate = CLOCK_GetRootClockFreq(clock_root);
diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c
index b7a39b1..b173131 100644
--- a/drivers/clock_control/clock_control_mcux_syscon.c
+++ b/drivers/clock_control/clock_control_mcux_syscon.c
@@ -206,7 +206,7 @@
#if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
-#if CONFIG_SOC_FAMILY_NXP_MCX
+#if CONFIG_SOC_SERIES_MCXN
case MCUX_USDHC1_CLK:
*rate = CLOCK_GetUsdhcClkFreq();
break;
diff --git a/drivers/clock_control/clock_control_npcx.c b/drivers/clock_control/clock_control_npcx.c
index 7aa280c..b41fb9d 100644
--- a/drivers/clock_control/clock_control_npcx.c
+++ b/drivers/clock_control/clock_control_npcx.c
@@ -223,8 +223,9 @@
/* Load M and N values into the frequency multiplier */
inst_cdcg->HFCGCTRL |= BIT(NPCX_HFCGCTRL_LOAD);
/* Wait for stable */
- while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
+ while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG)) {
;
+ }
}
/* Set all clock prescalers of core and peripherals. */
diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c
index e68c657..ebbae6e 100644
--- a/drivers/clock_control/clock_control_renesas_ra_cgc.c
+++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c
@@ -77,7 +77,7 @@
};
#define INIT_PCLK(node_id) \
- IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra8_cgc_pclk), \
+ IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \
(static const struct clock_control_ra_pclk_cfg node_id##_cfg = \
{.clk_src = DT_PROP_OR(node_id, clk_src, RA_CLOCK_SOURCE_DISABLE), \
.clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \
diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c
index b0bcb9c..e7f058e 100644
--- a/drivers/clock_control/clock_control_rpi_pico.c
+++ b/drivers/clock_control/clock_control_rpi_pico.c
@@ -488,13 +488,21 @@
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
- clocks_hw_t *clocks_regs = config->clocks_regs;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
- hw_set_bits(&clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
+ switch (clkid) {
+ case rpi_pico_clkid_pll_sys:
+ hw_clear_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
+ break;
+ case rpi_pico_clkid_pll_usb:
+ hw_clear_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
+ break;
+ default:
+ hw_set_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
+ }
return 0;
}
@@ -503,13 +511,21 @@
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
- clocks_hw_t *clocks_regs = config->clocks_regs;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
- hw_clear_bits(&clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
+ switch (clkid) {
+ case rpi_pico_clkid_pll_sys:
+ hw_set_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
+ break;
+ case rpi_pico_clkid_pll_usb:
+ hw_set_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
+ break;
+ default:
+ hw_clear_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
+ }
return 0;
}
diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index c487ef4..cb216bc 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -109,7 +109,8 @@
defined(CONFIG_SOC_STM32H745XX_M7) || defined(CONFIG_SOC_STM32H745XX_M4) ||\
defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\
defined(CONFIG_SOC_STM32H750XX) ||\
- defined(CONFIG_SOC_STM32H753XX)
+ defined(CONFIG_SOC_STM32H753XX) ||\
+ defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4)
/* All h7 SoC with maximum 480MHz SYSCLK */
#define SYSCLK_FREQ_MAX 480000000UL
#define AHB_FREQ_MAX 240000000UL
diff --git a/drivers/counter/counter_esp32_rtc.c b/drivers/counter/counter_esp32_rtc.c
index 379a9f0..9172e5e 100644
--- a/drivers/counter/counter_esp32_rtc.c
+++ b/drivers/counter/counter_esp32_rtc.c
@@ -22,7 +22,7 @@
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/esp32_clock_control.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
@@ -31,7 +31,7 @@
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL);
-#if defined(CONFIG_SOC_SERIES_ESP32C3)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t
#else
#define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t
@@ -42,6 +42,8 @@
struct counter_esp32_config {
struct counter_config_info counter_info;
int irq_source;
+ int irq_priority;
+ int irq_flags;
const struct device *clock_dev;
};
@@ -56,19 +58,23 @@
const struct counter_esp32_config *cfg = dev->config;
struct counter_esp32_data *data = dev->data;
-
/* RTC_SLOW_CLK is the default clk source */
clock_control_get_rate(cfg->clock_dev,
(clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW,
&data->clk_src_freq);
- esp_intr_alloc(cfg->irq_source,
- 0,
- (ESP32_COUNTER_RTC_ISR_HANDLER)counter_esp32_isr,
- (void *)dev,
- NULL);
+ int ret = esp_intr_alloc(cfg->irq_source,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags),
+ (ESP32_COUNTER_RTC_ISR_HANDLER)counter_esp32_isr,
+ (void *)dev,
+ NULL);
- return 0;
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ }
+
+ return ret;
}
static int counter_esp32_start(const struct device *dev)
@@ -108,7 +114,8 @@
uint32_t now;
uint32_t ticks = 0;
-#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32C3)
+#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3)
/* In ESP32/C3 Series the min possible value is 30 us*/
if (counter_ticks_to_us(dev, alarm_cfg->ticks) < 30) {
return -EINVAL;
@@ -199,7 +206,9 @@
.channels = 1
},
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
- .irq_source = DT_INST_IRQN(0),
+ .irq_source = DT_INST_IRQ_BY_IDX(0, 0, irq),
+ .irq_priority = DT_INST_IRQ_BY_IDX(0, 0, priority),
+ .irq_flags = DT_INST_IRQ_BY_IDX(0, 0, flags)
};
static const struct counter_driver_api rtc_timer_esp32_api = {
diff --git a/drivers/counter/counter_esp32_tmr.c b/drivers/counter/counter_esp32_tmr.c
index 34d6b82..ef90dad 100644
--- a/drivers/counter/counter_esp32_tmr.c
+++ b/drivers/counter/counter_esp32_tmr.c
@@ -18,16 +18,16 @@
#include <zephyr/drivers/counter.h>
#include <zephyr/spinlock.h>
#include <zephyr/kernel.h>
-#ifndef CONFIG_SOC_SERIES_ESP32C3
-#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#else
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#else
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL);
-#ifdef CONFIG_SOC_SERIES_ESP32C3
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#define ISR_HANDLER isr_handler_t
#else
#define ISR_HANDLER intr_handler_t
@@ -50,6 +50,8 @@
timer_group_t group;
timer_idx_t index;
int irq_source;
+ int irq_priority;
+ int irq_flags;
};
struct counter_esp32_data {
@@ -70,9 +72,11 @@
case TIMER_GROUP_0:
periph_module_enable(PERIPH_TIMG0_MODULE);
break;
+#if !defined(CONFIG_SOC_SERIES_ESP32C2)
case TIMER_GROUP_1:
periph_module_enable(PERIPH_TIMG1_MODULE);
break;
+#endif
default:
return -ENOTSUP;
}
@@ -92,10 +96,19 @@
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en);
timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0);
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en);
- esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
+
k_spin_unlock(&lock, key);
- return 0;
+ int ret = esp_intr_alloc(cfg->irq_source,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags),
+ (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ }
+
+ return ret;
}
static int counter_esp32_start(const struct device *dev)
@@ -252,7 +265,9 @@
}, \
.group = DT_INST_PROP(idx, group), \
.index = DT_INST_PROP(idx, index), \
- .irq_source = DT_INST_IRQN(idx), \
+ .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
+ .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags) \
}; \
\
\
diff --git a/drivers/counter/counter_gecko_stimer.c b/drivers/counter/counter_gecko_stimer.c
index c582133..263bb20 100644
--- a/drivers/counter/counter_gecko_stimer.c
+++ b/drivers/counter/counter_gecko_stimer.c
@@ -110,8 +110,9 @@
bool is_top_timer_running = false;
error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
- if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true))
+ if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
return 0;
+ }
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
error_code = sl_sleeptimer_start_timer(&top_timer, dev_data->top_data.ticks, top_callback,
diff --git a/drivers/counter/counter_ll_stm32_timer.c b/drivers/counter/counter_ll_stm32_timer.c
index 8f6b1ff..22bcb7b 100644
--- a/drivers/counter/counter_ll_stm32_timer.c
+++ b/drivers/counter/counter_ll_stm32_timer.c
@@ -395,18 +395,18 @@
apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV));
#else
apb_psc = STM32_APB1_PRESCALER;
-#endif
+#endif /* CONFIG_SOC_SERIES_STM32MP1X */
}
-#if !defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_SOC_SERIES_STM32G0X)
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f0_rcc)
else {
#if defined(CONFIG_SOC_SERIES_STM32MP1X)
apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV));
#else
apb_psc = STM32_APB2_PRESCALER;
-#endif
+#endif /* CONFIG_SOC_SERIES_STM32MP1X */
}
-#endif
-#endif
+#endif /* ! st_stm32f0_rcc */
+#endif /* CONFIG_SOC_SERIES_STM32H7X */
#if defined(RCC_DCKCFGR_TIMPRE) || defined(RCC_DCKCFGR1_TIMPRE) || \
defined(RCC_CFGR_TIMPRE)
diff --git a/drivers/counter/counter_native_posix.c b/drivers/counter/counter_native_posix.c
index d03517b..0e40844 100644
--- a/drivers/counter/counter_native_posix.c
+++ b/drivers/counter/counter_native_posix.c
@@ -181,8 +181,9 @@
{
ARG_UNUSED(dev);
- if (is_alarm_pending[chan_id])
+ if (is_alarm_pending[chan_id]) {
return -EBUSY;
+ }
uint32_t ticks = alarm_cfg->ticks;
diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c
index 71cbed2..a0dd964 100644
--- a/drivers/dai/intel/dmic/dmic.c
+++ b/drivers/dai/intel/dmic/dmic.c
@@ -76,11 +76,13 @@
int i;
int n = 0;
- if (x < Q_CONVERT_FLOAT(-11.5, 27))
+ if (x < Q_CONVERT_FLOAT(-11.5, 27)) {
return 0;
+ }
- if (x > Q_CONVERT_FLOAT(7.6245, 27))
+ if (x > Q_CONVERT_FLOAT(7.6245, 27)) {
return INT32_MAX;
+ }
/* x is Q5.27 */
xs = x;
@@ -94,8 +96,9 @@
*/
z = Q_SHIFT_RND(exp_small_fixed(Q_SHIFT_LEFT(xs, 27, 29)), 23, 20);
y = ONE_Q20;
- for (i = 0; i < (1 << n); i++)
+ for (i = 0; i < (1 << n); i++) {
y = (int32_t)Q_MULTSR_32X32((int64_t)y, z, 20, 20, 20);
+ }
return y;
}
@@ -104,8 +107,9 @@
{
int32_t arg;
- if (db < Q_CONVERT_FLOAT(-100.0, 24))
+ if (db < Q_CONVERT_FLOAT(-100.0, 24)) {
return 0;
+ }
/* Q8.24 x Q5.27, result needs to be Q5.27 */
arg = (int32_t)Q_MULTSR_32X32((int64_t)db, LOG10_DIV20_Q27, 24, 27, 27);
@@ -383,8 +387,9 @@
* Note: dai_put() function that calls remove() applies the spinlock
* so it is not needed here to protect access to mask bits.
*/
- if (active_fifos_mask || pause_mask)
+ if (active_fifos_mask || pause_mask) {
return 0;
+ }
/* Disable DMIC clock and power */
dai_dmic_en_clk_gating(dmic);
@@ -442,8 +447,9 @@
/* Read SSP timestamp registers */
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
- if (!ntk)
+ if (!ntk) {
goto out;
+ }
/* NTK was set, get wall clock */
tsd->walclk = sys_read64(TS_DMIC_LOCAL_WALCLK);
@@ -456,8 +462,9 @@
out:
tsd->walclk_rate = cfg->walclk_rate;
- if (!ntk)
+ if (!ntk) {
return -ENODATA;
+ }
return 0;
}
@@ -484,8 +491,9 @@
* task associated with each DAI, so we don't need to hold the lock to
* read the value here.
*/
- if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11)
+ if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {
return;
+ }
key = k_spin_lock(&dmic->lock);
@@ -659,10 +667,11 @@
* If stop is not for pausing, it is safe to clear the pause bit.
*/
dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);
- if (stop_is_pause)
+ if (stop_is_pause) {
dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);
- else
+ } else {
dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);
+ }
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
/* Don't stop CIC yet if one FIFO remains active */
diff --git a/drivers/dai/intel/dmic/dmic.h b/drivers/dai/intel/dmic/dmic.h
index d690c0c..f11b72b 100644
--- a/drivers/dai/intel/dmic/dmic.h
+++ b/drivers/dai/intel/dmic/dmic.h
@@ -205,11 +205,13 @@
time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
LOGRAMP_TIME_OFFS_Q0;
- if (time_ms > LOGRAMP_TIME_MAX_MS)
+ if (time_ms > LOGRAMP_TIME_MAX_MS) {
return LOGRAMP_TIME_MAX_MS;
+ }
- if (time_ms < LOGRAMP_TIME_MIN_MS)
+ if (time_ms < LOGRAMP_TIME_MIN_MS) {
return LOGRAMP_TIME_MIN_MS;
+ }
return time_ms;
}
diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c
index 5f150e6..1512d6e 100644
--- a/drivers/dai/intel/dmic/dmic_nhlt.c
+++ b/drivers/dai/intel/dmic/dmic_nhlt.c
@@ -668,8 +668,9 @@
/* Configure clock source */
ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source);
- if (ret)
+ if (ret) {
return ret;
+ }
/* Get OUTCONTROLx configuration */
if (num_fifos < 1 || num_fifos > DMIC_HW_FIFOS_MAX) {
@@ -678,8 +679,9 @@
}
for (n = 0; n < DMIC_HW_FIFOS_MAX; n++) {
- if (!(channel_ctrl_mask & (1 << n)))
+ if (!(channel_ctrl_mask & (1 << n))) {
continue;
+ }
val = *(uint32_t *)p;
ret = print_outcontrol(val);
@@ -802,8 +804,9 @@
#else
ret = dai_nhlt_dmic_dai_params_get(dmic);
#endif
- if (ret)
+ if (ret) {
return ret;
+ }
LOG_INF("dmic_set_config_nhlt(): enable0 %u, enable1 %u",
dmic->enable[0], dmic->enable[1]);
diff --git a/drivers/dai/intel/hda/hda.c b/drivers/dai/intel/hda/hda.c
index 920094e..220089d 100644
--- a/drivers/dai/intel/hda/hda.c
+++ b/drivers/dai/intel/hda/hda.c
@@ -32,10 +32,13 @@
struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
const struct dai_intel_ipc_hda_params *config = spec_config;
- if (config->channels)
+ if (config->channels) {
hda->params.channels = config->channels;
- if (config->rate)
+ }
+
+ if (config->rate) {
hda->params.rate = config->rate;
+ }
return 0;
}
@@ -65,8 +68,9 @@
{
struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
- if (cfg->type == DAI_INTEL_HDA)
+ if (cfg->type == DAI_INTEL_HDA) {
return dai_hda_set_config_tplg(dp, bespoke_cfg);
+ }
return 0;
}
diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
index 7292b82..532bdc8 100644
--- a/drivers/dai/intel/ssp/ssp.c
+++ b/drivers/dai/intel/ssp/ssp.c
@@ -1999,8 +1999,9 @@
aux_len = cfg_len - pre_aux_len;
aux_ptr = (uint8_t *)blob + pre_aux_len;
- if (aux_len <= 0)
+ if (aux_len <= 0) {
return 0;
+ }
return dai_ssp_parse_tlv(dp, aux_ptr, aux_len);
}
@@ -2132,17 +2133,20 @@
if (blob15->version == SSP_BLOB_VER_1_5) {
err = dai_ssp_parse_aux_data(dp, spec_config);
- if (err)
+ if (err) {
return err;
+ }
dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
- if (err)
+ if (err) {
return err;
+ }
} else {
dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
- if (err)
+ if (err) {
return err;
+ }
}
ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;
diff --git a/drivers/dai/nxp/esai/esai.c b/drivers/dai/nxp/esai/esai.c
index 1d7bea6..bcc0542 100644
--- a/drivers/dai/nxp/esai/esai.c
+++ b/drivers/dai/nxp/esai/esai.c
@@ -684,8 +684,6 @@
device_map(&data->regmap, cfg->regmap_phys, cfg->regmap_size, K_MEM_CACHE_NONE);
- ESAI_Reset(UINT_TO_ESAI(data->regmap));
-
ret = esai_parse_pinmodes(cfg, data);
if (ret < 0) {
return ret;
diff --git a/drivers/disk/sdmmc_subsys.c b/drivers/disk/sdmmc_subsys.c
index e2511d1..4eb61c9 100644
--- a/drivers/disk/sdmmc_subsys.c
+++ b/drivers/disk/sdmmc_subsys.c
@@ -93,12 +93,9 @@
case DISK_IOCTL_CTRL_INIT:
return disk_sdmmc_access_init(disk);
case DISK_IOCTL_CTRL_DEINIT:
- sdmmc_ioctl(&data->card, DISK_IOCTL_CTRL_SYNC, NULL);
- /* sd_init() will toggle power to SDMMC, so we can just mark
- * disk as uninitialized
- */
+ /* Card will be uninitialized after DEINIT */
data->status = SD_UNINIT;
- return 0;
+ return sdmmc_ioctl(&data->card, DISK_IOCTL_CTRL_DEINIT, NULL);
default:
return sdmmc_ioctl(&data->card, cmd, buf);
}
diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt
index 2122d0f..7f2aa6b 100644
--- a/drivers/display/CMakeLists.txt
+++ b/drivers/display/CMakeLists.txt
@@ -16,6 +16,7 @@
zephyr_library_sources_ifdef(CONFIG_MAX7219 display_max7219.c)
zephyr_library_sources_ifdef(CONFIG_OTM8009A display_otm8009a.c)
zephyr_library_sources_ifdef(CONFIG_SSD1306 ssd1306.c)
+zephyr_library_sources_ifdef(CONFIG_SSD1327 ssd1327.c)
zephyr_library_sources_ifdef(CONFIG_SSD16XX ssd16xx.c)
zephyr_library_sources_ifdef(CONFIG_ST7789V display_st7789v.c)
zephyr_library_sources_ifdef(CONFIG_ST7735R display_st7735r.c)
diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig
index 6c2cca4..5a05a79 100644
--- a/drivers/display/Kconfig
+++ b/drivers/display/Kconfig
@@ -26,6 +26,7 @@
source "drivers/display/Kconfig.ili9xxx"
source "drivers/display/Kconfig.sdl"
source "drivers/display/Kconfig.ssd1306"
+source "drivers/display/Kconfig.ssd1327"
source "drivers/display/Kconfig.ssd16xx"
source "drivers/display/Kconfig.st7735r"
source "drivers/display/Kconfig.st7789v"
diff --git a/drivers/display/Kconfig.ssd1327 b/drivers/display/Kconfig.ssd1327
new file mode 100644
index 0000000..1afd3d3
--- /dev/null
+++ b/drivers/display/Kconfig.ssd1327
@@ -0,0 +1,23 @@
+# SSD1327 display controller configuration options
+
+# Copyright (c) 2024 Savoir-faire Linux
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig SSD1327
+ bool "SSD1327 display driver"
+ default y
+ depends on DT_HAS_SOLOMON_SSD1327FB_ENABLED
+ select MIPI_DBI
+ help
+ Enable driver for SSD1327 display.
+
+if SSD1327
+
+config SSD1327_DEFAULT_CONTRAST
+ int "SSD1327 default contrast"
+ default 128
+ range 0 255
+ help
+ SSD1327 default contrast.
+
+endif # SSD1327
diff --git a/drivers/display/Kconfig.st7789v b/drivers/display/Kconfig.st7789v
index 61d9c54..f38cba1 100644
--- a/drivers/display/Kconfig.st7789v
+++ b/drivers/display/Kconfig.st7789v
@@ -24,4 +24,7 @@
config ST7789V_RGB565
bool "RGB565"
+config ST7789V_BGR565
+ bool "BGR565"
+
endchoice
diff --git a/drivers/display/display_sdl.c b/drivers/display/display_sdl.c
index e929a77..04370c8 100644
--- a/drivers/display/display_sdl.c
+++ b/drivers/display/display_sdl.c
@@ -534,7 +534,7 @@
DT_INST_FOREACH_STATUS_OKAY(DISPLAY_SDL_DEFINE)
-static void display_sdl_native_posix_options(void)
+static void display_sdl_options(void)
{
static struct args_struct_t sdl_display_options[] = {
{ .option = "display_zoom_pct",
@@ -551,4 +551,4 @@
native_add_command_line_opts(sdl_display_options);
}
-NATIVE_TASK(display_sdl_native_posix_options, PRE_BOOT_1, 1);
+NATIVE_TASK(display_sdl_options, PRE_BOOT_1, 1);
diff --git a/drivers/display/display_st7789v.c b/drivers/display/display_st7789v.c
index 69e4e2c..a98ecd5 100644
--- a/drivers/display/display_st7789v.c
+++ b/drivers/display/display_st7789v.c
@@ -52,10 +52,10 @@
uint16_t y_offset;
};
-#ifdef CONFIG_ST7789V_RGB565
-#define ST7789V_PIXEL_SIZE 2u
-#else
+#ifdef CONFIG_ST7789V_RGB888
#define ST7789V_PIXEL_SIZE 3u
+#else
+#define ST7789V_PIXEL_SIZE 2u
#endif
static void st7789v_set_lcd_margins(const struct device *dev,
@@ -164,6 +164,8 @@
}
if (IS_ENABLED(CONFIG_ST7789V_RGB565)) {
pixfmt = PIXEL_FORMAT_RGB_565;
+ } else if (IS_ENABLED(CONFIG_ST7789V_BGR565)) {
+ pixfmt = PIXEL_FORMAT_BGR_565;
} else {
pixfmt = PIXEL_FORMAT_RGB_888;
}
@@ -197,6 +199,9 @@
#ifdef CONFIG_ST7789V_RGB565
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565;
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565;
+#elif CONFIG_ST7789V_BGR565
+ capabilities->supported_pixel_formats = PIXEL_FORMAT_BGR_565;
+ capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
#else
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_888;
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_888;
@@ -209,6 +214,8 @@
{
#ifdef CONFIG_ST7789V_RGB565
if (pixel_format == PIXEL_FORMAT_RGB_565) {
+#elif CONFIG_ST7789V_BGR565
+ if (pixel_format == PIXEL_FORMAT_BGR_565) {
#else
if (pixel_format == PIXEL_FORMAT_RGB_888) {
#endif
diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
index 4581ea1..fdb4be9 100644
--- a/drivers/display/display_stm32_ltdc.c
+++ b/drivers/display/display_stm32_ltdc.c
@@ -17,6 +17,7 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/reset.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/cache.h>
@@ -73,6 +74,7 @@
struct gpio_dt_spec disp_on_gpio;
struct gpio_dt_spec bl_ctrl_gpio;
struct stm32_pclken pclken;
+ const struct reset_dt_spec reset;
const struct pinctrl_dev_config *pctrl;
void (*irq_config_func)(const struct device *dev);
const struct device *display_controller;
@@ -354,8 +356,7 @@
#endif
/* reset LTDC peripheral */
- __HAL_RCC_LTDC_FORCE_RESET();
- __HAL_RCC_LTDC_RELEASE_RESET();
+ (void)reset_line_toggle_dt(&config->reset);
data->current_pixel_format = DISPLAY_INIT_PIXEL_FORMAT;
data->current_pixel_size = STM32_LTDC_INIT_PIXEL_SIZE;
@@ -421,8 +422,7 @@
}
/* Reset LTDC peripheral registers */
- __HAL_RCC_LTDC_FORCE_RESET();
- __HAL_RCC_LTDC_RELEASE_RESET();
+ (void)reset_line_toggle_dt(&config->reset);
/* Turn off LTDC peripheral clock */
err = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
@@ -601,6 +601,7 @@
(GPIO_DT_SPEC_INST_GET(inst, disp_on_gpios)), ({ 0 })), \
.bl_ctrl_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, bl_ctrl_gpios), \
(GPIO_DT_SPEC_INST_GET(inst, bl_ctrl_gpios)), ({ 0 })), \
+ .reset = RESET_DT_SPEC_INST_GET(0), \
.pclken = { \
.enr = DT_INST_CLOCKS_CELL(inst, bits), \
.bus = DT_INST_CLOCKS_CELL(inst, bus) \
diff --git a/drivers/display/ssd1306.c b/drivers/display/ssd1306.c
index 6da20e2..4f3d6b8 100644
--- a/drivers/display/ssd1306.c
+++ b/drivers/display/ssd1306.c
@@ -107,7 +107,7 @@
static int ssd1306_write_bus_spi(const struct device *dev, uint8_t *buf, size_t len, bool command)
{
const struct ssd1306_config *config = dev->config;
- int errno;
+ int ret;
gpio_pin_set_dt(&config->data_cmd, command ? 0 : 1);
struct spi_buf tx_buf = {
@@ -120,9 +120,9 @@
.count = 1
};
- errno = spi_write_dt(&config->bus.spi, &tx_bufs);
+ ret = spi_write_dt(&config->bus.spi, &tx_bufs);
- return errno;
+ return ret;
}
static const char *ssd1306_bus_name_spi(const struct device *dev)
@@ -204,7 +204,7 @@
static inline int ssd1306_set_iref_mode(const struct device *dev)
{
- int errno = 0;
+ int ret = 0;
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {
SSD1306_SET_IREF_MODE,
@@ -212,10 +212,10 @@
};
if (config->use_internal_iref) {
- errno = ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+ ret = ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
- return errno;
+ return ret;
}
static int ssd1306_resume(const struct device *dev)
diff --git a/drivers/display/ssd1327.c b/drivers/display/ssd1327.c
new file mode 100644
index 0000000..65c9054
--- /dev/null
+++ b/drivers/display/ssd1327.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2024 Savoir-faire Linux
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ssd1327, CONFIG_DISPLAY_LOG_LEVEL);
+
+#include <string.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/display.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/mipi_dbi.h>
+#include <zephyr/kernel.h>
+
+#include "ssd1327_regs.h"
+
+#define SSD1327_ENABLE_VDD 0x01
+#define SSD1327_ENABLE_SECOND_PRECHARGE 0x62
+#define SSD1327_VCOMH_VOLTAGE 0x0f
+#define SSD1327_PHASES_VALUE 0xf1
+#define SSD1327_DEFAULT_PRECHARGE_V 0x08
+#define SSD1327_UNLOCK_COMMAND 0x12
+
+struct ssd1327_config {
+ const struct device *mipi_dev;
+ const struct mipi_dbi_config dbi_config;
+ uint16_t height;
+ uint16_t width;
+ uint8_t oscillator_freq;
+ uint8_t start_line;
+ uint8_t display_offset;
+ uint8_t multiplex_ratio;
+ uint8_t prechargep;
+ uint8_t remap_value;
+ bool color_inversion;
+};
+
+struct ssd1327_data {
+ uint8_t contrast;
+ uint8_t scan_mode;
+};
+
+static inline int ssd1327_write_bus_cmd(const struct device *dev, const uint8_t cmd,
+ const uint8_t *data, size_t len)
+{
+ const struct ssd1327_config *config = dev->config;
+ int err;
+
+ /* Values given after the memory register must be sent with pin D/C set to 0. */
+ /* Data is sent as a command following the mipi_cbi api */
+ err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, NULL, 0);
+ if (err) {
+ return err;
+ }
+ for (size_t i = 0; i < len; i++) {
+ err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
+ data[i], NULL, 0);
+ if (err) {
+ return err;
+ }
+ }
+ mipi_dbi_release(config->mipi_dev, &config->dbi_config);
+
+ return 0;
+}
+
+static inline int ssd1327_set_timing_setting(const struct device *dev)
+{
+ const struct ssd1327_config *config = dev->config;
+ uint8_t buf;
+
+ buf = SSD1327_PHASES_VALUE;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PHASE_LENGTH, &buf, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_OSC_FREQ, &config->oscillator_freq, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_PERIOD, &config->prechargep, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_LINEAR_LUT, NULL, 0)) {
+ return -EIO;
+ }
+ buf = SSD1327_DEFAULT_PRECHARGE_V;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_VOLTAGE, &buf, 1)) {
+ return -EIO;
+ }
+ buf = SSD1327_VCOMH_VOLTAGE;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_VCOMH, &buf, 1)) {
+ return -EIO;
+ }
+ buf = SSD1327_ENABLE_SECOND_PRECHARGE;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_FUNCTION_SELECTION_B, &buf, 1)) {
+ return -EIO;
+ }
+ buf = SSD1327_UNLOCK_COMMAND;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COMMAND_LOCK, &buf, 1)) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline int ssd1327_set_hardware_config(const struct device *dev)
+{
+ const struct ssd1327_config *config = dev->config;
+ uint8_t buf;
+
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_START_LINE, &config->start_line, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_OFFSET, &config->display_offset, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_NORMAL_DISPLAY, NULL, 0)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1)) {
+ return -EIO;
+ }
+ buf = SSD1327_ENABLE_VDD;
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_FUNCTION_A, &buf, 1)) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int ssd1327_resume(const struct device *dev)
+{
+ return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_ON, NULL, 0);
+}
+
+static int ssd1327_suspend(const struct device *dev)
+{
+ return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_OFF, NULL, 0);
+}
+
+static int ssd1327_set_display(const struct device *dev)
+{
+ const struct ssd1327_config *config = dev->config;
+ uint8_t x_position[] = {
+ 0,
+ config->width - 1
+ };
+ uint8_t y_position[] = {
+ 0,
+ config->height - 1
+ };
+
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position))) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position))) {
+ return -EIO;
+ }
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int ssd1327_write(const struct device *dev, const uint16_t x, const uint16_t y,
+ const struct display_buffer_descriptor *desc, const void *buf)
+{
+ const struct ssd1327_config *config = dev->config;
+ struct display_buffer_descriptor mipi_desc;
+ int err;
+ size_t buf_len;
+ uint8_t x_position[] = { x, x + desc->width - 1 };
+ uint8_t y_position[] = { y, y + desc->height - 1 };
+
+ if (desc->pitch < desc->width) {
+ LOG_ERR("Pitch is smaller than width");
+ return -1;
+ }
+ mipi_desc.pitch = desc->pitch;
+
+ /* Following the datasheet, in the GDDRAM, two segment are split in one register */
+ buf_len = MIN(desc->buf_size, desc->height * desc->width / 2);
+ if (buf == NULL || buf_len == 0U) {
+ LOG_ERR("Display buffer is not available");
+ return -1;
+ }
+ mipi_desc.buf_size = buf_len;
+
+ if (desc->pitch > desc->width) {
+ LOG_ERR("Unsupported mode");
+ return -1;
+ }
+
+ if ((y & 0x7) != 0U) {
+ LOG_ERR("Unsupported origin");
+ return -1;
+ }
+ mipi_desc.height = desc->height;
+ mipi_desc.width = desc->width;
+
+ LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch,
+ desc->width, desc->height, buf_len);
+
+ err = ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position));
+ if (err) {
+ return err;
+ }
+
+ err = ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position));
+ if (err) {
+ return err;
+ }
+
+ err = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc,
+ PIXEL_FORMAT_MONO10);
+ if (err) {
+ return err;
+ }
+ return mipi_dbi_release(config->mipi_dev, &config->dbi_config);
+}
+
+static int ssd1327_set_contrast(const struct device *dev, const uint8_t contrast)
+{
+ return ssd1327_write_bus_cmd(dev, SSD1327_SET_CONTRAST_CTRL, &contrast, 1);
+}
+
+static void ssd1327_get_capabilities(const struct device *dev,
+ struct display_capabilities *caps)
+{
+ const struct ssd1327_config *config = dev->config;
+
+ memset(caps, 0, sizeof(struct display_capabilities));
+ caps->x_resolution = config->width;
+ caps->y_resolution = config->height;
+ caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
+ caps->current_pixel_format = PIXEL_FORMAT_MONO10;
+ caps->screen_info = SCREEN_INFO_MONO_VTILED;
+}
+
+static int ssd1327_set_pixel_format(const struct device *dev,
+ const enum display_pixel_format pf)
+{
+ if (pf == PIXEL_FORMAT_MONO10) {
+ return 0;
+ }
+ LOG_ERR("Unsupported pixel format");
+ return -ENOTSUP;
+}
+
+static int ssd1327_init_device(const struct device *dev)
+{
+ const struct ssd1327_config *config = dev->config;
+ uint8_t buf;
+
+ /* Turn display off */
+ if (ssd1327_suspend(dev)) {
+ return -EIO;
+ }
+
+ if (ssd1327_set_display(dev)) {
+ return -EIO;
+ }
+
+ if (ssd1327_set_contrast(dev, CONFIG_SSD1327_DEFAULT_CONTRAST)) {
+ return -EIO;
+ }
+
+ if (ssd1327_set_hardware_config(dev)) {
+ return -EIO;
+ }
+
+ buf = (config->color_inversion ?
+ SSD1327_SET_REVERSE_DISPLAY : SSD1327_SET_NORMAL_DISPLAY);
+ if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ENTIRE_DISPLAY_OFF, &buf, 1)) {
+ return -EIO;
+ }
+
+ if (ssd1327_set_timing_setting(dev)) {
+ return -EIO;
+ }
+
+ if (ssd1327_resume(dev)) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int ssd1327_init(const struct device *dev)
+{
+ const struct ssd1327_config *config = dev->config;
+
+ LOG_DBG("Initializing device");
+
+ if (!device_is_ready(config->mipi_dev)) {
+ LOG_ERR("MIPI Device not ready!");
+ return -EINVAL;
+ }
+
+ if (mipi_dbi_reset(config->mipi_dev, SSD1327_RESET_DELAY)) {
+ LOG_ERR("Failed to reset device!");
+ return -EIO;
+ }
+ k_msleep(SSD1327_RESET_DELAY);
+
+ if (ssd1327_init_device(dev)) {
+ LOG_ERR("Failed to initialize device!");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static struct display_driver_api ssd1327_driver_api = {
+ .blanking_on = ssd1327_suspend,
+ .blanking_off = ssd1327_resume,
+ .write = ssd1327_write,
+ .set_contrast = ssd1327_set_contrast,
+ .get_capabilities = ssd1327_get_capabilities,
+ .set_pixel_format = ssd1327_set_pixel_format,
+};
+
+#define SSD1327_DEFINE(node_id) \
+ static struct ssd1327_data data##node_id; \
+ static const struct ssd1327_config config##node_id = { \
+ .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \
+ .dbi_config = { .mode = MIPI_DBI_MODE_SPI_4WIRE, \
+ .config = MIPI_DBI_SPI_CONFIG_DT(node_id, \
+ SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \
+ SPI_HOLD_ON_CS | SPI_LOCK_ON, 0), \
+ }, \
+ .height = DT_PROP(node_id, height), \
+ .width = DT_PROP(node_id, width), \
+ .oscillator_freq = DT_PROP(node_id, oscillator_freq), \
+ .display_offset = DT_PROP(node_id, display_offset), \
+ .start_line = DT_PROP(node_id, start_line), \
+ .multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \
+ .prechargep = DT_PROP(node_id, prechargep), \
+ .remap_value = DT_PROP(node_id, remap_value), \
+ .color_inversion = DT_PROP(node_id, inversion_on), \
+ }; \
+ \
+ DEVICE_DT_DEFINE(node_id, ssd1327_init, NULL, &data##node_id, &config##node_id, \
+ POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1327_driver_api);
+
+DT_FOREACH_STATUS_OKAY(solomon_ssd1327fb, SSD1327_DEFINE)
diff --git a/drivers/display/ssd1327_regs.h b/drivers/display/ssd1327_regs.h
new file mode 100644
index 0000000..443a137
--- /dev/null
+++ b/drivers/display/ssd1327_regs.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Savoir-faire Linux
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SSD1327_REGS_H__
+#define __SSD1327_REGS_H__
+
+/*
+ * Fundamental Command Table
+ */
+#define SSD1327_SET_COLUMN_ADDR 0x15
+#define SSD1327_SET_ROW_ADDR 0x75
+
+#define SSD1327_SET_CONTRAST_CTRL 0x81
+
+#define SSD1327_SET_SEGMENT_MAP_REMAPED 0xa0
+#define SSD1327_SET_DISPLAY_START_LINE 0xa1
+#define SSD1327_SET_DISPLAY_OFFSET 0xa2
+
+#define SSD1327_SET_NORMAL_DISPLAY 0xa4
+#define SSD1327_SET_ENTIRE_DISPLAY_ON 0xa5
+#define SSD1327_SET_ENTIRE_DISPLAY_OFF 0xa6
+#define SSD1327_SET_REVERSE_DISPLAY 0xa7
+#define SSD1327_SET_MULTIPLEX_RATIO 0xa8
+
+#define SSD1327_DISPLAY_OFF 0xae
+#define SSD1327_DISPLAY_ON 0xaf
+
+#define SSD1327_SET_FUNCTION_A 0xab
+#define SSD1327_SET_PHASE_LENGTH 0xb1
+#define SSD1327_SET_OSC_FREQ 0xb3
+#define SSD1327_SET_PRECHARGE_PERIOD 0xb6
+#define SSD1327_FUNCTION_SELECTION_B 0xd5
+
+#define SSD1327_LINEAR_LUT 0xb9
+
+#define SSD1327_SET_PRECHARGE_VOLTAGE 0xbc
+#define SSD1327_SET_VCOMH 0xbe
+
+
+#define SSD1327_SET_COMMAND_LOCK 0xfd
+
+/* Time constant in ms */
+#define SSD1327_RESET_DELAY 10
+
+#endif
diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt
index d84aea9..60fcdcc 100644
--- a/drivers/dma/CMakeLists.txt
+++ b/drivers/dma/CMakeLists.txt
@@ -42,3 +42,4 @@
zephyr_library_sources_ifdef(CONFIG_DMA_NXP_SOF_HOST_DMA dma_nxp_sof_host_dma.c)
zephyr_library_sources_ifdef(CONFIG_DMA_EMUL dma_emul.c)
zephyr_library_sources_ifdef(CONFIG_DMA_NXP_EDMA dma_nxp_edma.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_DW_AXI dma_dw_axi.c)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 7a49b6e..3b62808 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -78,4 +78,6 @@
source "drivers/dma/Kconfig.nxp_edma"
+source "drivers/dma/Kconfig.dw_axi_dmac"
+
endif # DMA
diff --git a/drivers/dma/Kconfig.dw_axi_dmac b/drivers/dma/Kconfig.dw_axi_dmac
new file mode 100644
index 0000000..758486a
--- /dev/null
+++ b/drivers/dma/Kconfig.dw_axi_dmac
@@ -0,0 +1,53 @@
+# DesignWare DMA configuration options
+
+# Copyright (c) 2023 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_DW_AXI
+ bool "DesignWare AXI DMA driver"
+ default y
+ depends on DT_HAS_SNPS_DESIGNWARE_DMA_AXI_ENABLED
+ imply DMA_64BIT
+ help
+ DesignWare AXI DMA driver.
+
+if DMA_DW_AXI
+
+config DMA_DW_AXI_MAX_DESC
+ int "allocate number of lli descriptor"
+ default 10
+ help
+ creates number of descriptor per channel in a statically allocated pool.
+ Each channel has its own dedicated pool.
+
+config DMA_DW_AXI_LLI_SUPPORT
+ bool "hardware supports linked list multi block transfer"
+ default y
+ help
+ This flag can be enabled if hardware support Linked List multi-block transfer
+
+config DMA_CHANNEL_STATUS_TIMEOUT
+ int "Channel status timeout"
+ default 1000
+ help
+ Max timeout to abort or disable the channel
+
+config DMA_DW_AXI_MAX_BURST_TXN_LEN
+ int "max burst transaction length"
+ default 8
+ help
+ set max number of source and destination data units supported
+
+config DMA_DW_AXI_DATA_WIDTH
+ int "data bus width"
+ default 64
+ help
+ update this flag to change the axi master interface data width
+
+config DMA_DW_AXI_MAX_BLOCK_TS
+ int "max block size"
+ default 32767
+ help
+ update this config to set maximum value of block size
+
+endif # DMA_DW_AXI
diff --git a/drivers/dma/dma_dw_axi.c b/drivers/dma/dma_dw_axi.c
new file mode 100644
index 0000000..917f700
--- /dev/null
+++ b/drivers/dma/dma_dw_axi.c
@@ -0,0 +1,912 @@
+/*
+ * Copyright (c) 2023 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT snps_designware_dma_axi
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/cache.h>
+
+LOG_MODULE_REGISTER(dma_designware_axi, CONFIG_DMA_LOG_LEVEL);
+
+#define DEV_CFG(_dev) ((const struct dma_dw_axi_dev_cfg *)(_dev)->config)
+#define DEV_DATA(_dev) ((struct dma_dw_axi_dev_data *const)(_dev)->data)
+
+/* mask for block transfer size */
+#define BLOCK_TS_MASK GENMASK(21, 0)
+
+/* blen : number of data units
+ * blen will always be in power of two
+ *
+ * when blen is 1 then set msize to zero otherwise find most significant bit set
+ * and subtract two (as IP doesn't support number of data items 2)
+ */
+#define DMA_DW_AXI_GET_MSIZE(blen) ((blen == 1) ? (0U) : (find_msb_set(blen) - 2U))
+
+/* Common_Registers_Address_Block */
+#define DMA_DW_AXI_IDREG 0x0
+#define DMA_DW_AXI_COMPVERREG 0x08
+#define DMA_DW_AXI_CFGREG 0x10
+#define DMA_DW_AXI_CHENREG 0x18
+#define DMA_DW_AXI_INTSTATUSREG 0x30
+#define DMA_DW_AXI_COMMONREG_INTCLEARREG 0x38
+#define DMA_DW_AXI_COMMONREG_INTSTATUS_ENABLEREG 0x40
+#define DMA_DW_AXI_COMMONREG_INTSIGNAL_ENABLEREG 0x48
+#define DMA_DW_AXI_COMMONREG_INTSTATUSREG 0x50
+#define DMA_DW_AXI_RESETREG 0x58
+#define DMA_DW_AXI_LOWPOWER_CFGREG 0x60
+
+/* Channel enable by setting ch_en and ch_en_we */
+#define CH_EN(chan) (BIT64(8 + chan) | BIT64(chan))
+/* Channel enable by setting ch_susp and ch_susp_we */
+#define CH_SUSP(chan) (BIT64(24 + chan) | BIT64(16 + chan))
+/* Channel enable by setting ch_abort and ch_abort_we */
+#define CH_ABORT(chan) (BIT64(40 + chan) | BIT64(32 + chan))
+
+/* channel susp/resume write enable pos */
+#define CH_RESUME_WE(chan) (BIT64(24 + chan))
+/* channel resume bit pos */
+#define CH_RESUME(chan) (BIT64(16 + chan))
+
+#define DMA_DW_AXI_CHAN_OFFSET(chan) (0x100 * chan)
+
+/* source address register for a channel */
+#define DMA_DW_AXI_CH_SAR(chan) (0x100 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* destination address register for a channel */
+#define DMA_DW_AXI_CH_DAR(chan) (0x108 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* block transfer size register for a channel */
+#define DMA_DW_AXI_CH_BLOCK_TS(chan) (0x110 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel control register */
+#define DMA_DW_AXI_CH_CTL(chan) (0x118 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel configuration register */
+#define DMA_DW_AXI_CH_CFG(chan) (0x120 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* linked list pointer register */
+#define DMA_DW_AXI_CH_LLP(chan) (0x128 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel status register */
+#define DMA_DW_AXI_CH_STATUSREG(chan) (0x130 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel software handshake source register */
+#define DMA_DW_AXI_CH_SWHSSRCREG(chan) (0x138 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel software handshake destination register */
+#define DMA_DW_AXI_CH_SWHSDSTREG(chan) (0x140 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel block transfer resume request register */
+#define DMA_DW_AXI_CH_BLK_TFR_RESUMEREQREG(chan) (0x148 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel AXI ID rester */
+#define DMA_DW_AXI_CH_AXI_IDREG(chan) (0x150 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel AXI QOS register */
+#define DMA_DW_AXI_CH_AXI_QOSREG(chan) (0x158 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel interrupt status enable register */
+#define DMA_DW_AXI_CH_INTSTATUS_ENABLEREG(chan) (0x180 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel interrupt status register */
+#define DMA_DW_AXI_CH_INTSTATUS(chan) (0x188 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel interrupt signal enable register */
+#define DMA_DW_AXI_CH_INTSIGNAL_ENABLEREG(chan) (0x190 + DMA_DW_AXI_CHAN_OFFSET(chan))
+/* channel interrupt clear register */
+#define DMA_DW_AXI_CH_INTCLEARREG(chan) (0x198 + DMA_DW_AXI_CHAN_OFFSET(chan))
+
+/* bitfield configuration for multi-block transfer */
+#define DMA_DW_AXI_CFG_SRC_MULTBLK_TYPE(x) FIELD_PREP(GENMASK64(1, 0), x)
+#define DMA_DW_AXI_CFG_DST_MULTBLK_TYPE(x) FIELD_PREP(GENMASK64(3, 2), x)
+
+/* bitfield configuration to assign handshaking interface to source and destination */
+#define DMA_DW_AXI_CFG_SRC_PER(x) FIELD_PREP(GENMASK64(9, 4), x)
+#define DMA_DW_AXI_CFG_DST_PER(x) FIELD_PREP(GENMASK64(16, 11), x)
+
+/* bitfield configuration for transfer type and flow controller */
+#define DMA_DW_AXI_CFG_TT_FC(x) FIELD_PREP(GENMASK64(34, 32), x)
+
+#define DMA_DW_AXI_CFG_HW_HS_SRC_BIT_POS 35
+#define DMA_DW_AXI_CFG_HW_HS_DST_BIT_POS 36
+
+#define DMA_DW_AXI_CFG_PRIORITY(x) FIELD_PREP(GENMASK64(51, 47), x)
+
+/* descriptor valid or not */
+#define DMA_DW_AXI_CTL_LLI_VALID BIT64(63)
+/* descriptor is last or not in a link */
+#define DMA_DW_AXI_CTL_LLI_LAST BIT64(62)
+/* interrupt on completion of block transfer */
+#define DMA_DW_AXI_CTL_IOC_BLK_TFR BIT64(58)
+/* source status enable bit */
+#define DMA_DW_AXI_CTL_SRC_STAT_EN BIT64(56)
+/* destination status enable bit */
+#define DMA_DW_AXI_CTL_DST_STAT_EN BIT64(57)
+/* source burst length enable */
+#define DMA_DW_AXI_CTL_ARLEN_EN BIT64(38)
+/* source burst length(considered when corresponding enable bit is set) */
+#define DMA_DW_AXI_CTL_ARLEN(x) FIELD_PREP(GENMASK64(46, 39), x)
+/* destination burst length enable */
+#define DMA_DW_AXI_CTL_AWLEN_EN BIT64(47)
+/* destination burst length(considered when corresponding enable bit is set) */
+#define DMA_DW_AXI_CTL_AWLEN(x) FIELD_PREP(GENMASK64(55, 48), x)
+
+/* source burst transaction length */
+#define DMA_DW_AXI_CTL_SRC_MSIZE(x) FIELD_PREP(GENMASK64(17, 14), x)
+/* destination burst transaction length */
+#define DMA_DW_AXI_CTL_DST_MSIZE(x) FIELD_PREP(GENMASK64(21, 18), x)
+/* source transfer width */
+#define DMA_DW_AXI_CTL_SRC_WIDTH(x) FIELD_PREP(GENMASK64(10, 8), x)
+/* destination transfer width */
+#define DMA_DW_AXI_CTL_DST_WIDTH(x) FIELD_PREP(GENMASK64(13, 11), x)
+
+/* mask all the interrupts */
+#define DMA_DW_AXI_IRQ_NONE 0
+/* enable block completion transfer interrupt */
+#define DMA_DW_AXI_IRQ_BLOCK_TFR BIT64(0)
+/* enable transfer completion interrupt */
+#define DMA_DW_AXI_IRQ_DMA_TFR BIT64(1)
+/* enable interrupts on any dma transfer error */
+#define DMA_DW_AXI_IRQ_ALL_ERR (GENMASK64(14, 5) | GENMASK64(21, 16))
+
+/* global enable bit for dma controller */
+#define DMA_DW_AXI_CFG_EN BIT64(0)
+/* global enable bit for interrupt */
+#define DMA_DW_AXI_CFG_INT_EN BIT64(1)
+
+/* descriptor used by dw axi dma controller*/
+struct dma_lli {
+ uint64_t sar;
+ uint64_t dar;
+ uint32_t block_ts_lo;
+ uint32_t reserved;
+ uint64_t llp;
+ uint64_t ctl;
+ uint32_t sstat;
+ uint32_t dstat;
+ uint64_t llp_status;
+ uint64_t reserved1;
+} __aligned(64);
+
+/* status of the channel */
+enum dma_dw_axi_ch_state {
+ DMA_DW_AXI_CH_IDLE,
+ DMA_DW_AXI_CH_SUSPENDED,
+ DMA_DW_AXI_CH_ACTIVE,
+ DMA_DW_AXI_CH_PREPARED,
+};
+
+/* source and destination transfer width */
+enum dma_dw_axi_ch_width {
+ BITS_8,
+ BITS_16,
+ BITS_32,
+ BITS_64,
+ BITS_128,
+ BITS_256,
+ BITS_512,
+};
+
+/* transfer direction and flow controller */
+enum dma_dw_axi_tt_fc {
+ M2M_DMAC,
+ M2P_DMAC,
+ P2M_DMAC,
+ P2P_DMAC,
+ P2M_SRC,
+ P2P_SRC,
+ M2P_DST,
+ P2P_DST,
+};
+
+/* type of multi-block transfer */
+enum dma_dw_axi_multi_blk_type {
+ MULTI_BLK_CONTIGUOUS,
+ MULTI_BLK_RELOAD,
+ MULTI_BLK_SHADOW_REG,
+ MULTI_BLK_LLI,
+};
+
+/* dma driver channel specific information */
+struct dma_dw_axi_ch_data {
+ /* lli descriptor base */
+ struct dma_lli *lli_desc_base;
+ /* lli current descriptor */
+ struct dma_lli *lli_desc_current;
+ /* dma channel state */
+ enum dma_dw_axi_ch_state ch_state;
+ /* direction of transfer */
+ uint32_t direction;
+ /* number of descriptors */
+ uint32_t lli_desc_count;
+ /* cfg register configuration for dma transfer */
+ uint64_t cfg;
+ /* mask and unmask interrupts */
+ uint64_t irq_unmask;
+ /* user call back for dma transfer completion */
+ dma_callback_t dma_xfer_callback;
+ /* user data for dma callback for dma transfer completion */
+ void *priv_data_xfer;
+ /* user call back for dma block transfer completion */
+ dma_callback_t dma_blk_xfer_callback;
+ /* user data for dma callback for dma block transfer completion */
+ void *priv_data_blk_tfr;
+};
+
+/* dma controller driver data structure */
+struct dma_dw_axi_dev_data {
+ /* dma context */
+ struct dma_context dma_ctx;
+
+ /* mmio address mapping info for dma controller */
+ DEVICE_MMIO_NAMED_RAM(dma_mmio);
+ /* pointer to store channel specific info */
+ struct dma_dw_axi_ch_data *chan;
+ /* pointer to hold descriptor base address */
+ struct dma_lli *dma_desc_pool;
+};
+
+/* Device constant configuration parameters */
+struct dma_dw_axi_dev_cfg {
+ /* dma address space to map */
+ DEVICE_MMIO_NAMED_ROM(dma_mmio);
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
+ /* Reset controller device configurations */
+ const struct reset_dt_spec reset;
+#endif
+ /* dma controller interrupt configuration function pointer */
+ void (*irq_config)(void);
+};
+
+/**
+ * @brief get current status of the channel
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param channel channel number
+ *
+ * @retval status of the channel
+ */
+static enum dma_dw_axi_ch_state dma_dw_axi_get_ch_status(const struct device *dev, uint32_t ch)
+{
+ uint32_t bit_status;
+ uint64_t ch_status;
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+
+ ch_status = sys_read64(reg_base + DMA_DW_AXI_CHENREG);
+
+ /* channel is active/busy in the dma transfer */
+ bit_status = ((ch_status >> ch) & 1);
+ if (bit_status) {
+ return DMA_DW_AXI_CH_ACTIVE;
+ }
+
+ /* channel is currently suspended */
+ bit_status = ((ch_status >> (16 + ch)) & 1);
+ if (bit_status) {
+ return DMA_DW_AXI_CH_SUSPENDED;
+ }
+
+ /* channel is idle */
+ return DMA_DW_AXI_CH_IDLE;
+}
+
+static void dma_dw_axi_isr(const struct device *dev)
+{
+ unsigned int channel;
+ uint64_t status, ch_status;
+ int ret_status = 0;
+ struct dma_dw_axi_ch_data *chan_data;
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+
+ /* read interrupt status register to find interrupt is for which channel */
+ status = sys_read64(reg_base + DMA_DW_AXI_INTSTATUSREG);
+ channel = find_lsb_set(status) - 1;
+ if (channel < 0) {
+ LOG_ERR("Spurious interrupt received channel:%u\n", channel);
+ return;
+ }
+
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("Interrupt received on invalid channel:%d\n", channel);
+ return;
+ }
+
+ /* retrieve channel specific data pointer for a channel */
+ chan_data = &dw_dev_data->chan[channel];
+
+ /* get dma transfer status */
+ ch_status = sys_read64(reg_base + DMA_DW_AXI_CH_INTSTATUS(channel));
+ if (!ch_status) {
+ LOG_ERR("Spurious interrupt received ch_status:0x%llx\n", ch_status);
+ return;
+ }
+
+ /* handle dma transfer errors if any */
+ if (ch_status & DMA_DW_AXI_IRQ_ALL_ERR) {
+ sys_write64(DMA_DW_AXI_IRQ_ALL_ERR,
+ reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));
+ LOG_ERR("DMA Error: Channel:%d Channel interrupt status:0x%llx\n",
+ channel, ch_status);
+ ret_status = -(ch_status & DMA_DW_AXI_IRQ_ALL_ERR);
+ }
+
+ /* handle block transfer completion */
+ if (ch_status & DMA_DW_AXI_IRQ_BLOCK_TFR) {
+ sys_write64(DMA_DW_AXI_IRQ_ALL_ERR | DMA_DW_AXI_IRQ_BLOCK_TFR,
+ reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));
+
+ if (chan_data->dma_blk_xfer_callback) {
+ chan_data->dma_blk_xfer_callback(dev,
+ chan_data->priv_data_blk_tfr, channel, ret_status);
+ }
+ }
+
+ /* handle dma transfer completion */
+ if (ch_status & DMA_DW_AXI_IRQ_DMA_TFR) {
+ sys_write64(DMA_DW_AXI_IRQ_ALL_ERR | DMA_DW_AXI_IRQ_DMA_TFR,
+ reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));
+
+ if (chan_data->dma_xfer_callback) {
+ chan_data->dma_xfer_callback(dev, chan_data->priv_data_xfer,
+ channel, ret_status);
+ chan_data->ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ }
+ }
+}
+
+/**
+ * @brief set data source and destination data width
+ *
+ * @param lli_desc Pointer to the descriptor
+ * @param src_data_width source data width
+ * @param dest_data_width destination data width
+ *
+ * @retval 0 on success, -ENOTSUP if the data width is not supported
+ */
+static int dma_dw_axi_set_data_width(struct dma_lli *lli_desc,
+ uint32_t src_data_width, uint32_t dest_data_width)
+{
+ if (src_data_width > CONFIG_DMA_DW_AXI_DATA_WIDTH ||
+ dest_data_width > CONFIG_DMA_DW_AXI_DATA_WIDTH) {
+ LOG_ERR("transfer width more than %u not supported", CONFIG_DMA_DW_AXI_DATA_WIDTH);
+ return -ENOTSUP;
+ }
+
+ switch (src_data_width) {
+ case 1:
+ /* one byte transfer */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_8);
+ break;
+ case 2:
+ /* 2-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_16);
+ break;
+ case 4:
+ /* 4-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_32);
+ break;
+ case 8:
+ /* 8-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_64);
+ break;
+ case 16:
+ /* 16-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_128);
+ break;
+ case 32:
+ /* 32-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_256);
+ break;
+ case 64:
+ /* 64-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_512);
+ break;
+ default:
+ LOG_ERR("Source transfer width not supported");
+ return -ENOTSUP;
+ }
+
+ switch (dest_data_width) {
+ case 1:
+ /* one byte transfer */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_8);
+ break;
+ case 2:
+ /* 2-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_16);
+ break;
+ case 4:
+ /* 4-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_32);
+ break;
+ case 8:
+ /* 8-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_64);
+ break;
+ case 16:
+ /* 16-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_128);
+ break;
+ case 32:
+ /* 32-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_256);
+ break;
+ case 64:
+ /* 64-bytes transfer width */
+ lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_512);
+ break;
+ default:
+ LOG_ERR("Destination transfer width not supported");
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+static int dma_dw_axi_config(const struct device *dev, uint32_t channel,
+ struct dma_config *cfg)
+{
+ int ret;
+ uint32_t msize_src, msize_dst, i, ch_state;
+ struct dma_dw_axi_ch_data *chan_data;
+ struct dma_block_config *blk_cfg;
+ struct dma_lli *lli_desc;
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+
+ /* check for invalid parameters before dereferencing them. */
+ if (cfg == NULL) {
+ LOG_ERR("invalid dma config :%p", cfg);
+ return -ENODATA;
+ }
+
+ /* check if the channel is valid */
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("invalid dma channel %d", channel);
+ return -EINVAL;
+ }
+
+ /* return if the channel is not idle */
+ ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ if (ch_state != DMA_DW_AXI_CH_IDLE) {
+ LOG_ERR("DMA channel:%d is not idle(status:%d)", channel, ch_state);
+ return -EBUSY;
+ }
+
+ if (!cfg->block_count) {
+ LOG_ERR("no blocks to transfer");
+ return -EINVAL;
+ }
+
+ /* descriptor should be less than max configured descriptor */
+ if (cfg->block_count > CONFIG_DMA_DW_AXI_MAX_DESC) {
+ LOG_ERR("dma:%s channel %d descriptor block count: %d larger than"
+ " max descriptors in pool: %d", dev->name, channel,
+ cfg->block_count, CONFIG_DMA_DW_AXI_MAX_DESC);
+ return -EINVAL;
+ }
+
+ if (cfg->source_burst_length > CONFIG_DMA_DW_AXI_MAX_BURST_TXN_LEN ||
+ cfg->dest_burst_length > CONFIG_DMA_DW_AXI_MAX_BURST_TXN_LEN ||
+ cfg->source_burst_length == 0 || cfg->dest_burst_length == 0) {
+ LOG_ERR("dma:%s burst length not supported", dev->name);
+ return -ENOTSUP;
+ }
+
+ /* get channel specific data pointer */
+ chan_data = &dw_dev_data->chan[channel];
+
+ /* check if the channel is currently idle */
+ if (chan_data->ch_state != DMA_DW_AXI_CH_IDLE) {
+ LOG_ERR("DMA channel:%d is busy", channel);
+ return -EBUSY;
+ }
+
+ /* burst transaction length for source and destination */
+ msize_src = DMA_DW_AXI_GET_MSIZE(cfg->source_burst_length);
+ msize_dst = DMA_DW_AXI_GET_MSIZE(cfg->dest_burst_length);
+
+ chan_data->cfg = 0;
+ chan_data->irq_unmask = 0;
+
+ chan_data->direction = cfg->channel_direction;
+
+ chan_data->lli_desc_base =
+ &dw_dev_data->dma_desc_pool[channel * CONFIG_DMA_DW_AXI_MAX_DESC];
+ chan_data->lli_desc_count = cfg->block_count;
+ memset(chan_data->lli_desc_base, 0,
+ sizeof(struct dma_lli) * chan_data->lli_desc_count);
+
+ lli_desc = chan_data->lli_desc_base;
+ blk_cfg = cfg->head_block;
+
+ /* max channel priority can be MAX_CHANNEL - 1 */
+ if (cfg->channel_priority < dw_dev_data->dma_ctx.dma_channels) {
+ chan_data->cfg |= DMA_DW_AXI_CFG_PRIORITY(cfg->channel_priority);
+ }
+
+ /* configure all the descriptors in a loop */
+ for (i = 0; i < cfg->block_count; i++) {
+
+ ret = dma_dw_axi_set_data_width(lli_desc, cfg->source_data_size,
+ cfg->dest_data_size);
+ if (ret) {
+ return ret;
+ }
+
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_STAT_EN |
+ DMA_DW_AXI_CTL_DST_STAT_EN | DMA_DW_AXI_CTL_IOC_BLK_TFR;
+
+ lli_desc->sar = blk_cfg->source_address;
+ lli_desc->dar = blk_cfg->dest_address;
+
+ /* set block transfer size*/
+ lli_desc->block_ts_lo = (blk_cfg->block_size / cfg->source_data_size) - 1;
+ if (lli_desc->block_ts_lo > CONFIG_DMA_DW_AXI_MAX_BLOCK_TS) {
+ LOG_ERR("block transfer size more than %u not supported",
+ CONFIG_DMA_DW_AXI_MAX_BLOCK_TS);
+ return -ENOTSUP;
+ }
+
+ /* configuration based on channel direction */
+ if (cfg->channel_direction == MEMORY_TO_MEMORY) {
+ chan_data->cfg |= DMA_DW_AXI_CFG_TT_FC(M2M_DMAC);
+
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |
+ DMA_DW_AXI_CTL_DST_MSIZE(msize_dst);
+
+ } else if (cfg->channel_direction == MEMORY_TO_PERIPHERAL) {
+
+ chan_data->cfg |= DMA_DW_AXI_CFG_TT_FC(M2P_DMAC);
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |
+ DMA_DW_AXI_CTL_DST_MSIZE(msize_dst);
+ WRITE_BIT(chan_data->cfg, DMA_DW_AXI_CFG_HW_HS_DST_BIT_POS, 0);
+
+ /* assign a hardware handshake interface */
+ chan_data->cfg |= DMA_DW_AXI_CFG_DST_PER(cfg->dma_slot);
+
+ } else if (cfg->channel_direction == PERIPHERAL_TO_MEMORY) {
+ lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |
+ DMA_DW_AXI_CTL_DST_MSIZE(msize_dst);
+ chan_data->cfg |= DMA_DW_AXI_CFG_TT_FC(P2M_DMAC);
+ WRITE_BIT(chan_data->cfg, DMA_DW_AXI_CFG_HW_HS_SRC_BIT_POS, 0);
+
+ /* assign a hardware handshake interface */
+ chan_data->cfg |= DMA_DW_AXI_CFG_SRC_PER(cfg->dma_slot);
+
+ } else {
+ LOG_ERR("%s: dma %s channel %d invalid direction %d",
+ __func__, dev->name, channel, cfg->channel_direction);
+
+ return -EINVAL;
+ }
+
+ /* set pointer to the next descriptor */
+ lli_desc->llp = ((uint64_t)(lli_desc + 1));
+
+#if defined(CONFIG_DMA_DW_AXI_LLI_SUPPORT)
+ /* configure multi block transfer size as linked list */
+ chan_data->cfg |= DMA_DW_AXI_CFG_SRC_MULTBLK_TYPE(MULTI_BLK_LLI) |
+ DMA_DW_AXI_CFG_DST_MULTBLK_TYPE(MULTI_BLK_LLI);
+
+ lli_desc->ctl |= DMA_DW_AXI_CTL_LLI_VALID;
+ /* last descriptor*/
+ if ((i + 1) == chan_data->lli_desc_count) {
+ lli_desc->ctl |= DMA_DW_AXI_CTL_LLI_LAST | DMA_DW_AXI_CTL_LLI_VALID;
+ lli_desc->llp = 0;
+ }
+#else
+ /* configure multi-block transfer as contiguous mode */
+ chan_data->cfg |= DMA_DW_AXI_CFG_SRC_MULTBLK_TYPE(MULTI_BLK_CONTIGUOUS) |
+ DMA_DW_AXI_CFG_DST_MULTBLK_TYPE(MULTI_BLK_CONTIGUOUS);
+#endif
+
+ /* next descriptor to configure*/
+ lli_desc++;
+ blk_cfg = blk_cfg->next_block;
+ }
+
+ arch_dcache_flush_range((void *)chan_data->lli_desc_base,
+ sizeof(struct dma_lli) * cfg->block_count);
+
+ chan_data->lli_desc_current = chan_data->lli_desc_base;
+
+ /* enable an interrupt depending on whether the callback is requested after dma transfer
+ * completion or dma block transfer completion
+ *
+ * disable an interrupt if callback is not requested
+ */
+ if (cfg->dma_callback && cfg->complete_callback_en) {
+ chan_data->dma_blk_xfer_callback = cfg->dma_callback;
+ chan_data->priv_data_blk_tfr = cfg->user_data;
+
+ chan_data->irq_unmask = DMA_DW_AXI_IRQ_BLOCK_TFR | DMA_DW_AXI_IRQ_DMA_TFR;
+ } else if (cfg->dma_callback && !cfg->complete_callback_en) {
+ chan_data->dma_xfer_callback = cfg->dma_callback;
+ chan_data->priv_data_xfer = cfg->user_data;
+
+ chan_data->irq_unmask = DMA_DW_AXI_IRQ_DMA_TFR;
+ } else {
+ chan_data->irq_unmask = DMA_DW_AXI_IRQ_NONE;
+ }
+
+ /* unmask error interrupts when error_callback_dis is 0 */
+ if (!cfg->error_callback_dis) {
+ chan_data->irq_unmask |= DMA_DW_AXI_IRQ_ALL_ERR;
+ }
+
+ /* dma descriptors are configured, ready to start dma transfer */
+ chan_data->ch_state = DMA_DW_AXI_CH_PREPARED;
+
+ return 0;
+}
+
+static int dma_dw_axi_start(const struct device *dev, uint32_t channel)
+{
+ uint32_t ch_state;
+ struct dma_dw_axi_ch_data *chan_data;
+ struct dma_lli *lli_desc;
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+
+ /* validate channel number */
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("invalid dma channel %d", channel);
+ return -EINVAL;
+ }
+
+ /* check whether channel is idle before initiating DMA transfer */
+ ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ if (ch_state != DMA_DW_AXI_CH_IDLE) {
+ LOG_ERR("DMA channel:%d is not idle", channel);
+ return -EBUSY;
+ }
+
+ /* get channel specific data pointer */
+ chan_data = &dw_dev_data->chan[channel];
+
+ if (chan_data->ch_state != DMA_DW_AXI_CH_PREPARED) {
+ LOG_ERR("DMA descriptors not configured");
+ return -EINVAL;
+ }
+
+ /* enable dma controller and global interrupt bit */
+ sys_write64(DMA_DW_AXI_CFG_INT_EN | DMA_DW_AXI_CFG_EN, reg_base + DMA_DW_AXI_CFGREG);
+
+ sys_write64(chan_data->cfg, reg_base + DMA_DW_AXI_CH_CFG(channel));
+
+ sys_write64(chan_data->irq_unmask,
+ reg_base + DMA_DW_AXI_CH_INTSTATUS_ENABLEREG(channel));
+ sys_write64(chan_data->irq_unmask,
+ reg_base + DMA_DW_AXI_CH_INTSIGNAL_ENABLEREG(channel));
+
+ lli_desc = chan_data->lli_desc_current;
+
+#if defined(CONFIG_DMA_DW_AXI_LLI_SUPPORT)
+ sys_write64(((uint64_t)lli_desc), reg_base + DMA_DW_AXI_CH_LLP(channel));
+#else
+ /* Program Source and Destination addresses */
+ sys_write64(lli_desc->sar, reg_base + DMA_DW_AXI_CH_SAR(channel));
+ sys_write64(lli_desc->dar, reg_base + DMA_DW_AXI_CH_DAR(channel));
+
+ sys_write64(lli_desc->block_ts_lo & BLOCK_TS_MASK,
+ reg_base + DMA_DW_AXI_CH_BLOCK_TS(channel));
+
+ /* Program CH.CTL register */
+ sys_write64(lli_desc->ctl, reg_base + DMA_DW_AXI_CH_CTL(channel));
+#endif
+
+ /* Enable the channel which will initiate DMA transfer */
+ sys_write64(CH_EN(channel), reg_base + DMA_DW_AXI_CHENREG);
+
+ chan_data->ch_state = dma_dw_axi_get_ch_status(dev, channel);
+
+ return 0;
+}
+
+static int dma_dw_axi_stop(const struct device *dev, uint32_t channel)
+{
+ bool is_channel_busy;
+ uint32_t ch_state;
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+
+ /* channel should be valid */
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("invalid dma channel %d", channel);
+ return -EINVAL;
+ }
+
+ /* return if the channel is idle as there is nothing to stop */
+ ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ if (ch_state == DMA_DW_AXI_CH_IDLE) {
+ /* channel is already idle */
+ return 0;
+ }
+
+ /* To stop transfer or abort the channel in case of abnormal state:
+ * 1. To disable channel, first suspend channel and drain the FIFO
+ * 2. Disable the channel. Channel may get hung and can't be disabled
+ * if there is no response from peripheral
+ * 3. If channel is not disabled, Abort the channel. Aborting channel will
+ * Flush out FIFO and data will be lost. Then corresponding interrupt will
+ * be raised for abort and CH_EN bit will be cleared from CHENREG register
+ */
+ sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG);
+
+ /* Try to disable the channel */
+ sys_clear_bit(reg_base + DMA_DW_AXI_CHENREG, channel);
+
+ is_channel_busy = WAIT_FOR((sys_read64(reg_base + DMA_DW_AXI_CHENREG)) & (BIT(channel)),
+ CONFIG_DMA_CHANNEL_STATUS_TIMEOUT, k_busy_wait(10));
+ if (is_channel_busy) {
+ LOG_WRN("No response from handshaking interface... Aborting a channel...");
+ sys_write64(CH_ABORT(channel), reg_base + DMA_DW_AXI_CHENREG);
+
+ is_channel_busy = WAIT_FOR((sys_read64(reg_base + DMA_DW_AXI_CHENREG)) &
+ (BIT(channel)), CONFIG_DMA_CHANNEL_STATUS_TIMEOUT,
+ k_busy_wait(10));
+ if (is_channel_busy) {
+ LOG_ERR("Channel abort failed");
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int dma_dw_axi_resume(const struct device *dev, uint32_t channel)
+{
+ uint32_t reg;
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+ uint32_t ch_state;
+
+ /* channel should be valid */
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("invalid dma channel %d", channel);
+ return -EINVAL;
+ }
+
+ ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ if (ch_state != DMA_DW_AXI_CH_SUSPENDED) {
+ LOG_INF("channel %u is not in suspended state so cannot resume channel", channel);
+ return 0;
+ }
+
+ reg = sys_read64(reg_base + DMA_DW_AXI_CHENREG);
+ /* channel susp write enable bit has to be asserted */
+ WRITE_BIT(reg, CH_RESUME_WE(channel), 1);
+ /* channel susp bit must be cleared to resume a channel*/
+ WRITE_BIT(reg, CH_RESUME(channel), 0);
+ /* resume a channel by writing 0: ch_susp and 1: ch_susp_we */
+ sys_write64(reg, reg_base + DMA_DW_AXI_CHENREG);
+
+ return 0;
+}
+
+/* suspend a dma channel */
+static int dma_dw_axi_suspend(const struct device *dev, uint32_t channel)
+{
+ int ret;
+ uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, dma_mmio);
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+ uint32_t ch_state;
+
+ /* channel should be valid */
+ if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {
+ LOG_ERR("invalid dma channel %u", channel);
+ return -EINVAL;
+ }
+
+ ch_state = dma_dw_axi_get_ch_status(dev, channel);
+ if (ch_state != DMA_DW_AXI_CH_ACTIVE) {
+ LOG_INF("nothing to suspend as dma channel %u is not busy", channel);
+ return 0;
+ }
+
+ /* suspend dma transfer */
+ sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG);
+
+ ret = WAIT_FOR(dma_dw_axi_get_ch_status(dev, channel) &
+ DMA_DW_AXI_CH_SUSPENDED, CONFIG_DMA_CHANNEL_STATUS_TIMEOUT,
+ k_busy_wait(10));
+ if (ret == 0) {
+ LOG_ERR("channel suspend failed");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dma_dw_axi_init(const struct device *dev)
+{
+ DEVICE_MMIO_NAMED_MAP(dev, dma_mmio, K_MEM_CACHE_NONE);
+ int i, ret;
+ struct dma_dw_axi_ch_data *chan_data;
+ const struct dma_dw_axi_dev_cfg *dw_dma_config = DEV_CFG(dev);
+ struct dma_dw_axi_dev_data *const dw_dev_data = DEV_DATA(dev);
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
+
+ if (dw_dma_config->reset.dev != NULL) {
+ /* check if reset manager is in ready state */
+ if (!device_is_ready(dw_dma_config->reset.dev)) {
+ LOG_ERR("reset controller device not found");
+ return -ENODEV;
+ }
+
+ /* assert and de-assert dma controller */
+ ret = reset_line_toggle(dw_dma_config->reset.dev, dw_dma_config->reset.id);
+ if (ret != 0) {
+ LOG_ERR("failed to reset dma controller");
+ return ret;
+ }
+ }
+#endif
+
+ /* initialize channel state variable */
+ for (i = 0; i < dw_dev_data->dma_ctx.dma_channels; i++) {
+ chan_data = &dw_dev_data->chan[i];
+ /* initialize channel state */
+ chan_data->ch_state = DMA_DW_AXI_CH_IDLE;
+ }
+
+ /* configure and enable interrupt lines */
+ dw_dma_config->irq_config();
+
+ return 0;
+}
+
+static const struct dma_driver_api dma_dw_axi_driver_api = {
+ .config = dma_dw_axi_config,
+ .start = dma_dw_axi_start,
+ .stop = dma_dw_axi_stop,
+ .suspend = dma_dw_axi_suspend,
+ .resume = dma_dw_axi_resume,
+};
+
+/* enable irq lines */
+#define CONFIGURE_DMA_IRQ(idx, inst) \
+ IF_ENABLED(DT_INST_IRQ_HAS_IDX(inst, idx), ( \
+ IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, idx, irq), \
+ DT_INST_IRQ_BY_IDX(inst, idx, priority), \
+ dma_dw_axi_isr, \
+ DEVICE_DT_INST_GET(inst), 0); \
+ irq_enable(DT_INST_IRQ_BY_IDX(inst, idx, irq)); \
+ ))
+
+#define DW_AXI_DMA_RESET_SPEC_INIT(inst) \
+ .reset = RESET_DT_SPEC_INST_GET(inst), \
+
+#define DW_AXI_DMAC_INIT(inst) \
+ static struct dma_dw_axi_ch_data chan_##inst[DT_INST_PROP(inst, dma_channels)]; \
+ static struct dma_lli \
+ dma_desc_pool_##inst[DT_INST_PROP(inst, dma_channels) * \
+ CONFIG_DMA_DW_AXI_MAX_DESC]; \
+ ATOMIC_DEFINE(dma_dw_axi_atomic##inst, \
+ DT_INST_PROP(inst, dma_channels)); \
+ static struct dma_dw_axi_dev_data dma_dw_axi_data_##inst = { \
+ .dma_ctx = { \
+ .magic = DMA_MAGIC, \
+ .atomic = dma_dw_axi_atomic##inst, \
+ .dma_channels = DT_INST_PROP(inst, dma_channels), \
+ }, \
+ .chan = chan_##inst, \
+ .dma_desc_pool = dma_desc_pool_##inst, \
+ }; \
+ static void dw_dma_irq_config_##inst(void); \
+ static const struct dma_dw_axi_dev_cfg dma_dw_axi_config_##inst = { \
+ DEVICE_MMIO_NAMED_ROM_INIT(dma_mmio, DT_DRV_INST(inst)), \
+ IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), \
+ (DW_AXI_DMA_RESET_SPEC_INIT(inst))) \
+ .irq_config = dw_dma_irq_config_##inst, \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(inst, \
+ &dma_dw_axi_init, \
+ NULL, \
+ &dma_dw_axi_data_##inst, \
+ &dma_dw_axi_config_##inst, POST_KERNEL, \
+ CONFIG_DMA_INIT_PRIORITY, \
+ &dma_dw_axi_driver_api); \
+ \
+ static void dw_dma_irq_config_##inst(void) \
+ { \
+ LISTIFY(DT_NUM_IRQS(DT_DRV_INST(inst)), CONFIGURE_DMA_IRQ, (), inst) \
+ }
+
+DT_INST_FOREACH_STATUS_OKAY(DW_AXI_DMAC_INIT)
diff --git a/drivers/dma/dma_dw_common.c b/drivers/dma/dma_dw_common.c
index f63595d..5b183c9 100644
--- a/drivers/dma/dma_dw_common.c
+++ b/drivers/dma/dma_dw_common.c
@@ -565,8 +565,9 @@
* needed
*/
ret = pm_device_state_get(dev, &pm_state);
- if (!ret && pm_state != PM_DEVICE_STATE_ACTIVE)
+ if (!ret && pm_state != PM_DEVICE_STATE_ACTIVE) {
goto out;
+ }
if (!dw_dma_is_enabled(dev, channel) && chan_data->state != DW_DMA_SUSPENDED) {
ret = 0;
diff --git a/drivers/dma/dma_emul.c b/drivers/dma/dma_emul.c
index 5397540..60c3486 100644
--- a/drivers/dma/dma_emul.c
+++ b/drivers/dma/dma_emul.c
@@ -526,7 +526,7 @@
};
#ifdef CONFIG_PM_DEVICE
-static int gpio_emul_pm_device_pm_action(const struct device *dev, enum pm_device_action action)
+static int dma_emul_pm_device_pm_action(const struct device *dev, enum pm_device_action action)
{
ARG_UNUSED(dev);
ARG_UNUSED(action);
diff --git a/drivers/dma/dma_esp32_gdma.c b/drivers/dma/dma_esp32_gdma.c
index 1f65d88..0a9e2ff 100644
--- a/drivers/dma/dma_esp32_gdma.c
+++ b/drivers/dma/dma_esp32_gdma.c
@@ -52,6 +52,12 @@
DMA_UNCONFIGURED
};
+struct irq_config {
+ uint8_t irq_source;
+ uint8_t irq_priority;
+ int irq_flags;
+};
+
struct dma_esp32_channel {
uint8_t dir;
uint8_t channel_id;
@@ -63,7 +69,7 @@
};
struct dma_esp32_config {
- int *irq_src;
+ struct irq_config *irq_config;
uint8_t irq_size;
void **irq_handlers;
uint8_t dma_channel_max;
@@ -539,13 +545,15 @@
static int dma_esp32_configure_irq(const struct device *dev)
{
struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config;
+ struct irq_config *irq_cfg = (struct irq_config *)config->irq_config;
for (uint8_t i = 0; i < config->irq_size; i++) {
- int ret = esp_intr_alloc(config->irq_src[i],
- 0,
- (ISR_HANDLER)config->irq_handlers[i],
- (void *)dev,
- NULL);
+ int ret = esp_intr_alloc(irq_cfg[i].irq_source,
+ ESP_PRIO_TO_FLAGS(irq_cfg[i].irq_priority) |
+ ESP_INT_FLAGS_CHECK(irq_cfg[i].irq_flags) | ESP_INTR_FLAG_IRAM,
+ (ISR_HANDLER)config->irq_handlers[i],
+ (void *)dev,
+ NULL);
if (ret != 0) {
LOG_ERR("Could not allocate interrupt handler");
return ret;
@@ -663,11 +671,19 @@
#endif
};
+#define IRQ_NUM(idx) DT_NUM_IRQS(DT_DRV_INST(idx))
+#define IRQ_ENTRY(n, idx) { \
+ DT_INST_IRQ_BY_IDX(idx, n, irq), \
+ DT_INST_IRQ_BY_IDX(idx, n, priority), \
+ DT_INST_IRQ_BY_IDX(idx, n, flags) },
+
#define DMA_ESP32_INIT(idx) \
- static int irq_numbers[] = DT_INST_PROP(idx, interrupts); \
+ static struct irq_config irq_config_##idx[] = { \
+ LISTIFY(IRQ_NUM(idx), IRQ_ENTRY, (), idx) \
+ }; \
static struct dma_esp32_config dma_config_##idx = { \
- .irq_src = irq_numbers, \
- .irq_size = ARRAY_SIZE(irq_numbers), \
+ .irq_config = irq_config_##idx, \
+ .irq_size = IRQ_NUM(idx), \
.irq_handlers = irq_handlers, \
.dma_channel_max = DT_INST_PROP(idx, dma_channels), \
.sram_alignment = DT_INST_PROP(idx, dma_buf_addr_alignment), \
diff --git a/drivers/eeprom/eeprom_simulator.c b/drivers/eeprom/eeprom_simulator.c
index 19efa5b..f6a604b 100644
--- a/drivers/eeprom/eeprom_simulator.c
+++ b/drivers/eeprom/eeprom_simulator.c
@@ -275,7 +275,7 @@
#ifdef CONFIG_ARCH_POSIX
-static void eeprom_native_posix_cleanup(void)
+static void eeprom_native_cleanup(void)
{
if ((mock_eeprom != MAP_FAILED) && (mock_eeprom != NULL)) {
munmap(mock_eeprom, DT_INST_PROP(0, size));
@@ -286,7 +286,7 @@
}
}
-static void eeprom_native_posix_options(void)
+static void eeprom_native_options(void)
{
static struct args_struct_t eeprom_options[] = {
{ .manual = false,
@@ -304,8 +304,7 @@
native_add_command_line_opts(eeprom_options);
}
-
-NATIVE_TASK(eeprom_native_posix_options, PRE_BOOT_1, 1);
-NATIVE_TASK(eeprom_native_posix_cleanup, ON_EXIT, 1);
+NATIVE_TASK(eeprom_native_options, PRE_BOOT_1, 1);
+NATIVE_TASK(eeprom_native_cleanup, ON_EXIT, 1);
#endif /* CONFIG_ARCH_POSIX */
diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt
index aa86765..8a67fc3 100644
--- a/drivers/entropy/CMakeLists.txt
+++ b/drivers/entropy/CMakeLists.txt
@@ -25,14 +25,15 @@
endif()
endif()
-zephyr_library_sources_ifdef(CONFIG_USERSPACE entropy_handlers.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_RV32M1_TRNG entropy_rv32m1_trng.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_TRNG entropy_gecko_trng.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG entropy_neorv32_trng.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c)
-zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAX32_TRNG entropy_max32.c)
+zephyr_library_sources_ifdef(CONFIG_USERSPACE entropy_handlers.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_RV32M1_TRNG entropy_rv32m1_trng.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_TRNG entropy_gecko_trng.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG entropy_neorv32_trng.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAX32_TRNG entropy_max32.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_RENESAS_RA_RSIP_E51A_TRNG entropy_renesas_ra.c)
zephyr_library_link_libraries_ifdef(CONFIG_BUILD_WITH_TFM tfm_api)
diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig
index 21bb7bd..debd0f8 100644
--- a/drivers/entropy/Kconfig
+++ b/drivers/entropy/Kconfig
@@ -37,6 +37,7 @@
source "drivers/entropy/Kconfig.psa_crypto"
source "drivers/entropy/Kconfig.npcx"
source "drivers/entropy/Kconfig.max32"
+source "drivers/entropy/Kconfig.renesas_ra"
config ENTROPY_HAS_DRIVER
bool
diff --git a/drivers/entropy/Kconfig.renesas_ra b/drivers/entropy/Kconfig.renesas_ra
new file mode 100644
index 0000000..c212e7b
--- /dev/null
+++ b/drivers/entropy/Kconfig.renesas_ra
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Renesas RA entropy generator driver configuration
+
+config ENTROPY_RENESAS_RA_RSIP_E51A_TRNG
+ bool "Renesas RA RSIP-E51A TRNG driver"
+ default y
+ depends on DT_HAS_RENESAS_RA_RSIP_E51A_TRNG_ENABLED
+ select ENTROPY_HAS_DRIVER
+ select USE_RA_FSP_SCE
+ help
+ This option enables the Renesas RA RSIP-E51A RNG.
diff --git a/drivers/entropy/entropy_esp32.c b/drivers/entropy/entropy_esp32.c
index 8be2891..95138cb 100644
--- a/drivers/entropy/entropy_esp32.c
+++ b/drivers/entropy/entropy_esp32.c
@@ -9,8 +9,6 @@
#include <string.h>
#include <soc/rtc.h>
#include <soc/wdev_reg.h>
-#include <soc/rtc_cntl_reg.h>
-#include <soc/apb_ctrl_reg.h>
#include <esp_system.h>
#include <soc.h>
#include <esp_cpu.h>
diff --git a/drivers/entropy/entropy_renesas_ra.c b/drivers/entropy/entropy_renesas_ra.c
new file mode 100644
index 0000000..49f9302
--- /dev/null
+++ b/drivers/entropy/entropy_renesas_ra.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_rsip_e51a_trng
+
+#include <soc.h>
+#include <zephyr/drivers/entropy.h>
+
+#include "hw_sce_trng_private.h"
+#include "hw_sce_private.h"
+
+static int entropy_ra_rsip_trng_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len)
+{
+ ARG_UNUSED(dev);
+
+ if (buf == NULL) {
+ return -EINVAL;
+ }
+
+ while (len > 0) {
+ uint32_t n[4];
+ const uint32_t to_copy = MIN(sizeof(n), len);
+
+ if (FSP_SUCCESS != HW_SCE_RNG_Read(n)) {
+ return -ENODATA;
+ }
+ memcpy(buf, n, to_copy);
+ buf += to_copy;
+ len -= to_copy;
+ }
+
+ return 0;
+}
+
+static const struct entropy_driver_api entropy_ra_rsip_trng_api = {
+ .get_entropy = entropy_ra_rsip_trng_get_entropy,
+};
+
+static int entropy_ra_rsip_trng_init(const struct device *dev)
+{
+ HW_SCE_McuSpecificInit();
+ return 0;
+}
+
+DEVICE_DT_INST_DEFINE(0, entropy_ra_rsip_trng_init, NULL, NULL, NULL, PRE_KERNEL_1,
+ CONFIG_ENTROPY_INIT_PRIORITY, &entropy_ra_rsip_trng_api);
diff --git a/drivers/entropy/entropy_smartbond.c b/drivers/entropy/entropy_smartbond.c
index 48ada62..8a376c7 100644
--- a/drivers/entropy/entropy_smartbond.c
+++ b/drivers/entropy/entropy_smartbond.c
@@ -94,6 +94,7 @@
} else {
CRG_TOP->CLK_AMBA_REG &= ~CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk;
TRNG->TRNG_CTRL_REG = 0;
+ NVIC_ClearPendingIRQ(IRQN);
entropy_smartbond_pm_policy_state_lock_put();
}
diff --git a/drivers/espi/espi_it8xxx2.c b/drivers/espi/espi_it8xxx2.c
index 92ccab7..8a8364c 100644
--- a/drivers/espi/espi_it8xxx2.c
+++ b/drivers/espi/espi_it8xxx2.c
@@ -209,6 +209,7 @@
*/
#define IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX 0x1000
#define IT8XXX2_ESPI_H2RAM_OFFSET_MASK GENMASK(5, 0)
+#define IT8XXX2_ESPI_H2RAM_BASEADDR_MASK (KB(CONFIG_SRAM_SIZE) - 1)
#if defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
#define H2RAM_ACPI_SHM_MAX ((CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) + \
@@ -260,8 +261,8 @@
uint8_t h2ram_offset;
/* Set the host to RAM cycle address offset */
- h2ram_offset = ((uint32_t)h2ram_pool & 0xffff) /
- IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX;
+ h2ram_offset = ((uint32_t)h2ram_pool & IT8XXX2_ESPI_H2RAM_BASEADDR_MASK) /
+ IT8XXX2_ESPI_H2RAM_POOL_SIZE_MAX;
gctrl->GCTRL_H2ROFSR =
(gctrl->GCTRL_H2ROFSR & ~IT8XXX2_ESPI_H2RAM_OFFSET_MASK) |
h2ram_offset;
@@ -854,13 +855,14 @@
break;
case E8042_RESUME_IRQ:
/* Enable KBC IBF interrupt */
- kbc_reg->KBHICR |= KBC_KBHICR_IBFCIE;
+ irq_enable(IT8XXX2_KBC_IBF_IRQ);
break;
case E8042_PAUSE_IRQ:
/* Disable KBC IBF interrupt */
- kbc_reg->KBHICR &= ~KBC_KBHICR_IBFCIE;
+ irq_disable(IT8XXX2_KBC_IBF_IRQ);
break;
case E8042_CLEAR_OBF:
+ volatile uint8_t _kbhicr __unused;
/*
* After enabling IBF/OBF clear mode, we have to make
* sure that IBF interrupt is not triggered before
@@ -877,6 +879,12 @@
kbc_reg->KBHICR &= ~KBC_KBHICR_COBF;
/* Disable clear mode */
kbc_reg->KBHICR &= ~KBC_KBHICR_IBFOBFCME;
+ /*
+ * I/O access synchronization, this load operation will
+ * guarantee the above modification of SOC's register
+ * can be seen by any following instructions.
+ */
+ _kbhicr = kbc_reg->KBHICR;
irq_unlock(key);
break;
case E8042_SET_FLAG:
@@ -912,9 +920,9 @@
/* Enable/Disable PMC1 (port 62h/66h) interrupt */
case ECUSTOM_HOST_SUBS_INTERRUPT_EN:
if (*data) {
- pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE;
+ irq_enable(IT8XXX2_PMC1_IBF_IRQ);
} else {
- pmc_reg->PM1CTL &= ~PMC_PM1CTL_IBFIE;
+ irq_disable(IT8XXX2_PMC1_IBF_IRQ);
}
break;
case ECUSTOM_HOST_CMD_SEND_RESULT:
diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c
index 3d3f2c7..0eae657 100644
--- a/drivers/espi/espi_npcx.c
+++ b/drivers/espi/espi_npcx.c
@@ -208,8 +208,9 @@
miwu_dev_callback_handler_t handler)
{
/* VW signal which has no wake-up input source */
- if (wui->table == NPCX_MIWU_TABLE_NONE)
+ if (wui->table == NPCX_MIWU_TABLE_NONE) {
return;
+ }
/* Install callback function */
npcx_miwu_init_dev_callback(callback, wui, handler, dev);
@@ -468,8 +469,9 @@
/* IE & WE bits are already set? */
if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
- IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE))
+ IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE)) {
return;
+ }
/* Set IE & WE bits in VWEVMS */
inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
@@ -699,17 +701,21 @@
}
/* Configure eSPI supported channels */
- if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL)
+ if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
+ }
- if (cfg->channel_caps & ESPI_CHANNEL_VWIRE)
+ if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
+ }
- if (cfg->channel_caps & ESPI_CHANNEL_OOB)
+ if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
+ }
- if (cfg->channel_caps & ESPI_CHANNEL_FLASH)
+ if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
+ }
LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
max_freq, io_mode, inst->ESPICFG);
@@ -769,9 +775,11 @@
}
/* Find signal in VW output table */
- for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++)
- if (vw_tbl[sig_idx].sig == signal)
+ for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++) {
+ if (vw_tbl[sig_idx].sig == signal) {
break;
+ }
+ }
if (sig_idx == vw_tbl_size) {
LOG_ERR("%s signal %d is invalid", __func__, signal);
@@ -814,7 +822,7 @@
uint8_t reg_idx, bitmask, sig_idx, val;
/* Find signal in VW input table */
- for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++)
+ for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++) {
if (vw_in_tbl[sig_idx].sig == signal) {
reg_idx = vw_in_tbl[sig_idx].reg_idx;
bitmask = vw_in_tbl[sig_idx].bitmask;
@@ -827,9 +835,10 @@
*level = !!(val & bitmask);
return 0;
}
+ }
/* Find signal in VW output table */
- for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++)
+ for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++) {
if (vw_out_tbl[sig_idx].sig == signal) {
reg_idx = vw_out_tbl[sig_idx].reg_idx;
bitmask = vw_out_tbl[sig_idx].bitmask;
@@ -841,6 +850,7 @@
*level = !!(val & bitmask);
return 0;
}
+ }
LOG_ERR("%s Out of index %d", __func__, signal);
return -EIO;
@@ -921,8 +931,9 @@
int i;
oob_data = 0;
- for (i = 0; i < sz_oob_tx % 4; i++)
+ for (i = 0; i < sz_oob_tx % 4; i++) {
oob_data |= (oob_buf[i] << (8 * i));
+ }
inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
}
@@ -934,8 +945,9 @@
oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
inst->OOBCTL = oob_data;
- while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL))
+ while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
;
+ }
LOG_DBG("%s issued!!", __func__);
return 0;
@@ -1004,8 +1016,9 @@
int i;
oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
- for (i = 0; i < sz_oob_rx % 4; i++)
+ for (i = 0; i < sz_oob_rx % 4; i++) {
*(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
+ }
}
/* Notify host that OOB received buffer is free now. */
@@ -1329,11 +1342,6 @@
const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
int i, ret;
- /* If booter doesn't set the host interface type */
- if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
- npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
- }
-
if (!device_is_ready(clk_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
@@ -1370,12 +1378,14 @@
#endif
/* Configure Virtual Wire input signals */
- for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
+ for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
espi_vw_config_input(dev, &vw_in_tbl[i]);
+ }
/* Configure Virtual Wire output signals */
- for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++)
+ for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++) {
espi_vw_config_output(dev, &vw_out_tbl[i]);
+ }
/* Configure Virtual Wire GPIOs that are output high at reset state */
for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
@@ -1383,9 +1393,10 @@
}
/* Configure wake-up input and callback for eSPI VW input signal */
- for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
+ for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
espi_init_wui_callback(dev, &vw_in_callback[i],
&vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
+ }
/* Configure wake-up input and callback for ESPI_RST signal */
espi_init_wui_callback(dev, &espi_rst_callback,
diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c
index 5d707d3..28a938b 100644
--- a/drivers/ethernet/eth_adin2111.c
+++ b/drivers/ethernet/eth_adin2111.c
@@ -1061,8 +1061,9 @@
}
if ((reg & UINT16_MAX) == sys_get_be16(&mac[0])) {
if ((port_idx == 0 && !(reg & ADIN2111_ADDR_APPLY2PORT1)) ||
- (port_idx == 1 && !(reg & ADIN2111_ADDR_APPLY2PORT2)))
+ (port_idx == 1 && !(reg & ADIN2111_ADDR_APPLY2PORT2))) {
continue;
+ }
ret = eth_adin2111_reg_read(dev, ADIN2111_ADDR_FILT_LWR + offset, ®);
if (ret < 0) {
diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c
index c92776a..59977d3 100644
--- a/drivers/ethernet/eth_esp32.c
+++ b/drivers/ethernet/eth_esp32.c
@@ -261,11 +261,13 @@
dev_data->dma_rx_buf, dev_data->dma_tx_buf);
/* Configure ISR */
- res = esp_intr_alloc(DT_IRQN(DT_NODELABEL(eth)),
- ESP_INTR_FLAG_IRAM,
- eth_esp32_isr,
- (void *)dev,
- NULL);
+ res = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, flags)) |
+ ESP_INTR_FLAG_IRAM,
+ eth_esp32_isr,
+ (void *)dev,
+ NULL);
if (res != 0) {
goto err;
}
diff --git a/drivers/ethernet/eth_ivshmem_queue.c b/drivers/ethernet/eth_ivshmem_queue.c
index 3301dd7..6f40464 100644
--- a/drivers/ethernet/eth_ivshmem_queue.c
+++ b/drivers/ethernet/eth_ivshmem_queue.c
@@ -82,8 +82,9 @@
memset(q->tx.shmem, 0, q->vring_header_size);
/* Init TX ring descriptors */
- for (unsigned int i = 0; i < q->tx.vring.num - 1; i++)
+ for (unsigned int i = 0; i < q->tx.vring.num - 1; i++) {
q->tx.vring.desc[i].next = i + 1;
+ }
q->tx.vring.desc[q->tx.vring.num - 1].next = 0;
}
diff --git a/drivers/ethernet/eth_lan865x.c b/drivers/ethernet/eth_lan865x.c
index e822ba8..870d6ab 100644
--- a/drivers/ethernet/eth_lan865x.c
+++ b/drivers/ethernet/eth_lan865x.c
@@ -368,8 +368,9 @@
lan865x_set_specific_multicast_addr(dev);
ret = lan865x_init_chip(dev, silicon_rev);
- if (ret < 0)
+ if (ret < 0) {
return ret;
+ }
if (cfg->plca->enable) {
ret = lan865x_config_plca(dev, cfg->plca->node_id,
diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
index f5913c9..99acf2b 100644
--- a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
+++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
@@ -294,8 +294,9 @@
if (CONFIG_ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME == 0) {
/* spin and wait forever for the reset flag to clear */
- while (ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE))
+ while (ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE)) {
;
+ }
goto done;
}
@@ -340,8 +341,9 @@
/* Wait for flush to finish */
while (ENET_QOS_REG_GET(MTL_QUEUE_MTL_TXQX_OP_MODE, FTQ,
- base->MTL_QUEUE[0].MTL_TXQX_OP_MODE))
+ base->MTL_QUEUE[0].MTL_TXQX_OP_MODE)) {
;
+ }
/* Enable only Transmit Queue 0 (optimization/configuration pending) with maximum size */
base->MTL_QUEUE[0].MTL_TXQX_OP_MODE =
diff --git a/drivers/ethernet/eth_nxp_s32_netc_priv.h b/drivers/ethernet/eth_nxp_s32_netc_priv.h
index e259b67..760522b 100644
--- a/drivers/ethernet/eth_nxp_s32_netc_priv.h
+++ b/drivers/ethernet/eth_nxp_s32_netc_priv.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -99,7 +99,7 @@
#define _CONCAT3(a, b, c) DT_CAT3(a, b, c)
struct nxp_s32_eth_msix {
- void (*handler)(uint8_t chan, const uint32_t *buf, uint8_t buf_size);
+ void (*handler)(uint8_t chan, const uint32 *buf, uint8_t buf_size);
struct mbox_dt_spec mbox_spec;
};
diff --git a/drivers/ethernet/eth_nxp_s32_netc_psi.c b/drivers/ethernet/eth_nxp_s32_netc_psi.c
index baab313..69ff36d 100644
--- a/drivers/ethernet/eth_nxp_s32_netc_psi.c
+++ b/drivers/ethernet/eth_nxp_s32_netc_psi.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -259,7 +259,7 @@
#define INIT_VSIS(n) DT_INST_NODE_HAS_PROP(n, vsis)
#define NETC_PSI_INSTANCE_DEFINE(n) \
-void nxp_s32_eth_psi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
+void nxp_s32_eth_psi##n##_rx_event(uint8_t chan, const uint32 *buf, uint8_t buf_size) \
{ \
ARG_UNUSED(chan); \
ARG_UNUSED(buf); \
@@ -281,8 +281,8 @@
} \
} \
\
-static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
-static Netc_Eth_Ip_MACFilterHashTableEntryType \
+static __nocache Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
+static __nocache Netc_Eth_Ip_MACFilterHashTableEntryType \
nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
\
NETC_TX_RING(n, 0, NETC_MIN_RING_LEN, NETC_MIN_RING_BUF_SIZE); \
@@ -359,27 +359,31 @@
NETC_VSI_RX_MSG_BUF_ARRAY, (,), n)), \
(EMPTY)) \
}, \
+ .maskMACVLANPromiscuousEnable = (uint16)0x3U, \
+ .maskVLANAllowUntaggedEnable = (uint32)0x30000U, \
}; \
\
static const Netc_Eth_Ip_StationInterfaceConfigType nxp_s32_eth##n##_si_cfg = { \
.NumberOfRxBDR = 1, \
.NumberOfTxBDR = 2, \
.txMruMailboxAddr = NULL, \
- .rxMruMailboxAddr = (uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
+ .rxMruMailboxAddr = (uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
.siMsgMruMailboxAddr = COND_CODE_1(INIT_VSIS(n), \
- ((uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), vsi_msg)), (NULL)), \
+ ((uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), vsi_msg)), (NULL)), \
+ .EnableSIMsgInterrupt = true, \
.RxInterrupts = (uint32_t)true, \
.TxInterrupts = (uint32_t)false, \
.MACFilterTableMaxNumOfEntries = CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE, \
}; \
\
-static uint8_t nxp_s32_eth##n##_switch_vlandr2dei_cfg[NETC_ETHSWT_NUMBER_OF_DR]; \
+static uint8_t nxp_s32_eth##n##_switch_vlandr2dei_cfg[NETC_ETHSWT_IP_NUMBER_OF_DR]; \
static Netc_EthSwt_Ip_PortIngressType nxp_s32_eth##n##_switch_port_ingress_cfg; \
static Netc_EthSwt_Ip_PortEgressType nxp_s32_eth##n##_switch_port_egress_cfg = { \
.vlanDrToDei = &nxp_s32_eth##n##_switch_vlandr2dei_cfg, \
}; \
-static Netc_EthSwt_Ip_PortType nxp_s32_eth##n##_switch_ports_cfg[NETC_ETHSWT_NUMBER_OF_PORTS] = {\
- LISTIFY(NETC_ETHSWT_NUMBER_OF_PORTS, NETC_SWITCH_PORT_CFG, (,), n) \
+static Netc_EthSwt_Ip_PortType \
+nxp_s32_eth##n##_switch_ports_cfg[NETC_ETHSWT_IP_NUMBER_OF_PORTS] = { \
+ LISTIFY(NETC_ETHSWT_IP_NUMBER_OF_PORTS, NETC_SWITCH_PORT_CFG, (,), n) \
}; \
\
static const Netc_EthSwt_Ip_ConfigType nxp_s32_eth##n##_switch_cfg = { \
diff --git a/drivers/ethernet/eth_nxp_s32_netc_vsi.c b/drivers/ethernet/eth_nxp_s32_netc_vsi.c
index f015934..bf5046c 100644
--- a/drivers/ethernet/eth_nxp_s32_netc_vsi.c
+++ b/drivers/ethernet/eth_nxp_s32_netc_vsi.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -82,7 +82,7 @@
#define NETC_VSI_INSTANCE_DEFINE(n) \
NETC_GENERATE_MAC_ADDRESS(n) \
\
- void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
+ void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32 *buf, uint8_t buf_size) \
{ \
Netc_Eth_Ip_MSIX_Rx(NETC_SI_NXP_S32_HW_INSTANCE(n)); \
} \
@@ -98,10 +98,10 @@
} \
} \
\
- static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
- Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
+ static __nocache Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
+ __nocache Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
__aligned(FEATURE_NETC_ETH_VSI_MSG_ALIGNMENT); \
- static Netc_Eth_Ip_MACFilterHashTableEntryType \
+ static __nocache Netc_Eth_Ip_MACFilterHashTableEntryType \
nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
\
NETC_RX_RING(n, TX_RING_IDX, CONFIG_ETH_NXP_S32_RX_RING_LEN, \
@@ -137,7 +137,8 @@
.NumberOfRxBDR = 1, \
.NumberOfTxBDR = 1, \
.txMruMailboxAddr = NULL, \
- .rxMruMailboxAddr = (uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
+ .rxMruMailboxAddr = (uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
+ .EnableSIMsgInterrupt = true, \
.RxInterrupts = (uint32_t)true, \
.TxInterrupts = (uint32_t)false, \
.MACFilterTableMaxNumOfEntries = CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE, \
diff --git a/drivers/ethernet/eth_smsc91x.c b/drivers/ethernet/eth_smsc91x.c
index a752296..ab19ecd 100644
--- a/drivers/ethernet/eth_smsc91x.c
+++ b/drivers/ethernet/eth_smsc91x.c
@@ -99,8 +99,9 @@
static void smsc_mmu_wait(struct smsc_data *sc)
{
__ASSERT((smsc_current_bank(sc) == 2), "%s called when not in bank 2", __func__);
- while (sys_read16(sc->smsc_reg + MMUCR) & MMUCR_BUSY)
+ while (sys_read16(sc->smsc_reg + MMUCR) & MMUCR_BUSY) {
;
+ }
}
static ALWAYS_INLINE uint8_t smsc_read_1(struct smsc_data *sc, int offset)
diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c
index 34825a7..6459f3c 100644
--- a/drivers/ethernet/eth_stm32_hal.c
+++ b/drivers/ethernet/eth_stm32_hal.c
@@ -59,7 +59,7 @@
#if defined(CONFIG_MDIO)
#define DEVICE_PHY_BY_NAME(n) \
- DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), ethernet_phy_0))
+ DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), __CONCAT(ethernet_phy_, PHY_ADDR)))
static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
diff --git a/drivers/ethernet/nxp_enet/eth_nxp_enet.c b/drivers/ethernet/nxp_enet/eth_nxp_enet.c
index 2995e82..a92b13f 100644
--- a/drivers/ethernet/nxp_enet/eth_nxp_enet.c
+++ b/drivers/ethernet/nxp_enet/eth_nxp_enet.c
@@ -620,8 +620,9 @@
{
uint32_t id = ETH_NXP_ENET_UNIQUE_ID;
- if (id == 0xFFFFFF)
+ if (id == 0xFFFFFF) {
LOG_ERR("No unique MAC can be provided in this platform");
+ }
/* Setting LAA bit because it is not guaranteed universally unique */
mac_addr[0] = FREESCALE_OUI_B0 | 0x02;
diff --git a/drivers/firmware/CMakeLists.txt b/drivers/firmware/CMakeLists.txt
new file mode 100644
index 0000000..1222e93
--- /dev/null
+++ b/drivers/firmware/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_ARM_SCMI scmi)
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
new file mode 100644
index 0000000..4157606
--- /dev/null
+++ b/drivers/firmware/Kconfig
@@ -0,0 +1,15 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Firmware drivers"
+
+config ARM_SCMI
+ bool "Support for ARM's SCMI"
+ depends on ARM || ARM64
+ help
+ Enable support for ARM's System Configuration and Management
+ Interface (SCMI).
+
+source "drivers/firmware/scmi/Kconfig"
+
+endmenu
diff --git a/drivers/firmware/scmi/CMakeLists.txt b/drivers/firmware/scmi/CMakeLists.txt
new file mode 100644
index 0000000..68e4c7a
--- /dev/null
+++ b/drivers/firmware/scmi/CMakeLists.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+# SCMI core files
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI core.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_MAILBOX_TRANSPORT mailbox.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_SHMEM shmem.c)
+
+# SCMI protocol helper files
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_CLK_HELPERS clk.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_PINCTRL_HELPERS pinctrl.c)
diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig
new file mode 100644
index 0000000..f75583f
--- /dev/null
+++ b/drivers/firmware/scmi/Kconfig
@@ -0,0 +1,59 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if ARM_SCMI
+
+config ARM_SCMI_CLK_HELPERS
+ bool "Helper functions for SCMI clock protocol"
+ default y
+ depends on DT_HAS_ARM_SCMI_CLOCK_ENABLED
+ help
+ Enable support for SCMI clock protocol helper functions.
+
+config ARM_SCMI_MAILBOX_TRANSPORT
+ bool "SCMI transport based on shared memory and doorbells"
+ default y
+ depends on DT_HAS_ARM_SCMI_ENABLED
+ depends on ARM_SCMI_SHMEM
+ select ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS
+ help
+ Enable support for SCMI transport based on shared memory
+ and doorbells.
+
+config ARM_SCMI_PINCTRL_HELPERS
+ bool "Helper functions for SCMI pinctrl protocol"
+ default y
+ depends on DT_HAS_ARM_SCMI_PINCTRL_ENABLED
+ help
+ Enable support for SCMI pinctrl protocol helper functions.
+
+config ARM_SCMI_SHMEM
+ bool "SCMI shared memory (SHMEM) driver"
+ default y
+ depends on DT_HAS_ARM_SCMI_SHMEM_ENABLED
+ help
+ Enable support for SCMI shared memory (SHMEM) driver.
+
+config ARM_SCMI_SHMEM_INIT_PRIORITY
+ int "SCMI shared memory (SHMEM) initialization priority"
+ default 15
+ help
+ SCMI SHMEM driver device initialization priority.
+
+config ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS
+ bool "Transport layer has static channels"
+ help
+ Enable this if the SCMI transport layer uses static channels.
+ What this means is that each protocol will have its channels
+ assigned at compile time. This option is recommended for
+ transport layer drivers which can use the default channel
+ allocation scheme (i.e: use protocol-specific channels if
+ they exist, otherwise use base protocol channels).
+
+config ARM_SCMI_TRANSPORT_INIT_PRIORITY
+ int "SCMI transport layer initialization priority"
+ default 20
+ help
+ SCMI transport driver device initialization priority.
+
+endif # ARM_SCMI
diff --git a/drivers/firmware/scmi/clk.c b/drivers/firmware/scmi/clk.c
new file mode 100644
index 0000000..4153495
--- /dev/null
+++ b/drivers/firmware/scmi/clk.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/clk.h>
+#include <string.h>
+
+/* TODO: if extended attributes are supported this should be moved
+ * to the header file so that users will have access to it.
+ */
+#define SCMI_CLK_CONFIG_EA_MASK GENMASK(23, 16)
+
+struct scmi_clock_attributes_reply {
+ int32_t status;
+ uint32_t attributes;
+};
+
+struct scmi_clock_rate_set_reply {
+ int32_t status;
+ uint32_t rate[2];
+};
+
+int scmi_clock_rate_get(struct scmi_protocol *proto,
+ uint32_t clk_id, uint32_t *rate)
+{
+ struct scmi_message msg, reply;
+ int ret;
+ struct scmi_clock_rate_set_reply reply_buffer;
+
+ /* sanity checks */
+ if (!proto || !rate) {
+ return -EINVAL;
+ }
+
+ if (proto->id != SCMI_PROTOCOL_CLOCK) {
+ return -EINVAL;
+ }
+
+ msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_CLOCK_RATE_GET,
+ SCMI_COMMAND, proto->id, 0x0);
+ msg.len = sizeof(clk_id);
+ msg.content = &clk_id;
+
+ reply.hdr = msg.hdr;
+ reply.len = sizeof(reply_buffer);
+ reply.content = &reply_buffer;
+
+ ret = scmi_send_message(proto, &msg, &reply);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (reply_buffer.status != SCMI_SUCCESS) {
+ return scmi_status_to_errno(reply_buffer.status);
+ }
+
+ *rate = reply_buffer.rate[0];
+
+ return 0;
+}
+
+int scmi_clock_config_set(struct scmi_protocol *proto,
+ struct scmi_clock_config *cfg)
+{
+ struct scmi_message msg, reply;
+ int status, ret;
+
+ /* sanity checks */
+ if (!proto || !cfg) {
+ return -EINVAL;
+ }
+
+ if (proto->id != SCMI_PROTOCOL_CLOCK) {
+ return -EINVAL;
+ }
+
+ /* extended attributes currently not supported */
+ if (cfg->attributes & SCMI_CLK_CONFIG_EA_MASK) {
+ return -ENOTSUP;
+ }
+
+ /* invalid because extended attributes are not supported */
+ if (SCMI_CLK_CONFIG_ENABLE_DISABLE(cfg->attributes) == 3) {
+ return -ENOTSUP;
+ }
+
+ /* this is a reserved value */
+ if (SCMI_CLK_CONFIG_ENABLE_DISABLE(cfg->attributes) == 2) {
+ return -EINVAL;
+ }
+
+ msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_CLOCK_CONFIG_SET,
+ SCMI_COMMAND, proto->id, 0x0);
+ msg.len = sizeof(*cfg);
+ msg.content = cfg;
+
+ reply.hdr = msg.hdr;
+ reply.len = sizeof(status);
+ reply.content = &status;
+
+ ret = scmi_send_message(proto, &msg, &reply);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (status != SCMI_SUCCESS) {
+ return scmi_status_to_errno(status);
+ }
+
+ return 0;
+}
+
+int scmi_clock_protocol_attributes(struct scmi_protocol *proto, uint32_t *attributes)
+{
+ struct scmi_message msg, reply;
+ struct scmi_clock_attributes_reply reply_buffer;
+ int ret;
+
+ /* sanity checks */
+ if (!proto || !attributes) {
+ return -EINVAL;
+ }
+
+ if (proto->id != SCMI_PROTOCOL_CLOCK) {
+ return -EINVAL;
+ }
+
+ msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES,
+ SCMI_COMMAND, proto->id, 0x0);
+ /* command has no parameters */
+ msg.len = 0x0;
+ msg.content = NULL;
+
+ reply.hdr = msg.hdr;
+ reply.len = sizeof(reply_buffer);
+ reply.content = &reply_buffer;
+
+ ret = scmi_send_message(proto, &msg, &reply);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (reply_buffer.status != 0) {
+ return scmi_status_to_errno(reply_buffer.status);
+ }
+
+ *attributes = reply_buffer.attributes;
+
+ return 0;
+}
diff --git a/drivers/firmware/scmi/core.c b/drivers/firmware/scmi/core.c
new file mode 100644
index 0000000..58e3544
--- /dev/null
+++ b/drivers/firmware/scmi/core.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+#include <zephyr/drivers/firmware/scmi/transport.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/device.h>
+
+LOG_MODULE_REGISTER(scmi_core);
+
+#define SCMI_CHAN_LOCK_TIMEOUT_USEC 500
+#define SCMI_CHAN_SEM_TIMEOUT_USEC 500
+
+int scmi_status_to_errno(int scmi_status)
+{
+ switch (scmi_status) {
+ case SCMI_SUCCESS:
+ return 0;
+ case SCMI_NOT_SUPPORTED:
+ return -EOPNOTSUPP;
+ case SCMI_INVALID_PARAMETERS:
+ return -EINVAL;
+ case SCMI_DENIED:
+ return -EACCES;
+ case SCMI_NOT_FOUND:
+ return -ENOENT;
+ case SCMI_OUT_OF_RANGE:
+ return -ERANGE;
+ case SCMI_IN_USE:
+ case SCMI_BUSY:
+ return -EBUSY;
+ case SCMI_PROTOCOL_ERROR:
+ return -EPROTO;
+ case SCMI_COMMS_ERROR:
+ case SCMI_GENERIC_ERROR:
+ case SCMI_HARDWARE_ERROR:
+ default:
+ return -EIO;
+ }
+}
+
+static void scmi_core_reply_cb(struct scmi_channel *chan)
+{
+ if (!k_is_pre_kernel()) {
+ k_sem_give(&chan->sem);
+ }
+}
+
+static int scmi_core_setup_chan(const struct device *transport,
+ struct scmi_channel *chan, bool tx)
+{
+ int ret;
+
+ if (!chan) {
+ return -EINVAL;
+ }
+
+ if (chan->ready) {
+ return 0;
+ }
+
+ /* no support for RX channels ATM */
+ if (!tx) {
+ return -ENOTSUP;
+ }
+
+ k_mutex_init(&chan->lock);
+ k_sem_init(&chan->sem, 0, 1);
+
+ chan->cb = scmi_core_reply_cb;
+
+ /* setup transport-related channel data */
+ ret = scmi_transport_setup_chan(transport, chan, tx);
+ if (ret < 0) {
+ LOG_ERR("failed to setup channel");
+ return ret;
+ }
+
+ /* protocols might share a channel. In such cases, this
+ * will stop them from being initialized again.
+ */
+ chan->ready = true;
+
+ return 0;
+}
+
+static int scmi_send_message_pre_kernel(struct scmi_protocol *proto,
+ struct scmi_message *msg,
+ struct scmi_message *reply)
+{
+ int ret;
+
+ ret = scmi_transport_send_message(proto->transport, proto->tx, msg);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* no kernel primitives, we're forced to poll here.
+ *
+ * Cortex-M quirk: no interrupts at this point => no timer =>
+ * no timeout mechanism => this can block the whole system.
+ *
+ * TODO: is there a better way to handle this?
+ */
+ while (!scmi_transport_channel_is_free(proto->transport, proto->tx)) {
+ }
+
+ ret = scmi_transport_read_message(proto->transport, proto->tx, reply);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+static int scmi_send_message_post_kernel(struct scmi_protocol *proto,
+ struct scmi_message *msg,
+ struct scmi_message *reply)
+{
+ int ret = 0;
+
+ if (!proto->tx) {
+ return -ENODEV;
+ }
+
+ /* wait for channel to be free */
+ ret = k_mutex_lock(&proto->tx->lock, K_USEC(SCMI_CHAN_LOCK_TIMEOUT_USEC));
+ if (ret < 0) {
+ LOG_ERR("failed to acquire chan lock");
+ return ret;
+ }
+
+ ret = scmi_transport_send_message(proto->transport, proto->tx, msg);
+ if (ret < 0) {
+ LOG_ERR("failed to send message");
+ goto out_release_mutex;
+ }
+
+ /* only one protocol instance can wait for a message reply at a time */
+ ret = k_sem_take(&proto->tx->sem, K_USEC(SCMI_CHAN_SEM_TIMEOUT_USEC));
+ if (ret < 0) {
+ LOG_ERR("failed to wait for msg reply");
+ goto out_release_mutex;
+ }
+
+ ret = scmi_transport_read_message(proto->transport, proto->tx, reply);
+ if (ret < 0) {
+ LOG_ERR("failed to read reply");
+ goto out_release_mutex;
+ }
+
+out_release_mutex:
+ k_mutex_unlock(&proto->tx->lock);
+
+ return ret;
+}
+
+int scmi_send_message(struct scmi_protocol *proto, struct scmi_message *msg,
+ struct scmi_message *reply)
+{
+ if (!proto->tx) {
+ return -ENODEV;
+ }
+
+ if (!proto->tx->ready) {
+ return -EINVAL;
+ }
+
+ if (k_is_pre_kernel()) {
+ return scmi_send_message_pre_kernel(proto, msg, reply);
+ } else {
+ return scmi_send_message_post_kernel(proto, msg, reply);
+ }
+}
+
+static int scmi_core_protocol_setup(const struct device *transport)
+{
+ int ret;
+
+ STRUCT_SECTION_FOREACH(scmi_protocol, it) {
+ it->transport = transport;
+
+#ifndef CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS
+ /* no static channel allocation, attempt dynamic binding */
+ it->tx = scmi_transport_request_channel(transport, it->id, true);
+#endif /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */
+
+ if (!it->tx) {
+ return -ENODEV;
+ }
+
+ ret = scmi_core_setup_chan(transport, it->tx, true);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int scmi_core_transport_init(const struct device *transport)
+{
+ int ret;
+
+ ret = scmi_transport_init(transport);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return scmi_core_protocol_setup(transport);
+}
diff --git a/drivers/firmware/scmi/mailbox.c b/drivers/firmware/scmi/mailbox.c
new file mode 100644
index 0000000..2c61afa
--- /dev/null
+++ b/drivers/firmware/scmi/mailbox.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+#include "mailbox.h"
+
+LOG_MODULE_REGISTER(scmi_mbox);
+
+static void scmi_mbox_cb(const struct device *mbox,
+ mbox_channel_id_t channel_id,
+ void *user_data,
+ struct mbox_msg *data)
+{
+ struct scmi_channel *scmi_chan = user_data;
+
+ if (scmi_chan->cb)
+ scmi_chan->cb(scmi_chan);
+}
+
+static int scmi_mbox_send_message(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg)
+{
+ struct scmi_mbox_channel *mbox_chan;
+ int ret;
+
+ mbox_chan = chan->data;
+
+ ret = scmi_shmem_write_message(mbox_chan->shmem, msg);
+ if (ret < 0) {
+ LOG_ERR("failed to write message to shmem: %d", ret);
+ return ret;
+ }
+
+ ret = mbox_send_dt(&mbox_chan->tx, NULL);
+ if (ret < 0) {
+ LOG_ERR("failed to ring doorbell: %d", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int scmi_mbox_read_message(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg)
+{
+ struct scmi_mbox_channel *mbox_chan;
+
+ mbox_chan = chan->data;
+
+ return scmi_shmem_read_message(mbox_chan->shmem, msg);
+}
+
+static bool scmi_mbox_channel_is_free(const struct device *transport,
+ struct scmi_channel *chan)
+{
+ struct scmi_mbox_channel *mbox_chan = chan->data;
+
+ return scmi_shmem_channel_status(mbox_chan->shmem) &
+ SCMI_SHMEM_CHAN_STATUS_BUSY_BIT;
+}
+
+static int scmi_mbox_setup_chan(const struct device *transport,
+ struct scmi_channel *chan,
+ bool tx)
+{
+ int ret;
+ struct scmi_mbox_channel *mbox_chan;
+ struct mbox_dt_spec *tx_reply;
+
+ mbox_chan = chan->data;
+
+ if (!tx) {
+ return -ENOTSUP;
+ }
+
+ if (mbox_chan->tx_reply.dev) {
+ tx_reply = &mbox_chan->tx_reply;
+ } else {
+ tx_reply = &mbox_chan->tx;
+ }
+
+ ret = mbox_register_callback_dt(tx_reply, scmi_mbox_cb, chan);
+ if (ret < 0) {
+ LOG_ERR("failed to register tx reply cb");
+ return ret;
+ }
+
+ ret = mbox_set_enabled_dt(tx_reply, true);
+ if (ret < 0) {
+ LOG_ERR("failed to enable tx reply dbell");
+ }
+
+ /* enable interrupt-based communication */
+ scmi_shmem_update_flags(mbox_chan->shmem,
+ SCMI_SHMEM_CHAN_FLAG_IRQ_BIT,
+ SCMI_SHMEM_CHAN_FLAG_IRQ_BIT);
+
+ return 0;
+}
+
+static struct scmi_transport_api scmi_mbox_api = {
+ .setup_chan = scmi_mbox_setup_chan,
+ .send_message = scmi_mbox_send_message,
+ .read_message = scmi_mbox_read_message,
+ .channel_is_free = scmi_mbox_channel_is_free,
+};
+
+DT_INST_SCMI_MAILBOX_DEFINE(0, PRE_KERNEL_1,
+ CONFIG_ARM_SCMI_TRANSPORT_INIT_PRIORITY,
+ &scmi_mbox_api);
diff --git a/drivers/firmware/scmi/mailbox.h b/drivers/firmware/scmi/mailbox.h
new file mode 100644
index 0000000..4e758d8
--- /dev/null
+++ b/drivers/firmware/scmi/mailbox.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
+#define _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
+
+#include <zephyr/drivers/firmware/scmi/transport.h>
+#include <zephyr/drivers/firmware/scmi/util.h>
+#include <zephyr/drivers/firmware/scmi/shmem.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/kernel.h>
+
+#define DT_DRV_COMPAT arm_scmi
+
+/* get a `struct device` for a protocol's shared memory area */
+#define _SCMI_MBOX_SHMEM_BY_IDX(node_id, idx) \
+ COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
+ (DEVICE_DT_GET(DT_PROP_BY_IDX(node_id, shmem, idx))), \
+ (NULL))
+
+/* get the name of mailbox channel's private data */
+#define _SCMI_MBOX_CHAN_NAME(proto, idx)\
+ CONCAT(SCMI_TRANSPORT_CHAN_NAME(proto, idx), _, priv)
+
+/* fetch a mailbox channel's doorbell */
+#define _SCMI_MBOX_CHAN_DBELL(node_id, name) \
+ COND_CODE_1(DT_PROP_HAS_NAME(node_id, mboxes, name), \
+ (MBOX_DT_SPEC_GET(node_id, name)), \
+ ({ }))
+
+/* define private data for a protocol TX channel */
+#define _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto) \
+ static struct scmi_mbox_channel _SCMI_MBOX_CHAN_NAME(proto, 0) =\
+ { \
+ .shmem = _SCMI_MBOX_SHMEM_BY_IDX(node_id, 0), \
+ .tx = _SCMI_MBOX_CHAN_DBELL(node_id, tx), \
+ .tx_reply = _SCMI_MBOX_CHAN_DBELL(node_id, tx_reply), \
+ }
+
+/*
+ * Define a mailbox channel. This does two things:
+ * 1) Define the mandatory `struct scmi_channel` structure
+ * 2) Define the mailbox-specific private data for said
+ * channel (i.e: a struct scmi_mbox_channel)
+ */
+#define _SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx) \
+ _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto); \
+ DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, \
+ &(_SCMI_MBOX_CHAN_NAME(proto, idx))); \
+
+/*
+ * Optionally define a mailbox channel for a protocol. This is optional
+ * because a protocol might not have a dedicated channel.
+ */
+#define _SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, proto, idx) \
+ COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
+ (_SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx)), \
+ ())
+
+/* define a TX channel for a protocol node. This is preferred over
+ * _SCMI_MBOX_CHAN_DEFINE_OPTIONAL() since support for RX channels
+ * might be added later on. This macro is supposed to also define
+ * the RX channel
+ */
+#define SCMI_MBOX_PROTO_CHAN_DEFINE(node_id)\
+ _SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, DT_REG_ADDR(node_id), 0)
+
+/* define and validate base protocol TX channel */
+#define DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \
+ BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 1 || \
+ (DT_INST_PROP_HAS_IDX(inst, shmem, 0) && \
+ DT_INST_PROP_HAS_NAME(inst, mboxes, tx)), \
+ "bad bidirectional channel description"); \
+ \
+ BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 2 || \
+ (DT_INST_PROP_HAS_NAME(inst, mboxes, tx) && \
+ DT_INST_PROP_HAS_NAME(inst, mboxes, tx_reply)), \
+ "bad unidirectional channel description"); \
+ \
+ BUILD_ASSERT(DT_INST_PROP_LEN(inst, shmem) == 1, \
+ "bad SHMEM count"); \
+ \
+ BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) <= 2, \
+ "bad mbox count"); \
+ \
+ _SCMI_MBOX_CHAN_DEFINE(DT_INST(inst, DT_DRV_COMPAT), SCMI_PROTOCOL_BASE, 0)
+
+/*
+ * Define the mailbox-based transport layer. What this does is:
+ *
+ * 1) Goes through all protocol nodes (children of the `scmi` node)
+ * and creates a `struct scmi_channel` and its associated
+ * `struct scmi_mbox_channel` if the protocol has a dedicated channel.
+ *
+ * 2) Creates aforementioned structures for the base protocol
+ * (identified by the `scmi` node)
+ *
+ * 3) "registers" the driver via `DT_INST_SCMI_TRANSPORT_DEFINE()`.
+ */
+#define DT_INST_SCMI_MAILBOX_DEFINE(inst, level, prio, api) \
+ DT_INST_FOREACH_CHILD_STATUS_OKAY(inst, SCMI_MBOX_PROTO_CHAN_DEFINE) \
+ DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \
+ DT_INST_SCMI_TRANSPORT_DEFINE(inst, NULL, NULL, NULL, level, prio, api)
+
+struct scmi_mbox_channel {
+ /* SHMEM area bound to the channel */
+ const struct device *shmem;
+ /* TX dbell */
+ struct mbox_dt_spec tx;
+ /* TX reply dbell */
+ struct mbox_dt_spec tx_reply;
+};
+
+#endif /* _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_ */
diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c
new file mode 100644
index 0000000..fd0ef80
--- /dev/null
+++ b/drivers/firmware/scmi/pinctrl.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/pinctrl.h>
+
+DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, arm_scmi_pinctrl), NULL);
+
+int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings)
+{
+ struct scmi_protocol *proto;
+ struct scmi_message msg, reply;
+ uint32_t config_num;
+ int32_t status, ret;
+
+ proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_PINCTRL);
+
+ /* sanity checks */
+ if (!settings) {
+ return -EINVAL;
+ }
+
+ if (!proto) {
+ return -EINVAL;
+ }
+
+ if (proto->id != SCMI_PROTOCOL_PINCTRL) {
+ return -EINVAL;
+ }
+
+ config_num = SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(settings->attributes);
+
+ if (!config_num) {
+ return -EINVAL;
+ }
+
+ if ((config_num * 2) > ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE) {
+ return -EINVAL;
+ }
+
+ msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_CONFIGURE,
+ SCMI_COMMAND, proto->id, 0x0);
+ msg.len = sizeof(*settings) -
+ (ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE - config_num * 2) * 4;
+ msg.content = settings;
+
+ reply.hdr = msg.hdr;
+ reply.len = sizeof(status);
+ reply.content = &status;
+
+ ret = scmi_send_message(proto, &msg, &reply);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (status != SCMI_SUCCESS) {
+ return scmi_status_to_errno(status);
+ }
+
+ return 0;
+}
diff --git a/drivers/firmware/scmi/shmem.c b/drivers/firmware/scmi/shmem.c
new file mode 100644
index 0000000..6ec645c
--- /dev/null
+++ b/drivers/firmware/scmi/shmem.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/shmem.h>
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+#include <zephyr/logging/log.h>
+#include <string.h>
+
+LOG_MODULE_REGISTER(arm_scmi_shmem);
+
+#define DT_DRV_COMPAT arm_scmi_shmem
+
+#ifndef DEVICE_MMIO_IS_IN_RAM
+#define device_map(virt, phys, size, flags) *(virt) = (phys)
+#endif /* DEVICE_MMIO_IS_IN_RAM */
+
+struct scmi_shmem_config {
+ uintptr_t phys_addr;
+ uint32_t size;
+};
+
+struct scmi_shmem_data {
+ mm_reg_t regmap;
+};
+
+struct scmi_shmem_layout {
+ volatile uint32_t res0;
+ volatile uint32_t chan_status;
+ volatile uint32_t res1[2];
+ volatile uint32_t chan_flags;
+ volatile uint32_t len;
+ volatile uint32_t msg_hdr;
+};
+
+int scmi_shmem_get_channel_status(const struct device *dev, uint32_t *status)
+{
+ struct scmi_shmem_data *data;
+ struct scmi_shmem_layout *layout;
+
+ data = dev->data;
+ layout = (struct scmi_shmem_layout *)data->regmap;
+
+ *status = layout->chan_status;
+
+ return 0;
+}
+
+static void scmi_shmem_memcpy(mm_reg_t dst, mm_reg_t src, uint32_t bytes)
+{
+ int i;
+
+ for (i = 0; i < bytes; i++) {
+ sys_write8(*(uint8_t *)(src + i), dst + i);
+ }
+}
+
+int scmi_shmem_read_message(const struct device *shmem, struct scmi_message *msg)
+{
+ struct scmi_shmem_layout *layout;
+ struct scmi_shmem_data *data;
+ const struct scmi_shmem_config *cfg;
+
+ data = shmem->data;
+ cfg = shmem->config;
+ layout = (struct scmi_shmem_layout *)data->regmap;
+
+ /* some sanity checks first */
+ if (!msg) {
+ return -EINVAL;
+ }
+
+ if (!msg->content && msg->len) {
+ return -EINVAL;
+ }
+
+ if (cfg->size < (sizeof(*layout) + msg->len)) {
+ LOG_ERR("message doesn't fit in shmem area");
+ return -EINVAL;
+ }
+
+ /* mismatch between expected reply size and actual size? */
+ if (msg->len != (layout->len - sizeof(layout->msg_hdr))) {
+ LOG_ERR("bad message len. Expected 0x%x, got 0x%x",
+ msg->len,
+ (uint32_t)(layout->len - sizeof(layout->msg_hdr)));
+ return -EINVAL;
+ }
+
+ /* header match? */
+ if (layout->msg_hdr != msg->hdr) {
+ LOG_ERR("bad message header. Expected 0x%x, got 0x%x",
+ msg->hdr, layout->msg_hdr);
+ return -EINVAL;
+ }
+
+ if (msg->content) {
+ scmi_shmem_memcpy(POINTER_TO_UINT(msg->content),
+ data->regmap + sizeof(*layout), msg->len);
+ }
+
+ return 0;
+}
+
+int scmi_shmem_write_message(const struct device *shmem, struct scmi_message *msg)
+{
+ struct scmi_shmem_layout *layout;
+ struct scmi_shmem_data *data;
+ const struct scmi_shmem_config *cfg;
+
+ data = shmem->data;
+ cfg = shmem->config;
+ layout = (struct scmi_shmem_layout *)data->regmap;
+
+ /* some sanity checks first */
+ if (!msg) {
+ return -EINVAL;
+ }
+
+ if (!msg->content && msg->len) {
+ return -EINVAL;
+ }
+
+ if (cfg->size < (sizeof(*layout) + msg->len)) {
+ return -EINVAL;
+ }
+
+ if (!(layout->chan_status & SCMI_SHMEM_CHAN_STATUS_BUSY_BIT)) {
+ return -EBUSY;
+ }
+
+ layout->len = sizeof(layout->msg_hdr) + msg->len;
+ layout->msg_hdr = msg->hdr;
+
+ if (msg->content) {
+ scmi_shmem_memcpy(data->regmap + sizeof(*layout),
+ POINTER_TO_UINT(msg->content), msg->len);
+ }
+
+ /* done, mark channel as busy and proceed */
+ layout->chan_status &= ~SCMI_SHMEM_CHAN_STATUS_BUSY_BIT;
+
+ return 0;
+}
+
+uint32_t scmi_shmem_channel_status(const struct device *shmem)
+{
+ struct scmi_shmem_layout *layout;
+ struct scmi_shmem_data *data;
+
+ data = shmem->data;
+ layout = (struct scmi_shmem_layout *)data->regmap;
+
+ return layout->chan_status;
+}
+
+void scmi_shmem_update_flags(const struct device *shmem, uint32_t mask, uint32_t val)
+{
+ struct scmi_shmem_layout *layout;
+ struct scmi_shmem_data *data;
+
+ data = shmem->data;
+ layout = (struct scmi_shmem_layout *)data->regmap;
+
+ layout->chan_flags = (layout->chan_flags & ~mask) | (val & mask);
+}
+
+static int scmi_shmem_init(const struct device *dev)
+{
+ const struct scmi_shmem_config *cfg;
+ struct scmi_shmem_data *data;
+
+ cfg = dev->config;
+ data = dev->data;
+
+ if (cfg->size < sizeof(struct scmi_shmem_layout)) {
+ return -EINVAL;
+ }
+
+ device_map(&data->regmap, cfg->phys_addr, cfg->size, K_MEM_CACHE_NONE);
+
+ return 0;
+}
+
+#define SCMI_SHMEM_INIT(inst) \
+static const struct scmi_shmem_config config_##inst = { \
+ .phys_addr = DT_INST_REG_ADDR(inst), \
+ .size = DT_INST_REG_SIZE(inst), \
+}; \
+ \
+static struct scmi_shmem_data data_##inst; \
+ \
+DEVICE_DT_INST_DEFINE(inst, &scmi_shmem_init, NULL, \
+ &data_##inst, &config_##inst, \
+ PRE_KERNEL_1, \
+ CONFIG_ARM_SCMI_SHMEM_INIT_PRIORITY, \
+ NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(SCMI_SHMEM_INIT);
diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig
index aae29ac..f2a8cba 100644
--- a/drivers/flash/Kconfig
+++ b/drivers/flash/Kconfig
@@ -86,10 +86,6 @@
if FLASH
-module = FLASH
-module-str = flash
-source "subsys/logging/Kconfig.template.log_config"
-
config FLASH_JESD216_API
bool "Provide API to read JESD216 flash parameters"
depends on FLASH_JESD216
@@ -239,4 +235,8 @@
source "drivers/flash/Kconfig.numaker_rmc"
+module = FLASH
+module-str = flash
+source "subsys/logging/Kconfig.template.log_config"
+
endif # FLASH
diff --git a/drivers/flash/Kconfig.mcux b/drivers/flash/Kconfig.mcux
index 7b3df83..22695be 100644
--- a/drivers/flash/Kconfig.mcux
+++ b/drivers/flash/Kconfig.mcux
@@ -106,4 +106,9 @@
This prevents faults when the data to write would be located on the
flash itself.
+# Avoid RWW hazards by defaulting logging to disabled
+choice FLASH_LOG_LEVEL_CHOICE
+ default FLASH_LOG_LEVEL_OFF if FLASH_MCUX_FLEXSPI_XIP
+endchoice
+
endif # HAS_MCUX_FLEXSPI
diff --git a/drivers/flash/flash_cadence_qspi_nor_ll.c b/drivers/flash/flash_cadence_qspi_nor_ll.c
index d997c42..b41c7b7 100644
--- a/drivers/flash/flash_cadence_qspi_nor_ll.c
+++ b/drivers/flash/flash_cadence_qspi_nor_ll.c
@@ -133,8 +133,9 @@
do {
uint32_t reg = sys_read32(cad_params->reg_base + CAD_QSPI_FLASHCMD);
- if (!(reg & CAD_QSPI_FLASHCMD_EXECUTE_STAT))
+ if (!(reg & CAD_QSPI_FLASHCMD_EXECUTE_STAT)) {
break;
+ }
count++;
} while (count < CAD_QSPI_COMMAND_TIMEOUT);
@@ -172,8 +173,9 @@
return -1;
}
- if ((num_bytes > 8) || (num_bytes == 0))
+ if ((num_bytes > 8) || (num_bytes == 0)) {
return -1;
+ }
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@@ -208,8 +210,9 @@
return -1;
}
- if ((num_bytes > 8) || (num_bytes == 0))
+ if ((num_bytes > 8) || (num_bytes == 0)) {
return -1;
+ }
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@@ -225,8 +228,9 @@
sys_write32(input[0], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA0);
- if (num_bytes > 4)
+ if (num_bytes > 4) {
sys_write32(input[1], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA1);
+ }
return cad_qspi_stig_cmd_helper(cad_params, cad_params->cad_qspi_cs, cmd);
}
@@ -236,8 +240,9 @@
{
uint32_t cmd;
- if (dummy > ((1 << CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX) - 1))
+ if (dummy > ((1 << CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX) - 1)) {
return -1;
+ }
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@@ -576,11 +581,13 @@
return -EINVAL;
}
- if (cad_qspi_idle(cad_params) == 0)
+ if (cad_qspi_idle(cad_params) == 0) {
return -1;
+ }
- if ((CAD_QSPI_INT_STATUS_ALL & mask) == 0)
+ if ((CAD_QSPI_INT_STATUS_ALL & mask) == 0) {
return -1;
+ }
sys_write32(mask, cad_params->reg_base + CAD_QSPI_IRQMSK);
return 0;
diff --git a/drivers/flash/flash_mspi_atxp032.c b/drivers/flash/flash_mspi_atxp032.c
index d722a4c..b69c796e 100644
--- a/drivers/flash/flash_mspi_atxp032.c
+++ b/drivers/flash/flash_mspi_atxp032.c
@@ -180,13 +180,14 @@
if (cfg->sw_multi_periph) {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
+ MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
+ }
} else {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_NONE, NULL))
+ MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
-
+ }
}
}
@@ -195,8 +196,9 @@
const struct flash_mspi_atxp032_config *cfg = flash->config;
struct flash_mspi_atxp032_data *data = flash->data;
- while (mspi_get_channel_status(cfg->bus, cfg->port))
+ while (mspi_get_channel_status(cfg->bus, cfg->port)) {
;
+ }
k_sem_give(&data->lock);
}
diff --git a/drivers/flash/flash_mspi_emul_device.c b/drivers/flash/flash_mspi_emul_device.c
index f6c21f6..1bfefd3 100644
--- a/drivers/flash/flash_mspi_emul_device.c
+++ b/drivers/flash/flash_mspi_emul_device.c
@@ -63,13 +63,14 @@
k_sem_take(&data->lock, K_FOREVER);
if (cfg->sw_multi_periph) {
while (mspi_dev_config(data->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
+ MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
+ }
} else {
while (mspi_dev_config(data->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_NONE, NULL))
+ MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
-
+ }
}
}
diff --git a/drivers/flash/flash_rpi_pico.c b/drivers/flash/flash_rpi_pico.c
index 01ace5f..4b7dac9 100644
--- a/drivers/flash/flash_rpi_pico.c
+++ b/drivers/flash/flash_rpi_pico.c
@@ -65,8 +65,9 @@
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void)
{
- if (boot2_copyout_valid)
+ if (boot2_copyout_valid) {
return;
+ }
for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
boot2_copyout[i] = ((uint32_t *)FLASH_BASE)[i];
__compiler_memory_barrier();
@@ -124,8 +125,9 @@
}
}
- if (!did_something && __builtin_expect(flash_was_aborted(), 0))
+ if (!did_something && __builtin_expect(flash_was_aborted(), 0)) {
break;
+ }
}
flash_cs_force(OUTOVER_HIGH);
}
diff --git a/drivers/flash/flash_simulator.c b/drivers/flash/flash_simulator.c
index 204da43..1041bc3 100644
--- a/drivers/flash/flash_simulator.c
+++ b/drivers/flash/flash_simulator.c
@@ -437,14 +437,14 @@
#ifdef CONFIG_ARCH_POSIX
-static void flash_native_posix_cleanup(void)
+static void flash_native_cleanup(void)
{
flash_mock_cleanup_native(flash_in_ram, flash_fd, mock_flash,
FLASH_SIMULATOR_FLASH_SIZE, flash_file_path,
flash_rm_at_exit);
}
-static void flash_native_posix_options(void)
+static void flash_native_options(void)
{
static struct args_struct_t flash_options[] = {
{ .option = "flash",
@@ -476,9 +476,8 @@
native_add_command_line_opts(flash_options);
}
-
-NATIVE_TASK(flash_native_posix_options, PRE_BOOT_1, 1);
-NATIVE_TASK(flash_native_posix_cleanup, ON_EXIT, 1);
+NATIVE_TASK(flash_native_options, PRE_BOOT_1, 1);
+NATIVE_TASK(flash_native_cleanup, ON_EXIT, 1);
#endif /* CONFIG_ARCH_POSIX */
diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c
index c893545..e852f74 100644
--- a/drivers/flash/flash_stm32_ospi.c
+++ b/drivers/flash/flash_stm32_ospi.c
@@ -987,7 +987,7 @@
HAL_StatusTypeDef ret;
const struct flash_stm32_ospi_config *dev_cfg = dev->config;
struct flash_stm32_ospi_data *dev_data = dev->data;
- OSPI_RegularCmdTypeDef s_command;
+ OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
OSPI_MemoryMappedTypeDef s_MemMappedCfg;
/* Configure octoflash in MemoryMapped mode */
@@ -995,87 +995,108 @@
(stm32_ospi_hal_address_size(dev) == HAL_OSPI_ADDRESS_24_BITS)) {
/* OPI mode and 3-bytes address size not supported by memory */
LOG_ERR("OSPI_SPI_MODE in 3Bytes addressing is not supported");
- return -EIO;
+ return -ENOTSUP;
}
/* Initialize the read command */
s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
- s_command.FlashId = HAL_OSPI_FLASH_ID_1;
- s_command.InstructionMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? HAL_OSPI_INSTRUCTION_1_LINE
- : HAL_OSPI_INSTRUCTION_8_LINES)
- : HAL_OSPI_INSTRUCTION_8_LINES;
- s_command.InstructionDtrMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? HAL_OSPI_INSTRUCTION_DTR_DISABLE
- : HAL_OSPI_INSTRUCTION_DTR_ENABLE;
- s_command.InstructionSize = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? HAL_OSPI_INSTRUCTION_8_BITS
- : HAL_OSPI_INSTRUCTION_16_BITS)
- : HAL_OSPI_INSTRUCTION_16_BITS;
- s_command.Instruction = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? ((stm32_ospi_hal_address_size(dev) ==
- HAL_OSPI_ADDRESS_24_BITS)
- ? SPI_NOR_CMD_READ_FAST
- : SPI_NOR_CMD_READ_FAST_4B)
- : dev_data->read_opcode)
- : SPI_NOR_OCMD_DTR_RD;
- s_command.AddressMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? HAL_OSPI_ADDRESS_1_LINE
- : HAL_OSPI_ADDRESS_8_LINES)
- : HAL_OSPI_ADDRESS_8_LINES;
- s_command.AddressDtrMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? HAL_OSPI_ADDRESS_DTR_DISABLE
- : HAL_OSPI_ADDRESS_DTR_ENABLE;
s_command.AddressSize = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
? stm32_ospi_hal_address_size(dev)
: HAL_OSPI_ADDRESS_32_BITS;
- s_command.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
- s_command.DataMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? HAL_OSPI_DATA_1_LINE
- : HAL_OSPI_DATA_8_LINES)
- : HAL_OSPI_DATA_8_LINES;
- s_command.DataDtrMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? HAL_OSPI_DATA_DTR_DISABLE
- : HAL_OSPI_DATA_DTR_ENABLE;
- s_command.DummyCycles = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? ((dev_cfg->data_mode == OSPI_SPI_MODE)
- ? SPI_NOR_DUMMY_RD
- : SPI_NOR_DUMMY_RD_OCTAL)
- : SPI_NOR_DUMMY_RD_OCTAL_DTR;
- s_command.DQSMode = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
- ? HAL_OSPI_DQS_DISABLE
- : HAL_OSPI_DQS_ENABLE;
-
- s_command.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
+ /* Adapt lines based on read_mode */
+ if (dev_cfg->data_mode != OSPI_OPI_MODE) {
+ switch (dev_data->read_mode) {
+ case JESD216_MODE_112:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
+ s_command.DataMode = HAL_OSPI_DATA_2_LINES;
+ break;
+ case JESD216_MODE_122:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
+ s_command.DataMode = HAL_OSPI_DATA_2_LINES;
+ break;
+ case JESD216_MODE_114:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
+ s_command.DataMode = HAL_OSPI_DATA_4_LINES;
+ break;
+ case JESD216_MODE_144:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
+ s_command.DataMode = HAL_OSPI_DATA_4_LINES;
+ break;
+ default:
+ /* Use lines based on data_mode set in ospi_prepare_cmd */
+ break;
+ }
+ }
+ /* Set instruction and dummy cycles parameters */
+ if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
+ /* DTR transfer rate (==> Octal mode) */
+ s_command.Instruction = SPI_NOR_OCMD_DTR_RD;
+ s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
+ } else {
+ /* STR transfer rate */
+ if (dev_cfg->data_mode == OSPI_OPI_MODE) {
+ /* OPI and STR */
+ s_command.Instruction = SPI_NOR_OCMD_RD;
+ s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
+ } else {
+ /* use SFDP:BFP read instruction */
+ s_command.Instruction = dev_data->read_opcode;
+ s_command.DummyCycles = dev_data->read_dummy;
+ }
+ }
ret = HAL_OSPI_Command(&dev_data->hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
if (ret != HAL_OK) {
- LOG_ERR("%d: Failed to set memory map", ret);
+ LOG_ERR("%d: Failed to set memory map read cmd", ret);
return -EIO;
}
/* Initialize the program command */
s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
- if (dev_cfg->data_rate == OSPI_STR_TRANSFER) {
- s_command.Instruction = (dev_cfg->data_mode == OSPI_SPI_MODE)
- ? ((stm32_ospi_hal_address_size(dev) ==
- HAL_OSPI_ADDRESS_24_BITS)
- ? SPI_NOR_CMD_PP
- : SPI_NOR_CMD_PP_4B)
- : SPI_NOR_OCMD_PAGE_PRG;
- } else {
- s_command.Instruction = SPI_NOR_OCMD_PAGE_PRG;
- }
s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
+ s_command.Instruction = dev_data->write_opcode;
+ s_command.DummyCycles = 0U;
+ /* Adapt lines based on write opcode */
+ switch (s_command.Instruction) {
+ case SPI_NOR_CMD_PP_4B:
+ __fallthrough;
+ case SPI_NOR_CMD_PP:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
+ s_command.DataMode = HAL_OSPI_DATA_1_LINE;
+ break;
+ case SPI_NOR_CMD_PP_1_1_2:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
+ s_command.DataMode = HAL_OSPI_DATA_2_LINES;
+ break;
+ case SPI_NOR_CMD_PP_1_1_4_4B:
+ __fallthrough;
+ case SPI_NOR_CMD_PP_1_1_4:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
+ s_command.DataMode = HAL_OSPI_DATA_4_LINES;
+ break;
+ case SPI_NOR_CMD_PP_1_4_4_4B:
+ __fallthrough;
+ case SPI_NOR_CMD_PP_1_4_4:
+ s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
+ s_command.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
+ s_command.DataMode = HAL_OSPI_DATA_4_LINES;
+ break;
+ default:
+ /* Use lines based on data_mode set in ospi_prepare_cmd */
+ break;
+ }
+
ret = HAL_OSPI_Command(&dev_data->hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
if (ret != HAL_OK) {
- LOG_ERR("%d: Failed to set memory mapped", ret);
+ LOG_ERR("%d: Failed to set memory map write cmd", ret);
return -EIO;
}
@@ -1084,11 +1105,11 @@
ret = HAL_OSPI_MemoryMapped(&dev_data->hospi, &s_MemMappedCfg);
if (ret != HAL_OK) {
- LOG_ERR("%d: Failed to set memory mapped", ret);
+ LOG_ERR("%d: Failed to enable memory map", ret);
return -EIO;
}
- LOG_INF("MemoryMap mode enabled");
+ LOG_DBG("MemoryMap mode enabled");
return 0;
}
diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c
index 0ce6d4e..64c604d 100644
--- a/drivers/flash/flash_stm32_qspi.c
+++ b/drivers/flash/flash_stm32_qspi.c
@@ -35,7 +35,7 @@
#define STM32_QSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)
#define STM32_QSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
-#define STM32_QSPI_RESET_CMD DT_PROP(DT_NODELABEL(quadspi), set_cmd)
+#define STM32_QSPI_RESET_CMD DT_INST_PROP(0, reset_cmd)
#include <stm32_ll_dma.h>
@@ -336,8 +336,10 @@
return -EIO;
}
+ LOG_DBG("Read JESD216-ID");
+
dev_data->cmd_status = 0;
- id = &data[0];
+ memcpy(id, data, JESD216_READ_ID_LEN);
return 0;
}
@@ -1270,6 +1272,9 @@
LOG_ERR("%d: Failed to send RESET_MEM", ret);
return ret;
}
+
+ LOG_DBG("Send Reset command");
+
return 0;
}
#endif
diff --git a/drivers/flash/flash_stm32h7x.c b/drivers/flash/flash_stm32h7x.c
index 620a855..afba8bc 100644
--- a/drivers/flash/flash_stm32h7x.c
+++ b/drivers/flash/flash_stm32h7x.c
@@ -189,6 +189,18 @@
}
regs->CCR2 = FLASH_FLAG_ALL_BANK2;
if (sr & error_bank2) {
+ /* Sometimes the STRBERR is seen when writing to flash
+ * from M4 (upper 128KiB) with code running from lower
+ * 896KiB. Don't know why it happens, but technical
+ * reference manual (section 4.7.4) says application can
+ * ignore this error and continue with normal write. So
+ * check and return here if the error is STRBERR and clear
+ * the error by setting CCR2 bit.
+ */
+ if (sr & FLASH_FLAG_STRBERR_BANK2) {
+ regs->CCR2 |= FLASH_FLAG_STRBERR_BANK2;
+ return 0;
+ }
LOG_ERR("Status Bank%d: 0x%08x", 2, sr);
return -EIO;
}
diff --git a/drivers/flash/soc_flash_cc13xx_cc26xx.c b/drivers/flash/soc_flash_cc13xx_cc26xx.c
index 893a280..c1cabf0 100644
--- a/drivers/flash/soc_flash_cc13xx_cc26xx.c
+++ b/drivers/flash/soc_flash_cc13xx_cc26xx.c
@@ -43,8 +43,9 @@
static void flash_cc13xx_cc26xx_cache_restore(uint32_t vims_mode)
{
- while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING)
+ while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
;
+ }
/* Restore VIMS mode and line buffers */
if (vims_mode != VIMS_MODE_DISABLED) {
@@ -61,8 +62,9 @@
/* VIMS and both line buffers should be off during flash update */
VIMSLineBufDisable(VIMS_BASE);
- while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING)
+ while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
;
+ }
/* Save current VIMS mode for restoring it later */
vims_mode = VIMSModeGet(VIMS_BASE);
@@ -139,8 +141,9 @@
/* Erase sector/page one by one, break out in case of an error */
cnt = size / FLASH_ERASE_SIZE;
for (i = 0; i < cnt; i++, offs += FLASH_ERASE_SIZE) {
- while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY)
+ while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
;
+ }
rc = FlashSectorErase(offs);
if (rc != FAPI_STATUS_SUCCESS) {
@@ -200,8 +203,9 @@
key = irq_lock();
- while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY)
+ while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
;
+ }
rc = FlashProgram((uint8_t *)data, offs, size);
if (rc != FAPI_STATUS_SUCCESS) {
rc = -EIO;
diff --git a/drivers/fpga/fpga_altera_agilex_bridge.c b/drivers/fpga/fpga_altera_agilex_bridge.c
index b593cc1..ca71c3d 100644
--- a/drivers/fpga/fpga_altera_agilex_bridge.c
+++ b/drivers/fpga/fpga_altera_agilex_bridge.c
@@ -270,18 +270,21 @@
return MBOX_CONFIG_STATUS_STATE_CONFIG;
}
- if (ret && ret != MBOX_CONFIG_STATUS_STATE_CONFIG)
+ if (ret && ret != MBOX_CONFIG_STATUS_STATE_CONFIG) {
return ret;
+ }
/* Make sure nStatus is not 0 */
ret = reconfig_status_resp->pin_status.pin_status;
- if (!(ret & RECONFIG_PIN_STATUS_NSTATUS))
+ if (!(ret & RECONFIG_PIN_STATUS_NSTATUS)) {
return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+ }
ret = reconfig_status_resp->soft_function_status;
if ((ret & RECONFIG_SOFTFUNC_STATUS_CONF_DONE) &&
- (ret & RECONFIG_SOFTFUNC_STATUS_INIT_DONE) && !reconfig_status_resp->state)
+ (ret & RECONFIG_SOFTFUNC_STATUS_INIT_DONE) && !reconfig_status_resp->state) {
return 0; /* Configuration success */
+ }
return MBOX_CONFIG_STATUS_STATE_CONFIG;
}
diff --git a/drivers/fpga/fpga_eos_s3.c b/drivers/fpga/fpga_eos_s3.c
index 30841dd..452735a 100644
--- a/drivers/fpga/fpga_eos_s3.c
+++ b/drivers/fpga/fpga_eos_s3.c
@@ -36,8 +36,9 @@
if (PMU->FB_STATUS == FPGA_STATUS_ACTIVE) {
return FPGA_STATUS_ACTIVE;
- } else
+ } else {
return FPGA_STATUS_INACTIVE;
+ }
}
static const char *eos_s3_fpga_get_info(const struct device *dev)
diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt
index 8a8dd71..90579a9 100644
--- a/drivers/gpio/CMakeLists.txt
+++ b/drivers/gpio/CMakeLists.txt
@@ -66,7 +66,7 @@
zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL64XXA gpio_pcal64xxa.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c)
-zephyr_library_sources_ifdef(CONFIG_GPIO_RA8 gpio_renesas_ra8.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 16252b2..54d45ef 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -155,7 +155,7 @@
source "drivers/gpio/Kconfig.psoc6"
source "drivers/gpio/Kconfig.rcar"
source "drivers/gpio/Kconfig.renesas_ra"
-source "drivers/gpio/Kconfig.renesas_ra8"
+source "drivers/gpio/Kconfig.renesas_ra_ioport"
source "drivers/gpio/Kconfig.rpi_pico"
source "drivers/gpio/Kconfig.rt1718s"
source "drivers/gpio/Kconfig.rv32m1"
diff --git a/drivers/gpio/Kconfig.renesas_ra8 b/drivers/gpio/Kconfig.renesas_ra8
deleted file mode 100644
index 81e5fbc..0000000
--- a/drivers/gpio/Kconfig.renesas_ra8
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config GPIO_RA8
- bool "Renesas RA8 GPIO driver"
- default y
- depends on DT_HAS_RENESAS_RA8_GPIO_ENABLED
- help
- Enable the Renesas RA8 GPIO driver.
diff --git a/drivers/gpio/Kconfig.renesas_ra_ioport b/drivers/gpio/Kconfig.renesas_ra_ioport
new file mode 100644
index 0000000..c09361c
--- /dev/null
+++ b/drivers/gpio/Kconfig.renesas_ra_ioport
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_RA_IOPORT
+ bool "Renesas RA GPIO IO port driver"
+ default y
+ depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED
+ help
+ Enable the Renesas RA GPIO IO port driver.
diff --git a/drivers/gpio/gpio_esp32.c b/drivers/gpio/gpio_esp32.c
index 7a1b679..db181dd 100644
--- a/drivers/gpio/gpio_esp32.c
+++ b/drivers/gpio/gpio_esp32.c
@@ -20,7 +20,9 @@
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32C6)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
@@ -33,7 +35,15 @@
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
-#ifdef CONFIG_SOC_SERIES_ESP32C3
+#ifdef CONFIG_SOC_SERIES_ESP32C2
+#define out out.val
+#define in in.val
+#define out_w1ts out_w1ts.val
+#define out_w1tc out_w1tc.val
+/* arch_curr_cpu() is not available for riscv based chips */
+#define CPU_ID() 0
+#define ISR_HANDLER isr_handler_t
+#elif CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data
#define in in.data
@@ -468,12 +478,18 @@
static bool isr_connected;
if (!isr_connected) {
- esp_intr_alloc(DT_IRQN(DT_NODELABEL(gpio0)),
- 0,
+ int ret = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, flags)),
(ISR_HANDLER)gpio_esp32_isr,
(void *)dev,
NULL);
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ return ret;
+ }
+
isr_connected = true;
}
diff --git a/drivers/gpio/gpio_max32.c b/drivers/gpio/gpio_max32.c
index 66f5d15..939a2a6 100644
--- a/drivers/gpio/gpio_max32.c
+++ b/drivers/gpio/gpio_max32.c
@@ -101,8 +101,8 @@
} else if (flags & GPIO_INPUT) {
gpio_cfg.func = MXC_GPIO_FUNC_IN;
} else {
- /* this case will not occur this function call for gpio mode in/out */
- gpio_cfg.func = MXC_GPIO_FUNC_ALT1; /* TODO: Think on it */
+ gpio_cfg.func = MXC_GPIO_FUNC_IN;
+ gpio_cfg.pad = MXC_GPIO_PAD_NONE;
}
if (flags & MAX32_GPIO_VSEL_VDDIOH) {
diff --git a/drivers/gpio/gpio_mcux_rgpio.c b/drivers/gpio/gpio_mcux_rgpio.c
index 16ad02c..ce0d3df 100644
--- a/drivers/gpio/gpio_mcux_rgpio.c
+++ b/drivers/gpio/gpio_mcux_rgpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2023, NXP
+ * Copyright 2023-2024, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -80,6 +80,39 @@
((size_t)config->pin_muxes[cfg_idx].config_register);
uint32_t reg = *gpio_cfg_reg;
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+ /* PUE/PDRV types have the same ODE bit */
+ if ((flags & GPIO_SINGLE_ENDED)) {
+ /* Set ODE bit */
+ reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
+ } else {
+ reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
+ }
+
+ if (config->pin_muxes[pin].pue_mux) {
+ if (flags & GPIO_PULL_UP) {
+ reg |= (IOMUXC_SW_PAD_CTL_PAD_PUS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK);
+ } else if (flags & GPIO_PULL_DOWN) {
+ reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
+ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
+ } else {
+ /* Set pin to highz */
+ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
+ }
+ } else {
+ /* PDRV type register layout */
+ if (flags & GPIO_PULL_UP) {
+ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
+ reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
+ } else if (flags & GPIO_PULL_DOWN) {
+ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
+ reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
+ } else {
+ /* Set pin to no pull */
+ reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
+ }
+ }
+#else
/* TODO: Default flags, work for i.MX 9352 */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
@@ -101,6 +134,7 @@
reg &= ~((0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |
(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT));
}
+#endif
memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg));
/* cfg register will be set by pinctrl_configure_pins */
diff --git a/drivers/gpio/gpio_pca95xx.c b/drivers/gpio/gpio_pca95xx.c
index f848912..2cfffe7 100644
--- a/drivers/gpio/gpio_pca95xx.c
+++ b/drivers/gpio/gpio_pca95xx.c
@@ -124,8 +124,9 @@
uint8_t b_buf;
int ret;
- if (pin >= 8)
+ if (pin >= 8) {
reg++;
+ }
ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf);
if (ret != 0) {
diff --git a/drivers/gpio/gpio_pcal64xxa.c b/drivers/gpio/gpio_pcal64xxa.c
index 93cc481..3ff6389 100644
--- a/drivers/gpio/gpio_pcal64xxa.c
+++ b/drivers/gpio/gpio_pcal64xxa.c
@@ -129,7 +129,7 @@
gpio_flags_t flags_io;
int rc;
- LOG_DBG("configure pin %i with flags 0x%08X", pin, flags);
+ LOG_DBG("%s: configure pin %i with flags 0x%08X", dev->name, pin, flags);
/* This device does not support open-source outputs, and open-drain
* outputs can be only configured port-wise.
@@ -182,7 +182,7 @@
if (rc == 0) {
drv_data->pins_cfg = pins_cfg;
} else {
- LOG_ERR("failed to apply pin config for device %s", dev->name);
+ LOG_ERR("%s: failed to apply pin config", dev->name);
}
k_sem_give(&drv_data->lock);
@@ -203,7 +203,7 @@
rc = drv_cfg->chip_api->inputs_read(&drv_cfg->i2c, &int_sources, &input_port);
if (rc != 0) {
- LOG_ERR("failed to read inputs from device %s", dev->name);
+ LOG_ERR("%s: failed to read inputs", dev->name);
k_sem_give(&drv_data->lock);
return rc;
}
@@ -293,8 +293,9 @@
int rc;
pcal64xxa_data_t output;
- LOG_DBG("setting port with mask 0x%" PRIpcal_data " with value 0x%" PRIpcal_data
- " and toggle 0x%" PRIpcal_data, mask, value, toggle);
+ LOG_DBG("%s: setting port with mask 0x%" PRIpcal_data " with value 0x%" PRIpcal_data
+ " and toggle 0x%" PRIpcal_data,
+ dev->name, mask, value, toggle);
if (k_is_in_isr()) {
return -EWOULDBLOCK;
@@ -325,7 +326,7 @@
}
static int pcal64xxa_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
- gpio_port_value_t value)
+ gpio_port_value_t value)
{
return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)mask, (pcal64xxa_data_t)value, 0);
}
@@ -346,14 +347,14 @@
}
static int pcal64xxa_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
- enum gpio_int_mode mode, enum gpio_int_trig trig)
+ enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_drv_data *drv_data = dev->data;
struct pcal64xxa_triggers triggers;
int rc;
- LOG_DBG("configure interrupt for pin %i", pin);
+ LOG_DBG("%s: configure interrupt for pin %i", dev->name, pin);
if (drv_cfg->gpio_interrupt.port == NULL) {
return -ENOTSUP;
@@ -394,7 +395,7 @@
if (rc == 0) {
drv_data->triggers = triggers;
} else {
- LOG_ERR("failed to apply triggers for device %s", dev->name);
+ LOG_ERR("%s: failed to apply triggers", dev->name);
}
k_sem_give(&drv_data->lock);
@@ -402,8 +403,8 @@
return rc;
}
-static int pcal64xxa_manage_callback(const struct device *dev,
- struct gpio_callback *callback, bool set)
+static int pcal64xxa_manage_callback(const struct device *dev, struct gpio_callback *callback,
+ bool set)
{
struct pcal64xxa_drv_data *drv_data = dev->data;
@@ -789,10 +790,11 @@
*/
if (drv_cfg->gpio_reset.port != NULL) {
if (!gpio_is_ready_dt(&drv_cfg->gpio_reset)) {
- LOG_ERR("reset gpio device is not ready");
+ LOG_ERR("%s: reset gpio device is not ready", dev->name);
return -ENODEV;
}
+ LOG_DBG("%s: trigger reset", dev->name);
rc = gpio_pin_configure_dt(&drv_cfg->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (rc != 0) {
LOG_ERR("%s: failed to configure RESET line: %d", dev->name, rc);
@@ -814,7 +816,7 @@
rc = drv_cfg->chip_api->reset_state_apply(&drv_cfg->i2c);
if (rc != 0) {
- LOG_ERR("failed to apply reset state to device %s", dev->name);
+ LOG_ERR("%s: failed to apply reset state", dev->name);
return rc;
}
}
@@ -822,7 +824,7 @@
/* Set initial configuration of the pins. */
rc = drv_cfg->chip_api->pins_cfg_apply(&drv_cfg->i2c, &initial_pins_cfg);
if (rc != 0) {
- LOG_ERR("failed to apply pin config for device %s", dev->name);
+ LOG_ERR("%s: failed to apply pin config", dev->name);
return rc;
}
@@ -839,7 +841,7 @@
/* Set initial state of the interrupt related registers. */
rc = drv_cfg->chip_api->triggers_apply(&drv_cfg->i2c, &initial_triggers);
if (rc != 0) {
- LOG_ERR("failed to apply triggers for device %s", dev->name);
+ LOG_ERR("%s: failed to apply triggers", dev->name);
return rc;
}
@@ -848,7 +850,7 @@
/* If the INT line is available, configure the callback for it. */
if (drv_cfg->gpio_interrupt.port != NULL) {
if (!gpio_is_ready_dt(&drv_cfg->gpio_interrupt)) {
- LOG_ERR("interrupt gpio device is not ready");
+ LOG_ERR("%s: interrupt gpio device is not ready", dev->name);
return -ENODEV;
}
@@ -882,13 +884,11 @@
#define PCAL64XXA_INIT_INT_GPIO_FIELDS(idx) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, int_gpios), \
- (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), int_gpios, 0)), \
- ({0}))
+ (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), int_gpios, 0)), ({0}))
#define PCAL64XXA_INIT_RESET_GPIO_FIELDS(idx) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, reset_gpios), \
- (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), reset_gpios, 0)), \
- ({0}))
+ (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), reset_gpios, 0)), ({0}))
#define GPIO_PCAL6408A_INST(idx) \
static const struct gpio_driver_api pcal6408a_drv_api##idx = { \
diff --git a/drivers/gpio/gpio_renesas_ra8.c b/drivers/gpio/gpio_renesas_ra8.c
deleted file mode 100644
index cdc24c1..0000000
--- a/drivers/gpio/gpio_renesas_ra8.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT renesas_ra8_gpio
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/pinctrl.h>
-#include <zephyr/dt-bindings/gpio/renesas-ra8-gpio.h>
-#include <zephyr/drivers/gpio/gpio_utils.h>
-#include <zephyr/irq.h>
-#include <soc.h>
-
-struct gpio_ra8_config {
- struct gpio_driver_config common;
- uint8_t port_num;
- R_PORT0_Type *port;
- gpio_pin_t vbatt_pins[];
-};
-
-struct gpio_ra8_data {
- struct gpio_driver_data common;
-};
-
-static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
-{
- const struct gpio_ra8_config *config = dev->config;
-
- struct ra_pinctrl_soc_pin pincfg = {0};
-
- if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
- return -ENOTSUP;
- }
-
- if ((flags & GPIO_PULL_DOWN) != 0U) {
- return -ENOTSUP;
- }
-
- if ((flags & GPIO_INT_ENABLE) != 0) {
- return -ENOTSUP;
- }
-
- if (config->vbatt_pins[0] != 0xFF) {
- uint32_t clear = 0;
-
- for (int i = 0; config->vbatt_pins[i] != '\0'; i++) {
- if (config->vbatt_pins[i] == pin) {
- WRITE_BIT(clear, i, 1);
- }
- }
-
- R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
-
- R_SYSTEM->VBTICTLR &= (uint8_t)~clear;
-
- R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
- }
-
- pincfg.port_num = config->port_num;
- pincfg.pin_num = pin;
-
- /* Change mode to general IO mode and disable IRQ and Analog input */
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PMR_Pos, 0);
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ASEL_Pos, 0);
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0);
-
- if ((flags & GPIO_OUTPUT) != 0U) {
- /* Set output pin initial value */
- if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 0);
- } else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1);
- }
-
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1);
- } else {
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 0);
- }
-
- if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_NCODR_Pos, 1);
- }
-
- if ((flags & GPIO_PULL_UP) != 0) {
- WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PCR_Pos, 1);
- }
-
- pincfg.cfg = pincfg.cfg |
- (((flags & RENESAS_GPIO_DS_MSK) >> 8) << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
-
- return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
-}
-
-static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value)
-{
- const struct gpio_ra8_config *config = dev->config;
- R_PORT0_Type *port = config->port;
-
- *value = port->PIDR;
-
- return 0;
-}
-
-static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
- gpio_port_value_t value)
-{
- const struct gpio_ra8_config *config = dev->config;
- R_PORT0_Type *port = config->port;
-
- port->PODR = ((port->PODR & ~mask) | (value & mask));
-
- return 0;
-}
-
-static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
- const struct gpio_ra8_config *config = dev->config;
- R_PORT0_Type *port = config->port;
-
- port->PODR = (port->PODR | pins);
-
- return 0;
-}
-
-static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
- const struct gpio_ra8_config *config = dev->config;
- R_PORT0_Type *port = config->port;
-
- port->PODR = (port->PODR & ~pins);
-
- return 0;
-}
-
-static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
-{
- const struct gpio_ra8_config *config = dev->config;
- R_PORT0_Type *port = config->port;
-
- port->PODR = (port->PODR ^ pins);
-
- return 0;
-}
-
-static const struct gpio_driver_api gpio_ra8_drv_api_funcs = {
- .pin_configure = gpio_ra8_pin_configure,
- .port_get_raw = gpio_ra8_port_get_raw,
- .port_set_masked_raw = gpio_ra8_port_set_masked_raw,
- .port_set_bits_raw = gpio_ra8_port_set_bits_raw,
- .port_clear_bits_raw = gpio_ra8_port_clear_bits_raw,
- .port_toggle_bits = gpio_ra8_port_toggle_bits,
- .pin_interrupt_configure = NULL,
- .manage_callback = NULL,
-};
-
-#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
- static const struct gpio_ra8_config gpio_ra8_config_##suffix = { \
- .common = \
- { \
- .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
- }, \
- .port_num = port_number, \
- .port = (R_PORT0_Type *)addr, \
- .vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \
- }; \
- static struct gpio_ra8_data gpio_ra8_data_##suffix; \
- DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra8_data_##suffix, \
- &gpio_ra8_config_##suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
- &gpio_ra8_drv_api_funcs)
-
-#define GPIO_DEVICE_INIT_RA8(suffix) \
- GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \
- DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \
- DT_REG_ADDR(DT_NODELABEL(ioport##suffix)))
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay)
-GPIO_DEVICE_INIT_RA8(0);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay)
-GPIO_DEVICE_INIT_RA8(1);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay)
-GPIO_DEVICE_INIT_RA8(2);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay)
-GPIO_DEVICE_INIT_RA8(3);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay)
-GPIO_DEVICE_INIT_RA8(4);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay)
-GPIO_DEVICE_INIT_RA8(5);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay)
-GPIO_DEVICE_INIT_RA8(6);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay)
-GPIO_DEVICE_INIT_RA8(7);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay)
-GPIO_DEVICE_INIT_RA8(8);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay)
-GPIO_DEVICE_INIT_RA8(9);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay)
-GPIO_DEVICE_INIT_RA8(a);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) */
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay)
-GPIO_DEVICE_INIT_RA8(b);
-#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) */
diff --git a/drivers/gpio/gpio_renesas_ra_ioport.c b/drivers/gpio/gpio_renesas_ra_ioport.c
new file mode 100644
index 0000000..b0869e1
--- /dev/null
+++ b/drivers/gpio/gpio_renesas_ra_ioport.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_gpio_ioport
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+
+struct gpio_ra_config {
+ struct gpio_driver_config common;
+ uint8_t port_num;
+ R_PORT0_Type *port;
+ gpio_pin_t vbatt_pins[];
+};
+
+struct gpio_ra_data {
+ struct gpio_driver_data common;
+};
+
+static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+ const struct gpio_ra_config *config = dev->config;
+
+ struct ra_pinctrl_soc_pin pincfg = {0};
+
+ if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
+ return -ENOTSUP;
+ }
+
+ if ((flags & GPIO_PULL_DOWN) != 0U) {
+ return -ENOTSUP;
+ }
+
+ if ((flags & GPIO_INT_ENABLE) != 0) {
+ return -ENOTSUP;
+ }
+
+ if (config->vbatt_pins[0] != 0xFF) {
+ uint32_t clear = 0;
+
+ for (int i = 0; config->vbatt_pins[i] != '\0'; i++) {
+ if (config->vbatt_pins[i] == pin) {
+ WRITE_BIT(clear, i, 1);
+ }
+ }
+
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+
+ R_SYSTEM->VBTICTLR &= (uint8_t)~clear;
+
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+ }
+
+ pincfg.port_num = config->port_num;
+ pincfg.pin_num = pin;
+
+ /* Change mode to general IO mode and disable IRQ and Analog input */
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PMR_Pos, 0);
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ASEL_Pos, 0);
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0);
+
+ if ((flags & GPIO_OUTPUT) != 0U) {
+ /* Set output pin initial value */
+ if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 0);
+ } else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1);
+ }
+
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1);
+ } else {
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 0);
+ }
+
+ if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_NCODR_Pos, 1);
+ }
+
+ if ((flags & GPIO_PULL_UP) != 0) {
+ WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PCR_Pos, 1);
+ }
+
+ pincfg.cfg = pincfg.cfg |
+ (((flags & RENESAS_GPIO_DS_MSK) >> 8) << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
+
+ return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
+}
+
+static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value)
+{
+ const struct gpio_ra_config *config = dev->config;
+ R_PORT0_Type *port = config->port;
+
+ *value = port->PIDR;
+
+ return 0;
+}
+
+static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+ gpio_port_value_t value)
+{
+ const struct gpio_ra_config *config = dev->config;
+ R_PORT0_Type *port = config->port;
+
+ port->PODR = ((port->PODR & ~mask) | (value & mask));
+
+ return 0;
+}
+
+static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+ const struct gpio_ra_config *config = dev->config;
+ R_PORT0_Type *port = config->port;
+
+ port->PODR = (port->PODR | pins);
+
+ return 0;
+}
+
+static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+ const struct gpio_ra_config *config = dev->config;
+ R_PORT0_Type *port = config->port;
+
+ port->PODR = (port->PODR & ~pins);
+
+ return 0;
+}
+
+static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+ const struct gpio_ra_config *config = dev->config;
+ R_PORT0_Type *port = config->port;
+
+ port->PODR = (port->PODR ^ pins);
+
+ return 0;
+}
+
+static const struct gpio_driver_api gpio_ra_drv_api_funcs = {
+ .pin_configure = gpio_ra_pin_configure,
+ .port_get_raw = gpio_ra_port_get_raw,
+ .port_set_masked_raw = gpio_ra_port_set_masked_raw,
+ .port_set_bits_raw = gpio_ra_port_set_bits_raw,
+ .port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
+ .port_toggle_bits = gpio_ra_port_toggle_bits,
+ .pin_interrupt_configure = NULL,
+ .manage_callback = NULL,
+};
+
+#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
+ static const struct gpio_ra_config gpio_ra_config_##suffix = { \
+ .common = \
+ { \
+ .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
+ }, \
+ .port_num = port_number, \
+ .port = (R_PORT0_Type *)addr, \
+ .vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \
+ }; \
+ static struct gpio_ra_data gpio_ra_data_##suffix; \
+ DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra_data_##suffix, &gpio_ra_config_##suffix, \
+ PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_drv_api_funcs)
+
+#define GPIO_DEVICE_INIT_RA(suffix) \
+ GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \
+ DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \
+ DT_REG_ADDR(DT_NODELABEL(ioport##suffix)))
+
+#define GPIO_DEVICE_INIT_RA_IF_OKAY(suffix) \
+ COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(ioport##suffix), okay), \
+ (GPIO_DEVICE_INIT_RA(suffix)), \
+ ())
+
+GPIO_DEVICE_INIT_RA_IF_OKAY(0);
+GPIO_DEVICE_INIT_RA_IF_OKAY(1);
+GPIO_DEVICE_INIT_RA_IF_OKAY(2);
+GPIO_DEVICE_INIT_RA_IF_OKAY(3);
+GPIO_DEVICE_INIT_RA_IF_OKAY(4);
+GPIO_DEVICE_INIT_RA_IF_OKAY(5);
+GPIO_DEVICE_INIT_RA_IF_OKAY(6);
+GPIO_DEVICE_INIT_RA_IF_OKAY(7);
+GPIO_DEVICE_INIT_RA_IF_OKAY(8);
+GPIO_DEVICE_INIT_RA_IF_OKAY(9);
+GPIO_DEVICE_INIT_RA_IF_OKAY(a);
+GPIO_DEVICE_INIT_RA_IF_OKAY(b);
diff --git a/drivers/gpio/gpio_rt1718s.h b/drivers/gpio/gpio_rt1718s.h
index 3a1c989..faba3cdb 100644
--- a/drivers/gpio/gpio_rt1718s.h
+++ b/drivers/gpio/gpio_rt1718s.h
@@ -155,8 +155,9 @@
static inline int rt1718s_reg_update(const struct device *dev, uint8_t reg_addr, uint8_t reg_val,
uint8_t new_val)
{
- if (reg_val == new_val)
+ if (reg_val == new_val) {
return 0;
+ }
return rt1718s_reg_write_byte(dev, reg_addr, new_val);
}
diff --git a/drivers/gpio/gpio_smartbond.c b/drivers/gpio/gpio_smartbond.c
index 06af6ff..0081989 100644
--- a/drivers/gpio/gpio_smartbond.c
+++ b/drivers/gpio/gpio_smartbond.c
@@ -17,8 +17,6 @@
#include <da1469x_pdc.h>
#include <da1469x_pd.h>
-#define GPIO_MODE_RESET 0x200
-
#define GPIO_PUPD_INPUT 0
#define GPIO_PUPD_INPUT_PU 1
#define GPIO_PUPD_INPUT_PD 2
@@ -117,8 +115,8 @@
const struct gpio_smartbond_config *config = dev->config;
if (flags == GPIO_DISCONNECTED) {
- /* Reset to default value */
- config->mode_regs[pin] = GPIO_MODE_RESET;
+ /* Set pin as input with no resistors selected */
+ config->mode_regs[pin] = GPIO_PUPD_INPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
return 0;
}
@@ -166,7 +164,8 @@
{
const struct gpio_smartbond_config *config = dev->config;
- config->data_regs->data = value & mask;
+ config->data_regs->set = value & mask;
+ config->data_regs->reset = ~value & mask;
return 0;
}
@@ -244,7 +243,9 @@
config->wkup_regs->clear = pin_mask;
data->both_edges_pins &= ~pin_mask;
#if CONFIG_PM
- da1469x_pdc_del(pdc_ix);
+ if (pdc_ix >= 0) {
+ da1469x_pdc_del(pdc_ix);
+ }
#endif
} else {
if (trig == GPIO_INT_TRIG_BOTH) {
diff --git a/drivers/haptics/drv2605.c b/drivers/haptics/drv2605.c
index 3427894..a1de615 100644
--- a/drivers/haptics/drv2605.c
+++ b/drivers/haptics/drv2605.c
@@ -90,6 +90,9 @@
#define DRV2605_LOOP_GAIN GENMASK(3, 2)
#define DRV2605_BEMF_GAIN GENMASK(1, 0)
+#define DRV2605_ACTUATOR_MODE_ERM 0
+#define DRV2605_ACTUATOR_MODE_LRA 1
+
#define DRV2605_REG_CONTROL1 0x1b
#define DRV2605_STARTUP_BOOST BIT(7)
#define DRV2605_AC_COUPLE BIT(5)
@@ -124,11 +127,9 @@
#define DRV2605_POWER_UP_DELAY_US 250
-enum drv2605_pm_state {
- DRV2605_PM_STATE_SHUTDOWN,
- DRV2605_PM_STATE_STANDBY,
- DRV2605_PM_STATE_ACTIVE,
-};
+#define DRV2605_VOLTAGE_SCALE_FACTOR_MV 5600
+
+#define DRV2605_CALCULATE_VOLTAGE(_volt) ((_volt * 255) / DRV2605_VOLTAGE_SCALE_FACTOR_MV)
struct drv2605_config {
struct i2c_dt_spec i2c;
@@ -458,6 +459,25 @@
return ret;
}
+ ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_RATED_VOLTAGE, config->rated_voltage);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_OVERDRIVE_CLAMP_VOLTAGE,
+ config->overdrive_clamp_voltage);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (config->actuator_mode == DRV2605_ACTUATOR_MODE_LRA) {
+ ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_CONTROL3,
+ DRV2605_LRA_OPEN_LOOP, DRV2605_LRA_OPEN_LOOP);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+
return 0;
}
@@ -601,11 +621,14 @@
\
static const struct drv2605_config drv2605_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
- .en_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, ti_en_gpios, {}), \
- .in_trig_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, ti_in_trig_gpios, {}), \
- .feedback_brake_factor = DT_INST_ENUM_IDX_OR(inst, ti_feedback_brake_factor, 3), \
- .loop_gain = DT_INST_ENUM_IDX_OR(inst, ti_loop_gain, 2), \
- .actuator_mode = DT_INST_ENUM_IDX_OR(inst, ti_actuator_mode, 0), \
+ .en_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, en_gpios, {}), \
+ .in_trig_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, in_trig_gpios, {}), \
+ .feedback_brake_factor = DT_INST_ENUM_IDX(inst, feedback_brake_factor), \
+ .loop_gain = DT_INST_ENUM_IDX(inst, loop_gain), \
+ .actuator_mode = DT_INST_ENUM_IDX(inst, actuator_mode), \
+ .rated_voltage = DRV2605_CALCULATE_VOLTAGE(DT_INST_PROP(inst, vib_rated_mv)), \
+ .overdrive_clamp_voltage = \
+ DRV2605_CALCULATE_VOLTAGE(DT_INST_PROP(inst, vib_overdrive_mv)), \
}; \
\
static struct drv2605_data drv2605_data_##inst = { \
diff --git a/drivers/hwinfo/hwinfo_esp32.c b/drivers/hwinfo/hwinfo_esp32.c
index 131c3fa..6c34c21 100644
--- a/drivers/hwinfo/hwinfo_esp32.c
+++ b/drivers/hwinfo/hwinfo_esp32.c
@@ -15,7 +15,10 @@
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
-#if !defined(CONFIG_SOC_SERIES_ESP32)
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ uint32_t rdata1 = sys_read32(EFUSE_RD_BLK2_DATA0_REG);
+ uint32_t rdata2 = sys_read32(EFUSE_RD_BLK2_DATA1_REG);
+#elif !defined(CONFIG_SOC_SERIES_ESP32)
uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG);
uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG);
#else
diff --git a/drivers/hwspinlock/sqn_hwspinlock.c b/drivers/hwspinlock/sqn_hwspinlock.c
index 7178b21..b6b80d9 100644
--- a/drivers/hwspinlock/sqn_hwspinlock.c
+++ b/drivers/hwspinlock/sqn_hwspinlock.c
@@ -56,12 +56,14 @@
*/
cpuid = mpidr_to_cpuid(read_mpidr_el1());
- if (sys_read8(get_lock_addr(dev, id)) == cpuid)
+ if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
+ }
sys_write8(cpuid, get_lock_addr(dev, id));
- if (sys_read8(get_lock_addr(dev, id)) == cpuid)
+ if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
+ }
return -EBUSY;
}
diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt
index aa46769..b46d933 100644
--- a/drivers/i2c/CMakeLists.txt
+++ b/drivers/i2c/CMakeLists.txt
@@ -90,6 +90,8 @@
i2c_ll_stm32.c
)
+zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_I2C_IIC i2c_renesas_ra_iic.c)
+
zephyr_library_sources_ifdef(CONFIG_I2C_TEST i2c_test.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE i2c_handlers.c)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 2002813..f005333 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -114,6 +114,7 @@
source "drivers/i2c/Kconfig.npcx"
source "drivers/i2c/Kconfig.test"
source "drivers/i2c/Kconfig.rcar"
+source "drivers/i2c/Kconfig.renesas_ra"
source "drivers/i2c/Kconfig.tca954x"
source "drivers/i2c/Kconfig.gd32"
source "drivers/i2c/Kconfig.ifx_cat1"
diff --git a/drivers/i2c/Kconfig.max32 b/drivers/i2c/Kconfig.max32
index b41f5ec..b8ae1fc 100644
--- a/drivers/i2c/Kconfig.max32
+++ b/drivers/i2c/Kconfig.max32
@@ -5,6 +5,7 @@
bool "Analog Devices MAX32 I2C driver"
default y
depends on DT_HAS_ADI_MAX32_I2C_ENABLED
+ select PINCTRL
help
i2c driver for max32 family.
@@ -17,4 +18,11 @@
Enable interrupt support for MAX32 I2C controller mode
transfers.
+config I2C_MAX32_DMA
+ bool "DMA support for MAX32 MCU I2C driver"
+ depends on I2C_MAX32_INTERRUPT
+ select DMA
+ help
+ Use DMA for MAX32 MCU I2C controller mode transfers.
+
endif # I2C_MAX32
diff --git a/drivers/i2c/Kconfig.renesas_ra b/drivers/i2c/Kconfig.renesas_ra
new file mode 100644
index 0000000..bf11f2d
--- /dev/null
+++ b/drivers/i2c/Kconfig.renesas_ra
@@ -0,0 +1,12 @@
+# Renesas RA Family
+
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config RENESAS_RA_I2C_IIC
+ bool "Renesas RA I2C IIC Master"
+ default y
+ depends on DT_HAS_RENESAS_RA_IIC_ENABLED
+ select USE_RA_FSP_I2C_IIC
+ help
+ Enable Renesas RA I2C IIC Driver.
diff --git a/drivers/i2c/i2c_ambiq.c b/drivers/i2c/i2c_ambiq.c
index ff83809..a8a06d0 100644
--- a/drivers/i2c/i2c_ambiq.c
+++ b/drivers/i2c/i2c_ambiq.c
@@ -9,6 +9,9 @@
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/pm/device_runtime.h>
#include <am_mcu_apollo.h>
@@ -186,6 +189,12 @@
return 0;
}
+ ret = pm_device_runtime_get(dev);
+
+ if (ret < 0) {
+ LOG_ERR("pm_device_runtime_get failed: %d", ret);
+ }
+
/* Send out messages */
k_sem_take(&data->bus_sem, K_FOREVER);
@@ -204,6 +213,15 @@
k_sem_give(&data->bus_sem);
+ /* Use async put to avoid useless device suspension/resumption
+ * when doing consecutive transmission.
+ */
+ ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+ if (ret < 0) {
+ LOG_ERR("pm_device_runtime_put failed: %d", ret);
+ }
+
return 0;
}
@@ -259,6 +277,34 @@
.transfer = i2c_ambiq_transfer,
};
+#ifdef CONFIG_PM_DEVICE
+static int i2c_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
+{
+ struct i2c_ambiq_data *data = dev->data;
+ uint32_t ret;
+ am_hal_sysctrl_power_state_e status;
+
+ switch (action) {
+ case PM_DEVICE_ACTION_RESUME:
+ status = AM_HAL_SYSCTRL_WAKE;
+ break;
+ case PM_DEVICE_ACTION_SUSPEND:
+ status = AM_HAL_SYSCTRL_DEEPSLEEP;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ ret = am_hal_iom_power_ctrl(data->iom_handler, status, true);
+
+ if (ret != AM_HAL_STATUS_SUCCESS) {
+ return -EPERM;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_PM_DEVICE */
+
#define AMBIQ_I2C_DEFINE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static int pwr_on_ambiq_i2c_##n(void) \
@@ -287,7 +333,8 @@
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.irq_config_func = i2c_irq_config_func_##n, \
.pwr_func = pwr_on_ambiq_i2c_##n}; \
- I2C_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_init, NULL, &i2c_ambiq_data##n, \
+ PM_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_pm_action); \
+ I2C_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_init, PM_DEVICE_DT_INST_GET(n), &i2c_ambiq_data##n, \
&i2c_ambiq_config##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_ambiq_driver_api);
diff --git a/drivers/i2c/i2c_emul.c b/drivers/i2c/i2c_emul.c
index 62e0b0d..0ec27f9 100644
--- a/drivers/i2c/i2c_emul.c
+++ b/drivers/i2c/i2c_emul.c
@@ -29,6 +29,16 @@
/* I2C host configuration */
uint32_t config;
uint32_t bitrate;
+#ifdef CONFIG_I2C_TARGET
+ struct i2c_target_config *target_cfg;
+#endif
+};
+
+struct i2c_emul_config {
+ struct emul_list_for_bus emul_list;
+ bool target_buffered_mode;
+ const struct i2c_dt_spec *forward_list;
+ uint16_t forward_list_size;
};
/**
@@ -74,13 +84,139 @@
return 0;
}
+#ifdef CONFIG_I2C_TARGET
+static int i2c_emul_send_to_target(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs)
+{
+ struct i2c_emul_data *data = dev->data;
+ const struct i2c_target_callbacks *callbacks = data->target_cfg->callbacks;
+
+#ifdef CONFIG_I2C_TARGET_BUFFER_MODE
+ const struct i2c_emul_config *config = dev->config;
+
+ if (config->target_buffered_mode) {
+ for (uint8_t i = 0; i < num_msgs; ++i) {
+ if (i2c_is_read_op(&msgs[i])) {
+ uint8_t *ptr = NULL;
+ uint32_t len;
+ int rc =
+ callbacks->buf_read_requested(data->target_cfg, &ptr, &len);
+
+ if (rc != 0) {
+ return rc;
+ }
+ if (len > msgs[i].len) {
+ LOG_ERR("buf_read_requested returned too many bytes");
+ return -ENOMEM;
+ }
+ memcpy(msgs[i].buf, ptr, len);
+ } else {
+ callbacks->buf_write_received(data->target_cfg, msgs[i].buf,
+ msgs[i].len);
+ }
+ if (i2c_is_stop_op(&msgs[i])) {
+ int rc = callbacks->stop(data->target_cfg);
+
+ if (rc != 0) {
+ return rc;
+ }
+ }
+ }
+ return 0;
+ }
+#endif /* CONFIG_I2C_TARGET_BUFFER_MODE */
+
+ for (uint8_t i = 0; i < num_msgs; ++i) {
+ LOG_DBG(" msgs[%u].flags? 0x%02x", i, msgs[i].flags);
+ if (i2c_is_read_op(&msgs[i])) {
+ for (uint32_t j = 0; j < msgs[i].len; ++j) {
+ int rc = 0;
+
+ if (j == 0) {
+ LOG_DBG(" Calling read_requested with data %p",
+ (void *)&msgs[i].buf[j]);
+ rc = callbacks->read_requested(data->target_cfg,
+ &msgs[i].buf[j]);
+ } else {
+ LOG_DBG(" Calling read_processed with data %p",
+ (void *)&msgs[i].buf[j]);
+ rc = callbacks->read_processed(data->target_cfg,
+ &msgs[i].buf[j]);
+ }
+ if (rc != 0) {
+ return rc;
+ }
+ }
+ } else {
+ for (uint32_t j = 0; j < msgs[i].len; ++j) {
+ int rc = 0;
+
+ if (j == 0) {
+ LOG_DBG(" Calling write_requested");
+ rc = callbacks->write_requested(data->target_cfg);
+ }
+ if (rc != 0) {
+ return rc;
+ }
+ LOG_DBG(" Calling write_received with data 0x%02x",
+ msgs[i].buf[j]);
+ rc = callbacks->write_received(data->target_cfg, msgs[i].buf[j]);
+ if (rc != 0) {
+ return rc;
+ }
+ }
+ }
+ if (i2c_is_stop_op(&msgs[i])) {
+ int rc = callbacks->stop(data->target_cfg);
+
+ if (rc != 0) {
+ return rc;
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_I2C_TARGET*/
+
static int i2c_emul_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
+ const struct i2c_emul_config *conf = dev->config;
struct i2c_emul *emul;
const struct i2c_emul_api *api;
int ret;
+ LOG_DBG("%s(dev=%p, addr=0x%02x)", __func__, (void *)dev, addr);
+#ifdef CONFIG_I2C_TARGET
+ struct i2c_emul_data *data = dev->data;
+
+ /*
+ * First check if the bus is configured as a target, targets either listen to the address or
+ * ignore the messages. So if the address doesn't match, we're just going to bail.
+ */
+ LOG_DBG(" has_target_cfg? %d", data->target_cfg != NULL);
+ if (data->target_cfg != NULL) {
+ LOG_DBG(" target_cfg->address? 0x%02x", data->target_cfg->address);
+ if (data->target_cfg->address != addr) {
+ return -EINVAL;
+ }
+ LOG_DBG(" forwarding to target");
+ return i2c_emul_send_to_target(dev, msgs, num_msgs);
+ }
+#endif /* CONFIG_I2C_TARGET */
+
+ /*
+ * We're not a target, but lets check if we need to forward this request before we start
+ * looking for a peripheral.
+ */
+ for (uint16_t i = 0; i < conf->forward_list_size; ++i) {
+ LOG_DBG(" Checking forward list [%u].addr? 0x%02x", i,
+ conf->forward_list[i].addr);
+ if (conf->forward_list[i].addr == addr) {
+ /* We need to forward this request */
+ return i2c_transfer(conf->forward_list[i].bus, msgs, num_msgs, addr);
+ }
+ }
+
emul = i2c_emul_find(dev, addr);
if (!emul) {
return -EIO;
@@ -132,12 +268,38 @@
return 0;
}
+#ifdef CONFIG_I2C_TARGET
+static int i2c_emul_target_register(const struct device *dev, struct i2c_target_config *cfg)
+{
+ struct i2c_emul_data *data = dev->data;
+
+ data->target_cfg = cfg;
+ return 0;
+}
+
+static int i2c_emul_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
+{
+ struct i2c_emul_data *data = dev->data;
+
+ if (data->target_cfg != cfg) {
+ return -EINVAL;
+ }
+
+ data->target_cfg = NULL;
+ return 0;
+}
+#endif /* CONFIG_I2C_TARGET */
+
/* Device instantiation */
static const struct i2c_driver_api i2c_emul_api = {
.configure = i2c_emul_configure,
.get_config = i2c_emul_get_config,
.transfer = i2c_emul_transfer,
+#ifdef CONFIG_I2C_TARGET
+ .target_register = i2c_emul_target_register,
+ .target_unregister = i2c_emul_target_unregister,
+#endif
};
#define EMUL_LINK_AND_COMMA(node_id) \
@@ -145,12 +307,27 @@
.dev = DEVICE_DT_GET(node_id), \
},
+#define EMUL_FORWARD_ITEM(node_id, prop, idx) \
+ { \
+ .bus = DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)), \
+ .addr = DT_PHA_BY_IDX(node_id, prop, idx, addr), \
+ },
+
#define I2C_EMUL_INIT(n) \
static const struct emul_link_for_bus emuls_##n[] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(n), EMUL_LINK_AND_COMMA)}; \
- static struct emul_list_for_bus i2c_emul_cfg_##n = { \
- .children = emuls_##n, \
- .num_children = ARRAY_SIZE(emuls_##n), \
+ static const struct i2c_dt_spec emul_forward_list_##n[] = { \
+ COND_CODE_1(DT_INST_NODE_HAS_PROP(n, forwards), \
+ (DT_INST_FOREACH_PROP_ELEM(n, forwards, EMUL_FORWARD_ITEM)), ())}; \
+ static struct i2c_emul_config i2c_emul_cfg_##n = { \
+ .emul_list = \
+ { \
+ .children = emuls_##n, \
+ .num_children = ARRAY_SIZE(emuls_##n), \
+ }, \
+ .target_buffered_mode = DT_INST_PROP(n, target_buffered_mode), \
+ .forward_list = emul_forward_list_##n, \
+ .forward_list_size = ARRAY_SIZE(emul_forward_list_##n), \
}; \
static struct i2c_emul_data i2c_emul_data_##n = { \
.bitrate = DT_INST_PROP(n, clock_frequency), \
diff --git a/drivers/i2c/i2c_ene_kb1200.c b/drivers/i2c/i2c_ene_kb1200.c
index 3c78932..3a24af2 100644
--- a/drivers/i2c/i2c_ene_kb1200.c
+++ b/drivers/i2c/i2c_ene_kb1200.c
@@ -145,8 +145,9 @@
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
- while (data->state != STATE_COMPLETE)
+ while (data->state != STATE_COMPLETE) {
;
+ }
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */
@@ -187,8 +188,9 @@
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
- while (data->state != STATE_COMPLETE)
+ while (data->state != STATE_COMPLETE) {
;
+ }
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */
diff --git a/drivers/i2c/i2c_esp32.c b/drivers/i2c/i2c_esp32.c
index 4462962..d15dac1 100644
--- a/drivers/i2c/i2c_esp32.c
+++ b/drivers/i2c/i2c_esp32.c
@@ -90,6 +90,8 @@
} mode;
int irq_source;
+ int irq_priority;
+ int irq_flags;
const uint32_t bitrate;
const uint32_t scl_timeout;
@@ -761,7 +763,17 @@
clock_control_on(config->clock_dev, config->clock_subsys);
- esp_intr_alloc(config->irq_source, 0, i2c_esp32_isr, (void *)dev, NULL);
+ ret = esp_intr_alloc(config->irq_source,
+ ESP_PRIO_TO_FLAGS(config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(config->irq_flags) | ESP_INTR_FLAG_IRAM,
+ i2c_esp32_isr,
+ (void *)dev,
+ NULL);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ return ret;
+ }
i2c_hal_master_init(&data->hal);
@@ -822,7 +834,9 @@
.tx_lsb_first = DT_PROP(I2C(idx), tx_lsb), \
.rx_lsb_first = DT_PROP(I2C(idx), rx_lsb), \
}, \
- .irq_source = ETS_I2C_EXT##idx##_INTR_SOURCE, \
+ .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
+ .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags), \
.bitrate = I2C_FREQUENCY(idx), \
.scl_timeout = I2C_ESP32_TIMEOUT(idx), \
}; \
diff --git a/drivers/i2c/i2c_max32.c b/drivers/i2c/i2c_max32.c
index 8783e6d..69901c3 100644
--- a/drivers/i2c/i2c_max32.c
+++ b/drivers/i2c/i2c_max32.c
@@ -12,6 +12,10 @@
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/irq.h>
+#if defined(CONFIG_I2C_MAX32_DMA)
+#include <zephyr/drivers/dma.h>
+#endif /* CONFIG_I2C_MAX32_DMA */
+
#include <wrap_max32_i2c.h>
#define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
@@ -21,6 +25,14 @@
#define I2C_RECOVER_MAX_RETRIES 3
+#ifdef CONFIG_I2C_MAX32_DMA
+struct max32_i2c_dma_config {
+ const struct device *dev;
+ const uint32_t channel;
+ const uint32_t slot;
+};
+#endif /* CONFIG_I2C_MAX32_DMA */
+
/* Driver config */
struct max32_i2c_config {
mxc_i2c_regs_t *regs;
@@ -32,6 +44,10 @@
uint8_t irqn;
void (*irq_config_func)(const struct device *dev);
#endif
+#ifdef CONFIG_I2C_MAX32_DMA
+ struct max32_i2c_dma_config tx_dma;
+ struct max32_i2c_dma_config rx_dma;
+#endif /* CONFIG_I2C_MAX32_DMA */
};
struct max32_i2c_data {
@@ -46,7 +62,7 @@
#endif /* CONFIG_I2C_TARGET */
uint32_t readb;
uint32_t written;
-#if defined(CONFIG_I2C_MAX32_INTERRUPT)
+#if defined(CONFIG_I2C_MAX32_INTERRUPT) || defined(CONFIG_I2C_MAX32_DMA)
struct k_sem xfer;
int err;
#endif
@@ -266,6 +282,149 @@
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
+#if defined(CONFIG_I2C_MAX32_DMA)
+static void i2c_max32_dma_callback(const struct device *dev, void *arg, uint32_t channel,
+ int status)
+{
+ struct max32_i2c_data *data = arg;
+ const struct device *i2c_dev = data->dev;
+ const struct max32_i2c_config *const cfg = i2c_dev->config;
+
+ if (status < 0) {
+ data->err = -EIO;
+ } else {
+ if (data->req.restart) {
+ Wrap_MXC_I2C_Restart(cfg->regs);
+ } else {
+ Wrap_MXC_I2C_Stop(cfg->regs);
+ }
+ }
+}
+
+static int i2c_max32_tx_dma_load(const struct device *dev, struct i2c_msg *msg)
+{
+ int ret;
+ const struct max32_i2c_config *config = dev->config;
+ struct max32_i2c_data *data = dev->data;
+ struct dma_config dma_cfg = {0};
+ struct dma_block_config dma_blk = {0};
+
+ dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+ dma_cfg.dma_callback = i2c_max32_dma_callback;
+ dma_cfg.user_data = (void *)data;
+ dma_cfg.dma_slot = config->tx_dma.slot;
+ dma_cfg.block_count = 1;
+ dma_cfg.source_data_size = 1U;
+ dma_cfg.source_burst_length = 1U;
+ dma_cfg.dest_data_size = 1U;
+ dma_cfg.head_block = &dma_blk;
+ dma_blk.block_size = msg->len;
+ dma_blk.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+ dma_blk.source_address = (uint32_t)msg->buf;
+
+ ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return dma_start(config->tx_dma.dev, config->tx_dma.channel);
+}
+
+static int i2c_max32_rx_dma_load(const struct device *dev, struct i2c_msg *msg)
+{
+ int ret;
+ const struct max32_i2c_config *config = dev->config;
+ struct max32_i2c_data *data = dev->data;
+ struct dma_config dma_cfg = {0};
+ struct dma_block_config dma_blk = {0};
+
+ dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
+ dma_cfg.dma_callback = i2c_max32_dma_callback;
+ dma_cfg.user_data = (void *)data;
+ dma_cfg.dma_slot = config->rx_dma.slot;
+ dma_cfg.block_count = 1;
+ dma_cfg.source_data_size = 1U;
+ dma_cfg.source_burst_length = 1U;
+ dma_cfg.dest_data_size = 1U;
+ dma_cfg.head_block = &dma_blk;
+ dma_blk.block_size = msg->len;
+ dma_blk.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+ dma_blk.dest_address = (uint32_t)msg->buf;
+
+ ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return dma_start(config->rx_dma.dev, config->rx_dma.channel);
+}
+
+static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+ uint16_t target_address)
+{
+ int ret = 0;
+ const struct max32_i2c_config *const cfg = dev->config;
+ struct max32_i2c_data *data = dev->data;
+ mxc_i2c_regs_t *i2c = cfg->regs;
+ uint8_t target_rw;
+ unsigned int i = 0;
+
+ k_sem_take(&data->lock, K_FOREVER);
+
+ MXC_I2C_SetRXThreshold(i2c, 1);
+ MXC_I2C_SetTXThreshold(i2c, 2);
+ MXC_I2C_ClearTXFIFO(i2c);
+ MXC_I2C_ClearRXFIFO(i2c);
+
+ for (i = 0; i < num_msgs; i++) {
+ data->req.restart = !(msgs[i].flags & I2C_MSG_STOP);
+ if (msgs[i].flags & I2C_MSG_READ) {
+ target_rw = (target_address << 1) | 0x1;
+ MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
+ Wrap_MXC_I2C_SetRxCount(i2c, msgs[i].len);
+ ret = i2c_max32_rx_dma_load(dev, &msgs[i]);
+ if (ret < 0) {
+ break;
+ }
+
+ MXC_I2C_EnableInt(
+ i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
+ i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
+ } else {
+ target_rw = (target_address << 1) & ~0x1;
+ MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
+ ret = i2c_max32_tx_dma_load(dev, &msgs[i]);
+ if (ret < 0) {
+ break;
+ }
+
+ MXC_I2C_EnableInt(
+ i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
+ i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
+ }
+ data->err = 0;
+
+ Wrap_MXC_I2C_Start(i2c);
+ ret = k_sem_take(&data->xfer, K_FOREVER);
+ Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
+ i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN);
+
+ if (data->err) {
+ ret = data->err;
+ }
+ if (ret) {
+ MXC_I2C_Stop(i2c);
+ dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
+ dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
+ }
+ }
+
+ k_sem_give(&data->lock);
+
+ return ret;
+}
+#endif /* CONFIG_I2C_MAX32_DMA */
+
#ifdef CONFIG_I2C_MAX32_INTERRUPT
static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
@@ -434,6 +593,13 @@
static int api_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
{
+#if CONFIG_I2C_MAX32_DMA
+ const struct max32_i2c_config *cfg = dev->config;
+
+ if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
+ return i2c_max32_transfer_dma(dev, msgs, num_msgs, target_address);
+ }
+#endif
return i2c_max32_transfer(dev, msgs, num_msgs, target_address);
}
@@ -615,6 +781,29 @@
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
+#ifdef CONFIG_I2C_MAX32_DMA
+static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c)
+{
+ struct max32_i2c_data *data = dev->data;
+ uint32_t int_fl0, int_fl1;
+ uint32_t int_en0, int_en1;
+
+ Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
+ MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
+ MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
+
+ if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
+ data->err = -EIO;
+ Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
+ k_sem_give(&data->xfer);
+ } else {
+ if (!data->err && (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
+ k_sem_give(&data->xfer);
+ }
+ }
+}
+#endif /* CONFIG_I2C_MAX32_DMA */
+
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
static void i2c_max32_isr(const struct device *dev)
{
@@ -624,6 +813,12 @@
#ifdef CONFIG_I2C_MAX32_INTERRUPT
if (data->target_mode == 0) {
+#ifdef CONFIG_I2C_MAX32_DMA
+ if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
+ i2c_max32_isr_controller_dma(dev, i2c);
+ return;
+ }
+#endif
i2c_max32_isr_controller(dev, i2c);
return;
}
@@ -713,6 +908,28 @@
#define I2C_MAX32_IRQ_CONFIG_FUNC(n)
#endif
+#if CONFIG_I2C_MAX32_DMA
+#define MAX32_DT_INST_DMA_CTLR(n, name) \
+ COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
+ (DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, name))), (NULL))
+
+#define MAX32_DT_INST_DMA_CELL(n, name, cell) \
+ COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
+ (0xff))
+
+#define MAX32_I2C_TX_DMA_INIT(n) \
+ .tx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, tx), \
+ .tx_dma.channel = MAX32_DT_INST_DMA_CELL(n, tx, channel), \
+ .tx_dma.slot = MAX32_DT_INST_DMA_CELL(n, tx, slot),
+#define MAX32_I2C_RX_DMA_INIT(n) \
+ .rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx), \
+ .rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel), \
+ .rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
+#else
+#define MAX32_I2C_TX_DMA_INIT(n)
+#define MAX32_I2C_RX_DMA_INIT(n)
+#endif
+
#define DEFINE_I2C_MAX32(_num) \
PINCTRL_DT_INST_DEFINE(_num); \
I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
@@ -723,7 +940,8 @@
.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
.bitrate = DT_INST_PROP(_num, clock_frequency), \
- I2C_MAX32_CONFIG_IRQ_FUNC(_num)}; \
+ I2C_MAX32_CONFIG_IRQ_FUNC(_num) MAX32_I2C_TX_DMA_INIT(_num) \
+ MAX32_I2C_RX_DMA_INIT(_num)}; \
static struct max32_i2c_data max32_i2c_data_##_num; \
I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
&max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
diff --git a/drivers/i2c/i2c_mcux_lpi2c_rtio.c b/drivers/i2c/i2c_mcux_lpi2c_rtio.c
index bd966d3..6b109945 100644
--- a/drivers/i2c/i2c_mcux_lpi2c_rtio.c
+++ b/drivers/i2c/i2c_mcux_lpi2c_rtio.c
@@ -192,13 +192,15 @@
switch (sqe->op) {
case RTIO_OP_RX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags,
- sqe->buf, sqe->buf_len, dt_spec->addr);
+ sqe->rx.buf, sqe->rx.buf_len, dt_spec->addr);
case RTIO_OP_TINY_TX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
- sqe->tiny_buf, sqe->tiny_buf_len, dt_spec->addr);
+ (uint8_t *)sqe->tiny_tx.buf, sqe->tiny_tx.buf_len,
+ dt_spec->addr);
case RTIO_OP_TX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
- sqe->buf, sqe->buf_len, dt_spec->addr);
+ (uint8_t *)sqe->tx.buf, sqe->tx.buf_len,
+ dt_spec->addr);
case RTIO_OP_I2C_CONFIGURE:
res = mcux_lpi2c_do_configure(dev, sqe->i2c_config);
return i2c_rtio_complete(data->ctx, res);
diff --git a/drivers/i2c/i2c_npcx_controller.c b/drivers/i2c/i2c_npcx_controller.c
index 1349a53..cf45a83 100644
--- a/drivers/i2c/i2c_npcx_controller.c
+++ b/drivers/i2c/i2c_npcx_controller.c
@@ -425,8 +425,9 @@
* Wait till i2c bus is idle. This bit is cleared to 0
* automatically after the STOP condition is generated.
*/
- if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP))
+ if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP)) {
break;
+ }
k_msleep(1);
} while (--timeout);
diff --git a/drivers/i2c/i2c_nrfx_twi_rtio.c b/drivers/i2c/i2c_nrfx_twi_rtio.c
index 7f5d5be..61456b0 100644
--- a/drivers/i2c/i2c_nrfx_twi_rtio.c
+++ b/drivers/i2c/i2c_nrfx_twi_rtio.c
@@ -69,13 +69,14 @@
switch (sqe->op) {
case RTIO_OP_RX:
return i2c_nrfx_twi_rtio_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags,
- sqe->buf, sqe->buf_len, dt_spec->addr);
+ sqe->rx.buf, sqe->rx.buf_len, dt_spec->addr);
case RTIO_OP_TINY_TX:
return i2c_nrfx_twi_rtio_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
- sqe->tiny_buf, sqe->tiny_buf_len, dt_spec->addr);
+ sqe->tiny_tx.buf, sqe->tiny_tx.buf_len,
+ dt_spec->addr);
case RTIO_OP_TX:
return i2c_nrfx_twi_rtio_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
- sqe->buf, sqe->buf_len, dt_spec->addr);
+ sqe->tx.buf, sqe->tx.buf_len, dt_spec->addr);
case RTIO_OP_I2C_CONFIGURE:
(void)i2c_nrfx_twi_configure(dev, sqe->i2c_config);
return false;
diff --git a/drivers/i2c/i2c_renesas_ra_iic.c b/drivers/i2c/i2c_renesas_ra_iic.c
new file mode 100644
index 0000000..9f854b7
--- /dev/null
+++ b/drivers/i2c/i2c_renesas_ra_iic.c
@@ -0,0 +1,556 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_iic
+
+#include <math.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+
+#include "r_iic_master.h"
+#include <errno.h>
+#include <soc.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(renesas_ra_iic);
+
+typedef void (*init_func_t)(const struct device *dev);
+static const double RA_IIC_MASTER_DIV_TIME_NS = 1000000000;
+
+struct i2c_ra_iic_config {
+ void (*irq_config_func)(const struct device *dev);
+ const struct pinctrl_dev_config *pcfg;
+ uint32_t noise_filter_stage;
+ double rise_time_s;
+ double fall_time_s;
+ uint32_t duty_cycle_percent;
+};
+
+struct i2c_ra_iic_data {
+ iic_master_instance_ctrl_t ctrl;
+ i2c_master_cfg_t fsp_config;
+ struct k_mutex bus_mutex;
+ struct k_sem complete_sem;
+ i2c_master_event_t event;
+ iic_master_extended_cfg_t iic_master_ext_cfg;
+ uint32_t dev_config;
+};
+
+/* IIC master clock setting calculation function. */
+static void calc_iic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+ iic_master_clock_settings_t *clk_cfg);
+
+/* FSP interruption handlers. */
+void iic_master_rxi_isr(void);
+void iic_master_txi_isr(void);
+void iic_master_tei_isr(void);
+void iic_master_eri_isr(void);
+
+struct ra_iic_master_bitrate {
+ uint32_t bitrate;
+ uint32_t duty;
+ uint32_t divider;
+ uint32_t brl;
+ uint32_t brh;
+ uint32_t duty_error_percent;
+};
+
+static int i2c_ra_iic_configure(const struct device *dev, uint32_t dev_config)
+{
+ struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
+
+ if (!(dev_config & I2C_MODE_CONTROLLER)) {
+ LOG_ERR("Only I2C Master mode supported.");
+ return -EIO;
+ }
+
+ switch (I2C_SPEED_GET(dev_config)) {
+ case I2C_SPEED_STANDARD:
+ data->fsp_config.rate = I2C_MASTER_RATE_STANDARD;
+ break;
+ case I2C_SPEED_FAST:
+ data->fsp_config.rate = I2C_MASTER_RATE_FAST;
+ break;
+ case I2C_SPEED_FAST_PLUS:
+ data->fsp_config.rate = I2C_MASTER_RATE_FASTPLUS;
+ break;
+ default:
+ LOG_ERR("%s: Invalid I2C speed rate flag: %d", __func__, I2C_SPEED_GET(dev_config));
+ return -EIO;
+ }
+
+ /* Recalc clock setting after updating config. */
+ calc_iic_master_clock_setting(dev, data->fsp_config.rate,
+ &data->iic_master_ext_cfg.clock_settings);
+
+ R_IIC_MASTER_Close(&data->ctrl);
+ R_IIC_MASTER_Open(&data->ctrl, &data->fsp_config);
+
+ /* save current devconfig. */
+ data->dev_config = dev_config;
+
+ return 0;
+}
+
+static int i2c_ra_iic_get_config(const struct device *dev, uint32_t *dev_config)
+{
+ struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
+ *dev_config = data->dev_config;
+
+ return 0;
+}
+
+#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK)
+
+static int i2c_ra_iic_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+ uint16_t addr)
+{
+ struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
+ struct i2c_msg *current, *next;
+ fsp_err_t fsp_err = FSP_SUCCESS;
+ int ret = 0;
+
+ if (!num_msgs) {
+ return 0;
+ }
+
+ /* Check for validity of all messages before transfer */
+ current = msgs;
+
+ /*
+ * Set I2C_MSG_RESTART flag on first message in order to send start
+ * condition
+ */
+ current->flags |= I2C_MSG_RESTART;
+
+ for (int i = 1; i <= num_msgs; i++) {
+ if (i < num_msgs) {
+ next = current + 1;
+
+ /*
+ * Restart condition between messages
+ * of different directions is required
+ */
+ if (OPERATION(current) != OPERATION(next)) {
+ if (!(next->flags & I2C_MSG_RESTART)) {
+ LOG_ERR("%s: Restart condition between messages of "
+ "different directions is required."
+ "Current/Total: [%d/%d]",
+ __func__, i, num_msgs);
+ ret = -EIO;
+ break;
+ }
+ }
+
+ /* Stop condition is only allowed on last message */
+ if (current->flags & I2C_MSG_STOP) {
+ LOG_ERR("%s: Invalid stop flag. Stop condition is only allowed on "
+ "last message. "
+ "Current/Total: [%d/%d]",
+ __func__, i, num_msgs);
+ ret = -EIO;
+ break;
+ }
+ } else {
+ current->flags |= I2C_MSG_STOP;
+ }
+
+ current++;
+ }
+
+ if (ret) {
+ return ret;
+ }
+
+ k_mutex_lock(&data->bus_mutex, K_FOREVER);
+
+ /* Set destination address with configured address mode before sending msg. */
+
+ i2c_master_addr_mode_t addr_mode = 0;
+
+ if (I2C_MSG_ADDR_10_BITS & data->dev_config) {
+ addr_mode = I2C_MASTER_ADDR_MODE_10BIT;
+ } else {
+ addr_mode = I2C_MASTER_ADDR_MODE_7BIT;
+ }
+
+ R_IIC_MASTER_SlaveAddressSet(&data->ctrl, addr, addr_mode);
+
+ /* Process input `msgs`. */
+
+ current = msgs;
+
+ while (num_msgs > 0) {
+ if (num_msgs > 1) {
+ next = current + 1;
+ } else {
+ next = NULL;
+ }
+
+ if (current->flags & I2C_MSG_READ) {
+ fsp_err =
+ R_IIC_MASTER_Read(&data->ctrl, current->buf, current->len,
+ next != NULL && (next->flags & I2C_MSG_RESTART));
+ } else {
+ fsp_err =
+ R_IIC_MASTER_Write(&data->ctrl, current->buf, current->len,
+ next != NULL && (next->flags & I2C_MSG_RESTART));
+ }
+
+ if (fsp_err != FSP_SUCCESS) {
+ switch (fsp_err) {
+ case FSP_ERR_INVALID_SIZE:
+ LOG_ERR("%s: Provided number of bytes more than uint16_t size "
+ "(65535) while DTC is used for data transfer.",
+ __func__);
+ break;
+ case FSP_ERR_IN_USE:
+ LOG_ERR("%s: Bus busy condition. Another transfer was in progress.",
+ __func__);
+ break;
+ default:
+ /* Should not reach here. */
+ LOG_ERR("%s: Unknown error. FSP_ERR=%d\n", __func__, fsp_err);
+ break;
+ }
+
+ ret = -EIO;
+ goto RELEASE_BUS;
+ }
+
+ /* Wait for callback to return. */
+ k_sem_take(&data->complete_sem, K_FOREVER);
+
+ /* Handle event msg from callback. */
+ switch (data->event) {
+ case I2C_MASTER_EVENT_ABORTED:
+ LOG_ERR("%s: %s failed.", __func__,
+ (current->flags & I2C_MSG_READ) ? "Read" : "Write");
+ ret = -EIO;
+ goto RELEASE_BUS;
+ case I2C_MASTER_EVENT_RX_COMPLETE:
+ break;
+ case I2C_MASTER_EVENT_TX_COMPLETE:
+ break;
+ default:
+ break;
+ }
+
+ current++;
+ num_msgs--;
+ }
+
+RELEASE_BUS:
+ k_mutex_unlock(&data->bus_mutex);
+
+ return ret;
+}
+
+static void i2c_ra_iic_callback(i2c_master_callback_args_t *p_args)
+{
+ const struct device *dev = p_args->p_context;
+ struct i2c_ra_iic_data *data = dev->data;
+
+ data->event = p_args->event;
+
+ k_sem_give(&data->complete_sem);
+}
+
+static int i2c_ra_iic_init(const struct device *dev)
+{
+ const struct i2c_ra_iic_config *config = dev->config;
+ struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *)dev->data;
+ fsp_err_t fsp_err = FSP_SUCCESS;
+ int ret = 0;
+
+ /* Configure dt provided device signals when available */
+ ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+
+ if (ret < 0) {
+ LOG_ERR("%s: pinctrl config failed.", __func__);
+ return ret;
+ }
+
+ k_mutex_init(&data->bus_mutex);
+ k_sem_init(&data->complete_sem, 0, 1);
+
+ switch (data->fsp_config.rate) {
+ case I2C_MASTER_RATE_STANDARD:
+ case I2C_MASTER_RATE_FAST:
+ case I2C_MASTER_RATE_FASTPLUS:
+ calc_iic_master_clock_setting(dev, data->fsp_config.rate,
+ &data->iic_master_ext_cfg.clock_settings);
+ data->iic_master_ext_cfg.timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT;
+ data->iic_master_ext_cfg.timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED;
+
+ data->fsp_config.p_extend = &data->iic_master_ext_cfg;
+ break;
+ default:
+ LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, data->fsp_config.rate);
+ return -ENOTSUP;
+ }
+
+ fsp_err = R_IIC_MASTER_Open(&data->ctrl, &data->fsp_config);
+ __ASSERT(fsp_err == FSP_SUCCESS, "%s: Open iic master failed. FSP_ERR=%d", __func__,
+ fsp_err);
+
+ config->irq_config_func(dev);
+
+ return 0;
+}
+
+static void calc_iic_master_bitrate(const struct i2c_ra_iic_config *config, uint32_t total_brl_brh,
+ uint32_t brh, uint32_t divider,
+ struct ra_iic_master_bitrate *result)
+{
+ const uint32_t noise_filter_stage = config->noise_filter_stage;
+ const double rise_time_s = config->rise_time_s;
+ const double fall_time_s = config->fall_time_s;
+ const uint32_t requested_duty = config->duty_cycle_percent;
+ const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB);
+ uint32_t constant_add = 0;
+
+ /* A constant is added to BRL and BRH in all formulas. This constand is 3 + nf
+ * when CKS == 0, or 2 + nf when CKS != 0.
+ */
+ if (divider == 0) {
+ constant_add = 3 + noise_filter_stage;
+ } else {
+ /* All dividers other than 0 use an addition of 2 + noise_filter_stages. */
+ constant_add = 2 + noise_filter_stage;
+ }
+
+ /* Converts all divided numbers to double to avoid data loss. */
+ uint32_t divided_pclk = (peripheral_clock >> divider);
+
+ result->bitrate =
+ 1 / ((total_brl_brh + 2 * constant_add) / divided_pclk + rise_time_s + fall_time_s);
+ result->duty =
+ 100 *
+ ((rise_time_s + ((brh + constant_add) / divided_pclk)) /
+ (rise_time_s + fall_time_s + ((total_brl_brh + 2 * constant_add)) / divided_pclk));
+ result->divider = divider;
+ result->brh = brh;
+ result->brl = total_brl_brh - brh;
+ result->duty_error_percent =
+ (result->duty > requested_duty ? result->duty - requested_duty
+ : requested_duty - result->duty) /
+ requested_duty;
+
+ LOG_DBG("%s: [input] total_brl_brh[%d] brh[%d] divider[%d]"
+ " [output] bitrate[%u] duty[%u] divider[%u] brh[%u] brl[%u] "
+ "duty_error_percent[%u]\n",
+ __func__, total_brl_brh, brh, divider, result->bitrate, result->duty,
+ result->divider, result->brh, result->brl, result->duty_error_percent);
+}
+
+static void calc_iic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+ iic_master_clock_settings_t *clk_cfg)
+{
+ const struct i2c_ra_iic_config *config = dev->config;
+ const uint32_t noise_filter_stage = config->noise_filter_stage;
+ const double rise_time_s = config->rise_time_s;
+ const double fall_time_s = config->fall_time_s;
+ const uint32_t requested_duty = config->duty_cycle_percent;
+ const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB);
+
+ uint32_t requested_bitrate = 0;
+
+ switch (fsp_i2c_rate) {
+ case I2C_MASTER_RATE_STANDARD:
+ case I2C_MASTER_RATE_FAST:
+ case I2C_MASTER_RATE_FASTPLUS:
+ requested_bitrate = fsp_i2c_rate;
+ break;
+ default:
+ LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, fsp_i2c_rate);
+ return;
+ }
+
+ /* Start with maximum possible bitrate. */
+ uint32_t min_brh = noise_filter_stage + 1;
+ uint32_t min_brl_brh = 2 * min_brh;
+ struct ra_iic_master_bitrate bitrate = {};
+
+ calc_iic_master_bitrate(config, min_brl_brh, min_brh, 0, &bitrate);
+
+ /* Start with the smallest divider because it gives the most resolution. */
+ uint32_t constant_add = 3 + noise_filter_stage;
+
+ for (int temp_divider = 0; temp_divider <= 7; ++temp_divider) {
+ if (1 == temp_divider) {
+ /* All dividers other than 0 use an addition of 2 + noise_filter_stages.
+ */
+ constant_add = 2 + noise_filter_stage;
+ }
+
+ /* If the requested bitrate cannot be achieved with this divider, continue.
+ */
+ uint32_t divided_pclk = (peripheral_clock >> temp_divider);
+ uint32_t total_brl_brh =
+ ceil(((1 / (double)requested_bitrate) - (rise_time_s + fall_time_s)) *
+ divided_pclk -
+ (2 * constant_add));
+
+ if ((total_brl_brh > 62) || (total_brl_brh < min_brl_brh)) {
+ continue;
+ }
+
+ uint32_t temp_brh = total_brl_brh * requested_duty / 100;
+
+ if (temp_brh < min_brh) {
+ temp_brh = min_brh;
+ }
+
+ /* Calculate the actual bitrate and duty cycle. */
+ struct ra_iic_master_bitrate temp_bitrate = {};
+
+ calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+ &temp_bitrate);
+
+ /* Adjust duty cycle down if it helps. */
+ struct ra_iic_master_bitrate test_bitrate = temp_bitrate;
+
+ while (test_bitrate.duty > requested_duty) {
+ temp_brh -= 1;
+
+ if ((temp_brh < min_brh) || ((total_brl_brh - temp_brh) > 31)) {
+ break;
+ }
+
+ struct ra_iic_master_bitrate new_bitrate = {};
+
+ calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+ &new_bitrate);
+
+ if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
+ temp_bitrate = new_bitrate;
+ } else {
+ break;
+ }
+ }
+
+ /* Adjust duty cycle up if it helps. */
+ while (test_bitrate.duty < requested_duty) {
+ ++temp_brh;
+
+ if ((temp_brh > total_brl_brh) || (temp_brh > 31) ||
+ ((total_brl_brh - temp_brh) < min_brh)) {
+ break;
+ }
+
+ struct ra_iic_master_bitrate new_bitrate = {};
+
+ calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+ &new_bitrate);
+
+ if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
+ temp_bitrate = new_bitrate;
+ } else {
+ break;
+ }
+ }
+
+ if ((temp_bitrate.brh < 32) && (temp_bitrate.brl < 32)) {
+ /* Valid setting found. */
+ bitrate = temp_bitrate;
+ break;
+ }
+ }
+
+ clk_cfg->brl_value = bitrate.brl;
+ clk_cfg->brh_value = bitrate.brh;
+ clk_cfg->cks_value = bitrate.divider;
+
+ LOG_DBG("%s: [input] rate[%u] [output] brl[%u] brh[%u] cks[%u]\n", __func__, fsp_i2c_rate,
+ clk_cfg->brl_value, clk_cfg->brh_value, clk_cfg->cks_value);
+}
+
+static const struct i2c_driver_api i2c_ra_iic_driver_api = {
+ .configure = i2c_ra_iic_configure,
+ .get_config = i2c_ra_iic_get_config,
+ .transfer = i2c_ra_iic_transfer,
+};
+
+#define _ELC_EVENT_IIC_RXI(channel) ELC_EVENT_IIC##channel##_RXI
+#define _ELC_EVENT_IIC_TXI(channel) ELC_EVENT_IIC##channel##_TXI
+#define _ELC_EVENT_IIC_TEI(channel) ELC_EVENT_IIC##channel##_TEI
+#define _ELC_EVENT_IIC_ERI(channel) ELC_EVENT_IIC##channel##_ERI
+
+#define ELC_EVENT_IIC_RXI(channel) _ELC_EVENT_IIC_RXI(channel)
+#define ELC_EVENT_IIC_TXI(channel) _ELC_EVENT_IIC_TXI(channel)
+#define ELC_EVENT_IIC_TEI(channel) _ELC_EVENT_IIC_TEI(channel)
+#define ELC_EVENT_IIC_ERI(channel) _ELC_EVENT_IIC_ERI(channel)
+
+#define I2C_RA_IIC_INIT(index) \
+ \
+ PINCTRL_DT_INST_DEFINE(index); \
+ \
+ static void i2c_ra_iic_irq_config_func##index(const struct device *dev) \
+ { \
+ R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] = \
+ ELC_EVENT_IIC_RXI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] = \
+ ELC_EVENT_IIC_TXI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] = \
+ ELC_EVENT_IIC_TEI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] = \
+ ELC_EVENT_IIC_ERI(DT_INST_PROP(index, channel)); \
+ \
+ IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, rxi, irq), \
+ DT_INST_IRQ_BY_NAME(index, rxi, priority), iic_master_rxi_isr, \
+ 0); \
+ IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, txi, irq), \
+ DT_INST_IRQ_BY_NAME(index, txi, priority), iic_master_txi_isr, \
+ 0); \
+ IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, tei, irq), \
+ DT_INST_IRQ_BY_NAME(index, tei, priority), iic_master_tei_isr, \
+ 0); \
+ IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, eri, irq), \
+ DT_INST_IRQ_BY_NAME(index, eri, priority), iic_master_eri_isr, \
+ 0); \
+ \
+ irq_enable(DT_INST_IRQ_BY_NAME(index, rxi, irq)); \
+ irq_enable(DT_INST_IRQ_BY_NAME(index, txi, irq)); \
+ irq_enable(DT_INST_IRQ_BY_NAME(index, tei, irq)); \
+ irq_enable(DT_INST_IRQ_BY_NAME(index, eri, irq)); \
+ } \
+ \
+ static const struct i2c_ra_iic_config i2c_ra_iic_config_##index = { \
+ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
+ .irq_config_func = i2c_ra_iic_irq_config_func##index, \
+ .noise_filter_stage = 1, /* Cannot be configured. */ \
+ .rise_time_s = DT_INST_PROP(index, rise_time_ns) / RA_IIC_MASTER_DIV_TIME_NS, \
+ .fall_time_s = DT_INST_PROP(index, fall_time_ns) / RA_IIC_MASTER_DIV_TIME_NS, \
+ .duty_cycle_percent = DT_INST_PROP(index, duty_cycle_percent), \
+ }; \
+ \
+ static struct i2c_ra_iic_data i2c_ra_iic_data_##index = { \
+ .fsp_config = \
+ { \
+ .channel = DT_INST_PROP(index, channel), \
+ .slave = 0, \
+ .rate = DT_INST_PROP(index, clock_frequency), \
+ .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, \
+ .ipl = DT_INST_PROP(index, interrupt_priority_level), \
+ .rxi_irq = DT_INST_IRQ_BY_NAME(index, rxi, irq), \
+ .txi_irq = DT_INST_IRQ_BY_NAME(index, txi, irq), \
+ .tei_irq = DT_INST_IRQ_BY_NAME(index, tei, irq), \
+ .eri_irq = DT_INST_IRQ_BY_NAME(index, eri, irq), \
+ .p_callback = i2c_ra_iic_callback, \
+ .p_context = DEVICE_DT_GET(DT_DRV_INST(index)), \
+ }, \
+ }; \
+ \
+ I2C_DEVICE_DT_INST_DEFINE(index, i2c_ra_iic_init, NULL, &i2c_ra_iic_data_##index, \
+ &i2c_ra_iic_config_##index, POST_KERNEL, \
+ CONFIG_I2C_INIT_PRIORITY, &i2c_ra_iic_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_RA_IIC_INIT)
diff --git a/drivers/i2c/i2c_sam_twihs_rtio.c b/drivers/i2c/i2c_sam_twihs_rtio.c
index db8d02e..bbece9d 100644
--- a/drivers/i2c/i2c_sam_twihs_rtio.c
+++ b/drivers/i2c/i2c_sam_twihs_rtio.c
@@ -164,8 +164,6 @@
/* Start the transfer by sending START condition */
twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
-
-
}
static void i2c_sam_twihs_complete(const struct device *dev, int status);
@@ -189,11 +187,11 @@
switch (sqe->op) {
case RTIO_OP_RX:
- read_msg_start(twihs, sqe->buf_len, dt_spec->addr);
+ read_msg_start(twihs, sqe->rx.buf_len, dt_spec->addr);
break;
case RTIO_OP_TX:
dev_data->buf_idx = 1;
- write_msg_start(twihs, sqe->buf, 0, dt_spec->addr);
+ write_msg_start(twihs, sqe->tx.buf, 0, dt_spec->addr);
break;
default:
LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
@@ -245,10 +243,10 @@
/* Byte received */
if (isr_status & TWIHS_SR_RXRDY) {
- sqe->buf[dev_data->buf_idx] = twihs->TWIHS_RHR;
+ sqe->rx.buf[dev_data->buf_idx] = twihs->TWIHS_RHR;
dev_data->buf_idx += 1;
- if (dev_data->buf_idx == sqe->buf_len - 1U) {
+ if (dev_data->buf_idx == sqe->rx.buf_len - 1U) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
}
@@ -256,7 +254,7 @@
/* Byte sent */
if (isr_status & TWIHS_SR_TXRDY) {
- if (dev_data->buf_idx == sqe->buf_len) {
+ if (dev_data->buf_idx == sqe->tx.buf_len) {
if (sqe->iodev_flags & RTIO_IODEV_I2C_STOP) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
@@ -268,7 +266,7 @@
return;
}
} else {
- twihs->TWIHS_THR = sqe->buf[dev_data->buf_idx++];
+ twihs->TWIHS_THR = sqe->tx.buf[dev_data->buf_idx++];
}
}
diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c
index 89b07cb..bb1354b 100644
--- a/drivers/i2s/i2s_mcux_sai.c
+++ b/drivers/i2s/i2s_mcux_sai.c
@@ -151,8 +151,9 @@
dma_stop(dev_dma, strm->dma_channel);
/* wait for TX FIFO to drain before disabling */
- while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0)
+ while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0) {
;
+ }
/* Disable the channel FIFO */
dev_cfg->base->TCR3 &= ~I2S_TCR3_TCE_MASK;
@@ -196,8 +197,9 @@
SAI_RxEnable(dev_cfg->base, false);
/* wait for Receiver to disable */
- while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK)
+ while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK) {
;
+ }
/* reset the FIFO pointer and clear error flags */
dev_cfg->base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK);
dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;
diff --git a/drivers/input/Kconfig.gt911 b/drivers/input/Kconfig.gt911
index e485746..89f55b5 100644
--- a/drivers/input/Kconfig.gt911
+++ b/drivers/input/Kconfig.gt911
@@ -26,4 +26,11 @@
help
Enable interrupt support (requires GPIO).
+config INPUT_GT911_MAX_TOUCH_POINTS
+ int "Touch Number"
+ default 1
+ range 1 5
+ help
+ Maximum number of touch points to be handled.
+ Multitouch is ignored if equal to 1.
endif # INPUT_GT911
diff --git a/drivers/input/input_esp32_touch_sensor.c b/drivers/input/input_esp32_touch_sensor.c
index 9f6858d..feb8fe6 100644
--- a/drivers/input/input_esp32_touch_sensor.c
+++ b/drivers/input/input_esp32_touch_sensor.c
@@ -162,7 +162,11 @@
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
- err = esp_intr_alloc(ETS_RTC_CORE_INTR_SOURCE, 0, intr_handler, (void *)handler_arg, NULL);
+
+ err = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(touch), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(touch), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(touch), 0, flags)),
+ intr_handler, (void *)handler_arg, NULL);
return err;
}
diff --git a/drivers/input/input_gt911.c b/drivers/input/input_gt911.c
index 23950cc..57c81b0 100644
--- a/drivers/input/input_gt911.c
+++ b/drivers/input/input_gt911.c
@@ -17,21 +17,26 @@
LOG_MODULE_REGISTER(gt911, CONFIG_INPUT_LOG_LEVEL);
/* GT911 used registers */
-#define DEVICE_ID BSWAP_16(0x8140U)
-#define REG_STATUS BSWAP_16(0x814EU)
-#define REG_FIRST_POINT BSWAP_16(0x814FU)
+#define DEVICE_ID BSWAP_16(0x8140U)
+#define REG_STATUS BSWAP_16(0x814EU)
/* REG_TD_STATUS: Touch points. */
-#define TOUCH_POINTS_MSK 0x0FU
+#define TOUCH_POINTS_MSK 0x0FU
/* REG_TD_STATUS: Pressed. */
-#define TOUCH_STATUS_MSK (1 << 7U)
+#define TOUCH_STATUS_MSK (1 << 7U)
/* The GT911's config */
-#define GT911_CONFIG_REG BSWAP_16(0x8047U)
-#define REG_CONFIG_VERSION GT911_CONFIG_REG
-#define REG_CONFIG_SIZE (186U)
-#define GT911_PRODUCT_ID (0x00313139U)
+#define REG_GT911_CONFIG BSWAP_16(0x8047U)
+#define REG_CONFIG_VERSION REG_GT911_CONFIG
+#define REG_CONFIG_TOUCH_NUM_OFFSET 0x5
+#define REG_CONFIG_SIZE 186U
+#define GT911_PRODUCT_ID 0x00313139U
+
+/* Points registers */
+#define REG_POINT_0 0x814F
+#define POINT_OFFSET 0x8
+#define REG_POINT_ADDR(n) BSWAP_16(REG_POINT_0 + POINT_OFFSET * n)
/** GT911 configuration (DT). */
struct gt911_config {
@@ -62,15 +67,15 @@
};
/** gt911 point reg */
-struct gt911_point_reg_t {
- uint8_t id; /*!< Track ID. */
- uint8_t lowX; /*!< Low byte of x coordinate. */
- uint8_t highX; /*!< High byte of x coordinate. */
- uint8_t lowY; /*!< Low byte of y coordinate. */
- uint8_t highY; /*!< High byte of x coordinate. */
- uint8_t lowSize; /*!< Low byte of point size. */
- uint8_t highSize; /*!< High byte of point size. */
- uint8_t reserved; /*!< Reserved. */
+struct gt911_point_reg {
+ uint8_t id; /*!< Track ID. */
+ uint8_t low_x; /*!< Low byte of x coordinate. */
+ uint8_t high_x; /*!< High byte of x coordinate. */
+ uint8_t low_y; /*!< Low byte of y coordinate. */
+ uint8_t high_y; /*!< High byte of x coordinate. */
+ uint8_t low_size; /*!< Low byte of point size. */
+ uint8_t high_size; /*!< High byte of point size. */
+ uint8_t reserved; /*!< Reserved. */
};
/*
@@ -78,8 +83,7 @@
* These wrappers handle the case where the GT911 did not accept the requested
* I2C address, and the alternate I2C address is used.
*/
-static int gt911_i2c_write(const struct device *dev,
- const uint8_t *buf, uint32_t num_bytes)
+static int gt911_i2c_write(const struct device *dev, const uint8_t *buf, uint32_t num_bytes)
{
const struct gt911_config *config = dev->config;
struct gt911_data *data = dev->data;
@@ -87,15 +91,14 @@
return i2c_write(config->bus.bus, buf, num_bytes, data->actual_address);
}
-static int gt911_i2c_write_read(const struct device *dev,
- const void *write_buf, size_t num_write,
+static int gt911_i2c_write_read(const struct device *dev, const void *write_buf, size_t num_write,
void *read_buf, size_t num_read)
{
const struct gt911_config *config = dev->config;
struct gt911_data *data = dev->data;
- return i2c_write_read(config->bus.bus, data->actual_address, write_buf,
- num_write, read_buf, num_read);
+ return i2c_write_read(config->bus.bus, data->actual_address, write_buf, num_write, read_buf,
+ num_read);
}
static int gt911_process(const struct device *dev)
@@ -103,28 +106,29 @@
int r;
uint16_t reg_addr;
uint8_t status;
+ uint8_t i;
+ uint8_t j;
+ uint16_t row;
+ uint16_t col;
uint8_t points;
- struct gt911_point_reg_t pointRegs;
- uint16_t row, col;
- bool pressed;
+ static uint8_t prev_points;
+ struct gt911_point_reg point_reg[CONFIG_INPUT_GT911_MAX_TOUCH_POINTS];
+ static struct gt911_point_reg prev_point_reg[CONFIG_INPUT_GT911_MAX_TOUCH_POINTS];
- /* obtain number of touch points (NOTE: multi-touch ignored) */
+ /* obtain number of touch points */
reg_addr = REG_STATUS;
- r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr),
- &status, sizeof(status));
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), &status, sizeof(status));
if (r < 0) {
return r;
}
- points = status & TOUCH_POINTS_MSK;
- if (points != 0U && points != 1U && (0 != (status & TOUCH_STATUS_MSK))) {
- points = 1;
- }
-
if (!(status & TOUCH_STATUS_MSK)) {
/* Status bit not set, ignore this event */
return 0;
}
+
+ points = status & TOUCH_POINTS_MSK;
+
/* need to clear the status */
uint8_t clear_buffer[3] = {(uint8_t)REG_STATUS, (uint8_t)(REG_STATUS >> 8), 0};
@@ -133,30 +137,56 @@
return r;
}
- /* obtain first point X, Y coordinates and event from:
- * REG_P1_XH, REG_P1_XL, REG_P1_YH, REG_P1_YL.
- */
- reg_addr = REG_FIRST_POINT;
- r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr),
- &pointRegs, sizeof(pointRegs));
- if (r < 0) {
- return r;
+ /* current points array */
+ for (i = 0; i <= points; i++) {
+ reg_addr = REG_POINT_ADDR(i);
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), &point_reg[i],
+ sizeof(point_reg[i]));
+
+ if (r < 0) {
+ return r;
+ }
}
- pressed = (points == 1);
- row = ((pointRegs.highY) << 8U) | pointRegs.lowY;
- col = ((pointRegs.highX) << 8U) | pointRegs.lowX;
+ /* touch events */
+ for (i = 0; i < points; i++) {
+ if (CONFIG_INPUT_GT911_MAX_TOUCH_POINTS > 1) {
+ input_report_abs(dev, INPUT_ABS_MT_SLOT, point_reg[i].id, true, K_FOREVER);
+ }
- LOG_DBG("pressed: %d, row: %d, col: %d", pressed, row, col);
+ row = ((point_reg[i].high_y) << 8U) | point_reg[i].low_y;
+ col = ((point_reg[i].high_x) << 8U) | point_reg[i].low_x;
- if (pressed) {
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
- } else {
- input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
}
+ /* release events */
+ for (i = 0; i < prev_points; i++) {
+ /* We look for the prev_point in the current points list */
+ for (j = 0; j < points; j++) {
+ if (prev_point_reg[i].id == point_reg[j].id) {
+ break;
+ }
+ }
+
+ if (j == points) {
+ if (CONFIG_INPUT_GT911_MAX_TOUCH_POINTS > 1) {
+ input_report_abs(dev, INPUT_ABS_MT_SLOT, prev_point_reg[i].id, true,
+ K_FOREVER);
+ }
+ row = ((prev_point_reg[i].high_y) << 8U) | prev_point_reg[i].low_y;
+ col = ((prev_point_reg[i].high_x) << 8U) | prev_point_reg[i].low_x;
+ input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
+ input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
+ input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
+ }
+ }
+
+ memcpy(prev_point_reg, point_reg, sizeof(point_reg));
+ prev_points = points;
+
return 0;
}
@@ -168,8 +198,7 @@
}
#ifdef CONFIG_INPUT_GT911_INTERRUPT
-static void gt911_isr_handler(const struct device *dev,
- struct gpio_callback *cb, uint32_t pins)
+static void gt911_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct gt911_data *data = CONTAINER_OF(cb, struct gt911_data, int_gpio_cb);
@@ -187,7 +216,7 @@
static uint8_t gt911_get_firmware_checksum(const uint8_t *firmware)
{
uint8_t sum = 0;
- uint16_t i = 0;
+ uint16_t i = 0;
for (i = 0; i < REG_CONFIG_SIZE - 2U; i++) {
sum += (*firmware);
@@ -199,7 +228,7 @@
static bool gt911_verify_firmware(const uint8_t *firmware)
{
- return ((firmware[REG_CONFIG_VERSION - GT911_CONFIG_REG] != 0U) &&
+ return ((firmware[REG_CONFIG_VERSION - REG_GT911_CONFIG] != 0U) &&
(gt911_get_firmware_checksum(firmware) == firmware[REG_CONFIG_SIZE - 2U]));
}
@@ -273,15 +302,13 @@
}
#ifdef CONFIG_INPUT_GT911_INTERRUPT
- r = gpio_pin_interrupt_configure_dt(&config->int_gpio,
- GPIO_INT_EDGE_TO_ACTIVE);
+ r = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (r < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt.");
return r;
}
- gpio_init_callback(&data->int_gpio_cb, gt911_isr_handler,
- BIT(config->int_gpio.pin));
+ gpio_init_callback(&data->int_gpio_cb, gt911_isr_handler, BIT(config->int_gpio.pin));
#else
k_timer_init(&data->timer, gt911_timer_handler, NULL);
#endif
@@ -299,20 +326,18 @@
* route the INT pin, or can only read it as an input (IE when
* using a level shifter).
*/
- r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr),
- ®_id, sizeof(reg_id));
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id, sizeof(reg_id));
if (r < 0) {
/* Try alternate address */
data->actual_address = config->alt_addr;
- r = gt911_i2c_write_read(dev, ®_addr,
- sizeof(reg_addr),
- ®_id, sizeof(reg_id));
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id,
+ sizeof(reg_id));
LOG_INF("Device did not accept I2C address, "
- "updated to 0x%02X", data->actual_address);
+ "updated to 0x%02X",
+ data->actual_address);
}
} else {
- r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr),
- ®_id, sizeof(reg_id));
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id, sizeof(reg_id));
}
if (r < 0) {
LOG_ERR("Device did not respond to I2C request");
@@ -324,24 +349,27 @@
}
/* need to setup the firmware first: read and write */
- uint8_t gt911Config[REG_CONFIG_SIZE + 2] = {
- (uint8_t)GT911_CONFIG_REG, (uint8_t)(GT911_CONFIG_REG >> 8)
- };
+ uint8_t gt911_config_firmware[REG_CONFIG_SIZE + 2] = {(uint8_t)REG_GT911_CONFIG,
+ (uint8_t)(REG_GT911_CONFIG >> 8)};
- reg_addr = GT911_CONFIG_REG;
- r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr),
- gt911Config + 2, REG_CONFIG_SIZE);
+ reg_addr = REG_GT911_CONFIG;
+ r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), gt911_config_firmware + 2,
+ REG_CONFIG_SIZE);
if (r < 0) {
return r;
}
- if (!gt911_verify_firmware(gt911Config + 2)) {
+ if (!gt911_verify_firmware(gt911_config_firmware + 2)) {
return -ENODEV;
}
- gt911Config[REG_CONFIG_SIZE] = gt911_get_firmware_checksum(gt911Config + 2);
- gt911Config[REG_CONFIG_SIZE + 1] = 1;
+ gt911_config_firmware[REG_CONFIG_TOUCH_NUM_OFFSET + 2] =
+ CONFIG_INPUT_GT911_MAX_TOUCH_POINTS;
- r = gt911_i2c_write(dev, gt911Config, sizeof(gt911Config));
+ gt911_config_firmware[REG_CONFIG_SIZE] =
+ gt911_get_firmware_checksum(gt911_config_firmware + 2);
+ gt911_config_firmware[REG_CONFIG_SIZE + 1] = 1;
+
+ r = gt911_i2c_write(dev, gt911_config_firmware, sizeof(gt911_config_firmware));
if (r < 0) {
return r;
}
@@ -360,17 +388,15 @@
return 0;
}
-#define GT911_INIT(index) \
- static const struct gt911_config gt911_config_##index = { \
- .bus = I2C_DT_SPEC_INST_GET(index), \
- .rst_gpio = GPIO_DT_SPEC_INST_GET_OR(index, reset_gpios, {0}), \
- .int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \
- .alt_addr = DT_INST_PROP_OR(index, alt_addr, 0), \
- }; \
- static struct gt911_data gt911_data_##index; \
- DEVICE_DT_INST_DEFINE(index, gt911_init, NULL, \
- >911_data_##index, >911_config_##index, \
- POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
- NULL);
+#define GT911_INIT(index) \
+ static const struct gt911_config gt911_config_##index = { \
+ .bus = I2C_DT_SPEC_INST_GET(index), \
+ .rst_gpio = GPIO_DT_SPEC_INST_GET_OR(index, reset_gpios, {0}), \
+ .int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \
+ .alt_addr = DT_INST_PROP_OR(index, alt_addr, 0), \
+ }; \
+ static struct gt911_data gt911_data_##index; \
+ DEVICE_DT_INST_DEFINE(index, gt911_init, NULL, >911_data_##index, >911_config_##index, \
+ POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(GT911_INIT)
diff --git a/drivers/input/input_pmw3610.c b/drivers/input/input_pmw3610.c
index bcf5549..f88e6b2 100644
--- a/drivers/input/input_pmw3610.c
+++ b/drivers/input/input_pmw3610.c
@@ -77,6 +77,7 @@
#define PERFORMANCE_FMODE_MASK (0x0f << 4)
#define PERFORMANCE_FMODE_NORMAL (0x00 << 4)
#define PERFORMANCE_FMODE_FORCE_AWAKE (0x0f << 4)
+#define POWER_UP_RESET 0x5a
#define POWER_UP_WAKEUP 0x96
#define SHUTDOWN_ENABLE 0xe7
#define SPI_PAGE0_1 0xff
@@ -363,6 +364,13 @@
gpio_pin_set_dt(&cfg->reset_gpio, 0);
k_sleep(K_MSEC(RESET_DELAY_MS));
+ } else {
+ ret = pmw3610_write_reg(dev, PMW3610_POWER_UP_RESET, POWER_UP_RESET);
+ if (ret < 0) {
+ return ret;
+ }
+
+ k_sleep(K_MSEC(RESET_DELAY_MS));
}
ret = pmw3610_read_reg(dev, PMW3610_PROD_ID, &val);
diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32
index 1b4a775..507161f 100644
--- a/drivers/interrupt_controller/Kconfig.esp32
+++ b/drivers/interrupt_controller/Kconfig.esp32
@@ -7,7 +7,7 @@
bool "Interrupt allocator for Xtensa-based Espressif SoCs"
default y
depends on SOC_FAMILY_ESPRESSIF_ESP32
- depends on !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
+ depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
help
Enable custom interrupt allocator for Espressif SoCs based on Xtensa
architecture.
diff --git a/drivers/interrupt_controller/Kconfig.esp32c3 b/drivers/interrupt_controller/Kconfig.esp32c3
index 4ce0674..c1a7239 100644
--- a/drivers/interrupt_controller/Kconfig.esp32c3
+++ b/drivers/interrupt_controller/Kconfig.esp32c3
@@ -4,7 +4,7 @@
config INTC_ESP32C3
bool "ESP32C3 interrupt controller driver"
depends on SOC_FAMILY_ESPRESSIF_ESP32
- depends on SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
+ depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
default y
help
Enables the esp32c3 interrupt controller driver to handle ISR
diff --git a/drivers/interrupt_controller/intc_esp32c3.c b/drivers/interrupt_controller/intc_esp32c3.c
index b213158..7e85450 100644
--- a/drivers/interrupt_controller/intc_esp32c3.c
+++ b/drivers/interrupt_controller/intc_esp32c3.c
@@ -68,7 +68,7 @@
static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0};
-#if defined(CONFIG_SOC_SERIES_ESP32C3)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
static uint32_t esp_intr_find_irq_for_source(uint32_t source)
{
diff --git a/drivers/interrupt_controller/intc_ite_it8xxx2.c b/drivers/interrupt_controller/intc_ite_it8xxx2.c
index 639256e..ca30943 100644
--- a/drivers/interrupt_controller/intc_ite_it8xxx2.c
+++ b/drivers/interrupt_controller/intc_ite_it8xxx2.c
@@ -282,8 +282,9 @@
#endif
/* Ensure interrupts of soc are disabled at default */
- for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
+ for (int i = 0; i < ARRAY_SIZE(reg_enable); i++) {
*reg_enable[i] = 0;
+ }
/*
* WORKAROUND: In the it8xxx2 chip, the interrupt for INT0 is reserved.
diff --git a/drivers/interrupt_controller/intc_plic.c b/drivers/interrupt_controller/intc_plic.c
index 0d00056..cf7fca0 100644
--- a/drivers/interrupt_controller/intc_plic.c
+++ b/drivers/interrupt_controller/intc_plic.c
@@ -295,8 +295,9 @@
const uint32_t local_irq = irq_from_level_2(irq);
mem_addr_t prio_addr = config->prio + (local_irq * sizeof(uint32_t));
- if (priority > config->max_prio)
+ if (priority > config->max_prio) {
priority = config->max_prio;
+ }
sys_write32(priority, prio_addr);
}
diff --git a/drivers/interrupt_controller/intc_swerv_pic.c b/drivers/interrupt_controller/intc_swerv_pic.c
index 96eb248..9ac4c41 100644
--- a/drivers/interrupt_controller/intc_swerv_pic.c
+++ b/drivers/interrupt_controller/intc_swerv_pic.c
@@ -229,8 +229,9 @@
{
uint32_t mie;
- if (irq > RISCV_MAX_GENERIC_IRQ)
+ if (irq > RISCV_MAX_GENERIC_IRQ) {
return swerv_pic_irq_is_enabled(irq);
+ }
__asm__ volatile ("csrr %0, mie" : "=r" (mie));
diff --git a/drivers/ipm/ipm_esp32.c b/drivers/ipm/ipm_esp32.c
index ad27392..27fb90b 100644
--- a/drivers/ipm/ipm_esp32.c
+++ b/drivers/ipm/ipm_esp32.c
@@ -33,8 +33,12 @@
};
struct esp32_ipm_config {
- uint32_t irq_source_pro_cpu;
- uint32_t irq_source_app_cpu;
+ int irq_source_pro_cpu;
+ int irq_priority_pro_cpu;
+ int irq_flags_pro_cpu;
+ int irq_source_app_cpu;
+ int irq_priority_app_cpu;
+ int irq_flags_app_cpu;
};
struct esp32_ipm_data {
@@ -68,9 +72,10 @@
}
/* first of all take the own of the shared memory */
- while (!atomic_cas(&dev_data->control->lock,
- ESP32_IPM_LOCK_FREE_VAL, dev_data->this_core_id))
+ while (!atomic_cas(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL,
+ dev_data->this_core_id)) {
;
+ }
if (dev_data->cb) {
@@ -205,6 +210,7 @@
{
struct esp32_ipm_data *data = (struct esp32_ipm_data *)dev->data;
struct esp32_ipm_config *cfg = (struct esp32_ipm_config *)dev->config;
+ int ret;
data->this_core_id = esp_core_id();
data->other_core_id = (data->this_core_id == 0) ? 1 : 0;
@@ -216,27 +222,42 @@
/* pro_cpu is responsible to initialize the lock of shared memory */
if (data->this_core_id == 0) {
- esp_intr_alloc(cfg->irq_source_pro_cpu,
- ESP_INTR_FLAG_IRAM,
- (intr_handler_t)esp32_ipm_isr,
- (void *)dev,
- NULL);
+ ret = esp_intr_alloc(cfg->irq_source_pro_cpu,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority_pro_cpu) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags_pro_cpu) |
+ ESP_INTR_FLAG_IRAM,
+ (intr_handler_t)esp32_ipm_isr,
+ (void *)dev,
+ NULL);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ return ret;
+ }
atomic_set(&data->control->lock, ESP32_IPM_LOCK_FREE_VAL);
} else {
/* app_cpu wait for initialization from pro_cpu, then takes it,
* after that releases
*/
- esp_intr_alloc(cfg->irq_source_app_cpu,
- ESP_INTR_FLAG_IRAM,
- (intr_handler_t)esp32_ipm_isr,
- (void *)dev,
- NULL);
+ ret = esp_intr_alloc(cfg->irq_source_app_cpu,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority_app_cpu) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags_app_cpu) |
+ ESP_INTR_FLAG_IRAM,
+ (intr_handler_t)esp32_ipm_isr,
+ (void *)dev,
+ NULL);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ return ret;
+ }
LOG_DBG("Waiting CPU0 to sync");
while (!atomic_cas(&data->control->lock,
- ESP32_IPM_LOCK_FREE_VAL, data->this_core_id))
+ ESP32_IPM_LOCK_FREE_VAL, data->this_core_id)) {
;
+ }
atomic_set(&data->control->lock, ESP32_IPM_LOCK_FREE_VAL);
@@ -263,9 +284,13 @@
#define ESP32_IPM_INIT(idx) \
\
-static struct esp32_ipm_config esp32_ipm_device_cfg_##idx = { \
- .irq_source_pro_cpu = DT_INST_IRQN(idx), \
- .irq_source_app_cpu = DT_INST_IRQN(idx) + 1, \
+static struct esp32_ipm_config esp32_ipm_device_cfg_##idx = { \
+ .irq_source_pro_cpu = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ .irq_priority_pro_cpu = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
+ .irq_flags_pro_cpu = DT_INST_IRQ_BY_IDX(idx, 0, flags), \
+ .irq_source_app_cpu = DT_INST_IRQ_BY_IDX(idx, 1, irq), \
+ .irq_priority_app_cpu = DT_INST_IRQ_BY_IDX(idx, 1, priority), \
+ .irq_flags_app_cpu = DT_INST_IRQ_BY_IDX(idx, 1, flags), \
}; \
\
static struct esp32_ipm_data esp32_ipm_device_data_##idx = { \
diff --git a/drivers/ipm/ipm_ivshmem.c b/drivers/ipm/ipm_ivshmem.c
index 46e009f..f0d18a4 100644
--- a/drivers/ipm/ipm_ivshmem.c
+++ b/drivers/ipm/ipm_ivshmem.c
@@ -60,8 +60,9 @@
/* get ready for next signal */
k_poll_signal_reset(&sig);
- if (dev_data->cb)
+ if (dev_data->cb) {
dev_data->cb(dev, dev_data->user_data, 0, NULL);
+ }
}
}
diff --git a/drivers/ipm/ipm_stm32_hsem.c b/drivers/ipm/ipm_stm32_hsem.c
index 1d29f1b..b19e32d 100644
--- a/drivers/ipm/ipm_stm32_hsem.c
+++ b/drivers/ipm/ipm_stm32_hsem.c
@@ -52,8 +52,9 @@
uint32_t mask_semid = (1U << data->rx_semid);
/* Check semaphore rx_semid interrupt status */
- if (!ll_hsem_isactiveflag_cmisr(HSEM, mask_semid))
+ if (!ll_hsem_isactiveflag_cmisr(HSEM, mask_semid)) {
return;
+ }
/* Notify user with NULL data pointer */
if (data->callback) {
diff --git a/drivers/mbox/Kconfig.nrfx b/drivers/mbox/Kconfig.nrfx
index 70aefd8..79b1230 100644
--- a/drivers/mbox/Kconfig.nrfx
+++ b/drivers/mbox/Kconfig.nrfx
@@ -3,7 +3,8 @@
config MBOX_NRFX_IPC
bool "MBOX NRF IPC driver"
- depends on HAS_HW_NRF_IPC
+ depends on DT_HAS_NORDIC_MBOX_NRF_IPC_ENABLED
+ default y
select NRFX_IPC
help
Driver for Nordic nRF messaging unit, based
diff --git a/drivers/mbox/mbox_nxp_s32_mru.c b/drivers/mbox/mbox_nxp_s32_mru.c
index 2c6246d..4a3f8cd 100644
--- a/drivers/mbox/mbox_nxp_s32_mru.c
+++ b/drivers/mbox/mbox_nxp_s32_mru.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -80,9 +80,9 @@
tx_cfg.NumTxMB = MRU_MAX_MBOX_PER_CHAN;
tx_cfg.LastTxMBIndex = MRU_MAX_MBOX_PER_CHAN - 1;
tx_cfg.MBAddList = (volatile uint32 * const *)tx_mbox_addr;
- tx_cfg.ChMBSTATAdd = &cfg->base->CHXCONFIG[channel].CH_MBSTAT;
+ tx_cfg.ChMBSTATAdd = (volatile uint32 *)&cfg->base->CHXCONFIG[channel].CH_MBSTAT;
- status = Mru_Ip_Transmit(&tx_cfg, (const uint32_t *)msg->data);
+ status = Mru_Ip_Transmit(&tx_cfg, (const uint32 *)msg->data);
return (status == MRU_IP_STATUS_SUCCESS ? 0 : -EBUSY);
}
@@ -208,11 +208,11 @@
}
#define MRU_CH_RX_CFG(i, n) \
- static volatile const uint32_t * const \
+ static volatile const uint32 * const \
nxp_s32_mru_##n##_ch_##i##_rx_mbox_addr[MRU_MAX_MBOX_PER_CHAN] = { \
- (uint32_t *const)MRU_MBOX_ADDR(n, i, 0), \
+ (uint32 *const)MRU_MBOX_ADDR(n, i, 0), \
}; \
- static uint32_t nxp_s32_mru_##n##_ch_##i##_buf[MRU_MAX_MBOX_PER_CHAN]; \
+ static uint32 nxp_s32_mru_##n##_ch_##i##_buf[MRU_MAX_MBOX_PER_CHAN]; \
static const Mru_Ip_ReceiveChannelType nxp_s32_mru_##n##_ch_##i##_rx_cfg = { \
.ChannelId = i, \
.ChannelIndex = i, \
@@ -235,18 +235,18 @@
#define MRU_CH_CFG(i, n) \
{ \
- .ChCFG0Add = &MRU_BASE(n)->CHXCONFIG[i].CH_CFG0, \
+ .ChCFG0Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG0, \
.ChCFG0 = RTU_MRU_CH_CFG0_IE(0) | RTU_MRU_CH_CFG0_MBE0(0), \
- .ChCFG1Add = &MRU_BASE(n)->CHXCONFIG[i].CH_CFG1, \
+ .ChCFG1Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG1, \
.ChCFG1 = RTU_MRU_CH_CFG1_MBIC0(MRU_INT_GROUP(DT_INST_IRQN(n))), \
- .ChMBSTATAdd = &MRU_BASE(n)->CHXCONFIG[i].CH_MBSTAT, \
+ .ChMBSTATAdd = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_MBSTAT, \
.NumMailbox = MRU_MAX_MBOX_PER_CHAN, \
.MBLinkReceiveChCfg = nxp_s32_mru_##n##_ch_##i##_rx_link_cfg \
}
/* Callback wrapper to adapt MRU's baremetal driver callback to Zephyr's mbox driver callback */
#define MRU_CALLBACK_WRAPPER_FUNC(n) \
- void nxp_s32_mru_##n##_cb(uint8_t channel, const uint32_t *buf, uint8_t mbox_count) \
+ void nxp_s32_mru_##n##_cb(uint8_t channel, const uint32 *buf, uint8_t mbox_count) \
{ \
const struct device *dev = DEVICE_DT_INST_GET(n); \
struct nxp_s32_mru_data *data = dev->data; \
@@ -283,8 +283,8 @@
.ChannelCfg = COND_CODE_0(MRU_RX_CHANNELS(n), \
(NULL), (nxp_s32_mru_##n##_ch_cfg)), \
.NOTIFYAdd = { \
- &MRU_BASE(n)->NOTIFY[0], \
- &MRU_BASE(n)->NOTIFY[1] \
+ (const volatile uint32 *)&MRU_BASE(n)->NOTIFY[0], \
+ (const volatile uint32 *)&MRU_BASE(n)->NOTIFY[1] \
}, \
}, \
.irq_group = MRU_INT_GROUP(DT_INST_IRQN(n)), \
diff --git a/drivers/mbox/mbox_stm32_hsem.c b/drivers/mbox/mbox_stm32_hsem.c
index a1e9ca9..3f416c2 100644
--- a/drivers/mbox/mbox_stm32_hsem.c
+++ b/drivers/mbox/mbox_stm32_hsem.c
@@ -115,8 +115,9 @@
struct mbox_stm32_hsem_data *data = dev->data;
/* Check semaphore rx_semid interrupt status */
- if (!stm32_hsem_is_rx_interrupt_active())
+ if (!stm32_hsem_is_rx_interrupt_active()) {
return;
+ }
if (data->cb != NULL) {
data->cb(dev, MBOX_RX_HSEM_ID, data->user_data, NULL);
diff --git a/drivers/mdio/mdio_shell.c b/drivers/mdio/mdio_shell.c
index ac79fbc..51d61ea 100644
--- a/drivers/mdio/mdio_shell.c
+++ b/drivers/mdio/mdio_shell.c
@@ -37,6 +37,8 @@
#define DT_DRV_COMPAT nxp_enet_qos_mdio
#elif DT_HAS_COMPAT_STATUS_OKAY(litex_liteeth_mdio)
#define DT_DRV_COMPAT litex_liteeth_mdio
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
+#define DT_DRV_COMPAT st_stm32_mdio
#else
#error "No known devicetree compatible match for MDIO shell"
#endif
diff --git a/drivers/memc/Kconfig b/drivers/memc/Kconfig
index 54c30e1..0e351bc 100644
--- a/drivers/memc/Kconfig
+++ b/drivers/memc/Kconfig
@@ -11,10 +11,6 @@
if MEMC
-module = MEMC
-module-str = memc
-source "subsys/logging/Kconfig.template.log_config"
-
config MEMC_INIT_PRIORITY
int "Initialization priority"
default 0
@@ -35,4 +31,8 @@
source "drivers/memc/Kconfig.mspi"
+module = MEMC
+module-str = memc
+source "subsys/logging/Kconfig.template.log_config"
+
endif
diff --git a/drivers/memc/Kconfig.mcux b/drivers/memc/Kconfig.mcux
index dd6c2da..7d23180 100644
--- a/drivers/memc/Kconfig.mcux
+++ b/drivers/memc/Kconfig.mcux
@@ -54,6 +54,11 @@
bool
select PINCTRL
+# Avoid RWW hazards by defaulting logging to disabled
+choice MEMC_LOG_LEVEL_CHOICE
+ default MEMC_LOG_LEVEL_OFF if FLASH_MCUX_FLEXSPI_XIP
+endchoice
+
endif # DT_HAS_NXP_IMX_FLEXSPI_ENABLED
diff --git a/drivers/memc/memc_mspi_aps6404l.c b/drivers/memc/memc_mspi_aps6404l.c
index 86503bc..300736c 100644
--- a/drivers/memc/memc_mspi_aps6404l.c
+++ b/drivers/memc/memc_mspi_aps6404l.c
@@ -144,13 +144,14 @@
if (cfg->sw_multi_periph) {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
+ MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
+ }
} else {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
- MSPI_DEVICE_CONFIG_NONE, NULL))
+ MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
-
+ }
}
}
@@ -159,8 +160,9 @@
const struct memc_mspi_aps6404l_config *cfg = psram->config;
struct memc_mspi_aps6404l_data *data = psram->data;
- while (mspi_get_channel_status(cfg->bus, cfg->port))
+ while (mspi_get_channel_status(cfg->bus, cfg->port)) {
;
+ }
k_sem_give(&data->lock);
}
diff --git a/drivers/mipi_dbi/CMakeLists.txt b/drivers/mipi_dbi/CMakeLists.txt
index 5e9f475..dcbf295 100644
--- a/drivers/mipi_dbi/CMakeLists.txt
+++ b/drivers/mipi_dbi/CMakeLists.txt
@@ -6,6 +6,7 @@
zephyr_sources_ifdef(CONFIG_MIPI_DBI_SMARTBOND mipi_dbi_smartbond.c)
zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_LCDIC mipi_dbi_nxp_lcdic.c)
zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF mipi_dbi_nxp_flexio_lcdif.c)
+zephyr_sources_ifdef(CONFIG_MIPI_DBI_STM32_FMC mipi_dbi_stm32_fmc.c)
# Data bus width is used by the SDK driver and processes it as a compile time option
if(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF)
dt_chosen(flexio0_lcd PROPERTY "zephyr,display")
diff --git a/drivers/mipi_dbi/Kconfig b/drivers/mipi_dbi/Kconfig
index 51181dd..0782664 100644
--- a/drivers/mipi_dbi/Kconfig
+++ b/drivers/mipi_dbi/Kconfig
@@ -25,5 +25,6 @@
source "drivers/mipi_dbi/Kconfig.smartbond"
source "drivers/mipi_dbi/Kconfig.nxp_lcdic"
source "drivers/mipi_dbi/Kconfig.nxp_flexio_lcdif"
+source "drivers/mipi_dbi/Kconfig.stm32_fmc"
endif
diff --git a/drivers/mipi_dbi/Kconfig.stm32_fmc b/drivers/mipi_dbi/Kconfig.stm32_fmc
new file mode 100644
index 0000000..b016cb5
--- /dev/null
+++ b/drivers/mipi_dbi/Kconfig.stm32_fmc
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Bootlin
+# SPDX-License-Identifier: Apache-2.0
+
+config MIPI_DBI_STM32_FMC
+ bool "MIPI DBI driver for STM32 FMC"
+ default y
+ depends on DT_HAS_ST_STM32_FMC_MIPI_DBI_ENABLED
+ select MEMC
+ help
+ Enable support for MIPI DBI driver for controller based on the stm32 FMC.
+
+if MIPI_DBI_STM32_FMC
+
+config MIPI_DBI_STM32_FMC_MEM_BARRIER
+ bool "Adds memory barrier after every address and data register access"
+ default y
+
+endif # MIPI_DBI_STM32_FMC
diff --git a/drivers/mipi_dbi/mipi_dbi_nxp_flexio_lcdif.c b/drivers/mipi_dbi/mipi_dbi_nxp_flexio_lcdif.c
index 15156cc..fac05f7 100644
--- a/drivers/mipi_dbi/mipi_dbi_nxp_flexio_lcdif.c
+++ b/drivers/mipi_dbi/mipi_dbi_nxp_flexio_lcdif.c
@@ -336,7 +336,7 @@
}
-static int mipi_dbi_flexio_lcdif_reset(const struct device *dev, uint32_t delay)
+static int mipi_dbi_flexio_lcdif_reset(const struct device *dev, k_timeout_t delay)
{
int err;
const struct mcux_flexio_lcdif_config *config = dev->config;
@@ -357,7 +357,7 @@
return err;
}
- k_msleep(delay);
+ k_sleep(delay);
err = gpio_pin_set_dt(&config->reset, 1);
if (err < 0) {
diff --git a/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c b/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c
index 7a44bee..5129396 100644
--- a/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c
+++ b/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c
@@ -558,12 +558,13 @@
return ret;
}
-static int mipi_dbi_lcdic_reset(const struct device *dev, uint32_t delay)
+static int mipi_dbi_lcdic_reset(const struct device *dev, k_timeout_t delay)
{
const struct mipi_dbi_lcdic_config *config = dev->config;
LCDIC_Type *base = config->base;
uint32_t lcdic_freq;
uint8_t rst_width, pulse_cnt;
+ uint32_t delay_ms = k_ticks_to_ms_ceil32(delay);
/* Calculate delay based off timer0 ratio. Formula given
* by RM is as follows:
@@ -574,8 +575,7 @@
&lcdic_freq)) {
return -EIO;
}
- rst_width = (delay * (lcdic_freq)) /
- ((1 << LCDIC_TIMER0_RATIO) * MSEC_PER_SEC);
+ rst_width = (delay_ms * (lcdic_freq)) / ((1 << LCDIC_TIMER0_RATIO) * MSEC_PER_SEC);
/* If rst_width is larger than max value supported by hardware,
* increase the pulse count (rounding up)
*/
diff --git a/drivers/mipi_dbi/mipi_dbi_smartbond.c b/drivers/mipi_dbi/mipi_dbi_smartbond.c
index 9569020..5a5cc27 100644
--- a/drivers/mipi_dbi/mipi_dbi_smartbond.c
+++ b/drivers/mipi_dbi/mipi_dbi_smartbond.c
@@ -123,7 +123,7 @@
}
#if MIPI_DBI_SMARTBOND_IS_RESET_AVAILABLE
-static int mipi_dbi_smartbond_reset(const struct device *dev, uint32_t delay)
+static int mipi_dbi_smartbond_reset(const struct device *dev, k_timeout_t delay)
{
const struct mipi_dbi_smartbond_config *config = dev->config;
int ret;
@@ -138,7 +138,7 @@
LOG_ERR("Cannot drive reset signal");
return ret;
}
- k_msleep(delay);
+ k_sleep(delay);
return gpio_pin_set_dt(&config->reset, 0);
}
diff --git a/drivers/mipi_dbi/mipi_dbi_spi.c b/drivers/mipi_dbi/mipi_dbi_spi.c
index 13d4e30..abbb029 100644
--- a/drivers/mipi_dbi/mipi_dbi_spi.c
+++ b/drivers/mipi_dbi/mipi_dbi_spi.c
@@ -42,8 +42,9 @@
* (first bit sent in each word) indicates if the word is a command or
* data. Typically 0 indicates a command and 1 indicates data, but some
* displays may vary.
+ * Index starts from 0 so that BIT(8) means 9th bit.
*/
-#define MIPI_DBI_DC_BIT BIT(9)
+#define MIPI_DBI_DC_BIT BIT(8)
static int mipi_dbi_spi_write_helper(const struct device *dev,
const struct mipi_dbi_config *dbi_config,
@@ -250,7 +251,7 @@
return spec->port != NULL;
}
-static int mipi_dbi_spi_reset(const struct device *dev, uint32_t delay)
+static int mipi_dbi_spi_reset(const struct device *dev, k_timeout_t delay)
{
const struct mipi_dbi_spi_config *config = dev->config;
int ret;
@@ -263,7 +264,7 @@
if (ret < 0) {
return ret;
}
- k_msleep(delay);
+ k_sleep(delay);
return gpio_pin_set_dt(&config->reset, 0);
}
diff --git a/drivers/mipi_dbi/mipi_dbi_stm32_fmc.c b/drivers/mipi_dbi/mipi_dbi_stm32_fmc.c
new file mode 100644
index 0000000..f71c36f
--- /dev/null
+++ b/drivers/mipi_dbi/mipi_dbi_stm32_fmc.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2024 Bootlin
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT st_stm32_fmc_mipi_dbi
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/mipi_dbi.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mipi_dbi_stm32_fmc, CONFIG_MIPI_DBI_LOG_LEVEL);
+
+struct mipi_dbi_stm32_fmc_config {
+ /* Reset GPIO */
+ const struct gpio_dt_spec reset;
+ /* Power GPIO */
+ const struct gpio_dt_spec power;
+ mem_addr_t register_addr;
+ mem_addr_t data_addr;
+ uint32_t fmc_address_setup_time;
+ uint32_t fmc_data_setup_time;
+ uint32_t fmc_memory_width;
+};
+
+struct mipi_dbi_stm32_fmc_data {
+ const struct mipi_dbi_config *dbi_config;
+};
+
+int mipi_dbi_stm32_fmc_check_config(const struct device *dev,
+ const struct mipi_dbi_config *dbi_config)
+{
+ const struct mipi_dbi_stm32_fmc_config *config = dev->config;
+ struct mipi_dbi_stm32_fmc_data *data = dev->data;
+ uint32_t fmc_write_cycles;
+
+ if (data->dbi_config == dbi_config) {
+ return 0;
+ }
+
+ if (dbi_config->mode != MIPI_DBI_MODE_8080_BUS_16_BIT) {
+ LOG_ERR("Only support Intel 8080 16-bits");
+ return -ENOTSUP;
+ }
+
+ if (config->fmc_memory_width != FMC_NORSRAM_MEM_BUS_WIDTH_16) {
+ LOG_ERR("Only supports 16-bit bus width");
+ return -EINVAL;
+ }
+
+ uint32_t hclk_freq =
+ STM32_AHB_PRESCALER * DT_PROP(STM32_CLOCK_CONTROL_NODE, clock_frequency);
+
+ /* According to the FMC documentation*/
+ fmc_write_cycles =
+ ((config->fmc_address_setup_time + 1) + (config->fmc_data_setup_time + 1)) * 1;
+
+ if (hclk_freq / fmc_write_cycles > dbi_config->config.frequency) {
+ LOG_ERR("Frequency is too high for the display controller");
+ return -EINVAL;
+ }
+
+ data->dbi_config = dbi_config;
+ return 0;
+}
+
+int mipi_dbi_stm32_fmc_command_write(const struct device *dev,
+ const struct mipi_dbi_config *dbi_config, uint8_t cmd,
+ const uint8_t *data_buf, size_t len)
+{
+ const struct mipi_dbi_stm32_fmc_config *config = dev->config;
+ int ret;
+ size_t i;
+
+ ret = mipi_dbi_stm32_fmc_check_config(dev, dbi_config);
+ if (ret < 0) {
+ return ret;
+ }
+
+ sys_write16(cmd, config->register_addr);
+ if (IS_ENABLED(CONFIG_MIPI_DBI_STM32_FMC_MEM_BARRIER)) {
+ barrier_dsync_fence_full();
+ }
+
+ for (i = 0U; i < len; i++) {
+ sys_write16((uint16_t)data_buf[i], config->data_addr);
+ if (IS_ENABLED(CONFIG_MIPI_DBI_STM32_FMC_MEM_BARRIER)) {
+ barrier_dsync_fence_full();
+ }
+ }
+
+ return 0;
+}
+
+static int mipi_dbi_stm32_fmc_write_display(const struct device *dev,
+ const struct mipi_dbi_config *dbi_config,
+ const uint8_t *framebuf,
+ struct display_buffer_descriptor *desc,
+ enum display_pixel_format pixfmt)
+{
+ const struct mipi_dbi_stm32_fmc_config *config = dev->config;
+ size_t i;
+ int ret;
+
+ ret = mipi_dbi_stm32_fmc_check_config(dev, dbi_config);
+ if (ret < 0) {
+ return ret;
+ }
+
+ for (i = 0U; i < desc->buf_size; i += 2) {
+ sys_write16(sys_get_le16(&framebuf[i]), config->data_addr);
+ if (IS_ENABLED(CONFIG_MIPI_DBI_STM32_FMC_MEM_BARRIER)) {
+ barrier_dsync_fence_full();
+ }
+ }
+
+ return 0;
+}
+
+static int mipi_dbi_stm32_fmc_reset(const struct device *dev, uint32_t delay)
+{
+ const struct mipi_dbi_stm32_fmc_config *config = dev->config;
+ int ret;
+
+ if (config->reset.port == NULL) {
+ return -ENOTSUP;
+ }
+
+ ret = gpio_pin_set_dt(&config->reset, 1);
+ if (ret < 0) {
+ return ret;
+ }
+
+ k_msleep(delay);
+
+ return gpio_pin_set_dt(&config->reset, 0);
+}
+
+static int mipi_dbi_stm32_fmc_init(const struct device *dev)
+{
+ const struct mipi_dbi_stm32_fmc_config *config = dev->config;
+
+ if (config->reset.port) {
+ if (!gpio_is_ready_dt(&config->reset)) {
+ LOG_ERR("Reset GPIO device not ready");
+ return -ENODEV;
+ }
+
+ if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE)) {
+ LOG_ERR("Couldn't configure reset pin");
+ return -EIO;
+ }
+ }
+
+ if (config->power.port) {
+ if (!gpio_is_ready_dt(&config->power)) {
+ LOG_ERR("Power GPIO device not ready");
+ return -ENODEV;
+ }
+
+ if (gpio_pin_configure_dt(&config->power, GPIO_OUTPUT)) {
+ LOG_ERR("Couldn't configure power pin");
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+static struct mipi_dbi_driver_api mipi_dbi_stm32_fmc_driver_api = {
+ .reset = mipi_dbi_stm32_fmc_reset,
+ .command_write = mipi_dbi_stm32_fmc_command_write,
+ .write_display = mipi_dbi_stm32_fmc_write_display,
+};
+
+#define MIPI_DBI_FMC_GET_ADDRESS(n) _CONCAT(FMC_BANK1_, UTIL_INC(DT_REG_ADDR(DT_INST_PARENT(n))))
+
+#define MIPI_DBI_FMC_GET_DATA_ADDRESS(n) \
+ MIPI_DBI_FMC_GET_ADDRESS(n) + (1 << (DT_INST_PROP(n, register_select_pin) + 1))
+
+#define MIPI_DBI_STM32_FMC_INIT(n) \
+ static const struct mipi_dbi_stm32_fmc_config mipi_dbi_stm32_fmc_config_##n = { \
+ .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \
+ .power = GPIO_DT_SPEC_INST_GET_OR(n, power_gpios, {}), \
+ .register_addr = MIPI_DBI_FMC_GET_ADDRESS(n), \
+ .data_addr = MIPI_DBI_FMC_GET_DATA_ADDRESS(n), \
+ .fmc_address_setup_time = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_timing, 0), \
+ .fmc_data_setup_time = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_timing, 2), \
+ .fmc_memory_width = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_control, 2), \
+ }; \
+ \
+ static struct mipi_dbi_stm32_fmc_data mipi_dbi_stm32_fmc_data_##n; \
+ \
+ DEVICE_DT_INST_DEFINE(n, mipi_dbi_stm32_fmc_init, NULL, &mipi_dbi_stm32_fmc_data_##n, \
+ &mipi_dbi_stm32_fmc_config_##n, POST_KERNEL, \
+ CONFIG_MIPI_DBI_INIT_PRIORITY, &mipi_dbi_stm32_fmc_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_STM32_FMC_INIT)
diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c
index 429983d..564afaa 100644
--- a/drivers/modem/modem_cellular.c
+++ b/drivers/modem/modem_cellular.c
@@ -1924,7 +1924,7 @@
MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match),
MODEM_CHAT_SCRIPT_CMD_RESP("AT+CIMI", cimi_match),
MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match),
- MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT+CMUX=0,0,5,127", 0));
+ MODEM_CHAT_SCRIPT_CMD_RESP("AT+CMUX=0,0,5,127", ok_match));
MODEM_CHAT_SCRIPT_DEFINE(swir_hl7800_init_chat_script, swir_hl7800_init_chat_script_cmds,
abort_matches, modem_cellular_chat_callback_handler, 10);
@@ -2109,44 +2109,54 @@
#define MODEM_CELLULAR_GET_USER_PIPES(inst) \
MODEM_CELLULAR_INST_NAME(user_pipes, inst)
-#define MODEM_CELLULAR_DEVICE_QUECTEL_BG95(inst) \
- MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
- \
- static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \
- .chat_delimiter = "\r", \
- .chat_filter = "\n", \
- .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
- }; \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_1, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
+/* Extract the first argument (pipe name) from a pair */
+#define MODEM_CELLULAR_GET_PIPE_NAME_ARG(arg1, ...) arg1
+
+/* Extract the second argument (DLCI address) from a pair */
+#define MODEM_CELLULAR_GET_DLCI_ADDRESS_ARG(arg1, arg2, ...) arg2
+
+/* Define user pipe data using instance and extracted pipe name */
+#define MODEM_CELLULAR_DEFINE_USER_PIPE_DATA_HELPER(_args, inst) \
+ MODEM_CELLULAR_DEFINE_USER_PIPE_DATA(inst, \
+ MODEM_CELLULAR_GET_PIPE_NAME_ARG _args, \
+ CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES)
+
+/* Initialize user pipe using instance, extracted pipe name, and DLCI address */
+#define MODEM_CELLULAR_INIT_USER_PIPE_HELPER(_args, inst) \
+ MODEM_CELLULAR_INIT_USER_PIPE(inst, \
+ MODEM_CELLULAR_GET_PIPE_NAME_ARG _args, \
+ MODEM_CELLULAR_GET_DLCI_ADDRESS_ARG _args)
+
+/*
+ * Define and initialize user pipes dynamically
+ * Takes an instance and pairs of (pipe name, DLCI address)
+ */
+#define MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, ...) \
+ FOR_EACH_FIXED_ARG(MODEM_CELLULAR_DEFINE_USER_PIPE_DATA_HELPER, \
+ (;), inst, __VA_ARGS__); \
MODEM_CELLULAR_DEFINE_USER_PIPES( \
inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_1, 4), \
- ); \
- \
+ FOR_EACH_FIXED_ARG(MODEM_CELLULAR_INIT_USER_PIPE_HELPER, \
+ (,), inst, __VA_ARGS__) \
+ );
+
+/* Helper to define modem instance */
+#define MODEM_CELLULAR_DEFINE_INSTANCE(inst, power_ms, reset_ms, startup_ms, shutdown_ms, start, \
+ init_script, \
+ dial_script, \
+ periodic_script) \
static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
.uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 10000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &quectel_bg95_init_chat_script, \
- .dial_chat_script = &quectel_bg95_dial_chat_script, \
- .periodic_chat_script = &_CONCAT(DT_DRV_COMPAT, _periodic_chat_script), \
+ .power_pulse_duration_ms = (power_ms), \
+ .reset_pulse_duration_ms = (reset_ms), \
+ .startup_time_ms = (startup_ms), \
+ .shutdown_time_ms = (shutdown_ms), \
+ .autostarts = (start), \
+ .init_chat_script = (init_script), \
+ .dial_chat_script = (dial_script), \
+ .periodic_chat_script = (periodic_script), \
.user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
.user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
}; \
@@ -2158,6 +2168,24 @@
&MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
&modem_cellular_api);
+#define MODEM_CELLULAR_DEVICE_QUECTEL_BG95(inst) \
+ MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
+ \
+ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \
+ .chat_delimiter = "\r", \
+ .chat_filter = "\n", \
+ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
+ }; \
+ \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3), \
+ (user_pipe_1, 4)) \
+ \
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 10000, 5000, false, \
+ &quectel_bg95_init_chat_script, \
+ &quectel_bg95_dial_chat_script, \
+ &quectel_bg95_periodic_chat_script)
+
#define MODEM_CELLULAR_DEVICE_QUECTEL_EG25_G(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
\
@@ -2167,45 +2195,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3), \
+ (user_pipe_1, 4)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_1, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_1, 4), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 500, \
- .startup_time_ms = 15000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &quectel_eg25_g_init_chat_script, \
- .dial_chat_script = &quectel_eg25_g_dial_chat_script, \
- .periodic_chat_script = &_CONCAT(DT_DRV_COMPAT, _periodic_chat_script), \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 500, 15000, 5000, false, \
+ &quectel_eg25_g_init_chat_script, \
+ &quectel_eg25_g_dial_chat_script, \
+ &quectel_eg25_g_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_SIMCOM_SIM7080(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2216,45 +2213,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3), \
+ (user_pipe_1, 4)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_1, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_1, 4), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 10000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &simcom_sim7080_init_chat_script, \
- .dial_chat_script = &simcom_sim7080_dial_chat_script, \
- .periodic_chat_script = &simcom_sim7080_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 10000, 5000, false, \
+ &simcom_sim7080_init_chat_script, \
+ &simcom_sim7080_dial_chat_script, \
+ &simcom_sim7080_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_U_BLOX_SARA_R4(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2265,45 +2231,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- gnss_pipe, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (gnss_pipe, 3), \
+ (user_pipe_0, 4)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, gnss_pipe, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 4), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 10000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &u_blox_sara_r4_init_chat_script, \
- .dial_chat_script = &u_blox_sara_r4_dial_chat_script, \
- .periodic_chat_script = &u_blox_sara_r4_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 10000, 5000, false, \
+ &u_blox_sara_r4_init_chat_script, \
+ &u_blox_sara_r4_dial_chat_script, \
+ &u_blox_sara_r4_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_U_BLOX_SARA_R5(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2314,46 +2249,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- gnss_pipe, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (gnss_pipe, 4), \
+ (user_pipe_0, 3)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, gnss_pipe, 4), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .autostarts = true, \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 1500, \
- .shutdown_time_ms = 13000, \
- .init_chat_script = &u_blox_sara_r5_init_chat_script, \
- .dial_chat_script = &u_blox_sara_r5_dial_chat_script, \
- .periodic_chat_script = &u_blox_sara_r5_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 1500, 13000, true, \
+ &u_blox_sara_r5_init_chat_script, \
+ &u_blox_sara_r5_dial_chat_script, \
+ &u_blox_sara_r5_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_SWIR_HL7800(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2364,45 +2267,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3), \
+ (user_pipe_1, 4)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_1, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_1, 4), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 10000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &swir_hl7800_init_chat_script, \
- .dial_chat_script = &swir_hl7800_dial_chat_script, \
- .periodic_chat_script = &swir_hl7800_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 10000, 5000, false, \
+ &swir_hl7800_init_chat_script, \
+ &swir_hl7800_dial_chat_script, \
+ &swir_hl7800_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_TELIT_ME910G1(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2413,38 +2285,13 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 5050, \
- .reset_pulse_duration_ms = 250, \
- .startup_time_ms = 15000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &telit_me910g1_init_chat_script, \
- .dial_chat_script = &telit_me910g1_dial_chat_script, \
- .periodic_chat_script = &telit_me910g1_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 5050, 250, 15000, 5000, false, \
+ &telit_me910g1_init_chat_script, \
+ &telit_me910g1_dial_chat_script, \
+ &telit_me910g1_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_NORDIC_NRF91_SLM(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 1500); \
@@ -2454,38 +2301,13 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- gnss_pipe, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (gnss_pipe, 3)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, gnss_pipe, 3), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .power_pulse_duration_ms = 100, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 2000, \
- .shutdown_time_ms = 10000, \
- .init_chat_script = &nordic_nrf91_slm_init_chat_script, \
- .dial_chat_script = &nordic_nrf91_slm_dial_chat_script, \
- .periodic_chat_script = &nordic_nrf91_slm_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 100, 100, 2000, 10000, false, \
+ &nordic_nrf91_slm_init_chat_script, \
+ &nordic_nrf91_slm_dial_chat_script, \
+ &nordic_nrf91_slm_periodic_chat_script)
#define MODEM_CELLULAR_DEVICE_SQN_GM02S(inst) \
MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \
@@ -2496,46 +2318,14 @@
.ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \
}; \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_0, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
+ MODEM_CELLULAR_DEFINE_AND_INIT_USER_PIPES(inst, \
+ (user_pipe_0, 3), \
+ (user_pipe_1, 4)) \
\
- MODEM_CELLULAR_DEFINE_USER_PIPE_DATA( \
- inst, \
- user_pipe_1, \
- CONFIG_MODEM_CELLULAR_USER_PIPE_BUFFER_SIZES \
- ); \
- \
- MODEM_CELLULAR_DEFINE_USER_PIPES( \
- inst, \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_0, 3), \
- MODEM_CELLULAR_INIT_USER_PIPE(inst, user_pipe_1, 4), \
- ); \
- \
- static const struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \
- .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
- .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \
- .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \
- .autostarts = true, \
- .power_pulse_duration_ms = 1500, \
- .reset_pulse_duration_ms = 100, \
- .startup_time_ms = 2000, \
- .shutdown_time_ms = 5000, \
- .init_chat_script = &sqn_gm02s_init_chat_script, \
- .dial_chat_script = &sqn_gm02s_dial_chat_script, \
- .periodic_chat_script = &sqn_gm02s_periodic_chat_script, \
- .user_pipes = MODEM_CELLULAR_GET_USER_PIPES(inst), \
- .user_pipes_size = ARRAY_SIZE(MODEM_CELLULAR_GET_USER_PIPES(inst)), \
- }; \
- \
- PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \
- \
- DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \
- &MODEM_CELLULAR_INST_NAME(data, inst), \
- &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \
- &modem_cellular_api);
+ MODEM_CELLULAR_DEFINE_INSTANCE(inst, 1500, 100, 2000, 5000, true, \
+ &sqn_gm02s_init_chat_script, \
+ &sqn_gm02s_dial_chat_script, \
+ &sqn_gm02s_periodic_chat_script)
#define DT_DRV_COMPAT quectel_bg95
DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_QUECTEL_BG95)
diff --git a/drivers/pinctrl/pinctrl_esp32.c b/drivers/pinctrl/pinctrl_esp32.c
index 581cc2b..89c1ba4 100644
--- a/drivers/pinctrl/pinctrl_esp32.c
+++ b/drivers/pinctrl/pinctrl_esp32.c
@@ -12,7 +12,12 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pinctrl/pinctrl_esp32_common.h>
-#ifdef CONFIG_SOC_SERIES_ESP32C3
+#ifdef CONFIG_SOC_SERIES_ESP32C2
+#define out out.val
+#define in in.val
+#define out_w1ts out_w1ts.val
+#define out_w1tc out_w1tc.val
+#elif CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data
#define in in.data
diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c
index 6bc9df4..8d60cea 100644
--- a/drivers/pinctrl/pinctrl_imx.c
+++ b/drivers/pinctrl/pinctrl_imx.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 NXP
+ * Copyright 2022, 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -33,7 +33,7 @@
}
#endif
-#ifdef CONFIG_SOC_MIMX9352_A55
+#ifdef CONFIG_SOC_MIMX9352
sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
(mem_addr_t)mux_register);
@@ -92,7 +92,10 @@
#elif defined(CONFIG_SOC_MIMX8MQ6)
CLOCK_EnableClock(kCLOCK_Iomux);
#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */
-
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+ CLOCK_EnableClock(kCLOCK_Iomuxc1);
+ CLOCK_EnableClock(kCLOCK_Iomuxc2);
+#endif /* CONFIG_SOC_SERIES_IMXRT118X */
return 0;
}
diff --git a/drivers/pinctrl/pinctrl_ite_it8xxx2.c b/drivers/pinctrl/pinctrl_ite_it8xxx2.c
index f7d71ad..91ca93e 100644
--- a/drivers/pinctrl/pinctrl_ite_it8xxx2.c
+++ b/drivers/pinctrl/pinctrl_ite_it8xxx2.c
@@ -6,6 +6,7 @@
#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
+#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
@@ -365,6 +366,20 @@
gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
+#if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS(DT_NODELABEL(i2c5), okay)
+ const struct gpio_dt_spec scl_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), scl_gpios);
+ const struct gpio_dt_spec sda_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), sda_gpios);
+
+ /*
+ * When setting these pins as I2C alternate mode and then setting
+ * GCR7 or func3-ext of GPIO extended, it will cause leakage.
+ * In order to prevent leakage, it must be set to GPIO INPUT mode.
+ */
+ /* Set I2C5 SCL as GPIO input to prevent leakage */
+ gpio_pin_configure_dt(&scl_gpios, GPIO_INPUT);
+ /* Set I2C5 SDA as GPIO input to prevent leakage */
+ gpio_pin_configure_dt(&sda_gpios, GPIO_INPUT);
+#endif
/*
* Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
* and I2C3 SMCLK3/SMDAT3 pins from GPB2/GPB5 to GPH1/GPH2,
diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt
index 38347a8..f535234 100644
--- a/drivers/pinctrl/renesas/CMakeLists.txt
+++ b/drivers/pinctrl/renesas/CMakeLists.txt
@@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c)
-zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA8 ra/pinctrl_renesas_ra8.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
diff --git a/drivers/pinctrl/renesas/ra/Kconfig b/drivers/pinctrl/renesas/ra/Kconfig
index 2ffaa63..3ca0305 100644
--- a/drivers/pinctrl/renesas/ra/Kconfig
+++ b/drivers/pinctrl/renesas/ra/Kconfig
@@ -9,9 +9,9 @@
help
Enable Renesas RA series pin controller driver.
-config PINCTRL_RENESAS_RA8
- bool "Renesas RA8 pinctrl driver"
+config PINCTRL_RENESAS_RA_PFS
+ bool "Renesas RA pinctrl driver"
default y
- depends on DT_HAS_RENESAS_RA8_PINCTRL_ENABLED
+ depends on DT_HAS_RENESAS_RA_PINCTRL_PFS_ENABLED
help
- Enable the Renesas RA8 pinctrl driver.
+ Enable the Renesas RA series pinctrl driver with PFS secure register.
diff --git a/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c
similarity index 100%
rename from drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c
rename to drivers/pinctrl/renesas/ra/pinctrl_ra.c
diff --git a/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c b/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c
index b72d0ee..44b480a 100644
--- a/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c
+++ b/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c
@@ -595,8 +595,9 @@
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
{
- if (RCAR_IS_GP_PIN(pin) == false)
+ if (RCAR_IS_GP_PIN(pin) == false) {
return -EINVAL;
+ }
*reg_index = pin / 32;
diff --git a/drivers/ps2/ps2_npcx_controller.c b/drivers/ps2/ps2_npcx_controller.c
index ad37d5e..991beb5 100644
--- a/drivers/ps2/ps2_npcx_controller.c
+++ b/drivers/ps2/ps2_npcx_controller.c
@@ -227,10 +227,12 @@
status = inst->PSTAT & (BIT(NPCX_PSTAT_PERR) | BIT(NPCX_PSTAT_RFERR));
if (status) {
- if (status & BIT(NPCX_PSTAT_PERR))
+ if (status & BIT(NPCX_PSTAT_PERR)) {
LOG_ERR("RX parity error");
- if (status & BIT(NPCX_PSTAT_RFERR))
+ }
+ if (status & BIT(NPCX_PSTAT_RFERR)) {
LOG_ERR("RX Frame error");
+ }
return -EIO;
}
diff --git a/drivers/pwm/pwm_mc_esp32.c b/drivers/pwm/pwm_mc_esp32.c
index 1297bb6..f45b282 100644
--- a/drivers/pwm/pwm_mc_esp32.c
+++ b/drivers/pwm/pwm_mc_esp32.c
@@ -87,7 +87,7 @@
uint8_t prescale_timer2;
struct mcpwm_esp32_channel_config channel_config[MCPWM_CHANNEL_NUM];
#ifdef CONFIG_PWM_CAPTURE
- void (*irq_config_func)(const struct device *dev);
+ int (*irq_config_func)(const struct device *dev);
#endif /* CONFIG_PWM_CAPTURE */
};
@@ -435,9 +435,13 @@
mcpwm_ll_group_flush_shadow(data->hal.dev);
#ifdef CONFIG_PWM_CAPTURE
- config->irq_config_func(dev);
+ ret = config->irq_config_func(dev);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ }
#endif /* CONFIG_PWM_CAPTURE */
- return 0;
+ return ret;
}
#ifdef CONFIG_PWM_CAPTURE
@@ -531,10 +535,15 @@
#ifdef CONFIG_PWM_CAPTURE
#define IRQ_CONFIG_FUNC(idx) \
- static void mcpwm_esp32_irq_config_func_##idx(const struct device *dev) \
+ static int mcpwm_esp32_irq_config_func_##idx(const struct device *dev) \
{ \
- esp_intr_alloc(DT_INST_IRQN(idx), 0, (intr_handler_t)mcpwm_esp32_isr, (void *)dev, \
- NULL); \
+ int ret; \
+ ret = esp_intr_alloc(DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ ESP_PRIO_TO_FLAGS(DT_INST_IRQ_BY_IDX(idx, 0, priority)) | \
+ ESP_INT_FLAGS_CHECK(DT_INST_IRQ_BY_IDX(idx, 0, flags)) | \
+ ESP_INTR_FLAG_IRAM, \
+ (intr_handler_t)mcpwm_esp32_isr, (void *)dev, NULL); \
+ return ret; \
}
#define CAPTURE_INIT(idx) .irq_config_func = mcpwm_esp32_irq_config_func_##idx
#else
diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c
index 70006e3..82224d1 100644
--- a/drivers/pwm/pwm_stm32.c
+++ b/drivers/pwm/pwm_stm32.c
@@ -330,6 +330,7 @@
*/
if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) &&
(period_cycles > UINT16_MAX + 1)) {
+ LOG_ERR("Cannot set PWM output, value exceeds 16-bit timer limit.");
return -ENOTSUP;
}
diff --git a/drivers/regulator/regulator_nxp_vref.c b/drivers/regulator/regulator_nxp_vref.c
index d3aa0f4..1e2f51e 100644
--- a/drivers/regulator/regulator_nxp_vref.c
+++ b/drivers/regulator/regulator_nxp_vref.c
@@ -43,8 +43,9 @@
*csr |= VREF_CSR_HCBGEN_MASK;
/* Monitor until stable */
- while (!(*csr & VREF_CSR_VREFST_MASK))
+ while (!(*csr & VREF_CSR_VREFST_MASK)) {
;
+ }
/* Enable output buffer */
*csr |= VREF_CSR_BUF21EN_MASK;
diff --git a/drivers/retained_mem/CMakeLists.txt b/drivers/retained_mem/CMakeLists.txt
index 4f9322c..2724c12 100644
--- a/drivers/retained_mem/CMakeLists.txt
+++ b/drivers/retained_mem/CMakeLists.txt
@@ -5,5 +5,6 @@
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_USERSPACE retained_mem_handlers.c)
zephyr_library_sources_ifdef(CONFIG_RETAINED_MEM_NRF_GPREGRET retained_mem_nrf_gpregret.c)
+zephyr_library_sources_ifdef(CONFIG_RETAINED_MEM_NRF_RAM_CTRL retained_mem_nrf_ram_ctrl.c)
zephyr_library_sources_ifdef(CONFIG_RETAINED_MEM_ZEPHYR_RAM retained_mem_zephyr_ram.c)
zephyr_library_sources_ifdef(CONFIG_RETAINED_MEM_ZEPHYR_REG retained_mem_zephyr_reg.c)
diff --git a/drivers/retained_mem/Kconfig.nrf b/drivers/retained_mem/Kconfig.nrf
index 5f94b75..3590249 100644
--- a/drivers/retained_mem/Kconfig.nrf
+++ b/drivers/retained_mem/Kconfig.nrf
@@ -8,3 +8,11 @@
help
Enable driver for Nordic nRF GPREGRET-based retained memory
register support.
+
+config RETAINED_MEM_NRF_RAM_CTRL
+ bool "nRF RAM retention driver"
+ default y
+ depends on DT_HAS_ZEPHYR_RETAINED_RAM_ENABLED && RETAINED_MEM_ZEPHYR_RAM && POWEROFF
+ depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF53X || SOC_SERIES_NRF54LX || SOC_SERIES_NRF91X
+ help
+ Enable driver for Nordic RAM retention.
diff --git a/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c b/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c
new file mode 100644
index 0000000..8be3d5c
--- /dev/null
+++ b/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+
+#include <helpers/nrfx_ram_ctrl.h>
+
+#define _BUILD_MEM_REGION(node_id) \
+ {.dt_addr = DT_REG_ADDR(DT_PARENT(node_id)),\
+ .dt_size = DT_REG_SIZE(DT_PARENT(node_id))}
+
+struct ret_mem_region {
+ uintptr_t dt_addr;
+ size_t dt_size;
+};
+
+static const struct ret_mem_region ret_mem_regions[] = {
+ DT_FOREACH_STATUS_OKAY(zephyr_retained_ram, _BUILD_MEM_REGION)
+};
+
+static int retained_mem_nrf_init(void)
+{
+ const struct ret_mem_region *rmr;
+
+ for (size_t i = 0; i < ARRAY_SIZE(ret_mem_regions); i++) {
+ rmr = &ret_mem_regions[i];
+ nrfx_ram_ctrl_retention_enable_set((void *)rmr->dt_addr, rmr->dt_size, true);
+ }
+
+ return 0;
+}
+
+SYS_INIT(retained_mem_nrf_init, PRE_KERNEL_1, 0);
diff --git a/drivers/rtc/rtc_fake.c b/drivers/rtc/rtc_fake.c
index f02cf48..76de2d7 100644
--- a/drivers/rtc/rtc_fake.c
+++ b/drivers/rtc/rtc_fake.c
@@ -20,19 +20,19 @@
#ifdef CONFIG_RTC_ALARM
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_supported_fields, const struct device *, uint16_t,
- uint16_t);
+ uint16_t *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_time, const struct device *, uint16_t, uint16_t,
- constr struct rtc_time *);
-DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t,
+ const struct rtc_time *);
+DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t *,
struct rtc_time *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_is_pending, const struct device *, uint16_t);
-DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *uint16_t,
+DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *, uint16_t,
rtc_alarm_callback, void *);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
-DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *rtc_alarm_callback,
- void *);
+DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *,
+ rtc_update_callback, void *);
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
diff --git a/drivers/rtc/rtc_rv3028.c b/drivers/rtc/rtc_rv3028.c
index a3c23de..039c5f9 100644
--- a/drivers/rtc/rtc_rv3028.c
+++ b/drivers/rtc/rtc_rv3028.c
@@ -123,7 +123,8 @@
/* The RV3028 enumerates months 1 to 12 */
#define RV3028_MONTH_OFFSET 1
-#define RV3028_EEBUSY_POLL_US 10000
+#define RV3028_EEBUSY_READ_POLL_MS 1
+#define RV3028_EEBUSY_WRITE_POLL_MS 10
#define RV3028_EEBUSY_TIMEOUT_MS 100
/* RTC alarm time fields supported by the RV3028 */
@@ -240,7 +241,7 @@
return 0;
}
-static int rv3028_eeprom_wait_busy(const struct device *dev)
+static int rv3028_eeprom_wait_busy(const struct device *dev, int poll_ms)
{
uint8_t status = 0;
int err;
@@ -261,7 +262,7 @@
return -ETIME;
}
- k_busy_wait(RV3028_EEBUSY_POLL_US);
+ k_msleep(poll_ms);
}
return 0;
@@ -291,7 +292,7 @@
ret = rv3028_update_reg8(dev, RV3028_REG_CONTROL1, RV3028_CONTROL1_EERD,
RV3028_CONTROL1_EERD);
- ret = rv3028_eeprom_wait_busy(dev);
+ ret = rv3028_eeprom_wait_busy(dev, RV3028_EEBUSY_WRITE_POLL_MS);
if (ret) {
rv3028_exit_eerd(dev);
return ret;
@@ -321,7 +322,7 @@
goto exit_eerd;
}
- err = rv3028_eeprom_wait_busy(dev);
+ err = rv3028_eeprom_wait_busy(dev, RV3028_EEBUSY_WRITE_POLL_MS);
exit_eerd:
rv3028_exit_eerd(dev);
@@ -338,7 +339,7 @@
goto exit_eerd;
}
- err = rv3028_eeprom_wait_busy(dev);
+ err = rv3028_eeprom_wait_busy(dev, RV3028_EEBUSY_READ_POLL_MS);
exit_eerd:
rv3028_exit_eerd(dev);
@@ -377,40 +378,6 @@
#if RV3028_INT_GPIOS_IN_USE
-static int rv3028_int_enable_unlocked(const struct device *dev, bool enable)
-{
- const struct rv3028_config *config = dev->config;
- uint8_t clkout = 0;
- int err;
-
- if (enable || config->cof == RV3028_CLKOUT_FD_LOW) {
- /* Disable CLKOUT */
- clkout |= FIELD_PREP(RV3028_CLKOUT_FD, RV3028_CLKOUT_FD_LOW);
- } else {
- /* Configure CLKOUT frequency */
- clkout |= RV3028_CLKOUT_CLKOE |
- FIELD_PREP(RV3028_CLKOUT_FD, config->cof);
- }
-
- /* Configure the CLKOUT register */
- err = rv3028_update_cfg(dev,
- RV3028_REG_CLKOUT,
- RV3028_CLKOUT_FD | RV3028_CLKOUT_CLKOE,
- clkout);
- if (err) {
- return err;
- }
-
- err = gpio_pin_interrupt_configure_dt(&config->gpio_int,
- enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE);
- if (err) {
- LOG_ERR("failed to %s GPIO interrupt (err %d)", enable ? "enable" : "disable", err);
- return err;
- }
-
- return 0;
-}
-
static void rv3028_work_cb(struct k_work *work)
{
struct rv3028_data *data = CONTAINER_OF(work, struct rv3028_data, work);
@@ -511,7 +478,7 @@
date[0] = bin2bcd(timeptr->tm_sec) & RV3028_SECONDS_MASK;
date[1] = bin2bcd(timeptr->tm_min) & RV3028_MINUTES_MASK;
date[2] = bin2bcd(timeptr->tm_hour) & RV3028_HOURS_24H_MASK;
- date[3] = bin2bcd(timeptr->tm_wday) & RV3028_WEEKDAY_MASK;
+ date[3] = timeptr->tm_wday & RV3028_WEEKDAY_MASK;
date[4] = bin2bcd(timeptr->tm_mday) & RV3028_DATE_MASK;
date[5] = bin2bcd(timeptr->tm_mon + RV3028_MONTH_OFFSET) & RV3028_MONTH_MASK;
date[6] = bin2bcd(timeptr->tm_year - RV3028_YEAR_OFFSET) & RV3028_YEAR_MASK;
@@ -559,7 +526,7 @@
timeptr->tm_sec = bcd2bin(date[0] & RV3028_SECONDS_MASK);
timeptr->tm_min = bcd2bin(date[1] & RV3028_MINUTES_MASK);
timeptr->tm_hour = bcd2bin(date[2] & RV3028_HOURS_24H_MASK);
- timeptr->tm_wday = bcd2bin(date[3] & RV3028_WEEKDAY_MASK);
+ timeptr->tm_wday = date[3] & RV3028_WEEKDAY_MASK;
timeptr->tm_mday = bcd2bin(date[4] & RV3028_DATE_MASK);
timeptr->tm_mon = bcd2bin(date[5] & RV3028_MONTH_MASK) - RV3028_MONTH_OFFSET;
timeptr->tm_year = bcd2bin(date[6] & RV3028_YEAR_MASK) + RV3028_YEAR_OFFSET;
@@ -613,7 +580,7 @@
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
regs[0] = bin2bcd(timeptr->tm_min) & RV3028_ALARM_MINUTES_MASK;
} else {
- regs[0] = RTC_ALARM_TIME_MASK_MINUTE;
+ regs[0] = RV3028_ALARM_MINUTES_AE_M;
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
@@ -725,8 +692,7 @@
#else
const struct rv3028_config *config = dev->config;
struct rv3028_data *data = dev->data;
- uint8_t control_2;
- int err = 0;
+ int err;
if (config->gpio_int.port == NULL) {
return -ENOTSUP;
@@ -742,26 +708,8 @@
data->alarm_callback = callback;
data->alarm_user_data = user_data;
- err = rv3028_read_reg8(dev, RV3028_REG_CONTROL2, &control_2);
- if (err) {
- goto unlock;
- }
-
- if (callback != NULL) {
- control_2 |= RV3028_CONTROL2_AIE;
- } else {
- control_2 &= ~(RV3028_CONTROL2_AIE);
- }
-
- if ((control_2 & RV3028_CONTROL2_UIE) == 0U) {
- /* Only change INT GPIO if periodic time update interrupt not enabled */
- err = rv3028_int_enable_unlocked(dev, callback != NULL);
- if (err) {
- goto unlock;
- }
- }
-
- err = rv3028_write_reg8(dev, RV3028_REG_CONTROL2, control_2);
+ err = rv3028_update_reg8(dev, RV3028_REG_CONTROL2, RV3028_CONTROL2_AIE,
+ callback != NULL ? RV3028_CONTROL2_AIE : 0);
if (err) {
goto unlock;
}
@@ -785,7 +733,6 @@
{
const struct rv3028_config *config = dev->config;
struct rv3028_data *data = dev->data;
- uint8_t control_2;
int err;
if (config->gpio_int.port == NULL) {
@@ -797,26 +744,8 @@
data->update_callback = callback;
data->update_user_data = user_data;
- err = rv3028_read_reg8(dev, RV3028_REG_CONTROL2, &control_2);
- if (err) {
- goto unlock;
- }
-
- if (callback != NULL) {
- control_2 |= RV3028_CONTROL2_UIE;
- } else {
- control_2 &= ~(RV3028_CONTROL2_UIE);
- }
-
- if ((control_2 & RV3028_CONTROL2_AIE) == 0U) {
- /* Only change INT GPIO if alarm interrupt not enabled */
- err = rv3028_int_enable_unlocked(dev, callback != NULL);
- if (err) {
- goto unlock;
- }
- }
-
- err = rv3028_write_reg8(dev, RV3028_REG_CONTROL2, control_2);
+ err = rv3028_update_reg8(dev, RV3028_REG_CONTROL2, RV3028_CONTROL2_UIE,
+ callback != NULL ? RV3028_CONTROL2_UIE : 0);
if (err) {
goto unlock;
}
@@ -867,6 +796,12 @@
return -ENODEV;
}
+ err = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+ if (err) {
+ LOG_ERR("failed to enable GPIO interrupt (err %d)", err);
+ return err;
+ }
+
gpio_init_callback(&data->int_callback, rv3028_int_handler,
BIT(config->gpio_int.pin));
diff --git a/drivers/rtc/rtc_rv8263.c b/drivers/rtc/rtc_rv8263.c
index bb3ae03..f3cf86c 100644
--- a/drivers/rtc/rtc_rv8263.c
+++ b/drivers/rtc/rtc_rv8263.c
@@ -65,21 +65,6 @@
#define YEAR_BITS GENMASK(7, 0)
#define VALIDATE_24HR BIT(6)
-#define MIN_SEC 0
-#define MAX_SEC 59
-#define MIN_MIN 0
-#define MAX_MIN 59
-#define MIN_HOUR 0
-#define MAX_HOUR 23
-#define MAX_WDAY 7
-#define MIN_WDAY 1
-#define MAX_MDAY 31
-#define MIN_MDAY 1
-#define MAX_MON 12
-#define MIN_MON 1
-#define MIN_YEAR_DIFF 0
-#define MAX_YEAR_DIFF 99
-
#define DT_DRV_COMPAT microcrystal_rv_8263_c8
LOG_MODULE_REGISTER(microcrystal_rv8263c8, CONFIG_RTC_LOG_LEVEL);
@@ -241,10 +226,10 @@
regs[3] = bin2bcd(timeptr->tm_hour) & HOURS_BITS;
regs[4] = bin2bcd(timeptr->tm_mday) & DATE_BITS;
regs[5] = bin2bcd(timeptr->tm_wday) & WEEKDAY_BITS;
- regs[6] = bin2bcd(timeptr->tm_mon) & MONTHS_BITS;
+ regs[6] = (bin2bcd(timeptr->tm_mon) & MONTHS_BITS) + 1;
regs[7] = bin2bcd(timeptr->tm_year - RV8263_YEAR_OFFSET) & YEAR_BITS;
- return i2c_write_dt(&config->i2c_bus, regs, 8);
+ return i2c_write_dt(&config->i2c_bus, regs, sizeof(regs));
}
static int rv8263c8_time_get(const struct device *dev, struct rtc_time *timeptr)
@@ -272,7 +257,7 @@
timeptr->tm_hour = bcd2bin(regs[2] & HOURS_BITS);
timeptr->tm_mday = bcd2bin(regs[3] & DATE_BITS);
timeptr->tm_wday = bcd2bin(regs[4] & WEEKDAY_BITS);
- timeptr->tm_mon = bcd2bin(regs[5] & MONTHS_BITS);
+ timeptr->tm_mon = bcd2bin(regs[5] & MONTHS_BITS) - 1;
timeptr->tm_year = bcd2bin(regs[6] & YEAR_BITS) + RV8263_YEAR_OFFSET;
/* Unused. */
@@ -413,7 +398,7 @@
const struct rtc_time *timeptr)
{
int err;
- uint8_t regs[5];
+ uint8_t regs[6];
const struct rv8263c8_config *config = dev->config;
ARG_UNUSED(id);
@@ -422,86 +407,69 @@
return -EINVAL;
}
- /* Disable the alarm when mask is zero. */
- if (mask == 0) {
- return i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
- RV8263C8_BM_ALARM_INT_ENABLE,
- RV8263C8_BM_ALARM_INT_DISABLE);
- }
-
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_ERR("Invalid mask!");
return -EINVAL;
}
- regs[0] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS;
- regs[1] = bin2bcd(timeptr->tm_min) & MINUTES_BITS;
- regs[2] = bin2bcd(timeptr->tm_hour) & HOURS_BITS;
- regs[3] = bin2bcd(timeptr->tm_mday) & DATE_BITS;
- regs[4] = bin2bcd(timeptr->tm_wday) & WEEKDAY_BITS;
-
- if (mask & RTC_ALARM_TIME_MASK_SECOND) {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_SECONDS_ALARM,
- RV8263C8_BM_ALARM_ENABLE | regs[0]);
+ if (mask == 0) {
+ err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
+ RV8263C8_BM_ALARM_INT_ENABLE | RV8263C8_BM_AF,
+ RV8263C8_BM_ALARM_INT_DISABLE);
} else {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_SECONDS_ALARM,
- RV8263C8_BM_ALARM_DISABLE);
+ /* Clear the AIE and AF bit to prevent false triggering of the alarm. */
+ err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
+ RV8263C8_BM_ALARM_INT_ENABLE | RV8263C8_BM_AF, 0);
}
if (err < 0) {
- LOG_ERR("Error while writing SECONDS alarm! Error: %i", err);
+ LOG_ERR("Error while enabling alarm! Error: %i", err);
return err;
}
+ regs[0] = RV8263C8_REGISTER_SECONDS_ALARM;
+
+ if (mask & RTC_ALARM_TIME_MASK_SECOND) {
+ regs[1] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS;
+ } else {
+ regs[1] = RV8263C8_BM_ALARM_DISABLE;
+ }
+
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_MINUTES_ALARM,
- RV8263C8_BM_ALARM_ENABLE | regs[1]);
+ regs[2] = bin2bcd(timeptr->tm_min) & MINUTES_BITS;
} else {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_MINUTES_ALARM,
- RV8263C8_BM_ALARM_DISABLE);
- }
-
- if (err < 0) {
- LOG_ERR("Error while writing MINUTE alarm! Error: %i", err);
- return err;
+ regs[2] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_HOURS_ALARM,
- RV8263C8_BM_ALARM_ENABLE | regs[2]);
+ regs[3] = bin2bcd(timeptr->tm_min) & HOURS_BITS;
} else {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_HOURS_ALARM,
- RV8263C8_BM_ALARM_DISABLE);
- }
-
- if (err < 0) {
- LOG_ERR("Error while writing HOUR alarm! Error: %i", err);
- return err;
+ regs[3] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_DATE_ALARM,
- RV8263C8_BM_ALARM_ENABLE | regs[3]);
+ regs[4] = bin2bcd(timeptr->tm_min) & DATE_BITS;
} else {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_DATE_ALARM,
- RV8263C8_BM_ALARM_DISABLE);
- }
-
- if (err < 0) {
- LOG_ERR("Error while writing MONTHDAY alarm! Error: %i", err);
- return err;
+ regs[4] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_WEEKDAY_ALARM,
- RV8263C8_BM_ALARM_ENABLE | regs[4]);
+ regs[5] = bin2bcd(timeptr->tm_min) & WEEKDAY_BITS;
} else {
- err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_WEEKDAY_ALARM,
- RV8263C8_BM_ALARM_DISABLE);
+ regs[5] = RV8263C8_BM_ALARM_DISABLE;
}
+ err = i2c_write_dt(&config->i2c_bus, regs, sizeof(regs));
if (err < 0) {
- LOG_ERR("Error while writing WEEKDAY alarm! Error: %i", err);
+ LOG_ERR("Error while setting alarm time! Error: %i", err);
+ return err;
+ }
+
+ if (mask != 0) {
+ /* Enable the alarm interrupt */
+ err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
+ RV8263C8_BM_ALARM_INT_ENABLE,
+ RV8263C8_BM_ALARM_INT_ENABLE);
}
return err;
@@ -529,27 +497,28 @@
return err;
}
- if (value[0] <= MAX_SEC) {
+ /* Check if the highest bit is not set. If so the alarm is enabled. */
+ if ((value[0] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_sec = bcd2bin(value[0]) & SECONDS_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_SECOND;
}
- if (value[1] <= MAX_MIN) {
+ if ((value[1] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_min = bcd2bin(value[1]) & MINUTES_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_MINUTE;
}
- if (value[2] <= MAX_HOUR) {
+ if ((value[2] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_hour = bcd2bin(value[2]) & HOURS_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_HOUR;
}
- if (value[3] <= MAX_MDAY) {
+ if ((value[3] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_mday = bcd2bin(value[3]) & DATE_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
- if (value[4] <= MAX_WDAY) {
+ if ((value[4] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_wday = bcd2bin(value[4]) & WEEKDAY_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_WEEKDAY;
}
@@ -560,7 +529,6 @@
static int rv8263c8_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
- int err;
const struct rv8263c8_config *config = dev->config;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
@@ -582,25 +550,7 @@
return -ENOTSUP;
#endif
- if ((callback == NULL) && (user_data == NULL)) {
- LOG_DBG("Disable alarm function");
-
- err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
- RV8263C8_BM_ALARM_INT_ENABLE,
- RV8263C8_BM_ALARM_INT_DISABLE);
- } else {
- LOG_DBG("Enable alarm function");
-
- err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
- RV8263C8_BM_ALARM_INT_ENABLE | RV8263C8_BM_AF,
- RV8263C8_BM_ALARM_INT_ENABLE);
- }
-
- if (err < 0) {
- LOG_ERR("Error while writing CONTROL2! Error: %i", err);
- }
-
- return err;
+ return 0;
}
static int rv8263c8_alarm_is_pending(const struct device *dev, uint16_t id)
diff --git a/drivers/sdhc/imx_usdhc.c b/drivers/sdhc/imx_usdhc.c
index 2909ea1..5a7f372 100644
--- a/drivers/sdhc/imx_usdhc.c
+++ b/drivers/sdhc/imx_usdhc.c
@@ -58,6 +58,7 @@
const struct gpio_dt_spec pwr_gpio;
const struct gpio_dt_spec detect_gpio;
bool detect_dat3;
+ bool detect_cd;
bool no_180_vol;
uint32_t data_timeout;
uint32_t read_watermark;
@@ -809,10 +810,18 @@
imx_usdhc_dat3_pull(cfg, true);
USDHC_CardDetectByData3(cfg->base, false);
}
+ } else if (cfg->detect_cd) {
+ /*
+ * Detect the card via the USDHC_CD signal internal to
+ * the peripheral
+ */
+ data->card_present = USDHC_DetectCardInsert(cfg->base);
} else if (cfg->detect_gpio.port) {
data->card_present = gpio_pin_get_dt(&cfg->detect_gpio) > 0;
} else {
- data->card_present = USDHC_DetectCardInsert(cfg->base);
+ LOG_WRN("No card detection method configured, assuming card "
+ "is present");
+ data->card_present = true;
}
return ((int)data->card_present);
}
@@ -1090,6 +1099,7 @@
.detect_gpio = GPIO_DT_SPEC_INST_GET_OR(n, cd_gpios, {0}), \
.data_timeout = DT_INST_PROP(n, data_timeout), \
.detect_dat3 = DT_INST_PROP(n, detect_dat3), \
+ .detect_cd = DT_INST_PROP(n, detect_cd), \
.no_180_vol = DT_INST_PROP(n, no_1_8_v), \
.read_watermark = DT_INST_PROP(n, read_watermark), \
.write_watermark = DT_INST_PROP(n, write_watermark), \
diff --git a/drivers/sdhc/sdhc_esp32.c b/drivers/sdhc/sdhc_esp32.c
index f77c585..686fd2f 100644
--- a/drivers/sdhc/sdhc_esp32.c
+++ b/drivers/sdhc/sdhc_esp32.c
@@ -12,8 +12,9 @@
#include <zephyr/logging/log.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-/* ESP32 includes */
#include <esp_clk_tree.h>
#include <hal/sdmmc_ll.h>
#include <esp_intr_alloc.h>
@@ -51,6 +52,8 @@
int slot;
const sdmmc_dev_t *sdio_hw;
+ const struct device *clock_dev;
+ const clock_control_subsys_t clock_subsys;
const struct pinctrl_dev_config *pcfg;
const struct gpio_dt_spec pwr_gpio;
/*
@@ -65,6 +68,8 @@
const int d3_pin;
int irq_source;
+ int irq_priority;
+ int irq_flags;
uint8_t bus_width_cfg;
struct sdhc_host_props props;
@@ -871,24 +876,13 @@
}
const uint16_t mask = BIT(slot);
- uint16_t temp;
if (width == 1) {
- temp = sdio_hw->ctype.card_width_8 & ~mask;
- HAL_FORCE_MODIFY_U32_REG_FIELD(sdio_hw->ctype, card_width_8, temp);
-
- temp = sdio_hw->ctype.card_width & ~mask;
- HAL_FORCE_MODIFY_U32_REG_FIELD(sdio_hw->ctype, card_width, temp);
-
+ sdio_hw->ctype.card_width_8 &= ~mask;
+ sdio_hw->ctype.card_width &= ~mask;
} else if (width == 4) {
- temp = sdio_hw->ctype.card_width_8 & ~mask;
- HAL_FORCE_MODIFY_U32_REG_FIELD(sdio_hw->ctype, card_width_8, temp);
-
- temp = sdio_hw->ctype.card_width | mask;
- HAL_FORCE_MODIFY_U32_REG_FIELD(sdio_hw->ctype, card_width, temp);
- } else if (width == 8) {
- temp = sdio_hw->ctype.card_width_8 | mask;
- HAL_FORCE_MODIFY_U32_REG_FIELD(sdio_hw->ctype, card_width_8, temp);
+ sdio_hw->ctype.card_width_8 &= ~mask;
+ sdio_hw->ctype.card_width |= mask;
} else {
return ESP_ERR_INVALID_ARG;
}
@@ -1195,7 +1189,7 @@
}
if ((ret_esp != 0) || esp_cmd.error) {
- LOG_DBG("\nError for command: %u arg %08x ret_esp = 0x%x error = 0x%x\n",
+ LOG_DBG("Error command: %u arg %08x ret_esp = 0x%x error = 0x%x\n",
cmd->opcode, cmd->arg, ret_esp, esp_cmd.error);
ret_esp = (ret_esp > 0) ? ret_esp : esp_cmd.error;
@@ -1320,9 +1314,16 @@
return -EINVAL;
}
- /* enable bus clock for registers */
- sdmmc_ll_enable_bus_clock(sdio_hw, true);
- sdmmc_ll_reset_register(sdio_hw);
+ if (!device_is_ready(cfg->clock_dev)) {
+ return -ENODEV;
+ }
+
+ ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys);
+
+ if (ret != 0) {
+ LOG_ERR("Error enabling SDHC clock");
+ return ret;
+ }
/* Enable clock to peripheral. Use smallest divider first */
ret = sdmmc_host_set_clk_div(sdio_hw, 2);
@@ -1340,8 +1341,11 @@
sdio_hw->ctrl.int_enable = 0;
/* Attach interrupt handler */
- ret = esp_intr_alloc(cfg->irq_source, 0, &sdio_esp32_isr, (void *)dev,
- &data->s_host_ctx.intr_handle);
+ ret = esp_intr_alloc(cfg->irq_source,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags) | ESP_INTR_FLAG_IRAM,
+ &sdio_esp32_isr, (void *)dev,
+ &data->s_host_ctx.intr_handle);
if (ret != 0) {
k_msgq_purge(data->s_host_ctx.event_queue);
@@ -1406,7 +1410,11 @@
\
static const struct sdhc_esp32_config sdhc_esp32_##n##_config = { \
.sdio_hw = (const sdmmc_dev_t *)DT_REG_ADDR(DT_INST_PARENT(n)), \
- .irq_source = DT_IRQN(DT_INST_PARENT(n)), \
+ .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
+ .clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), offset), \
+ .irq_source = DT_IRQ_BY_IDX(DT_INST_PARENT(n), 0, irq), \
+ .irq_priority = DT_IRQ_BY_IDX(DT_INST_PARENT(n), 0, priority), \
+ .irq_flags = DT_IRQ_BY_IDX(DT_INST_PARENT(n), 0, flags), \
.slot = DT_REG_ADDR(DT_DRV_INST(n)), \
.bus_width_cfg = DT_INST_PROP(n, bus_width), \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(n)), \
diff --git a/drivers/sdhc/sdhc_spi.c b/drivers/sdhc/sdhc_spi.c
index 14e817a..d567051 100644
--- a/drivers/sdhc/sdhc_spi.c
+++ b/drivers/sdhc/sdhc_spi.c
@@ -14,6 +14,7 @@
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/crc.h>
+#include <zephyr/pm/device_runtime.h>
LOG_MODULE_REGISTER(sdhc_spi, CONFIG_SDHC_LOG_LEVEL);
@@ -148,24 +149,30 @@
const struct sdhc_spi_config *config = dev->config;
struct sdhc_spi_data *data = dev->data;
struct spi_config *spi_cfg = data->spi_cfg;
- int ret;
+ int ret, ret2;
if (spi_cfg->frequency == 0) {
/* Use default 400KHZ frequency */
spi_cfg->frequency = SDMMC_CLOCK_400KHZ;
}
+
+ /* Request SPI bus to be active */
+ if (pm_device_runtime_get(config->spi_dev) < 0) {
+ return -EIO;
+ }
+
/* the initial 74 clocks must be sent while CS is high */
spi_cfg->operation |= SPI_CS_ACTIVE_HIGH;
ret = sdhc_spi_rx(config->spi_dev, spi_cfg, data->scratch, 10);
- if (ret != 0) {
- spi_release(config->spi_dev, spi_cfg);
- spi_cfg->operation &= ~SPI_CS_ACTIVE_HIGH;
- return ret;
- }
+
/* Release lock on SPI bus */
- ret = spi_release(config->spi_dev, spi_cfg);
+ ret2 = spi_release(config->spi_dev, spi_cfg);
spi_cfg->operation &= ~SPI_CS_ACTIVE_HIGH;
- return ret;
+
+ /* Release request for SPI bus to be active */
+ (void)pm_device_runtime_put(config->spi_dev);
+
+ return ret ? ret : ret2;
}
/* Checks if SPI SD card is sending busy signal */
@@ -184,9 +191,9 @@
if (response == 0xFF) {
return 0;
- } else
+ } else {
return 1;
-
+ }
}
/* Waits for SPI SD card to stop sending busy signal */
@@ -623,7 +630,7 @@
{
const struct sdhc_spi_config *config = dev->config;
struct sdhc_spi_data *dev_data = dev->data;
- int ret, stop_ret, retries = cmd->retries;
+ int ret, ret2, stop_ret, retries = cmd->retries;
const struct sdhc_command stop_cmd = {
.opcode = SD_STOP_TRANSMISSION,
.arg = 0,
@@ -631,6 +638,12 @@
.timeout_ms = 1000,
.retries = 1,
};
+
+ /* Request SPI bus to be active */
+ if (pm_device_runtime_get(config->spi_dev) < 0) {
+ return -EIO;
+ }
+
if (data == NULL) {
do {
ret = sdhc_spi_send_cmd(dev, cmd, false);
@@ -667,13 +680,14 @@
}
} while ((ret != 0) && (retries > 0));
}
- if (ret) {
- /* Release SPI bus */
- spi_release(config->spi_dev, dev_data->spi_cfg);
- return ret;
- }
+
/* Release SPI bus */
- return spi_release(config->spi_dev, dev_data->spi_cfg);
+ ret2 = spi_release(config->spi_dev, dev_data->spi_cfg);
+
+ /* Release request for SPI bus to be active */
+ (void)pm_device_runtime_put(config->spi_dev);
+
+ return ret ? ret : ret2;
}
static int sdhc_spi_set_io(const struct device *dev, struct sdhc_io *ios)
@@ -720,10 +734,12 @@
if (gpio_pin_set_dt(&cfg->pwr_gpio, 1)) {
return -EIO;
}
+ LOG_INF("Powered up");
} else {
if (gpio_pin_set_dt(&cfg->pwr_gpio, 0)) {
return -EIO;
}
+ LOG_INF("Powered down");
}
}
data->power_mode = ios->power_mode;
diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c
index 14015bb..6a538f6 100644
--- a/drivers/sensor/adi/adxl345/adxl345.c
+++ b/drivers/sensor/adi/adxl345/adxl345.c
@@ -165,7 +165,7 @@
data->bufz[s] = sample.z;
}
- return samples_count;
+ return 0;
}
static int adxl345_channel_get(const struct device *dev,
diff --git a/drivers/sensor/adi/adxl367/adxl367.c b/drivers/sensor/adi/adxl367/adxl367.c
index 1d5c31a..7810c9d 100644
--- a/drivers/sensor/adi/adxl367/adxl367.c
+++ b/drivers/sensor/adi/adxl367/adxl367.c
@@ -121,9 +121,10 @@
return ret;
}
- if (op_mode == ADXL367_MEASURE)
+ if (op_mode == ADXL367_MEASURE) {
/* Wait 100 ms to allow the acceleration outputs to settle */
k_sleep(K_MSEC(100));
+ }
return 0;
}
diff --git a/drivers/sensor/ams/tsl2540/tsl2540.c b/drivers/sensor/ams/tsl2540/tsl2540.c
index 98516d5..2a24c8b 100644
--- a/drivers/sensor/ams/tsl2540/tsl2540.c
+++ b/drivers/sensor/ams/tsl2540/tsl2540.c
@@ -212,10 +212,12 @@
}
#endif /* CONFIG_TSL2540_TRIGGER */
- switch ((enum sensor_attribute_tsl2540)attr) {
- case SENSOR_ATTR_GAIN:
+ if (attr == SENSOR_ATTR_GAIN) {
tsl2540_attr_set_gain(dev, (enum sensor_gain_tsl2540)val->val1);
- break;
+ goto exit;
+ }
+
+ switch ((enum sensor_attribute_tsl2540)attr) {
case SENSOR_ATTR_INT_APERS:
temp = (uint8_t)val->val1;
diff --git a/drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c b/drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c
index 487e135..20302ed 100644
--- a/drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c
+++ b/drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c
@@ -71,7 +71,9 @@
const struct pinctrl_dev_config *pincfg;
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
- const int irq_src;
+ const int irq_source;
+ const int irq_priority;
+ const int irq_flags;
struct pcnt_esp32_unit_config *unit_config;
const int unit_len;
};
@@ -340,7 +342,11 @@
data->trigger_handler = handler;
data->trigger = trig;
- ret = esp_intr_alloc(config->irq_src, 0, (intr_handler_t)pcnt_esp32_isr, (void *)dev, NULL);
+ ret = esp_intr_alloc(config->irq_source,
+ ESP_PRIO_TO_FLAGS(config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(config->irq_flags) | ESP_INTR_FLAG_IRAM,
+ (intr_handler_t)pcnt_esp32_isr, (void *)dev, NULL);
+
if (ret != 0) {
LOG_ERR("pcnt isr registration failed (%d)", ret);
return ret;
@@ -399,7 +405,9 @@
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
- .irq_src = DT_INST_IRQN(0),
+ .irq_source = DT_INST_IRQ_BY_IDX(0, 0, irq),
+ .irq_priority = DT_INST_IRQ_BY_IDX(0, 0, priority),
+ .irq_flags = DT_INST_IRQ_BY_IDX(0, 0, flags),
.unit_config = unit_config,
.unit_len = ARRAY_SIZE(unit_config),
};
diff --git a/drivers/sensor/nxp/CMakeLists.txt b/drivers/sensor/nxp/CMakeLists.txt
index 05270c5..73dc2cb 100644
--- a/drivers/sensor/nxp/CMakeLists.txt
+++ b/drivers/sensor/nxp/CMakeLists.txt
@@ -3,6 +3,7 @@
# zephyr-keep-sorted-start
add_subdirectory_ifdef(CONFIG_FXAS21002 fxas21002)
+add_subdirectory_ifdef(CONFIG_FXLS8974 fxls8974)
add_subdirectory_ifdef(CONFIG_FXOS8700 fxos8700)
add_subdirectory_ifdef(CONFIG_MCUX_ACMP mcux_acmp)
add_subdirectory_ifdef(CONFIG_MCUX_LPCMP mcux_lpcmp)
diff --git a/drivers/sensor/nxp/Kconfig b/drivers/sensor/nxp/Kconfig
index 3da1f9c..10e8139 100644
--- a/drivers/sensor/nxp/Kconfig
+++ b/drivers/sensor/nxp/Kconfig
@@ -3,6 +3,7 @@
# zephyr-keep-sorted-start
source "drivers/sensor/nxp/fxas21002/Kconfig"
+source "drivers/sensor/nxp/fxls8974/Kconfig"
source "drivers/sensor/nxp/fxos8700/Kconfig"
source "drivers/sensor/nxp/mcux_acmp/Kconfig"
source "drivers/sensor/nxp/mcux_lpcmp/Kconfig"
diff --git a/drivers/sensor/nxp/fxls8974/CMakeLists.txt b/drivers/sensor/nxp/fxls8974/CMakeLists.txt
new file mode 100644
index 0000000..9a295b6
--- /dev/null
+++ b/drivers/sensor/nxp/fxls8974/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Makefile - FXLS8974 3-axis accelerometer
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+zephyr_library()
+
+zephyr_library_sources(fxls8974.c)
+zephyr_library_sources_ifdef(CONFIG_FXLS8974_TRIGGER fxls8974_trigger.c)
diff --git a/drivers/sensor/nxp/fxls8974/Kconfig b/drivers/sensor/nxp/fxls8974/Kconfig
new file mode 100644
index 0000000..d50fe87
--- /dev/null
+++ b/drivers/sensor/nxp/fxls8974/Kconfig
@@ -0,0 +1,58 @@
+# FXLS8974 3-axis accelerometer
+
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig FXLS8974
+ bool "FXLS8974 accelerometer driver"
+ default y
+ depends on DT_HAS_NXP_FXLS8974_ENABLED
+ select I2C if $(dt_compat_on_bus,$(DT_COMPAT_NXP_FXLS8974),i2c)
+ select SPI if $(dt_compat_on_bus,$(DT_COMPAT_NXP_FXLS8974),spi)
+ help
+ Enable driver for the FXLS8974 accelerometer
+
+if FXLS8974
+
+choice
+ prompt "Trigger mode"
+ default FXLS8974_TRIGGER_NONE
+
+config FXLS8974_TRIGGER_NONE
+ bool "No trigger"
+
+config FXLS8974_TRIGGER_GLOBAL_THREAD
+ bool "Use global thread"
+ select FXLS8974_TRIGGER
+
+config FXLS8974_TRIGGER_OWN_THREAD
+ bool "Use own thread"
+ select FXLS8974_TRIGGER
+
+endchoice
+
+config FXLS8974_TRIGGER
+ bool
+
+config FXLS8974_DRDY_INT1
+ bool "Data ready interrupt to INT1 pin"
+ depends on FXLS8974_TRIGGER
+ help
+ Say Y to route data ready interrupt to INT1 pin. Say N to route to
+ INT2 pin.
+
+if FXLS8974_TRIGGER
+
+config FXLS8974_THREAD_PRIORITY
+ int "Own thread priority"
+ depends on FXLS8974_TRIGGER_OWN_THREAD
+ default 10
+
+config FXLS8974_THREAD_STACK_SIZE
+ int "Own thread stack size"
+ depends on FXLS8974_TRIGGER_OWN_THREAD
+ default 1024
+
+endif # FXLS8974_TRIGGER
+
+endif # FXLS8974
diff --git a/drivers/sensor/nxp/fxls8974/fxls8974.c b/drivers/sensor/nxp/fxls8974/fxls8974.c
new file mode 100644
index 0000000..049f289
--- /dev/null
+++ b/drivers/sensor/nxp/fxls8974/fxls8974.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright 2024 NXP
+ * Copyright (c) 2018 Phytec Messtechnik GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_fxls8974
+
+#include "fxls8974.h"
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/logging/log.h>
+#include <stdlib.h>
+
+LOG_MODULE_REGISTER(FXLS8974, CONFIG_SENSOR_LOG_LEVEL);
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+#define DIR_READ(a) ((a) & 0x7f)
+#define DIR_WRITE(a) ((a) | BIT(7))
+#define ADDR_7(a) ((a) & BIT(7))
+
+int fxls8974_transceive(const struct device *dev,
+ void *data, size_t length)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ const struct spi_buf buf = { .buf = data, .len = length };
+ const struct spi_buf_set s = { .bufs = &buf, .count = 1 };
+
+ return spi_transceive_dt(&cfg->bus_cfg.spi, &s, &s);
+}
+
+int fxls8974_read_spi(const struct device *dev,
+ uint8_t reg,
+ void *data,
+ size_t length)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ /* Reads must clock out a dummy byte after sending the address. */
+ uint8_t reg_buf[3] = { DIR_READ(reg), ADDR_7(reg), 0 };
+ const struct spi_buf buf[2] = {
+ { .buf = reg_buf, .len = 3 },
+ { .buf = data, .len = length }
+ };
+ const struct spi_buf_set tx = { .bufs = buf, .count = 1 };
+ const struct spi_buf_set rx = { .bufs = buf, .count = 2 };
+
+ return spi_transceive_dt(&cfg->bus_cfg.spi, &tx, &rx);
+}
+
+int fxls8974_byte_read_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t *byte)
+{
+ /* Reads must clock out a dummy byte after sending the address. */
+ uint8_t data[] = { DIR_READ(reg), ADDR_7(reg), 0};
+ int ret;
+
+ ret = fxls8974_transceive(dev, data, sizeof(data));
+
+ *byte = data[2];
+
+ return ret;
+}
+
+int fxls8974_byte_write_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t byte)
+{
+ uint8_t data[] = { DIR_WRITE(reg), ADDR_7(reg), byte };
+
+ return fxls8974_transceive(dev, data, sizeof(data));
+}
+
+int fxls8974_reg_field_update_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t mask,
+ uint8_t val)
+{
+ uint8_t old_val;
+
+ if (fxls8974_byte_read_spi(dev, reg, &old_val) < 0) {
+ return -EIO;
+ }
+
+ return fxls8974_byte_write_spi(dev, reg, (old_val & ~mask) | (val & mask));
+}
+
+static const struct fxls8974_io_ops fxls8974_spi_ops = {
+ .read = fxls8974_read_spi,
+ .byte_read = fxls8974_byte_read_spi,
+ .byte_write = fxls8974_byte_write_spi,
+ .reg_field_update = fxls8974_reg_field_update_spi,
+};
+#endif
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+int fxls8974_read_i2c(const struct device *dev,
+ uint8_t reg,
+ void *data,
+ size_t length)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ return i2c_burst_read_dt(&cfg->bus_cfg.i2c, reg, data, length);
+}
+
+int fxls8974_byte_read_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t *byte)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ return i2c_reg_read_byte_dt(&cfg->bus_cfg.i2c, reg, byte);
+}
+
+int fxls8974_byte_write_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t byte)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ return i2c_reg_write_byte_dt(&cfg->bus_cfg.i2c, reg, byte);
+}
+
+int fxls8974_reg_field_update_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t mask,
+ uint8_t val)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ return i2c_reg_update_byte_dt(&cfg->bus_cfg.i2c, reg, mask, val);
+}
+static const struct fxls8974_io_ops fxls8974_i2c_ops = {
+ .read = fxls8974_read_i2c,
+ .byte_read = fxls8974_byte_read_i2c,
+ .byte_write = fxls8974_byte_write_i2c,
+ .reg_field_update = fxls8974_reg_field_update_i2c,
+};
+#endif
+
+static int fxls8974_set_odr(const struct device *dev,
+ const struct sensor_value *val, enum fxls8974_wake mode)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ uint8_t odr;
+ /* val int32 */
+ switch (val->val1) {
+ case 3200:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_3200;
+ break;
+ case 800:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_800;
+ break;
+ case 400:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_400;
+ break;
+ case 200:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_200;
+ break;
+ case 100:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_100;
+ break;
+ case 50:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_50;
+ break;
+ case 25:
+ odr = FXLS8974_CTRLREG3_ODR_RATE_25;
+ break;
+ case 12:
+ if (val->val2 == 500000) {
+ odr = FXLS8974_CTRLREG3_ODR_RATE_12_5;
+ break;
+ }
+ return -EINVAL;
+ case 6:
+ if (val->val2 == 250000) {
+ odr = FXLS8974_CTRLREG3_ODR_RATE_6_25;
+ break;
+ }
+ return -EINVAL;
+ case 3:
+ if (val->val2 == 125000) {
+ odr = FXLS8974_CTRLREG3_ODR_RATE_3_125;
+ break;
+ }
+ return -EINVAL;
+ case 1:
+ if (val->val2 == 563000) {
+ odr = FXLS8974_CTRLREG3_ODR_RATE_1_563;
+ break;
+ }
+ return -EINVAL;
+ case 0:
+ if (val->val2 == 781000) {
+ odr = FXLS8974_CTRLREG3_ODR_RATE_0_781;
+ break;
+ }
+ return -EINVAL;
+ default:
+ return -EINVAL;
+ }
+
+ LOG_DBG("Set %s ODR to 0x%02x", (mode == FXLS8974_WAKE) ? "wake" : "sleep", odr);
+
+ /* Change the attribute and restore active mode. */
+ if (mode == FXLS8974_WAKE) {
+ return cfg->ops->reg_field_update(dev, FXLS8974_REG_CTRLREG3,
+ FXLS8974_CTRLREG3_WAKE_ODR_MASK,
+ odr<<4);
+ } else {
+ return cfg->ops->reg_field_update(dev, FXLS8974_REG_CTRLREG3,
+ FXLS8974_CTRLREG3_SLEEP_ODR_MASK,
+ odr);
+ }
+}
+
+static int fxls8974_attr_set(const struct device *dev,
+ enum sensor_channel chan,
+ enum sensor_attribute attr,
+ const struct sensor_value *val)
+{
+ if (chan != SENSOR_CHAN_ALL) {
+ return -ENOTSUP;
+ }
+
+ switch (attr) {
+ case SENSOR_ATTR_SAMPLING_FREQUENCY:
+ return fxls8974_set_odr(dev, val, FXLS8974_WAKE);
+ default:
+ return -ENOTSUP;
+ }
+ return 0;
+}
+
+static int fxls8974_sample_fetch(const struct device *dev, enum sensor_channel ch)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ struct fxls8974_data *data = dev->data;
+ uint8_t buf[FXLS8974_MAX_NUM_BYTES];
+ int16_t *raw;
+ int ret = 0;
+ int i;
+
+ k_sem_take(&data->sem, K_FOREVER);
+
+ /* Read all the accel channels in one I2C/SPI transaction. */
+ if (cfg->ops->read(dev, FXLS8974_REG_OUTXLSB, buf, FXLS8974_MAX_ACCEL_BYTES)) {
+ LOG_ERR("Could not fetch accelerometer data");
+ ret = -EIO;
+ goto exit;
+ }
+
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_OUTTEMP, buf+FXLS8974_DATA_TEMP_OFFSET)) {
+ LOG_ERR("Could not fetch temperature");
+ ret = -EIO;
+ goto exit;
+ }
+
+ /* Parse the buf into raw channel data (16-bit integers). To save
+ * RAM, store the data in raw format and wait to convert to the
+ * normalized sensor_value type until later.
+ */
+ __ASSERT(FXLS8974_MAX_NUM_CHANNELS <= ARRAY_SIZE(data->raw),
+ "Too many channels");
+
+ raw = &data->raw[FXLS8974_CHANNEL_ACCEL_X];
+
+ for (i = 0; i < FXLS8974_MAX_ACCEL_BYTES; i += 2) {
+ *raw++ = (buf[i+1] << 8) | (buf[i]);
+ }
+
+ *raw = *(buf+FXLS8974_MAX_ACCEL_BYTES);
+
+exit:
+ k_sem_give(&data->sem);
+
+ return ret;
+}
+
+static void fxls8974_accel_convert(struct sensor_value *val, int16_t raw,
+ uint8_t fsr)
+{
+ int64_t micro_ms2;
+
+ /* Convert units to micro m/s^2. */
+ micro_ms2 = (raw * SENSOR_G) >> fsr;
+
+ /* The maximum possible value is 16g, which in units of micro m/s^2
+ * always fits into 32-bits. Cast down to int32_t so we can use a
+ * faster divide.
+ */
+ val->val1 = (int32_t) micro_ms2 / 1000000;
+ val->val2 = (int32_t) micro_ms2 % 1000000;
+}
+
+static int fxls8974_get_accel_data(const struct device *dev,
+ struct sensor_value *val, enum sensor_channel ch)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ struct fxls8974_data *data = dev->data;
+ int16_t *raw;
+ uint8_t fsr;
+
+ k_sem_take(&data->sem, K_FOREVER);
+
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_CTRLREG1, &fsr)) {
+ LOG_ERR("Could not read scale settings");
+ return -EIO;
+ }
+
+ fsr = (fsr & FXLS8974_CTRLREG1_FSR_MASK) >> 1;
+ switch (fsr) {
+ case 0b00:
+ fsr = 10U;
+ break;
+ case 0b01:
+ fsr = 9U;
+ break;
+ case 0b10:
+ fsr = 8U;
+ break;
+ case 0b11:
+ fsr = 7U;
+ break;
+ }
+
+ if (ch == SENSOR_CHAN_ACCEL_XYZ) {
+ raw = &data->raw[FXLS8974_CHANNEL_ACCEL_X];
+ for (int i = 0; i < FXLS8974_MAX_ACCEL_CHANNELS; i++) {
+ fxls8974_accel_convert(val++, *raw++, fsr);
+ }
+ } else {
+ switch (ch) {
+ case SENSOR_CHAN_ACCEL_X:
+ raw = &data->raw[FXLS8974_CHANNEL_ACCEL_X];
+ break;
+ case SENSOR_CHAN_ACCEL_Y:
+ raw = &data->raw[FXLS8974_CHANNEL_ACCEL_Y];
+ break;
+ case SENSOR_CHAN_ACCEL_Z:
+ raw = &data->raw[FXLS8974_CHANNEL_ACCEL_Z];
+ break;
+ default:
+ return -ENOTSUP;
+ }
+ fxls8974_accel_convert(val, *raw, fsr);
+ }
+ k_sem_give(&data->sem);
+
+ return 0;
+}
+
+static int fxls8974_get_temp_data(const struct device *dev, struct sensor_value *val)
+{
+ struct fxls8974_data *data = dev->data;
+ int16_t *raw;
+
+ k_sem_take(&data->sem, K_FOREVER);
+ raw = &data->raw[FXLS8974_CHANNEL_TEMP];
+ val->val1 = *raw+FXLS8974_ZERO_TEMP;
+ k_sem_give(&data->sem);
+
+ return 0;
+}
+
+static int fxls8974_channel_get(const struct device *dev,
+ enum sensor_channel chan,
+ struct sensor_value *val)
+{
+
+ switch (chan) {
+ case SENSOR_CHAN_ALL:
+ if (fxls8974_get_accel_data(dev, val, SENSOR_CHAN_ACCEL_XYZ)) {
+ return -EIO;
+ }
+
+ val += FXLS8974_MAX_ACCEL_CHANNELS;
+
+ if (fxls8974_get_temp_data(dev, val)) {
+ return -EIO;
+ }
+ break;
+ case SENSOR_CHAN_ACCEL_XYZ:
+ return fxls8974_get_accel_data(dev, val, SENSOR_CHAN_ACCEL_XYZ);
+ case SENSOR_CHAN_ACCEL_X:
+ __fallthrough;
+ case SENSOR_CHAN_ACCEL_Y:
+ __fallthrough;
+ case SENSOR_CHAN_ACCEL_Z:
+ return fxls8974_get_accel_data(dev, val, chan);
+ case SENSOR_CHAN_AMBIENT_TEMP:
+ return fxls8974_get_temp_data(dev, val);
+ default:
+ LOG_ERR("Unsupported channel");
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
+
+int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ uint8_t val;
+
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_CTRLREG1, &val)) {
+ LOG_ERR("Could not get active setting");
+ return -EIO;
+ }
+ val &= FXLS8974_CTRLREG1_ACTIVE_MASK;
+
+ *active = val;
+
+ return 0;
+}
+
+int fxls8974_set_active(const struct device *dev, enum fxls8974_active active)
+{
+ const struct fxls8974_config *cfg = dev->config;
+
+ return cfg->ops->reg_field_update(dev, FXLS8974_REG_CTRLREG1,
+ FXLS8974_CTRLREG1_ACTIVE_MASK, active);
+}
+
+static void fxls8974_print_config(const struct device *dev)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ uint8_t regVal[5];
+
+ if (cfg->ops->read(dev, FXLS8974_REG_CTRLREG1, regVal, 5)) {
+ LOG_ERR("Failed to read config registers");
+ }
+ LOG_DBG("Current config:\n\r"
+ "CFG: 0x%02x CFG2: 0x%02x CFG3: 0x%02x CFG4: 0x%02x CFG5: 0x%02x",
+ regVal[0], regVal[1], regVal[2], regVal[3], regVal[4]);
+}
+
+static int fxls8974_init(const struct device *dev)
+{
+ const struct fxls8974_config *cfg = dev->config;
+ struct fxls8974_data *data = dev->data;
+ struct sensor_value odr = {.val1 = 6, .val2 = 250000};
+ uint8_t regVal;
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+ const struct i2c_dt_spec i2c_spec = cfg->bus_cfg.i2c;
+
+ if (cfg->inst_on_bus == FXLS8974_BUS_I2C) {
+ if (!i2c_is_ready_dt(&i2c_spec)) {
+ LOG_ERR("I2C bus device not ready");
+ return -ENODEV;
+ }
+ }
+#endif
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+ const struct spi_dt_spec spi_spec = cfg->bus_cfg.spi;
+
+ if (cfg->inst_on_bus == FXLS8974_BUS_SPI) {
+ if (!spi_is_ready_dt(&spi_spec)) {
+ LOG_ERR("SPI bus device not ready");
+ return -ENODEV;
+ }
+ }
+#endif
+
+ /* Software reset the sensor. Upon issuing a software
+ * reset command over the I2C interface, the sensor
+ * immediately resets and does not send any
+ * acknowledgment (ACK) of the written byte to the
+ * master. Therefore, do not check the return code of
+ * the I2C transaction.
+ */
+ cfg->ops->byte_write(dev, FXLS8974_REG_CTRLREG1,
+ FXLS8974_CTRLREG1_RST_MASK);
+
+ /* The sensor requires us to wait 1 ms after a reset before
+ * attempting further communications.
+ */
+ k_busy_wait(USEC_PER_MSEC);
+
+ /*
+ * Read the WHOAMI register to make sure we are talking to FXLS8974 or
+ * compatible device and not some other type of device that happens to
+ * have the same I2C address.
+ */
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_WHOAMI,
+ &data->whoami)) {
+ LOG_ERR("Could not get WHOAMI value");
+ return -EIO;
+ }
+
+ if (data->whoami == WHOAMI_ID_FXLS8974) {
+ LOG_DBG("Device ID 0x%x, FXLS8974", data->whoami);
+ } else {
+ LOG_ERR("Unknown Device ID 0x%x", data->whoami);
+ return -EIO;
+ }
+
+ if (fxls8974_get_active(dev, (enum fxls8974_active *)®Val)) {
+ LOG_ERR("Failed to set standby mode");
+ return -EIO;
+ }
+
+ if (regVal != FXLS8974_ACTIVE_OFF) {
+ LOG_ERR("Not in standby mode");
+ return -EIO;
+ }
+
+ if (cfg->ops->byte_write(dev, FXLS8974_REG_CTRLREG4,
+ FXLS8974_CTRLREG4_INT_POL_HIGH)) {
+ LOG_ERR("Could not set up register 4");
+ return -EIO;
+ }
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_CTRLREG4, ®Val)) {
+ LOG_ERR("Could not get CTRL_REG4 value");
+ return -EIO;
+ }
+
+ if (regVal != FXLS8974_CTRLREG4_INT_POL_HIGH) {
+ LOG_ERR("CTRLREG4 is not set up properly");
+ return -EIO;
+ }
+
+ if (fxls8974_set_odr(dev, &odr, FXLS8974_WAKE)) {
+ LOG_ERR("Could not set default data rate");
+ return -EIO;
+ }
+
+ /* Set the +-2G mode */
+ if (cfg->ops->byte_write(dev, FXLS8974_REG_CTRLREG1,
+ FXLS8974_CTRLREG1_FSR_2G)) {
+ LOG_ERR("Could not set range");
+ return -EIO;
+ }
+
+ if (cfg->ops->byte_read(dev, FXLS8974_REG_CTRLREG1,
+ ®Val)) {
+ LOG_ERR("Could not ret CTRL_REG1 value");
+ return -EIO;
+ }
+
+ if ((regVal & FXLS8974_CTRLREG1_FSR_MASK) != FXLS8974_CTRLREG1_FSR_2G) {
+ LOG_ERR("Wrong range selected!");
+ return -EIO;
+ }
+
+ k_sem_init(&data->sem, 0, K_SEM_MAX_LIMIT);
+
+#if CONFIG_FXLS8974_TRIGGER
+ if (fxls8974_trigger_init(dev)) {
+ LOG_ERR("Could not initialize interrupts");
+ return -EIO;
+ }
+#endif
+
+ if (fxls8974_set_active(dev, FXLS8974_ACTIVE_ON)) {
+ LOG_ERR("Could not set active mode");
+ return -EIO;
+ }
+
+ if (fxls8974_get_active(dev, (enum fxls8974_active *)®Val)) {
+ LOG_ERR("Failed to get active mode");
+ return -EIO;
+ }
+
+ if (regVal != FXLS8974_ACTIVE_ON) {
+ LOG_ERR("Not in active mode");
+ return -EIO;
+ }
+
+ fxls8974_print_config(dev);
+ k_sem_give(&data->sem);
+
+ LOG_DBG("Init complete");
+
+ return 0;
+}
+
+static const struct sensor_driver_api fxls8974_driver_api = {
+ .sample_fetch = fxls8974_sample_fetch,
+ .channel_get = fxls8974_channel_get,
+ .attr_set = fxls8974_attr_set,
+#if CONFIG_FXLS8974_TRIGGER
+ .trigger_set = fxls8974_trigger_set,
+#endif
+};
+
+#define FXLS8974_CONFIG_I2C(n) \
+ .bus_cfg = { .i2c = I2C_DT_SPEC_INST_GET(n) }, \
+ .ops = &fxls8974_i2c_ops, \
+ .range = DT_INST_PROP(n, range), \
+ .inst_on_bus = FXLS8974_BUS_I2C,
+
+#define FXLS8974_CONFIG_SPI(n) \
+ .bus_cfg = { .spi = SPI_DT_SPEC_INST_GET(n, \
+ SPI_OP_MODE_MASTER | SPI_WORD_SET(8), 0) }, \
+ .ops = &fxls8974_spi_ops, \
+ .range = DT_INST_PROP(n, range), \
+ .inst_on_bus = FXLS8974_BUS_SPI, \
+
+#define FXLS8974_SPI_OPERATION (SPI_WORD_SET(8) | \
+ SPI_OP_MODE_MASTER) \
+
+#define FXLS8974_INTM_PROPS(n, m) \
+ .int_gpio = GPIO_DT_SPEC_INST_GET(n, int##m##_gpios),
+
+#define FXLS8974_INT_PROPS(n) \
+ COND_CODE_1(CONFIG_FXLS8974_DRDY_INT1, \
+ (FXLS8974_INTM_PROPS(n, 1)), \
+ (FXLS8974_INTM_PROPS(n, 2)))
+
+#define FXLS8974_INT(n) \
+ COND_CODE_1(CONFIG_FXLS8974_TRIGGER, \
+ (FXLS8974_INT_PROPS(n)), \
+ ())
+
+#define FXLS8974_INIT(n) \
+ static const struct fxls8974_config fxls8974_config_##n = { \
+ COND_CODE_1(DT_INST_ON_BUS(n, spi), \
+ (FXLS8974_CONFIG_SPI(n)), \
+ (FXLS8974_CONFIG_I2C(n))) \
+ FXLS8974_INT(n) \
+ }; \
+ \
+ static struct fxls8974_data fxls8974_data_##n; \
+ \
+ SENSOR_DEVICE_DT_INST_DEFINE(n, \
+ fxls8974_init, \
+ NULL, \
+ &fxls8974_data_##n, \
+ &fxls8974_config_##n, \
+ POST_KERNEL, \
+ CONFIG_SENSOR_INIT_PRIORITY, \
+ &fxls8974_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(FXLS8974_INIT)
diff --git a/drivers/sensor/nxp/fxls8974/fxls8974.h b/drivers/sensor/nxp/fxls8974/fxls8974.h
new file mode 100644
index 0000000..e01cc78
--- /dev/null
+++ b/drivers/sensor/nxp/fxls8974/fxls8974.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor.h>
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+#include <zephyr/drivers/spi.h>
+#endif
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+#include <zephyr/drivers/i2c.h>
+#endif
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+#define FXLS8974_BUS_I2C (1<<0)
+#define FXLS8974_BUS_SPI (1<<1)
+#define FXLS8974_REG_OUTXLSB 0x04
+#define FXLS8974_REG_OUTTEMP 0x01
+#define FXLS8974_REG_WHOAMI 0x13
+#define FXLS8974_REG_CTRLREG1 0x15
+#define FXLS8974_REG_CTRLREG2 0x16
+#define FXLS8974_REG_CTRLREG3 0x17
+#define FXLS8974_REG_CTRLREG4 0x18
+#define FXLS8974_REG_CTRLREG5 0x19
+
+#define WHOAMI_ID_FXLS8974 0x86
+
+#define FXLS8974_CTRLREG1_ACTIVE_MASK 0x01
+#define FXLS8974_CTRLREG1_RST_MASK 0x80
+#define FXLS8974_CTRLREG1_FSR_MASK 0x06
+#define FXLS8974_CTRLREG1_FSR_2G 0x00
+#define FXLS8974_CTRLREG1_FSR_4G 0x02
+#define FXLS8974_CTRLREG1_FSR_8G 0x04
+#define FXLS8974_CTRLREG1_FSR_16G 0x06
+
+#define FXLS8974_CTRLREG2_WAKE_PM_MASK 0xC0
+#define FXLS8974_CTRLREG2_SLEEP_PM_MASK 0x30
+
+#define FXLS8974_CTRLREG3_WAKE_ODR_MASK 0xF0
+#define FXLS8974_CTRLREG3_SLEEP_ODR_MASK 0x0F
+
+#define FXLS8974_CTRLREG3_ODR_RATE_3200 0x00
+#define FXLS8974_CTRLREG3_ODR_RATE_1600 0x01
+#define FXLS8974_CTRLREG3_ODR_RATE_800 0x02
+#define FXLS8974_CTRLREG3_ODR_RATE_400 0x03
+#define FXLS8974_CTRLREG3_ODR_RATE_200 0x04
+#define FXLS8974_CTRLREG3_ODR_RATE_100 0x05
+#define FXLS8974_CTRLREG3_ODR_RATE_50 0x06
+#define FXLS8974_CTRLREG3_ODR_RATE_25 0x07
+#define FXLS8974_CTRLREG3_ODR_RATE_12_5 0x08
+#define FXLS8974_CTRLREG3_ODR_RATE_6_25 0x09
+#define FXLS8974_CTRLREG3_ODR_RATE_3_125 0x0A
+#define FXLS8974_CTRLREG3_ODR_RATE_1_563 0x0B
+#define FXLS8974_CTRLREG3_ODR_RATE_0_781 0x0C
+
+#define FXLS8974_CTRLREG4_INT_POL_HIGH 0x01
+
+#define FXLS8974_INTREG_EN 0x20
+#define FXLS8974_INT_PIN_SEL_REG 0x21
+
+#define FXLS8974_DATA_ACCEL_X_OFFSET 0
+#define FXLS8974_DATA_ACCEL_Y_OFFSET FXLS8974_BYTES_PER_CHANNEL_NORMAL
+#define FXLS8974_DATA_ACCEL_Z_OFFSET 2*FXLS8974_BYTES_PER_CHANNEL_NORMAL
+#define FXLS8974_DATA_TEMP_OFFSET 3*FXLS8974_BYTES_PER_CHANNEL_NORMAL
+#define FXLS8974_ZERO_TEMP 25
+
+#define FXLS8974_MAX_NUM_CHANNELS 4
+#define FXLS8974_MAX_ACCEL_CHANNELS 3
+#define FXLS8974_MAX_TEMP_CHANNELS 1
+
+#define FXLS8974_BYTES_PER_CHANNEL_NORMAL 2
+#define FXLS8974_BYTES_PER_CHANNEL_FAST 1
+
+#define FXLS8974_MAX_ACCEL_BYTES (FXLS8974_MAX_ACCEL_CHANNELS*2)
+#define FXLS8974_MAX_NUM_BYTES (FXLS8974_MAX_ACCEL_BYTES + FXLS8974_MAX_TEMP_CHANNELS)
+
+#define FXLS8974_DRDY_MASK 0x80
+
+enum fxls8974_active {
+ FXLS8974_ACTIVE_OFF = 0,
+ FXLS8974_ACTIVE_ON,
+};
+
+enum fxls8974_wake {
+ FXLS8974_WAKE = 0,
+ FXLS8974_SLEEP,
+};
+
+enum fxls8974_channel {
+ FXLS8974_CHANNEL_ACCEL_X = 0,
+ FXLS8974_CHANNEL_ACCEL_Y,
+ FXLS8974_CHANNEL_ACCEL_Z,
+ FXLS8974_CHANNEL_TEMP,
+};
+
+struct fxls8974_io_ops {
+ int (*read)(const struct device *dev,
+ uint8_t reg,
+ void *data,
+ size_t length);
+ int (*byte_read)(const struct device *dev,
+ uint8_t reg,
+ uint8_t *byte);
+ int (*byte_write)(const struct device *dev,
+ uint8_t reg,
+ uint8_t byte);
+ int (*reg_field_update)(const struct device *dev,
+ uint8_t reg,
+ uint8_t mask,
+ uint8_t val);
+};
+
+union fxls8974_bus_cfg {
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+ struct spi_dt_spec spi;
+#endif
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+ struct i2c_dt_spec i2c;
+#endif
+};
+
+struct fxls8974_config {
+ const union fxls8974_bus_cfg bus_cfg;
+ const struct fxls8974_io_ops *ops;
+ struct gpio_dt_spec reset_gpio;
+ uint8_t range;
+ uint8_t inst_on_bus;
+#ifdef CONFIG_FXLS8974_TRIGGER
+ struct gpio_dt_spec int_gpio;
+#endif
+
+};
+
+struct fxls8974_data {
+ struct k_sem sem;
+ int16_t raw[FXLS8974_MAX_NUM_CHANNELS];
+ uint8_t whoami;
+#ifdef CONFIG_FXLS8974_TRIGGER
+ const struct device *dev;
+ struct gpio_callback gpio_cb;
+ sensor_trigger_handler_t drdy_handler;
+ const struct sensor_trigger *drdy_trig;
+#endif
+#ifdef CONFIG_FXLS8974_TRIGGER_OWN_THREAD
+ K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_FXLS8974_THREAD_STACK_SIZE);
+ struct k_thread thread;
+ struct k_sem trig_sem;
+#endif
+#ifdef CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD
+ struct k_work work;
+#endif
+};
+
+int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active);
+int fxls8974_set_active(const struct device *dev, enum fxls8974_active active);
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+int fxls8974_byte_write_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t byte);
+
+int fxls8974_byte_read_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t *byte);
+
+int fxls8974_reg_field_update_spi(const struct device *dev,
+ uint8_t reg,
+ uint8_t mask,
+ uint8_t val);
+
+int fxls8974_read_spi(const struct device *dev,
+ uint8_t reg,
+ void *data,
+ size_t length);
+#endif
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+int fxls8974_byte_write_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t byte);
+
+int fxls8974_byte_read_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t *byte);
+
+int fxls8974_reg_field_update_i2c(const struct device *dev,
+ uint8_t reg,
+ uint8_t mask,
+ uint8_t val);
+
+int fxls8974_read_i2c(const struct device *dev,
+ uint8_t reg,
+ void *data,
+ size_t length);
+#endif
+#if CONFIG_FXLS8974_TRIGGER
+int fxls8974_trigger_init(const struct device *dev);
+int fxls8974_trigger_set(const struct device *dev,
+ const struct sensor_trigger *trig,
+ sensor_trigger_handler_t handler);
+#endif
diff --git a/drivers/sensor/nxp/fxls8974/fxls8974_trigger.c b/drivers/sensor/nxp/fxls8974/fxls8974_trigger.c
new file mode 100644
index 0000000..82fd723
--- /dev/null
+++ b/drivers/sensor/nxp/fxls8974/fxls8974_trigger.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2024 NXP
+ * Copyright (c) 2018 Phytec Messtechnik GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_fxls8974
+
+#include "fxls8974.h"
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(FXLS8974, CONFIG_SENSOR_LOG_LEVEL);
+
+static void fxls8974_gpio_callback(const struct device *dev,
+ struct gpio_callback *cb,
+ uint32_t pin_mask)
+{
+ struct fxls8974_data *data =
+ CONTAINER_OF(cb, struct fxls8974_data, gpio_cb);
+ const struct fxls8974_config *config = data->dev->config;
+
+ if ((pin_mask & BIT(config->int_gpio.pin)) == 0U) {
+ return;
+ }
+
+ gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_DISABLE);
+
+#if defined(CONFIG_FXLS8974_TRIGGER_OWN_THREAD)
+ k_sem_give(&data->trig_sem);
+#elif defined(CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD)
+ k_work_submit(&data->work);
+#endif
+}
+
+static int fxls8974_handle_drdy_int(const struct device *dev)
+{
+ struct fxls8974_data *data = dev->data;
+
+ if (data->drdy_handler) {
+ data->drdy_handler(dev, data->drdy_trig);
+ }
+
+ return 0;
+}
+
+static void fxls8974_handle_int(const struct device *dev)
+{
+ const struct fxls8974_config *config = dev->config;
+
+ fxls8974_handle_drdy_int(dev);
+
+ gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_LEVEL_HIGH);
+}
+
+#ifdef CONFIG_FXLS8974_TRIGGER_OWN_THREAD
+static void fxls8974_thread_main(void *p1, void *p2, void *p3)
+{
+ ARG_UNUSED(p2);
+ ARG_UNUSED(p3);
+
+ struct fxls8974_data *data = p1;
+
+ while (true) {
+ k_sem_take(&data->trig_sem, K_FOREVER);
+ fxls8974_handle_int(data->dev);
+ }
+}
+#endif
+
+#ifdef CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD
+static void fxls8974_work_handler(struct k_work *work)
+{
+ struct fxls8974_data *data =
+ CONTAINER_OF(work, struct fxls8974_data, work);
+
+ fxls8974_handle_int(data->dev);
+}
+#endif
+
+int fxls8974_trigger_set(const struct device *dev,
+ const struct sensor_trigger *trig,
+ sensor_trigger_handler_t handler)
+{
+ struct fxls8974_data *data = dev->data;
+ int ret = 0;
+
+ k_sem_take(&data->sem, K_FOREVER);
+
+ /* Put the sensor in standby mode */
+ if (fxls8974_set_active(dev, FXLS8974_ACTIVE_OFF)) {
+ LOG_ERR("Could not set standby mode");
+ ret = -EIO;
+ goto exit;
+ }
+
+ if (trig->type == SENSOR_TRIG_DATA_READY) {
+ data->drdy_handler = handler;
+ data->drdy_trig = trig;
+ } else {
+ LOG_ERR("Unsupported sensor trigger");
+ ret = -ENOTSUP;
+ goto exit;
+ }
+
+
+ /* Restore the previous active mode */
+ if (fxls8974_set_active(dev, FXLS8974_ACTIVE_ON)) {
+ LOG_ERR("Could not restore active mode");
+ ret = -EIO;
+ goto exit;
+ }
+
+exit:
+ k_sem_give(&data->sem);
+
+ return ret;
+}
+
+
+int fxls8974_trigger_init(const struct device *dev)
+{
+ const struct fxls8974_config *config = dev->config;
+ struct fxls8974_data *data = dev->data;
+ int ret;
+
+ data->dev = dev;
+
+#if defined(CONFIG_FXLS8974_TRIGGER_OWN_THREAD)
+ k_sem_init(&data->trig_sem, 0, K_SEM_MAX_LIMIT);
+ k_thread_create(&data->thread, data->thread_stack,
+ CONFIG_FXLS8974_THREAD_STACK_SIZE,
+ fxls8974_thread_main,
+ data, NULL, NULL,
+ K_PRIO_COOP(CONFIG_FXLS8974_THREAD_PRIORITY),
+ 0, K_NO_WAIT);
+#elif defined(CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD)
+ data->work.handler = fxls8974_work_handler;
+#endif
+
+ if (config->ops->byte_write(dev, FXLS8974_INTREG_EN,
+ FXLS8974_DRDY_MASK)) {
+ LOG_ERR("Could not enable interrupt");
+ return -EIO;
+ }
+
+#if !(CONFIG_FXLS8974_DRDY_INT1)
+ if (config->ops->byte_write(dev, FXLS8974_INT_PIN_SEL_REG,
+ FXLS8974_DRDY_MASK)) {
+ LOG_ERR("Could not configure interrupt pin routing");
+ return -EIO;
+ }
+#endif
+
+ if (!gpio_is_ready_dt(&config->int_gpio)) {
+ LOG_ERR("GPIO device not ready");
+ return -ENODEV;
+ }
+
+ ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
+ if (ret < 0) {
+ return ret;
+ }
+
+ gpio_init_callback(&data->gpio_cb, fxls8974_gpio_callback,
+ BIT(config->int_gpio.pin));
+
+ ret = gpio_add_callback(config->int_gpio.port, &data->gpio_cb);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/sensor/st/iis2iclx/iis2iclx.c b/drivers/sensor/st/iis2iclx/iis2iclx.c
index 3cc34cd..d667bf9 100644
--- a/drivers/sensor/st/iis2iclx/iis2iclx.c
+++ b/drivers/sensor/st/iis2iclx/iis2iclx.c
@@ -31,7 +31,7 @@
size_t i;
for (i = 0; i < ARRAY_SIZE(iis2iclx_odr_map); i++) {
- if (freq == iis2iclx_odr_map[i]) {
+ if (freq <= iis2iclx_odr_map[i]) {
return i;
}
}
@@ -50,7 +50,7 @@
return iis2iclx_odr_map[ARRAY_SIZE(iis2iclx_odr_map) - 1];
}
-static const uint16_t iis2iclx_accel_fs_map[] = {500, 3000, 1000, 2000};
+static const uint16_t iis2iclx_accel_fs_map[] = {500, 3000, 1000, 2000}; /* fs in mg */
static const uint16_t iis2iclx_accel_fs_sens[] = {1, 8, 2, 4};
static int iis2iclx_accel_range_to_fs_val(int32_t range)
@@ -130,7 +130,7 @@
int fs;
struct iis2iclx_data *data = dev->data;
- fs = iis2iclx_accel_range_to_fs_val(range);
+ fs = iis2iclx_accel_range_to_fs_val(range * 1000); /* pass range in mg */
if (fs < 0) {
return fs;
}
diff --git a/drivers/sensor/st/iis328dq/iis328dq.c b/drivers/sensor/st/iis328dq/iis328dq.c
index 99140e0..a38f0f5 100644
--- a/drivers/sensor/st/iis328dq/iis328dq.c
+++ b/drivers/sensor/st/iis328dq/iis328dq.c
@@ -77,10 +77,7 @@
} else if (odr <= 1) {
odr_reg = IIS328DQ_ODR_1Hz;
} else if (odr <= 2) {
- /* not sure what "5Hz2" is about, datasheet says PM=0b100 is 2Hz
- * https://github.com/STMicroelectronics/STMems_Standard_C_drivers/issues/162
- */
- odr_reg = IIS328DQ_ODR_5Hz2;
+ odr_reg = IIS328DQ_ODR_2Hz;
} else if (odr <= 5) {
odr_reg = IIS328DQ_ODR_5Hz;
} else if (odr <= 10) {
diff --git a/drivers/sensor/st/lis2dux12/lis2dux12.c b/drivers/sensor/st/lis2dux12/lis2dux12.c
index 44f6468..0d4a948 100644
--- a/drivers/sensor/st/lis2dux12/lis2dux12.c
+++ b/drivers/sensor/st/lis2dux12/lis2dux12.c
@@ -213,10 +213,9 @@
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
/* fetch raw data sample */
- lis2dux12_md_t mode;
lis2dux12_outt_data_t temp_data = {0};
- if (lis2dux12_outt_data_get(ctx, &mode, &temp_data) < 0) {
+ if (lis2dux12_outt_data_get(ctx, &temp_data) < 0) {
LOG_ERR("Failed to fetch raw temperature data sample");
return -EIO;
}
diff --git a/drivers/sensor/tdk/icm42670/CMakeLists.txt b/drivers/sensor/tdk/icm42670/CMakeLists.txt
index 56bcaf1..e225778 100644
--- a/drivers/sensor/tdk/icm42670/CMakeLists.txt
+++ b/drivers/sensor/tdk/icm42670/CMakeLists.txt
@@ -5,6 +5,7 @@
zephyr_library_sources(
icm42670.c
icm42670_spi.c
+ icm42670_i2c.c
)
zephyr_library_sources_ifdef(CONFIG_ICM42670_TRIGGER icm42670_trigger.c)
diff --git a/drivers/sensor/tdk/icm42670/Kconfig b/drivers/sensor/tdk/icm42670/Kconfig
index 7548f5e..40c2b4f 100644
--- a/drivers/sensor/tdk/icm42670/Kconfig
+++ b/drivers/sensor/tdk/icm42670/Kconfig
@@ -9,7 +9,8 @@
bool "ICM42670 Six-Axis Motion Tracking Device"
default y
depends on DT_HAS_INVENSENSE_ICM42670_ENABLED
- select SPI
+ select SPI if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670),spi)
+ select I2C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670),i2c)
help
Enable driver for ICM42670 SPI-based six-axis motion tracking device.
diff --git a/drivers/sensor/tdk/icm42670/icm42670.c b/drivers/sensor/tdk/icm42670/icm42670.c
index 34f64b7..fda9257 100644
--- a/drivers/sensor/tdk/icm42670/icm42670.c
+++ b/drivers/sensor/tdk/icm42670/icm42670.c
@@ -12,7 +12,6 @@
#include <zephyr/sys/byteorder.h>
#include "icm42670.h"
#include "icm42670_reg.h"
-#include "icm42670_spi.h"
#include "icm42670_trigger.h"
#include <zephyr/logging/log.h>
@@ -52,7 +51,7 @@
data->accel_sensitivity_shift = MIN_ACCEL_SENS_SHIFT + temp;
- return icm42670_spi_update_register(&cfg->spi, REG_ACCEL_CONFIG0,
+ return cfg->bus_io->update(&cfg->bus, REG_ACCEL_CONFIG0,
(uint8_t)MASK_ACCEL_UI_FS_SEL, temp);
}
@@ -79,7 +78,7 @@
data->gyro_sensitivity_x10 = icm42670_gyro_sensitivity_x10[temp];
- return icm42670_spi_update_register(&cfg->spi, REG_GYRO_CONFIG0,
+ return cfg->bus_io->update(&cfg->bus, REG_GYRO_CONFIG0,
(uint8_t)MASK_GYRO_UI_FS_SEL, temp);
}
@@ -117,7 +116,7 @@
temp = BIT_ACCEL_ODR_1;
}
- return icm42670_spi_update_register(&cfg->spi, REG_ACCEL_CONFIG0, (uint8_t)MASK_ACCEL_ODR,
+ return cfg->bus_io->update(&cfg->bus, REG_ACCEL_CONFIG0, (uint8_t)MASK_ACCEL_ODR,
temp);
}
@@ -149,7 +148,7 @@
temp = BIT_GYRO_ODR_12;
}
- return icm42670_spi_update_register(&cfg->spi, REG_GYRO_CONFIG0, (uint8_t)MASK_GYRO_ODR,
+ return cfg->bus_io->update(&cfg->bus, REG_GYRO_CONFIG0, (uint8_t)MASK_GYRO_ODR,
temp);
}
@@ -158,7 +157,7 @@
const struct icm42670_config *cfg = dev->config;
/* switch on MCLK by setting the IDLE bit */
- int res = icm42670_spi_single_write(&cfg->spi, REG_PWR_MGMT0, BIT_IDLE);
+ int res = cfg->bus_io->write(&cfg->bus, REG_PWR_MGMT0, BIT_IDLE);
if (res) {
return res;
@@ -169,7 +168,7 @@
uint8_t value = 0;
k_usleep(MCLK_POLL_INTERVAL_US);
- res = icm42670_spi_read(&cfg->spi, REG_MCLK_RDY, &value, 1);
+ res = cfg->bus_io->read(&cfg->bus, REG_MCLK_RDY, &value, 1);
if (res) {
return res;
@@ -193,7 +192,7 @@
k_msleep(3);
/* perform a soft reset to ensure a clean slate, reset bit will auto-clear */
- res = icm42670_spi_single_write(&cfg->spi, REG_SIGNAL_PATH_RESET, BIT_SOFT_RESET);
+ res = cfg->bus_io->write(&cfg->bus, REG_SIGNAL_PATH_RESET, BIT_SOFT_RESET);
if (res) {
LOG_ERR("write REG_SIGNAL_PATH_RESET failed");
@@ -204,14 +203,14 @@
k_msleep(SOFT_RESET_TIME_MS);
/* force SPI-4w hardware configuration (so that next read is correct) */
- res = icm42670_spi_single_write(&cfg->spi, REG_DEVICE_CONFIG, BIT_SPI_AP_4WIRE);
+ res = cfg->bus_io->write(&cfg->bus, REG_DEVICE_CONFIG, BIT_SPI_AP_4WIRE);
if (res) {
return res;
}
/* always use internal RC oscillator */
- res = icm42670_spi_single_write(&cfg->spi, REG_INTF_CONFIG1,
+ res = cfg->bus_io->write(&cfg->bus, REG_INTF_CONFIG1,
(uint8_t)FIELD_PREP(MASK_CLKSEL, BIT_CLKSEL_INT_RC));
if (res) {
@@ -219,7 +218,7 @@
}
/* clear reset done int flag */
- res = icm42670_spi_read(&cfg->spi, REG_INT_STATUS, &value, 1);
+ res = cfg->bus_io->read(&cfg->bus, REG_INT_STATUS, &value, 1);
if (res) {
return res;
@@ -237,7 +236,7 @@
return res;
}
- res = icm42670_spi_read(&cfg->spi, REG_WHO_AM_I, &value, 1);
+ res = cfg->bus_io->read(&cfg->bus, REG_WHO_AM_I, &value, 1);
if (res) {
return res;
@@ -263,7 +262,7 @@
value = FIELD_PREP(MASK_ACCEL_MODE, BIT_ACCEL_MODE_LNM) |
FIELD_PREP(MASK_GYRO_MODE, BIT_GYRO_MODE_LNM);
- res = icm42670_spi_update_register(&cfg->spi, REG_PWR_MGMT0,
+ res = cfg->bus_io->update(&cfg->bus, REG_PWR_MGMT0,
(uint8_t)(MASK_ACCEL_MODE | MASK_GYRO_MODE), value);
if (res) {
@@ -394,7 +393,7 @@
struct icm42670_data *data = dev->data;
uint8_t buffer[ACCEL_DATA_SIZE];
- int res = icm42670_spi_read(&cfg->spi, REG_ACCEL_DATA_X1, buffer, ACCEL_DATA_SIZE);
+ int res = cfg->bus_io->read(&cfg->bus, REG_ACCEL_DATA_X1, buffer, ACCEL_DATA_SIZE);
if (res) {
return res;
@@ -413,7 +412,7 @@
struct icm42670_data *data = dev->data;
uint8_t buffer[GYRO_DATA_SIZE];
- int res = icm42670_spi_read(&cfg->spi, REG_GYRO_DATA_X1, buffer, GYRO_DATA_SIZE);
+ int res = cfg->bus_io->read(&cfg->bus, REG_GYRO_DATA_X1, buffer, GYRO_DATA_SIZE);
if (res) {
return res;
@@ -432,7 +431,7 @@
struct icm42670_data *data = dev->data;
uint8_t buffer[TEMP_DATA_SIZE];
- int res = icm42670_spi_read(&cfg->spi, REG_TEMP_DATA1, buffer, TEMP_DATA_SIZE);
+ int res = cfg->bus_io->read(&cfg->bus, REG_TEMP_DATA1, buffer, TEMP_DATA_SIZE);
if (res) {
return res;
@@ -450,7 +449,7 @@
icm42670_lock(dev);
- int res = icm42670_spi_read(&cfg->spi, REG_INT_STATUS_DRDY, &status, 1);
+ int res = cfg->bus_io->read(&cfg->bus, REG_INT_STATUS_DRDY, &status, 1);
if (res) {
goto cleanup;
@@ -616,12 +615,18 @@
return res;
}
+static inline int icm42670_bus_check(const struct device *dev)
+{
+ const struct icm42670_config *cfg = dev->config;
+
+ return cfg->bus_io->check(&cfg->bus);
+}
+
static int icm42670_init(const struct device *dev)
{
struct icm42670_data *data = dev->data;
- const struct icm42670_config *cfg = dev->config;
- if (!spi_is_ready_dt(&cfg->spi)) {
+ if (icm42670_bus_check(dev) < 0) {
LOG_ERR("SPI bus is not ready");
return -ENODEV;
}
@@ -686,6 +691,16 @@
#define ICM42670_SPI_CFG \
SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_TRANSFER_MSB
+/* Initializes the bus members for an instance on a SPI bus. */
+#define ICM42670_CONFIG_SPI(inst) \
+ .bus.spi = SPI_DT_SPEC_INST_GET(inst, ICM42670_SPI_CFG, 0), \
+ .bus_io = &icm42670_bus_io_spi,
+
+/* Initializes the bus members for an instance on an I2C bus. */
+#define ICM42670_CONFIG_I2C(inst) \
+ .bus.i2c = I2C_DT_SPEC_INST_GET(inst), \
+ .bus_io = &icm42670_bus_io_i2c,
+
#define ICM42670_INIT(inst) \
static struct icm42670_data icm42670_driver_##inst = { \
.accel_hz = DT_INST_PROP(inst, accel_hz), \
@@ -693,12 +708,14 @@
.gyro_hz = DT_INST_PROP(inst, gyro_hz), \
.gyro_fs = DT_INST_PROP(inst, gyro_fs), \
}; \
- \
+ \
static const struct icm42670_config icm42670_cfg_##inst = { \
- .spi = SPI_DT_SPEC_INST_GET(inst, ICM42670_SPI_CFG, 0U), \
- .gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, { 0 }), \
+ COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
+ (ICM42670_CONFIG_SPI(inst)), \
+ (ICM42670_CONFIG_I2C(inst))) \
+ .gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}), \
}; \
- \
+ \
SENSOR_DEVICE_DT_INST_DEFINE(inst, icm42670_init, NULL, &icm42670_driver_##inst, \
&icm42670_cfg_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \
&icm42670_driver_api);
diff --git a/drivers/sensor/tdk/icm42670/icm42670.h b/drivers/sensor/tdk/icm42670/icm42670.h
index e3ca851..43adc3e 100644
--- a/drivers/sensor/tdk/icm42670/icm42670.h
+++ b/drivers/sensor/tdk/icm42670/icm42670.h
@@ -11,8 +11,45 @@
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
+#define ICM42670_BUS_SPI DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm42670, spi)
+#define ICM42670_BUS_I2C DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm42670, i2c)
+
+union icm42670_bus {
+#if ICM42670_BUS_SPI
+ struct spi_dt_spec spi;
+#endif
+#if ICM42670_BUS_I2C
+ struct i2c_dt_spec i2c;
+#endif
+};
+
+typedef int (*icm42670_bus_check_fn)(const union icm42670_bus *bus);
+typedef int (*icm42670_reg_read_fn)(const union icm42670_bus *bus,
+ uint16_t reg, uint8_t *data, size_t size);
+typedef int (*icm42670_reg_write_fn)(const union icm42670_bus *bus,
+ uint16_t reg, uint8_t data);
+
+typedef int (*icm42670_reg_update_fn)(const union icm42670_bus *bus,
+ uint16_t reg, uint8_t mask, uint8_t data);
+
+struct icm42670_bus_io {
+ icm42670_bus_check_fn check;
+ icm42670_reg_read_fn read;
+ icm42670_reg_write_fn write;
+ icm42670_reg_update_fn update;
+};
+
+#if ICM42670_BUS_SPI
+extern const struct icm42670_bus_io icm42670_bus_io_spi;
+#endif
+
+#if ICM42670_BUS_I2C
+extern const struct icm42670_bus_io icm42670_bus_io_i2c;
+#endif
+
struct icm42670_data {
int16_t accel_x;
int16_t accel_y;
@@ -45,7 +82,8 @@
};
struct icm42670_config {
- struct spi_dt_spec spi;
+ union icm42670_bus bus;
+ const struct icm42670_bus_io *bus_io;
struct gpio_dt_spec gpio_int;
};
diff --git a/drivers/sensor/tdk/icm42670/icm42670_i2c.c b/drivers/sensor/tdk/icm42670/icm42670_i2c.c
new file mode 100644
index 0000000..3ee3dfe
--- /dev/null
+++ b/drivers/sensor/tdk/icm42670/icm42670_i2c.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Bus-specific functionality for ICM42670 accessed via I2C.
+ */
+
+#include "icm42670.h"
+#include "icm42670_reg.h"
+
+#if ICM42670_BUS_I2C
+static int icm42670_bus_check_i2c(const union icm42670_bus *bus)
+{
+ return i2c_is_ready_dt(&bus->i2c) ? 0 : -ENODEV;
+}
+
+static int i2c_read_mreg(const union icm42670_bus *bus, uint8_t reg, uint8_t bank,
+ uint8_t *buf, size_t len)
+{
+ int res = i2c_reg_write_byte_dt(&bus->i2c, REG_BLK_SEL_R, bank);
+
+ if (res) {
+ return res;
+ }
+
+ /* reads from MREG registers must be done byte-by-byte */
+ for (size_t i = 0; i < len; i++) {
+ uint8_t addr = reg + i;
+
+ res = i2c_reg_write_byte_dt(&bus->i2c, REG_MADDR_R, addr);
+
+ if (res) {
+ return res;
+ }
+
+ k_usleep(MREG_R_W_WAIT_US);
+ res = i2c_reg_read_byte_dt(&bus->i2c, REG_M_R, &buf[i]);
+
+ if (res) {
+ return res;
+ }
+
+ k_usleep(MREG_R_W_WAIT_US);
+ }
+
+ return 0;
+}
+
+static int icm42670_reg_read_i2c(const union icm42670_bus *bus, uint16_t reg, uint8_t *data,
+ size_t len)
+{
+ int res = 0;
+ uint8_t bank = FIELD_GET(REG_BANK_MASK, reg);
+ uint8_t address = FIELD_GET(REG_ADDRESS_MASK, reg);
+
+ if (bank) {
+ res = i2c_read_mreg(bus, address, bank, data, len);
+ } else {
+ res = i2c_burst_read_dt(&bus->i2c, address, data, len);
+ }
+
+ return res;
+}
+
+static int i2c_write_mreg(const union icm42670_bus *bus, uint16_t reg, uint8_t bank,
+ uint8_t buf)
+{
+ int res = i2c_reg_write_byte_dt(&bus->i2c, REG_BLK_SEL_W, bank);
+
+ if (res) {
+ return res;
+ }
+
+ res = i2c_reg_write_byte_dt(&bus->i2c, REG_MADDR_W, reg);
+
+ if (res) {
+ return res;
+ }
+
+ res = i2c_reg_write_byte_dt(&bus->i2c, REG_M_W, buf);
+
+ if (res) {
+ return res;
+ }
+
+ k_usleep(MREG_R_W_WAIT_US);
+
+ return 0;
+}
+
+static int icm42670_reg_write_i2c(const union icm42670_bus *bus,
+ uint16_t reg, uint8_t data)
+{
+ int res = 0;
+ uint8_t bank = FIELD_GET(REG_BANK_MASK, reg);
+ uint8_t address = FIELD_GET(REG_ADDRESS_MASK, reg);
+
+ if (bank) {
+ res = i2c_write_mreg(bus, address, bank, data);
+ } else {
+ res = i2c_reg_write_byte_dt(&bus->i2c, address, data);
+ }
+
+ return res;
+}
+
+static int icm42670_reg_update_i2c(const union icm42670_bus *bus, uint16_t reg, uint8_t mask,
+ uint8_t val)
+{
+ return i2c_reg_update_byte_dt(&bus->i2c, reg, mask, val);
+}
+
+const struct icm42670_bus_io icm42670_bus_io_i2c = {
+ .check = icm42670_bus_check_i2c,
+ .read = icm42670_reg_read_i2c,
+ .write = icm42670_reg_write_i2c,
+ .update = icm42670_reg_update_i2c,
+};
+#endif /* ICM42670_BUS_I2C */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_spi.c b/drivers/sensor/tdk/icm42670/icm42670_spi.c
index 2edccb2..ce1b7b1 100644
--- a/drivers/sensor/tdk/icm42670/icm42670_spi.c
+++ b/drivers/sensor/tdk/icm42670/icm42670_spi.c
@@ -7,10 +7,11 @@
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
-#include "icm42670_spi.h"
+#include "icm42670.h"
#include "icm42670_reg.h"
-static inline int spi_write_register(const struct spi_dt_spec *bus, uint8_t reg, uint8_t data)
+#if ICM42670_BUS_SPI
+static inline int spi_write_register(const union icm42670_bus *bus, uint8_t reg, uint8_t data)
{
const struct spi_buf buf[2] = {
{
@@ -28,10 +29,10 @@
.count = 2,
};
- return spi_write_dt(bus, &tx);
+ return spi_write_dt(&bus->spi, &tx);
}
-static inline int spi_read_register(const struct spi_dt_spec *bus, uint8_t reg, uint8_t *data,
+static inline int spi_read_register(const union icm42670_bus *bus, uint8_t reg, uint8_t *data,
size_t len)
{
uint8_t tx_buffer = REG_SPI_READ_BIT | reg;
@@ -62,10 +63,10 @@
.count = 2,
};
- return spi_transceive_dt(bus, &tx, &rx);
+ return spi_transceive_dt(&bus->spi, &tx, &rx);
}
-static inline int spi_read_mreg(const struct spi_dt_spec *bus, uint8_t reg, uint8_t bank,
+static inline int spi_read_mreg(const union icm42670_bus *bus, uint8_t reg, uint8_t bank,
uint8_t *buf, size_t len)
{
int res = spi_write_register(bus, REG_BLK_SEL_R, bank);
@@ -97,7 +98,7 @@
return 0;
}
-static inline int spi_write_mreg(const struct spi_dt_spec *bus, uint8_t reg, uint8_t bank,
+static inline int spi_write_mreg(const union icm42670_bus *bus, uint8_t reg, uint8_t bank,
uint8_t buf)
{
int res = spi_write_register(bus, REG_BLK_SEL_W, bank);
@@ -123,7 +124,7 @@
return 0;
}
-int icm42670_spi_read(const struct spi_dt_spec *bus, uint16_t reg, uint8_t *data, size_t len)
+int icm42670_spi_read(const union icm42670_bus *bus, uint16_t reg, uint8_t *data, size_t len)
{
int res = 0;
uint8_t bank = FIELD_GET(REG_BANK_MASK, reg);
@@ -138,7 +139,22 @@
return res;
}
-int icm42670_spi_update_register(const struct spi_dt_spec *bus, uint16_t reg, uint8_t mask,
+int icm42670_spi_single_write(const union icm42670_bus *bus, uint16_t reg, uint8_t data)
+{
+ int res = 0;
+ uint8_t bank = FIELD_GET(REG_BANK_MASK, reg);
+ uint8_t address = FIELD_GET(REG_ADDRESS_MASK, reg);
+
+ if (bank) {
+ res = spi_write_mreg(bus, address, bank, data);
+ } else {
+ res = spi_write_register(bus, address, data);
+ }
+
+ return res;
+}
+
+int icm42670_spi_update_register(const union icm42670_bus *bus, uint16_t reg, uint8_t mask,
uint8_t data)
{
uint8_t temp = 0;
@@ -154,17 +170,16 @@
return icm42670_spi_single_write(bus, reg, temp);
}
-int icm42670_spi_single_write(const struct spi_dt_spec *bus, uint16_t reg, uint8_t data)
+static int icm42670_bus_check_spi(const union icm42670_bus *bus)
{
- int res = 0;
- uint8_t bank = FIELD_GET(REG_BANK_MASK, reg);
- uint8_t address = FIELD_GET(REG_ADDRESS_MASK, reg);
-
- if (bank) {
- res = spi_write_mreg(bus, address, bank, data);
- } else {
- res = spi_write_register(bus, address, data);
- }
-
- return res;
+ return spi_is_ready_dt(&bus->spi) ? 0 : -ENODEV;
}
+
+const struct icm42670_bus_io icm42670_bus_io_spi = {
+ .check = icm42670_bus_check_spi,
+ .read = icm42670_spi_read,
+ .write = icm42670_spi_single_write,
+ .update = icm42670_spi_update_register,
+};
+
+#endif /* ICM42670_BUS_SPI */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_spi.h b/drivers/sensor/tdk/icm42670/icm42670_spi.h
deleted file mode 100644
index 68bc652..0000000
--- a/drivers/sensor/tdk/icm42670/icm42670_spi.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2022 Esco Medical ApS
- * Copyright (c) 2020 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42670_SPI_H_
-#define ZEPHYR_DRIVERS_SENSOR_ICM42670_SPI_H_
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/spi.h>
-
-/**
- * @brief perform a single SPI write to a ICM42670 register
- *
- * this functions wraps all logic necessary to write to any of the ICM42670 registers, regardless
- * of which memory bank the register belongs to.
- *
- * @param bus SPI bus pointer
- * @param reg address of ICM42670 register to write to
- * @param data data byte to write to register
- * @return int 0 on success, negative error code otherwise
- */
-int icm42670_spi_single_write(const struct spi_dt_spec *bus, uint16_t reg, uint8_t data);
-
-/**
- * @brief update a single ICM42670 register value
- *
- * this functions wraps all logic necessary to update any of the ICM42670 registers, regardless
- * of which memory bank the register belongs to.
- *
- * @param bus SPI bus pointer
- * @param reg address of ICM42670 register to update
- * @param mask bitmask defining which bits of the register to update
- * @param data new value to update register with, respecting the bitmask
- * @return int 0 on success, negative error code otherwise
- */
-int icm42670_spi_update_register(const struct spi_dt_spec *bus, uint16_t reg, uint8_t mask,
- uint8_t data);
-
-/**
- * @brief read from one or more ICM42670 registers
- *
- * this functions wraps all logic necessary to read from any of the ICM42670 registers, regardless
- * of which memory bank the register belongs to.
- *
- * @param bus SPI bus pointer
- * @param reg start address of ICM42670 register(s) to read from
- * @param data pointer to byte array to read register values to
- * @param len number of bytes to read from the device
- * @return int 0 on success, negative error code otherwise
- */
-int icm42670_spi_read(const struct spi_dt_spec *bus, uint16_t reg, uint8_t *data, size_t len);
-
-#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42670_SPI_H_ */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_trigger.c b/drivers/sensor/tdk/icm42670/icm42670_trigger.c
index 1bd9ea6..3d84d88 100644
--- a/drivers/sensor/tdk/icm42670/icm42670_trigger.c
+++ b/drivers/sensor/tdk/icm42670/icm42670_trigger.c
@@ -10,7 +10,6 @@
#include <zephyr/sys/util.h>
#include "icm42670.h"
#include "icm42670_reg.h"
-#include "icm42670_spi.h"
#include "icm42670_trigger.h"
#include <zephyr/logging/log.h>
@@ -149,7 +148,7 @@
const struct icm42670_config *cfg = dev->config;
/* pulse-mode (auto clearing), push-pull and active-high */
- res = icm42670_spi_single_write(&cfg->spi, REG_INT_CONFIG,
+ res = cfg->bus_io->write(&cfg->bus, REG_INT_CONFIG,
BIT_INT1_DRIVE_CIRCUIT | BIT_INT1_POLARITY);
if (res) {
@@ -157,7 +156,7 @@
}
/* enable data ready interrupt on INT1 pin */
- return icm42670_spi_single_write(&cfg->spi, REG_INT_SOURCE0, BIT_INT_DRDY_INT1_EN);
+ return cfg->bus_io->write(&cfg->bus, REG_INT_SOURCE0, BIT_INT_DRDY_INT1_EN);
}
void icm42670_lock(const struct device *dev)
diff --git a/drivers/sensor/ti/lm95234/lm95234.c b/drivers/sensor/ti/lm95234/lm95234.c
index 9beabc6..c14f2ce 100644
--- a/drivers/sensor/ti/lm95234/lm95234.c
+++ b/drivers/sensor/ti/lm95234/lm95234.c
@@ -147,14 +147,16 @@
switch ((uint32_t)chan) {
case SENSOR_CHAN_ALL:
ret = lm95234_fetch_temp(cfg, data, SENSOR_CHAN_AMBIENT_TEMP, &data->local);
- if (ret)
+ if (ret) {
return ret;
+ }
for (int i = 0; i < ARRAY_SIZE(data->remote); i++) {
ret = lm95234_fetch_temp(cfg, data,
SENSOR_CHAN_LM95234_REMOTE_TEMP_1 + i,
&data->remote[i]);
- if (ret)
+ if (ret) {
return ret;
+ }
}
break;
case SENSOR_CHAN_AMBIENT_TEMP:
diff --git a/drivers/sensor/ti/tmp114/tmp114.c b/drivers/sensor/ti/tmp114/tmp114.c
index 747a825..128bfc5 100644
--- a/drivers/sensor/ti/tmp114/tmp114.c
+++ b/drivers/sensor/ti/tmp114/tmp114.c
@@ -27,6 +27,7 @@
#define TMP114_DEVICE_ID 0x1114
#define TMP114_ALERT_DATA_READY BIT(0)
+#define TMP114_AVG_MASK BIT(7)
struct tmp114_data {
uint16_t sample;
@@ -52,6 +53,15 @@
return 0;
}
+static int tmp114_reg_write(const struct device *dev, uint8_t reg,
+ uint16_t val)
+{
+ const struct tmp114_dev_config *cfg = dev->config;
+ uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF};
+
+ return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf));
+}
+
static inline int tmp114_device_id_check(const struct device *dev, uint16_t *id)
{
if (tmp114_reg_read(dev, TMP114_REG_DEVICE_ID, id) != 0) {
@@ -155,8 +165,41 @@
return 0;
}
+static int tmp114_attr_set(const struct device *dev,
+ enum sensor_channel chan,
+ enum sensor_attribute attr,
+ const struct sensor_value *val)
+{
+ int16_t value;
+ int rc;
+
+ if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
+ return -ENOTSUP;
+ }
+
+ switch (attr) {
+ case SENSOR_ATTR_OVERSAMPLING:
+ /* Enable the AVG in tmp114. The chip will do 8 avg of 8 samples
+ * to get a more accurate value.
+ */
+ rc = tmp114_reg_read(dev, TMP114_REG_CFGR, &value);
+ if (rc < 0) {
+ return rc;
+ }
+ value = value & ~TMP114_AVG_MASK;
+ if (val->val1) {
+ value |= TMP114_AVG_MASK;
+ }
+
+ return tmp114_reg_write(dev, TMP114_REG_CFGR, value);
+ default:
+ return -ENOTSUP;
+ }
+}
+
static const struct sensor_driver_api tmp114_driver_api = {
.attr_get = tmp114_attr_get,
+ .attr_set = tmp114_attr_set,
.sample_fetch = tmp114_sample_fetch,
.channel_get = tmp114_channel_get
};
diff --git a/drivers/sensor/voltage_divider/voltage.c b/drivers/sensor/voltage_divider/voltage.c
index f04b707..0869935 100644
--- a/drivers/sensor/voltage_divider/voltage.c
+++ b/drivers/sensor/voltage_divider/voltage.c
@@ -87,11 +87,10 @@
.channel_get = get,
};
-#ifdef CONFIG_PM_DEVICE
static int pm_action(const struct device *dev, enum pm_device_action action)
{
const struct voltage_config *config = dev->config;
- int ret;
+ int ret = 0;
if (config->gpio_power.port == NULL) {
/* No work to do */
@@ -99,25 +98,34 @@
}
switch (action) {
+ case PM_DEVICE_ACTION_TURN_ON:
+ ret = gpio_pin_configure_dt(&config->gpio_power, GPIO_OUTPUT_INACTIVE);
+ if (ret != 0) {
+ LOG_ERR("failed to configure GPIO for PM on");
+ }
+ break;
case PM_DEVICE_ACTION_RESUME:
ret = gpio_pin_set_dt(&config->gpio_power, 1);
if (ret != 0) {
LOG_ERR("failed to set GPIO for PM resume");
}
break;
+#ifdef CONFIG_PM_DEVICE
case PM_DEVICE_ACTION_SUSPEND:
ret = gpio_pin_set_dt(&config->gpio_power, 0);
if (ret != 0) {
LOG_ERR("failed to set GPIO for PM suspend");
}
break;
+ case PM_DEVICE_ACTION_TURN_OFF:
+ break;
+#endif /* CONFIG_PM_DEVICE */
default:
return -ENOTSUP;
}
return ret;
}
-#endif
static int voltage_init(const struct device *dev)
{
@@ -135,11 +143,6 @@
LOG_ERR("Power GPIO is not ready");
return -ENODEV;
}
-
- ret = gpio_pin_configure_dt(&config->gpio_power, GPIO_OUTPUT_ACTIVE);
- if (ret != 0) {
- LOG_ERR("failed to initialize GPIO for reset");
- }
}
ret = adc_channel_setup_dt(&config->voltage.port);
@@ -157,7 +160,7 @@
data->sequence.buffer = &data->raw;
data->sequence.buffer_size = sizeof(data->raw);
- return 0;
+ return pm_device_driver_init(dev, pm_action);
}
#define VOLTAGE_INIT(inst) \
diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt
index 03b986a..bbb7da1 100644
--- a/drivers/serial/CMakeLists.txt
+++ b/drivers/serial/CMakeLists.txt
@@ -77,6 +77,7 @@
zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c)
zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
+zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c)
if(CONFIG_UART_NATIVE_POSIX)
zephyr_library_compile_definitions(NO_POSIX_CHEATS)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index faa1502..ef557d0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -278,6 +278,6 @@
rsource "Kconfig.rzt2m"
-source "drivers/serial/Kconfig.renesas_ra8"
+rsource "Kconfig.renesas_ra8"
endif # SERIAL
diff --git a/drivers/serial/Kconfig.it8xxx2 b/drivers/serial/Kconfig.it8xxx2
index f89874f..0af4d83 100644
--- a/drivers/serial/Kconfig.it8xxx2
+++ b/drivers/serial/Kconfig.it8xxx2
@@ -4,7 +4,7 @@
config UART_ITE_IT8XXX2
bool "ITE IT8XXX2 UART driver"
default y
- select UART_NS16550_ITE_HIGH_SPEED_BUADRATE
+ select UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
depends on DT_HAS_ITE_IT8XXX2_UART_ENABLED
help
IT8XXX2 uses shared ns16550.c driver which does not
diff --git a/drivers/serial/Kconfig.native_posix b/drivers/serial/Kconfig.native_posix
index 3af6601..eaa13bb 100644
--- a/drivers/serial/Kconfig.native_posix
+++ b/drivers/serial/Kconfig.native_posix
@@ -13,7 +13,7 @@
if UART_NATIVE_POSIX
-choice
+choice NATIVE_UART_0
prompt "Native UART Port 0 connection"
default NATIVE_UART_0_ON_OWN_PTY
diff --git a/drivers/serial/Kconfig.nrfx b/drivers/serial/Kconfig.nrfx
index 930dd00..daf185c 100644
--- a/drivers/serial/Kconfig.nrfx
+++ b/drivers/serial/Kconfig.nrfx
@@ -32,7 +32,8 @@
bool "Legacy UARTE shim"
depends on UART_NRFX_UARTE
depends on !SOC_SERIES_NRF54LX
- depends on RISCV || !SOC_SERIES_NRF54HX
+ depends on !SOC_SERIES_NRF54HX || RISCV
+ depends on !SOC_SERIES_NRF92X || RISCV
# New shim takes more ROM. Until it is fixed use legacy shim.
default y
diff --git a/drivers/serial/Kconfig.ns16550 b/drivers/serial/Kconfig.ns16550
index fd7f115..12e8034 100644
--- a/drivers/serial/Kconfig.ns16550
+++ b/drivers/serial/Kconfig.ns16550
@@ -74,7 +74,7 @@
Texas Instruments K3 SoCs by enabling a vendor specific extended register
set.
-config UART_NS16550_ITE_HIGH_SPEED_BUADRATE
+config UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
bool "IT8XXX2 specific baud rate configuration"
help
Enable IT8XXX2 specific baud rate configuration.
diff --git a/drivers/serial/Kconfig.renesas_ra b/drivers/serial/Kconfig.renesas_ra
index 14311f2..37c6a12 100644
--- a/drivers/serial/Kconfig.renesas_ra
+++ b/drivers/serial/Kconfig.renesas_ra
@@ -1,4 +1,5 @@
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config UART_RENESAS_RA
@@ -9,3 +10,25 @@
select SERIAL_SUPPORT_INTERRUPT
help
Enable Renesas RA series UART driver.
+
+config UART_SCI_RA
+ bool "Renesas RA SCI UART"
+ default y
+ depends on DT_HAS_RENESAS_RA_SCI_UART_ENABLED
+ select SERIAL_HAS_DRIVER
+ select SERIAL_SUPPORT_INTERRUPT
+ select SERIAL_SUPPORT_ASYNC
+ select USE_RA_FSP_SCI_UART
+ select USE_RA_FSP_DTC if UART_ASYNC_API
+ help
+ Enable Renesas RA SCI UART Driver.
+
+if UART_SCI_RA
+
+config UART_RA_SCI_UART_FIFO_ENABLE
+ bool "RA SCI UART FIFO usage enable"
+ default y
+ help
+ Enable RA SCI FIFO
+
+endif
diff --git a/drivers/serial/serial_esp32_usb.c b/drivers/serial/serial_esp32_usb.c
index bc6ba33..e709710 100644
--- a/drivers/serial/serial_esp32_usb.c
+++ b/drivers/serial/serial_esp32_usb.c
@@ -43,6 +43,8 @@
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
int irq_source;
+ int irq_priority;
+ int irq_flags;
};
struct serial_esp32_usb_data {
@@ -50,7 +52,6 @@
uart_irq_callback_user_data_t irq_cb;
void *irq_cb_data;
#endif
- int irq_line;
int64_t last_tx_time;
};
@@ -107,9 +108,16 @@
int ret = clock_control_on(config->clock_dev, config->clock_subsys);
+ if (ret != 0) {
+ return ret;
+ }
+
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
- data->irq_line = esp_intr_alloc(config->irq_source, 0, (ISR_HANDLER)serial_esp32_usb_isr,
- (void *)dev, NULL);
+ ret = esp_intr_alloc(config->irq_source,
+ ESP_PRIO_TO_FLAGS(config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(config->irq_flags),
+ (ISR_HANDLER)serial_esp32_usb_isr,
+ (void *)dev, NULL);
#endif
return ret;
}
@@ -269,7 +277,9 @@
static const DRAM_ATTR struct serial_esp32_usb_config serial_esp32_usb_cfg = {
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
- .irq_source = DT_INST_IRQN(0)
+ .irq_source = DT_INST_IRQ_BY_IDX(0, 0, irq),
+ .irq_priority = DT_INST_IRQ_BY_IDX(0, 0, priority),
+ .irq_flags = DT_INST_IRQ_BY_IDX(0, 0, flags)
};
static struct serial_esp32_usb_data serial_esp32_usb_data_0;
diff --git a/drivers/serial/uart_bcm2711.c b/drivers/serial/uart_bcm2711.c
index c8de51b..2d501f0 100644
--- a/drivers/serial/uart_bcm2711.c
+++ b/drivers/serial/uart_bcm2711.c
@@ -80,8 +80,9 @@
static void bcm2711_mu_lowlevel_putc(mem_addr_t base, uint8_t ch)
{
/* Wait until there is data in the FIFO */
- while (!bcm2711_mu_lowlevel_can_putc(base))
+ while (!bcm2711_mu_lowlevel_can_putc(base)) {
;
+ }
/* Send the character */
sys_write32(ch, base + BCM2711_MU_IO);
@@ -93,8 +94,9 @@
uint32_t divider;
/* Wait until there is data in the FIFO */
- while (!bcm2711_mu_lowlevel_can_putc(base))
+ while (!bcm2711_mu_lowlevel_can_putc(base)) {
;
+ }
/* Disable port */
sys_write32(0x0, base + BCM2711_MU_CNTL);
@@ -148,8 +150,9 @@
{
struct bcm2711_uart_data *uart_data = dev->data;
- while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr))
+ while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
;
+ }
return sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
}
diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c
index cce4935..5a85f27 100644
--- a/drivers/serial/uart_esp32.c
+++ b/drivers/serial/uart_esp32.c
@@ -21,6 +21,10 @@
#include <esp32s3/rom/ets_sys.h>
#include <esp32s3/rom/gpio.h>
#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
+#elif defined(CONFIG_SOC_SERIES_ESP32C2)
+#include <esp32c2/rom/ets_sys.h>
+#include <esp32c2/rom/gpio.h>
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
#elif defined(CONFIG_SOC_SERIES_ESP32C3)
#include <esp32c3/rom/ets_sys.h>
#include <esp32c3/rom/gpio.h>
@@ -47,7 +51,9 @@
#include <soc.h>
#include <zephyr/drivers/uart.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32C6)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
@@ -61,7 +67,9 @@
LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL);
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+ defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32C6)
#define ISR_HANDLER isr_handler_t
#else
#define ISR_HANDLER intr_handler_t
@@ -73,6 +81,7 @@
const clock_control_subsys_t clock_subsys;
int irq_source;
int irq_priority;
+ int irq_flags;
bool tx_invert;
bool rx_invert;
#if CONFIG_UART_ASYNC_API
@@ -929,7 +938,8 @@
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
ret = esp_intr_alloc(config->irq_source,
- config->irq_priority,
+ ESP_PRIO_TO_FLAGS(config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(config->irq_flags),
(ISR_HANDLER)uart_esp32_isr,
(void *)dev,
NULL);
@@ -1001,12 +1011,9 @@
#define ESP_UART_UHCI_INIT(n) \
.uhci_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (&UHCI0), (NULL))
-#define UART_IRQ_PRIORITY ESP_INTR_FLAG_LEVEL2
-
#else
#define ESP_UART_DMA_INIT(n)
#define ESP_UART_UHCI_INIT(n)
-#define UART_IRQ_PRIORITY (0)
#endif
#define ESP32_UART_INIT(idx) \
@@ -1017,8 +1024,9 @@
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
- .irq_source = DT_INST_IRQN(idx), \
- .irq_priority = UART_IRQ_PRIORITY, \
+ .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
+ .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags), \
.tx_invert = DT_INST_PROP_OR(idx, tx_invert, false), \
.rx_invert = DT_INST_PROP_OR(idx, rx_invert, false), \
ESP_UART_DMA_INIT(idx)}; \
diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c
index d4abff5..a46dc34 100644
--- a/drivers/serial/uart_ns16550.c
+++ b/drivers/serial/uart_ns16550.c
@@ -267,7 +267,7 @@
#define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
-#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BUADRATE
+#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
/* Register definitions (ITE_IT8XXX2) */
#define REG_ECSPMR 0x08 /* EC Serial port mode reg */
@@ -427,8 +427,7 @@
return 0;
}
-#if (defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA) & (defined(CONFIG_UART_ASYNC_API)))\
- | UART_NS16550_PCP_ENABLED
+__maybe_unused
static void ns16550_outword(const struct uart_ns16550_device_config *cfg,
uintptr_t port, uint32_t val)
{
@@ -444,6 +443,7 @@
}
}
+__maybe_unused
static uint32_t ns16550_inword(const struct uart_ns16550_device_config *cfg,
uintptr_t port)
{
@@ -455,7 +455,6 @@
/* MMIO mapped */
return sys_read32(port);
}
-#endif
static inline uint8_t reg_interval(const struct device *dev)
{
@@ -482,7 +481,7 @@
return port;
}
-static uint32_t get_uart_burdrate_divisor(const struct device *dev,
+static uint32_t get_uart_baudrate_divisor(const struct device *dev,
uint32_t baud_rate,
uint32_t pclk)
{
@@ -494,8 +493,8 @@
return ((pclk + (baud_rate << 3)) / baud_rate) >> 4;
}
-#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BUADRATE
-static uint32_t get_ite_uart_burdrate_divisor(const struct device *dev,
+#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
+static uint32_t get_ite_uart_baudrate_divisor(const struct device *dev,
uint32_t baud_rate,
uint32_t pclk)
{
@@ -517,7 +516,7 @@
*/
ns16550_outbyte(dev_cfg, ECSPMR(dev), ECSPMR_ECHS);
} else {
- divisor = get_uart_burdrate_divisor(dev, baud_rate, pclk);
+ divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
/* Set ECSPMR register as default */
ns16550_outbyte(dev_cfg, ECSPMR(dev), 0);
}
@@ -534,10 +533,10 @@
uint8_t lcr_cache;
if ((baud_rate != 0U) && (pclk != 0U)) {
-#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BUADRATE
- divisor = get_ite_uart_burdrate_divisor(dev, baud_rate, pclk);
+#ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
+ divisor = get_ite_uart_baudrate_divisor(dev, baud_rate, pclk);
#else
- divisor = get_uart_burdrate_divisor(dev, baud_rate, pclk);
+ divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
#endif
/* set the DLAB to access the baud rate divisor registers */
lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
diff --git a/drivers/serial/uart_nxp_s32_linflexd.c b/drivers/serial/uart_nxp_s32_linflexd.c
index b4f58dc..4ab143a 100644
--- a/drivers/serial/uart_nxp_s32_linflexd.c
+++ b/drivers/serial/uart_nxp_s32_linflexd.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -255,7 +255,7 @@
static void uart_nxp_s32_event_handler(const uint8 instance,
Linflexd_Uart_Ip_EventType event,
- void *user_data)
+ const void *user_data)
{
const struct device *dev = (const struct device *)user_data;
const struct uart_nxp_s32_config *config = dev->config;
diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c
index d28d75b..02238e8 100644
--- a/drivers/serial/uart_pl011.c
+++ b/drivers/serial/uart_pl011.c
@@ -33,7 +33,17 @@
#endif
#include "uart_pl011_registers.h"
+
+#if defined(CONFIG_SOC_FAMILY_AMBIQ)
#include "uart_pl011_ambiq.h"
+#endif
+
+#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+#define PM_INST_GET(n) PM_DEVICE_DT_INST_GET(n)
+#else
+#define PM_INST_GET(n) NULL
+#endif
+
#include "uart_pl011_raspberrypi_pico.h"
struct pl011_config {
@@ -648,33 +658,30 @@
};
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
-#define PL011_INIT(n) \
- PINCTRL_DEFINE(n) \
- COMPAT_SPECIFIC_DEFINE(n) \
- PL011_CONFIG_PORT(n) \
- \
- static struct pl011_data pl011_data_port_##n = { \
- .uart_cfg = { \
- .baudrate = DT_INST_PROP(n, current_speed), \
- .parity = UART_CFG_PARITY_NONE, \
- .stop_bits = UART_CFG_STOP_BITS_1, \
- .data_bits = UART_CFG_DATA_BITS_8, \
- .flow_ctrl = DT_INST_PROP(n, hw_flow_control) \
- ? UART_CFG_FLOW_CTRL_RTS_CTS \
- : UART_CFG_FLOW_CTRL_NONE, \
- }, \
- .clk_freq = COND_CODE_1( \
- DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), \
- (DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency)), (0)), \
- }; \
- \
- DEVICE_DT_INST_DEFINE(n, pl011_init, \
- NULL, \
- &pl011_data_port_##n, \
- &pl011_cfg_port_##n, \
- PRE_KERNEL_1, \
- CONFIG_SERIAL_INIT_PRIORITY, \
- &pl011_driver_api);
+#define PL011_INIT(n) \
+ PINCTRL_DEFINE(n) \
+ COMPAT_SPECIFIC_DEFINE(n) \
+ PL011_CONFIG_PORT(n) \
+ \
+ static struct pl011_data pl011_data_port_##n = { \
+ .uart_cfg = \
+ { \
+ .baudrate = DT_INST_PROP(n, current_speed), \
+ .parity = UART_CFG_PARITY_NONE, \
+ .stop_bits = UART_CFG_STOP_BITS_1, \
+ .data_bits = UART_CFG_DATA_BITS_8, \
+ .flow_ctrl = DT_INST_PROP(n, hw_flow_control) \
+ ? UART_CFG_FLOW_CTRL_RTS_CTS \
+ : UART_CFG_FLOW_CTRL_NONE, \
+ }, \
+ .clk_freq = \
+ COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), \
+ (DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency)), (0)), \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(n, pl011_init, PM_INST_GET(n), &pl011_data_port_##n, \
+ &pl011_cfg_port_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
+ &pl011_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PL011_INIT)
diff --git a/drivers/serial/uart_pl011_ambiq.h b/drivers/serial/uart_pl011_ambiq.h
index 62d6d92..5866ff7 100644
--- a/drivers/serial/uart_pl011_ambiq.h
+++ b/drivers/serial/uart_pl011_ambiq.h
@@ -9,8 +9,11 @@
#include <zephyr/device.h>
#include <zephyr/kernel.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
#include "uart_pl011_registers.h"
+#include <am_mcu_apollo.h>
#define PWRCTRL_MAX_WAIT_US 5
@@ -50,6 +53,113 @@
return pl011_ambiq_clk_set(dev, clk);
}
+#ifdef CONFIG_PM_DEVICE
+
+/* Register status record.
+ * The register status will be preserved to this variable before entering sleep mode,
+ * and they will be restored after wake up.
+ */
+typedef struct {
+ bool bValid;
+ uint32_t regILPR;
+ uint32_t regIBRD;
+ uint32_t regFBRD;
+ uint32_t regLCRH;
+ uint32_t regCR;
+ uint32_t regIFLS;
+ uint32_t regIER;
+} uart_register_state_t;
+static uart_register_state_t sRegState[2];
+
+static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
+{
+ int key;
+
+ /*Uart module number*/
+ uint32_t ui32Module = ((uint32_t)get_uart(dev) == UART0_BASE) ? 0 : 1;
+
+ /*Uart Power module*/
+ am_hal_pwrctrl_periph_e eUARTPowerModule =
+ ((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + ui32Module));
+
+ /*Uart register status*/
+ uart_register_state_t *pRegisterStatus = &sRegState[ui32Module];
+
+ /* Decode the requested power state and update UART operation accordingly.*/
+ switch (action) {
+
+ /* Turn on the UART. */
+ case PM_DEVICE_ACTION_RESUME:
+
+ /* Make sure we don't try to restore an invalid state.*/
+ if (!pRegisterStatus->bValid) {
+ return -EPERM;
+ }
+
+ /*The resume and suspend actions may be executed back-to-back,
+ * so we add a busy wait here for stabilization.
+ */
+ k_busy_wait(100);
+
+ /* Enable power control.*/
+ am_hal_pwrctrl_periph_enable(eUARTPowerModule);
+
+ /* Restore UART registers*/
+ key = irq_lock();
+
+ UARTn(ui32Module)->ILPR = pRegisterStatus->regILPR;
+ UARTn(ui32Module)->IBRD = pRegisterStatus->regIBRD;
+ UARTn(ui32Module)->FBRD = pRegisterStatus->regFBRD;
+ UARTn(ui32Module)->LCRH = pRegisterStatus->regLCRH;
+ UARTn(ui32Module)->CR = pRegisterStatus->regCR;
+ UARTn(ui32Module)->IFLS = pRegisterStatus->regIFLS;
+ UARTn(ui32Module)->IER = pRegisterStatus->regIER;
+ pRegisterStatus->bValid = false;
+
+ irq_unlock(key);
+
+ return 0;
+ case PM_DEVICE_ACTION_SUSPEND:
+
+ while ((get_uart(dev)->fr & PL011_FR_BUSY) != 0)
+ ;
+
+ /* Preserve UART registers*/
+ key = irq_lock();
+
+ pRegisterStatus->regILPR = UARTn(ui32Module)->ILPR;
+ pRegisterStatus->regIBRD = UARTn(ui32Module)->IBRD;
+ pRegisterStatus->regFBRD = UARTn(ui32Module)->FBRD;
+ pRegisterStatus->regLCRH = UARTn(ui32Module)->LCRH;
+ pRegisterStatus->regCR = UARTn(ui32Module)->CR;
+ pRegisterStatus->regIFLS = UARTn(ui32Module)->IFLS;
+ pRegisterStatus->regIER = UARTn(ui32Module)->IER;
+ pRegisterStatus->bValid = true;
+
+ irq_unlock(key);
+
+ /* Clear all interrupts before sleeping as having a pending UART
+ * interrupt burns power.
+ */
+ UARTn(ui32Module)->IEC = 0xFFFFFFFF;
+
+ /* If the user is going to sleep, certain bits of the CR register
+ * need to be 0 to be low power and have the UART shut off.
+ * Since the user either wishes to retain state which takes place
+ * above or the user does not wish to retain state, it is acceptable
+ * to set the entire CR register to 0.
+ */
+ UARTn(ui32Module)->CR = 0;
+
+ /* Disable power control.*/
+ am_hal_pwrctrl_periph_disable(eUARTPowerModule);
+ return 0;
+ default:
+ return -ENOTSUP;
+ }
+}
+#endif /* CONFIG_PM_DEVICE */
+
/* Problem: writes to power configure register takes some time to take effective.
* Solution: Check device's power status to ensure that register has taken effective.
* Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
@@ -57,7 +167,8 @@
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
#define DEVPWRSTATUS_OFFSET 0x10
#define HCPA_MASK 0x4
-#define AMBIQ_UART_DEFINE(n) \
+#define AMBIQ_UART_DEFINE(n) \
+ PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
static int pwr_on_ambiq_uart_##n(void) \
{ \
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
diff --git a/drivers/serial/uart_ql_usbserialport_s3b.c b/drivers/serial/uart_ql_usbserialport_s3b.c
index 26109f6..48b698e 100644
--- a/drivers/serial/uart_ql_usbserialport_s3b.c
+++ b/drivers/serial/uart_ql_usbserialport_s3b.c
@@ -51,9 +51,10 @@
*/
static void uart_usbserial_poll_out(const struct device *dev, unsigned char c)
{
- /* Wait for room in Tx FIFO */
- while (usbserial_tx_fifo_full())
+ /* Wait for room in Tx FIFO */
+ while (usbserial_tx_fifo_full()) {
;
+ }
usbserial_regs->wdata = c;
}
diff --git a/drivers/serial/uart_renesas_ra8_sci_b.c b/drivers/serial/uart_renesas_ra8_sci_b.c
index 0f7ec05..3db0c32 100644
--- a/drivers/serial/uart_renesas_ra8_sci_b.c
+++ b/drivers/serial/uart_renesas_ra8_sci_b.c
@@ -1038,14 +1038,10 @@
#define UART_RA_SCI_B_DTC_INIT(index) \
do { \
- if (DT_INST_PROP_OR(index, rx_dtc, false)) { \
- uart_ra_sci_b_data_##index.fsp_config.p_transfer_rx = \
- &uart_ra_sci_b_data_##index.rx_transfer; \
- } \
- if (DT_INST_PROP_OR(index, tx_dtc, false)) { \
- uart_ra_sci_b_data_##index.fsp_config.p_transfer_tx = \
- &uart_ra_sci_b_data_##index.tx_transfer; \
- } \
+ uart_ra_sci_b_data_##index.fsp_config.p_transfer_rx = \
+ &uart_ra_sci_b_data_##index.rx_transfer; \
+ uart_ra_sci_b_data_##index.fsp_config.p_transfer_tx = \
+ &uart_ra_sci_b_data_##index.tx_transfer; \
} while (0)
#define UART_RA_SCI_B_ASYNC_INIT(index) \
diff --git a/drivers/serial/uart_renesas_ra_sci.c b/drivers/serial/uart_renesas_ra_sci.c
new file mode 100644
index 0000000..f1327c5
--- /dev/null
+++ b/drivers/serial/uart_renesas_ra_sci.c
@@ -0,0 +1,1212 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_sci_uart
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+#include "r_sci_uart.h"
+#include "r_dtc.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ra_sci_uart);
+
+#define SCI_UART_SSR_FIFO_DR_RDF (R_SCI0_SSR_FIFO_DR_Msk | R_SCI0_SSR_FIFO_RDF_Msk)
+#define SCI_UART_SSR_FIFO_TDFE_TEND (R_SCI0_SSR_FIFO_TDFE_Msk | R_SCI0_SSR_FIFO_TEND_Msk)
+#define SCI_UART_SSR_TDRE_TEND (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk)
+#define SCI_UART_SSR_ERR_MSK (R_SCI0_SSR_ORER_Msk | R_SCI0_SSR_FER_Msk | R_SCI0_SSR_PER_Msk)
+#define SCI_UART_SSR_FIFO_ERR_MSK \
+ (R_SCI0_SSR_FIFO_ORER_Msk | R_SCI0_SSR_FIFO_FER_Msk | R_SCI0_SSR_FIFO_PER_Msk)
+
+#if defined(CONFIG_UART_ASYNC_API)
+void sci_uart_rxi_isr(void);
+void sci_uart_txi_isr(void);
+void sci_uart_tei_isr(void);
+void sci_uart_eri_isr(void);
+#endif
+
+struct uart_ra_sci_config {
+ const struct pinctrl_dev_config *pcfg;
+
+ R_SCI0_Type * const regs;
+};
+
+struct uart_ra_sci_data {
+ const struct device *dev;
+ struct st_sci_uart_instance_ctrl sci;
+ struct uart_config uart_config;
+ struct st_uart_cfg fsp_config;
+ struct st_sci_uart_extended_cfg fsp_config_extend;
+ struct st_baud_setting_t fsp_baud_setting;
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+ uart_irq_callback_user_data_t user_cb;
+ void *user_cb_data;
+ uint32_t ssr;
+#endif
+#if defined(CONFIG_UART_ASYNC_API)
+ uart_callback_t async_user_cb;
+ void *async_user_cb_data;
+
+ struct k_work_delayable rx_timeout_work;
+ size_t rx_timeout;
+ size_t rx_buf_len;
+ size_t rx_buf_offset;
+ size_t rx_buf_cap;
+ uint8_t *rx_buffer;
+ size_t rx_next_buf_cap;
+ uint8_t *rx_next_buf;
+
+ struct st_transfer_instance rx_transfer;
+ struct st_dtc_instance_ctrl rx_transfer_ctrl;
+ struct st_transfer_info rx_transfer_info;
+ struct st_transfer_cfg rx_transfer_cfg;
+ struct st_dtc_extended_cfg rx_transfer_cfg_extend;
+
+ struct k_work_delayable tx_timeout;
+ size_t tx_buf_cap;
+
+ struct st_transfer_instance tx_transfer;
+ struct st_dtc_instance_ctrl tx_transfer_ctrl;
+ struct st_transfer_info tx_transfer_info;
+ struct st_transfer_cfg tx_transfer_cfg;
+ struct st_dtc_extended_cfg tx_transfer_cfg_extend;
+#endif
+};
+
+static int uart_ra_sci_poll_in(const struct device *dev, unsigned char *c)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->SCR_b.RIE) {
+ /* This function cannot be used if async reception was enabled */
+ return -EBUSY;
+ }
+
+ if (IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0
+ ? cfg->regs->FDR_b.R == 0U
+ : cfg->regs->SSR_b.RDRF == 0U) {
+ /* There are no characters available to read. */
+ return -1;
+ }
+
+ /* got a character */
+ *c = IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0
+ ? cfg->regs->FRDRL
+ : cfg->regs->RDR;
+
+ return 0;
+}
+
+static void uart_ra_sci_poll_out(const struct device *dev, unsigned char c)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth > 0) {
+ while (cfg->regs->FDR_b.T > 0x8) {
+ }
+ cfg->regs->FTDRL = c;
+ } else
+#endif
+ {
+ while (cfg->regs->SSR_b.TDRE == 0U) {
+ }
+ cfg->regs->TDR = c;
+ }
+}
+
+static int uart_ra_sci_err_check(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ int errors = 0;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth > 0) {
+ const uint8_t status = cfg->regs->SSR_FIFO;
+ uint8_t ssr_fifo = 0;
+
+ if (status & R_SCI0_SSR_FIFO_ORER_Msk) {
+ errors |= UART_ERROR_OVERRUN;
+ ssr_fifo |= R_SCI0_SSR_FIFO_ORER_Msk;
+ }
+ if (status & R_SCI0_SSR_FIFO_PER_Msk) {
+ errors |= UART_ERROR_PARITY;
+ ssr_fifo |= R_SCI0_SSR_FIFO_PER_Msk;
+ }
+ if (status & R_SCI0_SSR_FIFO_FER_Msk) {
+ errors |= UART_ERROR_FRAMING;
+ ssr_fifo |= R_SCI0_SSR_FIFO_FER_Msk;
+ }
+ cfg->regs->SSR_FIFO &= ~ssr_fifo;
+ } else
+#endif
+ {
+ const uint8_t status = cfg->regs->SSR;
+ uint8_t ssr = 0;
+
+ if (status & R_SCI0_SSR_ORER_Msk) {
+ errors |= UART_ERROR_OVERRUN;
+ ssr |= R_SCI0_SSR_ORER_Msk;
+ }
+ if (status & R_SCI0_SSR_PER_Msk) {
+ errors |= UART_ERROR_PARITY;
+ ssr |= R_SCI0_SSR_PER_Msk;
+ }
+ if (status & R_SCI0_SSR_FER_Msk) {
+ errors |= UART_ERROR_FRAMING;
+ ssr |= R_SCI0_SSR_FER_Msk;
+ }
+ cfg->regs->SSR &= ~ssr;
+ }
+
+ return errors;
+}
+
+static int uart_ra_sci_apply_config(const struct uart_config *config,
+ struct st_uart_cfg *fsp_config,
+ struct st_sci_uart_extended_cfg *fsp_config_extend,
+ struct st_baud_setting_t *fsp_baud_setting)
+{
+ fsp_err_t fsp_err;
+
+ fsp_err = R_SCI_UART_BaudCalculate(config->baudrate, true, 5000, fsp_baud_setting);
+ if (fsp_err != FSP_SUCCESS) {
+ LOG_DBG("drivers: uart: baud calculate error");
+ return -EINVAL;
+ }
+
+ switch (config->parity) {
+ case UART_CFG_PARITY_NONE:
+ fsp_config->parity = UART_PARITY_OFF;
+ break;
+ case UART_CFG_PARITY_ODD:
+ fsp_config->parity = UART_PARITY_ODD;
+ break;
+ case UART_CFG_PARITY_EVEN:
+ fsp_config->parity = UART_PARITY_EVEN;
+ break;
+ case UART_CFG_PARITY_MARK:
+ return -ENOTSUP;
+ case UART_CFG_PARITY_SPACE:
+ return -ENOTSUP;
+ default:
+ return -EINVAL;
+ }
+
+ switch (config->stop_bits) {
+ case UART_CFG_STOP_BITS_0_5:
+ return -ENOTSUP;
+ case UART_CFG_STOP_BITS_1:
+ fsp_config->stop_bits = UART_STOP_BITS_1;
+ break;
+ case UART_CFG_STOP_BITS_1_5:
+ return -ENOTSUP;
+ case UART_CFG_STOP_BITS_2:
+ fsp_config->stop_bits = UART_STOP_BITS_2;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (config->data_bits) {
+ case UART_CFG_DATA_BITS_5:
+ return -ENOTSUP;
+ case UART_CFG_DATA_BITS_6:
+ return -ENOTSUP;
+ case UART_CFG_DATA_BITS_7:
+ fsp_config->data_bits = UART_DATA_BITS_7;
+ break;
+ case UART_CFG_DATA_BITS_8:
+ fsp_config->data_bits = UART_DATA_BITS_8;
+ break;
+ case UART_CFG_DATA_BITS_9:
+ fsp_config->data_bits = UART_DATA_BITS_9;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ fsp_config_extend->rx_fifo_trigger = 0x8;
+#endif
+
+ switch (config->flow_ctrl) {
+ case UART_CFG_FLOW_CTRL_NONE:
+ fsp_config_extend->flow_control = 0;
+ fsp_config_extend->rs485_setting.enable = false;
+ break;
+ case UART_CFG_FLOW_CTRL_RTS_CTS:
+ fsp_config_extend->flow_control = SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS;
+ fsp_config_extend->rs485_setting.enable = false;
+ break;
+ case UART_CFG_FLOW_CTRL_DTR_DSR:
+ return -ENOTSUP;
+ case UART_CFG_FLOW_CTRL_RS485:
+ /* TODO: implement this config */
+ return -ENOTSUP;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+
+static int uart_ra_sci_configure(const struct device *dev, const struct uart_config *config)
+{
+ int err;
+ fsp_err_t fsp_err;
+ struct uart_ra_sci_data *data = dev->data;
+
+ err = uart_ra_sci_apply_config(config, &data->fsp_config, &data->fsp_config_extend,
+ &data->fsp_baud_setting);
+ if (err) {
+ return err;
+ }
+
+ fsp_err = R_SCI_UART_Close(&data->sci);
+ fsp_err |= R_SCI_UART_Open(&data->sci, &data->fsp_config);
+ if (fsp_err != FSP_SUCCESS) {
+ LOG_DBG("drivers: serial: uart configure failed");
+ return -EIO;
+ }
+ memcpy(&data->uart_config, config, sizeof(*config));
+
+ return 0;
+}
+
+static int uart_ra_sci_config_get(const struct device *dev, struct uart_config *cfg)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ memcpy(cfg, &data->uart_config, sizeof(*cfg));
+ return 0;
+}
+
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+static int uart_ra_sci_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ uint8_t num_tx = 0U;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ while ((size - num_tx > 0) && cfg->regs->FDR_b.T < data->sci.fifo_depth) {
+ /* Send a character (8bit , parity none) */
+ cfg->regs->FTDRL = tx_data[num_tx++];
+ }
+ cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND;
+ } else
+#endif
+ {
+ if (size > 0 && cfg->regs->SSR_b.TDRE) {
+ /* Send a character (8bit , parity none) */
+ cfg->regs->TDR = tx_data[num_tx++];
+ }
+ };
+
+ return num_tx;
+}
+
+static int uart_ra_sci_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ uint8_t num_rx = 0U;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ while ((size - num_rx > 0) && cfg->regs->FDR_b.R > 0) {
+ /* Receive a character (8bit , parity none) */
+ rx_data[num_rx++] = cfg->regs->FRDRL;
+ }
+ cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF;
+ } else
+#endif
+ {
+ if (size > 0 && cfg->regs->SSR_b.RDRF) {
+ /* Receive a character (8bit , parity none) */
+ rx_data[num_rx++] = cfg->regs->RDR;
+ }
+ cfg->regs->SSR &= (uint8_t)~R_SCI0_SSR_RDRF_Msk;
+ }
+
+ return num_rx;
+}
+
+static void uart_ra_sci_irq_tx_enable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_TDFE_TEND;
+ } else
+#endif
+ {
+ cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_TDRE_TEND;
+ }
+
+ cfg->regs->SCR |= (R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);
+}
+
+static void uart_ra_sci_irq_tx_disable(const struct device *dev)
+{
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ cfg->regs->SCR &= ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);
+}
+
+static int uart_ra_sci_irq_tx_ready(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ int ret;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_FIFO_TDFE_Msk);
+ } else
+#endif
+ {
+ ret = (cfg->regs->SCR_b.TIE == 1U) && (data->ssr & R_SCI0_SSR_TDRE_Msk);
+ }
+
+ return ret;
+}
+
+static int uart_ra_sci_irq_tx_complete(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ return (cfg->regs->SCR_b.TEIE == 1U) && (data->ssr & BIT(R_SCI0_SSR_TEND_Pos));
+}
+
+static void uart_ra_sci_irq_rx_enable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_DR_RDF);
+ } else
+#endif
+ {
+ cfg->regs->SSR_b.RDRF = 0U;
+ }
+ cfg->regs->SCR_b.RIE = 1U;
+}
+
+static void uart_ra_sci_irq_rx_disable(const struct device *dev)
+{
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ cfg->regs->SCR_b.RIE = 0U;
+}
+
+static int uart_ra_sci_irq_rx_ready(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ int ret;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & SCI_UART_SSR_FIFO_DR_RDF);
+ } else
+#endif
+ {
+ ret = (cfg->regs->SCR_b.RIE == 1U) && (data->ssr & R_SCI0_SSR_RDRF_Msk);
+ }
+
+ return ret;
+}
+
+static void uart_ra_sci_irq_err_enable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ NVIC_EnableIRQ(data->fsp_config.eri_irq);
+}
+
+static void uart_ra_sci_irq_err_disable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ NVIC_DisableIRQ(data->fsp_config.eri_irq);
+}
+
+static int uart_ra_sci_irq_is_pending(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ uint8_t scr;
+ uint8_t ssr;
+ int ret;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ scr = cfg->regs->SCR;
+ ssr = cfg->regs->SSR_FIFO;
+ ret = ((scr & R_SCI0_SCR_TIE_Msk) &&
+ (ssr & (R_SCI0_SSR_FIFO_TEND_Msk | R_SCI0_SSR_FIFO_TDFE_Msk))) ||
+ ((scr & R_SCI0_SCR_RIE_Msk) &&
+ ((ssr & (R_SCI0_SSR_FIFO_RDF_Msk | R_SCI0_SSR_FIFO_DR_Msk |
+ R_SCI0_SSR_FIFO_FER_Msk | R_SCI0_SSR_FIFO_ORER_Msk |
+ R_SCI0_SSR_FIFO_PER_Msk))));
+ } else
+#endif
+ {
+ scr = cfg->regs->SCR;
+ ssr = cfg->regs->SSR;
+ ret = ((scr & R_SCI0_SCR_TIE_Msk) &&
+ (ssr & (R_SCI0_SSR_TEND_Msk | R_SCI0_SSR_TDRE_Msk))) ||
+ ((scr & R_SCI0_SCR_RIE_Msk) &&
+ (ssr & (R_SCI0_SSR_RDRF_Msk | R_SCI0_SSR_PER_Msk | R_SCI0_SSR_FER_Msk |
+ R_SCI0_SSR_ORER_Msk)));
+ }
+
+ return ret;
+}
+
+static int uart_ra_sci_irq_update(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ data->ssr = cfg->regs->SSR_FIFO;
+ uint8_t ssr = data->ssr ^ (R_SCI0_SSR_FIFO_ORER_Msk | R_SCI0_SSR_FIFO_FER_Msk |
+ R_SCI0_SSR_FIFO_PER_Msk);
+ cfg->regs->SSR_FIFO &= ssr;
+ } else
+#endif
+ {
+ data->ssr = cfg->regs->SSR;
+ uint8_t ssr =
+ data->ssr ^ (R_SCI0_SSR_ORER_Msk | R_SCI0_SSR_FER_Msk | R_SCI0_SSR_PER_Msk);
+ cfg->regs->SSR_FIFO &= ssr;
+ }
+
+ return 1;
+}
+
+static void uart_ra_sci_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+ void *cb_data)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ data->user_cb = cb;
+ data->user_cb_data = cb_data;
+
+#if CONFIG_UART_EXCLUSIVE_API_CALLBACKS
+ data->async_user_cb = NULL;
+ data->async_user_cb_data = NULL;
+#endif
+}
+
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#ifdef CONFIG_UART_ASYNC_API
+
+static int fsp_err_to_errno(fsp_err_t fsp_err)
+{
+ switch (fsp_err) {
+ case FSP_ERR_INVALID_ARGUMENT:
+ return -EINVAL;
+ case FSP_ERR_NOT_OPEN:
+ return -EIO;
+ case FSP_ERR_IN_USE:
+ return -EBUSY;
+ case FSP_ERR_UNSUPPORTED:
+ return -ENOTSUP;
+ case 0:
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int uart_ra_sci_async_callback_set(const struct device *dev, uart_callback_t cb,
+ void *cb_data)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ data->async_user_cb = cb;
+ data->async_user_cb_data = cb_data;
+
+#if CONFIG_UART_EXCLUSIVE_API_CALLBACKS
+ data->user_cb = NULL;
+ data->user_cb_data = NULL;
+#endif
+ return 0;
+}
+
+static int uart_ra_sci_async_tx(const struct device *dev, const uint8_t *buf, size_t len,
+ int32_t timeout)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ int err;
+
+ err = fsp_err_to_errno(R_SCI_UART_Write(&data->sci, buf, len));
+ if (err) {
+ return err;
+ }
+ data->tx_buf_cap = len;
+ if (timeout != SYS_FOREVER_US && timeout != 0) {
+ k_work_reschedule(&data->tx_timeout, Z_TIMEOUT_US(timeout));
+ }
+
+ return 0;
+}
+
+static inline void async_user_callback(const struct device *dev, struct uart_event *event)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ if (data->async_user_cb) {
+ data->async_user_cb(dev, event, data->async_user_cb_data);
+ }
+}
+
+static inline void async_rx_release_buf(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ struct uart_event event = {
+ .type = UART_RX_BUF_RELEASED,
+ .data.rx.buf = (uint8_t *)data->rx_buffer,
+ };
+ async_user_callback(dev, &event);
+ data->rx_buffer = NULL;
+ data->rx_buf_offset = 0;
+ data->rx_buf_len = 0;
+ data->rx_buf_cap = 0;
+}
+
+static inline void async_rx_release_next_buf(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ struct uart_event event = {
+ .type = UART_RX_BUF_RELEASED,
+ .data.rx.buf = (uint8_t *)data->rx_next_buf,
+ };
+ async_user_callback(dev, &event);
+ data->rx_next_buf = NULL;
+}
+
+static inline void async_rx_req_buf(const struct device *dev)
+{
+ struct uart_event event = {
+ .type = UART_RX_BUF_REQUEST,
+ };
+
+ async_user_callback(dev, &event);
+}
+
+static inline void async_rx_disable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ struct uart_event event = {
+ .type = UART_RX_DISABLED,
+ };
+ async_user_callback(dev, &event);
+
+ /* Disable the RXI request and clear the status flag to be ready for the next reception */
+ cfg->regs->SCR_b.RIE = 0;
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth != 0) {
+ cfg->regs->SSR_FIFO &= (uint8_t)~SCI_UART_SSR_FIFO_DR_RDF;
+ } else
+#endif
+ {
+ cfg->regs->SSR_b.RDRF = 0;
+ }
+}
+
+static inline void async_rx_ready(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ if (!data->rx_buf_len) {
+ return;
+ }
+
+ struct uart_event event = {
+ .type = UART_RX_RDY,
+ .data.rx.buf = (uint8_t *)data->rx_buffer,
+ .data.rx.offset = data->rx_buf_offset,
+ .data.rx.len = data->rx_buf_len,
+ };
+ async_user_callback(data->dev, &event);
+ data->rx_buf_offset += data->rx_buf_len;
+ data->rx_buf_len = 0;
+}
+
+static inline void disable_tx(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ /* Transmit interrupts must be disabled to start with. */
+ cfg->regs->SCR &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk);
+
+ /*
+ * Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND
+ * is 0 causes SCI peripheral to work abnormally.
+ */
+ while (IS_ENABLED(CONFIG_UART_RA_SCI_UART_FIFO_ENABLE) && data->sci.fifo_depth
+ ? cfg->regs->SSR_FIFO_b.TEND != 1U
+ : cfg->regs->SSR_b.TEND != 1U) {
+ }
+
+ cfg->regs->SCR_b.TE = 0;
+}
+
+static inline void enable_tx(const struct device *dev)
+{
+ const struct uart_ra_sci_config *cfg = dev->config;
+
+ cfg->regs->SCR_b.TE = 1;
+}
+
+static int uart_ra_sci_async_tx_abort(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ int err = 0;
+
+ if (!data->sci.p_tx_src) {
+ return -EFAULT;
+ }
+
+ disable_tx(dev);
+
+ if (FSP_SUCCESS != R_SCI_UART_Abort(&data->sci, UART_DIR_TX)) {
+ LOG_DBG("drivers: serial: uart abort tx failed");
+ err = -EIO;
+ goto unlock;
+ }
+ transfer_properties_t tx_properties = {0};
+
+ if (FSP_SUCCESS != R_DTC_InfoGet(data->tx_transfer.p_ctrl, &tx_properties)) {
+ LOG_DBG("drivers: serial: uart abort tx failed");
+ err = -EIO;
+ goto unlock;
+ }
+ struct uart_event event = {
+ .type = UART_TX_ABORTED,
+ .data.tx.buf = (uint8_t *)data->sci.p_tx_src,
+ .data.tx.len = data->tx_buf_cap - tx_properties.transfer_length_remaining,
+ };
+ async_user_callback(dev, &event);
+ k_work_cancel_delayable(&data->tx_timeout);
+
+unlock:
+ enable_tx(dev);
+ return err;
+}
+
+static int uart_ra_sci_async_rx_enable(const struct device *dev, uint8_t *buf, size_t len,
+ int32_t timeout)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ const struct uart_ra_sci_config *cfg = dev->config;
+ int err = 0;
+ unsigned int key = irq_lock();
+
+ if (data->rx_buffer) {
+ err = -EAGAIN;
+ goto unlock;
+ }
+
+#if CONFIG_UART_RA_SCI_UART_FIFO_ENABLE
+ if (data->sci.fifo_depth) {
+ cfg->regs->SSR_FIFO &= (uint8_t) ~(SCI_UART_SSR_FIFO_ERR_MSK);
+ } else
+#endif
+ {
+ cfg->regs->SSR = (uint8_t)~SCI_UART_SSR_ERR_MSK;
+ }
+
+ err = fsp_err_to_errno(R_SCI_UART_Read(&data->sci, buf, len));
+ if (err) {
+ goto unlock;
+ }
+
+ data->rx_timeout = timeout;
+ data->rx_buffer = buf;
+ data->rx_buf_cap = len;
+ data->rx_buf_len = 0;
+ data->rx_buf_offset = 0;
+
+ /* Call buffer request user callback */
+ async_rx_req_buf(dev);
+ cfg->regs->SCR_b.RIE = 1;
+
+unlock:
+ irq_unlock(key);
+ return err;
+}
+
+static int uart_ra_sci_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ data->rx_next_buf = buf;
+ data->rx_next_buf_cap = len;
+
+ return 0;
+}
+
+static int uart_ra_sci_async_rx_disable(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ uint32_t remaining_byte = 0;
+ int err = 0;
+ unsigned int key = irq_lock();
+
+ if (!data->rx_buffer) {
+ err = -EAGAIN;
+ goto unlock;
+ }
+
+ k_work_cancel_delayable(&data->rx_timeout_work);
+ if (FSP_SUCCESS != R_SCI_UART_ReadStop(&data->sci, &remaining_byte)) {
+ LOG_DBG("drivers: serial: uart stop reading failed");
+ err = -EIO;
+ goto unlock;
+ }
+
+ async_rx_ready(dev);
+ async_rx_release_buf(dev);
+ async_rx_release_next_buf(dev);
+ async_rx_disable(dev);
+
+unlock:
+ irq_unlock(key);
+ return err;
+}
+
+static inline void async_evt_rx_err(const struct device *dev, enum uart_rx_stop_reason reason)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ k_work_cancel_delayable(&data->rx_timeout_work);
+ struct uart_event event = {
+ .type = UART_RX_STOPPED,
+ .data.rx_stop.reason = reason,
+ .data.rx_stop.data.buf = (uint8_t *)data->sci.p_rx_dest,
+ .data.rx_stop.data.offset = 0,
+ .data.rx_stop.data.len =
+ data->rx_buf_cap - data->rx_buf_offset - data->sci.rx_dest_bytes,
+ };
+ async_user_callback(dev, &event);
+}
+
+static inline void async_evt_rx_complete(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+ unsigned int key = irq_lock();
+
+ async_rx_ready(dev);
+ async_rx_release_buf(dev);
+ if (data->rx_next_buf) {
+ data->rx_buffer = data->rx_next_buf;
+ data->rx_buf_offset = 0;
+ data->rx_buf_cap = data->rx_next_buf_cap;
+ data->rx_next_buf = NULL;
+ R_SCI_UART_Read(&data->sci, data->rx_buffer, data->rx_buf_cap);
+ async_rx_req_buf(dev);
+ } else {
+ async_rx_disable(dev);
+ }
+ irq_unlock(key);
+}
+
+static inline void async_evt_tx_done(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+
+ k_work_cancel_delayable(&data->tx_timeout);
+ struct uart_event event = {
+ .type = UART_TX_DONE,
+ .data.tx.buf = (uint8_t *)data->sci.p_tx_src,
+ .data.tx.len = data->tx_buf_cap,
+ };
+ async_user_callback(dev, &event);
+}
+
+static void uart_ra_sci_callback_adapter(struct st_uart_callback_arg *fsp_args)
+{
+ const struct device *dev = fsp_args->p_context;
+
+ switch (fsp_args->event) {
+ case UART_EVENT_TX_COMPLETE:
+ return async_evt_tx_done(dev);
+ case UART_EVENT_RX_COMPLETE:
+ async_evt_rx_complete(dev);
+ case UART_EVENT_ERR_PARITY:
+ return async_evt_rx_err(dev, UART_ERROR_PARITY);
+ case UART_EVENT_ERR_FRAMING:
+ return async_evt_rx_err(dev, UART_ERROR_FRAMING);
+ case UART_EVENT_ERR_OVERFLOW:
+ return async_evt_rx_err(dev, UART_ERROR_OVERRUN);
+ case UART_EVENT_BREAK_DETECT:
+ return async_evt_rx_err(dev, UART_BREAK);
+ case UART_EVENT_TX_DATA_EMPTY:
+ case UART_EVENT_RX_CHAR:
+ break;
+ }
+}
+
+static void uart_ra_sci_rx_timeout_handler(struct k_work *work)
+{
+ struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+ struct uart_ra_sci_data *data =
+ CONTAINER_OF(dwork, struct uart_ra_sci_data, rx_timeout_work);
+ unsigned int key = irq_lock();
+
+ async_rx_ready(data->dev);
+ irq_unlock(key);
+}
+
+static void uart_ra_sci_tx_timeout_handler(struct k_work *work)
+{
+ struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+ struct uart_ra_sci_data *data = CONTAINER_OF(dwork, struct uart_ra_sci_data, tx_timeout);
+
+ uart_ra_sci_async_tx_abort(data->dev);
+}
+
+#endif /* CONFIG_UART_ASYNC_API */
+
+static const struct uart_driver_api uart_ra_sci_driver_api = {
+ .poll_in = uart_ra_sci_poll_in,
+ .poll_out = uart_ra_sci_poll_out,
+ .err_check = uart_ra_sci_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+ .configure = uart_ra_sci_configure,
+ .config_get = uart_ra_sci_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+ .fifo_fill = uart_ra_sci_fifo_fill,
+ .fifo_read = uart_ra_sci_fifo_read,
+ .irq_tx_enable = uart_ra_sci_irq_tx_enable,
+ .irq_tx_disable = uart_ra_sci_irq_tx_disable,
+ .irq_tx_ready = uart_ra_sci_irq_tx_ready,
+ .irq_rx_enable = uart_ra_sci_irq_rx_enable,
+ .irq_rx_disable = uart_ra_sci_irq_rx_disable,
+ .irq_tx_complete = uart_ra_sci_irq_tx_complete,
+ .irq_rx_ready = uart_ra_sci_irq_rx_ready,
+ .irq_err_enable = uart_ra_sci_irq_err_enable,
+ .irq_err_disable = uart_ra_sci_irq_err_disable,
+ .irq_is_pending = uart_ra_sci_irq_is_pending,
+ .irq_update = uart_ra_sci_irq_update,
+ .irq_callback_set = uart_ra_sci_irq_callback_set,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+#if CONFIG_UART_ASYNC_API
+ .callback_set = uart_ra_sci_async_callback_set,
+ .tx = uart_ra_sci_async_tx,
+ .tx_abort = uart_ra_sci_async_tx_abort,
+ .rx_enable = uart_ra_sci_async_rx_enable,
+ .rx_buf_rsp = uart_ra_sci_async_rx_buf_rsp,
+ .rx_disable = uart_ra_sci_async_rx_disable,
+#endif /* CONFIG_UART_ASYNC_API */
+};
+
+static int uart_ra_sci_init(const struct device *dev)
+{
+ const struct uart_ra_sci_config *config = dev->config;
+ struct uart_ra_sci_data *data = dev->data;
+ int ret;
+ fsp_err_t fsp_err;
+
+ /* Configure dt provided device signals when available */
+ ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* Setup fsp sci_uart setting */
+ ret = uart_ra_sci_apply_config(&data->uart_config, &data->fsp_config,
+ &data->fsp_config_extend, &data->fsp_baud_setting);
+ if (ret != 0) {
+ return ret;
+ }
+
+ data->fsp_config_extend.p_baud_setting = &data->fsp_baud_setting;
+#if defined(CONFIG_UART_ASYNC_API)
+ data->fsp_config.p_callback = uart_ra_sci_callback_adapter;
+ data->fsp_config.p_context = dev;
+ k_work_init_delayable(&data->tx_timeout, uart_ra_sci_tx_timeout_handler);
+ k_work_init_delayable(&data->rx_timeout_work, uart_ra_sci_rx_timeout_handler);
+#endif /* defined(CONFIG_UART_ASYNC_API) */
+ data->fsp_config.p_extend = &data->fsp_config_extend;
+
+ fsp_err = R_SCI_UART_Open(&data->sci, &data->fsp_config);
+ if (fsp_err != FSP_SUCCESS) {
+ LOG_DBG("drivers: uart: initialize failed");
+ return -EIO;
+ }
+ irq_disable(data->fsp_config.eri_irq);
+ return 0;
+}
+
+#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
+static void uart_ra_sci_rxi_isr(const struct device *dev)
+{
+ struct uart_ra_sci_data *data = dev->data;
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+ if (data->user_cb != NULL) {
+ data->user_cb(dev, data->user_cb_data);
+ goto out;
+ }
+#endif
+
+#if defined(CONFIG_UART_ASYNC_API)
+ if (data->rx_timeout != SYS_FOREVER_US && data->rx_timeout != 0) {
+ k_work_reschedule(&data->rx_timeout_work, Z_TIMEOUT_US(data->rx_timeout));
+ }
+ data->rx_buf_len++;
+ if (data->rx_buf_len + data->rx_buf_offset == data->rx_buf_cap) {
+ sci_uart_rxi_isr();
+ } else {
+ goto out;
+ }
+#endif
+out:
+ R_ICU->IELSR_b[data->fsp_config.rxi_irq].IR = 0U;
+}
+
+static void uart_ra_sci_txi_isr(const struct device *dev)
+{
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+ struct uart_ra_sci_data *data = dev->data;
+
+ if (data->user_cb != NULL) {
+ data->user_cb(dev, data->user_cb_data);
+ R_ICU->IELSR_b[data->fsp_config.txi_irq].IR = 0U;
+ return;
+ }
+#endif
+
+#if defined(CONFIG_UART_ASYNC_API)
+ sci_uart_txi_isr();
+#endif
+}
+
+static void uart_ra_sci_tei_isr(const struct device *dev)
+{
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+ struct uart_ra_sci_data *data = dev->data;
+
+ if (data->user_cb != NULL) {
+ data->user_cb(dev, data->user_cb_data);
+ R_ICU->IELSR_b[data->fsp_config.tei_irq].IR = 0U;
+ return;
+ }
+#endif
+
+#if defined(CONFIG_UART_ASYNC_API)
+ sci_uart_tei_isr();
+#endif
+}
+
+static void uart_ra_sci_eri_isr(const struct device *dev)
+{
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
+ struct uart_ra_sci_data *data = dev->data;
+
+ if (data->user_cb != NULL) {
+ data->user_cb(dev, data->user_cb_data);
+ R_ICU->IELSR_b[data->fsp_config.eri_irq].IR = 0U;
+ return;
+ }
+#endif
+
+#if defined(CONFIG_UART_ASYNC_API)
+ sci_uart_eri_isr();
+#endif
+}
+#endif
+
+#define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI
+#define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI
+#define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI
+#define _ELC_EVENT_SCI_ERI(channel) ELC_EVENT_SCI##channel##_ERI
+
+#define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel)
+#define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel)
+#define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel)
+#define ELC_EVENT_SCI_ERI(channel) _ELC_EVENT_SCI_ERI(channel)
+
+#if CONFIG_UART_ASYNC_API
+#define UART_RA_SCI_ASYNC_INIT(index) \
+ .rx_transfer_info = \
+ { \
+ .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, \
+ .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, \
+ .transfer_settings_word_b.irq = TRANSFER_IRQ_EACH, \
+ .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, \
+ .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED, \
+ .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, \
+ .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, \
+ .p_dest = (void *)NULL, \
+ .p_src = (void const *)NULL, \
+ .num_blocks = 0, \
+ .length = 0, \
+ }, \
+ .rx_transfer_cfg_extend = {.activation_source = \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)}, \
+ .rx_transfer_cfg = \
+ { \
+ .p_info = &uart_ra_sci_data_##index.rx_transfer_info, \
+ .p_extend = &uart_ra_sci_data_##index.rx_transfer_cfg_extend, \
+ }, \
+ .rx_transfer = \
+ { \
+ .p_ctrl = &uart_ra_sci_data_##index.rx_transfer_ctrl, \
+ .p_cfg = &uart_ra_sci_data_##index.rx_transfer_cfg, \
+ .p_api = &g_transfer_on_dtc, \
+ }, \
+ .tx_transfer_info = \
+ { \
+ .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, \
+ .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, \
+ .transfer_settings_word_b.irq = TRANSFER_IRQ_END, \
+ .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, \
+ .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, \
+ .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, \
+ .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, \
+ .p_dest = (void *)NULL, \
+ .p_src = (void const *)NULL, \
+ .num_blocks = 0, \
+ .length = 0, \
+ }, \
+ .tx_transfer_cfg_extend = {.activation_source = \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)}, \
+ .tx_transfer_cfg = \
+ { \
+ .p_info = &uart_ra_sci_data_##index.tx_transfer_info, \
+ .p_extend = &uart_ra_sci_data_##index.tx_transfer_cfg_extend, \
+ }, \
+ .tx_transfer = { \
+ .p_ctrl = &uart_ra_sci_data_##index.tx_transfer_ctrl, \
+ .p_cfg = &uart_ra_sci_data_##index.tx_transfer_cfg, \
+ .p_api = &g_transfer_on_dtc, \
+ },
+
+#define UART_RA_SCI_DTC_INIT(index) \
+ { \
+ uart_ra_sci_data_##index.fsp_config.p_transfer_rx = \
+ &uart_ra_sci_data_##index.rx_transfer; \
+ uart_ra_sci_data_##index.fsp_config.p_transfer_tx = \
+ &uart_ra_sci_data_##index.tx_transfer; \
+ }
+
+#else
+#define UART_RA_SCI_ASYNC_INIT(index)
+#define UART_RA_SCI_DTC_INIT(index)
+#endif
+
+#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
+#define UART_RA_SCI_IRQ_INIT(index) \
+ { \
+ R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] = \
+ ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] = \
+ ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] = \
+ ELC_EVENT_SCI_TEI(DT_INST_PROP(index, channel)); \
+ R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] = \
+ ELC_EVENT_SCI_ERI(DT_INST_PROP(index, channel)); \
+ \
+ IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \
+ uart_ra_sci_rxi_isr, DEVICE_DT_INST_GET(index), 0); \
+ IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \
+ uart_ra_sci_txi_isr, DEVICE_DT_INST_GET(index), 0); \
+ IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \
+ uart_ra_sci_tei_isr, DEVICE_DT_INST_GET(index), 0); \
+ IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \
+ DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, priority), \
+ uart_ra_sci_eri_isr, DEVICE_DT_INST_GET(index), 0); \
+ \
+ irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)); \
+ irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)); \
+ irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)); \
+ }
+#else
+#define UART_RA_SCI_IRQ_INIT(index)
+#endif
+
+#define UART_RA_SCI_INIT(index) \
+ PINCTRL_DT_DEFINE(DT_INST_PARENT(index)); \
+ static const struct uart_ra_sci_config uart_ra_sci_config_##index = { \
+ .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(index)), \
+ .regs = (R_SCI0_Type *)DT_REG_ADDR(DT_INST_PARENT(index)), \
+ }; \
+ \
+ static struct uart_ra_sci_data uart_ra_sci_data_##index = { \
+ .uart_config = \
+ { \
+ .baudrate = DT_INST_PROP(index, current_speed), \
+ .parity = UART_CFG_PARITY_NONE, \
+ .stop_bits = UART_CFG_STOP_BITS_1, \
+ .data_bits = UART_CFG_DATA_BITS_8, \
+ .flow_ctrl = COND_CODE_1(DT_NODE_HAS_PROP(idx, hw_flow_control), \
+ (UART_CFG_FLOW_CTRL_RTS_CTS), \
+ (UART_CFG_FLOW_CTRL_NONE)), \
+ }, \
+ .fsp_config = \
+ { \
+ .channel = DT_INST_PROP(index, channel), \
+ .rxi_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \
+ .rxi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
+ .txi_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \
+ .txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
+ .tei_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \
+ .tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \
+ .eri_ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, priority), \
+ .eri_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \
+ }, \
+ .fsp_config_extend = {}, \
+ .fsp_baud_setting = {}, \
+ .dev = DEVICE_DT_INST_GET(index), \
+ UART_RA_SCI_ASYNC_INIT(index)}; \
+ \
+ static int uart_ra_sci_init##index(const struct device *dev) \
+ { \
+ UART_RA_SCI_IRQ_INIT(index); \
+ UART_RA_SCI_DTC_INIT(index); \
+ int err = uart_ra_sci_init(dev); \
+ if (err != 0) { \
+ return err; \
+ } \
+ return 0; \
+ } \
+ DEVICE_DT_INST_DEFINE(index, uart_ra_sci_init##index, NULL, &uart_ra_sci_data_##index, \
+ &uart_ra_sci_config_##index, PRE_KERNEL_1, \
+ CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_sci_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_RA_SCI_INIT)
diff --git a/drivers/spi/Kconfig.max32 b/drivers/spi/Kconfig.max32
index ca75a37..3440739 100644
--- a/drivers/spi/Kconfig.max32
+++ b/drivers/spi/Kconfig.max32
@@ -5,6 +5,7 @@
bool "MAX32 MCU SPI controller driver"
default y
depends on DT_HAS_ADI_MAX32_SPI_ENABLED
+ select PINCTRL
help
Enable SPI support on the MAX32 family of processors.
diff --git a/drivers/spi/spi_ambiq.c b/drivers/spi/spi_ambiq.c
index b998b49..384366c 100644
--- a/drivers/spi/spi_ambiq.c
+++ b/drivers/spi/spi_ambiq.c
@@ -13,6 +13,10 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/pm/device_runtime.h>
+
#include <stdlib.h>
#include <errno.h>
#include "spi_context.h"
@@ -344,6 +348,12 @@
return 0;
}
+ ret = pm_device_runtime_get(dev);
+
+ if (ret < 0) {
+ LOG_ERR("pm_device_runtime_get failed: %d", ret);
+ }
+
/* context setup */
spi_context_lock(&data->ctx, false, NULL, NULL, config);
@@ -360,6 +370,15 @@
spi_context_release(&data->ctx, ret);
+ /* Use async put to avoid useless device suspension/resumption
+ * when doing consecutive transmission.
+ */
+ ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+ if (ret < 0) {
+ LOG_ERR("pm_device_runtime_put failed: %d", ret);
+ }
+
return ret;
}
@@ -421,6 +440,35 @@
return ret;
}
+#ifdef CONFIG_PM_DEVICE
+static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
+{
+ struct spi_ambiq_data *data = dev->data;
+ uint32_t ret;
+ am_hal_sysctrl_power_state_e status;
+
+ switch (action) {
+ case PM_DEVICE_ACTION_RESUME:
+ status = AM_HAL_SYSCTRL_WAKE;
+ break;
+ case PM_DEVICE_ACTION_SUSPEND:
+ status = AM_HAL_SYSCTRL_DEEPSLEEP;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ ret = am_hal_iom_power_ctrl(data->iom_handler, status, true);
+
+ if (ret != AM_HAL_STATUS_SUCCESS) {
+ LOG_ERR("am_hal_iom_power_ctrl failed: %d", ret);
+ return -EPERM;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_PM_DEVICE */
+
#define AMBIQ_SPI_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static int pwr_on_ambiq_spi_##n(void) \
@@ -448,7 +496,9 @@
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.irq_config_func = spi_irq_config_func_##n, \
.pwr_func = pwr_on_ambiq_spi_##n}; \
- DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, NULL, &spi_ambiq_data##n, &spi_ambiq_config##n, \
- POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_ambiq_driver_api);
+ PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action); \
+ DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
+ &spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
+ &spi_ambiq_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPI_INIT)
diff --git a/drivers/spi/spi_bitbang.c b/drivers/spi/spi_bitbang.c
index 15ab576..bffe937 100644
--- a/drivers/spi/spi_bitbang.c
+++ b/drivers/spi/spi_bitbang.c
@@ -231,7 +231,8 @@
const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
- struct k_poll_signal *async)
+ spi_callback_t cb,
+ void *userdata)
{
return -ENOTSUP;
}
diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c
index d733cef..408f1af 100644
--- a/drivers/spi/spi_esp32_spim.c
+++ b/drivers/spi/spi_esp32_spim.c
@@ -244,11 +244,17 @@
spi_ll_disable_int(cfg->spi);
spi_ll_clear_int_stat(cfg->spi);
- esp_intr_alloc(cfg->irq_source,
- 0,
+ err = esp_intr_alloc(cfg->irq_source,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags) | ESP_INTR_FLAG_IRAM,
(ISR_HANDLER)spi_esp32_isr,
(void *)dev,
NULL);
+
+ if (err != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", err);
+ return err;
+ }
#endif
err = spi_context_cs_configure_all(&data->ctx);
@@ -525,7 +531,9 @@
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.duty_cycle = 0, \
.input_delay_ns = 0, \
- .irq_source = DT_INST_IRQN(idx), \
+ .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
+ .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
+ .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
diff --git a/drivers/spi/spi_esp32_spim.h b/drivers/spi/spi_esp32_spim.h
index 03da08f..414e31b 100644
--- a/drivers/spi/spi_esp32_spim.h
+++ b/drivers/spi/spi_esp32_spim.h
@@ -30,6 +30,8 @@
int duty_cycle;
int input_delay_ns;
int irq_source;
+ int irq_priority;
+ int irq_flags;
const struct pinctrl_dev_config *pcfg;
clock_control_subsys_t clock_subsys;
bool use_iomux;
diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c
index b822d5e..4cbf21d 100644
--- a/drivers/spi/spi_mcux_lpspi.c
+++ b/drivers/spi/spi_mcux_lpspi.c
@@ -753,23 +753,23 @@
switch (sqe->op) {
case RTIO_OP_RX:
transfer.txData = NULL;
- transfer.rxData = sqe->buf;
- transfer.dataSize = sqe->buf_len;
+ transfer.rxData = sqe->rx.buf;
+ transfer.dataSize = sqe->rx.buf_len;
break;
case RTIO_OP_TX:
transfer.rxData = NULL;
- transfer.txData = sqe->buf;
- transfer.dataSize = sqe->buf_len;
+ transfer.txData = sqe->tx.buf;
+ transfer.dataSize = sqe->tx.buf_len;
break;
case RTIO_OP_TINY_TX:
transfer.rxData = NULL;
- transfer.txData = sqe->tiny_buf;
- transfer.dataSize = sqe->tiny_buf_len;
+ transfer.txData = sqe->tiny_tx.buf;
+ transfer.dataSize = sqe->tiny_tx.buf_len;
break;
case RTIO_OP_TXRX:
- transfer.txData = sqe->tx_buf;
- transfer.rxData = sqe->rx_buf;
- transfer.dataSize = sqe->txrx_buf_len;
+ transfer.txData = sqe->txrx.tx_buf;
+ transfer.rxData = sqe->txrx.rx_buf;
+ transfer.dataSize = sqe->txrx.buf_len;
break;
default:
LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
diff --git a/drivers/spi/spi_nxp_s32.c b/drivers/spi/spi_nxp_s32.c
index 60ef0d4..e7cda40 100644
--- a/drivers/spi/spi_nxp_s32.c
+++ b/drivers/spi/spi_nxp_s32.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,8 +10,6 @@
#include <zephyr/drivers/pinctrl.h>
#include "spi_nxp_s32.h"
-extern Spi_Ip_StateStructureType * Spi_Ip_apxStateStructureArray[SPI_INSTANCE_COUNT];
-
static bool spi_nxp_s32_last_packet(struct spi_nxp_s32_data *data)
{
struct spi_context *ctx = &data->ctx;
@@ -45,6 +43,7 @@
Spi_Ip_StatusType status;
Spi_Ip_CallbackType data_cb;
+ Spi_Ip_TransferAdjustmentType param;
#ifdef CONFIG_NXP_S32_SPI_INTERRUPT
data_cb = config->cb;
@@ -56,12 +55,9 @@
data->transfer_len = MIN(data->transfer_len,
SPI_NXP_S32_MAX_BYTES_PER_PACKAGE(data->bytes_per_frame));
- /*
- * Keep CS signal asserted until the last package, there is no other way
- * than directly intervening to internal state of low level driver
- */
- Spi_Ip_apxStateStructureArray[config->spi_hw_cfg->Instance]->KeepCs =
- !spi_nxp_s32_last_packet(data);
+ param.KeepCs = !spi_nxp_s32_last_packet(data);
+ param.DeviceParams = NULL;
+ Spi_Ip_UpdateTransferParam(&data->transfer_cfg, ¶m);
status = Spi_Ip_AsyncTransmit(&data->transfer_cfg, (uint8_t *)data->ctx.tx_buf,
data->ctx.rx_buf, data->transfer_len, data_cb);
diff --git a/drivers/spi/spi_pl022.c b/drivers/spi/spi_pl022.c
index 817a826..0e4c1f9 100644
--- a/drivers/spi/spi_pl022.c
+++ b/drivers/spi/spi_pl022.c
@@ -741,8 +741,9 @@
data->rx_count = 0;
/* Ensure writable */
- while (!SSP_TX_FIFO_EMPTY(cfg->reg))
+ while (!SSP_TX_FIFO_EMPTY(cfg->reg)) {
;
+ }
/* Drain RX FIFO */
while (SSP_RX_FIFO_NOT_EMPTY(cfg->reg))
SSP_READ_REG(SSP_DR(cfg->reg));
@@ -762,8 +763,9 @@
fifo_cnt++;
}
while (data->rx_count < chunk_len && fifo_cnt > 0) {
- if (!SSP_RX_FIFO_NOT_EMPTY(cfg->reg))
+ if (!SSP_RX_FIFO_NOT_EMPTY(cfg->reg)) {
continue;
+ }
txrx = SSP_READ_REG(SSP_DR(cfg->reg));
diff --git a/drivers/spi/spi_sam.c b/drivers/spi/spi_sam.c
index fb42cb6..fc8e296 100644
--- a/drivers/spi/spi_sam.c
+++ b/drivers/spi/spi_sam.c
@@ -657,16 +657,17 @@
switch (sqe->op) {
case RTIO_OP_RX:
- ret = spi_sam_rx(dev, cfg->regs, sqe->buf, sqe->buf_len);
+ ret = spi_sam_rx(dev, cfg->regs, sqe->rx.buf, sqe->rx.buf_len);
break;
case RTIO_OP_TX:
- ret = spi_sam_tx(dev, cfg->regs, sqe->buf, sqe->buf_len);
+ ret = spi_sam_tx(dev, cfg->regs, sqe->tx.buf, sqe->tx.buf_len);
break;
case RTIO_OP_TINY_TX:
- ret = spi_sam_tx(dev, cfg->regs, sqe->tiny_buf, sqe->tiny_buf_len);
+ ret = spi_sam_tx(dev, cfg->regs, sqe->tiny_tx.buf, sqe->tiny_tx.buf_len);
break;
case RTIO_OP_TXRX:
- ret = spi_sam_txrx(dev, cfg->regs, sqe->tx_buf, sqe->rx_buf, sqe->txrx_buf_len);
+ ret = spi_sam_txrx(dev, cfg->regs, sqe->txrx.tx_buf, sqe->txrx.rx_buf,
+ sqe->txrx.buf_len);
break;
default:
LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
diff --git a/drivers/timer/Kconfig.esp32 b/drivers/timer/Kconfig.esp32
index 4dd2892..304ad12 100644
--- a/drivers/timer/Kconfig.esp32
+++ b/drivers/timer/Kconfig.esp32
@@ -5,7 +5,7 @@
config ESP32_SYS_TIMER
bool "ESP32 sys-timer support (ESP32Cx series)"
- depends on SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
+ depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
default y
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c
index b5f859a..1a3183a 100644
--- a/drivers/timer/cortex_m_systick.c
+++ b/drivers/timer/cortex_m_systick.c
@@ -31,16 +31,14 @@
*/
#define MIN_DELAY MAX(1024U, ((uint32_t)CYC_PER_TICK/16U))
-#define TICKLESS (IS_ENABLED(CONFIG_TICKLESS_KERNEL))
-
static struct k_spinlock lock;
static uint32_t last_load;
#ifdef CONFIG_CORTEX_M_SYSTICK_64BIT_CYCLE_COUNTER
-#define cycle_t uint64_t
+typedef uint64_t cycle_t;
#else
-#define cycle_t uint32_t
+typedef uint32_t cycle_t;
#endif
/*
@@ -164,10 +162,13 @@
return (last_load - val2) + overflow_cyc;
}
-/* Callout out of platform assembly, not hooked via IRQ_CONNECT... */
-void sys_clock_isr(void *arg)
+/* sys_clock_isr is calling directly from the platform's vectors table.
+ * However using ISR_DIRECT_DECLARE() is not so suitable due to possible
+ * tracing overflow, so here is a stripped down version of it.
+ */
+ARCH_ISR_DIAG_OFF
+__attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
{
- ARG_UNUSED(arg);
uint32_t dcycles;
uint32_t dticks;
@@ -187,13 +188,14 @@
* sys_clock_idle_exit function.
*/
if (timeout_idle) {
+ ISR_DIRECT_PM();
z_arm_int_exit();
return;
}
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
- if (TICKLESS) {
+ if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* In TICKLESS mode, the SysTick.LOAD is re-programmed
* in sys_clock_set_timeout(), followed by resetting of
* the counter (VAL = 0).
@@ -213,8 +215,11 @@
} else {
sys_clock_announce(1);
}
+
+ ISR_DIRECT_PM();
z_arm_int_exit();
}
+ARCH_ISR_DIAG_ON
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
@@ -329,7 +334,7 @@
uint32_t sys_clock_elapsed(void)
{
- if (!TICKLESS) {
+ if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
@@ -421,7 +426,15 @@
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
if (last_load == TIMER_STOPPED) {
- SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+ /* We really don’t know here how much time has passed,
+ * so let’s restart the timer from scratch.
+ */
+ K_SPINLOCK(&lock) {
+ last_load = CYC_PER_TICK;
+ SysTick->LOAD = last_load - 1;
+ SysTick->VAL = 0; /* resets timer to last_load */
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+ }
}
}
diff --git a/drivers/timer/esp32_sys_timer.c b/drivers/timer/esp32_sys_timer.c
index 2eeb71d..bb36445 100644
--- a/drivers/timer/esp32_sys_timer.c
+++ b/drivers/timer/esp32_sys_timer.c
@@ -143,13 +143,19 @@
static int sys_clock_driver_init(void)
{
+ int ret;
- esp_intr_alloc(DT_IRQN(DT_NODELABEL(systimer0)),
- 0,
+ ret = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(systimer0), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(systimer0), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(systimer0), 0, flags)),
sys_timer_isr,
NULL,
NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
systimer_hal_init(&systimer_hal);
systimer_hal_connect_alarm_counter(&systimer_hal,
SYSTIMER_ALARM_OS_TICK_CORE0, SYSTIMER_COUNTER_OS_TICK);
diff --git a/drivers/timer/ite_it8xxx2_timer.c b/drivers/timer/ite_it8xxx2_timer.c
index 62ab394..86866bf 100644
--- a/drivers/timer/ite_it8xxx2_timer.c
+++ b/drivers/timer/ite_it8xxx2_timer.c
@@ -340,15 +340,15 @@
if (raw == EXT_RAW_CNT) {
hw_cnt = ms;
} else {
- if (clock_source_sel == EXT_PSR_32P768K)
+ if (clock_source_sel == EXT_PSR_32P768K) {
hw_cnt = MS_TO_COUNT(32768, ms);
- else if (clock_source_sel == EXT_PSR_1P024K)
+ } else if (clock_source_sel == EXT_PSR_1P024K) {
hw_cnt = MS_TO_COUNT(1024, ms);
- else if (clock_source_sel == EXT_PSR_32)
+ } else if (clock_source_sel == EXT_PSR_32) {
hw_cnt = MS_TO_COUNT(32, ms);
- else if (clock_source_sel == EXT_PSR_EC_CLK)
+ } else if (clock_source_sel == EXT_PSR_EC_CLK) {
hw_cnt = MS_TO_COUNT(EC_FREQ, ms);
- else {
+ } else {
LOG_ERR("Timer %d clock source error !", ext_timer);
return -1;
}
diff --git a/drivers/timer/mcux_os_timer.c b/drivers/timer/mcux_os_timer.c
index c278f59..74580e6 100644
--- a/drivers/timer/mcux_os_timer.c
+++ b/drivers/timer/mcux_os_timer.c
@@ -16,7 +16,9 @@
#include <zephyr/drivers/counter.h>
#include <zephyr/pm/pm.h>
#include "fsl_ostimer.h"
+#ifndef CONFIG_SOC_MCXN236
#include "fsl_power.h"
+#endif
#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
/ (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c
index c12b970..ba67c2d 100644
--- a/drivers/timer/stm32_lptim_timer.c
+++ b/drivers/timer/stm32_lptim_timer.c
@@ -162,8 +162,9 @@
/* Update autoreload register */
autoreload_next = arr;
- if (!autoreload_ready)
+ if (!autoreload_ready) {
return;
+ }
/* The ARR register ready, we could set it directly */
if ((arr > 0) && (arr != LL_LPTIM_GetAutoReload(LPTIM))) {
diff --git a/drivers/timer/ti_dmtimer.c b/drivers/timer/ti_dmtimer.c
index 7b04b92..e8476e8 100644
--- a/drivers/timer/ti_dmtimer.c
+++ b/drivers/timer/ti_dmtimer.c
@@ -54,8 +54,9 @@
static void ti_dmtimer_isr(void *data)
{
/* If no pending event */
- if (!TI_DM_TIMER_READ(IRQSTATUS))
+ if (!TI_DM_TIMER_READ(IRQSTATUS)) {
return;
+ }
k_spinlock_key_t key = k_spin_lock(&lock);
diff --git a/drivers/usb/common/nrf_usbd_common/nrf_usbd_common.c b/drivers/usb/common/nrf_usbd_common/nrf_usbd_common.c
index 3db193e..fcd5cff 100644
--- a/drivers/usb/common/nrf_usbd_common/nrf_usbd_common.c
+++ b/drivers/usb/common/nrf_usbd_common/nrf_usbd_common.c
@@ -1029,6 +1029,16 @@
volatile uint32_t *dma_endevent;
uint32_t epdatastatus = 0;
+ /* Always check and clear SOF but call handler only if SOF interrupt
+ * is actually enabled.
+ */
+ if (NRF_USBD->EVENTS_SOF) {
+ NRF_USBD->EVENTS_SOF = 0;
+ if (NRF_USBD->INTENSET & USBD_INTEN_SOF_Msk) {
+ ev_sof_handler();
+ }
+ }
+
/* Clear EPDATA event and only then get and clear EPDATASTATUS to make
* sure we don't miss any event.
*/
@@ -1066,16 +1076,6 @@
ev_usbreset_handler();
}
- /* Always check and clear SOF but call handler only if SOF interrupt
- * is actually enabled.
- */
- if (NRF_USBD->EVENTS_SOF) {
- NRF_USBD->EVENTS_SOF = 0;
- if (NRF_USBD->INTENSET & USBD_INTEN_SOF_Msk) {
- ev_sof_handler();
- }
- }
-
if (NRF_USBD->EVENTS_USBEVENT) {
NRF_USBD->EVENTS_USBEVENT = 0;
ev_usbevent_handler();
diff --git a/drivers/usb/common/usb_dwc2_hw.h b/drivers/usb/common/usb_dwc2_hw.h
index 88d32a9..5203cb0 100644
--- a/drivers/usb/common/usb_dwc2_hw.h
+++ b/drivers/usb/common/usb_dwc2_hw.h
@@ -755,13 +755,17 @@
* IN at offsets 0x0910 + (0x20 * n), n = 1 .. x,
* OUT at offsets 0x0B10 + (0x20 * n), n = 1 .. x
*/
+#define USB_DWC2_DEPTSIZN_MC_POS 29UL
+#define USB_DWC2_DEPTSIZN_MC_MASK (0x3UL << USB_DWC2_DEPTSIZN_MC_POS)
#define USB_DWC2_DEPTSIZN_PKTCNT_POS 19UL
#define USB_DWC2_DEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DEPTSIZN_PKTCNT_POS)
#define USB_DWC2_DEPTSIZN_XFERSIZE_POS 0UL
#define USB_DWC2_DEPTSIZN_XFERSIZE_MASK 0x7FFFFUL
+USB_DWC2_GET_FIELD_DEFINE(deptsizn_mc, DEPTSIZN_MC)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE)
+USB_DWC2_SET_FIELD_DEFINE(deptsizn_mc, DEPTSIZN_MC)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE)
diff --git a/drivers/usb/device/Kconfig b/drivers/usb/device/Kconfig
index 74d9ddb..d8a4b0d 100644
--- a/drivers/usb/device/Kconfig
+++ b/drivers/usb/device/Kconfig
@@ -154,13 +154,10 @@
if USB_MCUX
-choice USB_MCUX_CONTROLLER_TYPE
- prompt "USB Controller type"
- help
- Select the type of controller available in the SoC.
-
config USB_DC_NXP_EHCI
bool "MXRT EHCI USB Device Controller"
+ default y
+ depends on DT_HAS_NXP_EHCI_ENABLED
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
select USB_DC_HAS_HS_SUPPORT
help
@@ -168,13 +165,13 @@
config USB_DC_NXP_LPCIP3511
bool "LPC USB Device Controller"
+ default y
+ depends on DT_HAS_NXP_LPCIP3511_ENABLED
select USB_DC_HAS_HS_SUPPORT if "$(dt_nodelabel_enabled,usbhs)"
select PINCTRL
help
LPC USB Device Controller Driver.
-endchoice
-
config USB_DC_MSG_QUEUE_LEN
int
default 10
diff --git a/drivers/usb/device/usb_dc_mcux.c b/drivers/usb/device/usb_dc_mcux.c
index d626620..b28499d 100644
--- a/drivers/usb/device/usb_dc_mcux.c
+++ b/drivers/usb/device/usb_dc_mcux.c
@@ -78,7 +78,7 @@
/* Controller ID is for HAL usage */
#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || \
defined(CONFIG_SOC_SERIES_IMXRT6XX) || \
- defined(CONFIG_SOC_LPC55S28) || \
+ defined(CONFIG_SOC_LPC55S26) || defined(CONFIG_SOC_LPC55S28) || \
defined(CONFIG_SOC_LPC55S16)
#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
#elif defined(CONFIG_SOC_LPC55S36)
@@ -91,7 +91,7 @@
#endif /* LPC55s69 */
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || \
defined(CONFIG_SOC_SERIES_IMXRT10XX) || \
- defined(CONFIG_SOC_SERIES_MCXNX4X)
+ defined(CONFIG_SOC_SERIES_MCXN)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay)
#define CONTROLLER_ID kUSB_ControllerEhci0
#elif DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay)
diff --git a/drivers/usb/udc/CMakeLists.txt b/drivers/usb/udc/CMakeLists.txt
index 6004729..44c9bf0 100644
--- a/drivers/usb/udc/CMakeLists.txt
+++ b/drivers/usb/udc/CMakeLists.txt
@@ -15,3 +15,4 @@
zephyr_library_sources_ifdef(CONFIG_UDC_IT82XX2 udc_it82xx2.c)
zephyr_library_sources_ifdef(CONFIG_UDC_NXP_EHCI udc_mcux_ehci.c)
zephyr_library_sources_ifdef(CONFIG_UDC_NXP_IP3511 udc_mcux_ip3511.c)
+zephyr_library_sources_ifdef(CONFIG_UDC_NUMAKER udc_numaker.c)
diff --git a/drivers/usb/udc/Kconfig b/drivers/usb/udc/Kconfig
index bd6f71e..59b8062 100644
--- a/drivers/usb/udc/Kconfig
+++ b/drivers/usb/udc/Kconfig
@@ -62,5 +62,6 @@
source "drivers/usb/udc/Kconfig.stm32"
source "drivers/usb/udc/Kconfig.it82xx2"
source "drivers/usb/udc/Kconfig.mcux"
+source "drivers/usb/udc/Kconfig.numaker"
endif # UDC_DRIVER
diff --git a/drivers/usb/udc/Kconfig.numaker b/drivers/usb/udc/Kconfig.numaker
new file mode 100644
index 0000000..8b7e59f
--- /dev/null
+++ b/drivers/usb/udc/Kconfig.numaker
@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config UDC_NUMAKER
+ bool "Nuvoton NuMaker USB 1.1 device controller"
+ default y
+ depends on DT_HAS_NUVOTON_NUMAKER_USBD_ENABLED
+ help
+ Enable Nuvoton NuMaker USB 1.1 device controller driver
+
+if UDC_NUMAKER
+
+config UDC_NUMAKER_MSG_QUEUE_SIZE
+ int "UDC NuMaker message queue size"
+ default 32
+ help
+ Maximum number of messages the driver can queue for interrupt bottom half processing.
+
+config UDC_NUMAKER_THREAD_STACK_SIZE
+ int "UDC NuMaker driver internal thread stack size"
+ default 1536
+ help
+ Size of the stack for the driver internal thread.
+
+config UDC_NUMAKER_THREAD_PRIORITY
+ int "UDC NuMaker driver internal thread priority"
+ default 8
+ help
+ Priority of the driver internal thread.
+
+endif # UDC_NUMAKER
diff --git a/drivers/usb/udc/udc_common.c b/drivers/usb/udc/udc_common.c
index c152d4a..53ae5a3 100644
--- a/drivers/usb/udc/udc_common.c
+++ b/drivers/usb/udc/udc_common.c
@@ -124,7 +124,7 @@
return NULL;
}
- return net_buf_get(&ep_cfg->fifo, K_NO_WAIT);
+ return k_fifo_get(&ep_cfg->fifo, K_NO_WAIT);
}
struct net_buf *udc_buf_get_all(const struct device *dev, const uint8_t ep)
@@ -169,7 +169,7 @@
void udc_buf_put(struct udc_ep_config *const ep_cfg,
struct net_buf *const buf)
{
- net_buf_put(&ep_cfg->fifo, buf);
+ k_fifo_put(&ep_cfg->fifo, buf);
}
void udc_ep_buf_set_setup(struct net_buf *const buf)
@@ -262,7 +262,7 @@
return false;
}
- if (mps > cfg->caps.mps) {
+ if (USB_MPS_EP_SIZE(mps) > USB_MPS_EP_SIZE(cfg->caps.mps)) {
return false;
}
@@ -273,12 +273,16 @@
}
break;
case USB_EP_TYPE_INTERRUPT:
- if (!cfg->caps.interrupt) {
+ if (!cfg->caps.interrupt ||
+ (USB_MPS_ADDITIONAL_TRANSACTIONS(mps) &&
+ !cfg->caps.high_bandwidth)) {
return false;
}
break;
case USB_EP_TYPE_ISO:
- if (!cfg->caps.iso) {
+ if (!cfg->caps.iso ||
+ (USB_MPS_ADDITIONAL_TRANSACTIONS(mps) &&
+ !cfg->caps.high_bandwidth)) {
return false;
}
break;
diff --git a/drivers/usb/udc/udc_dwc2.c b/drivers/usb/udc/udc_dwc2.c
index cab7994..038c887 100644
--- a/drivers/usb/udc/udc_dwc2.c
+++ b/drivers/usb/udc/udc_dwc2.c
@@ -50,7 +50,14 @@
* of 512 bytes. The value must be adjusted according to the number of OUT
* endpoints.
*/
-#define UDC_DWC2_GRXFSIZ_DEFAULT (15U + 512U/4U)
+#define UDC_DWC2_GRXFSIZ_FS_DEFAULT (15U + 512U/4U)
+/* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
+ * * 1 control endpoint in Completer/Buffer DMA mode: 13 locations
+ * * Global OUT NAK: 1 location
+ * * Space for 3 * 1024 packets: ((1024/4) + 1) * 3 = 774 locations
+ * Driver adds 2 locations for each OUT endpoint to this value.
+ */
+#define UDC_DWC2_GRXFSIZ_HS_DEFAULT (13 + 1 + 774)
/* TX FIFO0 depth in 32-bit words (used by control IN endpoint) */
#define UDC_DWC2_FIFO0_DEPTH 16U
@@ -251,6 +258,18 @@
}
}
+static bool dwc2_ep_is_periodic(struct udc_ep_config *const cfg)
+{
+ switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) {
+ case USB_EP_TYPE_INTERRUPT:
+ __fallthrough;
+ case USB_EP_TYPE_ISO:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool dwc2_dma_buffer_ok_to_use(const struct device *dev, void *buf,
uint32_t xfersize, uint16_t mps)
{
@@ -261,8 +280,8 @@
return false;
}
- /* If Max Packet Size is not */
- if (unlikely(mps % 4) && (xfersize > mps)) {
+ /* We can only do 1 packet if Max Packet Size is not multiple of 4 */
+ if (unlikely(mps % 4) && (xfersize > USB_MPS_EP_SIZE(mps))) {
LOG_ERR("Padding not supported");
return false;
}
@@ -283,29 +302,43 @@
mem_addr_t diepctl_reg = (mem_addr_t)&base->in_ep[ep_idx].diepctl;
mem_addr_t diepint_reg = (mem_addr_t)&base->in_ep[ep_idx].diepint;
- uint32_t max_xfersize, max_pktcnt, pktcnt, spcavail;
+ uint32_t max_xfersize, max_pktcnt, pktcnt;
+ const uint32_t addnl = USB_MPS_ADDITIONAL_TRANSACTIONS(cfg->mps);
const size_t d = sizeof(uint32_t);
unsigned int key;
uint32_t len;
+ const bool is_periodic = dwc2_ep_is_periodic(cfg);
- spcavail = dwc2_ftx_avail(dev, ep_idx);
- /* Round down to multiple of endpoint MPS */
- spcavail -= spcavail % cfg->mps;
- /*
- * Here, the available space should be equal to the FIFO space
- * assigned/configured for that endpoint because we do not schedule another
- * transfer until the previous one has not finished. For simplicity,
- * we only check that the available space is not less than the endpoint
- * MPS.
- */
- if (spcavail < cfg->mps) {
- LOG_ERR("ep 0x%02x FIFO space is too low, %u (%u)",
- cfg->addr, spcavail, dwc2_ftx_avail(dev, ep_idx));
- return -EAGAIN;
+ if (priv->bufferdma) {
+ /* DMA automatically handles packet split */
+ len = buf->len;
+ } else {
+ uint32_t spcavail = dwc2_ftx_avail(dev, ep_idx);
+ uint32_t spcperpkt = ROUND_UP(udc_mps_ep_size(cfg), 4);
+ uint32_t max_pkts, max_transfer;
+
+ /* Maximum number of packets that can fit in TxFIFO */
+ max_pkts = spcavail / spcperpkt;
+
+ /* We can transfer up to max_pkts MPS packets and a short one */
+ max_transfer = (max_pkts * udc_mps_ep_size(cfg)) +
+ (spcavail % spcperpkt);
+
+ /* If there is enough space for the transfer, there's no need
+ * to check any additional conditions. If the transfer is larger
+ * than TxFIFO then TxFIFO must be able to hold at least one
+ * packet (for periodic transfers at least the number of packets
+ * per microframe).
+ */
+ if ((buf->len > max_transfer) && ((1 + addnl) > max_pkts)) {
+ LOG_ERR("ep 0x%02x FIFO space is too low, %u (%u)",
+ cfg->addr, spcavail, buf->len);
+ return -EAGAIN;
+ }
+
+ len = MIN(buf->len, max_transfer);
}
- len = MIN(buf->len, spcavail);
-
if (len != 0U) {
max_pktcnt = dwc2_get_iept_pktctn(dev, ep_idx);
max_xfersize = dwc2_get_iept_xfersize(dev, ep_idx);
@@ -315,32 +348,34 @@
* Avoid short packets if the transfer size cannot be
* handled in one set.
*/
- len = ROUND_DOWN(max_xfersize, cfg->mps);
+ len = ROUND_DOWN(max_xfersize, USB_MPS_TO_TPL(cfg->mps));
}
/*
* Determine the number of packets for the current transfer;
* if the pktcnt is too large, truncate the actual transfer length.
*/
- pktcnt = DIV_ROUND_UP(len, cfg->mps);
+ pktcnt = DIV_ROUND_UP(len, udc_mps_ep_size(cfg));
if (pktcnt > max_pktcnt) {
- pktcnt = max_pktcnt;
- len = pktcnt * cfg->mps;
+ pktcnt = ROUND_DOWN(max_pktcnt, (1 + addnl));
+ len = pktcnt * udc_mps_ep_size(cfg);
}
} else {
/* ZLP */
pktcnt = 1U;
}
- LOG_DBG("Prepare ep 0x%02x xfer len %u pktcnt %u spcavail %u",
- cfg->addr, len, pktcnt, spcavail);
+ LOG_DBG("Prepare ep 0x%02x xfer len %u pktcnt %u addnl %u",
+ cfg->addr, len, pktcnt, addnl);
priv->tx_len[ep_idx] = len;
/* Lock and write to endpoint FIFO */
key = irq_lock();
/* Set number of packets and transfer size */
- sys_write32((pktcnt << USB_DWC2_DEPTSIZN_PKTCNT_POS) | len, dieptsiz_reg);
+ sys_write32((is_periodic ? usb_dwc2_set_deptsizn_mc(1 + addnl) : 0) |
+ usb_dwc2_set_deptsizn_pktcnt(pktcnt) |
+ usb_dwc2_set_deptsizn_xfersize(len), dieptsiz_reg);
if (priv->bufferdma) {
if (!dwc2_dma_buffer_ok_to_use(dev, buf->data, len, cfg->mps)) {
@@ -363,22 +398,30 @@
sys_write32(USB_DWC2_DIEPINT_INEPNAKEFF, diepint_reg);
if (!priv->bufferdma) {
- /* FIFO access is always in 32-bit words */
+ const uint8_t *src = buf->data;
- for (uint32_t i = 0UL; i < len; i += d) {
- uint32_t val = buf->data[i];
+ while (pktcnt > 0) {
+ uint32_t pktlen = MIN(len, udc_mps_ep_size(cfg));
- if (i + 1 < len) {
- val |= ((uint32_t)buf->data[i + 1UL]) << 8;
- }
- if (i + 2 < len) {
- val |= ((uint32_t)buf->data[i + 2UL]) << 16;
- }
- if (i + 3 < len) {
- val |= ((uint32_t)buf->data[i + 3UL]) << 24;
+ for (uint32_t i = 0UL; i < pktlen; i += d) {
+ uint32_t val = src[i];
+
+ if (i + 1 < pktlen) {
+ val |= ((uint32_t)src[i + 1UL]) << 8;
+ }
+ if (i + 2 < pktlen) {
+ val |= ((uint32_t)src[i + 2UL]) << 16;
+ }
+ if (i + 3 < pktlen) {
+ val |= ((uint32_t)src[i + 3UL]) << 24;
+ }
+
+ sys_write32(val, UDC_DWC2_EP_FIFO(base, ep_idx));
}
- sys_write32(val, UDC_DWC2_EP_FIFO(base, ep_idx));
+ pktcnt--;
+ src += pktlen;
+ len -= pktlen;
}
}
@@ -430,14 +473,17 @@
/* Do as many packets in a single DMA as possible */
if (size > priv->max_xfersize) {
- size = ROUND_DOWN(priv->max_xfersize, cfg->mps);
+ size = ROUND_DOWN(priv->max_xfersize,
+ USB_MPS_TO_TPL(cfg->mps));
}
} else {
/* Completer mode can always program Max Packet Size, RxFLvl
* interrupt will drop excessive data if necessary (i.e. buffer
- * is too short).
+ * is too short). The value returned must be Max Packet Size
+ * multiple in order for dwc2_handle_rxflvl() to correctly
+ * detect when RX has to be prepared during large transfers.
*/
- size = cfg->mps;
+ size = USB_MPS_TO_TPL(cfg->mps);
}
return size;
@@ -452,12 +498,15 @@
uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
mem_addr_t doeptsiz_reg = (mem_addr_t)&base->out_ep[ep_idx].doeptsiz;
mem_addr_t doepctl_reg = dwc2_get_dxepctl_reg(dev, ep_idx);
+ uint32_t pktcnt;
uint32_t doeptsiz;
uint32_t xfersize;
xfersize = dwc2_rx_xfer_size(priv, cfg, buf);
- doeptsiz = xfersize | usb_dwc2_set_deptsizn_pktcnt(DIV_ROUND_UP(xfersize, cfg->mps));
+ pktcnt = DIV_ROUND_UP(xfersize, udc_mps_ep_size(cfg));
+ doeptsiz = usb_dwc2_set_deptsizn_pktcnt(pktcnt) |
+ usb_dwc2_set_deptsizn_xfersize(xfersize);
if (cfg->addr == USB_CONTROL_EP_OUT) {
/* Use 1 to allow 8 byte long buffers for SETUP data */
doeptsiz |= (1 << USB_DWC2_DOEPTSIZ0_SUPCNT_POS);
@@ -590,7 +639,7 @@
buf = udc_buf_get(dev, cfg->addr);
if (buf == NULL) {
- LOG_ERR("No buffer queued for control ep");
+ LOG_ERR("No buffer queued for ep 0x%02x", cfg->addr);
return -ENODATA;
}
@@ -838,8 +887,14 @@
break;
}
- if (net_buf_tailroom(buf) && evt.bcnt == ep_cfg->mps) {
- dwc2_prep_rx(dev, buf, ep_cfg, 0);
+ if ((evt.bcnt % udc_mps_ep_size(ep_cfg)) == 0 && net_buf_tailroom(buf)) {
+ uint32_t doeptsiz;
+
+ /* Prepare next read only when transfer finished */
+ doeptsiz = sys_read32((mem_addr_t)&base->out_ep[evt.ep].doeptsiz);
+ if (usb_dwc2_get_deptsizn_xfersize(doeptsiz) == 0) {
+ dwc2_prep_rx(dev, buf, ep_cfg, 0);
+ }
} else {
k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
}
@@ -954,7 +1009,7 @@
net_buf_add(buf, evt.bcnt);
- if (((evt.bcnt % ep_cfg->mps) == 0) && net_buf_tailroom(buf)) {
+ if ((evt.bcnt % udc_mps_ep_size(ep_cfg)) == 0 && net_buf_tailroom(buf)) {
dwc2_prep_rx(dev, buf, ep_cfg, 0);
} else {
k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
@@ -1134,6 +1189,8 @@
{
struct udc_dwc2_data *const priv = udc_get_private(dev);
uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
+ const uint32_t addnl = USB_MPS_ADDITIONAL_TRANSACTIONS(cfg->mps);
+ uint32_t reqdep;
uint32_t txfaddr;
uint32_t txfdep;
uint32_t tmp;
@@ -1141,6 +1198,14 @@
/* Keep everything but FIFO number */
tmp = *diepctl & ~USB_DWC2_DEPCTL_TXFNUM_MASK;
+ reqdep = DIV_ROUND_UP(udc_mps_ep_size(cfg), 4U);
+ if (priv->bufferdma) {
+ /* In DMA mode, TxFIFO capable of holding 2 packets is enough */
+ reqdep *= MIN(2, (1 + addnl));
+ } else {
+ reqdep *= (1 + addnl);
+ }
+
if (priv->dynfifosizing) {
if (priv->txf_set & ~BIT_MASK(ep_idx)) {
dwc2_unset_unused_fifo(dev);
@@ -1161,7 +1226,7 @@
}
/* Make sure to not set TxFIFO greater than hardware allows */
- txfdep = DIV_ROUND_UP(cfg->mps, 4U);
+ txfdep = reqdep;
if (txfdep > priv->max_txfifo_depth[ep_idx]) {
return -ENOMEM;
}
@@ -1172,7 +1237,7 @@
txfdep = dwc2_get_txfdep(dev, ep_idx - 1);
txfaddr = dwc2_get_txfaddr(dev, ep_idx - 1);
- if (cfg->mps < txfdep * 4U) {
+ if (reqdep > txfdep) {
return -ENOMEM;
}
@@ -1264,11 +1329,7 @@
dxepctl_reg = (mem_addr_t)&base->in_ep[ep_idx].diepctl;
}
- if (cfg->mps > usb_dwc2_get_depctl_mps(UINT16_MAX)) {
- return -EINVAL;
- }
-
- if (priv->bufferdma && (cfg->mps % 4)) {
+ if (priv->bufferdma && (udc_mps_ep_size(cfg) % 4)) {
/* TODO: In Buffer DMA mode, DMA will insert padding bytes in
* between packets if endpoint Max Packet Size is not multiple
* of 4 (DWORD) and single transfer spans across multiple
@@ -1288,7 +1349,7 @@
dxepctl = sys_read32(dxepctl_reg);
/* Set max packet size */
dxepctl &= ~USB_DWC2_DEPCTL_MPS_MASK;
- dxepctl |= cfg->mps << USB_DWC2_DEPCTL_MPS_POS;
+ dxepctl |= usb_dwc2_set_depctl_mps(udc_mps_ep_size(cfg));
/* Set endpoint type */
dxepctl &= ~USB_DWC2_DEPCTL_EPTYPE_MASK;
@@ -1312,7 +1373,7 @@
return -EINVAL;
}
- if (USB_EP_DIR_IS_IN(cfg->addr) && cfg->mps != 0U) {
+ if (USB_EP_DIR_IS_IN(cfg->addr) && udc_mps_ep_size(cfg) != 0U) {
int ret = dwc2_set_dedicated_fifo(dev, cfg, &dxepctl);
if (ret) {
@@ -1515,7 +1576,8 @@
cfg->addr, ep_idx, dxepctl);
}
- if (USB_EP_DIR_IS_IN(cfg->addr) && cfg->mps != 0U && ep_idx != 0U) {
+ if (USB_EP_DIR_IS_IN(cfg->addr) && udc_mps_ep_size(cfg) != 0U &&
+ ep_idx != 0U) {
dwc2_unset_dedicated_fifo(dev, cfg, &dxepctl);
}
@@ -1742,6 +1804,7 @@
uint32_t ghwcfg4;
uint32_t val;
int ret;
+ bool hs_phy;
ret = dwc2_core_soft_reset(dev);
if (ret) {
@@ -1842,12 +1905,14 @@
USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_ULPI;
dcfg |= USB_DWC2_DCFG_DEVSPD_USBHS20
<< USB_DWC2_DCFG_DEVSPD_POS;
+ hs_phy = true;
break;
case USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS:
gusbcfg |= USB_DWC2_GUSBCFG_PHYSEL_USB20 |
USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_UTMI;
dcfg |= USB_DWC2_DCFG_DEVSPD_USBHS20
<< USB_DWC2_DCFG_DEVSPD_POS;
+ hs_phy = true;
break;
case USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS:
__fallthrough;
@@ -1859,6 +1924,7 @@
dcfg |= USB_DWC2_DCFG_DEVSPD_USBFS1148
<< USB_DWC2_DCFG_DEVSPD_POS;
+ hs_phy = false;
}
if (usb_dwc2_get_ghwcfg4_phydatawidth(ghwcfg4)) {
@@ -1897,13 +1963,28 @@
if (priv->dynfifosizing) {
uint32_t gnptxfsiz;
+ uint32_t default_depth;
+
+ /* TODO: For proper runtime FIFO sizing UDC driver would have to
+ * have prior knowledge of the USB configurations. Only with the
+ * prior knowledge, the driver will be able to fairly distribute
+ * available resources. For the time being just use different
+ * defaults based on maximum configured PHY speed, but this has
+ * to be revised if e.g. thresholding support would be necessary
+ * on some target.
+ */
+ if (hs_phy) {
+ default_depth = UDC_DWC2_GRXFSIZ_HS_DEFAULT;
+ } else {
+ default_depth = UDC_DWC2_GRXFSIZ_FS_DEFAULT;
+ }
+ default_depth += priv->outeps * 2U;
/* Driver does not dynamically resize RxFIFO so there is no need
* to store reset value. Read the reset value and make sure that
* the programmed value is not greater than what driver sets.
*/
- priv->rxfifo_depth = MIN(priv->rxfifo_depth,
- UDC_DWC2_GRXFSIZ_DEFAULT + priv->outeps * 2U);
+ priv->rxfifo_depth = MIN(priv->rxfifo_depth, default_depth);
sys_write32(usb_dwc2_set_grxfsiz(priv->rxfifo_depth), grxfsiz_reg);
/* Set TxFIFO 0 depth */
@@ -2082,6 +2163,7 @@
config->ep_cfg_out[n].caps.bulk = 1;
config->ep_cfg_out[n].caps.interrupt = 1;
config->ep_cfg_out[n].caps.iso = 1;
+ config->ep_cfg_out[n].caps.high_bandwidth = data->caps.hs;
config->ep_cfg_out[n].caps.mps = mps;
}
@@ -2117,6 +2199,7 @@
config->ep_cfg_in[n].caps.bulk = 1;
config->ep_cfg_in[n].caps.interrupt = 1;
config->ep_cfg_in[n].caps.iso = 1;
+ config->ep_cfg_in[n].caps.high_bandwidth = data->caps.hs;
config->ep_cfg_in[n].caps.mps = mps;
}
diff --git a/drivers/usb/udc/udc_it82xx2.c b/drivers/usb/udc/udc_it82xx2.c
index 70209f1..d14ce36 100644
--- a/drivers/usb/udc/udc_it82xx2.c
+++ b/drivers/usb/udc/udc_it82xx2.c
@@ -705,7 +705,7 @@
it82xx2_usb_fifo_ctrl(dev, ep);
}
- len = MIN(buf->len, ep_cfg->mps);
+ len = MIN(buf->len, udc_mps_ep_size(ep_cfg));
for (size_t i = 0; i < len; i++) {
ff_regs[fifo_idx].ep_tx_fifo_data = buf->data[i];
@@ -874,7 +874,7 @@
}
ep_cfg = udc_get_ep_cfg(dev, ep);
- net_buf_pull(buf, MIN(buf->len, ep_cfg->mps));
+ net_buf_pull(buf, MIN(buf->len, udc_mps_ep_size(ep_cfg)));
it82xx2_usb_set_ep_ctrl(dev, ep, EP_DATA_SEQ_TOGGLE, true);
@@ -1016,7 +1016,7 @@
}
ep_cfg = udc_get_ep_cfg(dev, ep);
- if (len > ep_cfg->mps) {
+ if (len > udc_mps_ep_size(ep_cfg)) {
LOG_ERR("Failed to handle this packet due to the packet size");
return -ENOBUFS;
}
diff --git a/drivers/usb/udc/udc_kinetis.c b/drivers/usb/udc/udc_kinetis.c
index 4040bc7..6331110 100644
--- a/drivers/usb/udc/udc_kinetis.c
+++ b/drivers/usb/udc/udc_kinetis.c
@@ -195,10 +195,10 @@
}
if (USB_EP_DIR_IS_OUT(cfg->addr)) {
- len = MIN(net_buf_tailroom(buf), cfg->mps);
+ len = MIN(net_buf_tailroom(buf), udc_mps_ep_size(cfg));
data_ptr = net_buf_tail(buf);
} else {
- len = MIN(buf->len, cfg->mps);
+ len = MIN(buf->len, udc_mps_ep_size(cfg));
data_ptr = buf->data;
}
@@ -243,7 +243,7 @@
}
bd = usbfsotg_get_ebd(dev, cfg, false);
- length = MIN(net_buf_tailroom(buf), cfg->mps);
+ length = MIN(net_buf_tailroom(buf), udc_mps_ep_size(cfg));
priv->out_buf[cfg->stat.odd] = buf;
priv->busy[cfg->stat.odd] = true;
@@ -267,7 +267,7 @@
}
bd = usbfsotg_get_ebd(dev, cfg, true);
- length = MIN(net_buf_tailroom(buf), cfg->mps);
+ length = MIN(net_buf_tailroom(buf), udc_mps_ep_size(cfg));
priv->out_buf[!cfg->stat.odd] = buf;
priv->busy[!cfg->stat.odd] = true;
@@ -594,7 +594,8 @@
}
net_buf_add(buf, len);
- if (net_buf_tailroom(buf) >= ep_cfg->mps && len == ep_cfg->mps) {
+ if (net_buf_tailroom(buf) >= udc_mps_ep_size(ep_cfg) &&
+ len == udc_mps_ep_size(ep_cfg)) {
if (ep == USB_CONTROL_EP_OUT) {
usbfsotg_ctrl_feed_start(dev, buf);
} else {
diff --git a/drivers/usb/udc/udc_mcux_ehci.c b/drivers/usb/udc/udc_mcux_ehci.c
index 451066b..920279e 100644
--- a/drivers/usb/udc/udc_mcux_ehci.c
+++ b/drivers/usb/udc/udc_mcux_ehci.c
@@ -151,7 +151,7 @@
return -ENOMEM;
}
- net_buf_put(&cfg->fifo, buf);
+ k_fifo_put(&cfg->fifo, buf);
ret = udc_mcux_ep_feed(dev, cfg, buf);
@@ -454,6 +454,9 @@
case kUSB_DeviceNotifyAttach:
udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
break;
+ case kUSB_DeviceNotifySOF:
+ udc_submit_event(dev, UDC_EVT_SOF, 0);
+ break;
default:
ep = mcux_msg->code;
if (mcux_msg->isSetup) {
@@ -568,6 +571,7 @@
ep_init.zlt = 0U;
ep_init.interval = cfg->interval;
ep_init.endpointAddress = cfg->addr;
+ /* HAL expects wMaxPacketSize value directly in maxPacketSize field */
ep_init.maxPacketSize = cfg->mps;
switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) {
@@ -730,6 +734,7 @@
config->ep_cfg_out[i].caps.interrupt = 1;
config->ep_cfg_out[i].caps.iso = 1;
config->ep_cfg_out[i].caps.mps = 1024;
+ config->ep_cfg_out[i].caps.high_bandwidth = 1;
}
config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
@@ -750,6 +755,7 @@
config->ep_cfg_in[i].caps.interrupt = 1;
config->ep_cfg_in[i].caps.iso = 1;
config->ep_cfg_in[i].caps.mps = 1024;
+ config->ep_cfg_in[i].caps.high_bandwidth = 1;
}
config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
diff --git a/drivers/usb/udc/udc_mcux_ip3511.c b/drivers/usb/udc/udc_mcux_ip3511.c
index 4c709fd..724c422 100644
--- a/drivers/usb/udc/udc_mcux_ip3511.c
+++ b/drivers/usb/udc/udc_mcux_ip3511.c
@@ -151,7 +151,7 @@
return -ENOMEM;
}
- net_buf_put(&cfg->fifo, buf);
+ k_fifo_put(&cfg->fifo, buf);
ret = udc_mcux_ep_feed(dev, cfg, buf);
@@ -454,6 +454,9 @@
case kUSB_DeviceNotifyAttach:
udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
break;
+ case kUSB_DeviceNotifySOF:
+ udc_submit_event(dev, UDC_EVT_SOF, 0);
+ break;
default:
ep = mcux_msg->code;
if (mcux_msg->isSetup) {
@@ -568,6 +571,7 @@
ep_init.zlt = 0U;
ep_init.interval = cfg->interval;
ep_init.endpointAddress = cfg->addr;
+ /* HAL expects wMaxPacketSize value directly in maxPacketSize field */
ep_init.maxPacketSize = cfg->mps;
switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) {
@@ -744,6 +748,10 @@
config->ep_cfg_out[i].caps.interrupt = 1;
config->ep_cfg_out[i].caps.iso = 1;
config->ep_cfg_out[i].caps.mps = 1024;
+ if ((priv->controller_id == kUSB_ControllerLpcIp3511Hs0) ||
+ (priv->controller_id == kUSB_ControllerLpcIp3511Hs1)) {
+ config->ep_cfg_out[i].caps.high_bandwidth = 1;
+ }
}
config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
@@ -764,6 +772,10 @@
config->ep_cfg_in[i].caps.interrupt = 1;
config->ep_cfg_in[i].caps.iso = 1;
config->ep_cfg_in[i].caps.mps = 1024;
+ if ((priv->controller_id == kUSB_ControllerLpcIp3511Hs0) ||
+ (priv->controller_id == kUSB_ControllerLpcIp3511Hs1)) {
+ config->ep_cfg_in[i].caps.high_bandwidth = 1;
+ }
}
config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
diff --git a/drivers/usb/udc/udc_nrf.c b/drivers/usb/udc/udc_nrf.c
index 4b82e25..4076713 100644
--- a/drivers/usb/udc/udc_nrf.c
+++ b/drivers/usb/udc/udc_nrf.c
@@ -308,7 +308,7 @@
return -ENOMEM;
}
- net_buf_put(&cfg->fifo, buf);
+ k_fifo_put(&cfg->fifo, buf);
udc_nrf_clear_control_out(dev);
return 0;
@@ -553,7 +553,7 @@
uint16_t mps;
__ASSERT_NO_MSG(cfg);
- mps = (cfg->mps == 0) ? cfg->caps.mps : cfg->mps;
+ mps = (udc_mps_ep_size(cfg) == 0) ? cfg->caps.mps : udc_mps_ep_size(cfg);
nrf_usbd_common_ep_max_packet_size_set(cfg->addr, mps);
nrf_usbd_common_ep_enable(cfg->addr);
if (!NRF_USBD_EPISO_CHECK(cfg->addr)) {
diff --git a/drivers/usb/udc/udc_numaker.c b/drivers/usb/udc/udc_numaker.c
new file mode 100644
index 0000000..2fba252
--- /dev/null
+++ b/drivers/usb/udc/udc_numaker.c
@@ -0,0 +1,1805 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nuvoton_numaker_usbd
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/usb/udc.h>
+#include <zephyr/sys/math_extras.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_numaker.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(udc_numaker, CONFIG_UDC_DRIVER_LOG_LEVEL);
+
+#include <soc.h>
+#include <NuMicro.h>
+
+#include "udc_common.h"
+
+/* USBD notes
+ *
+ * 1. Require 48MHz clock source
+ * (1) Not support HIRC48 as clock source. It involves trim with USB SOF packets
+ * and isn't suitable in HAL.
+ * (2) Instead of HICR48, core clock is required to be multiple of 48MHz e.g. 192MHz,
+ * to generate necessary 48MHz.
+ */
+
+/* For bus reset, keep 'SE0' (USB spec: SE0 >= 2.5 ms) */
+#define NUMAKER_USBD_BUS_RESET_DRV_SE0_US 3000
+
+/* For bus resume, generate 'K' (USB spec: 'K' >= 1 ms) */
+#define NUMAKER_USBD_BUS_RESUME_DRV_K_US 1500
+
+/* Reserve DMA buffer for Setup/CTRL OUT/CTRL IN, required to be 8-byte aligned */
+#define NUMAKER_USBD_DMABUF_SIZE_SETUP 8
+#define NUMAKER_USBD_DMABUF_SIZE_CTRLOUT 64
+#define NUMAKER_USBD_DMABUF_SIZE_CTRLIN 64
+
+enum numaker_usbd_msg_type {
+ /* Setup packet received */
+ NUMAKER_USBD_MSG_TYPE_SETUP,
+ /* OUT transaction for specific EP completed */
+ NUMAKER_USBD_MSG_TYPE_OUT,
+ /* IN transaction for specific EP completed */
+ NUMAKER_USBD_MSG_TYPE_IN,
+ /* Re-activate queued transfer for specific EP */
+ NUMAKER_USBD_MSG_TYPE_XFER,
+ /* S/W reconnect */
+ NUMAKER_USBD_MSG_TYPE_SW_RECONN,
+};
+
+struct numaker_usbd_msg {
+ enum numaker_usbd_msg_type type;
+ union {
+ struct {
+ enum udc_event_type type;
+ } udc_bus_event;
+ struct {
+ uint8_t packet[8];
+ } setup;
+ struct {
+ uint8_t ep;
+ } out;
+ struct {
+ uint8_t ep;
+ } in;
+ struct {
+ uint8_t ep;
+ } xfer;
+ };
+};
+
+/* EP H/W context */
+struct numaker_usbd_ep {
+ bool valid;
+
+ const struct device *dev; /* Pointer to the containing device */
+
+ uint8_t ep_hw_idx; /* BSP USBD driver EP index EP0, EP1, EP2, etc */
+ uint32_t ep_hw_cfg; /* BSP USBD driver EP configuration */
+
+ /* EP DMA buffer */
+ bool dmabuf_valid;
+ uint32_t dmabuf_base;
+ uint32_t dmabuf_size;
+
+ /* NOTE: On USBD, Setup and CTRL OUT are not completely separated. CTRL OUT MXPLD
+ * can be overridden to 8 by next Setup. To overcome it, we make one copy of CTRL
+ * OUT MXPLD immediately on its interrupt.
+ */
+ uint32_t mxpld_ctrlout;
+
+ /* EP address */
+ bool addr_valid;
+ uint8_t addr;
+
+ /* EP MPS */
+ bool mps_valid;
+ uint16_t mps;
+};
+
+/* Immutable device context */
+struct udc_numaker_config {
+ struct udc_ep_config *ep_cfg_out;
+ struct udc_ep_config *ep_cfg_in;
+ uint32_t ep_cfg_out_size;
+ uint32_t ep_cfg_in_size;
+ USBD_T *base;
+ const struct reset_dt_spec reset;
+ uint32_t clk_modidx;
+ uint32_t clk_src;
+ uint32_t clk_div;
+ const struct device *clkctrl_dev;
+ void (*irq_config_func)(const struct device *dev);
+ void (*irq_unconfig_func)(const struct device *dev);
+ const struct pinctrl_dev_config *pincfg;
+ uint32_t dmabuf_size;
+ bool disallow_iso_inout_same;
+ void (*make_thread)(const struct device *dev);
+};
+
+/* EP H/W context manager */
+struct numaker_usbd_ep_mgmt {
+ /* EP H/W context management
+ *
+ * Allocate-only, and de-allocate all on re-initialize in udc_numaker_init().
+ */
+ uint8_t ep_idx;
+
+ /* DMA buffer management
+ *
+ * Allocate-only, and de-allocate all on re-initialize in udc_numaker_init().
+ */
+ uint32_t dmabuf_pos;
+};
+
+/* Mutable device context */
+struct udc_numaker_data {
+ uint8_t addr; /* Host assigned USB device address */
+
+ struct k_msgq *msgq;
+
+ struct numaker_usbd_ep_mgmt ep_mgmt; /* EP management */
+
+ struct numaker_usbd_ep *ep_pool;
+ uint32_t ep_pool_size;
+
+ struct k_thread thread_data;
+
+ /* Track end of CTRL DATA OUT/STATUS OUT stage
+ *
+ * net_buf can over-allocate for UDC_BUF_GRANULARITY requirement
+ * and net_buf_tailroom() cannot reflect free buffer room exactly
+ * as allocate request. Manually track it instead.
+ */
+ uint32_t ctrlout_tailroom;
+};
+
+static inline void numaker_usbd_sw_connect(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+
+ /* Clear all interrupts first for clean */
+ base->INTSTS = base->INTSTS;
+
+ /* Enable relevant interrupts */
+ base->INTEN = USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP | USBD_INT_SOF;
+
+ /* Clear SE0 for connect */
+ base->SE0 &= ~USBD_DRVSE0;
+}
+
+static inline void numaker_usbd_sw_disconnect(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+
+ /* Set SE0 for disconnect */
+ base->SE0 |= USBD_DRVSE0;
+}
+
+static inline void numaker_usbd_sw_reconnect(const struct device *dev)
+{
+ /* Keep SE0 to trigger bus reset */
+ numaker_usbd_sw_disconnect(dev);
+ k_sleep(K_USEC(NUMAKER_USBD_BUS_RESET_DRV_SE0_US));
+ numaker_usbd_sw_connect(dev);
+}
+
+static inline void numaker_usbd_reset_addr(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ USBD_T *const base = config->base;
+
+ base->FADDR = 0;
+ priv->addr = 0;
+}
+
+static inline void numaker_usbd_set_addr(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ USBD_T *const base = config->base;
+
+ if (base->FADDR != priv->addr) {
+ base->FADDR = priv->addr;
+ }
+}
+
+/* USBD EP base by e.g. EP0, EP1, ... */
+static inline USBD_EP_T *numaker_usbd_ep_base(const struct device *dev, uint32_t ep_hw_idx)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+
+ return base->EP + ep_hw_idx;
+}
+
+static inline void numaker_usbd_ep_sync_udc_halt(struct numaker_usbd_ep *ep_cur, bool stalled)
+{
+ const struct device *dev = ep_cur->dev;
+ struct udc_ep_config *ep_cfg;
+
+ __ASSERT_NO_MSG(ep_cur->addr_valid);
+ ep_cfg = udc_get_ep_cfg(dev, ep_cur->addr);
+ ep_cfg->stat.halted = stalled;
+}
+
+static inline void numaker_usbd_ep_set_stall(struct numaker_usbd_ep *ep_cur)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ /* Set EP to stalled */
+ ep_base->CFGP |= USBD_CFGP_SSTALL_Msk;
+ numaker_usbd_ep_sync_udc_halt(ep_cur, true);
+}
+
+/* Reset EP to unstalled and data toggle bit to 0 */
+static inline void numaker_usbd_ep_clear_stall_n_data_toggle(struct numaker_usbd_ep *ep_cur)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ /* Reset EP to unstalled */
+ ep_base->CFGP &= ~USBD_CFGP_SSTALL_Msk;
+ numaker_usbd_ep_sync_udc_halt(ep_cur, false);
+
+ /* Reset EP data toggle bit to 0 */
+ ep_base->CFG &= ~USBD_CFG_DSQSYNC_Msk;
+}
+
+static int numaker_usbd_send_msg(const struct device *dev, const struct numaker_usbd_msg *msg)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ int err;
+
+ err = k_msgq_put(priv->msgq, msg, K_NO_WAIT);
+ if (err < 0) {
+ /* Try to recover by S/W reconnect */
+ struct numaker_usbd_msg msg_reconn = {
+ .type = NUMAKER_USBD_MSG_TYPE_SW_RECONN,
+ };
+
+ LOG_ERR("Message queue overflow");
+
+ /* Discard all not yet received messages for error recovery below */
+ k_msgq_purge(priv->msgq);
+
+ err = k_msgq_put(priv->msgq, &msg_reconn, K_NO_WAIT);
+ if (err < 0) {
+ LOG_ERR("Message queue overflow again");
+ }
+ }
+
+ return err;
+}
+
+static int numaker_usbd_hw_setup(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+ int err;
+ struct numaker_scc_subsys scc_subsys;
+
+ /* Reset controller ready? */
+ if (!device_is_ready(config->reset.dev)) {
+ LOG_ERR("Reset controller not ready");
+ return -ENODEV;
+ }
+
+ SYS_UnlockReg();
+
+ /* Configure USB PHY for USBD */
+ SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) |
+ (SYS_USBPHY_USBROLE_STD_USBD | SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk);
+
+ /* Invoke Clock controller to enable module clock */
+ memset(&scc_subsys, 0x00, sizeof(scc_subsys));
+ scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
+ scc_subsys.pcc.clk_modidx = config->clk_modidx;
+ scc_subsys.pcc.clk_src = config->clk_src;
+ scc_subsys.pcc.clk_div = config->clk_div;
+
+ /* Equivalent to CLK_EnableModuleClock() */
+ err = clock_control_on(config->clkctrl_dev, (clock_control_subsys_t)&scc_subsys);
+ if (err < 0) {
+ goto cleanup;
+ }
+ /* Equivalent to CLK_SetModuleClock() */
+ err = clock_control_configure(config->clkctrl_dev, (clock_control_subsys_t)&scc_subsys,
+ NULL);
+ if (err < 0) {
+ goto cleanup;
+ }
+
+ /* Configure pinmux (NuMaker's SYS MFP) */
+ err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+ if (err < 0) {
+ goto cleanup;
+ }
+
+ /* Invoke Reset controller to reset module to default state */
+ /* Equivalent to SYS_ResetModule()
+ */
+ reset_line_toggle_dt(&config->reset);
+
+ /* Initialize USBD engine */
+ /* NOTE: BSP USBD driver: ATTR = 0x7D0 */
+ base->ATTR = USBD_ATTR_BYTEM_Msk | BIT(9) | USBD_ATTR_DPPUEN_Msk | USBD_ATTR_USBEN_Msk |
+ BIT(6) | USBD_ATTR_PHYEN_Msk;
+
+ /* Set SE0 for S/W disconnect */
+ numaker_usbd_sw_disconnect(dev);
+
+ /* NOTE: Ignore DT maximum-speed with USBD fixed to full-speed */
+
+ /* Initialize IRQ */
+ config->irq_config_func(dev);
+
+cleanup:
+
+ SYS_LockReg();
+
+ return err;
+}
+
+static void numaker_usbd_hw_shutdown(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+ struct numaker_scc_subsys scc_subsys;
+
+ SYS_UnlockReg();
+
+ /* Uninitialize IRQ */
+ config->irq_unconfig_func(dev);
+
+ /* Set SE0 for S/W disconnect */
+ numaker_usbd_sw_disconnect(dev);
+
+ /* Disable USB PHY */
+ base->ATTR &= ~USBD_PHY_EN;
+
+ /* Invoke Clock controller to disable module clock */
+ memset(&scc_subsys, 0x00, sizeof(scc_subsys));
+ scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
+ scc_subsys.pcc.clk_modidx = config->clk_modidx;
+
+ /* Equivalent to CLK_DisableModuleClock() */
+ clock_control_off(config->clkctrl_dev, (clock_control_subsys_t)&scc_subsys);
+
+ /* Invoke Reset controller to reset module to default state */
+ /* Equivalent to SYS_ResetModule() */
+ reset_line_toggle_dt(&config->reset);
+
+ SYS_LockReg();
+}
+
+/* Interrupt top half processing for bus reset */
+static void numaker_usbd_bus_reset_th(const struct device *dev)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ USBD_EP_T *ep_base;
+
+ for (uint32_t i = 0ul; i < priv->ep_pool_size; i++) {
+ ep_base = numaker_usbd_ep_base(dev, EP0 + i);
+
+ /* Cancel EP on-going transaction */
+ ep_base->CFGP |= USBD_CFGP_CLRRDY_Msk;
+
+ /* Reset EP to unstalled */
+ ep_base->CFGP &= ~USBD_CFGP_SSTALL_Msk;
+
+ /* Reset EP data toggle bit to 0 */
+ ep_base->CFG &= ~USBD_CFG_DSQSYNC_Msk;
+
+ /* Except EP0/EP1 kept resident for CTRL OUT/IN, disable all other EPs */
+ if (i >= 2) {
+ ep_base->CFG = 0;
+ }
+ }
+
+ numaker_usbd_reset_addr(dev);
+}
+
+/* USBD SRAM base for DMA */
+static inline uint32_t numaker_usbd_buf_base(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+
+ return ((uint32_t)base + 0x800ul);
+}
+
+/* Copy Setup packet to user buffer */
+static void numaker_usbd_setup_copy_to_user(const struct device *dev, uint8_t *usrbuf)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+ uint32_t dmabuf_addr;
+
+ dmabuf_addr = numaker_usbd_buf_base(dev) + (base->STBUFSEG & USBD_STBUFSEG_STBUFSEG_Msk);
+
+ bytecpy(usrbuf, (uint8_t *)dmabuf_addr, 8ul);
+}
+
+/* Copy data to user buffer
+ *
+ * size_p holds size to copy/copied on input/output
+ */
+static void numaker_usbd_ep_copy_to_user(struct numaker_usbd_ep *ep_cur, uint8_t *usrbuf,
+ uint32_t *size_p, uint32_t *rmn_p)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+ uint32_t dmabuf_addr;
+ uint32_t data_rmn;
+
+ __ASSERT_NO_MSG(size_p);
+ __ASSERT_NO_MSG(ep_cur->dmabuf_valid);
+
+ dmabuf_addr = numaker_usbd_buf_base(dev) + ep_base->BUFSEG;
+
+ /* NOTE: See comment on mxpld_ctrlout for why make one copy of CTRL OUT's MXPLD */
+ if (ep_cur->addr == USB_CONTROL_EP_OUT) {
+ data_rmn = ep_cur->mxpld_ctrlout;
+ } else {
+ data_rmn = ep_base->MXPLD;
+ }
+
+ *size_p = MIN(*size_p, data_rmn);
+
+ bytecpy(usrbuf, (uint8_t *)dmabuf_addr, *size_p);
+ data_rmn -= *size_p;
+
+ if (rmn_p) {
+ *rmn_p = data_rmn;
+ }
+}
+
+/* Copy data from user buffer
+ *
+ * size_p holds size to copy/copied on input/output
+ */
+static void numaker_usbd_ep_copy_from_user(struct numaker_usbd_ep *ep_cur, const uint8_t *usrbuf,
+ uint32_t *size_p)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+ uint32_t dmabuf_addr;
+
+ __ASSERT_NO_MSG(size_p);
+ __ASSERT_NO_MSG(ep_cur->dmabuf_valid);
+ __ASSERT_NO_MSG(ep_cur->mps_valid);
+ __ASSERT_NO_MSG(ep_cur->mps <= ep_cur->dmabuf_size);
+
+ dmabuf_addr = numaker_usbd_buf_base(dev) + ep_base->BUFSEG;
+
+ *size_p = MIN(*size_p, ep_cur->mps);
+
+ bytecpy((uint8_t *)dmabuf_addr, (uint8_t *)usrbuf, *size_p);
+}
+
+static void numaker_usbd_ep_config_dmabuf(struct numaker_usbd_ep *ep_cur, uint32_t dmabuf_base,
+ uint32_t dmabuf_size)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ ep_base->BUFSEG = dmabuf_base;
+
+ ep_cur->dmabuf_valid = true;
+ ep_cur->dmabuf_base = dmabuf_base;
+ ep_cur->dmabuf_size = dmabuf_size;
+}
+
+static void numaker_usbd_ep_abort(struct numaker_usbd_ep *ep_cur)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ /* Abort EP on-going transaction */
+ ep_base->CFGP |= USBD_CFGP_CLRRDY_Msk;
+
+ if (ep_cur->addr_valid) {
+ udc_ep_set_busy(dev, ep_cur->addr, false);
+ }
+}
+
+/* Configure EP major common parts */
+static void numaker_usbd_ep_config_major(struct numaker_usbd_ep *ep_cur,
+ struct udc_ep_config *const ep_cfg)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ ep_cur->mps_valid = true;
+ ep_cur->mps = ep_cfg->mps;
+
+ /* Configure EP transfer type, DATA0/1 toggle, direction, number, etc. */
+ ep_cur->ep_hw_cfg = 0;
+
+ /* Clear STALL Response in Setup stage */
+ if ((ep_cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) == USB_EP_TYPE_CONTROL) {
+ ep_cur->ep_hw_cfg |= USBD_CFG_CSTALL;
+ }
+
+ /* Default to DATA0 */
+ ep_cur->ep_hw_cfg &= ~USBD_CFG_DSQSYNC_Msk;
+
+ /* Endpoint IN/OUT, though, default to disabled */
+ ep_cur->ep_hw_cfg |= USBD_CFG_EPMODE_DISABLE;
+
+ /* Isochronous or not */
+ if ((ep_cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) == USB_EP_TYPE_ISO) {
+ ep_cur->ep_hw_cfg |= USBD_CFG_TYPE_ISO;
+ }
+
+ /* Endpoint index */
+ ep_cur->ep_hw_cfg |=
+ (USB_EP_GET_IDX(ep_cfg->addr) << USBD_CFG_EPNUM_Pos) & USBD_CFG_EPNUM_Msk;
+
+ ep_base->CFG = ep_cur->ep_hw_cfg;
+}
+
+static void numaker_usbd_ep_enable(struct numaker_usbd_ep *ep_cur)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ /* For safe, EP (re-)enable from clean state */
+ numaker_usbd_ep_abort(ep_cur);
+ numaker_usbd_ep_clear_stall_n_data_toggle(ep_cur);
+
+ /* Enable EP to IN/OUT */
+ ep_cur->ep_hw_cfg &= ~USBD_CFG_STATE_Msk;
+ if (USB_EP_DIR_IS_IN(ep_cur->addr)) {
+ ep_cur->ep_hw_cfg |= USBD_CFG_EPMODE_IN;
+ } else {
+ ep_cur->ep_hw_cfg |= USBD_CFG_EPMODE_OUT;
+ }
+
+ ep_base->CFG = ep_cur->ep_hw_cfg;
+
+ /* For USBD, no separate EP interrupt control */
+}
+
+static void numaker_usbd_ep_disable(struct numaker_usbd_ep *ep_cur)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ /* For USBD, no separate EP interrupt control */
+
+ /* Disable EP */
+ ep_cur->ep_hw_cfg = (ep_cur->ep_hw_cfg & ~USBD_CFG_STATE_Msk) | USBD_CFG_EPMODE_DISABLE;
+ ep_base->CFG = ep_cur->ep_hw_cfg;
+}
+
+/* Start EP data transaction */
+static void udc_numaker_ep_trigger(struct numaker_usbd_ep *ep_cur, uint32_t len)
+{
+ const struct device *dev = ep_cur->dev;
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_cur->ep_hw_idx);
+
+ if (ep_cur->addr_valid) {
+ udc_ep_set_busy(dev, ep_cur->addr, true);
+ }
+
+ ep_base->MXPLD = len;
+}
+
+static struct numaker_usbd_ep *numaker_usbd_ep_mgmt_alloc_ep(const struct device *dev)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ struct numaker_usbd_ep_mgmt *ep_mgmt = &priv->ep_mgmt;
+ struct numaker_usbd_ep *ep_cur = NULL;
+
+ if (ep_mgmt->ep_idx < priv->ep_pool_size) {
+ ep_cur = priv->ep_pool + ep_mgmt->ep_idx;
+ ep_mgmt->ep_idx++;
+
+ __ASSERT_NO_MSG(!ep_cur->valid);
+
+ /* Indicate this EP H/W context is allocated */
+ ep_cur->valid = true;
+ }
+
+ return ep_cur;
+}
+
+/* Allocate DMA buffer
+ *
+ * Return -ENOMEM on OOM error, or 0 on success with DMA buffer base/size (rounded up) allocated
+ */
+static int numaker_usbd_ep_mgmt_alloc_dmabuf(const struct device *dev, uint32_t size,
+ uint32_t *dmabuf_base_p, uint32_t *dmabuf_size_p)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ struct numaker_usbd_ep_mgmt *ep_mgmt = &priv->ep_mgmt;
+
+ __ASSERT_NO_MSG(dmabuf_base_p);
+ __ASSERT_NO_MSG(dmabuf_size_p);
+
+ /* Required to be 8-byte aligned */
+ size = ROUND_UP(size, 8);
+
+ ep_mgmt->dmabuf_pos += size;
+ if (ep_mgmt->dmabuf_pos > config->dmabuf_size) {
+ ep_mgmt->dmabuf_pos -= size;
+ return -ENOMEM;
+ }
+
+ *dmabuf_base_p = ep_mgmt->dmabuf_pos - size;
+ *dmabuf_size_p = size;
+ return 0;
+}
+
+/* Initialize all EP H/W contexts */
+static void numaker_usbd_ep_mgmt_init(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ USBD_T *const base = config->base;
+ struct numaker_usbd_ep_mgmt *ep_mgmt = &priv->ep_mgmt;
+
+ struct numaker_usbd_ep *ep_cur;
+ struct numaker_usbd_ep *ep_end;
+
+ /* Initialize all fields to zero for clean state */
+ memset(ep_mgmt, 0x00, sizeof(*ep_mgmt));
+
+ ep_cur = priv->ep_pool;
+ ep_end = priv->ep_pool + priv->ep_pool_size;
+
+ /* Initialize all EP H/W contexts */
+ for (; ep_cur != ep_end; ep_cur++) {
+ /* Zero-initialize */
+ memset(ep_cur, 0x00, sizeof(*ep_cur));
+
+ /* Pointer to the containing device */
+ ep_cur->dev = dev;
+
+ /* BSP USBD driver EP handle */
+ ep_cur->ep_hw_idx = EP0 + (ep_cur - priv->ep_pool);
+ }
+
+ /* Reserve 1st/2nd EP H/W contexts (BSP USBD driver EP0/EP1) for CTRL OUT/IN */
+ ep_mgmt->ep_idx = 2;
+
+ /* Reserve DMA buffer for Setup/CTRL OUT/CTRL IN, starting from 0 */
+ ep_mgmt->dmabuf_pos = 0;
+
+ /* Configure DMA buffer for Setup packet */
+ base->STBUFSEG = ep_mgmt->dmabuf_pos;
+ ep_mgmt->dmabuf_pos += NUMAKER_USBD_DMABUF_SIZE_SETUP;
+
+ /* Reserve 1st EP H/W context (BSP USBD driver EP0) for CTRL OUT */
+ ep_cur = priv->ep_pool + 0;
+ ep_cur->valid = true;
+ ep_cur->addr_valid = true;
+ ep_cur->addr = USB_EP_GET_ADDR(0, USB_EP_DIR_OUT);
+ numaker_usbd_ep_config_dmabuf(ep_cur, ep_mgmt->dmabuf_pos,
+ NUMAKER_USBD_DMABUF_SIZE_CTRLOUT);
+ ep_mgmt->dmabuf_pos += NUMAKER_USBD_DMABUF_SIZE_CTRLOUT;
+ ep_cur->mps_valid = true;
+ ep_cur->mps = NUMAKER_USBD_DMABUF_SIZE_CTRLOUT;
+
+ /* Reserve 2nd EP H/W context (BSP USBD driver EP1) for CTRL IN */
+ ep_cur = priv->ep_pool + 1;
+ ep_cur->valid = true;
+ ep_cur->addr_valid = true;
+ ep_cur->addr = USB_EP_GET_ADDR(0, USB_EP_DIR_IN);
+ numaker_usbd_ep_config_dmabuf(ep_cur, ep_mgmt->dmabuf_pos, NUMAKER_USBD_DMABUF_SIZE_CTRLIN);
+ ep_mgmt->dmabuf_pos += NUMAKER_USBD_DMABUF_SIZE_CTRLIN;
+ ep_cur->mps_valid = true;
+ ep_cur->mps = NUMAKER_USBD_DMABUF_SIZE_CTRLIN;
+}
+
+/* Find EP H/W context by EP address */
+static struct numaker_usbd_ep *numaker_usbd_ep_mgmt_find_ep(const struct device *dev,
+ const uint8_t ep)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ struct numaker_usbd_ep *ep_cur = priv->ep_pool;
+ struct numaker_usbd_ep *ep_end = priv->ep_pool + priv->ep_pool_size;
+
+ for (; ep_cur != ep_end; ep_cur++) {
+ if (!ep_cur->valid) {
+ continue;
+ }
+
+ if (!ep_cur->addr_valid) {
+ continue;
+ }
+
+ if (ep == ep_cur->addr) {
+ return ep_cur;
+ }
+ }
+
+ return NULL;
+}
+
+/* Bind EP H/W context to EP address */
+static struct numaker_usbd_ep *numaker_usbd_ep_mgmt_bind_ep(const struct device *dev,
+ const uint8_t ep)
+{
+ struct numaker_usbd_ep *ep_cur = numaker_usbd_ep_mgmt_find_ep(dev, ep);
+
+ if (!ep_cur) {
+ ep_cur = numaker_usbd_ep_mgmt_alloc_ep(dev);
+
+ if (!ep_cur) {
+ return NULL;
+ }
+
+ /* Bind EP H/W context to EP address */
+ ep_cur->addr = ep;
+ ep_cur->addr_valid = true;
+ }
+
+ /* Assert EP H/W context bound to EP address */
+ __ASSERT_NO_MSG(ep_cur->valid);
+ __ASSERT_NO_MSG(ep_cur->addr_valid);
+ __ASSERT_NO_MSG(ep_cur->addr == ep);
+
+ return ep_cur;
+}
+
+static int numaker_usbd_xfer_out(const struct device *dev, uint8_t ep, bool strict)
+{
+ struct net_buf *buf;
+ struct numaker_usbd_ep *ep_cur;
+
+ if (!USB_EP_DIR_IS_OUT(ep)) {
+ LOG_ERR("Invalid EP address 0x%02x for data out", ep);
+ return -EINVAL;
+ }
+
+ if (udc_ep_is_busy(dev, ep)) {
+ if (strict) {
+ LOG_ERR("EP 0x%02x busy", ep);
+ return -EAGAIN;
+ }
+
+ return 0;
+ }
+
+ buf = udc_buf_peek(dev, ep);
+ if (buf == NULL) {
+ if (strict) {
+ LOG_ERR("No buffer queued for EP 0x%02x", ep);
+ return -ENODATA;
+ }
+
+ return 0;
+ }
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep);
+ return -ENODEV;
+ }
+
+ udc_numaker_ep_trigger(ep_cur, ep_cur->mps);
+
+ return 0;
+}
+
+static int numaker_usbd_xfer_in(const struct device *dev, uint8_t ep, bool strict)
+{
+ struct net_buf *buf;
+ struct numaker_usbd_ep *ep_cur;
+ uint32_t data_len;
+
+ if (!USB_EP_DIR_IS_IN(ep)) {
+ LOG_ERR("Invalid EP address 0x%02x for data in", ep);
+ return -EINVAL;
+ }
+
+ if (udc_ep_is_busy(dev, ep)) {
+ if (strict) {
+ LOG_ERR("EP 0x%02x busy", ep);
+ return -EAGAIN;
+ }
+
+ return 0;
+ }
+
+ buf = udc_buf_peek(dev, ep);
+ if (buf == NULL) {
+ if (strict) {
+ LOG_ERR("No buffer queued for EP 0x%02x", ep);
+ return -ENODATA;
+ }
+
+ return 0;
+ }
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep);
+ if (!ep_cur) {
+ LOG_ERR("ep=0x%02x", ep);
+ return -ENODEV;
+ }
+
+ data_len = buf->len;
+ if (data_len) {
+ numaker_usbd_ep_copy_from_user(ep_cur, buf->data, &data_len);
+ net_buf_pull(buf, data_len);
+ } else if (udc_ep_buf_has_zlp(buf)) {
+ /* zlp, send exactly once */
+ udc_ep_buf_clear_zlp(buf);
+ } else {
+ /* initially empty net_buf, send exactly once */
+ }
+
+ udc_numaker_ep_trigger(ep_cur, data_len);
+
+ return 0;
+}
+
+static int numaker_usbd_ctrl_feed_dout(const struct device *dev, const size_t length)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ struct udc_ep_config *ep_cfg;
+ struct net_buf *buf;
+
+ ep_cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
+ if (ep_cfg == NULL) {
+ LOG_ERR("Bind udc_ep_config: ep=0x%02x", USB_CONTROL_EP_OUT);
+ return -ENODEV;
+ }
+
+ buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
+ if (buf == NULL) {
+ LOG_ERR("Allocate net_buf: ep=0x%02x", USB_CONTROL_EP_OUT);
+ return -ENOMEM;
+ }
+ priv->ctrlout_tailroom = length;
+
+ k_fifo_put(&ep_cfg->fifo, buf);
+
+ return numaker_usbd_xfer_out(dev, ep_cfg->addr, true);
+}
+
+/* Message handler for Setup transaction completed */
+static int numaker_usbd_msg_handle_setup(const struct device *dev, struct numaker_usbd_msg *msg)
+{
+ int err;
+ uint8_t ep;
+ struct numaker_usbd_ep *ep_cur;
+ struct net_buf *buf;
+ uint8_t *data_ptr;
+
+ __ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_SETUP);
+
+ ep = USB_CONTROL_EP_OUT;
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep);
+ return -ENODEV;
+ }
+
+ /* We should have reserved 1st/2nd EP H/W contexts for CTRL OUT/IN */
+ __ASSERT_NO_MSG(ep_cur->addr == USB_CONTROL_EP_OUT);
+ __ASSERT_NO_MSG((ep_cur + 1)->addr == USB_CONTROL_EP_IN);
+
+ /* Abort previous CTRL OUT/IN */
+ numaker_usbd_ep_abort(ep_cur);
+ numaker_usbd_ep_abort(ep_cur + 1);
+
+ /* CTRL OUT/IN reset to unstalled by H/W on receive of Setup packet */
+ numaker_usbd_ep_sync_udc_halt(ep_cur, false);
+ numaker_usbd_ep_sync_udc_halt(ep_cur + 1, false);
+
+ buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, 8);
+ if (buf == NULL) {
+ LOG_ERR("Failed to allocate for Setup");
+ return -ENOMEM;
+ }
+
+ udc_ep_buf_set_setup(buf);
+ data_ptr = net_buf_tail(buf);
+ numaker_usbd_setup_copy_to_user(dev, data_ptr);
+ net_buf_add(buf, 8);
+
+ /* Update to next stage of CTRL transfer */
+ udc_ctrl_update_stage(dev, buf);
+
+ if (udc_ctrl_stage_is_data_out(dev)) {
+ /* Allocate and feed buffer for DATA OUT stage */
+ err = numaker_usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
+ if (err == -ENOMEM) {
+ err = udc_submit_ep_event(dev, buf, err);
+ }
+ } else if (udc_ctrl_stage_is_data_in(dev)) {
+ err = udc_ctrl_submit_s_in_status(dev);
+ } else {
+ err = udc_ctrl_submit_s_status(dev);
+ }
+
+ return err;
+}
+
+/* Message handler for DATA OUT transaction completed */
+static int numaker_usbd_msg_handle_out(const struct device *dev, struct numaker_usbd_msg *msg)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ int err;
+ uint8_t ep;
+ struct numaker_usbd_ep *ep_cur;
+ struct net_buf *buf;
+ uint8_t *data_ptr;
+ uint32_t data_len;
+ uint32_t data_rmn;
+
+ __ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_OUT);
+
+ ep = msg->out.ep;
+
+ udc_ep_set_busy(dev, ep, false);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep);
+ return -ENODEV;
+ }
+
+ buf = udc_buf_peek(dev, ep);
+ if (buf == NULL) {
+ LOG_ERR("No buffer queued for ep=0x%02x", ep);
+ return -ENODATA;
+ }
+
+ if (ep == USB_CONTROL_EP_OUT) {
+ __ASSERT_NO_MSG(net_buf_tailroom(buf) >= priv->ctrlout_tailroom);
+ data_len = priv->ctrlout_tailroom;
+ } else {
+ data_len = net_buf_tailroom(buf);
+ }
+ data_ptr = net_buf_tail(buf);
+ numaker_usbd_ep_copy_to_user(ep_cur, data_ptr, &data_len, &data_rmn);
+ net_buf_add(buf, data_len);
+ if (ep == USB_CONTROL_EP_OUT) {
+ __ASSERT_NO_MSG(priv->ctrlout_tailroom >= data_len);
+ priv->ctrlout_tailroom -= data_len;
+ }
+
+ if (data_rmn) {
+ LOG_ERR("Buffer queued for ep=0x%02x cannot accommodate packet", ep);
+ return -ENOBUFS;
+ }
+
+ /* CTRL DATA OUT/STATUS OUT stage completed */
+ if (ep == USB_CONTROL_EP_OUT && priv->ctrlout_tailroom != 0) {
+ goto next_xfer;
+ }
+
+ /* To submit the peeked buffer */
+ udc_buf_get(dev, ep);
+
+ if (ep == USB_CONTROL_EP_OUT) {
+ if (udc_ctrl_stage_is_status_out(dev)) {
+ /* s-in-status finished */
+ err = udc_ctrl_submit_status(dev, buf);
+ if (err < 0) {
+ LOG_ERR("udc_ctrl_submit_status failed for s-in-status: %d", err);
+ return err;
+ }
+ }
+
+ /* Update to next stage of CTRL transfer */
+ udc_ctrl_update_stage(dev, buf);
+
+ if (udc_ctrl_stage_is_status_in(dev)) {
+ err = udc_ctrl_submit_s_out_status(dev, buf);
+ if (err < 0) {
+ LOG_ERR("udc_ctrl_submit_s_out_status failed for s-out-status: %d",
+ err);
+ return err;
+ }
+ }
+ } else {
+ err = udc_submit_ep_event(dev, buf, 0);
+ if (err < 0) {
+ LOG_ERR("udc_submit_ep_event failed for ep=0x%02x: %d", ep, err);
+ return err;
+ }
+ }
+
+next_xfer:
+ /* Continue with next DATA OUT transaction on request */
+ numaker_usbd_xfer_out(dev, ep, false);
+
+ return 0;
+}
+
+/* Message handler for DATA IN transaction completed */
+static int numaker_usbd_msg_handle_in(const struct device *dev, struct numaker_usbd_msg *msg)
+{
+ int err;
+ uint8_t ep;
+ struct numaker_usbd_ep *ep_cur;
+ struct net_buf *buf;
+
+ __ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_IN);
+
+ ep = msg->in.ep;
+
+ udc_ep_set_busy(dev, ep, false);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep);
+ return -ENODEV;
+ }
+
+ buf = udc_buf_peek(dev, ep);
+ if (buf == NULL) {
+ /* No DATA IN request */
+ return 0;
+ }
+
+ if (buf->len || udc_ep_buf_has_zlp(buf)) {
+ goto xfer_next;
+ }
+
+ /* To submit the peeked buffer */
+ udc_buf_get(dev, ep);
+
+ if (ep == USB_CONTROL_EP_IN) {
+ if (udc_ctrl_stage_is_status_in(dev) || udc_ctrl_stage_is_no_data(dev)) {
+ /* s-out-status/s-status finished */
+ err = udc_ctrl_submit_status(dev, buf);
+ if (err < 0) {
+ LOG_ERR("udc_ctrl_submit_status failed for s-out-status/s-status: "
+ "%d",
+ err);
+ return err;
+ }
+ }
+
+ /* Update to next stage of CTRL transfer */
+ udc_ctrl_update_stage(dev, buf);
+
+ if (udc_ctrl_stage_is_status_out(dev)) {
+ /* DATA IN stage finished, release buffer */
+ net_buf_unref(buf);
+
+ /* Allocate and feed buffer for STATUS OUT stage */
+ err = numaker_usbd_ctrl_feed_dout(dev, 0);
+ if (err < 0) {
+ LOG_ERR("ctrl_feed_dout failed for status out: %d", err);
+ return err;
+ }
+ }
+ } else {
+ err = udc_submit_ep_event(dev, buf, 0);
+ if (err < 0) {
+ LOG_ERR("udc_submit_ep_event failed for ep=0x%02x: %d", ep, err);
+ return err;
+ }
+ }
+
+xfer_next:
+ /* Continue with next DATA IN transaction on request */
+ numaker_usbd_xfer_in(dev, ep, false);
+
+ return 0;
+}
+
+/* Message handler for queued transfer re-activated */
+static int numaker_usbd_msg_handle_xfer(const struct device *dev, struct numaker_usbd_msg *msg)
+{
+ uint8_t ep;
+
+ __ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_XFER);
+
+ ep = msg->xfer.ep;
+
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ numaker_usbd_xfer_out(dev, ep, false);
+ } else {
+ numaker_usbd_xfer_in(dev, ep, false);
+ }
+
+ return 0;
+}
+
+/* Message handler for S/W reconnect */
+static int numaker_usbd_msg_handle_sw_reconn(const struct device *dev, struct numaker_usbd_msg *msg)
+{
+ __ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_SW_RECONN);
+
+ /* S/W reconnect for error recovery */
+ numaker_usbd_sw_reconnect(dev);
+
+ return 0;
+}
+
+static void numaker_usbd_msg_handler(const struct device *dev)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ int err;
+ struct numaker_usbd_msg msg;
+
+ while (true) {
+ if (k_msgq_get(priv->msgq, &msg, K_FOREVER)) {
+ continue;
+ }
+
+ err = 0;
+
+ udc_lock_internal(dev, K_FOREVER);
+
+ switch (msg.type) {
+ case NUMAKER_USBD_MSG_TYPE_SETUP:
+ err = numaker_usbd_msg_handle_setup(dev, &msg);
+ break;
+
+ case NUMAKER_USBD_MSG_TYPE_OUT:
+ err = numaker_usbd_msg_handle_out(dev, &msg);
+ break;
+
+ case NUMAKER_USBD_MSG_TYPE_IN:
+ err = numaker_usbd_msg_handle_in(dev, &msg);
+ break;
+
+ case NUMAKER_USBD_MSG_TYPE_XFER:
+ err = numaker_usbd_msg_handle_xfer(dev, &msg);
+ break;
+
+ case NUMAKER_USBD_MSG_TYPE_SW_RECONN:
+ err = numaker_usbd_msg_handle_sw_reconn(dev, &msg);
+ break;
+
+ default:
+ __ASSERT_NO_MSG(false);
+ }
+
+ udc_unlock_internal(dev);
+
+ if (err) {
+ udc_submit_event(dev, UDC_EVT_ERROR, err);
+ }
+ }
+}
+
+static void numaker_udbd_isr(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_numaker_data *priv = udc_get_private(dev);
+ USBD_T *const base = config->base;
+
+ struct numaker_usbd_msg msg = {0};
+
+ uint32_t volatile usbd_intsts = base->INTSTS;
+ uint32_t volatile usbd_bus_state = base->ATTR;
+
+ /* USB plug-in/unplug */
+ if (usbd_intsts & USBD_INTSTS_FLDET) {
+ /* Floating detect */
+ base->INTSTS = USBD_INTSTS_FLDET;
+
+ if (base->VBUSDET & USBD_VBUSDET_VBUSDET_Msk) {
+ /* USB plug-in */
+
+ /* Enable back USB/PHY */
+ base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+
+ /* UDC stack would handle bottom-half processing */
+ udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
+
+ LOG_DBG("USB plug-in");
+ } else {
+ /* USB unplug */
+
+ /* Disable USB */
+ base->ATTR &= ~USBD_USB_EN;
+
+ /* UDC stack would handle bottom-half processing */
+ udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
+
+ LOG_DBG("USB unplug");
+ }
+ }
+
+ /* USB wake-up */
+ if (usbd_intsts & USBD_INTSTS_WAKEUP) {
+ /* Clear event flag */
+ base->INTSTS = USBD_INTSTS_WAKEUP;
+
+ LOG_DBG("USB wake-up");
+ }
+
+ /* USB reset/suspend/resume */
+ if (usbd_intsts & USBD_INTSTS_BUS) {
+ /* Clear event flag */
+ base->INTSTS = USBD_INTSTS_BUS;
+
+ if (usbd_bus_state & USBD_STATE_USBRST) {
+ /* Bus reset */
+
+ /* Enable back USB/PHY */
+ base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+
+ /* Bus reset top half */
+ numaker_usbd_bus_reset_th(dev);
+
+ /* UDC stack would handle bottom-half processing,
+ * including reset device address (udc_set_address),
+ * un-configure device (udc_ep_disable), etc.
+ */
+ udc_submit_event(dev, UDC_EVT_RESET, 0);
+
+ LOG_DBG("USB reset");
+ }
+ if (usbd_bus_state & USBD_STATE_SUSPEND) {
+ /* Enable USB but disable PHY */
+ base->ATTR &= ~USBD_PHY_EN;
+
+ /* UDC stack would handle bottom-half processing */
+ udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
+
+ LOG_DBG("USB suspend");
+ }
+ if (usbd_bus_state & USBD_STATE_RESUME) {
+ /* Enable back USB/PHY */
+ base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+
+ /* UDC stack would handle bottom-half processing */
+ udc_submit_event(dev, UDC_EVT_RESUME, 0);
+
+ LOG_DBG("USB resume");
+ }
+ }
+
+ /* USB SOF */
+ if (usbd_intsts & USBD_INTSTS_SOFIF_Msk) {
+ /* Clear event flag */
+ base->INTSTS = USBD_INTSTS_SOFIF_Msk;
+
+ /* UDC stack would handle bottom-half processing */
+ udc_submit_event(dev, UDC_EVT_SOF, 0);
+ }
+
+ /* USB Setup/EP */
+ if (usbd_intsts & USBD_INTSTS_USB) {
+ uint32_t epintsts;
+
+ /* Setup event */
+ if (usbd_intsts & USBD_INTSTS_SETUP) {
+ USBD_EP_T *ep0_base = numaker_usbd_ep_base(dev, EP0);
+ USBD_EP_T *ep1_base = numaker_usbd_ep_base(dev, EP1);
+
+ /* Clear event flag */
+ base->INTSTS = USBD_INTSTS_SETUP;
+
+ /* Clear the data IN/OUT ready flag of control endpoints */
+ ep0_base->CFGP |= USBD_CFGP_CLRRDY_Msk;
+ ep1_base->CFGP |= USBD_CFGP_CLRRDY_Msk;
+
+ /* By USB spec, following transactions, regardless of Data/Status stage,
+ * will always be DATA1
+ */
+ ep0_base->CFG |= USBD_CFG_DSQSYNC_Msk;
+ ep1_base->CFG |= USBD_CFG_DSQSYNC_Msk;
+
+ /* Message for bottom-half processing */
+ /* NOTE: In Zephyr USB device stack, Setup packet is passed via
+ * CTRL OUT EP
+ */
+ msg.type = NUMAKER_USBD_MSG_TYPE_SETUP;
+ numaker_usbd_setup_copy_to_user(dev, msg.setup.packet);
+ numaker_usbd_send_msg(dev, &msg);
+ }
+
+ /* EP events */
+ epintsts = base->EPINTSTS;
+
+ base->EPINTSTS = epintsts;
+
+ while (epintsts) {
+ uint32_t ep_hw_idx = u32_count_trailing_zeros(epintsts);
+ USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_hw_idx);
+ uint8_t ep_dir;
+ uint8_t ep_idx;
+ uint8_t ep;
+
+ /* We don't enable INNAKEN interrupt, so as long as EP event occurs,
+ * we can just regard one data transaction has completed (ACK for
+ * CTRL/BULK/INT or no-ACK for Iso), that is, no need to check EPSTS0,
+ * EPSTS1, etc.
+ */
+
+ /* EP direction, number, and address */
+ ep_dir = ((ep_base->CFG & USBD_CFG_STATE_Msk) == USBD_CFG_EPMODE_IN)
+ ? USB_EP_DIR_IN
+ : USB_EP_DIR_OUT;
+ ep_idx = (ep_base->CFG & USBD_CFG_EPNUM_Msk) >> USBD_CFG_EPNUM_Pos;
+ ep = USB_EP_GET_ADDR(ep_idx, ep_dir);
+
+ /* NOTE: See comment in udc_numaker_set_address()'s implementation
+ * for safe place to change USB device address
+ */
+ if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_IN)) {
+ numaker_usbd_set_addr(dev);
+ }
+
+ /* NOTE: See comment on mxpld_ctrlout for why make one copy of
+ * CTRL OUT's MXPLD
+ */
+ if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_OUT)) {
+ struct numaker_usbd_ep *ep_ctrlout = priv->ep_pool + 0;
+ USBD_EP_T *ep_ctrlout_base =
+ numaker_usbd_ep_base(dev, ep_ctrlout->ep_hw_idx);
+
+ ep_ctrlout->mxpld_ctrlout = ep_ctrlout_base->MXPLD;
+ }
+
+ /* Message for bottom-half processing */
+ if (USB_EP_DIR_IS_OUT(ep)) {
+ msg.type = NUMAKER_USBD_MSG_TYPE_OUT;
+ msg.out.ep = ep;
+ } else {
+ msg.type = NUMAKER_USBD_MSG_TYPE_IN;
+ msg.in.ep = ep;
+ }
+ numaker_usbd_send_msg(dev, &msg);
+
+ /* Have handled this EP and go next */
+ epintsts &= ~BIT(ep_hw_idx);
+ }
+ }
+}
+
+static enum udc_bus_speed udc_numaker_device_speed(const struct device *dev)
+{
+ return UDC_BUS_SPEED_FS;
+}
+
+static int udc_numaker_ep_enqueue(const struct device *dev, struct udc_ep_config *const ep_cfg,
+ struct net_buf *buf)
+{
+ struct numaker_usbd_msg msg = {0};
+
+ LOG_DBG("%p enqueue %p", dev, buf);
+ udc_buf_put(ep_cfg, buf);
+
+ /* Resume the EP's queued transfer */
+ if (!ep_cfg->stat.halted) {
+ msg.type = NUMAKER_USBD_MSG_TYPE_XFER;
+ msg.xfer.ep = ep_cfg->addr;
+ numaker_usbd_send_msg(dev, &msg);
+ }
+
+ return 0;
+}
+
+static int udc_numaker_ep_dequeue(const struct device *dev, struct udc_ep_config *const ep_cfg)
+{
+ struct net_buf *buf;
+ struct numaker_usbd_ep *ep_cur;
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep_cfg->addr);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep_cfg->addr);
+ return -ENODEV;
+ }
+
+ numaker_usbd_ep_abort(ep_cur);
+
+ buf = udc_buf_get_all(dev, ep_cfg->addr);
+ if (buf) {
+ udc_submit_ep_event(dev, buf, -ECONNABORTED);
+ }
+
+ return 0;
+}
+
+static int udc_numaker_ep_set_halt(const struct device *dev, struct udc_ep_config *const ep_cfg)
+{
+ struct numaker_usbd_ep *ep_cur;
+
+ LOG_DBG("Set halt ep 0x%02x", ep_cfg->addr);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep_cfg->addr);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep_cfg->addr);
+ return -ENODEV;
+ }
+
+ /* Set EP to stalled */
+ numaker_usbd_ep_set_stall(ep_cur);
+
+ return 0;
+}
+
+static int udc_numaker_ep_clear_halt(const struct device *dev, struct udc_ep_config *const ep_cfg)
+{
+ struct numaker_usbd_ep *ep_cur;
+ struct numaker_usbd_msg msg = {0};
+
+ LOG_DBG("Clear halt ep 0x%02x", ep_cfg->addr);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep_cfg->addr);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep_cfg->addr);
+ return -ENODEV;
+ }
+
+ /* Reset EP to unstalled and data toggle bit to 0 */
+ numaker_usbd_ep_clear_stall_n_data_toggle(ep_cur);
+
+ /* Resume the EP's queued transfer */
+ msg.type = NUMAKER_USBD_MSG_TYPE_XFER;
+ msg.xfer.ep = ep_cfg->addr;
+ numaker_usbd_send_msg(dev, &msg);
+
+ return 0;
+}
+
+static int udc_numaker_ep_enable(const struct device *dev, struct udc_ep_config *const ep_cfg)
+{
+ int err;
+ uint32_t dmabuf_base;
+ uint32_t dmabuf_size;
+ struct numaker_usbd_ep *ep_cur;
+
+ LOG_DBG("Enable ep 0x%02x", ep_cfg->addr);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep_cfg->addr);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep_cfg->addr);
+ return -ENODEV;
+ }
+
+ /* Configure EP DMA buffer */
+ if (!ep_cur->dmabuf_valid || ep_cur->dmabuf_size < ep_cfg->mps) {
+ /* Allocate DMA buffer */
+ err = numaker_usbd_ep_mgmt_alloc_dmabuf(dev, ep_cfg->mps, &dmabuf_base,
+ &dmabuf_size);
+ if (err < 0) {
+ LOG_ERR("Allocate DMA buffer failed");
+ return err;
+ }
+
+ /* Configure EP DMA buffer */
+ numaker_usbd_ep_config_dmabuf(ep_cur, dmabuf_base, dmabuf_size);
+ }
+
+ /* Configure EP majorly */
+ numaker_usbd_ep_config_major(ep_cur, ep_cfg);
+
+ /* Enable EP */
+ numaker_usbd_ep_enable(ep_cur);
+
+ return 0;
+}
+
+static int udc_numaker_ep_disable(const struct device *dev, struct udc_ep_config *const ep_cfg)
+{
+ struct numaker_usbd_ep *ep_cur;
+
+ LOG_DBG("Disable ep 0x%02x", ep_cfg->addr);
+
+ /* Bind EP H/W context to EP address */
+ ep_cur = numaker_usbd_ep_mgmt_bind_ep(dev, ep_cfg->addr);
+ if (!ep_cur) {
+ LOG_ERR("Bind EP H/W context: ep=0x%02x", ep_cfg->addr);
+ return -ENODEV;
+ }
+
+ /* Disable EP */
+ numaker_usbd_ep_disable(ep_cur);
+
+ return 0;
+}
+
+static int udc_numaker_host_wakeup(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ USBD_T *const base = config->base;
+
+ /* Enable back USB/PHY first */
+ base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
+
+ /* Then generate 'K' */
+ base->ATTR |= USBD_ATTR_RWAKEUP_Msk;
+ k_sleep(K_USEC(NUMAKER_USBD_BUS_RESUME_DRV_K_US));
+ base->ATTR ^= USBD_ATTR_RWAKEUP_Msk;
+
+ return 0;
+}
+
+static int udc_numaker_set_address(const struct device *dev, const uint8_t addr)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+
+ LOG_DBG("Set new address %u for %p", addr, dev);
+
+ /* NOTE: Timing for configuring USB device address into H/W is critical. It must be done
+ * in-between SET_ADDRESS control transfer and next transfer. For this, it is done in
+ * IN ACK ISR of SET_ADDRESS control transfer.
+ */
+ priv->addr = addr;
+
+ return 0;
+}
+
+static int udc_numaker_enable(const struct device *dev)
+{
+ LOG_DBG("Enable device %p", dev);
+
+ /* S/W connect */
+ numaker_usbd_sw_connect(dev);
+
+ return 0;
+}
+
+static int udc_numaker_disable(const struct device *dev)
+{
+ LOG_DBG("Enable device %p", dev);
+
+ /* S/W disconnect */
+ numaker_usbd_sw_disconnect(dev);
+
+ return 0;
+}
+
+static int udc_numaker_init(const struct device *dev)
+{
+ int err;
+
+ /* Initialize USBD H/W */
+ err = numaker_usbd_hw_setup(dev);
+ if (err < 0) {
+ LOG_ERR("Set up H/W: %d", err);
+ return err;
+ }
+
+ /* USB device address defaults to 0 */
+ numaker_usbd_reset_addr(dev);
+
+ /* Initialize all EP H/W contexts */
+ numaker_usbd_ep_mgmt_init(dev);
+
+ if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT, USB_EP_TYPE_CONTROL, 64, 0)) {
+ LOG_ERR("Failed to enable control endpoint");
+ return -EIO;
+ }
+
+ if (udc_ep_enable_internal(dev, USB_CONTROL_EP_IN, USB_EP_TYPE_CONTROL, 64, 0)) {
+ LOG_ERR("Failed to enable control endpoint");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int udc_numaker_shutdown(const struct device *dev)
+{
+ struct udc_numaker_data *priv = udc_get_private(dev);
+
+ if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
+ LOG_ERR("Failed to disable control endpoint");
+ return -EIO;
+ }
+
+ if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
+ LOG_ERR("Failed to disable control endpoint");
+ return -EIO;
+ }
+
+ /* Uninitialize USBD H/W */
+ numaker_usbd_hw_shutdown(dev);
+
+ /* Purge message queue */
+ k_msgq_purge(priv->msgq);
+
+ return 0;
+}
+
+static int udc_numaker_lock(const struct device *dev)
+{
+ return udc_lock_internal(dev, K_FOREVER);
+}
+
+static int udc_numaker_unlock(const struct device *dev)
+{
+ return udc_unlock_internal(dev);
+}
+
+static int udc_numaker_driver_preinit(const struct device *dev)
+{
+ const struct udc_numaker_config *config = dev->config;
+ struct udc_data *data = dev->data;
+ int err;
+
+ data->caps.rwup = true;
+ data->caps.addr_before_status = true;
+ data->caps.mps0 = UDC_MPS0_64;
+
+ /* Some soc series don't allow ISO IN/OUT to be assigned the same EP number.
+ * This is addressed by limiting all OUT/IN EP addresses in top/bottom halves,
+ * except CTRL OUT/IN.
+ */
+
+ for (int i = 0; i < config->ep_cfg_out_size; i++) {
+ /* Limit all OUT EP numbers to 0, 1~7 */
+ if (config->disallow_iso_inout_same && i != 0 && i >= 8) {
+ continue;
+ }
+
+ config->ep_cfg_out[i].caps.out = 1;
+ if (i == 0) {
+ config->ep_cfg_out[i].caps.control = 1;
+ config->ep_cfg_out[i].caps.mps = 64;
+ } else {
+ config->ep_cfg_out[i].caps.bulk = 1;
+ config->ep_cfg_out[i].caps.interrupt = 1;
+ config->ep_cfg_out[i].caps.iso = 1;
+ config->ep_cfg_out[i].caps.mps = 1023;
+ }
+
+ config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
+ err = udc_register_ep(dev, &config->ep_cfg_out[i]);
+ if (err != 0) {
+ LOG_ERR("Failed to register endpoint");
+ return err;
+ }
+ }
+
+ for (int i = 0; i < config->ep_cfg_in_size; i++) {
+ /* Limit all IN EP numbers to 0, 8~15 */
+ if (config->disallow_iso_inout_same && i != 0 && i < 8) {
+ continue;
+ }
+
+ config->ep_cfg_in[i].caps.in = 1;
+ if (i == 0) {
+ config->ep_cfg_in[i].caps.control = 1;
+ config->ep_cfg_in[i].caps.mps = 64;
+ } else {
+ config->ep_cfg_in[i].caps.bulk = 1;
+ config->ep_cfg_in[i].caps.interrupt = 1;
+ config->ep_cfg_in[i].caps.iso = 1;
+ config->ep_cfg_in[i].caps.mps = 1023;
+ }
+
+ config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
+ err = udc_register_ep(dev, &config->ep_cfg_in[i]);
+ if (err != 0) {
+ LOG_ERR("Failed to register endpoint");
+ return err;
+ }
+ }
+
+ config->make_thread(dev);
+
+ return 0;
+}
+
+static const struct udc_api udc_numaker_api = {
+ .device_speed = udc_numaker_device_speed,
+ .ep_enqueue = udc_numaker_ep_enqueue,
+ .ep_dequeue = udc_numaker_ep_dequeue,
+ .ep_set_halt = udc_numaker_ep_set_halt,
+ .ep_clear_halt = udc_numaker_ep_clear_halt,
+ .ep_enable = udc_numaker_ep_enable,
+ .ep_disable = udc_numaker_ep_disable,
+ .host_wakeup = udc_numaker_host_wakeup,
+ .set_address = udc_numaker_set_address,
+ .enable = udc_numaker_enable,
+ .disable = udc_numaker_disable,
+ .init = udc_numaker_init,
+ .shutdown = udc_numaker_shutdown,
+ .lock = udc_numaker_lock,
+ .unlock = udc_numaker_unlock,
+};
+
+#define UDC_NUMAKER_DEVICE_DEFINE(inst) \
+ PINCTRL_DT_INST_DEFINE(inst); \
+ \
+ static void udc_numaker_irq_config_func_##inst(const struct device *dev) \
+ { \
+ IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), numaker_udbd_isr, \
+ DEVICE_DT_INST_GET(inst), 0); \
+ \
+ irq_enable(DT_INST_IRQN(inst)); \
+ } \
+ \
+ static void udc_numaker_irq_unconfig_func_##inst(const struct device *dev) \
+ { \
+ irq_disable(DT_INST_IRQN(inst)); \
+ } \
+ \
+ K_THREAD_STACK_DEFINE(udc_numaker_stack_##inst, CONFIG_UDC_NUMAKER_THREAD_STACK_SIZE); \
+ \
+ static void udc_numaker_thread_##inst(void *dev, void *arg1, void *arg2) \
+ { \
+ ARG_UNUSED(arg1); \
+ ARG_UNUSED(arg2); \
+ numaker_usbd_msg_handler(dev); \
+ } \
+ \
+ static void udc_numaker_make_thread_##inst(const struct device *dev) \
+ { \
+ struct udc_numaker_data *priv = udc_get_private(dev); \
+ \
+ k_thread_create(&priv->thread_data, udc_numaker_stack_##inst, \
+ K_THREAD_STACK_SIZEOF(udc_numaker_stack_##inst), \
+ udc_numaker_thread_##inst, (void *)dev, NULL, NULL, \
+ K_PRIO_COOP(CONFIG_UDC_NUMAKER_THREAD_PRIORITY), K_ESSENTIAL, \
+ K_NO_WAIT); \
+ k_thread_name_set(&priv->thread_data, dev->name); \
+ } \
+ \
+ static struct udc_ep_config \
+ ep_cfg_out_##inst[MIN(DT_INST_PROP(inst, num_bidir_endpoints), 16)]; \
+ static struct udc_ep_config \
+ ep_cfg_in_##inst[MIN(DT_INST_PROP(inst, num_bidir_endpoints), 16)]; \
+ \
+ static const struct udc_numaker_config udc_numaker_config_##inst = { \
+ .ep_cfg_out = ep_cfg_out_##inst, \
+ .ep_cfg_in = ep_cfg_in_##inst, \
+ .ep_cfg_out_size = ARRAY_SIZE(ep_cfg_out_##inst), \
+ .ep_cfg_in_size = ARRAY_SIZE(ep_cfg_in_##inst), \
+ .make_thread = udc_numaker_make_thread_##inst, \
+ .base = (USBD_T *)DT_INST_REG_ADDR(inst), \
+ .reset = RESET_DT_SPEC_INST_GET(inst), \
+ .clk_modidx = DT_INST_CLOCKS_CELL(inst, clock_module_index), \
+ .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
+ .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
+ .clkctrl_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(inst))), \
+ .irq_config_func = udc_numaker_irq_config_func_##inst, \
+ .irq_unconfig_func = udc_numaker_irq_unconfig_func_##inst, \
+ .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
+ .dmabuf_size = DT_INST_PROP(inst, dma_buffer_size), \
+ .disallow_iso_inout_same = DT_INST_PROP(inst, disallow_iso_in_out_same_number), \
+ }; \
+ \
+ static struct numaker_usbd_ep \
+ numaker_usbd_ep_pool_##inst[DT_INST_PROP(inst, num_bidir_endpoints)]; \
+ \
+ K_MSGQ_DEFINE(numaker_usbd_msgq_##inst, sizeof(struct numaker_usbd_msg), \
+ CONFIG_UDC_NUMAKER_MSG_QUEUE_SIZE, 4); \
+ \
+ static struct udc_numaker_data udc_priv_##inst = { \
+ .msgq = &numaker_usbd_msgq_##inst, \
+ .ep_pool = numaker_usbd_ep_pool_##inst, \
+ .ep_pool_size = DT_INST_PROP(inst, num_bidir_endpoints), \
+ }; \
+ \
+ static struct udc_data udc_data_##inst = { \
+ .mutex = Z_MUTEX_INITIALIZER(udc_data_##inst.mutex), \
+ .priv = &udc_priv_##inst, \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(inst, udc_numaker_driver_preinit, NULL, &udc_data_##inst, \
+ &udc_numaker_config_##inst, POST_KERNEL, \
+ CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &udc_numaker_api);
+
+DT_INST_FOREACH_STATUS_OKAY(UDC_NUMAKER_DEVICE_DEFINE)
diff --git a/drivers/usb/udc/udc_stm32.c b/drivers/usb/udc/udc_stm32.c
index 937cd08..845f461 100644
--- a/drivers/usb/udc/udc_stm32.c
+++ b/drivers/usb/udc/udc_stm32.c
@@ -136,7 +136,7 @@
return -ENOMEM;
}
- net_buf_put(&cfg->fifo, buf);
+ k_fifo_put(&cfg->fifo, buf);
HAL_PCD_EP_Receive(&priv->pcd, cfg->addr, buf->data, buf->size);
@@ -423,7 +423,7 @@
const struct udc_stm32_config *cfg = dev->config;
uint32_t size;
- size = MIN(ep->mps, cfg->ep_mps);
+ size = MIN(udc_mps_ep_size(ep), cfg->ep_mps);
if (!enable) {
priv->occupied_mem -= size;
@@ -487,7 +487,7 @@
return 0;
}
- words = MIN(ep->mps, cfg->ep_mps) / 4;
+ words = MIN(udc_mps_ep_size(ep), cfg->ep_mps) / 4;
words = (words <= 64) ? words * 2 : words;
if (!enable) {
@@ -667,8 +667,8 @@
return ret;
}
- status = HAL_PCD_EP_Open(&priv->pcd, ep_cfg->addr, ep_cfg->mps,
- ep_type);
+ status = HAL_PCD_EP_Open(&priv->pcd, ep_cfg->addr,
+ udc_mps_ep_size(ep_cfg), ep_type);
if (status != HAL_OK) {
LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d",
ep_cfg->addr, (int)status);
diff --git a/drivers/usb/udc/udc_virtual.c b/drivers/usb/udc/udc_virtual.c
index d1ba034..cc21649 100644
--- a/drivers/usb/udc/udc_virtual.c
+++ b/drivers/usb/udc/udc_virtual.c
@@ -183,7 +183,7 @@
LOG_DBG("Handle data OUT, %zu | %zu", pkt->length, net_buf_tailroom(buf));
- if (net_buf_tailroom(buf) == 0 || pkt->length < ep_cfg->mps) {
+ if (net_buf_tailroom(buf) == 0 || pkt->length < udc_mps_ep_size(ep_cfg)) {
buf = udc_buf_get(dev, ep);
if (ep == USB_CONTROL_EP_OUT) {
@@ -246,13 +246,13 @@
}
LOG_DBG("Handle data IN, %zu | %u | %u",
- pkt->length, buf->len, ep_cfg->mps);
+ pkt->length, buf->len, udc_mps_ep_size(ep_cfg));
min_len = MIN(pkt->length, buf->len);
memcpy(pkt->data, buf->data, min_len);
net_buf_pull(buf, min_len);
pkt->length = min_len;
- if (buf->len == 0 || pkt->length < ep_cfg->mps) {
+ if (buf->len == 0 || pkt->length < udc_mps_ep_size(ep_cfg)) {
if (udc_ep_buf_has_zlp(buf)) {
udc_ep_buf_clear_zlp(buf);
goto continue_in;
diff --git a/drivers/video/ov2640.c b/drivers/video/ov2640.c
index c9da591..e337073 100644
--- a/drivers/video/ov2640.c
+++ b/drivers/video/ov2640.c
@@ -108,6 +108,7 @@
#define REG04_DEFAULT 0x28
#define REG04_HFLIP_IMG 0x80
#define REG04_VFLIP_IMG 0x40
+#define REG04_VREF_EN 0x10
#define REG04_HREF_EN 0x08
#define REG04_SET(x) (REG04_DEFAULT | x)
@@ -791,9 +792,9 @@
reg = ov2640_read_reg(&cfg->i2c, REG04);
if (enable) {
- reg |= REG04_VFLIP_IMG;
+ reg |= REG04_VFLIP_IMG | REG04_VREF_EN;
} else {
- reg &= ~REG04_VFLIP_IMG;
+ reg &= ~(REG04_VFLIP_IMG | REG04_VREF_EN);
}
ret |= ov2640_write_reg(&cfg->i2c, REG04, reg);
diff --git a/drivers/video/video_stm32_dcmi.c b/drivers/video/video_stm32_dcmi.c
index d8f875b..51fb14c 100644
--- a/drivers/video/video_stm32_dcmi.c
+++ b/drivers/video/video_stm32_dcmi.c
@@ -308,12 +308,17 @@
struct video_buffer *vbuf)
{
struct video_stm32_dcmi_data *data = dev->data;
+ const uint32_t buffer_size = data->pitch * data->height;
if (ep != VIDEO_EP_OUT) {
return -EINVAL;
}
- vbuf->bytesused = data->pitch * data->height;
+ if (buffer_size > vbuf->size) {
+ return -EINVAL;
+ }
+
+ vbuf->bytesused = buffer_size;
k_fifo_put(&data->fifo_in, vbuf);
@@ -356,6 +361,28 @@
return ret;
}
+static inline int video_stm32_dcmi_set_ctrl(const struct device *dev, unsigned int cid, void *value)
+{
+ const struct video_stm32_dcmi_config *config = dev->config;
+ int ret;
+
+ /* Forward to source dev if any */
+ ret = video_set_ctrl(config->sensor_dev, cid, value);
+
+ return ret;
+}
+
+static inline int video_stm32_dcmi_get_ctrl(const struct device *dev, unsigned int cid, void *value)
+{
+ const struct video_stm32_dcmi_config *config = dev->config;
+ int ret;
+
+ /* Forward to source dev if any */
+ ret = video_get_ctrl(config->sensor_dev, cid, value);
+
+ return ret;
+}
+
static const struct video_driver_api video_stm32_dcmi_driver_api = {
.set_format = video_stm32_dcmi_set_fmt,
.get_format = video_stm32_dcmi_get_fmt,
@@ -364,6 +391,8 @@
.enqueue = video_stm32_dcmi_enqueue,
.dequeue = video_stm32_dcmi_dequeue,
.get_caps = video_stm32_dcmi_get_caps,
+ .set_ctrl = video_stm32_dcmi_set_ctrl,
+ .get_ctrl = video_stm32_dcmi_get_ctrl,
};
static void video_stm32_dcmi_irq_config_func(const struct device *dev)
diff --git a/drivers/watchdog/CMakeLists.txt b/drivers/watchdog/CMakeLists.txt
index 6ade11b..87dc99d 100644
--- a/drivers/watchdog/CMakeLists.txt
+++ b/drivers/watchdog/CMakeLists.txt
@@ -18,6 +18,7 @@
zephyr_library_sources_ifdef(CONFIG_WDT_XT_ESP32 xt_wdt_esp32.c)
zephyr_library_sources_ifdef(CONFIG_WDT_GECKO wdt_gecko.c)
zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT8XXX2 wdt_ite_it8xxx2.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_LITEX wdt_litex.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MAX32 wdt_max32.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_IMX_WDOG wdt_mcux_imx_wdog.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG wdt_mcux_wdog.c)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d40f5f6..95eaf31 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -132,4 +132,6 @@
source "drivers/watchdog/Kconfig.ene"
+source "drivers/watchdog/Kconfig.litex"
+
endif # WATCHDOG
diff --git a/drivers/watchdog/Kconfig.litex b/drivers/watchdog/Kconfig.litex
new file mode 100644
index 0000000..3853f81
--- /dev/null
+++ b/drivers/watchdog/Kconfig.litex
@@ -0,0 +1,12 @@
+# LiteX WDT configuration
+
+# Copyright (C) 2024 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_LITEX
+ bool "LiteX Watchdog (WDT) Driver"
+ default y
+ depends on DT_HAS_LITEX_WATCHDOG_ENABLED
+ select HAS_WDT_DISABLE_AT_BOOT
+ help
+ Enable WDT driver for LiteX.
diff --git a/drivers/watchdog/wdt_dw.c b/drivers/watchdog/wdt_dw.c
index 657001b..fd0e338 100644
--- a/drivers/watchdog/wdt_dw.c
+++ b/drivers/watchdog/wdt_dw.c
@@ -186,8 +186,9 @@
}
#endif
ret = dw_wdt_probe((uint32_t)reg_base, dev_config->reset_pulse_length);
- if (ret)
+ if (ret) {
return ret;
+ }
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
if (dev_config->irq_config) {
diff --git a/drivers/watchdog/wdt_esp32.c b/drivers/watchdog/wdt_esp32.c
index f5ef51f..e86e573 100644
--- a/drivers/watchdog/wdt_esp32.c
+++ b/drivers/watchdog/wdt_esp32.c
@@ -51,6 +51,8 @@
const clock_control_subsys_t clock_subsys;
void (*connect_irq)(void);
int irq_source;
+ int irq_priority;
+ int irq_flags;
};
static inline void wdt_esp32_seal(const struct device *dev)
@@ -166,11 +168,17 @@
wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
- esp_intr_alloc(config->irq_source,
- 0,
- (ISR_HANDLER)wdt_esp32_isr,
- (void *)dev,
- NULL);
+ int ret = esp_intr_alloc(config->irq_source,
+ ESP_PRIO_TO_FLAGS(config->irq_priority) |
+ ESP_INT_FLAGS_CHECK(config->irq_flags),
+ (ISR_HANDLER)wdt_esp32_isr,
+ (void *)dev,
+ NULL);
+
+ if (ret != 0) {
+ LOG_ERR("could not allocate interrupt (err %d)", ret);
+ return ret;
+ }
#ifndef CONFIG_WDT_DISABLE_AT_BOOT
wdt_esp32_enable(dev);
@@ -190,7 +198,9 @@
static struct wdt_esp32_data wdt##idx##_data; \
static struct wdt_esp32_config wdt_esp32_config##idx = { \
.wdt_inst = WDT_MWDT##idx, \
- .irq_source = DT_IRQN(DT_NODELABEL(wdt##idx)), \
+ .irq_source = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, irq), \
+ .irq_priority = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, priority), \
+ .irq_flags = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, flags), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
}; \
diff --git a/drivers/watchdog/wdt_litex.c b/drivers/watchdog/wdt_litex.c
new file mode 100644
index 0000000..469c13a
--- /dev/null
+++ b/drivers/watchdog/wdt_litex.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2024 Vogl Electronic GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT litex_watchdog
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/device.h>
+#include <zephyr/sys_clock.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(wdt_litex, CONFIG_WDT_LOG_LEVEL);
+
+#include <soc.h>
+
+struct wdt_litex_data {
+ wdt_callback_t callback;
+ uint32_t timeout;
+ bool reset_soc_mode;
+ bool pause_halted;
+};
+
+struct wdt_litex_config {
+ uint32_t control_addr;
+ uint32_t cycles_addr;
+ uint32_t cycles_size;
+ uint32_t remaining_addr;
+ uint32_t ev_status_addr;
+ uint32_t ev_pending_addr;
+ uint32_t ev_enable_addr;
+ void (*irq_cfg_func)(void);
+};
+
+#define CONTROL_FEED_BIT BIT(0)
+#define CONTROL_ENABLE_BIT BIT(8)
+#define CONTROL_RESET_BIT BIT(16)
+#define CONTROL_PAUSE_HALTED_BIT BIT(24)
+
+static bool wdt_litex_is_enabled(const struct device *dev)
+{
+ const struct wdt_litex_config *config = dev->config;
+
+ return litex_read8(config->control_addr) & BIT(0);
+}
+
+static void wdt_litex_irq_enable(const struct device *dev)
+{
+ const struct wdt_litex_config *config = dev->config;
+ struct wdt_litex_data *data = dev->data;
+
+ if (!data->callback) {
+ return;
+ }
+
+ litex_write8(BIT(0), config->ev_pending_addr);
+
+ litex_write8(BIT(0), config->ev_enable_addr);
+}
+
+static void wdt_litex_enable(const struct device *dev)
+{
+ const struct wdt_litex_config *config = dev->config;
+ struct wdt_litex_data *data = dev->data;
+ uint32_t control;
+
+ if (config->cycles_size <= 4) {
+ litex_write32(k_ms_to_cyc_floor32(data->timeout), config->cycles_addr);
+ } else {
+ litex_write64(k_ms_to_cyc_floor64(data->timeout), config->cycles_addr);
+ }
+
+ control = CONTROL_FEED_BIT | CONTROL_ENABLE_BIT;
+
+ if (data->reset_soc_mode) {
+ control |= CONTROL_RESET_BIT;
+ }
+ if (data->pause_halted) {
+ control |= CONTROL_PAUSE_HALTED_BIT;
+ }
+
+ litex_write32(control, config->control_addr);
+
+ wdt_litex_irq_enable(dev);
+}
+
+static int wdt_litex_disable(const struct device *dev)
+{
+ const struct wdt_litex_config *config = dev->config;
+
+ litex_write8(0, config->ev_enable_addr);
+
+ if (!wdt_litex_is_enabled(dev)) {
+ return -EFAULT;
+ }
+ litex_write16(CONTROL_ENABLE_BIT, config->control_addr);
+
+ return 0;
+}
+
+static int wdt_litex_feed(const struct device *dev, int channel_id)
+{
+ const struct wdt_litex_config *config = dev->config;
+
+ if (channel_id != 0) {
+ return -EINVAL;
+ }
+
+ litex_write8(CONTROL_FEED_BIT, config->control_addr);
+
+ return 0;
+}
+
+static int wdt_litex_setup(const struct device *dev, uint8_t options)
+{
+ struct wdt_litex_data *data = dev->data;
+
+ data->pause_halted = !!(options & WDT_OPT_PAUSE_HALTED_BY_DBG);
+
+ if (options & WDT_OPT_PAUSE_IN_SLEEP) {
+ return -ENOTSUP;
+ }
+
+ if (wdt_litex_is_enabled(dev)) {
+ return -EBUSY;
+ }
+
+ wdt_litex_enable(dev);
+ wdt_litex_feed(dev, 0);
+
+ return 0;
+}
+
+static int wdt_litex_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
+{
+ const struct wdt_litex_config *config = dev->config;
+ struct wdt_litex_data *data = dev->data;
+
+ if (cfg->window.min != 0U || cfg->window.max == 0U) {
+ return -EINVAL;
+ }
+
+ if (cfg->window.max > (config->cycles_size <= 4 ? k_cyc_to_ms_floor32(UINT32_MAX)
+ : k_cyc_to_ms_floor64(UINT64_MAX))) {
+ return -EINVAL;
+ }
+
+ if (wdt_litex_is_enabled(dev)) {
+ return -EBUSY;
+ }
+
+ data->timeout = cfg->window.max;
+ data->callback = cfg->callback;
+
+ /* Set mode of watchdog and callback */
+ switch (cfg->flags) {
+ case WDT_FLAG_RESET_SOC:
+ LOG_DBG("Configuring reset SOC mode");
+ data->reset_soc_mode = true;
+ break;
+
+ case WDT_FLAG_RESET_NONE:
+ LOG_DBG("Configuring non-reset mode");
+ data->reset_soc_mode = false;
+ break;
+
+ default:
+ LOG_ERR("Unsupported watchdog config flag");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void wdt_litex_isr(void *arg)
+{
+ const struct device *dev = (const struct device *)arg;
+ const struct wdt_litex_config *config = dev->config;
+ struct wdt_litex_data *data = dev->data;
+ unsigned int key = irq_lock();
+
+ if (data->callback) {
+ data->callback(dev, 0);
+ }
+
+ litex_write8(BIT(0), config->ev_pending_addr);
+
+ irq_unlock(key);
+}
+
+static int wdt_litex_init(const struct device *dev)
+{
+ const struct wdt_litex_config *const config = dev->config;
+
+ config->irq_cfg_func();
+
+#ifndef CONFIG_WDT_DISABLE_AT_BOOT
+ wdt_litex_enable(dev);
+#endif
+
+ return 0;
+}
+
+static const struct wdt_driver_api wdt_api = {
+ .setup = wdt_litex_setup,
+ .disable = wdt_litex_disable,
+ .install_timeout = wdt_litex_install_timeout,
+ .feed = wdt_litex_feed,
+};
+
+#define LITEX_WDT_INIT(n) \
+ static void wdt_litex_cfg_func_##n(void); \
+ \
+ static struct wdt_litex_data wdt_litex_data##n; \
+ static struct wdt_litex_config wdt_litex_config##n = { \
+ .control_addr = DT_INST_REG_ADDR_BY_NAME(n, control), \
+ .cycles_addr = DT_INST_REG_ADDR_BY_NAME(n, cycles), \
+ .cycles_size = DT_INST_REG_SIZE_BY_NAME(n, cycles), \
+ .remaining_addr = DT_INST_REG_ADDR_BY_NAME(n, remaining), \
+ .ev_status_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_status), \
+ .ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_pending), \
+ .ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_enable), \
+ .irq_cfg_func = wdt_litex_cfg_func_##n, \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(n, wdt_litex_init, NULL, &wdt_litex_data##n, &wdt_litex_config##n, \
+ PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_api) \
+ \
+ static void wdt_litex_cfg_func_##n(void) \
+ { \
+ IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), wdt_litex_isr, \
+ DEVICE_DT_INST_GET(n), 0); \
+ irq_enable(DT_INST_IRQN(n)); \
+ }
+
+DT_INST_FOREACH_STATUS_OKAY(LITEX_WDT_INIT)
diff --git a/drivers/watchdog/wdt_mcux_wwdt.c b/drivers/watchdog/wdt_mcux_wwdt.c
index cd24b1d..cfaf98d 100644
--- a/drivers/watchdog/wdt_mcux_wwdt.c
+++ b/drivers/watchdog/wdt_mcux_wwdt.c
@@ -83,7 +83,7 @@
}
#if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) \
- || defined(CONFIG_SOC_SERIES_MCXNX4X)
+ || defined(CONFIG_SOC_SERIES_MCXN)
clock_freq = CLOCK_GetWdtClkFreq(0);
#elif defined(CONFIG_SOC_SERIES_RW6XX)
clock_freq = CLOCK_GetWdtClkFreq();
diff --git a/drivers/watchdog/xt_wdt_esp32.c b/drivers/watchdog/xt_wdt_esp32.c
index 7e0141d..ae902c6 100644
--- a/drivers/watchdog/xt_wdt_esp32.c
+++ b/drivers/watchdog/xt_wdt_esp32.c
@@ -42,6 +42,8 @@
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
int irq_source;
+ int irq_priority;
+ int irq_flags;
};
static int esp32_xt_wdt_setup(const struct device *dev, uint8_t options)
@@ -126,8 +128,11 @@
xt_wdt_hal_enable_backup_clk(&data->hal,
ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ/1000);
- int err = esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)esp32_xt_wdt_isr, (void *)dev,
- NULL);
+ int err = esp_intr_alloc(cfg->irq_source,
+ ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
+ ESP_INT_FLAGS_CHECK(cfg->irq_flags),
+ (ISR_HANDLER)esp32_xt_wdt_isr, (void *)dev, NULL);
+
if (err) {
LOG_ERR("Failed to register ISR\n");
return -EFAULT;
@@ -151,7 +156,9 @@
static struct esp32_xt_wdt_config esp32_xt_wdt_config0 = {
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
- .irq_source = DT_INST_IRQN(0),
+ .irq_source = DT_INST_IRQ_BY_IDX(0, 0, irq),
+ .irq_priority = DT_INST_IRQ_BY_IDX(0, 0, priority),
+ .irq_flags = DT_INST_IRQ_BY_IDX(0, 0, flags)
};
DEVICE_DT_DEFINE(DT_NODELABEL(xt_wdt),
diff --git a/drivers/wifi/esp32/src/esp_wifi_drv.c b/drivers/wifi/esp32/src/esp_wifi_drv.c
index 1c3c9f0..edf25b0 100644
--- a/drivers/wifi/esp32/src/esp_wifi_drv.c
+++ b/drivers/wifi/esp32/src/esp_wifi_drv.c
@@ -611,6 +611,9 @@
if (esp_wifi_get_mode(&mode) == ESP_OK) {
if (mode == ESP32_WIFI_MODE_STA) {
+ wifi_phy_mode_t phy_mode;
+ esp_err_t err;
+
esp_wifi_get_config(ESP_IF_WIFI_STA, &conf);
esp_wifi_sta_get_ap_info(&ap_info);
@@ -619,14 +622,18 @@
status->rssi = ap_info.rssi;
memcpy(status->bssid, ap_info.bssid, WIFI_MAC_ADDR_LEN);
- if (ap_info.phy_11b) {
- status->link_mode = WIFI_1;
- } else if (ap_info.phy_11g) {
- status->link_mode = WIFI_3;
- } else if (ap_info.phy_11n) {
- status->link_mode = WIFI_4;
- } else if (ap_info.phy_11ax) {
- status->link_mode = WIFI_6;
+ err = esp_wifi_sta_get_negotiated_phymode(&phy_mode);
+ if (err == ESP_OK) {
+ if (phy_mode == WIFI_PHY_MODE_11B) {
+ status->link_mode = WIFI_1;
+ } else if (phy_mode == WIFI_PHY_MODE_11G) {
+ status->link_mode = WIFI_3;
+ } else if ((phy_mode == WIFI_PHY_MODE_HT20) ||
+ (phy_mode == WIFI_PHY_MODE_HT40)) {
+ status->link_mode = WIFI_4;
+ } else if (phy_mode == WIFI_PHY_MODE_HE20) {
+ status->link_mode = WIFI_6;
+ }
}
status->beacon_interval = conf.sta.listen_interval;
diff --git a/drivers/wifi/infineon/airoc_wifi.c b/drivers/wifi/infineon/airoc_wifi.c
index e3d8e6a..70db293 100644
--- a/drivers/wifi/infineon/airoc_wifi.c
+++ b/drivers/wifi/infineon/airoc_wifi.c
@@ -363,6 +363,37 @@
}
}
+static enum ethernet_hw_caps airoc_get_capabilities(const struct device *dev)
+{
+ ARG_UNUSED(dev);
+
+ return ETHERNET_HW_FILTERING;
+}
+
+static int airoc_set_config(const struct device *dev,
+ enum ethernet_config_type type,
+ const struct ethernet_config *config)
+{
+ ARG_UNUSED(dev);
+ whd_mac_t whd_mac_addr;
+
+ switch (type) {
+ case ETHERNET_CONFIG_TYPE_FILTER:
+ for (int i = 0; i < WHD_ETHER_ADDR_LEN; i++) {
+ whd_mac_addr.octet[i] = config->filter.mac_address.addr[i];
+ }
+ if (config->filter.set) {
+ whd_wifi_register_multicast_address(airoc_if, &whd_mac_addr);
+ } else {
+ whd_wifi_unregister_multicast_address(airoc_if, &whd_mac_addr);
+ }
+ return 0;
+ default:
+ break;
+ }
+ return -ENOTSUP;
+}
+
static void *link_events_handler(whd_interface_t ifp, const whd_event_header_t *event_header,
const uint8_t *event_data, void *handler_user_data)
{
@@ -502,7 +533,7 @@
goto error;
}
- if (usr_result.security == 0) {
+ if (usr_result.security == WHD_SECURITY_UNKNOWN) {
ret = -EAGAIN;
LOG_ERR("Could not scan device");
goto error;
@@ -620,10 +651,18 @@
params->channel);
}
- if (params->psk_length == 0) {
+ switch (params->security) {
+ case WIFI_SECURITY_TYPE_NONE:
security = WHD_SECURITY_OPEN;
- } else {
+ break;
+ case WIFI_SECURITY_TYPE_PSK:
security = WHD_SECURITY_WPA2_AES_PSK;
+ break;
+ case WIFI_SECURITY_TYPE_SAE:
+ security = WHD_SECURITY_WPA3_SAE;
+ break;
+ default:
+ goto error;
}
if (whd_wifi_init_ap(airoc_ap_if, &ssid, security, (const uint8_t *)params->psk,
@@ -650,6 +689,7 @@
data->is_ap_up = true;
airoc_if = airoc_ap_if;
+ net_if_dormant_off(data->iface);
error:
k_sem_give(&data->sema_common);
@@ -695,6 +735,7 @@
if (whd_ret == CY_RSLT_SUCCESS) {
data->is_ap_up = false;
airoc_if = airoc_sta_if;
+ net_if_dormant_on(data->iface);
} else {
LOG_ERR("Can't stop wifi ap: %u", whd_ret);
}
@@ -769,6 +810,8 @@
static const struct net_wifi_mgmt_offload airoc_api = {
.wifi_iface.iface_api.init = airoc_mgmt_init,
.wifi_iface.send = airoc_mgmt_send,
+ .wifi_iface.get_capabilities = airoc_get_capabilities,
+ .wifi_iface.set_config = airoc_set_config,
.wifi_mgmt_api = &airoc_wifi_mgmt,
};
diff --git a/drivers/wifi/nrfwifi/CMakeLists.txt b/drivers/wifi/nrfwifi/CMakeLists.txt
index 4ba57b4..3d1ea0b 100644
--- a/drivers/wifi/nrfwifi/CMakeLists.txt
+++ b/drivers/wifi/nrfwifi/CMakeLists.txt
@@ -76,14 +76,10 @@
src/wifi_mgmt_scan.c
)
-zephyr_library_sources_ifdef(CONFIG_NRF70_SYSTEM_MODE
+zephyr_library_sources_ifdef(CONFIG_NRF70_SYSTEM_MODE_COMMON
src/wifi_mgmt.c
)
-zephyr_library_sources_ifdef(CONFIG_NRF70_SCAN_ONLY
- src/wifi_mgmt_scan.c
-)
-
zephyr_library_sources_ifdef(CONFIG_NRF70_RADIO_TEST
${OS_AGNOSTIC_BASE}/fw_if/umac_if/src/radio_test/fmac_api.c
${OS_AGNOSTIC_BASE}/fw_if/umac_if/src/fmac_util.c
@@ -244,6 +240,10 @@
-DNRF70_LOG_VERBOSE
)
+zephyr_compile_definitions_ifdef(CONFIG_NRF70_AP_MODE
+ -DNRF70_AP_MODE
+)
+
zephyr_compile_definitions(
-DNRF70_RX_NUM_BUFS=${CONFIG_NRF70_RX_NUM_BUFS}
-DNRF70_MAX_TX_TOKENS=${CONFIG_NRF70_MAX_TX_TOKENS}
diff --git a/drivers/wifi/nrfwifi/Kconfig.nrfwifi b/drivers/wifi/nrfwifi/Kconfig.nrfwifi
index bad9cfb..b7947ce 100644
--- a/drivers/wifi/nrfwifi/Kconfig.nrfwifi
+++ b/drivers/wifi/nrfwifi/Kconfig.nrfwifi
@@ -78,6 +78,10 @@
endchoice
+config NRF70_SYSTEM_MODE_COMMON
+ bool
+ default y if NRF70_SYSTEM_MODE || NRF70_SYSTEM_WITH_RAW_MODES
+
config NET_L2_ETHERNET
default y if !NRF70_RADIO_TEST
@@ -667,4 +671,33 @@
there will be a internal hardware switch to add delay between the two operations. This
is typically 4ms delay for nRF70.
+config NRF_WIFI_FEAT_WMM
+ bool "WMM/QoS support"
+ default y
+ help
+ This option controls disable/enable of the WMM(Wireless Multi-Media) feature.
+
+choice NRF_WIFI_PS_DATA_RETRIEVAL_MECHANISM
+ prompt "Power save data retrieval mechanism"
+ default NRF_WIFI_PS_POLL_BASED_RETRIEVAL
+ help
+ Select the mechanism to retrieve buffered data from AP.
+
+config NRF_WIFI_PS_POLL_BASED_RETRIEVAL
+ bool "PS-Poll frame based mechanism to retrieve buffered data from AP"
+ help
+ When AP notifies about availability of buffered data, the STA stays in power save
+ and retrieves the frames one-by-one, this conserved more power but adds latency
+ to the traffic. Ideal for minimum number of frames.
+
+config NRF_WIFI_QOS_NULL_BASED_RETRIEVAL
+ bool "QoS null frame based mechanism to retrieve buffered data from AP"
+ help
+ When AP notifies about availability of buffered data, the STA comes out of
+ power save and then AP can deliver all buffered frames without any additional
+ overhead or latency, but STA enters power save after a delay costing more power
+ depending on the delay. Ideal for heavy buffered traffic.
+
+endchoice
+
endif # WIFI_NRF70
diff --git a/drivers/wifi/nrfwifi/inc/net_if.h b/drivers/wifi/nrfwifi/inc/net_if.h
index f4abf50..8d97802 100644
--- a/drivers/wifi/nrfwifi/inc/net_if.h
+++ b/drivers/wifi/nrfwifi/inc/net_if.h
@@ -61,4 +61,6 @@
void nrf_wifi_set_iface_event_handler(void *os_vif_ctx,
struct nrf_wifi_umac_event_set_interface *event,
unsigned int event_len);
+
+int nrf_wifi_stats_reset(const struct device *dev);
#endif /* __ZEPHYR_NET_IF_H__ */
diff --git a/drivers/wifi/nrfwifi/src/fmac_main.c b/drivers/wifi/nrfwifi/src/fmac_main.c
index a6ae71e..8d8558a 100644
--- a/drivers/wifi/nrfwifi/src/fmac_main.c
+++ b/drivers/wifi/nrfwifi/src/fmac_main.c
@@ -19,6 +19,7 @@
#include <zephyr/net/wifi_mgmt.h>
#include <zephyr/net/conn_mgr_connectivity.h>
#include <zephyr/net/conn_mgr_connectivity_impl.h>
+#include <zephyr/net/conn_mgr/connectivity_wifi_mgmt.h>
#include <util.h>
@@ -44,6 +45,7 @@
LOG_MODULE_DECLARE(wifi_nrf, CONFIG_WIFI_NRF70_LOG_LEVEL);
struct nrf_wifi_drv_priv_zep rpu_drv_priv_zep;
+extern const struct nrf_wifi_osal_ops nrf_wifi_os_zep_ops;
/* 3 bytes for addreess, 3 bytes for length */
#define MAX_PKT_RAM_TX_ALIGN_OVERHEAD 6
@@ -72,7 +74,6 @@
"TX buffer size must be at least as big as the MTU and headroom");
static const unsigned char aggregation = 1;
-static const unsigned char wmm = 1;
static const unsigned char max_num_tx_agg_sessions = 4;
static const unsigned char max_num_rx_agg_sessions = 8;
static const unsigned char reorder_buf_size = 16;
@@ -260,7 +261,7 @@
vif_ctx_zep->rssi = MBM_TO_DBM(signal);
vif_ctx_zep->rssi_record_timestamp_us =
- nrf_wifi_osal_time_get_curr_us(fmac_dev_ctx->fpriv->opriv);
+ nrf_wifi_osal_time_get_curr_us();
}
#endif /* CONFIG_NRF70_STA_MODE */
@@ -706,7 +707,7 @@
#ifdef CONFIG_NRF70_DATA_TX
data_config.aggregation = aggregation;
- data_config.wmm = wmm;
+ data_config.wmm = IS_ENABLED(CONFIG_NRF_WIFI_FEAT_WMM);
data_config.max_num_tx_agg_sessions = max_num_tx_agg_sessions;
data_config.max_num_rx_agg_sessions = max_num_rx_agg_sessions;
data_config.max_tx_aggregation = max_tx_aggregation;
@@ -763,12 +764,22 @@
callbk_fns.get_conn_info_callbk_fn = nrf_wifi_supp_event_proc_get_conn_info;
#endif /* CONFIG_NRF70_STA_MODE */
+ /* The OSAL layer needs to be initialized before any other initialization
+ * so that other layers (like FW IF,HW IF etc) have access to OS ops
+ */
+ nrf_wifi_osal_init(&nrf_wifi_os_zep_ops);
+
rpu_drv_priv_zep.fmac_priv = nrf_wifi_fmac_init(&data_config,
rx_buf_pools,
&callbk_fns);
#else /* !CONFIG_NRF70_RADIO_TEST */
enum nrf_wifi_status status = NRF_WIFI_STATUS_FAIL;
+ /* The OSAL layer needs to be initialized before any other initialization
+ * so that other layers (like FW IF,HW IF etc) have access to OS ops
+ */
+ nrf_wifi_osal_init(&nrf_wifi_os_zep_ops);
+
rpu_drv_priv_zep.fmac_priv = nrf_wifi_fmac_init_rt();
#endif /* CONFIG_NRF70_RADIO_TEST */
@@ -809,6 +820,7 @@
#ifdef CONFIG_NRF70_RADIO_TEST
fmac_deinit:
nrf_wifi_fmac_deinit_rt(rpu_drv_priv_zep.fmac_priv);
+ nrf_wifi_osal_deinit();
#endif /* CONFIG_NRF70_RADIO_TEST */
err:
return -1;
@@ -820,6 +832,7 @@
.scan = nrf_wifi_disp_scan_zep,
#ifdef CONFIG_NET_STATISTICS_WIFI
.get_stats = nrf_wifi_stats_get,
+ .reset_stats = nrf_wifi_stats_reset,
#endif /* CONFIG_NET_STATISTICS_WIFI */
#ifdef CONFIG_NRF70_STA_MODE
.set_power_save = nrf_wifi_set_power_save,
@@ -929,5 +942,5 @@
#endif /* CONFIG_NRF70_STA_MODE */
#ifdef CONFIG_NET_CONNECTION_MANAGER_CONNECTIVITY_WIFI_MGMT
-CONNECTIVITY_WIFI_MGMT_BIND(Z_DEVICE_DT_DEV_ID(DT_DRV_INST(0)), L2_CONN_WLAN0);
+CONNECTIVITY_WIFI_MGMT_BIND(Z_DEVICE_DT_DEV_ID(DT_DRV_INST(0)));
#endif /* CONFIG_NET_CONNECTION_MANAGER_CONNECTIVITY_WIFI_MGMT */
diff --git a/drivers/wifi/nrfwifi/src/net_if.c b/drivers/wifi/nrfwifi/src/net_if.c
index 55d4908..94d53e2 100644
--- a/drivers/wifi/nrfwifi/src/net_if.c
+++ b/drivers/wifi/nrfwifi/src/net_if.c
@@ -282,6 +282,9 @@
#ifdef CONFIG_NRF70_DATA_TX
struct nrf_wifi_vif_ctx_zep *vif_ctx_zep = NULL;
struct nrf_wifi_ctx_zep *rpu_ctx_zep = NULL;
+ struct nrf_wifi_fmac_dev_ctx_def *def_dev_ctx = NULL;
+ struct rpu_host_stats *host_stats = NULL;
+ void *nbuf = NULL;
if (!dev || !pkt) {
LOG_ERR("%s: vif_ctx_zep is NULL", __func__);
@@ -306,6 +309,15 @@
goto unlock;
}
+ def_dev_ctx = wifi_dev_priv(rpu_ctx_zep->rpu_ctx);
+ host_stats = &def_dev_ctx->host_stats;
+ nbuf = net_pkt_to_nbuf(pkt);
+ if (!nbuf) {
+ LOG_DBG("Failed to allocate net_pkt");
+ host_stats->total_tx_drop_pkts++;
+ goto out;
+ }
+
#ifdef CONFIG_NRF70_RAW_DATA_TX
if ((*(unsigned int *)pkt->frags->data) == NRF_WIFI_MAGIC_NUM_RAWTX) {
if (vif_ctx_zep->if_carr_state != NRF_WIFI_FMAC_IF_CARR_STATE_ON) {
@@ -314,7 +326,7 @@
ret = nrf_wifi_fmac_start_rawpkt_xmit(rpu_ctx_zep->rpu_ctx,
vif_ctx_zep->vif_idx,
- net_pkt_to_nbuf(pkt));
+ nbuf);
} else {
#endif /* CONFIG_NRF70_RAW_DATA_TX */
if ((vif_ctx_zep->if_carr_state != NRF_WIFI_FMAC_IF_CARR_STATE_ON) ||
@@ -324,7 +336,7 @@
ret = nrf_wifi_fmac_start_xmit(rpu_ctx_zep->rpu_ctx,
vif_ctx_zep->vif_idx,
- net_pkt_to_nbuf(pkt));
+ nbuf);
#ifdef CONFIG_NRF70_RAW_DATA_TX
}
#endif /* CONFIG_NRF70_RAW_DATA_TX */
@@ -487,8 +499,7 @@
}
#endif
- if (!nrf_wifi_utils_is_mac_addr_valid(fmac_dev_ctx->fpriv->opriv,
- vif_ctx_zep->mac_addr.addr)) {
+ if (!nrf_wifi_utils_is_mac_addr_valid(vif_ctx_zep->mac_addr.addr)) {
LOG_ERR("%s: Invalid MAC address: %s",
__func__,
net_sprint_ll_addr(vif_ctx_zep->mac_addr.addr,
@@ -682,8 +693,7 @@
mac_addr = net_if_get_link_addr(vif_ctx_zep->zep_net_if_ctx)->addr;
mac_addr_len = net_if_get_link_addr(vif_ctx_zep->zep_net_if_ctx)->len;
- if (!nrf_wifi_utils_is_mac_addr_valid(fmac_dev_ctx->fpriv->opriv,
- mac_addr)) {
+ if (!nrf_wifi_utils_is_mac_addr_valid(mac_addr)) {
status = nrf_wifi_get_mac_addr(vif_ctx_zep);
if (status != NRF_WIFI_STATUS_SUCCESS) {
LOG_ERR("%s: Failed to get MAC address",
@@ -1142,4 +1152,52 @@
out:
return ret;
}
+
+int nrf_wifi_stats_reset(const struct device *dev)
+{
+ enum nrf_wifi_status status = NRF_WIFI_STATUS_FAIL;
+ struct nrf_wifi_ctx_zep *rpu_ctx_zep = NULL;
+ struct nrf_wifi_vif_ctx_zep *vif_ctx_zep = NULL;
+ struct nrf_wifi_fmac_dev_ctx_def *def_dev_ctx = NULL;
+ int ret = -1;
+
+ if (!dev) {
+ LOG_ERR("%s Device not found", __func__);
+ goto out;
+ }
+
+ vif_ctx_zep = dev->data;
+ if (!vif_ctx_zep) {
+ LOG_ERR("%s: vif_ctx_zep is NULL", __func__);
+ goto out;
+ }
+
+ ret = k_mutex_lock(&vif_ctx_zep->vif_lock, K_FOREVER);
+ if (ret != 0) {
+ LOG_ERR("%s: Failed to lock vif_lock", __func__);
+ goto out;
+ }
+
+ rpu_ctx_zep = vif_ctx_zep->rpu_ctx_zep;
+ if (!rpu_ctx_zep || !rpu_ctx_zep->rpu_ctx) {
+ LOG_DBG("%s: rpu_ctx_zep or rpu_ctx is NULL",
+ __func__);
+ goto unlock;
+ }
+
+ status = nrf_wifi_fmac_stats_reset(rpu_ctx_zep->rpu_ctx);
+ if (status != NRF_WIFI_STATUS_SUCCESS) {
+ LOG_ERR("%s: nrf_wifi_fmac_stats_reset failed", __func__);
+ goto unlock;
+ }
+
+ def_dev_ctx = wifi_dev_priv(rpu_ctx_zep->rpu_ctx);
+ memset(&def_dev_ctx->host_stats, 0, sizeof(struct rpu_host_stats));
+
+ ret = 0;
+unlock:
+ k_mutex_unlock(&vif_ctx_zep->vif_lock);
+out:
+ return ret;
+}
#endif /* CONFIG_NET_STATISTICS_WIFI */
diff --git a/drivers/wifi/nrfwifi/src/qspi/src/qspi_if.c b/drivers/wifi/nrfwifi/src/qspi/src/qspi_if.c
index 968ca72..29fadd9 100644
--- a/drivers/wifi/nrfwifi/src/qspi/src/qspi_if.c
+++ b/drivers/wifi/nrfwifi/src/qspi/src/qspi_if.c
@@ -85,18 +85,47 @@
* PCLK192M frequency"), but after that operation is complete, the default
* divider needs to be restored to avoid increased current consumption.
*/
-/* To prevent anomaly 159, use only divider /1 for HFCLK192M. */
+#if (INST_0_SCK_FREQUENCY >= NRF_QSPI_BASE_CLOCK_FREQ)
+/* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */
#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1
-#if (QSPI_IF_DEVICE_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 4))
-/* For requested SCK >= 24 MHz, use HFCLK192M / 1 / (2*4) = 24 MHz */
-#define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV4
+#define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV1
+/* If anomaly 159 is to be prevented, only /1 divider can be used. */
+#elif NRF53_ERRATA_159_ENABLE_WORKAROUND
+#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1
+#define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ, \
+ INST_0_SCK_FREQUENCY) - 1)
+#elif (INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 2))
+/* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */
+#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_2
+#define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV1
+#elif (INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 3))
+/* For 48 MHz > SCK >= 32 MHz, use HFCLK192M / 1 / (2*3) = 32 MHz */
+#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1
+#define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV3
#else
-/* For requested SCK < 24 MHz, calculate the configuration value. */
+/* For requested SCK < 32 MHz, use divider /2 for HFCLK192M. */
+#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_2
#define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ / 2, \
QSPI_IF_DEVICE_FREQUENCY) - 1)
#endif
+
+#if BASE_CLOCK_DIV == NRF_CLOCK_HFCLK_DIV_1
+/* For 8 MHz, use HFCLK192M / 1 / (2*12) */
+#define INST_0_SCK_CFG_WAKE NRF_QSPI_FREQ_DIV12
+#elif BASE_CLOCK_DIV == NRF_CLOCK_HFCLK_DIV_2
/* For 8 MHz, use HFCLK192M / 2 / (2*6) */
#define INST_0_SCK_CFG_WAKE NRF_QSPI_FREQ_DIV6
+#else
+#error "Unsupported base clock divider for wake-up frequency."
+#endif
+
+/* After the base clock divider is changed, some time is needed for the new
+ * setting to take effect. This value specifies the delay (in microseconds)
+ * to be applied to ensure that the clock is ready when the QSPI operation
+ * starts. It was measured with a logic analyzer (unfortunately, the nRF5340
+ * specification does not provide any numbers in this regard).
+ */
+#define BASE_CLOCK_SWITCH_DELAY_US 7
#else
/*
@@ -353,6 +382,7 @@
*/
#if defined(CONFIG_SOC_SERIES_NRF53X)
nrf_clock_hfclk192m_div_set(NRF_CLOCK, BASE_CLOCK_DIV);
+ k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
}
@@ -362,6 +392,7 @@
/* Restore the default base clock divider to reduce power consumption.
*/
nrf_clock_hfclk192m_div_set(NRF_CLOCK, NRF_CLOCK_HFCLK_DIV_4);
+ k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
#ifdef CONFIG_MULTITHREADING
@@ -652,6 +683,7 @@
/* Configure physical interface */
initstruct->phy_if.sck_freq = INST_0_SCK_CFG;
+
/* Using MHZ fails checkpatch constant check */
if (QSPI_IF_DEVICE_FREQUENCY >= 16000000) {
qspi_cfg->qspi_slave_latency = 1;
@@ -687,6 +719,7 @@
* divider.
*/
nrf_clock_hfclk192m_div_set(NRF_CLOCK, BASE_CLOCK_DIV);
+ k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
nrfx_err_t res = _nrfx_qspi_init(&QSPIconfig, qspi_handler, dev_data);
@@ -694,6 +727,7 @@
#if defined(CONFIG_SOC_SERIES_NRF53X)
/* Restore the default /4 divider after the QSPI initialization. */
nrf_clock_hfclk192m_div_set(NRF_CLOCK, NRF_CLOCK_HFCLK_DIV_4);
+ k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
int ret = qspi_get_zephyr_ret_code(res);
diff --git a/drivers/wifi/nrfwifi/src/shim.c b/drivers/wifi/nrfwifi/src/shim.c
index 209bc12..4db264f 100644
--- a/drivers/wifi/nrfwifi/src/shim.c
+++ b/drivers/wifi/nrfwifi/src/shim.c
@@ -872,7 +872,7 @@
return strlen(str);
}
-static const struct nrf_wifi_osal_ops nrf_wifi_os_zep_ops = {
+const struct nrf_wifi_osal_ops nrf_wifi_os_zep_ops = {
.mem_alloc = zep_shim_mem_alloc,
.mem_zalloc = zep_shim_mem_zalloc,
.mem_free = k_free,
@@ -962,8 +962,3 @@
.assert = zep_shim_assert,
.strlen = zep_shim_strlen,
};
-
-const struct nrf_wifi_osal_ops *get_os_ops(void)
-{
- return &nrf_wifi_os_zep_ops;
-}
diff --git a/drivers/wifi/nrfwifi/src/wifi_mgmt.c b/drivers/wifi/nrfwifi/src/wifi_mgmt.c
index 2d67e56..b18e893 100644
--- a/drivers/wifi/nrfwifi/src/wifi_mgmt.c
+++ b/drivers/wifi/nrfwifi/src/wifi_mgmt.c
@@ -203,15 +203,13 @@
}
do {
- nrf_wifi_osal_sleep_ms(fmac_dev_ctx->fpriv->opriv,
- 1);
+ nrf_wifi_osal_sleep_ms(1);
count++;
} while ((vif_ctx_zep->ps_config_info_evnt == false) &&
(count < NRF_WIFI_FMAC_PS_CONF_EVNT_RECV_TIMEOUT));
if (count == NRF_WIFI_FMAC_PS_CONF_EVNT_RECV_TIMEOUT) {
- nrf_wifi_osal_log_err(fmac_dev_ctx->fpriv->opriv,
- "%s: Timed out",
+ nrf_wifi_osal_log_err("%s: Timed out",
__func__);
goto out;
}
@@ -697,19 +695,16 @@
switch (sleep_evnt->info.type) {
case TWT_BLOCK_TX:
- nrf_wifi_osal_spinlock_take(fmac_dev_ctx->fpriv->opriv,
- def_dev_ctx->tx_config.tx_lock);
+ nrf_wifi_osal_spinlock_take(def_dev_ctx->tx_config.tx_lock);
def_dev_ctx->twt_sleep_status = NRF_WIFI_FMAC_TWT_STATE_SLEEP;
wifi_mgmt_raise_twt_sleep_state(vif_ctx_zep->zep_net_if_ctx,
WIFI_TWT_STATE_SLEEP);
- nrf_wifi_osal_spinlock_rel(fmac_dev_ctx->fpriv->opriv,
- def_dev_ctx->tx_config.tx_lock);
+ nrf_wifi_osal_spinlock_rel(def_dev_ctx->tx_config.tx_lock);
break;
case TWT_UNBLOCK_TX:
- nrf_wifi_osal_spinlock_take(fmac_dev_ctx->fpriv->opriv,
- def_dev_ctx->tx_config.tx_lock);
+ nrf_wifi_osal_spinlock_take(def_dev_ctx->tx_config.tx_lock);
def_dev_ctx->twt_sleep_status = NRF_WIFI_FMAC_TWT_STATE_AWAKE;
wifi_mgmt_raise_twt_sleep_state(vif_ctx_zep->zep_net_if_ctx,
WIFI_TWT_STATE_AWAKE);
@@ -722,8 +717,7 @@
}
}
#endif
- nrf_wifi_osal_spinlock_rel(fmac_dev_ctx->fpriv->opriv,
- def_dev_ctx->tx_config.tx_lock);
+ nrf_wifi_osal_spinlock_rel(def_dev_ctx->tx_config.tx_lock);
break;
default:
break;
diff --git a/drivers/wifi/nrfwifi/src/wifi_mgmt_scan.c b/drivers/wifi/nrfwifi/src/wifi_mgmt_scan.c
index 64bf876..66cd72e 100644
--- a/drivers/wifi/nrfwifi/src/wifi_mgmt_scan.c
+++ b/drivers/wifi/nrfwifi/src/wifi_mgmt_scan.c
@@ -192,7 +192,7 @@
}
scan_info->scan_params.center_frequency[k++] = nrf_wifi_utils_chan_to_freq(
- fmac_dev_ctx->fpriv->opriv, band, params->band_chan[i].channel);
+ band, params->band_chan[i].channel);
if (scan_info->scan_params.center_frequency[k - 1] == -1) {
LOG_ERR("%s: Invalid channel %d", __func__,
@@ -414,23 +414,16 @@
fmac_dev_ctx = rpu_ctx_zep->rpu_ctx;
- frame_length = nrf_wifi_osal_nbuf_data_size(fmac_dev_ctx->fpriv->opriv,
- nwb);
+ frame_length = nrf_wifi_osal_nbuf_data_size(nwb);
if (frame_length > CONFIG_WIFI_MGMT_RAW_SCAN_RESULT_LENGTH) {
- nrf_wifi_osal_mem_cpy(fmac_dev_ctx->fpriv->opriv,
- &bcn_prb_resp_info.data,
- nrf_wifi_osal_nbuf_data_get(
- fmac_dev_ctx->fpriv->opriv,
- nwb),
+ nrf_wifi_osal_mem_cpy(&bcn_prb_resp_info.data,
+ nrf_wifi_osal_nbuf_data_get(nwb),
CONFIG_WIFI_MGMT_RAW_SCAN_RESULT_LENGTH);
} else {
- nrf_wifi_osal_mem_cpy(fmac_dev_ctx->fpriv->opriv,
- &bcn_prb_resp_info.data,
- nrf_wifi_osal_nbuf_data_get(
- fmac_dev_ctx->fpriv->opriv,
- nwb),
+ nrf_wifi_osal_mem_cpy(&bcn_prb_resp_info.data,
+ nrf_wifi_osal_nbuf_data_get(nwb),
frame_length);
}
diff --git a/drivers/wifi/nrfwifi/src/wifi_util.c b/drivers/wifi/nrfwifi/src/wifi_util.c
index 7dc4e78..aec5527 100644
--- a/drivers/wifi/nrfwifi/src/wifi_util.c
+++ b/drivers/wifi/nrfwifi/src/wifi_util.c
@@ -295,7 +295,7 @@
for (int i = 0; i < NRF_WIFI_FMAC_AC_MAX ; i++) {
queue = def_dev_ctx->tx_config.data_pending_txq[peer_index][i];
- tx_pending_pkts = nrf_wifi_utils_q_len(fmac_dev_ctx->fpriv->opriv, queue);
+ tx_pending_pkts = nrf_wifi_utils_q_len(queue);
shell_fprintf(
sh,
diff --git a/drivers/wifi/nrfwifi/src/wpa_supp_if.c b/drivers/wifi/nrfwifi/src/wpa_supp_if.c
index d99e4fa..6abddfb 100644
--- a/drivers/wifi/nrfwifi/src/wpa_supp_if.c
+++ b/drivers/wifi/nrfwifi/src/wpa_supp_if.c
@@ -1172,8 +1172,8 @@
vif_ctx_zep->signal_info = si;
- rssi_record_elapsed_time_ms = nrf_wifi_osal_time_elapsed_us(fmac_dev_ctx->fpriv->opriv,
- vif_ctx_zep->rssi_record_timestamp_us) / 1000;
+ rssi_record_elapsed_time_ms =
+ nrf_wifi_osal_time_elapsed_us(vif_ctx_zep->rssi_record_timestamp_us) / 1000;
if (rssi_record_elapsed_time_ms > CONFIG_NRF70_RSSI_STALE_TIMEOUT_MS) {
ret = nrf_wifi_fmac_get_station(rpu_ctx_zep->rpu_ctx, vif_ctx_zep->vif_idx, bssid);
diff --git a/drivers/xen/dom0/domctl.c b/drivers/xen/dom0/domctl.c
index 2b1e3a6..5d51785 100644
--- a/drivers/xen/dom0/domctl.c
+++ b/drivers/xen/dom0/domctl.c
@@ -114,8 +114,9 @@
};
rc = do_domctl(&domctl);
- if (rc)
+ if (rc) {
return rc;
+ }
*size_mb = domctl.u.paging_mempool.size;
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index a16cce8..7828821 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -132,9 +132,10 @@
__ASSERT(cb != NULL, "%s: NULL callback for evtchn #%u\n",
__func__, port);
- if (event_channels[port].cb != empty_callback)
+ if (event_channels[port].cb != empty_callback) {
LOG_WRN("%s: re-bind callback for evtchn #%u\n",
__func__, port);
+ }
event_channels[port].priv = data;
event_channels[port].cb = cb;
diff --git a/dts/arm/adi/max32/max32655.dtsi b/dts/arm/adi/max32/max32655.dtsi
index c09ec12..fbc3624 100644
--- a/dts/arm/adi/max32/max32655.dtsi
+++ b/dts/arm/adi/max32/max32655.dtsi
@@ -75,5 +75,25 @@
clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
status = "disabled";
};
+
+ spi0: spi@400be000 {
+ compatible = "adi,max32-spi";
+ reg = <0x400be000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
+ interrupts = <56 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32662.dtsi b/dts/arm/adi/max32/max32662.dtsi
index 5a3e22d..1da8771 100644
--- a/dts/arm/adi/max32/max32662.dtsi
+++ b/dts/arm/adi/max32/max32662.dtsi
@@ -6,6 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max32662_dma.h>
&flash0 {
reg = <0x10000000 DT_SIZE_K(256)>;
@@ -58,5 +59,35 @@
compatible = "mmio-sram";
reg = <0x20013000 DT_SIZE_K(4)>;
};
+
+ dma0: dma@40028000 {
+ compatible = "adi,max32-dma";
+ reg = <0x40028000 0x1000>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+ interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
+ dma-channels = <4>;
+ status = "disabled";
+ #dma-cells = <2>;
+ };
+
+ spi0: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40047000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40047000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+ interrupts = <17 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi
index e9fd4bc..0b452e3 100644
--- a/dts/arm/adi/max32/max32666.dtsi
+++ b/dts/arm/adi/max32/max32666.dtsi
@@ -96,5 +96,55 @@
erase-block-size = <8192>;
};
};
+
+ dma0: dma@40028000 {
+ compatible = "adi,max32-dma";
+ reg = <0x40028000 0x1000>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+ interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
+ dma-channels = <8>;
+ status = "disabled";
+ #dma-cells = <2>;
+ };
+
+ dma1: dma@40035000 {
+ compatible = "adi,max32-dma";
+ reg = <0x40035000 0x1000>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
+ interrupts = <72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
+ dma-channels = <8>;
+ status = "disabled";
+ #dma-cells = <2>;
+ };
+
+ spi0: spi@400be000 {
+ compatible = "adi,max32-spi";
+ reg = <0x400be000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS1 14>;
+ interrupts = <56 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
+
+ spi2: spi@40047000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40047000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+ interrupts = <17 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32670.dtsi b/dts/arm/adi/max32/max32670.dtsi
index d4c40c1..3015533 100644
--- a/dts/arm/adi/max32/max32670.dtsi
+++ b/dts/arm/adi/max32/max32670.dtsi
@@ -85,5 +85,35 @@
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
status = "disabled";
};
+
+ spi0: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40047000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40047000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+ interrupts = <17 0>;
+ status = "disabled";
+ };
+
+ spi2: spi@40048000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40048000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
+ interrupts = <18 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32672.dtsi b/dts/arm/adi/max32/max32672.dtsi
index ac2db6e..b2cbad5 100644
--- a/dts/arm/adi/max32/max32672.dtsi
+++ b/dts/arm/adi/max32/max32672.dtsi
@@ -104,5 +104,35 @@
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
status = "disabled";
};
+
+ spi0: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40047000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40047000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+ interrupts = <17 0>;
+ status = "disabled";
+ };
+
+ spi2: spi@40048000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40048000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
+ interrupts = <18 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32675.dtsi b/dts/arm/adi/max32/max32675.dtsi
index 8ab6a74..5c16ae5 100644
--- a/dts/arm/adi/max32/max32675.dtsi
+++ b/dts/arm/adi/max32/max32675.dtsi
@@ -6,6 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max32675_dma.h>
&flash0 {
reg = <0x10000000 DT_SIZE_K(384)>;
@@ -59,5 +60,25 @@
compatible = "mmio-sram";
reg = <0x20024000 DT_SIZE_K(16)>;
};
+
+ dma0: dma@40028000 {
+ compatible = "adi,max32-dma";
+ reg = <0x40028000 0x1000>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+ interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
+ dma-channels = <8>;
+ status = "disabled";
+ #dma-cells = <2>;
+ };
+
+ spi1: spi@40047000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40047000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+ interrupts = <17 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32680.dtsi b/dts/arm/adi/max32/max32680.dtsi
index decfaaf..fb87049 100644
--- a/dts/arm/adi/max32/max32680.dtsi
+++ b/dts/arm/adi/max32/max32680.dtsi
@@ -75,5 +75,25 @@
clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
status = "disabled";
};
+
+ spi0: spi@400be000 {
+ compatible = "adi,max32-spi";
+ reg = <0x400be000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
+ interrupts = <56 0>;
+ status = "disabled";
+ };
+
+ spi1: spi@40046000 {
+ compatible = "adi,max32-spi";
+ reg = <0x40046000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+ interrupts = <16 0>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/arm/adi/max32/max32690.dtsi b/dts/arm/adi/max32/max32690.dtsi
index f0fe7d9..d5277ee3 100644
--- a/dts/arm/adi/max32/max32690.dtsi
+++ b/dts/arm/adi/max32/max32690.dtsi
@@ -21,10 +21,6 @@
erase-block-size = <16384>;
};
-&gcr {
- /delete-property/ sysclk-prescaler;
-};
-
&pinctrl {
reg = <0x40008000 0x3220>;
diff --git a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
index 824729c..de76a84 100644
--- a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
@@ -3,6 +3,7 @@
#include <arm/armv7-m.dtsi>
#include <mem.h>
#include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
@@ -22,6 +23,32 @@
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
+ cpu-power-states = <&idle &suspend_to_ram>;
+ };
+
+ power-states {
+ idle: idle {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-idle";
+ /* As Apollo3blue datasheet, run_to_sleep and sleep_to_run
+ * transition time are both lower than 1us, but considering
+ * the software overhead we set a bigger value.
+ */
+ min-residency-us = <100>;
+ exit-latency-us = <5>;
+ };
+
+ suspend_to_ram: suspend_to_ram {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-ram";
+ /* As Apollo3blue datasheet, run_to_deepsleep transition time is
+ * the software overhead 1us and deepsleep_to_run transition time
+ * is about 25us,but considering the software overhead, we set
+ * a bigger value.
+ */
+ min-residency-us = <2000>;
+ exit-latency-us = <125>;
+ };
};
};
@@ -148,6 +175,7 @@
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
+ zephyr,pm-device-runtime-auto;
};
uart1: uart@4001d000 {
@@ -158,6 +186,7 @@
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
+ zephyr,pm-device-runtime-auto;
};
spi0: spi@50004000 {
@@ -167,6 +196,7 @@
interrupts = <6 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
+ zephyr,pm-device-runtime-auto;
};
spi1: spi@50005000 {
@@ -176,6 +206,7 @@
interrupts = <7 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
+ zephyr,pm-device-runtime-auto;
};
spi2: spi@50006000 {
@@ -185,6 +216,7 @@
interrupts = <8 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
+ zephyr,pm-device-runtime-auto;
};
spi3: spi@50007000 {
@@ -194,6 +226,7 @@
interrupts = <9 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
+ zephyr,pm-device-runtime-auto;
};
spi4: spi@50008000 {
@@ -203,6 +236,7 @@
interrupts = <10 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
+ zephyr,pm-device-runtime-auto;
};
spi5: spi@50009000 {
@@ -212,6 +246,7 @@
interrupts = <11 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
+ zephyr,pm-device-runtime-auto;
};
i2c0: i2c@50004000 {
@@ -221,6 +256,7 @@
interrupts = <6 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
+ zephyr,pm-device-runtime-auto;
};
i2c1: i2c@50005000 {
@@ -230,6 +266,7 @@
interrupts = <7 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
+ zephyr,pm-device-runtime-auto;
};
i2c2: i2c@50006000 {
@@ -239,6 +276,7 @@
interrupts = <8 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
+ zephyr,pm-device-runtime-auto;
};
i2c3: i2c@50007000 {
@@ -248,6 +286,7 @@
interrupts = <9 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
+ zephyr,pm-device-runtime-auto;
};
i2c4: i2c@50008000 {
@@ -257,6 +296,7 @@
interrupts = <10 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
+ zephyr,pm-device-runtime-auto;
};
i2c5: i2c@50009000 {
@@ -266,6 +306,18 @@
interrupts = <11 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
+ zephyr,pm-device-runtime-auto;
+ };
+
+ adc0: adc@50010000 {
+ reg = <0x50010000 0x400>;
+ interrupts = <18 0>;
+ interrupt-names = "ADC";
+ channel-count = <10>;
+ internal-vref-mv = <1500>;
+ status = "disabled";
+ #io-channel-cells = <1>;
+ ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
};
mspi0: spi@40020000 {
diff --git a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
index d3e2368..e41e17f 100644
--- a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
@@ -3,6 +3,7 @@
#include <arm/armv7-m.dtsi>
#include <mem.h>
#include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
@@ -22,6 +23,32 @@
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
+ cpu-power-states = <&idle &suspend_to_ram>;
+ };
+
+ power-states {
+ idle: idle {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-idle";
+ /* As Apollo3blueplus datasheet, run_to_sleep and sleep_to_run
+ * transition time are both lower than 1us, but considering
+ * the software overhead we set a bigger value.
+ */
+ min-residency-us = <100>;
+ exit-latency-us = <5>;
+ };
+
+ suspend_to_ram: suspend_to_ram {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-ram";
+ /* As Apollo3blueplus datasheet, run_to_deepsleep transition time
+ * is the software overhead 1us and deepsleep_to_run transition
+ * time is about 25us,but considering the software overhead,
+ * we set a bigger value.
+ */
+ min-residency-us = <2000>;
+ exit-latency-us = <125>;
+ };
};
};
@@ -166,6 +193,7 @@
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
+ zephyr,pm-device-runtime-auto;
};
uart1: uart@4001d000 {
@@ -176,6 +204,7 @@
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
+ zephyr,pm-device-runtime-auto;
};
spi0: spi@50004000 {
@@ -185,6 +214,7 @@
interrupts = <6 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
+ zephyr,pm-device-runtime-auto;
};
spi1: spi@50005000 {
@@ -194,6 +224,7 @@
interrupts = <7 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
+ zephyr,pm-device-runtime-auto;
};
spi2: spi@50006000 {
@@ -203,6 +234,7 @@
interrupts = <8 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
+ zephyr,pm-device-runtime-auto;
};
spi3: spi@50007000 {
@@ -212,6 +244,7 @@
interrupts = <9 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
+ zephyr,pm-device-runtime-auto;
};
spi4: spi@50008000 {
@@ -221,6 +254,7 @@
interrupts = <10 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
+ zephyr,pm-device-runtime-auto;
};
spi5: spi@50009000 {
@@ -230,6 +264,7 @@
interrupts = <11 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
+ zephyr,pm-device-runtime-auto;
};
i2c0: i2c@50004000 {
@@ -239,6 +274,7 @@
interrupts = <6 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
+ zephyr,pm-device-runtime-auto;
};
i2c1: i2c@50005000 {
@@ -248,6 +284,7 @@
interrupts = <7 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
+ zephyr,pm-device-runtime-auto;
};
i2c2: i2c@50006000 {
@@ -257,6 +294,7 @@
interrupts = <8 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
+ zephyr,pm-device-runtime-auto;
};
i2c3: i2c@50007000 {
@@ -266,6 +304,7 @@
interrupts = <9 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
+ zephyr,pm-device-runtime-auto;
};
i2c4: i2c@50008000 {
@@ -275,6 +314,7 @@
interrupts = <10 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
+ zephyr,pm-device-runtime-auto;
};
i2c5: i2c@50009000 {
@@ -284,6 +324,18 @@
interrupts = <11 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
+ zephyr,pm-device-runtime-auto;
+ };
+
+ adc0: adc@50010000 {
+ reg = <0x50010000 0x400>;
+ interrupts = <18 0>;
+ interrupt-names = "ADC";
+ channel-count = <10>;
+ internal-vref-mv = <1500>;
+ status = "disabled";
+ #io-channel-cells = <1>;
+ ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
};
mspi0: mspi@50014000 {
diff --git a/dts/arm/nordic/nrf9280_cpuapp.dtsi b/dts/arm/nordic/nrf9280_cpuapp.dtsi
new file mode 100644
index 0000000..29edae3
--- /dev/null
+++ b/dts/arm/nordic/nrf9280_cpuapp.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf9280.dtsi>
+
+cpu: &cpuapp {};
+systick: &cpuapp_systick {};
+nvic: &cpuapp_nvic {};
+cpuppr_vevif: &cpuppr_vevif_tx {};
+cpusys_vevif: &cpusys_vevif_tx {};
+wdt010: &cpuapp_wdt010 {};
+wdt011: &cpuapp_wdt011 {};
+
+/delete-node/ &cpuppr;
+/delete-node/ &cpurad;
+/delete-node/ &cpurad_peripherals;
+/delete-node/ &cpurad_ppb;
+/delete-node/ &cpurad_ram0;
+
+/ {
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&cpuapp_nvic>;
+ ranges;
+ };
+};
+
+&cpuapp_ppb {
+ compatible = "simple-bus";
+ ranges;
+};
+
+&cpusec_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpuapp_bellboard {
+ compatible = "nordic,nrf-bellboard-rx";
+};
+
+&cpurad_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpucell_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&gpiote130 {
+ interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&gpiote131 {
+ interrupts = <107 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&grtc {
+ interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>;
+};
diff --git a/dts/arm/nordic/nrf9280_cpurad.dtsi b/dts/arm/nordic/nrf9280_cpurad.dtsi
new file mode 100644
index 0000000..265cd62
--- /dev/null
+++ b/dts/arm/nordic/nrf9280_cpurad.dtsi
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf9280.dtsi>
+
+cpu: &cpurad {};
+systick: &cpurad_systick {};
+nvic: &cpurad_nvic {};
+cpuppr_vevif: &cpuppr_vevif_tx {};
+cpusys_vevif: &cpusys_vevif_tx {};
+wdt010: &cpurad_wdt010 {};
+wdt011: &cpurad_wdt011 {};
+
+/delete-node/ &cpuapp;
+/delete-node/ &cpuapp_peripherals;
+/delete-node/ &cpuapp_ppb;
+/delete-node/ &cpuapp_ram0;
+/delete-node/ &cpuppr;
+
+/ {
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&cpurad_nvic>;
+ ranges;
+ };
+};
+
+&cpurad_ppb {
+ compatible = "simple-bus";
+ ranges;
+};
+
+&cpusec_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpuapp_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpurad_bellboard {
+ compatible = "nordic,nrf-bellboard-rx";
+};
+
+&gpiote130 {
+ interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&grtc {
+ owned-channels = <7 8 9 10 11 12 13 14 15>;
+ child-owned-channels = <8 9 10 11 12>;
+ nonsecure-channels = <8 9 10 11 12>;
+ interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>,
+ <109 NRF_DEFAULT_IRQ_PRIORITY>,
+ <110 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&dppic130 {
+ owned-channels = <0>;
+ sink-channels = <0>;
+ nonsecure-channels = <0>;
+ status = "okay";
+};
+
+&dppic132 {
+ owned-channels = <0>;
+ source-channels = <0>;
+ nonsecure-channels = <0>;
+ status = "okay";
+};
+
+&ipct130 {
+ owned-channels = <0>;
+ source-channel-links = <0 3 0>;
+ status = "okay";
+};
diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi
index 1dd4530..a0f5119 100644
--- a/dts/arm/nuvoton/m2l31x.dtsi
+++ b/dts/arm/nuvoton/m2l31x.dtsi
@@ -48,6 +48,7 @@
clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 |
NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>;
core-clock = <DT_FREQ_M(72)>;
+ powerdown-mode = <NUMAKER_CLK_PMUCTL_PDMSEL_DPD0>;
pcc: peripheral-clock-controller {
compatible = "nuvoton,numaker-pcc";
diff --git a/dts/arm/nuvoton/m46x.dtsi b/dts/arm/nuvoton/m46x.dtsi
index cdab366..df53c08 100644
--- a/dts/arm/nuvoton/m46x.dtsi
+++ b/dts/arm/nuvoton/m46x.dtsi
@@ -51,6 +51,7 @@
#clock-cells = <0>;
/* hxt = "enable"; */
lxt = "enable";
+ hirc48m = "enable";
clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 |
NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>;
core-clock = <200000000>;
@@ -606,8 +607,8 @@
reg = <0x400c0000 0x1000>;
interrupts = <53 0>;
resets = <&rst NUMAKER_USBD_RST>;
- clocks = <&pcc NUMAKER_USBD_MODULE NUMAKER_CLK_CLKSEL0_USBSEL_PLL_DIV2
- NUMAKER_CLK_CLKDIV0_USB(2)>;
+ clocks = <&pcc NUMAKER_USBD_MODULE NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M
+ NUMAKER_CLK_CLKDIV0_USB(1)>;
dma-buffer-size = <1536>;
status = "disabled";
num-bidir-endpoints = <25>;
diff --git a/dts/arm/nuvoton/npcm/npcm.dtsi b/dts/arm/nuvoton/npcm/npcm.dtsi
new file mode 100644
index 0000000..c16607b
--- /dev/null
+++ b/dts/arm/nuvoton/npcm/npcm.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m4";
+ reg = <0>;
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nuvoton/npcm/npcm4.dtsi b/dts/arm/nuvoton/npcm/npcm4.dtsi
new file mode 100644
index 0000000..b23a80a
--- /dev/null
+++ b/dts/arm/nuvoton/npcm/npcm4.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device tree declarations of npcm soc family */
+#include "npcm.dtsi"
+
+/ {
+ soc {
+
+ mdc: mdc@4000c000 {
+ compatible = "syscon";
+ reg = <0x4000c000 0xa>;
+ reg-io-width = <1>;
+ };
+
+ mdc_header: mdc@4000c00a {
+ compatible = "syscon";
+ reg = <0x4000c00a 0x4>;
+ reg-io-width = <2>;
+ };
+ };
+
+ soc-if {
+ };
+};
diff --git a/dts/arm/nuvoton/npcm400.dtsi b/dts/arm/nuvoton/npcm400.dtsi
new file mode 100644
index 0000000..580d781
--- /dev/null
+++ b/dts/arm/nuvoton/npcm400.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device tree declarations of npcm soc family */
+#include <mem.h>
+#include "npcm/npcm4.dtsi"
+
+/ {
+ flash0: flash@80000 {
+ reg = <0x00080000 DT_SIZE_M(1)>;
+ };
+
+ sram0: memory@10008000 {
+ compatible = "mmio-sram";
+ reg = <0x10008000 DT_SIZE_K(764)>;
+ };
+
+ soc {
+ };
+};
diff --git a/dts/arm/nxp/nxp_imx93_m33.dtsi b/dts/arm/nxp/nxp_imx93_m33.dtsi
new file mode 100644
index 0000000..22a87c6
--- /dev/null
+++ b/dts/arm/nxp/nxp_imx93_m33.dtsi
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <mem.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m33";
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mpu: mpu@e000ed90 {
+ compatible = "arm,armv8m-mpu";
+ reg = <0xe000ed90 0x40>;
+ };
+ };
+ };
+
+ soc {
+ itcm: itcm@ffe0000 {
+ compatible = "nxp,imx-itcm";
+ reg = <0xffe0000 DT_SIZE_K(128)>;
+ };
+
+ dtcm: dtcm@20000000 {
+ compatible = "nxp,imx-dtcm";
+ reg = <0x20000000 DT_SIZE_K(128)>;
+ };
+
+ iomuxc: iomuxc@443c0000 {
+ compatible = "nxp,imx-iomuxc";
+ reg = <0x443c0000 DT_SIZE_K(64)>;
+ status = "okay";
+ pinctrl: pinctrl {
+ status = "okay";
+ compatible = "nxp,imx93-pinctrl";
+ };
+ };
+
+ ccm: ccm@44450000 {
+ compatible = "nxp,imx-ccm-rev2";
+ reg = <0x44450000 DT_SIZE_K(64)>;
+ #clock-cells = <3>;
+ };
+
+ gpio1: gpio@47400000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x47400000 DT_SIZE_K(64)>;
+ interrupts = <10 0>, <11 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x43810000 DT_SIZE_K(64)>;
+ interrupts = <57 0>, <58 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x43820000 DT_SIZE_K(64)>;
+ interrupts = <59 0>, <60 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio4: gpio@43830000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x43830000 DT_SIZE_K(64)>;
+ interrupts = <189 0>, <190 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
+ reg = <0x44390000 DT_SIZE_K(64)>;
+ interrupts = <20 3>;
+ clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>;
+ status = "disabled";
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <3>;
+};
+
+&gpio1 {
+ pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io00>,
+ <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>,
+ <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>,
+ <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>,
+ <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>,
+ <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>,
+ <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>,
+ <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>,
+ <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>,
+ <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>,
+ <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>,
+ <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>,
+ <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>,
+ <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>,
+ <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>,
+ <&iomuxc1_wdog_any_gpio_io_gpio1_io15>;
+};
+
+&gpio2 {
+ pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io00>,
+ <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>,
+ <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>,
+ <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>,
+ <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>,
+ <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>,
+ <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>,
+ <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>,
+ <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>,
+ <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>,
+ <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>,
+ <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>,
+ <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>,
+ <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>,
+ <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>,
+ <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>,
+ <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>,
+ <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>,
+ <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>,
+ <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>,
+ <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>,
+ <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>,
+ <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>,
+ <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>,
+ <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>,
+ <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>,
+ <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>,
+ <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>,
+ <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>,
+ <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>;
+};
+
+&gpio3 {
+ pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>,
+ <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>,
+ <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>,
+ <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>,
+ <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>,
+ <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>,
+ <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>,
+ <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>,
+ <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>,
+ <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>,
+ <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>,
+ <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>,
+ <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>,
+ <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>,
+ <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>,
+ <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>,
+ <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>,
+ <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>,
+ <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>,
+ <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>,
+ <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>,
+ <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>,
+ <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>,
+ <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>,
+ <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>,
+ <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>,
+ <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>,
+ <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>,
+ <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>,
+ <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>,
+ <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>,
+ <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>;
+};
+
+&gpio4 {
+ pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io00>,
+ <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>,
+ <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>,
+ <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>,
+ <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>,
+ <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>,
+ <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>,
+ <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>,
+ <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>,
+ <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>,
+ <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>,
+ <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>,
+ <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>,
+ <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>,
+ <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>,
+ <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>,
+ <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>,
+ <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>,
+ <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>,
+ <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>,
+ <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>,
+ <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>,
+ <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>,
+ <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>,
+ <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>,
+ <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>,
+ <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>,
+ <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>,
+ <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>,
+ <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>;
+};
diff --git a/dts/arm/nxp/nxp_ke1xz.dtsi b/dts/arm/nxp/nxp_ke1xz.dtsi
index e5b39f6..465b9f5 100644
--- a/dts/arm/nxp/nxp_ke1xz.dtsi
+++ b/dts/arm/nxp/nxp_ke1xz.dtsi
@@ -25,6 +25,32 @@
compatible = "arm,cortex-m0+";
clock-frequency = <48000000>;
reg = <0>;
+ cpu-power-states = <&idle &stop &pstop1 &pstop2>;
+ };
+
+ power-states {
+ idle: idle {
+ compatible = "zephyr,power-state";
+ power-state-name = "runtime-idle";
+ };
+
+ stop: stop {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-idle";
+ substate-id = <0>;
+ };
+
+ pstop1: pstop1 {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-idle";
+ substate-id = <1>;
+ };
+
+ pstop2: pstop2 {
+ compatible = "zephyr,power-state";
+ power-state-name = "suspend-to-idle";
+ substate-id = <2>;
+ };
};
};
@@ -150,6 +176,16 @@
status = "disabled";
};
+ lptmr0: lptmr@40040000 {
+ compatible = "nxp,lptmr";
+ reg = <0x40040000 0x1000>;
+ interrupts = <29 0>;
+ clock-frequency = <128000>;
+ prescaler = <1>;
+ clk-source = <1>;
+ resolution = <16>;
+ };
+
porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0x1000>;
@@ -180,6 +216,26 @@
clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>;
};
+ pmc: pmc@4007d000 {
+ reg = <0x4007d000 0x1000>;
+
+ lpo: lpo128k {
+ compatible = "fixed-clock";
+ clock-frequency = <128000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ wdog: watchdog@40052000 {
+ compatible = "nxp,kinetis-wdog32";
+ reg = <0x40052000 0x1000>;
+ interrupts = <28 0>;
+ clocks = <&lpo>;
+ clk-source = <1>;
+ clk-divider = <256>;
+ status = "disabled";
+ };
+
gpios0: gpios0@400ff000 {
compatible = "nxp,gpio-cluster";
interrupts = <7 2>;
diff --git a/dts/arm/nxp/nxp_lpc55S06_ns.dtsi b/dts/arm/nxp/nxp_lpc55S06_ns.dtsi
index ac62b6f..fc7cd24 100644
--- a/dts/arm/nxp/nxp_lpc55S06_ns.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S06_ns.dtsi
@@ -6,7 +6,7 @@
/ {
soc {
- sram: sram@400000 {
+ sram: sram@4000000 {
ranges = <0x4000000 0x4000000 0x20000000>;
};
diff --git a/dts/arm/nxp/nxp_lpc55S16_ns.dtsi b/dts/arm/nxp/nxp_lpc55S16_ns.dtsi
index ba52753..51f28ae 100644
--- a/dts/arm/nxp/nxp_lpc55S16_ns.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S16_ns.dtsi
@@ -6,7 +6,7 @@
/ {
soc {
- sram: sram@400000 {
+ sram: sram@4000000 {
ranges = <0x4000000 0x4000000 0x20000000>;
};
diff --git a/dts/arm/nxp/nxp_lpc55S26_ns.dtsi b/dts/arm/nxp/nxp_lpc55S26_ns.dtsi
new file mode 100644
index 0000000..4f6686b
--- /dev/null
+++ b/dts/arm/nxp/nxp_lpc55S26_ns.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Maxime Vincent <maxime@veemax.be>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ soc {
+ sram: sram@400000 {
+ ranges = <0x4000000 0x4000000 0x20000000>;
+ };
+
+ peripheral: peripheral@40000000 {
+ ranges = <0x0 0x40000000 0x10000000>;
+ };
+ };
+};
+
+#include "nxp_lpc55S2x_common.dtsi"
+
+&iap {
+ status = "okay";
+};
diff --git a/dts/arm/nxp/nxp_lpc55S2x.dtsi b/dts/arm/nxp/nxp_lpc55S2x.dtsi
index 274727d..22177cf 100644
--- a/dts/arm/nxp/nxp_lpc55S2x.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S2x.dtsi
@@ -11,7 +11,7 @@
/ {
soc {
- sram: sram@400000 {
+ sram: sram@4000000 {
ranges = <0x4000000 0x4000000 0x20000000>;
};
diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
index bb29407..9f659c8 100644
--- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
@@ -256,6 +256,16 @@
status = "disabled";
};
+ sc_timer: pwm@85000 {
+ compatible = "nxp,sctimer-pwm";
+ reg = <0x85000 0x1000>;
+ interrupts = <12 0>;
+ status = "disabled";
+ clocks = <&syscon MCUX_SCTIMER_CLK>;
+ prescaler = <2>;
+ #pwm-cells = <3>;
+ };
+
hs_lspi: spi@9f000 {
compatible = "nxp,lpc-spi";
/* Enabling cs-gpios below will allow using GPIO CS,
diff --git a/dts/arm/nxp/nxp_lpc55S36_ns.dtsi b/dts/arm/nxp/nxp_lpc55S36_ns.dtsi
index 92e8fc1..7292aca 100644
--- a/dts/arm/nxp/nxp_lpc55S36_ns.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S36_ns.dtsi
@@ -6,7 +6,7 @@
/ {
soc {
- sram: sram@400000 {
+ sram: sram@4000000 {
ranges = <0x4000000 0x4000000 0x20000000>;
};
diff --git a/dts/arm/nxp/nxp_mcxn23x.dtsi b/dts/arm/nxp/nxp_mcxn23x.dtsi
new file mode 100644
index 0000000..6585f48
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxn23x.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+
+/ {
+ soc {
+ sram: sram@14000000 {
+ ranges = <0x4000000 0x14000000 0x20000000>;
+ };
+
+ peripheral: peripheral@50000000 {
+ ranges = <0x0 0x50000000 0x10000000>;
+
+ ftfe: flash-controller@43000 {
+ ranges = <0x0 0x10000000 0x4000000>;
+ };
+ };
+ };
+};
+
+#include "nxp_mcxn23x_common.dtsi"
+
+/*
+ * Explicitly enable FMU after we include the common dtsi file,
+ * which will set it to disabled.
+ */
+&fmu {
+ status = "okay";
+};
diff --git a/dts/arm/nxp/nxp_mcxn23x_common.dtsi b/dts/arm/nxp/nxp_mcxn23x_common.dtsi
new file mode 100644
index 0000000..53965dd
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxn23x_common.dtsi
@@ -0,0 +1,691 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-m33f";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mpu: mpu@e000ed90 {
+ compatible = "arm,armv8m-mpu";
+ reg = <0xe000ed90 0x40>;
+ };
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "nxp,kinetis-pinctrl";
+ status = "okay";
+ };
+};
+
+&sram {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sramx: memory@4000000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ reg = <0x4000000 DT_SIZE_K(96)>;
+ zephyr,memory-region = "SRAM1";
+ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+ };
+
+ /* mcxn23x Memory configurations:
+ *
+ * RAM blocks RAMA through SRAM4 are contiguous address ranges
+ *
+ * MCXN23X: 352KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
+ * RAMC: 64K, RAMD: 64K, RAME: 64K
+ */
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(256)>;
+ };
+};
+
+&peripheral {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ syscon: syscon@0 {
+ compatible = "nxp,lpc-syscon";
+ reg = <0x0 0x4000>;
+ #clock-cells = <1>;
+ };
+
+ porta: pinmux@116000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x116000 0x1000>;
+ clocks = <&syscon MCUX_PORT0_CLK>;
+ };
+
+ portb: pinmux@117000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x117000 0x1000>;
+ clocks = <&syscon MCUX_PORT1_CLK>;
+ };
+
+ portc: pinmux@118000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x118000 0x1000>;
+ clocks = <&syscon MCUX_PORT2_CLK>;
+ };
+
+ portd: pinmux@119000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x119000 0x1000>;
+ clocks = <&syscon MCUX_PORT3_CLK>;
+ };
+
+ porte: pinmux@11a000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x11a000 0x1000>;
+ clocks = <&syscon MCUX_PORT4_CLK>;
+ };
+
+ portf: pinmux@42000 {
+ compatible = "nxp,kinetis-pinmux";
+ reg = <0x42000 0x1000>;
+ clocks = <&syscon MCUX_PORT5_CLK>;
+ };
+
+ gpio0: gpio@96000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x96000 0x1000>;
+ interrupts = <17 0>,<18 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&porta>;
+ };
+
+ gpio1: gpio@98000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x98000 0x1000>;
+ interrupts = <19 0>,<20 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&portb>;
+ };
+
+ gpio2: gpio@9a000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x9a000 0x1000>;
+ interrupts = <21 0>,<22 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&portc>;
+ };
+
+ gpio3: gpio@9c000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x9c000 0x1000>;
+ interrupts = <23 0>,<24 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&portd>;
+ };
+
+ gpio4: gpio@9e000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x9e000 0x1000>;
+ interrupts = <25 0>,<26 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&porte>;
+ };
+
+ gpio5: gpio@40000 {
+ compatible = "nxp,kinetis-gpio";
+ status = "disabled";
+ reg = <0x40000 0x1000>;
+ interrupts = <27 0>,<28 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nxp,kinetis-port = <&portf>;
+ };
+
+ flexcomm0: flexcomm@92000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0x92000 0x1000>;
+ interrupts = <35 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm0_lpuart0: lpuart@92000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0x92000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
+ status = "disabled";
+ };
+ flexcomm0_lpspi0: lpspi@92000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0x92000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ flexcomm0_lpi2c0: lpi2c@92800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0x92800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm1: flexcomm@93000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0x93000 0x1000>;
+ interrupts = <36 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm1_lpuart1: lpuart@93000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0x93000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
+ /* DMA channels 0 and 1, muxed to LPUART1 RX and TX */
+ dmas = <&edma0 0 71>, <&edma0 1 72>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm1_lpspi1: lpspi@93000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0x93000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
+ dmas = <&edma0 0 71>, <&edma0 1 72>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm1_lpi2c1: lpi2c@93800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0x93800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm2: flexcomm@94000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0x94000 0x1000>;
+ interrupts = <37 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm2_lpuart2: lpuart@94000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0x94000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
+ /* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
+ dmas = <&edma0 4 73>, <&edma0 5 74>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm2_lpspi2: lpspi@94000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0x94000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */
+ dmas = <&edma0 4 73>, <&edma0 5 74>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm2_lpi2c2: lpi2c@94800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0x94800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm3: flexcomm@95000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0x95000 0x1000>;
+ interrupts = <38 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm3_lpuart3: lpuart@95000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0x95000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
+ status = "disabled";
+ };
+ flexcomm3_lpspi3: lpspi@95000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0x95000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ flexcomm3_lpi2c3: lpi2c@95800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0x95800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm4: flexcomm@b4000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0xb4000 0x1000>;
+ interrupts = <39 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm4_lpuart4: lpuart@b4000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0xb4000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
+ /* DMA channels 2 and 3, muxed to LPUART4 RX and TX */
+ dmas = <&edma0 2 77>, <&edma0 3 78>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm4_lpspi4: lpspi@b4000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0xb4000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */
+ dmas = <&edma0 2 77>, <&edma0 3 78>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ flexcomm4_lpi2c4: lpi2c@b4800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0xb4800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm5: flexcomm@b5000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0xb5000 0x1000>;
+ interrupts = <40 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm5_lpuart5: lpuart@b5000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0xb5000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
+ status = "disabled";
+ };
+ flexcomm5_lpspi5: lpspi@b5000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0xb5000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ flexcomm5_lpi2c5: lpi2c@b5800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0xb5800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm6: flexcomm@b6000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0xb6000 0x1000>;
+ interrupts = <41 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm6_lpuart6: lpuart@b6000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0xb6000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
+ status = "disabled";
+ };
+ flexcomm6_lpspi6: lpspi@b6000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0xb6000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ flexcomm6_lpi2c6: lpi2c@b6800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0xb6800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flexcomm7: flexcomm@b7000 {
+ compatible = "nxp,lp-flexcomm";
+ reg = <0xb7000 0x1000>;
+ interrupts = <42 0>;
+ status = "disabled";
+
+ ranges = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flexcomm7_lpuart7: lpuart@b7000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0xb7000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
+ status = "disabled";
+ };
+ flexcomm7_lpspi7: lpspi@b7000 {
+ compatible = "nxp,imx-lpspi";
+ reg = <0xb7000 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ flexcomm7_lpi2c7: lpi2c@b7800 {
+ compatible = "nxp,imx-lpi2c";
+ reg = <0xb7800 0x1000>;
+ clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ edma0: dma-controller@80000 {
+ #dma-cells = <2>;
+ compatible = "nxp,mcux-edma-v4";
+ dma-channels = <16>;
+ dma-requests = <120>;
+
+ reg = <0x80000 0x1000>;
+ interrupts = <1 0>, <2 0>, <3 0>, <4 0>,
+ <5 0>, <6 0>, <7 0>, <8 0>,
+ <9 0>, <10 0>, <11 0>, <12 0>,
+ <13 0>, <14 0>, <15 0>, <16 0>;
+ no-error-irq;
+ status = "disabled";
+ };
+
+ edma1: dma-controller@a0000 {
+ #dma-cells = <2>;
+ compatible = "nxp,mcux-edma-v4";
+ dma-channels = <16>;
+ dma-requests = <120>;
+
+ reg = <0xa0000 0x1000>;
+ interrupts = <77 0>, <78 0>, <79 0>, <80 0>,
+ <81 0>, <82 0>, <83 0>, <84 0>,
+ <85 0>, <86 0>, <87 0>, <88 0>,
+ <89 0>, <90 0>, <91 0>, <92 0>;
+ no-error-irq;
+ status = "disabled";
+ };
+
+ fmu: flash-controller@43000 {
+ compatible = "nxp,iap-msf1";
+ reg = <0x43000 0x1000>;
+ interrupts = <138 0>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0 DT_SIZE_M(1)>;
+ erase-block-size = <8192>;
+ /* MCXN23x ROM Flash API supports writing of 128B pages. */
+ write-block-size = <128>;
+ };
+ };
+
+ os_timer: timers@49000 {
+ compatible = "nxp,os-timer";
+ reg = <0x49000 0x1000>;
+ interrupts = <57 0>;
+ status = "disabled";
+ };
+
+ wwdt0: watchdog@16000 {
+ compatible = "nxp,lpc-wwdt";
+ reg = <0x16000 0x1000>;
+ interrupts = <152 0>;
+ status = "disabled";
+ clk-divider = <1>;
+ };
+
+ flexpwm0: flexpwm@ce000 {
+ compatible = "nxp,flexpwm";
+ reg = <0xce000 0x1000>;
+ interrupt-names = "RELOAD-ERROR", "FAULT";
+ interrupts = <112 0>, <113 0>;
+ flexpwm0_pwm0: pwm0 {
+ compatible = "nxp,imx-pwm";
+ index = <0>;
+ interrupts = <114 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm0_pwm1: pwm1 {
+ compatible = "nxp,imx-pwm";
+ index = <1>;
+ interrupts = <115 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm0_pwm2: pwm2 {
+ compatible = "nxp,imx-pwm";
+ index = <2>;
+ interrupts = <116 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm0_pwm3: pwm3 {
+ compatible = "nxp,imx-pwm";
+ index = <3>;
+ interrupts = <117 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+ };
+
+ flexpwm1: flexpwm@d0000 {
+ compatible = "nxp,flexpwm";
+ reg = <0xd0000 0x1000>;
+ interrupt-names = "RELOAD-ERROR", "FAULT";
+ interrupts = <118 0>, <119 0>;
+ flexpwm1_pwm0: pwm0 {
+ compatible = "nxp,imx-pwm";
+ index = <0>;
+ interrupts = <120 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm1_pwm1: pwm1 {
+ compatible = "nxp,imx-pwm";
+ index = <1>;
+ interrupts = <121 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm1_pwm2: pwm2 {
+ compatible = "nxp,imx-pwm";
+ index = <2>;
+ interrupts = <122 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+
+ flexpwm1_pwm3: pwm3 {
+ compatible = "nxp,imx-pwm";
+ index = <3>;
+ interrupts = <123 0>;
+ #pwm-cells = <3>;
+ clocks = <&syscon MCUX_BUS_CLK>;
+ nxp,prescaler = <128>;
+ status = "disabled";
+ run-in-wait;
+ };
+ };
+
+ ctimer0: ctimer@c000 {
+ compatible = "nxp,lpc-ctimer";
+ reg = <0xc000 0x1000>;
+ interrupts = <31 0>;
+ status = "disabled";
+ clk-source = <1>;
+ clocks = <&syscon MCUX_CTIMER0_CLK>;
+ mode = <0>;
+ input = <0>;
+ prescale = <0>;
+ };
+
+ ctimer1: ctimer@d000 {
+ compatible = "nxp,lpc-ctimer";
+ reg = <0xd000 0x1000>;
+ interrupts = <32 0>;
+ status = "disabled";
+ clk-source = <1>;
+ clocks = <&syscon MCUX_CTIMER1_CLK>;
+ mode = <0>;
+ input = <0>;
+ prescale = <0>;
+ };
+
+ ctimer2: ctimer@e000 {
+ compatible = "nxp,lpc-ctimer";
+ reg = <0xe000 0x1000>;
+ interrupts = <34 0>;
+ status = "disabled";
+ clk-source = <1>;
+ clocks = <&syscon MCUX_CTIMER2_CLK>;
+ mode = <0>;
+ input = <0>;
+ prescale = <0>;
+ };
+
+ ctimer3: ctimer@f000 {
+ compatible = "nxp,lpc-ctimer";
+ reg = <0xf000 0x1000>;
+ interrupts = <55 0>;
+ status = "disabled";
+ clk-source = <1>;
+ clocks = <&syscon MCUX_CTIMER3_CLK>;
+ mode = <0>;
+ input = <0>;
+ prescale = <0>;
+ };
+
+ ctimer4: ctimer@10000 {
+ compatible = "nxp,lpc-ctimer";
+ reg = <0x10000 0x1000>;
+ interrupts = <56 0>;
+ status = "disabled";
+ clk-source = <1>;
+ clocks = <&syscon MCUX_CTIMER4_CLK>;
+ mode = <0>;
+ input = <0>;
+ prescale = <0>;
+ };
+};
+
+&systick {
+ /*
+ * MCXN23X relies by default on the OS Timer for system clock
+ * implementation, so the SysTick node is not to be enabled.
+ */
+ status = "disabled";
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nxp/nxp_mcxn23x_ns.dtsi b/dts/arm/nxp/nxp_mcxn23x_ns.dtsi
new file mode 100644
index 0000000..c61c047
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxn23x_ns.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ soc {
+ sram: sram@4000000 {
+ ranges = <0x4000000 0x4000000 0x20000000>;
+ };
+
+ peripheral: peripheral@40000000 {
+ ranges = <0x0 0x40000000 0x10000000>;
+ };
+ };
+};
+
+#include "nxp_mcxn23x_common.dtsi"
diff --git a/dts/arm/nxp/nxp_rt1010.dtsi b/dts/arm/nxp/nxp_rt1010.dtsi
index 00f124e..81b7a99 100644
--- a/dts/arm/nxp/nxp_rt1010.dtsi
+++ b/dts/arm/nxp/nxp_rt1010.dtsi
@@ -57,6 +57,8 @@
};
&edma0 {
+ /* Each channel has separate interrupt entry */
+ irq-shared-offset = <0>;
dma-channels = <16>;
};
diff --git a/dts/arm/nxp/nxp_rt118x.dtsi b/dts/arm/nxp/nxp_rt118x.dtsi
new file mode 100644
index 0000000..6151230
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt118x.dtsi
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/clock/imx_ccm_rev2.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m33f";
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mpu: mpu@e000ed90 {
+ compatible = "arm,armv8m-mpu";
+ reg = <0xe000ed90 0x40>;
+ };
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m7";
+ reg = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&peripheral {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * Note that the offsets here are relative to the base address
+ * defined in either nxp_rt118x_cm33_ns.dtsi, nxp_rt118x_cm33.dtsi
+ * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ
+ * between non-secure (0x40000000) and secure modes (0x50000000).
+ */
+ iomuxc: iomuxc@2A10000 {
+ compatible = "nxp,imx-iomuxc";
+ reg = <0x2A10000 0x4000>;
+ pinctrl: pinctrl {
+ status = "okay";
+ compatible = "nxp,mcux-rt11xx-pinctrl";
+ };
+ };
+
+ iomuxc_aon: iomuxc@43C0000 {
+ compatible = "nxp,mcux-rt-pinctrl";
+ reg = <0x43C0000 0x4000>;
+ status = "okay";
+ };
+
+ ccm: ccm@4450000 {
+ compatible = "nxp,imx-ccm-rev2";
+ reg = <0x4450000 0x4000>;
+ #clock-cells = <3>;
+ };
+
+ lpuart1: uart@4380000 {
+ compatible = "nxp,kinetis-lpuart";
+ reg = <0x4380000 0x4000>;
+ interrupts = <19 0>;
+ clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@7400000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x7400000 0x4000>;
+ interrupts = <10 0>, <11 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio4: gpio@3830000 {
+ compatible = "nxp,imx-rgpio";
+ reg = <0x3830000 0x4000>;
+ interrupts = <232 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ lpi2c1: i2c@4340000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4340000 0x4000>;
+ interrupts = <13 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 6>;
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@4350000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4350000 0x4000>;
+ interrupts = <14 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 8>;
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@2530000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2530000 0x4000>;
+ interrupts = <62 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x70 10>;
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@2540000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2540000 0x4000>;
+ interrupts = <63 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x80 24>;
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@2d30000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2d30000 0x4000>;
+ interrupts = <152 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>;
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@2d40000 {
+ compatible = "nxp,imx-lpi2c";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2d40000 0x4000>;
+ interrupts = <153 0>;
+ clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>;
+ status = "disabled";
+ };
+};
+
+&flexspi1 {
+ compatible = "nxp,imx-flexspi";
+ interrupts = <55 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
+};
diff --git a/dts/arm/nxp/nxp_rt118x_cm33.dtsi b/dts/arm/nxp/nxp_rt118x_cm33.dtsi
new file mode 100644
index 0000000..0b3635b
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt118x_cm33.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <mem.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+ soc {
+ itcm: itcm@1FFE0000 {
+ compatible = "nxp,imx-itcm";
+ reg = <0x1FFE0000 DT_SIZE_K(128)>;
+ };
+
+ dtcm: dtcm@30000000 {
+ compatible = "nxp,imx-dtcm";
+ reg = <0x30000000 DT_SIZE_K(128)>;
+ };
+
+ peripheral: peripheral@50000000 {
+ ranges = <0x0 0x50000000 0x10000000>;
+ };
+
+ flexspi1: spi@525e0000 {
+ reg = <0x525e0000 0x4000>,<0x38000000 DT_SIZE_M(128)>;
+ };
+ };
+};
+
+#include <nxp/nxp_rt118x.dtsi>
+
+/ {
+ cpus {
+ /delete-node/ cpu@1;
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <3>;
+};
+
+/*
+ * GPIO pinmux options. These options define the pinmux settings
+ * for GPIO ports on the package, so that the GPIO driver can
+ * select GPIO mux options during GPIO configuration.
+ */
+
+&gpio1{
+ pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
+ <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+ <&iomuxc_aon_gpio_aon_02_gpio1_io02>,
+ <&iomuxc_aon_gpio_aon_03_gpio1_io03>,
+ <&iomuxc_aon_gpio_aon_04_gpio1_io04>,
+ <&iomuxc_aon_gpio_aon_05_gpio1_io05>,
+ <&iomuxc_aon_gpio_aon_06_gpio1_io06>,
+ <&iomuxc_aon_gpio_aon_07_gpio1_io07>,
+ <&iomuxc_aon_gpio_aon_08_gpio1_io08>,
+ <&iomuxc_aon_gpio_aon_09_gpio1_io09>,
+ <&iomuxc_aon_gpio_aon_10_gpio1_io10>,
+ <&iomuxc_aon_gpio_aon_11_gpio1_io11>,
+ <&iomuxc_aon_gpio_aon_12_gpio1_io12>,
+ <&iomuxc_aon_gpio_aon_13_gpio1_io13>,
+ <&iomuxc_aon_gpio_aon_14_gpio1_io14>,
+ <&iomuxc_aon_gpio_aon_15_gpio1_io15>,
+ <&iomuxc_aon_gpio_aon_16_gpio1_io16>,
+ <&iomuxc_aon_gpio_aon_17_gpio1_io17>,
+ <&iomuxc_aon_gpio_aon_18_gpio1_io18>,
+ <&iomuxc_aon_gpio_aon_19_gpio1_io19>,
+ <&iomuxc_aon_gpio_aon_20_gpio1_io20>,
+ <&iomuxc_aon_gpio_aon_21_gpio1_io21>,
+ <&iomuxc_aon_gpio_aon_22_gpio1_io22>,
+ <&iomuxc_aon_gpio_aon_23_gpio1_io23>,
+ <&iomuxc_aon_gpio_aon_24_gpio1_io24>,
+ <&iomuxc_aon_gpio_aon_25_gpio1_io25>,
+ <&iomuxc_aon_gpio_aon_26_gpio1_io26>,
+ <&iomuxc_aon_gpio_aon_27_gpio1_io27>;
+};
+
+&gpio4{
+ pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>,
+ <&iomuxc_gpio_ad_01_gpio4_io01>,
+ <&iomuxc_gpio_ad_02_gpio4_io02>,
+ <&iomuxc_gpio_ad_03_gpio4_io03>,
+ <&iomuxc_gpio_ad_04_gpio4_io04>,
+ <&iomuxc_gpio_ad_05_gpio4_io05>,
+ <&iomuxc_gpio_ad_06_gpio4_io06>,
+ <&iomuxc_gpio_ad_07_gpio4_io07>,
+ <&iomuxc_gpio_ad_08_gpio4_io08>,
+ <&iomuxc_gpio_ad_09_gpio4_io09>,
+ <&iomuxc_gpio_ad_10_gpio4_io10>,
+ <&iomuxc_gpio_ad_11_gpio4_io11>,
+ <&iomuxc_gpio_ad_12_gpio4_io12>,
+ <&iomuxc_gpio_ad_13_gpio4_io13>,
+ <&iomuxc_gpio_ad_14_gpio4_io14>,
+ <&iomuxc_gpio_ad_15_gpio4_io15>,
+ <&iomuxc_gpio_ad_16_gpio4_io16>,
+ <&iomuxc_gpio_ad_17_gpio4_io17>,
+ <&iomuxc_gpio_ad_18_gpio4_io18>,
+ <&iomuxc_gpio_ad_19_gpio4_io19>,
+ <&iomuxc_gpio_ad_20_gpio4_io20>,
+ <&iomuxc_gpio_ad_21_gpio4_io21>,
+ <&iomuxc_gpio_ad_22_gpio4_io22>,
+ <&iomuxc_gpio_ad_23_gpio4_io23>,
+ <&iomuxc_gpio_ad_24_gpio4_io24>,
+ <&iomuxc_gpio_ad_25_gpio4_io25>,
+ <&iomuxc_gpio_ad_26_gpio4_io26>,
+ <&iomuxc_gpio_ad_27_gpio4_io27>,
+ <&iomuxc_gpio_ad_28_gpio4_io28>,
+ <&iomuxc_gpio_ad_29_gpio4_io29>,
+ <&iomuxc_gpio_ad_30_gpio4_io30>,
+ <&iomuxc_gpio_ad_31_gpio4_io31>;
+};
diff --git a/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi
new file mode 100644
index 0000000..c6221e9
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <mem.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+ soc {
+ itcm: itcm@FFE0000 {
+ compatible = "nxp,imx-itcm";
+ reg = <0xFFE0000 DT_SIZE_K(128)>;
+ };
+
+ dtcm: dtcm@20000000 {
+ compatible = "nxp,imx-dtcm";
+ reg = <0x20000000 DT_SIZE_K(128)>;
+ };
+
+ peripheral: peripheral@40000000 {
+ ranges = <0x0 0x40000000 0x10000000>;
+ };
+
+ flexspi1: spi@425e0000 {
+ reg = <0x425e0000 0x4000>,<0x28000000 DT_SIZE_M(128)>;
+ };
+
+ };
+};
+
+#include <nxp/nxp_rt118x.dtsi>
+
+/ {
+ cpus {
+ /delete-node/ cpu@1;
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <3>;
+};
+
+/*
+ * GPIO pinmux options. These options define the pinmux settings
+ * for GPIO ports on the package, so that the GPIO driver can
+ * select GPIO mux options during GPIO configuration.
+ */
+
+&gpio1{
+ pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
+ <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+ <&iomuxc_aon_gpio_aon_02_gpio1_io02>,
+ <&iomuxc_aon_gpio_aon_03_gpio1_io03>,
+ <&iomuxc_aon_gpio_aon_04_gpio1_io04>,
+ <&iomuxc_aon_gpio_aon_05_gpio1_io05>,
+ <&iomuxc_aon_gpio_aon_06_gpio1_io06>,
+ <&iomuxc_aon_gpio_aon_07_gpio1_io07>,
+ <&iomuxc_aon_gpio_aon_08_gpio1_io08>,
+ <&iomuxc_aon_gpio_aon_09_gpio1_io09>,
+ <&iomuxc_aon_gpio_aon_10_gpio1_io10>,
+ <&iomuxc_aon_gpio_aon_11_gpio1_io11>,
+ <&iomuxc_aon_gpio_aon_12_gpio1_io12>,
+ <&iomuxc_aon_gpio_aon_13_gpio1_io13>,
+ <&iomuxc_aon_gpio_aon_14_gpio1_io14>,
+ <&iomuxc_aon_gpio_aon_15_gpio1_io15>,
+ <&iomuxc_aon_gpio_aon_16_gpio1_io16>,
+ <&iomuxc_aon_gpio_aon_17_gpio1_io17>,
+ <&iomuxc_aon_gpio_aon_18_gpio1_io18>,
+ <&iomuxc_aon_gpio_aon_19_gpio1_io19>,
+ <&iomuxc_aon_gpio_aon_20_gpio1_io20>,
+ <&iomuxc_aon_gpio_aon_21_gpio1_io21>,
+ <&iomuxc_aon_gpio_aon_22_gpio1_io22>,
+ <&iomuxc_aon_gpio_aon_23_gpio1_io23>,
+ <&iomuxc_aon_gpio_aon_24_gpio1_io24>,
+ <&iomuxc_aon_gpio_aon_25_gpio1_io25>,
+ <&iomuxc_aon_gpio_aon_26_gpio1_io26>,
+ <&iomuxc_aon_gpio_aon_27_gpio1_io27>;
+};
+
+&gpio4{
+ pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>,
+ <&iomuxc_gpio_ad_01_gpio4_io01>,
+ <&iomuxc_gpio_ad_02_gpio4_io02>,
+ <&iomuxc_gpio_ad_03_gpio4_io03>,
+ <&iomuxc_gpio_ad_04_gpio4_io04>,
+ <&iomuxc_gpio_ad_05_gpio4_io05>,
+ <&iomuxc_gpio_ad_06_gpio4_io06>,
+ <&iomuxc_gpio_ad_07_gpio4_io07>,
+ <&iomuxc_gpio_ad_08_gpio4_io08>,
+ <&iomuxc_gpio_ad_09_gpio4_io09>,
+ <&iomuxc_gpio_ad_10_gpio4_io10>,
+ <&iomuxc_gpio_ad_11_gpio4_io11>,
+ <&iomuxc_gpio_ad_12_gpio4_io12>,
+ <&iomuxc_gpio_ad_13_gpio4_io13>,
+ <&iomuxc_gpio_ad_14_gpio4_io14>,
+ <&iomuxc_gpio_ad_15_gpio4_io15>,
+ <&iomuxc_gpio_ad_16_gpio4_io16>,
+ <&iomuxc_gpio_ad_17_gpio4_io17>,
+ <&iomuxc_gpio_ad_18_gpio4_io18>,
+ <&iomuxc_gpio_ad_19_gpio4_io19>,
+ <&iomuxc_gpio_ad_20_gpio4_io20>,
+ <&iomuxc_gpio_ad_21_gpio4_io21>,
+ <&iomuxc_gpio_ad_22_gpio4_io22>,
+ <&iomuxc_gpio_ad_23_gpio4_io23>,
+ <&iomuxc_gpio_ad_24_gpio4_io24>,
+ <&iomuxc_gpio_ad_25_gpio4_io25>,
+ <&iomuxc_gpio_ad_26_gpio4_io26>,
+ <&iomuxc_gpio_ad_27_gpio4_io27>,
+ <&iomuxc_gpio_ad_28_gpio4_io28>,
+ <&iomuxc_gpio_ad_29_gpio4_io29>,
+ <&iomuxc_gpio_ad_30_gpio4_io30>,
+ <&iomuxc_gpio_ad_31_gpio4_io31>;
+};
diff --git a/dts/arm/nxp/nxp_rt118x_cm7.dtsi b/dts/arm/nxp/nxp_rt118x_cm7.dtsi
new file mode 100644
index 0000000..e99e6a3
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt118x_cm7.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <mem.h>
+
+/ {
+ soc {
+ itcm: itcm@0{
+ compatible = "nxp,imx-itcm";
+ reg = <0x00000000 DT_SIZE_K(256)>;
+ };
+
+ dtcm: dtcm@20000000 {
+ compatible = "nxp,imx-dtcm";
+ reg = <0x20000000 DT_SIZE_K(256)>;
+ };
+
+ peripheral: peripheral@40000000 {
+ ranges = <0x0 0x40000000 0x10000000>;
+ };
+ flexspi1: spi@425e0000 {
+ reg = <0x425e0000 0x4000>,<0x28000000 DT_SIZE_M(128)>;
+ };
+ };
+};
+
+#include <nxp/nxp_rt118x.dtsi>
+
+/ {
+ cpus {
+ /delete-node/ cpu@0;
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <4>;
+};
+
+/*
+ * GPIO pinmux options. These options define the pinmux settings
+ * for GPIO ports on the package, so that the GPIO driver can
+ * select GPIO mux options during GPIO configuration.
+ */
+
+&gpio1{
+ pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
+ <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+ <&iomuxc_aon_gpio_aon_02_gpio1_io02>,
+ <&iomuxc_aon_gpio_aon_03_gpio1_io03>,
+ <&iomuxc_aon_gpio_aon_04_gpio1_io04>,
+ <&iomuxc_aon_gpio_aon_05_gpio1_io05>,
+ <&iomuxc_aon_gpio_aon_06_gpio1_io06>,
+ <&iomuxc_aon_gpio_aon_07_gpio1_io07>,
+ <&iomuxc_aon_gpio_aon_08_gpio1_io08>,
+ <&iomuxc_aon_gpio_aon_09_gpio1_io09>,
+ <&iomuxc_aon_gpio_aon_10_gpio1_io10>,
+ <&iomuxc_aon_gpio_aon_11_gpio1_io11>,
+ <&iomuxc_aon_gpio_aon_12_gpio1_io12>,
+ <&iomuxc_aon_gpio_aon_13_gpio1_io13>,
+ <&iomuxc_aon_gpio_aon_14_gpio1_io14>,
+ <&iomuxc_aon_gpio_aon_15_gpio1_io15>,
+ <&iomuxc_aon_gpio_aon_16_gpio1_io16>,
+ <&iomuxc_aon_gpio_aon_17_gpio1_io17>,
+ <&iomuxc_aon_gpio_aon_18_gpio1_io18>,
+ <&iomuxc_aon_gpio_aon_19_gpio1_io19>,
+ <&iomuxc_aon_gpio_aon_20_gpio1_io20>,
+ <&iomuxc_aon_gpio_aon_21_gpio1_io21>,
+ <&iomuxc_aon_gpio_aon_22_gpio1_io22>,
+ <&iomuxc_aon_gpio_aon_23_gpio1_io23>,
+ <&iomuxc_aon_gpio_aon_24_gpio1_io24>,
+ <&iomuxc_aon_gpio_aon_25_gpio1_io25>,
+ <&iomuxc_aon_gpio_aon_26_gpio1_io26>,
+ <&iomuxc_aon_gpio_aon_27_gpio1_io27>;
+};
+
+&gpio4{
+ pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>,
+ <&iomuxc_gpio_ad_01_gpio4_io01>,
+ <&iomuxc_gpio_ad_02_gpio4_io02>,
+ <&iomuxc_gpio_ad_03_gpio4_io03>,
+ <&iomuxc_gpio_ad_04_gpio4_io04>,
+ <&iomuxc_gpio_ad_05_gpio4_io05>,
+ <&iomuxc_gpio_ad_06_gpio4_io06>,
+ <&iomuxc_gpio_ad_07_gpio4_io07>,
+ <&iomuxc_gpio_ad_08_gpio4_io08>,
+ <&iomuxc_gpio_ad_09_gpio4_io09>,
+ <&iomuxc_gpio_ad_10_gpio4_io10>,
+ <&iomuxc_gpio_ad_11_gpio4_io11>,
+ <&iomuxc_gpio_ad_12_gpio4_io12>,
+ <&iomuxc_gpio_ad_13_gpio4_io13>,
+ <&iomuxc_gpio_ad_14_gpio4_io14>,
+ <&iomuxc_gpio_ad_15_gpio4_io15>,
+ <&iomuxc_gpio_ad_16_gpio4_io16>,
+ <&iomuxc_gpio_ad_17_gpio4_io17>,
+ <&iomuxc_gpio_ad_18_gpio4_io18>,
+ <&iomuxc_gpio_ad_19_gpio4_io19>,
+ <&iomuxc_gpio_ad_20_gpio4_io20>,
+ <&iomuxc_gpio_ad_21_gpio4_io21>,
+ <&iomuxc_gpio_ad_22_gpio4_io22>,
+ <&iomuxc_gpio_ad_23_gpio4_io23>,
+ <&iomuxc_gpio_ad_24_gpio4_io24>,
+ <&iomuxc_gpio_ad_25_gpio4_io25>,
+ <&iomuxc_gpio_ad_26_gpio4_io26>,
+ <&iomuxc_gpio_ad_27_gpio4_io27>,
+ <&iomuxc_gpio_ad_28_gpio4_io28>,
+ <&iomuxc_gpio_ad_29_gpio4_io29>,
+ <&iomuxc_gpio_ad_30_gpio4_io30>,
+ <&iomuxc_gpio_ad_31_gpio4_io31>;
+};
diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi
index 3887104..407e624 100644
--- a/dts/arm/nxp/nxp_rt11xx.dtsi
+++ b/dts/arm/nxp/nxp_rt11xx.dtsi
@@ -11,7 +11,7 @@
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
-#include <zephyr/dt-bindings/pm/imx_spc.h>
+#include <zephyr/dt-bindings/power/imx_spc.h>
#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
/ {
chosen {
diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi
index 89fc98c..3c33a37 100644
--- a/dts/arm/nxp/nxp_rw6xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi
@@ -151,6 +151,16 @@
pmu: pmu@31000 {
reg = <0x31000 0x130>;
compatible = "nxp,rw-pmu";
+ pin0: pin0 {
+ compatible = "nxp,aon-wakeup-pin";
+ interrupts = <100 0>;
+ status = "disabled";
+ };
+ pin1: pin1 {
+ compatible = "nxp,aon-wakeup-pin";
+ interrupts = <101 0>;
+ status = "disabled";
+ };
};
trng: random@14000 {
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
index afad04b..bd41084 100644
--- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -686,7 +686,7 @@
};
};
- can0: can@4741b000 {
+ canxl0: can@4741b000 {
compatible = "nxp,s32-canxl";
reg = <0x4741b000 0x1000>,
<0x47423000 0x1000>,
@@ -700,7 +700,7 @@
clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
};
- can1: can@4751b000 {
+ canxl1: can@4751b000 {
compatible = "nxp,s32-canxl";
reg = <0x4751b000 0x1000>,
<0x47523000 0x1000>,
@@ -713,5 +713,366 @@
interrupt-names = "rx_tx_mru", "error";
clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
};
+
+ flexcan0: can@449a0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ reg = <0x449a0000 0x4000>;
+ clk-source = <0>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 583 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 584 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 585 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan1: can@449b0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ reg = <0x449b0000 0x4000>;
+ clk-source = <0>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan2: can@449c0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x449c0000 0x4000>;
+ interrupts = <GIC_SPI 593 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan3: can@449d0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x449d0000 0x4000>;
+ interrupts = <GIC_SPI 599 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 601 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 602 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan4: can@449e0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x449e0000 0x4000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 607 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 608 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 610 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan5: can@449f0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x449f0000 0x4000>;
+ interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 613 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 614 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 615 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 616 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan6: can@44ba0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44ba0000 0x4000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 619 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 620 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 621 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 622 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan7: can@44bb0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44bb0000 0x4000>;
+ interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 625 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 626 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 627 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 628 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan8: can@44bc0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44bc0000 0x4000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 631 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 632 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 633 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 634 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan9: can@44bd0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44bd0000 0x4000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 637 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 638 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan10: can@44be0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44be0000 0x4000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 643 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 645 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 646 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan11: can@44bf0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44bf0000 0x4000>;
+ interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 649 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 650 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 651 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan12: can@44da0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44da0000 0x4000>;
+ interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 655 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 656 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 657 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 658 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan13: can@44db0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44db0000 0x4000>;
+ interrupts = <GIC_SPI 659 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 663 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan14: can@44dc0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44dc0000 0x4000>;
+ interrupts = <GIC_SPI 665 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan15: can@44dd0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44dd0000 0x4000>;
+ interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 674 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 676 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan16: can@44de0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44de0000 0x4000>;
+ interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan17: can@44df0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44df0000 0x4000>;
+ interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan18: can@44fa0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44fa0000 0x4000>;
+ interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan19: can@44fb0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44fb0000 0x4000>;
+ interrupts = <GIC_SPI 695 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 698 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan20: can@44fc0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44fc0000 0x4000>;
+ interrupts = <GIC_SPI 701 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 703 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 704 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 705 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan21: can@44fd0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44fd0000 0x4000>;
+ interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 709 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 710 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan22: can@44fe0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44fe0000 0x4000>;
+ interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 716 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 717 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 718 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
+ flexcan23: can@44ff0000 {
+ compatible = "nxp,flexcan-fd", "nxp,flexcan";
+ clk-source = <0>;
+ reg = <0x44ff0000 0x4000>;
+ interrupts = <GIC_SPI 719 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 721 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 722 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 723 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 724 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
+ "ored_64_95_mb", "ored_96_127_mb";
+ clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
+ status = "disabled";
+ };
+
};
};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi
new file mode 100644
index 0000000..ed2059d
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra2/r7fa2a1xh.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x00000000 DT_SIZE_K(256)>;
+ };
+ flash1: flash@40100000 {
+ compatible = "soc-nv-flash";
+ reg = <0x40100000 DT_SIZE_K(8)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
new file mode 100644
index 0000000..23e990b
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra2/ra2xx.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/delete-node/ &sci2;
+/delete-node/ &sci3;
+/delete-node/ &ioport6;
+/delete-node/ &ioport7;
+/delete-node/ &ioport8;
+
+/ {
+ soc {
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(32)>;
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(12)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(48)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+
+ sdadcclk: sdadcclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi
new file mode 100644
index 0000000..5839795
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <freq.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m23";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ system: system@4001e000 {
+ compatible = "renesas,ra-system";
+ reg = <0x4001e000 0x1000>;
+ status = "okay";
+ };
+
+ ioport0: gpio@40040000 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040000 0x20>;
+ port = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport1: gpio@40040020 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040020 0x20>;
+ port = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport2: gpio@40040040 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040040 0x20>;
+ port = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport3: gpio@40040060 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040060 0x20>;
+ port = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport4: gpio@40040080 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040080 0x20>;
+ port = <4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport5: gpio@400400a0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400a0 0x20>;
+ port = <5>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport6: gpio@400400c0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400c0 0x20>;
+ port = <6>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport7: gpio@400400e0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400e0 0x20>;
+ port = <7>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport8: gpio@40040100 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040100 0x20>;
+ port = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport9: gpio@40040120 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040120 0x20>;
+ port = <9>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller@40040800 {
+ compatible = "renesas,ra-pinctrl-pfs";
+ reg = <0x40040800 0x3c0>;
+ status = "okay";
+ };
+
+ sci0: sci@40070000 {
+ compatible = "renesas,ra-sci";
+ interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070000 0x20>;
+ clocks = <&pclkb MSTPB 31>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <0>;
+ status = "disabled";
+ };
+ };
+
+ sci1: sci@40070020 {
+ compatible = "renesas,ra-sci";
+ interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070020 0x20>;
+ clocks = <&pclkb MSTPB 30>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <1>;
+ status = "disabled";
+ };
+ };
+
+ sci2: sci@40070040 {
+ compatible = "renesas,ra-sci";
+ interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070040 0x20>;
+ clocks = <&pclkb MSTPB 29>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <2>;
+ status = "disabled";
+ };
+ };
+
+ sci3: sci@40070060 {
+ compatible = "renesas,ra-sci";
+ interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070060 0x20>;
+ clocks = <&pclkb MSTPB 28>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <3>;
+ status = "disabled";
+ };
+ };
+
+ sci9: sci@40070120 {
+ compatible = "renesas,ra-sci";
+ interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070120 0x20>;
+ clocks = <&pclkb MSTPB 22>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <9>;
+ status = "disabled";
+ };
+ };
+
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ id_code: id_code@1010018 {
+ compatible = "zephyr,memory-region";
+ reg = <0x01010018 0x20>;
+ zephyr,memory-region = "ID_CODE";
+ status = "okay";
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <2>;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi
new file mode 100644
index 0000000..f8a45b5
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6e10x.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_M(1)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
new file mode 100644
index 0000000..f446913
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(256)>;
+ };
+
+ ioport6: gpio@400800c0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400800c0 0x20>;
+ port = <6>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport7: gpio@400800e0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400800e0 0x20>;
+ port = <7>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ sci1: sci1@40118100 {
+ compatible = "renesas,ra-sci";
+ interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118100 0x100>;
+ clocks = <&pclka MSTPB 30>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <1>;
+ status = "disabled";
+ };
+ };
+
+ sci2: sci2@40118200 {
+ compatible = "renesas,ra-sci";
+ interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118200 0x100>;
+ clocks = <&pclka MSTPB 29>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <2>;
+ status = "disabled";
+ };
+ };
+
+ sci3: sci3@40118300 {
+ compatible = "renesas,ra-sci";
+ interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118300 0x100>;
+ clocks = <&pclka MSTPB 28>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <3>;
+ status = "disabled";
+ };
+ };
+
+ sci4: sci4@40118400 {
+ compatible = "renesas,ra-sci";
+ interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118400 0x100>;
+ clocks = <&pclka MSTPB 27>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <4>;
+ status = "disabled";
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_HOCO>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pll2: pll2 {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL2 */
+ source = <RA_PLL_SOURCE_DISABLE>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi
new file mode 100644
index 0000000..8ccb1e3
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6e2bb3cfm.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6e2bx.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_K(256)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
new file mode 100644
index 0000000..7110aeb
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(40)>;
+ };
+
+ ioport8: gpio@40080100 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080100 0x20>;
+ port = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ id_code: id_code@100a120 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0100a120 0x10>;
+ zephyr,memory-region = "ID_CODE";
+ status = "okay";
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <10 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ canfdclk: canfdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ cecclk: cecclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ i3cclk: i3cclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
new file mode 100644
index 0000000..f281d51
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
+
+/ {
+ soc {
+ sram0: memory@1ffe0000 {
+ compatible = "mmio-sram";
+ reg = <0x1ffe0000 DT_SIZE_K(256)>;
+ };
+
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_K(512)>;
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(12)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <0>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_USB_CLOCK_DIV_5>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi
new file mode 100644
index 0000000..4a3320b
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6m2ax.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ compatible = "renesas,ra6-flash-controller";
+ reg = <0x407e0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <4 1>, <5 1>;
+ interrupt-names = "frdyi", "fiferr";
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_M(1)>;
+ write-block-size = <128>;
+ erase-block-size = <8192>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
new file mode 100644
index 0000000..82a6333
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@1ffe0000 {
+ compatible = "mmio-sram";
+ reg = <0x1ffe0000 DT_SIZE_K(384)>;
+ };
+
+ sci5: sci5@400700a0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700a0 0x20>;
+ clocks = <&pclka MSTPB 26>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <5>;
+ status = "disabled";
+ };
+ };
+
+ sci6: sci6@400700c0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700c0 0x20>;
+ clocks = <&pclka MSTPB 25>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <6>;
+ status = "disabled";
+ };
+ };
+
+ sci7: sci7@400700e0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700e0 0x20>;
+ clocks = <&pclka MSTPB 24>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <7>;
+ status = "disabled";
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(12)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_1>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <1>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_USB_CLOCK_DIV_5>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi
new file mode 100644
index 0000000..f6ed099
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m3ah3cfc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6m3ax.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_M(2)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
new file mode 100644
index 0000000..b23a8fc
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@1ffe0000 {
+ compatible = "mmio-sram";
+ reg = <0x1ffe0000 DT_SIZE_K(640)>;
+ };
+
+ ioport8: gpio@40040100 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040100 0x20>;
+ port = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport9: gpio@40040120 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040120 0x20>;
+ port = <9>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioporta: gpio@40040140 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040140 0x20>;
+ port = <10>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioportb: gpio@40040160 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040160 0x20>;
+ port = <11>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ sci5: sci5@400700a0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700a0 0x20>;
+ clocks = <&pclka MSTPB 26>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <5>;
+ status = "disabled";
+ };
+ };
+
+ sci6: sci6@400700c0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700c0 0x20>;
+ clocks = <&pclka MSTPB 25>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <6>;
+ status = "disabled";
+ };
+ };
+
+ sci7: sci7@400700e0 {
+ compatible = "renesas,ra-sci";
+ interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x400700e0 0x20>;
+ clocks = <&pclka MSTPB 24>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <7>;
+ status = "disabled";
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(24)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <1>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_USB_CLOCK_DIV_5>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi
new file mode 100644
index 0000000..4ab1124
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6m4ax.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_M(1)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
new file mode 100644
index 0000000..188f686
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(256)>;
+ };
+
+ sci1: sci1@40118100 {
+ compatible = "renesas,ra-sci";
+ interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118100 0x100>;
+ clocks = <&pclka MSTPB 30>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <1>;
+ status = "disabled";
+ };
+ };
+
+ sci2: sci2@40118200 {
+ compatible = "renesas,ra-sci";
+ interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118200 0x100>;
+ clocks = <&pclka MSTPB 29>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <2>;
+ status = "disabled";
+ };
+ };
+
+ sci3: sci3@40118300 {
+ compatible = "renesas,ra-sci";
+ interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118300 0x100>;
+ clocks = <&pclka MSTPB 28>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <3>;
+ status = "disabled";
+ };
+ };
+
+ sci4: sci4@40118400 {
+ compatible = "renesas,ra-sci";
+ interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118400 0x100>;
+ clocks = <&pclka MSTPB 27>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <4>;
+ status = "disabled";
+ };
+ };
+
+ sci5: sci5@40118500 {
+ compatible = "renesas,ra-sci";
+ interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118500 0x100>;
+ clocks = <&pclka MSTPB 26>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <5>;
+ status = "disabled";
+ };
+ };
+
+ sci6: sci6@40118600 {
+ compatible = "renesas,ra-sci";
+ interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118600 0x100>;
+ clocks = <&pclka MSTPB 25>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <6>;
+ status = "disabled";
+ };
+ };
+
+ sci7: sci7@40118700 {
+ compatible = "renesas,ra-sci";
+ interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118700 0x100>;
+ clocks = <&pclka MSTPB 24>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <7>;
+ status = "disabled";
+ };
+ };
+
+ sci8: sci8@40118800 {
+ compatible = "renesas,ra-sci";
+ interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118800 0x100>;
+ clocks = <&pclka MSTPB 23>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <8>;
+ status = "disabled";
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(24)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_3>;
+ mul = <25 0>;
+ status = "disabled";
+ };
+
+ pll2: pll2 {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL2 */
+ source = <RA_PLL_SOURCE_DISABLE>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <0>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ octaspiclk: octaspiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi
new file mode 100644
index 0000000..cf75071
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6m5xh.dtsi>
+
+/ {
+ soc {
+ flash-controller@407e0000 {
+ reg = <0x407e0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0x0 DT_SIZE_M(2)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
new file mode 100644
index 0000000..2097c1f
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ soc {
+ sram0: memory@20000000 {
+ compatible = "mmio-sram";
+ reg = <0x20000000 DT_SIZE_K(512)>;
+ };
+
+ ioport6: gpio@400800c0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400800c0 0x20>;
+ port = <6>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport7: gpio@400800e0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400800e0 0x20>;
+ port = <7>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport8: gpio@40080100 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080100 0x20>;
+ port = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport9: gpio@40080120 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080120 0x20>;
+ port = <9>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioporta: gpio@40080140 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080140 0x20>;
+ port = <10>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioportb: gpio@40080160 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080160 0x20>;
+ port = <11>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ sci1: sci1@40118100 {
+ compatible = "renesas,ra-sci";
+ interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118100 0x100>;
+ clocks = <&pclka MSTPB 30>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <1>;
+ status = "disabled";
+ };
+ };
+
+ sci2: sci2@40118200 {
+ compatible = "renesas,ra-sci";
+ interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118200 0x100>;
+ clocks = <&pclka MSTPB 29>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <2>;
+ status = "disabled";
+ };
+ };
+
+ sci3: sci3@40118300 {
+ compatible = "renesas,ra-sci";
+ interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118300 0x100>;
+ clocks = <&pclka MSTPB 28>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <3>;
+ status = "disabled";
+ };
+ };
+
+ sci4: sci4@40118400 {
+ compatible = "renesas,ra-sci";
+ interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118400 0x100>;
+ clocks = <&pclka MSTPB 27>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <4>;
+ status = "disabled";
+ };
+ };
+
+ sci5: sci5@40118500 {
+ compatible = "renesas,ra-sci";
+ interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118500 0x100>;
+ clocks = <&pclka MSTPB 26>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <5>;
+ status = "disabled";
+ };
+ };
+
+ sci6: sci6@40118600 {
+ compatible = "renesas,ra-sci";
+ interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118600 0x100>;
+ clocks = <&pclka MSTPB 25>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <6>;
+ status = "disabled";
+ };
+ };
+
+ sci7: sci7@40118700 {
+ compatible = "renesas,ra-sci";
+ interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118700 0x100>;
+ clocks = <&pclka MSTPB 24>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <7>;
+ status = "disabled";
+ };
+ };
+
+ sci8: sci8@40118800 {
+ compatible = "renesas,ra-sci";
+ interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118800 0x100>;
+ clocks = <&pclka MSTPB 23>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <8>;
+ status = "disabled";
+ };
+ };
+ };
+
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(24)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_3>;
+ mul = <25 0>;
+ status = "disabled";
+ };
+
+ pll2: pll2 {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL2 */
+ source = <RA_PLL_SOURCE_DISABLE>;
+ div = <RA_PLL_DIV_2>;
+ mul = <20 0>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ status = "okay";
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <0>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ u60clk: u60clk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ octaspiclk: octaspiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ canfdclk: canfdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ cecclk: cecclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
new file mode 100644
index 0000000..2f9a4f0
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <freq.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m33";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mpu: mpu@e000ed90 {
+ compatible = "arm,armv8m-mpu";
+ reg = <0xe000ed90 0x40>;
+ };
+ };
+ };
+
+ soc {
+ interrupt-parent = <&nvic>;
+
+ system: system@4001e000 {
+ compatible = "renesas,ra-system";
+ reg = <0x4001e000 0x1000>;
+ status = "okay";
+ };
+
+ ioport0: gpio@40080000 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080000 0x20>;
+ port = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport1: gpio@40080020 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080020 0x20>;
+ port = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport2: gpio@40080040 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080040 0x20>;
+ port = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport3: gpio@40080060 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080060 0x20>;
+ port = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport4: gpio@40080080 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40080080 0x20>;
+ port = <4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport5: gpio@400800a0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400800a0 0x20>;
+ port = <5>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ pinctrl: pin-contrller@40080800 {
+ compatible = "renesas,ra-pinctrl-pfs";
+ reg = <0x40080800 0x3c0>;
+ status = "okay";
+ };
+
+ sci0: sci0@40118000 {
+ compatible = "renesas,ra-sci";
+ interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118000 0x100>;
+ clocks = <&pclka MSTPB 31>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <0>;
+ status = "disabled";
+ };
+ };
+
+ sci9: sci9@40118900 {
+ compatible = "renesas,ra-sci";
+ interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40118900 0x100>;
+ clocks = <&pclka MSTPB 22>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <9>;
+ status = "disabled";
+ };
+ };
+
+ option_setting_ofs: option_setting_ofs@100a100 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0100a100 0x18>;
+ zephyr,memory-region = "OPTION_SETTING_OFS";
+ status = "okay";
+ };
+
+ option_setting_sas: option_setting_sas@100a134 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0100a134 0xcc>;
+ zephyr,memory-region = "OPTION_SETTING_SAS";
+ status = "okay";
+ };
+
+ option_setting_s: option_setting_s@100a200 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0100a200 0x100>;
+ zephyr,memory-region = "OPTION_SETTING_S";
+ status = "okay";
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi
new file mode 100644
index 0000000..f28cbaa
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <freq.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-m4";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mpu: mpu@e000ed90 {
+ compatible = "arm,armv7m-mpu";
+ reg = <0xe000ed90 0x40>;
+ };
+ };
+ };
+
+ soc {
+
+ system: system@4001e000 {
+ compatible = "renesas,ra-system";
+ reg = <0x4001e000 0x1000>;
+ status = "okay";
+ };
+
+ ioport0: gpio@40040000 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040000 0x20>;
+ port = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport1: gpio@40040020 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040020 0x20>;
+ port = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport2: gpio@40040040 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040040 0x20>;
+ port = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport3: gpio@40040060 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040060 0x20>;
+ port = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport4: gpio@40040080 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x40040080 0x20>;
+ port = <4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport5: gpio@400400a0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400a0 0x20>;
+ port = <5>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport6: gpio@400400c0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400c0 0x20>;
+ port = <6>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ ioport7: gpio@400400e0 {
+ compatible = "renesas,ra-gpio-ioport";
+ reg = <0x400400e0 0x20>;
+ port = <7>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ pinctrl: pin-contrller@40040800 {
+ compatible = "renesas,ra-pinctrl-pfs";
+ reg = <0x40040800 0x3c0>;
+ status = "okay";
+ };
+
+ sci0: sci0@40070000 {
+ compatible = "renesas,ra-sci";
+ interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070000 0x20>;
+ clocks = <&pclka MSTPB 31>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <0>;
+ status = "disabled";
+ };
+ };
+
+ sci1: sci1@40070020 {
+ compatible = "renesas,ra-sci";
+ interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070020 0x20>;
+ clocks = <&pclka MSTPB 30>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <1>;
+ status = "disabled";
+ };
+ };
+
+ sci2: sci2@40070040 {
+ compatible = "renesas,ra-sci";
+ interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070040 0x20>;
+ clocks = <&pclka MSTPB 29>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <2>;
+ status = "disabled";
+ };
+ };
+
+ sci3: sci3@40070060 {
+ compatible = "renesas,ra-sci";
+ interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070060 0x20>;
+ clocks = <&pclka MSTPB 27>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <3>;
+ status = "disabled";
+ };
+ };
+
+ sci4: sci4@40070080 {
+ compatible = "renesas,ra-sci";
+ interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070080 0x20>;
+ clocks = <&pclka MSTPB 26>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <4>;
+ status = "disabled";
+ };
+ };
+
+ sci8: sci8@40070100 {
+ compatible = "renesas,ra-sci";
+ interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070100 0x20>;
+ clocks = <&pclka MSTPB 23>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <8>;
+ status = "disabled";
+ };
+ };
+
+ sci9: sci9@40070120 {
+ compatible = "renesas,ra-sci";
+ interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x40070120 0x20>;
+ clocks = <&pclka MSTPB 22>;
+ status = "disabled";
+ uart {
+ compatible = "renesas,ra-sci-uart";
+ channel = <9>;
+ status = "disabled";
+ };
+ };
+
+ id_code: id_code@100a150 {
+ compatible = "zephyr,memory-region";
+ reg = <0x0100a150 0x10>;
+ zephyr,memory-region = "ID_CODE";
+ status = "okay";
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1bhecbd.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1bhecbd.dtsi
new file mode 100644
index 0000000..6bccb6e
--- /dev/null
+++ b/dts/arm/renesas/ra/ra8/r7fa8d1bhecbd.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/r7fa8d1xh.dtsi>
+
+/ {
+ soc {
+ flash-controller@407fe000 {
+ flash0: flash@2000000 {
+ compatible = "soc-nv-flash";
+ reg = <0x02000000 DT_SIZE_M(2)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
new file mode 100644
index 0000000..ed1b550
--- /dev/null
+++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/ra8x1.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(20)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(48)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <96 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(480)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(480)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(480)>;
+ status = "disabled";
+ };
+
+ pll2: pll2 {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL2 */
+ source = <RA_PLL_SOURCE_DISABLE>;
+ div = <RA_PLL_DIV_2>;
+ mul = <96 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(0)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(0)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(0)>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+ status = "okay";
+
+ cpuclk: cpuclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclke: pclke {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <1>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ sciclk: sciclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ spiclk: spiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ canfdclk: canfdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ i3cclk: i3cclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ u60clk: u60clk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ octaspiclk: octaspiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ lcdclk: lcdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
index 53393b2..21c2468 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
@@ -10,7 +10,7 @@
/ {
clocks: clocks {
xtal: clock-xtal {
- compatible = "renesas,ra8-cgc-external-clock";
+ compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
status = "disabled";
@@ -35,14 +35,14 @@
};
subclk: clock-subclk {
- compatible = "renesas,ra8-cgc-subclk";
+ compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pll: pll {
- compatible = "renesas,ra8-cgc-pll";
+ compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL */
@@ -59,7 +59,7 @@
};
pll2: pll2 {
- compatible = "renesas,ra8-cgc-pll";
+ compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL2 */
@@ -76,65 +76,65 @@
};
pclkblock: pclkblock {
- compatible = "renesas,ra8-cgc-pclk-block";
+ compatible = "renesas,ra-cgc-pclk-block";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
status = "okay";
cpuclk: cpuclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
bclkout: bclkout {
- compatible = "renesas,ra8-cgc-busclk";
+ compatible = "renesas,ra-cgc-busclk";
clk_out_div = <2>;
sdclk = <1>;
#clock-cells = <0>;
@@ -144,56 +144,56 @@
};
fclk: fclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
sciclk: sciclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
spiclk: spiclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
canfdclk: canfdclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
i3cclk: i3cclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uclk: uclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
u60clk: u60clk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
octaspiclk: octaspiclk {
- compatible = "renesas,ra8-cgc-pclk";
+ compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi
new file mode 100644
index 0000000..d593493
--- /dev/null
+++ b/dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/r7fa8t1xh.dtsi>
+
+/ {
+ soc {
+ flash-controller@407fe000 {
+ flash0: flash@2000000 {
+ compatible = "soc-nv-flash";
+ reg = <0x02000000 DT_SIZE_M(2)>;
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
new file mode 100644
index 0000000..59bda1f
--- /dev/null
+++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/ra8x1.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+ clocks: clocks {
+ xtal: clock-xtal {
+ compatible = "renesas,ra-cgc-external-clock";
+ clock-frequency = <DT_FREQ_M(24)>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ hoco: clock-hoco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(48)>;
+ #clock-cells = <0>;
+ };
+
+ moco: clock-moco {
+ compatible = "fixed-clock";
+ clock-frequency = <DT_FREQ_M(8)>;
+ #clock-cells = <0>;
+ };
+
+ loco: clock-loco {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ subclk: clock-subclk {
+ compatible = "renesas,ra-cgc-subclk";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+
+ pll: pll {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL */
+ source = <RA_PLL_SOURCE_MAIN_OSC>;
+ div = <RA_PLL_DIV_2>;
+ mul = <80 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(480)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(480)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(480)>;
+ status = "disabled";
+ };
+
+ pll2: pll2 {
+ compatible = "renesas,ra-cgc-pll";
+ #clock-cells = <0>;
+
+ /* PLL2 */
+ source = <RA_PLL_SOURCE_DISABLE>;
+ div = <RA_PLL_DIV_2>;
+ mul = <96 0>;
+ divp = <RA_PLL_DIV_2>;
+ freqp = <DT_FREQ_M(0)>;
+ divq = <RA_PLL_DIV_2>;
+ freqq = <DT_FREQ_M(0)>;
+ divr = <RA_PLL_DIV_2>;
+ freqr = <DT_FREQ_M(0)>;
+ status = "disabled";
+ };
+
+ pclkblock: pclkblock {
+ compatible = "renesas,ra-cgc-pclk-block";
+ #clock-cells = <0>;
+ sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+ status = "okay";
+
+ cpuclk: cpuclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_1>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ iclk: iclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclka: pclka {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkb: pclkb {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkc: pclkc {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclkd: pclkd {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ pclke: pclke {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_2>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ bclk: bclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_4>;
+ bclkout: bclkout {
+ compatible = "renesas,ra-cgc-busclk";
+ clk_out_div = <2>;
+ sdclk = <1>;
+ #clock-cells = <0>;
+ };
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ fclk: fclk {
+ compatible = "renesas,ra-cgc-pclk";
+ clk_div = <RA_SYS_CLOCK_DIV_8>;
+ #clock-cells = <2>;
+ status = "okay";
+ };
+
+ clkout: clkout {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ sciclk: sciclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ spiclk: spiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ canfdclk: canfdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ i3cclk: i3cclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ uclk: uclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ u60clk: u60clk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ octaspiclk: octaspiclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+
+ lcdclk: lcdclk {
+ compatible = "renesas,ra-cgc-pclk";
+ #clock-cells = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi
index 33aa1a6..925636c 100644
--- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi
+++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi
@@ -7,7 +7,7 @@
#include <mem.h>
#include <arm/armv8.1-m.dtsi>
#include <freq.h>
-#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
/ {
@@ -44,13 +44,13 @@
};
pinctrl: pin-controller@40400800 {
- compatible = "renesas,ra8-pinctrl";
+ compatible = "renesas,ra-pinctrl-pfs";
reg = <0x40400800 0x3c0>;
status = "okay";
};
ioport0: gpio@40400000 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400000 0x20>;
port = <0>;
gpio-controller;
@@ -60,7 +60,7 @@
};
ioport1: gpio@40400020 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400020 0x20>;
port = <1>;
gpio-controller;
@@ -70,7 +70,7 @@
};
ioport2: gpio@40400040 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400040 0x20>;
port = <2>;
gpio-controller;
@@ -80,7 +80,7 @@
};
ioport3: gpio@40400060 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400060 0x20>;
port = <3>;
gpio-controller;
@@ -90,7 +90,7 @@
};
ioport4: gpio@40400080 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400080 0x20>;
port = <4>;
gpio-controller;
@@ -101,7 +101,7 @@
};
ioport5: gpio@404000a0 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x404000a0 0x20>;
port = <5>;
gpio-controller;
@@ -111,7 +111,7 @@
};
ioport6: gpio@404000c0 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x404000c0 0x20>;
port = <6>;
gpio-controller;
@@ -121,7 +121,7 @@
};
ioport7: gpio@404000e0 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x404000e0 0x20>;
port = <7>;
gpio-controller;
@@ -131,7 +131,7 @@
};
ioport8: gpio@40400100 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400100 0x20>;
port = <8>;
gpio-controller;
@@ -141,7 +141,7 @@
};
ioport9: gpio@40400120 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400120 0x20>;
port = <9>;
gpio-controller;
@@ -151,7 +151,7 @@
};
ioporta: gpio@40400140 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400140 0x20>;
port = <10>;
gpio-controller;
@@ -161,7 +161,7 @@
};
ioportb: gpio@40400160 {
- compatible = "renesas,ra8-gpio";
+ compatible = "renesas,ra-gpio-ioport";
reg = <0x40400160 0x20>;
port = <11>;
gpio-controller;
@@ -170,6 +170,23 @@
status = "disabled";
};
+ iic0: iic0@4025e000 {
+ compatible = "renesas,ra-iic";
+ channel = <0>;
+ interrupts = <87 1>, <88 1>, <89 1>, <90 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x4025E000 0x100>;
+ status = "disabled";
+ };
+ iic1: iic1@4025e100 {
+ compatible = "renesas,ra-iic";
+ channel = <1>;
+ interrupts = <91 1>, <92 1>, <93 1>, <94 1>;
+ interrupt-names = "rxi", "txi", "tei", "eri";
+ reg = <0x4025E100 0x100>;
+ status = "disabled";
+ };
+
sci0: sci0@40358000 {
compatible = "renesas,ra-sci";
interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
@@ -260,6 +277,32 @@
#size-cells = <1>;
};
+ adc0: adc@40332000 {
+ compatible = "renesas,ra-adc";
+ interrupts = <38 1>;
+ interrupt-names = "scanend";
+ reg = <0x40332000 0x100>;
+ #io-channel-cells = <1>;
+ vref-mv = <3300>;
+ channels-num = <12>;
+ status = "disabled";
+ };
+
+ adc1: adc@40332200 {
+ compatible = "renesas,ra-adc";
+ interrupts = <39 1>;
+ interrupt-names = "scanend";
+ reg = <0x40332200 0x100>;
+ #io-channel-cells = <1>;
+ vref-mv = <3300>;
+ channels-num = <13>;
+ status = "disabled";
+ };
+
+ trng: trng {
+ compatible = "renesas,ra-rsip-e51a-trng";
+ };
+
option_setting_ofs: option_setting_ofs@300a100 {
compatible = "zephyr,memory-region";
reg = <0x0300a100 0x18>;
diff --git a/dts/arm/st/f4/stm32f429.dtsi b/dts/arm/st/f4/stm32f429.dtsi
index 2bd7dad..e3a21d5 100644
--- a/dts/arm/st/f4/stm32f429.dtsi
+++ b/dts/arm/st/f4/stm32f429.dtsi
@@ -25,6 +25,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+ resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
diff --git a/dts/arm/st/f7/stm32f746.dtsi b/dts/arm/st/f7/stm32f746.dtsi
index 8d8296a..a85bbac 100644
--- a/dts/arm/st/f7/stm32f746.dtsi
+++ b/dts/arm/st/f7/stm32f746.dtsi
@@ -17,6 +17,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+ resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};
diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi
index 5180a2c..6ed8d68 100644
--- a/dts/arm/st/f7/stm32f767.dtsi
+++ b/dts/arm/st/f7/stm32f767.dtsi
@@ -18,6 +18,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+ resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};
diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi
index 05e5969..10e66c2 100644
--- a/dts/arm/st/h7/stm32h723.dtsi
+++ b/dts/arm/st/h7/stm32h723.dtsi
@@ -88,6 +88,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+ resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};
diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi
index ca25961..389e285 100644
--- a/dts/arm/st/h7/stm32h743.dtsi
+++ b/dts/arm/st/h7/stm32h743.dtsi
@@ -49,6 +49,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+ resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};
diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi
index 5cfa418..ce4e01c 100644
--- a/dts/arm/st/h7/stm32h745.dtsi
+++ b/dts/arm/st/h7/stm32h745.dtsi
@@ -42,6 +42,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+ resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};
diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi
index 50d2017..5fcdc46 100644
--- a/dts/arm/st/h7/stm32h750.dtsi
+++ b/dts/arm/st/h7/stm32h750.dtsi
@@ -49,6 +49,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+ resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};
diff --git a/dts/arm/st/h7/stm32h755.dtsi b/dts/arm/st/h7/stm32h755.dtsi
new file mode 100644
index 0000000..8637763
--- /dev/null
+++ b/dts/arm/st/h7/stm32h755.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7_dualcore.dtsi>
+#include <st/h7/stm32h745.dtsi>
+
+/ {
+ soc {
+ compatible = "st,stm32h755", "st,stm32h7", "simple-bus";
+
+ cryp: cryp@48021000 {
+ compatible = "st,stm32-cryp";
+ reg = <0x48021000 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+ interrupts = <79 0>;
+ status = "disabled";
+ };
+
+ hash: cryp@48021400 {
+ compatible = "st,stm32-cryp";
+ reg = <0x48021400 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+ interrupts = <80 0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/arm/st/h7/stm32h755Xi_m4.dtsi b/dts/arm/st/h7/stm32h755Xi_m4.dtsi
new file mode 100644
index 0000000..4d72f69
--- /dev/null
+++ b/dts/arm/st/h7/stm32h755Xi_m4.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h755.dtsi>
+
+/delete-node/ &flash0;
+
+/ {
+ cpus {
+ /delete-node/ cpu@0;
+ };
+
+ soc {
+ flash-controller@52002000 {
+ flash1: flash@8100000 {
+ reg = <0x08100000 DT_SIZE_K(1024)>;
+ };
+ };
+
+ mailbox@58026400 {
+ interrupts = <126 0>;
+ };
+ };
+};
diff --git a/dts/arm/st/h7/stm32h755Xi_m7.dtsi b/dts/arm/st/h7/stm32h755Xi_m7.dtsi
new file mode 100644
index 0000000..47d80cb1
--- /dev/null
+++ b/dts/arm/st/h7/stm32h755Xi_m7.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h755.dtsi>
+
+/delete-node/ &flash1;
+
+/ {
+ cpus {
+ /delete-node/ cpu@1;
+ };
+
+ dtcm: memory@20000000 {
+ compatible = "zephyr,memory-region", "arm,dtcm";
+ reg = <0x20000000 DT_SIZE_K(128)>;
+ zephyr,memory-region = "DTCM";
+ };
+
+ soc {
+ flash-controller@52002000 {
+ flash0: flash@8000000 {
+ reg = <0x08000000 DT_SIZE_K(1024)>;
+ };
+ };
+
+ mailbox@58026400 {
+ interrupts = <125 0>;
+ };
+ };
+};
diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi
index a9a570e..5be690d 100644
--- a/dts/arm/st/h7/stm32h7a3.dtsi
+++ b/dts/arm/st/h7/stm32h7a3.dtsi
@@ -52,6 +52,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+ resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l4r9.dtsi b/dts/arm/st/l4/stm32l4r9.dtsi
index 52d1e8b..20b47a0 100644
--- a/dts/arm/st/l4/stm32l4r9.dtsi
+++ b/dts/arm/st/l4/stm32l4r9.dtsi
@@ -17,7 +17,8 @@
reg = <0x40016800 0x200>;
interrupts = <91 0>, <92 0>;
interrupt-names = "ltdc", "ltdc_er";
- clocks = <&rcc STM32_CLOCK_BUS_APB2 0x40000000>;
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+ resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
index d4f7a7f..c4cf89a 100644
--- a/dts/arm/st/l5/stm32l5.dtsi
+++ b/dts/arm/st/l5/stm32l5.dtsi
@@ -704,6 +704,13 @@
interrupts = <106 0>;
status = "disabled";
};
+
+ fmc: fmc@44020000 {
+ compatible = "st,stm32-fmc";
+ reg = <0x44020000 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+ status = "disabled";
+ };
};
die_temp: dietemp {
diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi
index 97e72c7..4368b9f 100644
--- a/dts/arm/st/mp1/stm32mp157.dtsi
+++ b/dts/arm/st/mp1/stm32mp157.dtsi
@@ -395,6 +395,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>;
+ resets = <&rctl STM32_RESET(APB4, 26U)>;
status = "disabled";
};
};
diff --git a/dts/arm64/intel/intel_socfpga_agilex5.dtsi b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
index b238305..4d0d601 100644
--- a/dts/arm64/intel/intel_socfpga_agilex5.dtsi
+++ b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
@@ -239,4 +239,39 @@
status = "disabled";
};
+ dma0: dma@10DB0000 {
+ compatible = "snps,designware-dma-axi";
+ #dma-cells = <1>;
+ reg = <0x10DB0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>;
+ dma-channels = <4>;
+ resets = <&reset RSTMGR_DMA_RSTLINE>;
+ status = "disabled";
+ };
+
+ dma1: dma@10DC0000 {
+ compatible = "snps,designware-dma-axi";
+ #dma-cells = <1>;
+ reg = <0x10DC0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL
+ IRQ_DEFAULT_PRIORITY>;
+ dma-channels = <4>;
+ resets = <&reset RSTMGR_DMA_RSTLINE>;
+ status = "disabled";
+ };
};
diff --git a/dts/bindings/adc/ambiq,adc.yaml b/dts/bindings/adc/ambiq,adc.yaml
new file mode 100644
index 0000000..034eadf
--- /dev/null
+++ b/dts/bindings/adc/ambiq,adc.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2024 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Ambiq ADC node
+
+compatible: "ambiq,adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+properties:
+ reg:
+ required: true
+
+ interrupts:
+ required: true
+
+ channel-count:
+ type: int
+ required: true
+ description: The maximum channels supported on each unit.
+
+ internal-vref-mv:
+ type: int
+ required: true
+ description: Indicates the reference voltage of the ADC in mV.
+
+io-channel-cells:
+ - input
diff --git a/dts/bindings/adc/nxp,vf610-adc.yaml b/dts/bindings/adc/nxp,vf610-adc.yaml
index fcba99c..78ba552 100644
--- a/dts/bindings/adc/nxp,vf610-adc.yaml
+++ b/dts/bindings/adc/nxp,vf610-adc.yaml
@@ -5,7 +5,7 @@
compatible: "nxp,vf610-adc"
-include: adc-controller.yaml
+include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -30,21 +30,5 @@
"#io-channel-cells":
const: 1
- rdc:
- type: int
- required: true
- description: |
- Set the RDC permission for this peripheral: the RDC controls which
- processor can access to this peripheral. User can select to assign this
- peripheral to the M4 processor, A9 processor or both with R/W or RW
- permissions. To set wanted permission a user should use the helper
- macro RDC_DOMAIN_PERM(domain,permission) where domain must be one of
- M4_DOMAIN_ID or A9_DOMAIN_ID and permission one among
- RDC_DOMAIN_PERM_NONE, RDC_DOMAIN_PERM_W, RDC_DOMAIN_PERM_R,
- RDC_DOMAIN_PERM_RW. Example to allow both processor to read/write to
- this peripheral a user should put:
- rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |
- RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
-
io-channel-cells:
- input
diff --git a/dts/bindings/adc/renesas,ra-adc.yaml b/dts/bindings/adc/renesas,ra-adc.yaml
new file mode 100644
index 0000000..f760a6a
--- /dev/null
+++ b/dts/bindings/adc/renesas,ra-adc.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA ADC node
+
+compatible: "renesas,ra-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+ reg:
+ required: true
+
+ vref-mv:
+ type: int
+ required: true
+ description: ADC reference voltage (Unit:mV)
+
+ channels-num:
+ type: int
+ required: true
+ description: ADC channels number
+
+ "#io-channel-cells":
+ const: 1
+
+io-channel-cells:
+ - input
diff --git a/dts/bindings/arm/nxp,imx-epit.yaml b/dts/bindings/arm/nxp,imx-epit.yaml
index 9c67b17..0f24c71d 100644
--- a/dts/bindings/arm/nxp,imx-epit.yaml
+++ b/dts/bindings/arm/nxp,imx-epit.yaml
@@ -1,11 +1,11 @@
-# Copyright (c) 2018, NXP
+# Copyright 2018, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX Enhanced Periodic Interrupt Timer (EPIT)
compatible: "nxp,imx-epit"
-include: base.yaml
+include: [base.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -18,8 +18,3 @@
type: int
required: true
description: Set the EPIT prescaler between 0 and 4095
-
- rdc:
- type: int
- required: true
- description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/clock/nuvoton,numaker-scc.yaml b/dts/bindings/clock/nuvoton,numaker-scc.yaml
index b2143e6..fbada7b 100644
--- a/dts/bindings/clock/nuvoton,numaker-scc.yaml
+++ b/dts/bindings/clock/nuvoton,numaker-scc.yaml
@@ -29,7 +29,7 @@
- "enable"
- "disable"
- hirc48:
+ hirc48m:
type: string
description: |
Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48)
diff --git a/dts/bindings/clock/renesas,ra-cgc-busclk.yaml b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml
new file mode 100644
index 0000000..949a739
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA External Bus Clock
+
+compatible: "renesas,ra-cgc-busclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+ clk_out_div:
+ type: int
+ enum:
+ - 0
+ - 1
+ - 2
+ description: |
+ Select EBCLK division ratio from BCLK
+ - 0: disable
+ - 1: EBCLK div/1
+ - 2: EBCLK div/2
+
+ sdclk:
+ type: int
+ enum:
+ - 0
+ - 1
+ description: |
+ SDCLK enable or disable
+ - 0: disable
+ - 1: enable
diff --git a/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml
new file mode 100644
index 0000000..3981894
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Clock Generation Circuit external clock configuration
+
+compatible: "renesas,ra-cgc-external-clock"
+
+include: [fixed-clock.yaml, base.yaml]
+
+properties:
+ mosel:
+ type: int
+ default: 0
+ enum:
+ - 0
+ - 1
+ description: |
+ Choose the way for external Clock Oscillator supply
+ 0: Resonator
+ 1: External clock input
diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
new file mode 100644
index 0000000..6380b71
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Clock Control node pclk block
+
+compatible: "renesas,ra-cgc-pclk-block"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+ sysclock-src:
+ required: true
+ type: int
diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
new file mode 100644
index 0000000..cc001c1
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Clock Control Peripheral Clock
+
+compatible: "renesas,ra-cgc-pclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+ clk_src:
+ type: int
+
+ clk_div:
+ type: int
+ required: true
+ description: Prescale divider to calculate the subclock frequency from the
+ system clock frequency.
+
+ "#clock-cells":
+ const: 2
+
+clock-cells:
+ - mstp
+ - stop_bit
diff --git a/dts/bindings/clock/renesas,ra-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml
new file mode 100644
index 0000000..a974f54c
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Clock Generation Circuit PLL Clock
+
+compatible: "renesas,ra-cgc-pll"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+ source:
+ required: true
+ type: int
+ div:
+ required: true
+ type: int
+ mul:
+ required: true
+ type: array
+ divp:
+ type: int
+ freqp:
+ type: int
+ divq:
+ type: int
+ freqq:
+ type: int
+ divr:
+ type: int
+ freqr:
+ type: int
+
+ "#clock-cells":
+ const: 0
diff --git a/dts/bindings/clock/renesas,ra-cgc-subclk.yaml b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml
new file mode 100644
index 0000000..afb98c5
--- /dev/null
+++ b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Sub-Clock
+
+compatible: "renesas,ra-cgc-subclk"
+
+include: fixed-clock.yaml
+
+properties:
+ drive-capability:
+ type: int
+ default: 0
+ enum:
+ - 0
+ - 1
+ - 2
+ - 3
+ description: |
+ Sub-Clock Oscillator Drive Capability Switching
+ - 0: Standard (12.5pf)
+ - 1: Lowpower mode 1 (9pf)
+ - 2: Lowpower mode 2 (7pf)
+ - 3: Lowpower mode 3 (4pf)
+
+ stabilization-time:
+ type: int
+ default: 1000
+ description: |
+ Sub-Clock stabilization time in micro seconds
diff --git a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml b/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml
deleted file mode 100644
index 1d2ae98..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml
+++ /dev/null
@@ -1,31 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 External Bus Clock
-
-compatible: "renesas,ra8-cgc-busclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
- clk_out_div:
- type: int
- enum:
- - 0
- - 1
- - 2
- description: |
- Select EBCLK division ratio from BCLK
- - 0: disable
- - 1: EBCLK div/1
- - 2: EBCLK div/2
-
- sdclk:
- type: int
- enum:
- - 0
- - 1
- description: |
- SDCLK enable or disable
- - 0: disable
- - 1: enable
diff --git a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml b/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml
deleted file mode 100644
index cdbefd9..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 Clock Generation Circuit external clock configuration
-
-compatible: "renesas,ra8-cgc-external-clock"
-
-include: [fixed-clock.yaml, base.yaml]
-
-properties:
- mosel:
- type: int
- default: 0
- enum:
- - 0
- - 1
- description: |
- Choose the way for external Clock Oscillator supply
- 0: Resonator
- 1: External clock input
diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml
deleted file mode 100644
index 9ad2542..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 clock control node pclk block
-
-compatible: "renesas,ra8-cgc-pclk-block"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
- sysclock-src:
- required: true
- type: int
diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml
deleted file mode 100644
index aece92b..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml
+++ /dev/null
@@ -1,25 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 Clock Control Peripheral Clock
-
-compatible: "renesas,ra8-cgc-pclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
- clk_src:
- type: int
-
- clk_div:
- type: int
- required: true
- description: Prescale divider to calculate the subclock frequency from the
- system clock frequency.
-
- "#clock-cells":
- const: 2
-
-clock-cells:
- - mstp
- - stop_bit
diff --git a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml b/dts/bindings/clock/renesas,ra8-cgc-pll.yaml
deleted file mode 100644
index a18f6cf..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 Clock Generation Circuit PLL Clock
-
-compatible: "renesas,ra8-cgc-pll"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
- source:
- required: true
- type: int
- div:
- required: true
- type: int
- mul:
- required: true
- type: array
- divp:
- required: true
- type: int
- freqp:
- required: true
- type: int
- divq:
- type: int
- freqq:
- type: int
- divr:
- type: int
- freqr:
- type: int
-
- "#clock-cells":
- const: 0
diff --git a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml b/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml
deleted file mode 100644
index 7ed083b..0000000
--- a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml
+++ /dev/null
@@ -1,30 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 Sub-Clock
-
-compatible: "renesas,ra8-cgc-subclk"
-
-include: fixed-clock.yaml
-
-properties:
- drive-capability:
- type: int
- default: 0
- enum:
- - 0
- - 1
- - 2
- - 3
- description: |
- Sub-Clock Oscillator Drive Capability Switching
- - 0: Standard (12.5pf)
- - 1: Lowpower mode 1 (9pf)
- - 2: Lowpower mode 2 (7pf)
- - 3: Lowpower mode 3 (4pf)
-
- stabilization-time:
- type: int
- default: 1000
- description: |
- Sub-Clock stabilization time in micro seconds
diff --git a/dts/bindings/counter/nxp,lptmr.yaml b/dts/bindings/counter/nxp,lptmr.yaml
index d44fcb5..bf6252e 100644
--- a/dts/bindings/counter/nxp,lptmr.yaml
+++ b/dts/bindings/counter/nxp,lptmr.yaml
@@ -20,7 +20,13 @@
clk-source:
type: int
required: true
- description: Prescaler clock source (0 to 3)
+ enum: [0, 1, 2, 3]
+ description: |
+ Selects the clock to be used by the LPMTR prescaler/glitch filter.
+ In time counter mode, this field selects the input clock to the prescaler.
+ In pulse counter mode, this field selects the input clock to the glitch filter.
+ The clock connections vary by device, see the device reference manual for
+ more details.
input-pin:
type: int
diff --git a/dts/bindings/cpu/espressif,riscv.yaml b/dts/bindings/cpu/espressif,riscv.yaml
index 374d51c..ba9ec79 100644
--- a/dts/bindings/cpu/espressif,riscv.yaml
+++ b/dts/bindings/cpu/espressif,riscv.yaml
@@ -28,5 +28,6 @@
type: int
description: Value of the external XTAL connected to ESP32. This is typically 40 MHz.
enum:
- - 40000000
+ - 26000000
- 32000000
+ - 40000000
diff --git a/dts/bindings/display/solomon,ssd1327fb.yaml b/dts/bindings/display/solomon,ssd1327fb.yaml
new file mode 100644
index 0000000..c543daf
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1327fb.yaml
@@ -0,0 +1,50 @@
+# Copyright (c) 2024, Savoir-faire Linux
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1327 128x128 dot-matrix display controller on MIPI_DBI bus
+
+include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
+
+compatible: "solomon,ssd1327fb"
+
+properties:
+ oscillator-freq:
+ type: int
+ required: true
+ description: Front clock divider / oscillator frequency
+
+ display-offset:
+ type: int
+ required: true
+ description: Vertical offset by com from 0 ~ 127
+
+ start-line:
+ type: int
+ required: true
+ description: Start line of display RAM to be displayed by selecting a value from 0 to 127
+
+ multiplex-ratio:
+ type: int
+ required: true
+ description: Multiplex ratio from 16MUX to 128MUX
+
+ prechargep:
+ type: int
+ required: true
+ description: Pre-charge period ranging from 0 to 15 DCLK's
+
+ remap-value:
+ type: int
+ required: true
+ description: Remap register
+
+ Has multiple configurations (see each bit setting in the datasheet)
+ - Column Address Remapping (A[0])
+ - Nibble Remapping (A[1])
+ - Address increment mode (A[2])
+ - COM Remapping (A[4])
+ - Splitting of Odd / Even COM Signals (A[6])
+
+ inversion-on:
+ type: boolean
+ description: Turn on display color inverting
diff --git a/dts/bindings/display/st,stm32-ltdc.yaml b/dts/bindings/display/st,stm32-ltdc.yaml
index 5513c81..eee7dc8 100644
--- a/dts/bindings/display/st,stm32-ltdc.yaml
+++ b/dts/bindings/display/st,stm32-ltdc.yaml
@@ -6,7 +6,7 @@
compatible: "st,stm32-ltdc"
-include: [lcd-controller.yaml, pinctrl-device.yaml]
+include: [lcd-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
properties:
disp-on-gpios:
@@ -30,6 +30,9 @@
clocks:
required: true
+ resets:
+ required: true
+
interrupts:
required: true
diff --git a/dts/bindings/dma/snps,designware-dma-axi.yaml b/dts/bindings/dma/snps,designware-dma-axi.yaml
new file mode 100644
index 0000000..baf27c4
--- /dev/null
+++ b/dts/bindings/dma/snps,designware-dma-axi.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2023 Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys Designware axi DMA Controller node
+
+compatible: "snps,designware-dma-axi"
+
+include: [dma-controller.yaml, reset-device.yaml]
+
+properties:
+ reg:
+ required: true
+
+ dma-channels:
+ required: true
+
+ interrupts:
+ required: true
+
+ "#dma-cells":
+ const: 1
+
+# #dma-cells : Must be <1>.
+# The 1st cell specifies the hardware handshaking signal ID
+# Example of device-tree dma channel configuration:
+#
+# &spi0 {
+# /* Configure DMA */
+# dmas = <&dma0 18>, <&dma0 19>;
+# dma-names = "tx", "rx";
+# };
+#
+# In above spi node numbers 18 and 19 represents the
+# peripheral handshaking interface ID
+dma-cells:
+ - slot
diff --git a/dts/bindings/ethernet/nxp,enet1g.yaml b/dts/bindings/ethernet/nxp,enet1g.yaml
index 4c7e99a..f46582d 100644
--- a/dts/bindings/ethernet/nxp,enet1g.yaml
+++ b/dts/bindings/ethernet/nxp,enet1g.yaml
@@ -5,7 +5,7 @@
compatible: "nxp,enet1g"
-include: ["base.yaml"]
+include: ["base.yaml", "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -13,7 +13,3 @@
clocks:
required: true
-
- rdc:
- type: int
- description: Set the RDC(Resource Domain Controller) domain permission for this peripheral
diff --git a/dts/bindings/firmware/arm,scmi-clock.yaml b/dts/bindings/firmware/arm,scmi-clock.yaml
new file mode 100644
index 0000000..5f0aa16
--- /dev/null
+++ b/dts/bindings/firmware/arm,scmi-clock.yaml
@@ -0,0 +1,27 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Control and Management Interface (SCMI) clock protocol
+
+compatible: "arm,scmi-clock"
+
+include: [base.yaml, clock-controller.yaml]
+
+properties:
+ shmem:
+ type: phandles
+
+ reg:
+ required: true
+ const: [0x14]
+
+ "#clock-cells":
+ required: true
+ const: 1
+ description: |
+ Vendor-specific clock identifier. Needs to match identifier
+ expected by the SCMI platform as this is directly used in SCMI
+ clock management messages.
+
+clock-cells:
+ - name
diff --git a/dts/bindings/firmware/arm,scmi-pinctrl.yaml b/dts/bindings/firmware/arm,scmi-pinctrl.yaml
new file mode 100644
index 0000000..f1e52b0
--- /dev/null
+++ b/dts/bindings/firmware/arm,scmi-pinctrl.yaml
@@ -0,0 +1,20 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Control and Management Interface (SCMI) pinctrl protocol
+
+compatible: "arm,scmi-pinctrl"
+
+include: base.yaml
+
+properties:
+ reg:
+ required: true
+ const: [0x19]
+
+child-binding:
+ description: SCMI pin protocol pin group
+ properties:
+ pinmux:
+ required: true
+ type: array
diff --git a/dts/bindings/firmware/arm,scmi-shmem.yaml b/dts/bindings/firmware/arm,scmi-shmem.yaml
new file mode 100644
index 0000000..aa968a3
--- /dev/null
+++ b/dts/bindings/firmware/arm,scmi-shmem.yaml
@@ -0,0 +1,12 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Control and Management Interface (SCMI) shared memory (SHMEM)
+
+compatible: "arm,scmi-shmem"
+
+include: [base.yaml]
+
+properties:
+ reg:
+ required: true
diff --git a/dts/bindings/firmware/arm,scmi.yaml b/dts/bindings/firmware/arm,scmi.yaml
new file mode 100644
index 0000000..5ece8e5
--- /dev/null
+++ b/dts/bindings/firmware/arm,scmi.yaml
@@ -0,0 +1,68 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ System Control and Management Interface (SCMI) with doorbell
+ and shared memory (SHMEM) transport.
+
+ Devicetree example:
+ #include <mem.h>
+
+ scmi_res0: memory@44611000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x44611000 0x80>;
+ };
+
+ mu5: mailbox@44610000 {
+ compatible = "nxp,mbox-imx-mu";
+ reg = <0x44610000 DT_SIZE_K(4)>;
+ interrupts = <205 0>;
+ #mbox-cells = <1>;
+ };
+
+ scmi {
+ compatible = "arm,scmi";
+ shmem = <&scmi_res0>;
+ mboxes = <&mu5 0>;
+ mbox-names = "tx";
+
+ protocol@14 {
+ compatible = "arm,scmi-clock";
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ protocol@19 {
+ compatible = "arm,scmi-pinctrl";
+ reg = <0x19>;
+
+ pinctrl {
+ compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl";
+ };
+ };
+ };
+
+compatible: "arm,scmi"
+
+include: [base.yaml]
+
+properties:
+ shmem:
+ type: phandle
+ required: true
+ description: |
+ Phandle to node describing TX channel shared memory area.
+ This translates to a **single** SCMI transmit channel.
+
+ mboxes:
+ required: true
+ description: |
+ List of mailbox channel specifiers. It should contain one or two specifiers:
+ 1) tx - 1 mbox / 1 shmem (platform and agent use the same
+ mailbox channel for signaling)
+ 2) tx_reply - 2 mbox / 1 shmem (platform and agent use different
+ mailbox channels for signaling)
+
+ mbox-names:
+ required: true
+ description: mailbox channel specifier names
diff --git a/dts/bindings/gpio/nxp,imx-gpio.yaml b/dts/bindings/gpio/nxp,imx-gpio.yaml
index 6662e63..d13db06 100644
--- a/dts/bindings/gpio/nxp,imx-gpio.yaml
+++ b/dts/bindings/gpio/nxp,imx-gpio.yaml
@@ -1,20 +1,16 @@
-# Copyright (c) 2017, NXP
+# Copyright 2017, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX GPIO node
compatible: "nxp,imx-gpio"
-include: [gpio-controller.yaml, base.yaml]
+include: [gpio-controller.yaml, base.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
required: true
- rdc:
- type: int
- description: Set the RDC permission for this peripheral
-
pinmux:
type: phandles
description: |
diff --git a/dts/bindings/gpio/nxp,imx-rgpio.yaml b/dts/bindings/gpio/nxp,imx-rgpio.yaml
index eaa4e08..14aef8a 100644
--- a/dts/bindings/gpio/nxp,imx-rgpio.yaml
+++ b/dts/bindings/gpio/nxp,imx-rgpio.yaml
@@ -1,20 +1,16 @@
-# Copyright 2024, NXP
+# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX RGPIO node
compatible: "nxp,imx-rgpio"
-include: [gpio-controller.yaml, base.yaml]
+include: [gpio-controller.yaml, base.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
required: true
- rdc:
- type: int
- description: Set the RDC permission for this peripheral
-
pinmux:
type: phandles
description: |
diff --git a/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
new file mode 100644
index 0000000..bdf5305
--- /dev/null
+++ b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA GPIO IO port
+
+compatible: "renesas,ra-gpio-ioport"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+ reg:
+ required: true
+
+ port:
+ type: int
+ required: true
+
+ vbatts_pins:
+ type: array
+ description: Array of vbatt pin on port
+
+ "#gpio-cells":
+ const: 2
+
+gpio-cells:
+ - pin
+ - flags
diff --git a/dts/bindings/gpio/renesas,ra8-gpio.yaml b/dts/bindings/gpio/renesas,ra8-gpio.yaml
deleted file mode 100644
index 9f6df08..0000000
--- a/dts/bindings/gpio/renesas,ra8-gpio.yaml
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA8 GPIO
-
-compatible: "renesas,ra8-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
- reg:
- required: true
-
- port:
- type: int
- required: true
-
- vbatts_pins:
- type: array
- description: Array of vbatt pin on port
-
- "#gpio-cells":
- const: 2
-
-gpio-cells:
- - pin
- - flags
diff --git a/dts/bindings/haptics/ti,drv2605.yaml b/dts/bindings/haptics/ti,drv2605.yaml
index 0b71cc0..484267c 100644
--- a/dts/bindings/haptics/ti,drv2605.yaml
+++ b/dts/bindings/haptics/ti,drv2605.yaml
@@ -11,6 +11,7 @@
properties:
actuator-mode:
+ required: true
type: string
enum:
- "ERM"
@@ -26,6 +27,11 @@
- "8X"
- "16X"
- "DISABLED"
+ default: "3X"
+ description: |
+ Selects the feedback gain ratio between braking gain and driving gain.
+ According to the datasheet, a value of 2 ("3X") is valid for most
+ actuators.
loop-gain:
type: string
enum:
@@ -33,3 +39,25 @@
- "MEDIUM"
- "HIGH"
- "VERY_HIGH"
+ default: "HIGH"
+ description: |
+ Selects a loop gain for the feedback control. According to the datasheet,
+ a value of 2 ("HIGH") is valid for most actuators.
+ vib-rated-mv:
+ type: int
+ default: 3200
+ description: |
+ Sets the reference voltage for full-scale output during closed-loop
+ operation. The default value is inherited from ti,drv260x.yaml in Linux.
+ vib-overdrive-mv:
+ type: int
+ default: 3200
+ description: |
+ Sets a clamp so that the automatic overdrive is bounded. The default
+ value is inherited from ti,drv260x.yaml in Linux.
+ en-gpios:
+ type: phandle-array
+ description: GPIO to enable and disable the device.
+ in-trig-gpios:
+ type: phandle-array
+ description: GPIO to trigger ROM waveforms or drive an input signal.
diff --git a/dts/bindings/i2c/fsl,imx21-i2c.yaml b/dts/bindings/i2c/fsl,imx21-i2c.yaml
index 8c9238d..7a8fcaa 100644
--- a/dts/bindings/i2c/fsl,imx21-i2c.yaml
+++ b/dts/bindings/i2c/fsl,imx21-i2c.yaml
@@ -5,7 +5,7 @@
compatible: "fsl,imx21-i2c"
-include: [i2c-controller.yaml, pinctrl-device.yaml]
+include: [i2c-controller.yaml, pinctrl-device.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -13,8 +13,3 @@
interrupts:
required: true
-
- rdc:
- type: int
- required: true
- description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/i2c/renesas,ra-iic.yaml b/dts/bindings/i2c/renesas,ra-iic.yaml
new file mode 100644
index 0000000..298ab0e
--- /dev/null
+++ b/dts/bindings/i2c/renesas,ra-iic.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA I2C Master controller
+
+compatible: "renesas,ra-iic"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+ reg:
+ required: true
+
+ channel:
+ required: true
+ type: int
+
+ interrupts:
+ required: true
+
+ rise-time-ns:
+ type: int
+ default: 120
+
+ fall-time-ns:
+ type: int
+ default: 120
+
+ duty-cycle-percent:
+ type: int
+ default: 50
+
+ interrupt-priority-level:
+ type: int
+ default: 12
diff --git a/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml
index 3352e29..2d5c57a 100644
--- a/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml
+++ b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml
@@ -10,3 +10,23 @@
properties:
reg:
required: true
+ target-buffered-mode:
+ type: boolean
+ description: |
+ This option is used when the I2C target is enabled and it can support
+ buffered mode for I2C target transfer. When 'false', the target will use
+ PIO (Programmed I/O) mode.
+ forwards:
+ type: phandle-array
+ description: |
+ When added, read/write requests sent to this bus for a given address will
+ be forwarded to the specified phandle (must be another i2c bus). As an
+ example, if we wanted to forward any requests from i2c0@0x20 to i2c1, we
+ would use:
+
+ &i2c0 {
+ forward = <&i2c1 0x20>;
+ };
+
+forward-cells:
+ - addr
diff --git a/dts/bindings/input/zephyr,input-double-tap.yaml b/dts/bindings/input/zephyr,input-double-tap.yaml
new file mode 100644
index 0000000..18d297f
--- /dev/null
+++ b/dts/bindings/input/zephyr,input-double-tap.yaml
@@ -0,0 +1,48 @@
+# Copyright 2024 Kelly Helmut Lord
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ Input double tap pseudo-device
+
+ Listens for key events as an input and produces key events as output
+ corresponding to double taps.
+
+ Can be optionally be associated to a specific device to listen for events
+ only from that device.
+
+ Example configuration:
+
+ #include <zephyr/dt-bindings/input/input-event-codes.h>
+
+ double_tap {
+ input = <&buttons>;
+ compatible = "zephyr,input-double-tap";
+ input-codes = <INPUT_KEY_0>, <INPUT_KEY_1>;
+ double-tap-codes = <INPUT_KEY_A>, <INPUT_KEY_B>;
+ double-tap-delay-ms = <300>;
+ };
+
+compatible: "zephyr,input-double-tap"
+
+properties:
+ input:
+ type: phandle
+ description: |
+ Input device phandle, if not specified listen for input from all devices.
+
+ input-codes:
+ type: array
+ required: true
+ description: |
+ Array of input event key codes (INPUT_KEY_* or INPUT_BTN_*).
+
+ double-tap-codes:
+ type: array
+ required: true
+ description: |
+ Array of key codes to be generated for double taps (INPUT_KEY_* or INPUT_BTN_*).
+
+ double-tap-delay-ms:
+ type: int
+ required: true
+ description: Maximum time delay between taps to register a double tap, in milliseconds.
diff --git a/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
index f8c651e..acebbca 100644
--- a/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
+++ b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
@@ -10,5 +10,10 @@
reg:
required: true
+ "#interrupt-cells":
+ const: 3
+
interrupt-cells:
- irq
+ - priority
+ - flags
diff --git a/dts/bindings/ipm/nxp,imx-mu.yaml b/dts/bindings/ipm/nxp,imx-mu.yaml
index 3988be6..8e16087 100644
--- a/dts/bindings/ipm/nxp,imx-mu.yaml
+++ b/dts/bindings/ipm/nxp,imx-mu.yaml
@@ -1,11 +1,11 @@
-# Copyright (c) 2018, NXP
+# Copyright 2018, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX Messaging Unit
compatible: "nxp,imx-mu"
-include: base.yaml
+include: [base.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -13,8 +13,3 @@
interrupts:
required: true
-
- rdc:
- type: int
- required: true
- description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/mipi-dbi/st,mipi-dbi-fmc.yaml b/dts/bindings/mipi-dbi/st,mipi-dbi-fmc.yaml
new file mode 100644
index 0000000..06e2718
--- /dev/null
+++ b/dts/bindings/mipi-dbi/st,mipi-dbi-fmc.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Bootlin
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 FMC display controller
+compatible: "st,stm32-fmc-mipi-dbi"
+
+include: ["mipi-dbi-controller.yaml"]
+
+properties:
+ reset-gpios:
+ type: phandle-array
+ description: |
+ Reset GPIO pin. Set high to reset the display
+
+ power-gpios:
+ type: phandle-array
+ description: |
+ Power GPIO pin. Set high to power the display.
+
+ register-select-pin:
+ type: int
+ required: true
+ description: |
+ Address pin used as Register Select for the display controller.
diff --git a/dts/bindings/misc/nxp,rdc-policy.yaml b/dts/bindings/misc/nxp,rdc-policy.yaml
new file mode 100644
index 0000000..2a8bd1e
--- /dev/null
+++ b/dts/bindings/misc/nxp,rdc-policy.yaml
@@ -0,0 +1,16 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+ rdc:
+ type: int
+ description: |
+ Set the RDC permission for specified peripheral: Resource Domain Controller (RDC)
+ supports flexible configuration on IP’s access permission, each individual IP can,
+ for example, be configured as A-core only or M-core only. This property uses some
+ macros defined in 'include/zephyr/dt-bindings/rdc/imx_rdc.h' to configure current
+ peripheral's access permission.
+ For example to allow both A53 and M7 Core to have read/write permission to current
+ peripheral:
+ rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
+ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
diff --git a/dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml b/dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml
new file mode 100644
index 0000000..2cbd6a6
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,ra-pincrl-pfs.yaml
@@ -0,0 +1,108 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ The Renesas RA pin controller is a node responsible for controlling
+ pin function selection and pin properties, such as routing a SCI0 RXD
+ to P610.
+
+ The node has the 'pinctrl' node label set in your SoC's devicetree,
+ so you can modify it like this:
+
+ &pinctrl {
+ /* your modifications go here */
+ };
+
+ All device pin configurations should be placed in child nodes of the
+ 'pinctrl' node, as shown in this example:
+
+ /* You can put this in places like a board-pinctrl.dtsi file in
+ * your board directory, or a devicetree overlay in your application.
+ */
+
+ /* include pre-defined combinations for the SoC variant used by the board */
+ #include <dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+
+ &pinctrl {
+ /* configuration for the sci0 "default" state */
+ sci0_default: sci0_default {
+ group1 {
+ /* tx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
+ drive-strength = "medium";
+ };
+ group2 {
+ /* rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
+ };
+ };
+ };
+
+ The 'sci0_default' child node encodes the pin configurations for a
+ particular state of a device; in this case, the default (that is, active)
+ state.
+
+ As shown, pin configurations are organized in groups within each child node.
+ Each group can specify a list of pin function selections in the 'psels'
+ property.
+
+ A group can also specify shared pin properties common to all the specified
+ pins, such as the 'input-enable' property in group 2. Here is a list of
+ supported standard pin properties:
+
+ - bias-disable: Disable pull-up/down (default, not required).
+ - bias-pull-up: Enable pull-up resistor.
+ - input-enable: Enable input from the pin.
+ - drive-strength: Set the drive strength of the pin. Possible
+ values are: low, medium, highspeed-high, high.
+
+ To link pin configurations with a device, use a pinctrl-N property for some
+ number N, like this example you could place in your board's DTS file:
+
+ #include "board-pinctrl.dtsi"
+
+ &sci0 {
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-1 = <&uart0_sleep>;
+ pinctrl-names = "default", "sleep";
+ };
+
+compatible: "renesas,ra-pinctrl-pfs"
+
+include: base.yaml
+
+child-binding:
+ description: |
+ Definitions for a pinctrl state.
+ child-binding:
+
+ include:
+ - name: pincfg-node.yaml
+ property-allowlist:
+ - bias-disable
+ - bias-pull-up
+ - input-enable
+ - drive-open-drain
+
+ properties:
+ psels:
+ required: true
+ type: array
+ description: |
+ An array of pins sharing the same group properties. Each
+ element of the array is an integer constructed from the
+ pin number and the alternative function of the pin.
+ drive-strength:
+ type: string
+ enum:
+ - "low"
+ - "medium"
+ - "highspeed-high"
+ - "high"
+ default: "low"
+ description: |
+ The drive strength of a pin. The default value is low, as this
+ is the power on reset value.
+ renesas,analog-enable:
+ type: boolean
+ description: enable analog input
diff --git a/dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml b/dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml
deleted file mode 100644
index e4240db..0000000
--- a/dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml
+++ /dev/null
@@ -1,105 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
- The Renesas RA pin controller is a node responsible for controlling
- pin function selection and pin properties, such as routing a SCI0 RXD
- to P610.
-
- The node has the 'pinctrl' node label set in your SoC's devicetree,
- so you can modify it like this:
-
- &pinctrl {
- /* your modifications go here */
- };
-
- All device pin configurations should be placed in child nodes of the
- 'pinctrl' node, as shown in this example:
-
- /* You can put this in places like a board-pinctrl.dtsi file in
- * your board directory, or a devicetree overlay in your application.
- */
-
- /* include pre-defined combinations for the SoC variant used by the board */
- #include <dt-bindings/pinctrl/renesas/ra-pinctrl.h>
-
- &pinctrl {
- /* configuration for the sci0 "default" state */
- sci0_default: sci0_default {
- group1 {
- /* tx */
- psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
- drive-strength = "medium";
- };
- group2 {
- /* rx */
- psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
- };
- };
- };
-
- The 'sci0_default' child node encodes the pin configurations for a
- particular state of a device; in this case, the default (that is, active)
- state.
-
- As shown, pin configurations are organized in groups within each child node.
- Each group can specify a list of pin function selections in the 'psels'
- property.
-
- A group can also specify shared pin properties common to all the specified
- pins, such as the 'input-enable' property in group 2. Here is a list of
- supported standard pin properties:
-
- - bias-disable: Disable pull-up/down (default, not required).
- - bias-pull-up: Enable pull-up resistor.
- - input-enable: Enable input from the pin.
- - drive-strength: Set the drive strength of the pin. Possible
- values are: low, medium, highspeed-high, high.
-
- To link pin configurations with a device, use a pinctrl-N property for some
- number N, like this example you could place in your board's DTS file:
-
- #include "board-pinctrl.dtsi"
-
- &sci0 {
- pinctrl-0 = <&uart0_default>;
- pinctrl-1 = <&uart0_sleep>;
- pinctrl-names = "default", "sleep";
- };
-
-compatible: "renesas,ra8-pinctrl"
-
-include: base.yaml
-
-child-binding:
- description: |
- Definitions for a pinctrl state.
- child-binding:
-
- include:
- - name: pincfg-node.yaml
- property-allowlist:
- - bias-disable
- - bias-pull-up
- - input-enable
- - drive-open-drain
-
- properties:
- psels:
- required: true
- type: array
- description: |
- An array of pins sharing the same group properties. Each
- element of the array is an integer constructed from the
- pin number and the alternative function of the pin.
- drive-strength:
- type: string
- enum:
- - "low"
- - "medium"
- - "highspeed-high"
- - "high"
- default: "low"
- description: |
- The drive strength of a pin. The default value is low, as this
- is the power on reset value.
diff --git a/dts/bindings/power/nxp,aon-wakeup-pin.yaml b/dts/bindings/power/nxp,aon-wakeup-pin.yaml
new file mode 100644
index 0000000..1eec851
--- /dev/null
+++ b/dts/bindings/power/nxp,aon-wakeup-pin.yaml
@@ -0,0 +1,24 @@
+# Copyright 2024, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Some NXP SoC's have pins dedicated to generate a wakeup interrupt.
+
+compatible: "nxp,aon-wakeup-pin"
+
+include: base.yaml
+
+properties:
+ interrupts:
+ type: array
+ required: true
+ description: Interrupt to wakeup the SoC from low power modes.
+
+ wakeup-level:
+ type: string
+ enum:
+ - "low"
+ - "high"
+ default: "high"
+ description: |
+ Wakeup level on the pin, default is wakeup on high level
+ which is the reset value.
diff --git a/dts/bindings/pwm/fsl,imx27-pwm.yaml b/dts/bindings/pwm/fsl,imx27-pwm.yaml
index 10bf3e9..edb5e9d 100644
--- a/dts/bindings/pwm/fsl,imx27-pwm.yaml
+++ b/dts/bindings/pwm/fsl,imx27-pwm.yaml
@@ -10,7 +10,7 @@
compatible: "fsl,imx27-pwm"
-include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
+include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -24,11 +24,6 @@
required: true
description: Set the PWM prescale between 0 and 4096
- rdc:
- type: int
- required: true
- description: Set the RDC permission for this peripheral
-
"#pwm-cells":
const: 2
diff --git a/dts/bindings/rng/renesas,ra-rsip-e51a-trng.yaml b/dts/bindings/rng/renesas,ra-rsip-e51a-trng.yaml
new file mode 100644
index 0000000..461ded7
--- /dev/null
+++ b/dts/bindings/rng/renesas,ra-rsip-e51a-trng.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA RSIP-E51A TRNG
+
+compatible: "renesas,ra-rsip-e51a-trng"
+
+include: base.yaml
diff --git a/dts/bindings/sdhc/nxp,imx-usdhc.yaml b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
index 3b8df7d..bccdf51 100644
--- a/dts/bindings/sdhc/nxp,imx-usdhc.yaml
+++ b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
@@ -66,3 +66,10 @@
Enable the host to detect an SD card via the DAT3 line of the SD card
connection. Requires the board to define a function to pull DAT3 low or
high using pullup/pulldown resistors.
+
+ detect-cd:
+ type: boolean
+ description: |
+ Use the host's internal card detect signal (USDHC_CD) to detect the SD
+ card. This signal is available as an alternative to card detect via GPIO,
+ and should be connected to the SD slot's detect pin if used.
diff --git a/dts/bindings/sensor/invensense,icm42670-i2c.yaml b/dts/bindings/sensor/invensense,icm42670-i2c.yaml
new file mode 100644
index 0000000..37311b4
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42670-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42670 motion tracking device
+
+compatible: "invensense,icm42670"
+
+include: [i2c-device.yaml, "invensense,icm42670.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm42670-spi.yaml b/dts/bindings/sensor/invensense,icm42670-spi.yaml
new file mode 100644
index 0000000..069a78e
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42670-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2022 Esco Medical ApS
+# Copyright (c) 2020 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42670 motion tracking device
+
+compatible: "invensense,icm42670"
+
+include: [spi-device.yaml, "invensense,icm42670.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm42670.yaml b/dts/bindings/sensor/invensense,icm42670.yaml
index 1f2ddeb..39fb582 100644
--- a/dts/bindings/sensor/invensense,icm42670.yaml
+++ b/dts/bindings/sensor/invensense,icm42670.yaml
@@ -4,9 +4,7 @@
description: ICM-42670 motion tracking device
-compatible: "invensense,icm42670"
-
-include: [sensor-device.yaml, spi-device.yaml]
+include: [sensor-device.yaml]
properties:
int-gpios:
diff --git a/dts/bindings/sensor/invensense,icm42688.yaml b/dts/bindings/sensor/invensense,icm42688.yaml
index 29c70fb..c3c628e 100644
--- a/dts/bindings/sensor/invensense,icm42688.yaml
+++ b/dts/bindings/sensor/invensense,icm42688.yaml
@@ -74,10 +74,10 @@
Specify the accelerometer range in g.
Default is power-up configuration.
enum:
- - 0 # ICM42688_DT_ACCEL_FS_16G
- - 1 # ICM42688_DT_ACCEL_FS_8G
- - 2 # ICM42688_DT_ACCEL_FS_4G
- - 3 # ICM42688_DT_ACCEL_FS_2G
+ - 0 # ICM42688_DT_ACCEL_FS_16
+ - 1 # ICM42688_DT_ACCEL_FS_8
+ - 2 # ICM42688_DT_ACCEL_FS_4
+ - 3 # ICM42688_DT_ACCEL_FS_2
gyro-pwr-mode:
type: int
diff --git a/dts/bindings/sensor/nxp,fxls8974-common.yaml b/dts/bindings/sensor/nxp,fxls8974-common.yaml
new file mode 100644
index 0000000..0c60be2
--- /dev/null
+++ b/dts/bindings/sensor/nxp,fxls8974-common.yaml
@@ -0,0 +1,43 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXLS8974 3-axis accelerometer sensor
+
+include: sensor-device.yaml
+
+properties:
+ reset-gpios:
+ type: phandle-array
+ description: |
+ RST pin
+ This pin defaults to active high when consumed by the sensor.
+ The property value should ensure the flags properly describe
+ the signal that is presented to the driver.
+
+ int1-gpios:
+ type: phandle-array
+ description: |
+ INT1 pin
+ This pin defaults to active low when produced by the sensor.
+ The property value should ensure the flags properly describe
+ the signal that is presented to the driver.
+
+ int2-gpios:
+ type: phandle-array
+ description: |
+ INT2 pin
+ This pin defaults to active low when produced by the sensor.
+ The property value should ensure the flags properly describe
+ the signal that is presented to the driver.
+
+ range:
+ type: int
+ default: 2
+ description: |
+ Range in g. Default value is 2 because it is the most sensitive setting.
+ 16g (7.81 mg/LSB), 8g (3.91 mg/LSB), 4g (1.95 mg/LSB), 2g (0.98 mg/LSB).
+ enum:
+ - 16
+ - 8
+ - 4
+ - 2
diff --git a/dts/bindings/sensor/nxp,fxls8974-i2c.yaml b/dts/bindings/sensor/nxp,fxls8974-i2c.yaml
new file mode 100644
index 0000000..f1b410f
--- /dev/null
+++ b/dts/bindings/sensor/nxp,fxls8974-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXLS8974 3-axis accelerometer sensor
+
+compatible: "nxp,fxls8974"
+
+include: ["i2c-device.yaml", "nxp,fxls8974-common.yaml"]
diff --git a/dts/bindings/sensor/nxp,fxls8974-spi.yaml b/dts/bindings/sensor/nxp,fxls8974-spi.yaml
new file mode 100644
index 0000000..976c5c2
--- /dev/null
+++ b/dts/bindings/sensor/nxp,fxls8974-spi.yaml
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXLS8974 3-axis accelerometer sensor
+
+compatible: "nxp,fxls8974"
+
+include: ["spi-device.yaml", "nxp,fxls8974-common.yaml"]
diff --git a/dts/bindings/serial/nxp,imx-iuart.yaml b/dts/bindings/serial/nxp,imx-iuart.yaml
index d5c6996..b0bcd60 100644
--- a/dts/bindings/serial/nxp,imx-iuart.yaml
+++ b/dts/bindings/serial/nxp,imx-iuart.yaml
@@ -3,7 +3,7 @@
compatible: "nxp,imx-iuart"
-include: [uart-controller.yaml, pinctrl-device.yaml]
+include: [uart-controller.yaml, pinctrl-device.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -17,7 +17,3 @@
pinctrl-names:
required: true
-
- rdc:
- type: int
- description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/serial/nxp,imx-uart.yaml b/dts/bindings/serial/nxp,imx-uart.yaml
index 7e19df0..b36344f 100644
--- a/dts/bindings/serial/nxp,imx-uart.yaml
+++ b/dts/bindings/serial/nxp,imx-uart.yaml
@@ -1,11 +1,11 @@
-# Copyright (c) 2017, NXP
+# Copyright 2017, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: iMX UART
compatible: "nxp,imx-uart"
-include: [uart-controller.yaml, pinctrl-device.yaml]
+include: [uart-controller.yaml, pinctrl-device.yaml, "nxp,rdc-policy.yaml"]
properties:
reg:
@@ -19,11 +19,6 @@
required: true
description: Set the UART Port to modem mode 0 (dce) 64 (dte)
- rdc:
- type: int
- required: true
- description: Set the RDC permission for this peripheral
-
pinctrl-0:
required: true
diff --git a/dts/bindings/serial/renesas,ra-sci-uart.yaml b/dts/bindings/serial/renesas,ra-sci-uart.yaml
new file mode 100644
index 0000000..55faae5
--- /dev/null
+++ b/dts/bindings/serial/renesas,ra-sci-uart.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA SCI UART controller
+
+compatible: "renesas,ra-sci-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+ channel:
+ type: int
+ required: true
diff --git a/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml b/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml
index 80717d8..68490c4 100644
--- a/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml
+++ b/dts/bindings/serial/renesas,ra8-uart-sci-b.yaml
@@ -11,11 +11,3 @@
channel:
type: int
required: true
-
- tx-dtc:
- type: boolean
- description: Enable dtc support for transmit
-
- rx-dtc:
- type: boolean
- description: Enable dtc support for receive
diff --git a/dts/bindings/timer/arm,armv6m-systick.yaml b/dts/bindings/timer/arm,armv6m-systick.yaml
index 607d1d4..1615f23 100644
--- a/dts/bindings/timer/arm,armv6m-systick.yaml
+++ b/dts/bindings/timer/arm,armv6m-systick.yaml
@@ -5,8 +5,4 @@
compatible: "arm,armv6m-systick"
-include: base.yaml
-
-properties:
- reg:
- required: true
+include: [cortex-m-systick.yaml]
diff --git a/dts/bindings/timer/arm,armv7m-systick.yaml b/dts/bindings/timer/arm,armv7m-systick.yaml
index ae9bc5a..213ca23 100644
--- a/dts/bindings/timer/arm,armv7m-systick.yaml
+++ b/dts/bindings/timer/arm,armv7m-systick.yaml
@@ -5,8 +5,4 @@
compatible: "arm,armv7m-systick"
-include: base.yaml
-
-properties:
- reg:
- required: true
+include: [cortex-m-systick.yaml]
diff --git a/dts/bindings/timer/arm,armv8.1m-systick.yaml b/dts/bindings/timer/arm,armv8.1m-systick.yaml
index a161623..a7e0f01 100644
--- a/dts/bindings/timer/arm,armv8.1m-systick.yaml
+++ b/dts/bindings/timer/arm,armv8.1m-systick.yaml
@@ -5,8 +5,4 @@
compatible: "arm,armv8.1m-systick"
-include: base.yaml
-
-properties:
- reg:
- required: true
+include: [cortex-m-systick.yaml]
diff --git a/dts/bindings/timer/arm,armv8m-systick.yaml b/dts/bindings/timer/arm,armv8m-systick.yaml
index 50215a8..fe1407b 100644
--- a/dts/bindings/timer/arm,armv8m-systick.yaml
+++ b/dts/bindings/timer/arm,armv8m-systick.yaml
@@ -5,8 +5,4 @@
compatible: "arm,armv8m-systick"
-include: base.yaml
-
-properties:
- reg:
- required: true
+include: [cortex-m-systick.yaml]
diff --git a/dts/bindings/timer/cortex-m-systick.yaml b/dts/bindings/timer/cortex-m-systick.yaml
new file mode 100644
index 0000000..325bd26
--- /dev/null
+++ b/dts/bindings/timer/cortex-m-systick.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 MUNIC SA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for SysTick of ARM Cortex-M chips
+include: base.yaml
+
+properties:
+ reg:
+ required: true
diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt
index 27edef9..b243c8e 100644
--- a/dts/bindings/vendor-prefixes.txt
+++ b/dts/bindings/vendor-prefixes.txt
@@ -732,6 +732,7 @@
winsen Zhengzhou Winsen Electronics Technology Co., Ltd.
winstar Winstar Display Corp.
wits Shenzhen Merrii Technology Co., Ltd. (WITS)
+witte Witte Technology
wiznet WIZnet Co., Ltd.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.
diff --git a/dts/bindings/watchdog/litex,watchdog.yaml b/dts/bindings/watchdog/litex,watchdog.yaml
new file mode 100644
index 0000000..8ad78cb
--- /dev/null
+++ b/dts/bindings/watchdog/litex,watchdog.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX watchdog.
+
+compatible: "litex,watchdog"
+
+include: base.yaml
+
+properties:
+ reg:
+ required: true
+
+ interrupts:
+ required: true
diff --git a/dts/common/nordic/nrf9280.dtsi b/dts/common/nordic/nrf9280.dtsi
new file mode 100644
index 0000000..166c865
--- /dev/null
+++ b/dts/common/nordic/nrf9280.dtsi
@@ -0,0 +1,1270 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <nordic/nrf_common.dtsi>
+
+#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
+#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
+#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
+
+/delete-node/ &sw_pwm;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpuapp: cpu@2 {
+ compatible = "arm,cortex-m33";
+ reg = <2>;
+ device_type = "cpu";
+ clock-frequency = <DT_FREQ_M(320)>;
+ };
+
+ cpurad: cpu@3 {
+ compatible = "arm,cortex-m33";
+ reg = <3>;
+ device_type = "cpu";
+ clock-frequency = <DT_FREQ_M(256)>;
+ };
+
+ cpuppr: cpu@d {
+ compatible = "nordic,vpr";
+ reg = <13>;
+ device_type = "cpu";
+ clock-frequency = <DT_FREQ_M(16)>;
+ riscv,isa = "rv32emc";
+ nordic,bus-width = <32>;
+
+ cpuppr_vevif_rx: mailbox {
+ compatible = "nordic,nrf-vevif-task-rx";
+ status = "disabled";
+ interrupt-parent = <&cpuppr_clic>;
+ interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
+ <1 NRF_DEFAULT_IRQ_PRIORITY>,
+ <2 NRF_DEFAULT_IRQ_PRIORITY>,
+ <3 NRF_DEFAULT_IRQ_PRIORITY>,
+ <4 NRF_DEFAULT_IRQ_PRIORITY>,
+ <5 NRF_DEFAULT_IRQ_PRIORITY>,
+ <6 NRF_DEFAULT_IRQ_PRIORITY>,
+ <7 NRF_DEFAULT_IRQ_PRIORITY>,
+ <8 NRF_DEFAULT_IRQ_PRIORITY>,
+ <9 NRF_DEFAULT_IRQ_PRIORITY>,
+ <10 NRF_DEFAULT_IRQ_PRIORITY>,
+ <11 NRF_DEFAULT_IRQ_PRIORITY>,
+ <12 NRF_DEFAULT_IRQ_PRIORITY>,
+ <13 NRF_DEFAULT_IRQ_PRIORITY>,
+ <14 NRF_DEFAULT_IRQ_PRIORITY>,
+ <15 NRF_DEFAULT_IRQ_PRIORITY>;
+ #mbox-cells = <1>;
+ nordic,tasks = <16>;
+ nordic,tasks-mask = <0x0000fff0>;
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpurad_uicr_ext: memory@e401000 {
+ reg = <0xe401000 DT_SIZE_K(2)>;
+ };
+
+ cpuapp_uicr_ext: memory@e401800 {
+ reg = <0xe401800 DT_SIZE_K(2)>;
+ };
+ };
+
+ clocks {
+ hfxo: hfxo {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <DT_FREQ_M(32)>;
+ };
+
+ fll16m: fll16m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <DT_FREQ_M(16)>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mram1x: mram@e000000 {
+ compatible = "nordic,mram";
+ reg = <0xe000000 DT_SIZE_K(8192)>;
+ erase-block-size = <4096>;
+ write-block-size = <16>;
+ };
+
+ cpuapp_uicr: uicr@fff8000 {
+ compatible = "nordic,nrf-uicr-v2";
+ reg = <0xfff8000 DT_SIZE_K(2)>;
+ domain = <2>;
+ ptr-ext-uicr = <&cpuapp_uicr_ext>;
+ };
+
+ cpurad_uicr: uicr@fffa000 {
+ compatible = "nordic,nrf-uicr-v2";
+ reg = <0xfffa000 DT_SIZE_K(2)>;
+ domain = <3>;
+ ptr-ext-uicr = <&cpurad_uicr_ext>;
+ };
+
+ ficr: ficr@fffe000 {
+ compatible = "nordic,nrf-ficr";
+ reg = <0xfffe000 DT_SIZE_K(2)>;
+ #nordic,ficr-cells = <1>;
+ };
+
+ cpuapp_ram0: sram@22000000 {
+ compatible = "mmio-sram";
+ reg = <0x22000000 DT_SIZE_K(32)>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000000 0x8000>;
+ };
+
+ cpurad_ram0: sram@23000000 {
+ compatible = "mmio-sram";
+ reg = <0x23000000 DT_SIZE_K(192)>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x23000000 0x30000>;
+ };
+
+ cpurad_ram1: sram@23040000 {
+ compatible = "mmio-sram";
+ reg = <0x23040000 DT_SIZE_K(32)>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x23040000 0x8000>;
+ };
+
+ cpuapp_peripherals: peripheral@52000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x52000000 0x1000000>;
+
+ cpuapp_hsfll: clock@d000 {
+ compatible = "nordic,nrf-hsfll";
+ #clock-cells = <0>;
+ reg = <0xd000 0x1000>;
+ clocks = <&fll16m>;
+ clock-frequency = <DT_FREQ_M(320)>;
+ nordic,ficrs =
+ <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>,
+ <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>,
+ <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>;
+ nordic,ficr-names = "vsup", "coarse", "fine";
+ };
+
+ cpuapp_ipct: ipct@13000 {
+ compatible = "nordic,nrf-ipct-local";
+ reg = <0x13000 0x1000>;
+ status = "disabled";
+ channels = <4>;
+ interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
+ <65 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ cpuapp_wdt010: watchdog@14000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x14000 0x1000>;
+ status = "disabled";
+ interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ cpuapp_wdt011: watchdog@15000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x15000 0x1000>;
+ status = "disabled";
+ interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ cpuapp_ieee802154: ieee802154 {
+ compatible = "nordic,nrf-ieee802154";
+ status = "disabled";
+ };
+
+ cpuapp_resetinfo: resetinfo@1e000 {
+ compatible = "nordic,nrf-resetinfo";
+ reg = <0x1e000 0x1000>;
+ };
+ };
+
+ cpurad_peripherals: peripheral@53000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53000000 0x1000000>;
+
+ cpurad_hsfll: clock@d000 {
+ compatible = "nordic,nrf-hsfll";
+ #clock-cells = <0>;
+ reg = <0xd000 0x1000>;
+ clocks = <&fll16m>;
+ clock-frequency = <DT_FREQ_M(256)>;
+ nordic,ficrs =
+ <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>,
+ <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>,
+ <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>;
+ nordic,ficr-names = "vsup", "coarse", "fine";
+ };
+
+ cpurad_wdt010: watchdog@13000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x13000 0x1000>;
+ status = "disabled";
+ interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ cpurad_wdt011: watchdog@14000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x14000 0x1000>;
+ status = "disabled";
+ interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ cpurad_resetinfo: resetinfo@1e000 {
+ compatible = "nordic,nrf-resetinfo";
+ reg = <0x1e000 0x1000>;
+ };
+
+ dppic020: dppic@22000 {
+ compatible = "nordic,nrf-dppic-local";
+ reg = <0x22000 0x1000>;
+ status = "disabled";
+ };
+
+ cpurad_ipct: ipct@24000 {
+ compatible = "nordic,nrf-ipct-local";
+ reg = <0x24000 0x1000>;
+ status = "disabled";
+ channels = <8>;
+ interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
+ <65 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ egu020: egu@25000 {
+ compatible = "nordic,nrf-egu";
+ reg = <0x25000 0x1000>;
+ status = "disabled";
+ interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ timer020: timer@28000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x28000 0x1000>;
+ status = "disabled";
+ cc-num = <8>;
+ interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ max-frequency = <DT_FREQ_M(32)>;
+ prescaler = <0>;
+ };
+
+ timer021: timer@29000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x29000 0x1000>;
+ status = "disabled";
+ cc-num = <8>;
+ interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ max-frequency = <DT_FREQ_M(32)>;
+ prescaler = <0>;
+ };
+
+ timer022: timer@2a000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x2a000 0x1000>;
+ status = "disabled";
+ cc-num = <8>;
+ interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ max-frequency = <DT_FREQ_M(32)>;
+ prescaler = <0>;
+ };
+
+ rtc: rtc@2b000 {
+ compatible = "nordic,nrf-rtc";
+ reg = <0x2b000 0x1000>;
+ status = "disabled";
+ cc-num = <4>;
+ clock-frequency = <32768>;
+ interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>;
+ prescaler = <1>;
+ };
+
+ radio: radio@2c000 {
+ compatible = "nordic,nrf-radio";
+ reg = <0x2c000 0x1000>;
+ status = "disabled";
+ ble-2mbps-supported;
+ ble-coded-phy-supported;
+ dfe-supported;
+ ieee802154-supported;
+ interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>;
+
+ cpurad_ieee802154: ieee802154 {
+ compatible = "nordic,nrf-ieee802154";
+ status = "disabled";
+ };
+ };
+
+ ccm030: ccm@3a000 {
+ compatible = "nordic,nrf-ccm";
+ reg = <0x3a000 0x1000>;
+ interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>;
+ status = "disabled";
+ };
+
+ ecb030: ecb@3b000 {
+ compatible = "nordic,nrf-ecb";
+ reg = <0x3b000 0x1000>;
+ interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>;
+ status = "disabled";
+ };
+
+ ccm031: ccm@3c000 {
+ compatible = "nordic,nrf-ccm";
+ reg = <0x3c000 0x1000>;
+ interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>;
+ status = "disabled";
+ };
+
+ ecb031: ecb@3d000 {
+ compatible = "nordic,nrf-ecb";
+ reg = <0x3d000 0x1000>;
+ status = "disabled";
+ interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+ };
+
+ global_peripherals: peripheral@5f000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5f000000 0x1000000>;
+
+ usbhs: usbhs@86000 {
+ compatible = "nordic,nrf-usbhs", "snps,dwc2";
+ reg = <0x86000 0x1000>, <0x2f700000 0x40000>;
+ reg-names = "wrapper", "core";
+ interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>;
+ num-in-eps = <8>;
+ num-out-eps = <10>;
+ ghwcfg1 = <0xaa555000>;
+ ghwcfg2 = <0x22abfc72>;
+ ghwcfg4 = <0x1e10aa60>;
+ status = "disabled";
+ };
+
+ exmif: spi@95000 {
+ compatible = "nordic,nrf-exmif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x95000 0x500 0x95500 0xb00>;
+ reg-names = "wrapper", "core";
+ interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>;
+ clock-frequency = <DT_FREQ_M(400)>;
+ fifo-depth = <32>;
+ max-xfer-size = <16>;
+ status = "disabled";
+ };
+
+ cpusec_bellboard: mailbox@99000 {
+ reg = <0x99000 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ };
+
+ cpuapp_bellboard: mailbox@9a000 {
+ reg = <0x9a000 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ };
+
+ cpurad_bellboard: mailbox@9b000 {
+ reg = <0x9b000 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ };
+
+ cpucell_bellboard: mailbox@9c000 {
+ reg = <0x9c000 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ };
+
+ canpll: clock-controller@8c2000{
+ compatible = "nordic,nrf-auxpll";
+ reg = <0x8c2000 0x1000>;
+ interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>;
+ clocks = <&hfxo>;
+ #clock-cells = <0>;
+ nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>;
+ nordic,frequency = <0>;
+ nordic,out-div = <2>;
+ nordic,out-drive = <0>;
+ nordic,current-tune = <6>;
+ nordic,sdm-disable;
+ nordic,range = "high";
+ status = "disabled";
+ };
+
+ cpusys_vevif_tx: mailbox@8c8000 {
+ compatible = "nordic,nrf-vevif-task-tx";
+ reg = <0x8c8000 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ nordic,tasks = <32>;
+ nordic,tasks-mask = <0xfffff0ff>;
+ };
+
+ ipct120: ipct@8d1000 {
+ compatible = "nordic,nrf-ipct-global";
+ reg = <0x8d1000 0x1000>;
+ status = "disabled";
+ channels = <8>;
+ global-domain-id = <12>;
+ };
+
+ can120: can@8d8000 {
+ compatible = "nordic,nrf-can";
+ reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
+ reg-names = "wrapper", "m_can", "message_ram";
+ interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>;
+ clocks = <&canpll>;
+ bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+ status = "disabled";
+ };
+
+ can121: can@8db000 {
+ compatible = "nordic,nrf-can";
+ reg = <0x8db000 0x400>, <0x2fbf7800 0x800>, <0x2fbf0000 0x7800>;
+ reg-names = "wrapper", "m_can", "message_ram";
+ interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
+ clocks = <&canpll>;
+ bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+ status = "disabled";
+ };
+
+ dppic120: dppic@8e1000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x8e1000 0x1000>;
+ status = "disabled";
+ };
+
+ timer120: timer@8e2000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x8e2000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ max-frequency = <DT_FREQ_M(320)>;
+ prescaler = <0>;
+ };
+
+ timer121: timer@8e3000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x8e3000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ max-frequency = <DT_FREQ_M(320)>;
+ prescaler = <0>;
+ };
+
+ pwm120: pwm@8e4000 {
+ compatible = "nordic,nrf-pwm";
+ reg = <0x8e4000 0x1000>;
+ status = "disabled";
+ interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>;
+ #pwm-cells = <3>;
+ };
+
+ spi120: spi@8e6000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x8e6000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(32)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart120: uart@8e6000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x8e6000 0x1000>;
+ status = "disabled";
+ interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ spi121: spi@8e7000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x8e7000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(32)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ cpuppr_vpr: vpr@908000 {
+ compatible = "nordic,nrf-vpr-coprocessor";
+ reg = <0x908000 0x1000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x908000 0x1000>;
+
+ cpuppr_vevif_tx: mailbox@0 {
+ compatible = "nordic,nrf-vevif-task-tx";
+ reg = <0x0 0x1000>;
+ status = "disabled";
+ #mbox-cells = <1>;
+ nordic,tasks = <16>;
+ nordic,tasks-mask = <0x0000fff0>;
+ };
+ };
+
+ ipct130: ipct@921000 {
+ compatible = "nordic,nrf-ipct-global";
+ reg = <0x921000 0x1000>;
+ status = "disabled";
+ channels = <8>;
+ global-domain-id = <13>;
+ };
+
+ dppic130: dppic@922000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x922000 0x1000>;
+ status = "disabled";
+ };
+
+ rtc130: rtc@928000 {
+ compatible = "nordic,nrf-rtc";
+ reg = <0x928000 0x1000>;
+ status = "disabled";
+ cc-num = <4>;
+ clock-frequency = <32768>;
+ interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>;
+ prescaler = <1>;
+ };
+
+ rtc131: rtc@929000 {
+ compatible = "nordic,nrf-rtc";
+ reg = <0x929000 0x1000>;
+ status = "disabled";
+ cc-num = <4>;
+ clock-frequency = <32768>;
+ interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>;
+ prescaler = <1>;
+ };
+
+ wdt131: watchdog@92b000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x92b000 0x1000>;
+ status = "disabled";
+ interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ wdt132: watchdog@92c000 {
+ compatible = "nordic,nrf-wdt";
+ reg = <0x92c000 0x1000>;
+ status = "disabled";
+ interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ gpiote130: gpiote@934000 {
+ compatible = "nordic,nrf-gpiote";
+ reg = <0x934000 0x1000>;
+ status = "disabled";
+ instance = <130>;
+ };
+
+ gpiote131: gpiote@935000 {
+ compatible = "nordic,nrf-gpiote";
+ reg = <0x935000 0x1000>;
+ status = "disabled";
+ instance = <131>;
+ };
+
+ gpio0: gpio@938000 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x938000 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote130>;
+ ngpios = <13>;
+ port = <0>;
+ };
+
+ gpio1: gpio@938200 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x938200 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote130>;
+ ngpios = <12>;
+ port = <1>;
+ };
+
+ gpio2: gpio@938400 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x938400 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote130>;
+ ngpios = <12>;
+ port = <2>;
+ };
+
+ gpio6: gpio@938c00 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x938c00 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <14>;
+ port = <6>;
+ };
+
+ gpio8: gpio@939000 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939000 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <5>;
+ port = <8>;
+ };
+
+ gpio9: gpio@939200 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939200 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote130>;
+ ngpios = <6>;
+ port = <9>;
+ };
+
+ gpio10: gpio@939400 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939400 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ port = <10>;
+ };
+
+ gpio11: gpio@939600 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939600 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote131>;
+ ngpios = <8>;
+ port = <11>;
+ };
+
+ gpio12: gpio@939800 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939800 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote131>;
+ ngpios = <3>;
+ port = <12>;
+ };
+
+ gpio13: gpio@939a00 {
+ compatible = "nordic,nrf-gpio";
+ reg = <0x939a00 0x200>;
+ status = "disabled";
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpiote-instance = <&gpiote131>;
+ ngpios = <4>;
+ port = <13>;
+ };
+
+ dppic131: dppic@981000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x981000 0x1000>;
+ status = "disabled";
+ };
+
+ adc: adc@982000 {
+ compatible = "nordic,nrf-saadc";
+ reg = <0x982000 0x1000>;
+ interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>;
+ status = "disabled";
+ #io-channel-cells = <1>;
+ };
+
+ comp: comparator@983000 {
+ compatible = "nordic,nrf-comp";
+ reg = <0x983000 0x1000>;
+ status = "disabled";
+ interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>;
+ #io-channel-cells = <1>;
+ };
+
+ temp: temperature-sensor@984000 {
+ compatible = "nordic,nrf-temp";
+ reg = <0x984000 0x1000>;
+ interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>;
+ status = "disabled";
+ };
+
+ dppic132: dppic@991000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x991000 0x1000>;
+ status = "disabled";
+ };
+
+ qdec130: qdec@994000 {
+ compatible = "nordic,nrf-qdec";
+ reg = <0x994000 0x1000>;
+ status = "disabled";
+ interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ qdec131: qdec@995000 {
+ compatible = "nordic,nrf-qdec";
+ reg = <0x995000 0x1000>;
+ status = "disabled";
+ interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>;
+ };
+
+ grtc: grtc@99c000 {
+ compatible = "nordic,nrf-grtc";
+ reg = <0x99c000 0x1000>;
+ status = "disabled";
+ cc-num = <16>;
+ };
+
+ dppic133: dppic@9a1000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x9a1000 0x1000>;
+ status = "disabled";
+ };
+
+ timer130: timer@9a2000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9a2000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ timer131: timer@9a3000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9a3000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ pwm130: pwm@9a4000 {
+ compatible = "nordic,nrf-pwm";
+ reg = <0x9a4000 0x1000>;
+ status = "disabled";
+ interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>;
+ #pwm-cells = <3>;
+ };
+
+ i2c130: i2c@9a5000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9a5000 0x1000>;
+ status = "disabled";
+ interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi130: spi@9a5000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9a5000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart130: uart@9a5000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9a5000 0x1000>;
+ status = "disabled";
+ interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ i2c131: i2c@9a6000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9a6000 0x1000>;
+ status = "disabled";
+ interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi131: spi@9a6000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9a6000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart131: uart@9a6000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9a6000 0x1000>;
+ status = "disabled";
+ interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ dppic134: dppic@9b1000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x9b1000 0x1000>;
+ status = "disabled";
+ };
+
+ timer132: timer@9b2000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9b2000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ timer133: timer@9b3000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9b3000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ pwm131: pwm@9b4000 {
+ compatible = "nordic,nrf-pwm";
+ reg = <0x9b4000 0x1000>;
+ status = "disabled";
+ interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>;
+ #pwm-cells = <3>;
+ };
+
+ i2c132: i2c@9b5000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9b5000 0x1000>;
+ status = "disabled";
+ interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi132: spi@9b5000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9b5000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart132: uart@9b5000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9b5000 0x1000>;
+ status = "disabled";
+ interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ i2c133: i2c@9b6000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9b6000 0x1000>;
+ status = "disabled";
+ interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi133: spi@9b6000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9b6000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart133: uart@9b6000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9b6000 0x1000>;
+ status = "disabled";
+ interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ dppic135: dppic@9c1000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x9c1000 0x1000>;
+ status = "disabled";
+ };
+
+ timer134: timer@9c2000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9c2000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ timer135: timer@9c3000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9c3000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ pwm132: pwm@9c4000 {
+ compatible = "nordic,nrf-pwm";
+ reg = <0x9c4000 0x1000>;
+ status = "disabled";
+ interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>;
+ #pwm-cells = <3>;
+ };
+
+ i2c134: i2c@9c5000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9c5000 0x1000>;
+ status = "disabled";
+ interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi134: spi@9c5000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9c5000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart134: uart@9c5000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9c5000 0x1000>;
+ status = "disabled";
+ interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ i2c135: i2c@9c6000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9c6000 0x1000>;
+ status = "disabled";
+ interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi135: spi@9c6000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9c6000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart135: uart@9c6000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9c6000 0x1000>;
+ status = "disabled";
+ interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ dppic136: dppic@9d1000 {
+ compatible = "nordic,nrf-dppic-global";
+ reg = <0x9d1000 0x1000>;
+ status = "disabled";
+ };
+
+ timer136: timer@9d2000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9d2000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ timer137: timer@9d3000 {
+ compatible = "nordic,nrf-timer";
+ reg = <0x9d3000 0x1000>;
+ status = "disabled";
+ cc-num = <6>;
+ interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-bit-width = <32>;
+ prescaler = <0>;
+ };
+
+ pwm133: pwm@9d4000 {
+ compatible = "nordic,nrf-pwm";
+ reg = <0x9d4000 0x1000>;
+ status = "disabled";
+ interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>;
+ #pwm-cells = <3>;
+ };
+
+ i2c136: i2c@9d5000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9d5000 0x1000>;
+ status = "disabled";
+ interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi136: spi@9d5000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9d5000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart136: uart@9d5000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9d5000 0x1000>;
+ status = "disabled";
+ interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+
+ i2c137: i2c@9d6000 {
+ compatible = "nordic,nrf-twim";
+ reg = <0x9d6000 0x1000>;
+ status = "disabled";
+ interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
+ easydma-maxcnt-bits = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
+ <NRF_FUN_TWIM_SCL>;
+ };
+
+ spi137: spi@9d6000 {
+ compatible = "nordic,nrf-spim";
+ reg = <0x9d6000 0x1000>;
+ status = "disabled";
+ easydma-maxcnt-bits = <15>;
+ interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
+ max-frequency = <DT_FREQ_M(8)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rx-delay-supported;
+ rx-delay = <1>;
+ nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
+ <NRF_FUN_SPIM_SCK>,
+ <NRF_FUN_SPIS_MISO>,
+ <NRF_FUN_SPIS_SCK>;
+ };
+
+ uart137: uart@9d6000 {
+ compatible = "nordic,nrf-uarte";
+ reg = <0x9d6000 0x1000>;
+ status = "disabled";
+ interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
+ nordic,clockpin-enable = <NRF_FUN_UART_TX>;
+ };
+ };
+ };
+
+ cpuapp_ppb: cpuapp-ppb-bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpuapp_systick: timer@e000e010 {
+ compatible = "arm,armv8m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ cpuapp_nvic: interrupt-controller@e000e100 {
+ compatible = "arm,v8m-nvic";
+ reg = <0xe000e100 0xc00>;
+ arm,num-irq-priority-bits = <3>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ };
+ };
+
+ cpurad_ppb: cpurad-ppb-bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpurad_systick: timer@e000e010 {
+ compatible = "arm,armv8m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ cpurad_nvic: interrupt-controller@e000e100 {
+ compatible = "arm,v8m-nvic";
+ reg = <0xe000e100 0xc00>;
+ arm,num-irq-priority-bits = <3>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ };
+ };
+
+ cpuppr_private: cpuppr-private-bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpuppr_clic: interrupt-controller@5f909000 {
+ compatible = "nordic,nrf-clic";
+ reg = <0x5f909000 0x3000>;
+ status = "disabled";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ };
+ };
+
+ temp_nrfs: temp {
+ compatible = "nordic,nrf-temp-nrfs";
+ status = "disabled";
+ };
+};
diff --git a/dts/riscv/espressif/esp32c2/esp32c2.dtsi b/dts/riscv/espressif/esp32c2/esp32c2.dtsi
new file mode 100644
index 0000000..4aaf8d7
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp32c2.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c2_common.dtsi"
diff --git a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
new file mode 100644
index 0000000..ab60ddb
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h>
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
+#include <dt-bindings/pinctrl/esp32-pinctrl.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ die-temp0 = &coretemp;
+ };
+
+ chosen {
+ zephyr,entropy = &trng0;
+ zephyr,flash-controller = &flash;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "espressif,riscv", "riscv";
+ riscv,isa = "rv32imc_zicsr";
+ reg = <0>;
+ clock-source = <ESP32_CPU_CLK_SRC_PLL>;
+ clock-frequency = <DT_FREQ_M(120)>;
+ xtal-freq = <DT_FREQ_M(26)>;
+ };
+ };
+
+ pinctrl: pin-controller {
+ compatible = "espressif,esp32-pinctrl";
+ status = "okay";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ sram0: memory@3fc7c000 {
+ compatible = "mmio-sram";
+ reg = <0x3fc7c000 0x50000>;
+ };
+
+ intc: interrupt-controller@600c2000 {
+ compatible = "espressif,esp32-intc";
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x600c2000 0x198>;
+ status = "okay";
+ };
+
+ systimer0: systimer@60023000 {
+ compatible = "espressif,esp32-systimer";
+ reg = <0x60023000 0x80>;
+ interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ status = "okay";
+ };
+
+ rtc: rtc@60008000 {
+ compatible = "espressif,esp32-rtc";
+ reg = <0x60008000 0x1000>;
+ fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
+ slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
+ #clock-cells = <1>;
+ status = "okay";
+ };
+
+ rtc_timer: rtc_timer@60008004 {
+ reg = <0x60008004 0xC>;
+ compatible = "espressif,esp32-rtc-timer";
+ clocks = <&rtc ESP32_MODULE_MAX>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ status = "disabled";
+ };
+
+ flash: flash-controller@60002000 {
+ compatible = "espressif,esp32-flash-controller";
+ reg = <0x60002000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ compatible = "soc-nv-flash";
+ reg = <0 0x400000>;
+ erase-block-size = <4096>;
+ write-block-size = <4>;
+ };
+ };
+
+ gpio0: gpio@60004000 {
+ compatible = "espressif,esp32-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x60004000 0x800>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ /* Maximum available pins (per port)
+ * Actual occupied pins are specified
+ * on part number dtsi level, using
+ * the `gpio-reserved-ranges` property.
+ */
+ ngpios = <20>; /* 0..20 */
+ };
+
+ i2c0: i2c@60013000 {
+ compatible = "espressif,esp32-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60013000 0x1000>;
+ interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_I2C0_MODULE>;
+ status = "disabled";
+ };
+
+ uart0: uart@60000000 {
+ compatible = "espressif,esp32-uart";
+ reg = <0x60000000 0x400>;
+ status = "disabled";
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_UART0_MODULE>;
+ };
+
+ uart1: uart@60010000 {
+ compatible = "espressif,esp32-uart";
+ reg = <0x60010000 0x400>;
+ status = "disabled";
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_UART1_MODULE>;
+ current-speed = <115200>;
+ };
+
+ ledc0: ledc@60019000 {
+ compatible = "espressif,esp32-ledc";
+ pwm-controller;
+ #pwm-cells = <3>;
+ reg = <0x60019000 0x1000>;
+ clocks = <&rtc ESP32_LEDC_MODULE>;
+ status = "disabled";
+ };
+
+ timer0: counter@6001f000 {
+ compatible = "espressif,esp32-timer";
+ reg = <0x6001F000 DT_SIZE_K(4)>;
+ group = <0>;
+ index = <0>;
+ interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ status = "disabled";
+ };
+
+ trng0: trng@3ff700b0 {
+ compatible = "espressif,esp32-trng";
+ reg = <0x3FF700B0 0x4>;
+ status = "disabled";
+ };
+
+ spi2: spi@60024000 {
+ compatible = "espressif,esp32-spi";
+ reg = <0x60024000 DT_SIZE_K(4)>;
+ interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_SPI2_MODULE>;
+ dma-clk = <ESP32_GDMA_MODULE>;
+ dma-host = <0>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@6001f048 {
+ compatible = "espressif,esp32-watchdog";
+ reg = <0x6001f048 0x20>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_TIMG0_MODULE>;
+ status = "disabled";
+ };
+
+ coretemp: coretemp@60040058 {
+ compatible = "espressif,esp32-temp";
+ friendly-name = "coretemp";
+ reg = <0x60040058 0x4>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/riscv/espressif/esp32c2/esp8684_mini_h2.dtsi b/dts/riscv/espressif/esp32c2/esp8684_mini_h2.dtsi
new file mode 100644
index 0000000..18a7f49
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp8684_mini_h2.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c2_common.dtsi"
+
+/* 2MB flash */
+&flash0 {
+ reg = <0x0 DT_SIZE_M(2)>;
+};
diff --git a/dts/riscv/espressif/esp32c2/esp8684_mini_h4.dtsi b/dts/riscv/espressif/esp32c2/esp8684_mini_h4.dtsi
new file mode 100644
index 0000000..d7fd012
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp8684_mini_h4.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c2_common.dtsi"
+
+/* 4MB flash */
+&flash0 {
+ reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/riscv/espressif/esp32c2/esp8684_wroom_h2.dtsi b/dts/riscv/espressif/esp32c2/esp8684_wroom_h2.dtsi
new file mode 100644
index 0000000..18a7f49
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp8684_wroom_h2.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c2_common.dtsi"
+
+/* 2MB flash */
+&flash0 {
+ reg = <0x0 DT_SIZE_M(2)>;
+};
diff --git a/dts/riscv/espressif/esp32c2/esp8684_wroom_h4.dtsi b/dts/riscv/espressif/esp32c2/esp8684_wroom_h4.dtsi
new file mode 100644
index 0000000..d7fd012
--- /dev/null
+++ b/dts/riscv/espressif/esp32c2/esp8684_wroom_h4.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c2_common.dtsi"
+
+/* 4MB flash */
+&flash0 {
+ reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
index 71b7031..4dab389 100644
--- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
+++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
@@ -88,7 +88,7 @@
intc: interrupt-controller@600c2000 {
compatible = "espressif,esp32-intc";
#address-cells = <0>;
- #interrupt-cells = <1>;
+ #interrupt-cells = <3>;
interrupt-controller;
reg = <0x600c2000 0x198>;
status = "okay";
@@ -97,7 +97,7 @@
systimer0: systimer@60023000 {
compatible = "espressif,esp32-systimer";
reg = <0x60023000 0x80>;
- interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE>;
+ interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "okay";
};
@@ -115,7 +115,7 @@
compatible = "espressif,esp32-xt-wdt";
reg = <0x60008004 0x4>;
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -124,7 +124,7 @@
reg = <0x60008004 0xC>;
compatible = "espressif,esp32-rtc-timer";
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "okay";
};
@@ -149,7 +149,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x60004000 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
/* Maximum available pins (per port)
* Actual occupied pins are specified
@@ -164,7 +164,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60013000 0x1000>;
- interrupts = <I2C_EXT0_INTR_SOURCE>;
+ interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C0_MODULE>;
status = "disabled";
@@ -174,7 +174,7 @@
compatible = "espressif,esp32-uart";
reg = <0x60000000 0x400>;
status = "disabled";
- interrupts = <UART0_INTR_SOURCE>;
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART0_MODULE>;
};
@@ -183,7 +183,7 @@
compatible = "espressif,esp32-uart";
reg = <0x60010000 0x400>;
status = "disabled";
- interrupts = <UART1_INTR_SOURCE>;
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART1_MODULE>;
current-speed = <115200>;
@@ -202,7 +202,7 @@
compatible = "espressif,esp32-usb-serial";
reg = <0x60043000 0x400>;
status = "disabled";
- interrupts = <USB_INTR_SOURCE>;
+ interrupts = <USB_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_USB_MODULE>;
};
@@ -212,7 +212,7 @@
reg = <0x6001F000 DT_SIZE_K(4)>;
group = <0>;
index = <0>;
- interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -222,7 +222,7 @@
reg = <0x60020000 DT_SIZE_K(4)>;
group = <1>;
index = <0>;
- interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -236,7 +236,7 @@
twai: can@6002b000 {
compatible = "espressif,esp32-twai";
reg = <0x6002b000 DT_SIZE_K(4)>;
- interrupts = <TWAI_INTR_SOURCE>;
+ interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TWAI_MODULE>;
status = "disabled";
@@ -245,7 +245,7 @@
spi2: spi@60024000 {
compatible = "espressif,esp32-spi";
reg = <0x60024000 DT_SIZE_K(4)>;
- interrupts = <SPI2_INTR_SOURCE>;
+ interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SPI2_MODULE>;
dma-clk = <ESP32_GDMA_MODULE>;
@@ -256,7 +256,7 @@
wdt0: watchdog@6001f048 {
compatible = "espressif,esp32-watchdog";
reg = <0x6001f048 0x20>;
- interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "disabled";
@@ -265,7 +265,7 @@
wdt1: watchdog@60020048 {
compatible = "espressif,esp32-watchdog";
reg = <0x60020048 0x20>;
- interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
status = "disabled";
@@ -300,7 +300,10 @@
compatible = "espressif,esp32-gdma";
reg = <0x6003f000 DT_SIZE_K(4)>;
#dma-cells = <1>;
- interrupts = <DMA_CH0_INTR_SOURCE DMA_CH1_INTR_SOURCE DMA_CH2_INTR_SOURCE>;
+ interrupts =
+ <DMA_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_GDMA_MODULE>;
dma-channels = <6>;
diff --git a/dts/riscv/espressif/esp32c3/esp32c3_wroom_n4.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_wroom_n4.dtsi
new file mode 100644
index 0000000..8f0cfa6
--- /dev/null
+++ b/dts/riscv/espressif/esp32c3/esp32c3_wroom_n4.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32c3_common.dtsi"
+
+/* 4MB flash */
+&flash0 {
+ reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
index 1a519c0..ceb0f04 100644
--- a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
+++ b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
@@ -27,10 +27,27 @@
compatible = "espressif,riscv";
riscv,isa = "rv32imac_zicsr";
reg = <0>;
+ cpu-power-states = <&light_sleep &deep_sleep>;
clock-source = <ESP32_CPU_CLK_SRC_PLL>;
clock-frequency = <DT_FREQ_M(160)>;
xtal-freq = <DT_FREQ_M(40)>;
};
+
+ power-states {
+ light_sleep: light_sleep {
+ compatible = "zephyr,power-state";
+ power-state-name = "standby";
+ min-residency-us = <200>;
+ exit-latency-us = <60>;
+ };
+
+ deep_sleep: deep_sleep {
+ compatible = "zephyr,power-state";
+ power-state-name = "soft-off";
+ min-residency-us = <2000>;
+ exit-latency-us = <212>;
+ };
+ };
};
pinctrl: pin-controller {
@@ -52,7 +69,7 @@
intc: interrupt-controller@60010000 {
compatible = "espressif,esp32-intc";
#address-cells = <0>;
- #interrupt-cells = <1>;
+ #interrupt-cells = <3>;
interrupt-controller;
reg = <0x60010000 DT_SIZE_K(4)>;
status = "okay";
@@ -61,26 +78,25 @@
systimer0: systimer@6000a000 {
compatible = "espressif,esp32-systimer";
reg = <0x6000A000 DT_SIZE_K(4)>;
- interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE>;
+ interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "okay";
};
- rtc: rtc@600b000 {
+ rtc: rtc@600b0000 {
compatible = "espressif,esp32-rtc";
- reg = <0x600B000 DT_SIZE_K(1)>;
+ reg = <0x600B0000 DT_SIZE_K(1)>;
fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
#clock-cells = <1>;
status = "okay";
-
};
rtc_timer: rtc_timer@600b0c00 {
compatible = "espressif,esp32-rtc-timer";
reg = <0x600B0C00 DT_SIZE_K(1)>;
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <LP_RTC_TIMER_INTR_SOURCE>;
+ interrupts = <LP_RTC_TIMER_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -88,7 +104,7 @@
spi2: spi@60081000 {
compatible = "espressif,esp32-spi";
reg = <0x60081000 DT_SIZE_K(4)>;
- interrupts = <GSPI2_INTR_SOURCE>;
+ interrupts = <GSPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SPI2_MODULE>;
dma-clk = <ESP32_GDMA_MODULE>;
@@ -99,7 +115,7 @@
wdt0: watchdog@60008048 {
compatible = "espressif,esp32-watchdog";
reg = <0x60008048 0x20>;
- interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "disabled";
@@ -108,7 +124,7 @@
wdt1: watchdog@60009048 {
compatible = "espressif,esp32-watchdog";
reg = <0x60009048 0x20>;
- interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
status = "disabled";
@@ -132,9 +148,13 @@
compatible = "espressif,esp32-gdma";
reg = <0x60080000 DT_SIZE_K(4)>;
#dma-cells = <1>;
- interrupts = <DMA_IN_CH0_INTR_SOURCE DMA_OUT_CH0_INTR_SOURCE
- DMA_IN_CH1_INTR_SOURCE DMA_OUT_CH1_INTR_SOURCE
- DMA_IN_CH2_INTR_SOURCE DMA_OUT_CH2_INTR_SOURCE>;
+ interrupts =
+ <DMA_IN_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_OUT_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_IN_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_OUT_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_IN_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <DMA_OUT_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_GDMA_MODULE>;
dma-channels = <6>;
@@ -147,7 +167,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x60091000 DT_SIZE_K(4)>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
ngpios = <30>; /* 0..29 */
};
@@ -156,7 +176,7 @@
compatible = "espressif,esp32-uart";
reg = <0x60000000 DT_SIZE_K(4)>;
status = "disabled";
- interrupts = <UART0_INTR_SOURCE>;
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART0_MODULE>;
};
@@ -165,7 +185,7 @@
compatible = "espressif,esp32-uart";
reg = <0x60001000 DT_SIZE_K(4)>;
status = "disabled";
- interrupts = <UART1_INTR_SOURCE>;
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART1_MODULE>;
current-speed = <115200>;
@@ -175,7 +195,7 @@
compatible = "espressif,esp32-usb-serial";
reg = <0x6000F000 0x1000>;
status = "disabled";
- interrupts = <USB_SERIAL_JTAG_INTR_SOURCE>;
+ interrupts = <USB_SERIAL_JTAG_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_USB_MODULE>;
};
@@ -189,5 +209,4 @@
status = "disabled";
};
};
-
};
diff --git a/dts/riscv/nordic/nrf9280_cpuppr.dtsi b/dts/riscv/nordic/nrf9280_cpuppr.dtsi
new file mode 100644
index 0000000..ad5fb30
--- /dev/null
+++ b/dts/riscv/nordic/nrf9280_cpuppr.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf9280.dtsi>
+
+cpu: &cpuppr {};
+clic: &cpuppr_clic {};
+cpuppr_vevif: &cpuppr_vevif_rx {};
+cpusys_vevif: &cpusys_vevif_tx {};
+
+/delete-node/ &cpuapp;
+/delete-node/ &cpuapp_peripherals;
+/delete-node/ &cpuapp_ppb;
+/delete-node/ &cpuapp_ram0;
+/delete-node/ &cpurad;
+/delete-node/ &cpurad_peripherals;
+/delete-node/ &cpurad_ppb;
+/delete-node/ &cpurad_ram0;
+
+/ {
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&cpuppr_clic>;
+ ranges;
+ };
+};
+
+&cpuppr_private {
+ compatible = "simple-bus";
+ ranges;
+};
+
+&cpuppr_clic {
+ status = "okay";
+};
+
+&cpusec_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpuapp_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&cpurad_bellboard {
+ compatible = "nordic,nrf-bellboard-tx";
+};
+
+&gpiote130 {
+ interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&grtc {
+ interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>;
+};
diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi
index bf93141..8557d2e 100644
--- a/dts/riscv/riscv32-litex-vexriscv.dtsi
+++ b/dts/riscv/riscv32-litex-vexriscv.dtsi
@@ -144,6 +144,23 @@
"uptime_cycles";
status = "disabled";
};
+ wdt0: watchdog@e000d000 {
+ compatible = "litex,watchdog";
+ interrupt-parent = <&intc0>;
+ reg = <0xe000d000 0x4>,
+ <0xe000d004 0x4>,
+ <0xe000d008 0x4>,
+ <0xe000d00c 0x4>,
+ <0xe000d010 0x4>,
+ <0xe000d014 0x4>;
+ reg-names = "control",
+ "cycles",
+ "remaining",
+ "ev_status",
+ "ev_pending",
+ "ev_enable";
+ interrupts = <8 15>;
+ };
mdio0: mdio@e0008000 {
compatible = "litex,liteeth-mdio";
reg = <0xe0008000 0x4>,
diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi
index f646dc7..6003ec00 100644
--- a/dts/xtensa/espressif/esp32/esp32_common.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi
@@ -74,7 +74,7 @@
eth: eth {
compatible = "espressif,esp32-eth";
- interrupts = <ETH_MAC_INTR_SOURCE>;
+ interrupts = <ETH_MAC_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_EMAC_MODULE>;
status = "disabled";
@@ -110,7 +110,7 @@
};
intc: interrupt-controller@3ff00104 {
- #interrupt-cells = <1>;
+ #interrupt-cells = <3>;
compatible = "espressif,esp32-intc";
interrupt-controller;
reg = <0x3ff00104 0x114>;
@@ -131,7 +131,7 @@
reg = <0x3ff48004 0xC>;
compatible = "espressif,esp32-rtc-timer";
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "okay";
};
@@ -139,8 +139,6 @@
flash: flash-controller@3ff42000 {
compatible = "espressif,esp32-flash-controller";
reg = <0x3ff42000 0x1000>;
- /* interrupts = <3 0>; */
-
#address-cells = <1>;
#size-cells = <1>;
@@ -166,7 +164,9 @@
status = "disabled";
shared-memory = <&ipmmem0>;
shared-memory-size = <0x400>;
- interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
+ interrupts =
+ <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
@@ -176,7 +176,9 @@
status = "disabled";
shared-memory = <&ipmmem0>;
shared-memory-size = <0x400>;
- interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
+ interrupts =
+ <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
#mbox-cells = <1>;
};
@@ -184,21 +186,21 @@
ipi0: ipi@3f4c0058 {
compatible = "espressif,crosscore-interrupt";
reg = <0x3f4c0058 0x4>;
- interrupts = <FROM_CPU_INTR0_SOURCE>;
+ interrupts = <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
ipi1: ipi@3f4c005c {
compatible = "espressif,crosscore-interrupt";
reg = <0x3f4c005c 0x4>;
- interrupts = <FROM_CPU_INTR1_SOURCE>;
+ interrupts = <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
uart0: uart@3ff40000 {
compatible = "espressif,esp32-uart";
reg = <0x3ff40000 0x400>;
- interrupts = <UART0_INTR_SOURCE>;
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART0_MODULE>;
status = "disabled";
@@ -207,7 +209,7 @@
uart1: uart@3ff50000 {
compatible = "espressif,esp32-uart";
reg = <0x3ff50000 0x400>;
- interrupts = <UART1_INTR_SOURCE>;
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART1_MODULE>;
status = "disabled";
@@ -216,7 +218,7 @@
uart2: uart@3ff6e000 {
compatible = "espressif,esp32-uart";
reg = <0x3ff6E000 0x400>;
- interrupts = <UART2_INTR_SOURCE>;
+ interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART2_MODULE>;
status = "disabled";
@@ -225,7 +227,7 @@
pcnt: pcnt@3ff57000 {
compatible = "espressif,esp32-pcnt";
reg = <0x3ff57000 0x1000>;
- interrupts = <PCNT_INTR_SOURCE>;
+ interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PCNT_MODULE>;
status = "disabled";
@@ -242,7 +244,7 @@
mcpwm0: mcpwm@3ff5e000 {
compatible = "espressif,esp32-mcpwm";
reg = <0x3ff5e000 0x1000>;
- interrupts = <PWM0_INTR_SOURCE>;
+ interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PWM0_MODULE>;
#pwm-cells = <3>;
@@ -252,7 +254,7 @@
mcpwm1: mcpwm@3ff6c000 {
compatible = "espressif,esp32-mcpwm";
reg = <0x3ff6c000 0x1000>;
- interrupts = <PWM1_INTR_SOURCE>;
+ interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PWM1_MODULE>;
#pwm-cells = <3>;
@@ -277,7 +279,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x3ff44000 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
/* Maximum available pins (per port)
* Actual occupied pins are specified
@@ -292,7 +294,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x3ff44800 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
ngpios = <8>; /* 32..39 */
};
@@ -301,7 +303,7 @@
touch: touch@3ff48858 {
compatible = "espressif,esp32-touch";
reg = <0x3ff48858 0x38>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -311,7 +313,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3ff53000 0x1000>;
- interrupts = <I2C_EXT0_INTR_SOURCE>;
+ interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C0_MODULE>;
status = "disabled";
@@ -322,7 +324,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3ff67000 0x1000>;
- interrupts = <I2C_EXT1_INTR_SOURCE>;
+ interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C1_MODULE>;
status = "disabled";
@@ -331,14 +333,13 @@
trng0: trng@3ff75144 {
compatible = "espressif,esp32-trng";
reg = <0x3FF75144 0x4>;
- /* interrupts = <33 0>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
status = "disabled";
};
wdt0: watchdog@3ff5f048 {
compatible = "espressif,esp32-watchdog";
reg = <0x3ff5f048 0x20>;
- interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "okay";
@@ -347,7 +348,7 @@
wdt1: watchdog@3ff60048 {
compatible = "espressif,esp32-watchdog";
reg = <0x3ff60048 0x20>;
- interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
status = "disabled";
@@ -356,7 +357,7 @@
spi2: spi@3ff64000 {
compatible = "espressif,esp32-spi";
reg = <0x3ff64000 DT_SIZE_K(4)>;
- interrupts = <SPI2_INTR_SOURCE>;
+ interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_HSPI_MODULE>;
dma-clk = <ESP32_SPI_DMA_MODULE>;
@@ -367,7 +368,7 @@
spi3: spi@3ff65000 {
compatible = "espressif,esp32-spi";
reg = <0x3ff65000 DT_SIZE_K(4)>;
- interrupts = <SPI3_INTR_SOURCE>;
+ interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_VSPI_MODULE>;
dma-clk = <ESP32_SPI_DMA_MODULE>;
@@ -378,7 +379,7 @@
twai: can@3ff6b000 {
compatible = "espressif,esp32-twai";
reg = <0x3ff6b000 DT_SIZE_K(4)>;
- interrupts = <TWAI_INTR_SOURCE>;
+ interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TWAI_MODULE>;
status = "disabled";
@@ -389,7 +390,7 @@
reg = <0x3ff5f000 DT_SIZE_K(4)>;
group = <0>;
index = <0>;
- interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -399,7 +400,7 @@
reg = <0x3ff5f024 DT_SIZE_K(4)>;
group = <0>;
index = <1>;
- interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -409,7 +410,7 @@
reg = <0x3ff60000 DT_SIZE_K(4)>;
group = <1>;
index = <0>;
- interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -419,7 +420,7 @@
reg = <0x3ff60024 DT_SIZE_K(4)>;
group = <1>;
index = <1>;
- interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -427,7 +428,7 @@
dac: dac@3ff48800 {
compatible = "espressif,esp32-dac";
reg = <0x3ff48800 0x100>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SARADC_MODULE>;
#io-channel-cells = <1>;
@@ -455,7 +456,7 @@
sdhc: sdhc@3ff68000 {
compatible = "espressif,esp32-sdhc";
reg = <0x3ff68000 0x1000>;
- interrupts = <SDIO_HOST_INTR_SOURCE>;
+ interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SDMMC_MODULE>;
#address-cells = <1>;
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
index a855bd0..1c4d330 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
@@ -85,7 +85,7 @@
};
intc: interrupt-controller@3f4c2000 {
- #interrupt-cells = <1>;
+ #interrupt-cells = <3>;
compatible = "espressif,esp32-intc";
interrupt-controller;
reg = <0x3f4c2000 0x114>;
@@ -105,7 +105,7 @@
compatible = "espressif,esp32-xt-wdt";
reg = <0x3f408004 0x4>;
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -114,7 +114,7 @@
reg = <0x3f408004 0xC>;
compatible = "espressif,esp32-rtc-timer";
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "okay";
};
@@ -146,7 +146,7 @@
compatible = "espressif,esp32-uart";
reg = <0x3f400000 0x400>;
status = "disabled";
- interrupts = <UART0_INTR_SOURCE>;
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART0_MODULE>;
};
@@ -155,7 +155,7 @@
compatible = "espressif,esp32-uart";
reg = <0x3f410000 0x400>;
status = "disabled";
- interrupts = <UART1_INTR_SOURCE>;
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART1_MODULE>;
current-speed = <115200>;
@@ -164,7 +164,7 @@
pcnt: pcnt@3f417000 {
compatible = "espressif,esp32-pcnt";
reg = <0x3f417000 0x1000>;
- interrupts = <PCNT_INTR_SOURCE>;
+ interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PCNT_MODULE>;
status = "disabled";
@@ -184,7 +184,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x3f404000 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
/* Maximum available pins (per port)
* Actual occupied pins are specified
@@ -199,7 +199,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x3f404800 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
ngpios = <22>; /* 32..53 */
};
@@ -207,7 +207,7 @@
touch: touch@3f40885c {
compatible = "espressif,esp32-touch";
reg = <0x3f40885c 0xc0 0x3f408104 0x18>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -217,7 +217,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3f413000 0x1000>;
- interrupts = <I2C_EXT0_INTR_SOURCE>;
+ interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C0_MODULE>;
status = "disabled";
@@ -228,7 +228,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3f427000 0x1000>;
- interrupts = <I2C_EXT1_INTR_SOURCE>;
+ interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C1_MODULE>;
status = "disabled";
@@ -239,7 +239,7 @@
reg = <0x3f41f000 DT_SIZE_K(4)>;
group = <0>;
index = <0>;
- interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -249,7 +249,7 @@
reg = <0x3f41f024 DT_SIZE_K(4)>;
group = <0>;
index = <1>;
- interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -259,7 +259,7 @@
reg = <0x3f420000 DT_SIZE_K(4)>;
group = <1>;
index = <0>;
- interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -269,7 +269,7 @@
reg = <0x3f420024 DT_SIZE_K(4)>;
group = <1>;
index = <1>;
- interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
@@ -282,7 +282,7 @@
spi2: spi@3f424000 {
compatible = "espressif,esp32-spi";
reg = <0x3f424000 DT_SIZE_K(4)>;
- interrupts = <SPI2_INTR_SOURCE>;
+ interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_FSPI_MODULE>;
dma-clk = <ESP32_SPI2_DMA_MODULE>;
@@ -293,7 +293,7 @@
spi3: spi@3f425000 {
compatible = "espressif,esp32-spi";
reg = <0x3f425000 DT_SIZE_K(4)>;
- interrupts = <SPI3_INTR_SOURCE>;
+ interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_HSPI_MODULE>;
dma-clk = <ESP32_SPI3_DMA_MODULE>;
@@ -304,7 +304,7 @@
wdt0: watchdog@3f41f048 {
compatible = "espressif,esp32-watchdog";
reg = <0x3f41f048 0x20>;
- interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "disabled";
@@ -313,7 +313,7 @@
wdt1: watchdog@3f42f048 {
compatible = "espressif,esp32-watchdog";
reg = <0x3f42f048 0x20>;
- interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
status = "disabled";
@@ -322,7 +322,7 @@
dac: dac@3f408800 {
compatible = "espressif,esp32-dac";
reg = <0x3f408800 0x100>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PERIPH_SARADC_MODULE>;
#io-channel-cells = <1>;
@@ -356,7 +356,7 @@
twai: can@3f42b000 {
compatible = "espressif,esp32-twai";
reg = <0x3f42b000 DT_SIZE_K(4)>;
- interrupts = <TWAI_INTR_SOURCE>;
+ interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TWAI_MODULE>;
status = "disabled";
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
index 5d4f5b2..bd2fc58 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
@@ -102,7 +102,7 @@
};
intc: interrupt-controller@600c2000 {
- #interrupt-cells = <1>;
+ #interrupt-cells = <3>;
compatible = "espressif,esp32-intc";
interrupt-controller;
reg = <0x600c2000 0x1000>;
@@ -122,7 +122,7 @@
compatible = "espressif,esp32-xt-wdt";
reg = <0x60021004 0x4>;
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -131,7 +131,7 @@
reg = <0x60008004 0xC>;
compatible = "espressif,esp32-rtc-timer";
clocks = <&rtc ESP32_MODULE_MAX>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -139,8 +139,6 @@
flash: flash-controller@60002000 {
compatible = "espressif,esp32-flash-controller";
reg = <0x60002000 0x1000>;
- /* interrupts = <3 0>; */
-
#address-cells = <1>;
#size-cells = <1>;
@@ -167,7 +165,9 @@
status = "disabled";
shared-memory = <&ipmmem0>;
shared-memory-size = <0x400>;
- interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
+ interrupts =
+ <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
@@ -177,7 +177,9 @@
status = "disabled";
shared-memory = <&ipmmem0>;
shared-memory-size = <0x400>;
- interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
+ interrupts =
+ <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+ <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
#mbox-cells = <1>;
};
@@ -185,7 +187,7 @@
uart0: uart@60000000 {
compatible = "espressif,esp32-uart";
reg = <0x60000000 0x1000>;
- interrupts = <UART0_INTR_SOURCE>;
+ interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART0_MODULE>;
status = "disabled";
@@ -194,7 +196,7 @@
uart1: uart@60010000 {
compatible = "espressif,esp32-uart";
reg = <0x60010000 0x1000>;
- interrupts = <UART1_INTR_SOURCE>;
+ interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART1_MODULE>;
status = "disabled";
@@ -203,7 +205,7 @@
uart2: uart@6002e000 {
compatible = "espressif,esp32-uart";
reg = <0x6002e000 0x1000>;
- interrupts = <UART2_INTR_SOURCE>;
+ interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_UART2_MODULE>;
status = "disabled";
@@ -227,7 +229,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x60004000 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
/* Maximum available pins (per port)
* Actual occupied pins are specified
@@ -242,7 +244,7 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x60004800 0x800>;
- interrupts = <GPIO_INTR_SOURCE>;
+ interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
ngpios = <22>; /* 32..53 */
};
@@ -251,7 +253,7 @@
touch: touch@6000885c {
compatible = "espressif,esp32-touch";
reg = <0x6000885c 0x88 0x60008908 0x18>;
- interrupts = <RTC_CORE_INTR_SOURCE>;
+ interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -261,7 +263,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60013000 DT_SIZE_K(4)>;
- interrupts = <I2C_EXT0_INTR_SOURCE>;
+ interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C0_MODULE>;
status = "disabled";
@@ -272,7 +274,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60027000 DT_SIZE_K(4)>;
- interrupts = <I2C_EXT1_INTR_SOURCE>;
+ interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_I2C1_MODULE>;
status = "disabled";
@@ -281,7 +283,7 @@
spi2: spi@60024000 {
compatible = "espressif,esp32-spi";
reg = <0x60024000 DT_SIZE_K(4)>;
- interrupts = <SPI2_INTR_SOURCE>;
+ interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SPI2_MODULE>;
dma-clk = <ESP32_GDMA_MODULE>;
@@ -292,7 +294,7 @@
spi3: spi@60025000 {
compatible = "espressif,esp32-spi";
reg = <0x60025000 DT_SIZE_K(4)>;
- interrupts = <SPI3_INTR_SOURCE>;
+ interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_SPI3_MODULE>;
dma-clk = <ESP32_GDMA_MODULE>;
@@ -328,7 +330,7 @@
twai: can@6002b000 {
compatible = "espressif,esp32-twai";
reg = <0x6002b000 DT_SIZE_K(4)>;
- interrupts = <TWAI_INTR_SOURCE>;
+ interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TWAI_MODULE>;
status = "disabled";
@@ -338,7 +340,7 @@
compatible = "espressif,esp32-usb-serial";
reg = <0x60038000 DT_SIZE_K(4)>;
status = "disabled";
- interrupts = <USB_SERIAL_JTAG_INTR_SOURCE>;
+ interrupts = <USB_SERIAL_JTAG_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_USB_MODULE>;
};
@@ -348,7 +350,7 @@
reg = <0x6001f000 DT_SIZE_K(4)>;
group = <0>;
index = <0>;
- interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -358,7 +360,7 @@
reg = <0x6001f024 DT_SIZE_K(4)>;
group = <0>;
index = <1>;
- interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -368,7 +370,7 @@
reg = <0x60020000 DT_SIZE_K(4)>;
group = <1>;
index = <0>;
- interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
@@ -378,14 +380,14 @@
reg = <0x60020024 DT_SIZE_K(4)>;
group = <1>;
index = <1>;
- interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
};
wdt0: watchdog@6001f048 {
compatible = "espressif,esp32-watchdog";
reg = <0x6001f048 0x20>;
- interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG0_MODULE>;
status = "disabled";
@@ -394,7 +396,7 @@
wdt1: watchdog@60020048 {
compatible = "espressif,esp32-watchdog";
reg = <0x60020048 0x20>;
- interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
+ interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_TIMG1_MODULE>;
status = "disabled";
@@ -417,7 +419,7 @@
mcpwm0: mcpwm@6001e000 {
compatible = "espressif,esp32-mcpwm";
reg = <0x6001e000 DT_SIZE_K(4)>;
- interrupts = <PWM0_INTR_SOURCE>;
+ interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PWM0_MODULE>;
#pwm-cells = <3>;
@@ -427,7 +429,7 @@
mcpwm1: mcpwm@6002c000 {
compatible = "espressif,esp32-mcpwm";
reg = <0x6002c000 DT_SIZE_K(4)>;
- interrupts = <PWM1_INTR_SOURCE>;
+ interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PWM1_MODULE>;
#pwm-cells = <3>;
@@ -437,7 +439,7 @@
pcnt: pcnt@60017000 {
compatible = "espressif,esp32-pcnt";
reg = <0x60017000 DT_SIZE_K(4)>;
- interrupts = <PCNT_INTR_SOURCE>;
+ interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_PCNT_MODULE>;
status = "disabled";
@@ -447,9 +449,17 @@
compatible = "espressif,esp32-gdma";
reg = <0x6003f000 DT_SIZE_K(4)>;
#dma-cells = <1>;
- interrupts = <DMA_IN_CH0_INTR_SOURCE DMA_OUT_CH0_INTR_SOURCE
- DMA_IN_CH1_INTR_SOURCE DMA_OUT_CH1_INTR_SOURCE
- DMA_IN_CH2_INTR_SOURCE DMA_OUT_CH2_INTR_SOURCE>;
+ interrupts =
+ <DMA_IN_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_OUT_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_IN_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_OUT_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_IN_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_OUT_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_IN_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_OUT_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_IN_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
+ <DMA_OUT_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>;
interrupt-parent = <&intc>;
clocks = <&rtc ESP32_GDMA_MODULE>;
dma-channels = <10>;
@@ -457,5 +467,26 @@
status = "disabled";
};
+ sdhc: sdhc@60028000 {
+ compatible = "espressif,esp32-sdhc";
+ reg = <0x60028000 0x1000>;
+ interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+ interrupt-parent = <&intc>;
+ clocks = <&rtc ESP32_SDMMC_MODULE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sdhc0: sdhc@0 {
+ compatible = "espressif,esp32-sdhc-slot";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ sdhc1: sdhc@1 {
+ compatible = "espressif,esp32-sdhc-slot";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/include/zephyr/arch/arm/arch.h b/include/zephyr/arch/arm/arch.h
index 804e1d2..2da9e7f 100644
--- a/include/zephyr/arch/arm/arch.h
+++ b/include/zephyr/arch/arm/arch.h
@@ -19,9 +19,6 @@
/* Add include for DTS generated information */
#include <zephyr/devicetree.h>
-/* ARM GPRs are often designated by two different names */
-#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
-
#include <zephyr/arch/arm/thread.h>
#include <zephyr/arch/arm/exception.h>
#include <zephyr/arch/arm/irq.h>
diff --git a/include/zephyr/arch/arm/cortex_a_r/cmsis.h b/include/zephyr/arch/arm/cortex_a_r/cmsis.h
deleted file mode 100644
index e1e7071..0000000
--- a/include/zephyr/arch/arm/cortex_a_r/cmsis.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-#define ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-
-#include <cmsis_core.h>
-
-#warning This header is deprecated, please include <cmsis_core.h>
-
-#endif /* ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
diff --git a/include/zephyr/arch/arm/cortex_a_r/exception.h b/include/zephyr/arch/arm/cortex_a_r/exception.h
index cd8377b..8fcc6d0 100644
--- a/include/zephyr/arch/arm/cortex_a_r/exception.h
+++ b/include/zephyr/arch/arm/cortex_a_r/exception.h
@@ -54,6 +54,9 @@
};
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
+/* ARM GPRs are often designated by two different names */
+#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
+
struct arch_esf {
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
struct __extra_esf_info extra_info;
diff --git a/include/zephyr/arch/arm/cortex_m/cmsis.h b/include/zephyr/arch/arm/cortex_m/cmsis.h
deleted file mode 100644
index c16b008..0000000
--- a/include/zephyr/arch/arm/cortex_m/cmsis.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
-#define ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
-
-#include <cmsis_core.h>
-
-#warning This header is deprecated, please include <cmsis_core.h>
-
-#endif /* ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */
diff --git a/include/zephyr/arch/arm/cortex_m/exception.h b/include/zephyr/arch/arm/cortex_m/exception.h
index 2deed9b..6f60317 100644
--- a/include/zephyr/arch/arm/cortex_m/exception.h
+++ b/include/zephyr/arch/arm/cortex_m/exception.h
@@ -98,6 +98,9 @@
};
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
+/* ARM GPRs are often designated by two different names */
+#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
+
struct arch_esf {
struct __basic_sf {
sys_define_gpr_with_alias(a1, r0);
diff --git a/include/zephyr/arch/common/pm_s2ram.h b/include/zephyr/arch/common/pm_s2ram.h
index 451794a..34c544c 100644
--- a/include/zephyr/arch/common/pm_s2ram.h
+++ b/include/zephyr/arch/common/pm_s2ram.h
@@ -7,6 +7,7 @@
*
* @brief public S2RAM APIs.
* @defgroup pm_s2ram S2RAM APIs
+ * @ingroup subsys_pm
* @{
*/
diff --git a/include/zephyr/arch/xtensa/arch.h b/include/zephyr/arch/xtensa/arch.h
index c69f083..90614e7 100644
--- a/include/zephyr/arch/xtensa/arch.h
+++ b/include/zephyr/arch/xtensa/arch.h
@@ -45,6 +45,7 @@
/**
* @defgroup xtensa_apis Xtensa APIs
+ * @ingroup arch-interface
* @{
* @}
*
diff --git a/include/zephyr/bluetooth/audio/audio.h b/include/zephyr/bluetooth/audio/audio.h
index 3a82617..5826503 100644
--- a/include/zephyr/bluetooth/audio/audio.h
+++ b/include/zephyr/bluetooth/audio/audio.h
@@ -1554,7 +1554,7 @@
*
* @retval 0 if the flag was found
* @retval -EINVAL if arguments are invalid
- * @retval -ENODATA if not the flag was not found
+ * @retval -ENODATA if the flag was not found
*/
int bt_audio_codec_cfg_meta_get_bcast_audio_immediate_rend_flag(
const struct bt_audio_codec_cfg *codec_cfg);
diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h
index 9e8317b..f18c034 100644
--- a/include/zephyr/bluetooth/audio/bap.h
+++ b/include/zephyr/bluetooth/audio/bap.h
@@ -1158,8 +1158,10 @@
/**
* @brief Create audio unicast group.
*
- * Create a new audio unicast group with one or more audio streams as a unicast client. Streams in
- * a unicast group shall share the same interval, framing and latency (see @ref bt_audio_codec_qos).
+ * Create a new audio unicast group with one or more audio streams as a unicast client.
+ * All streams shall share the same framing.
+ * All streams in the same direction shall share the same interval and latency (see
+ * @ref bt_audio_codec_qos).
*
* @param[in] param The unicast group create parameters.
* @param[out] unicast_group Pointer to the unicast group created.
diff --git a/include/zephyr/bluetooth/audio/vcp.h b/include/zephyr/bluetooth/audio/vcp.h
index ae26112..0e07ec8 100644
--- a/include/zephyr/bluetooth/audio/vcp.h
+++ b/include/zephyr/bluetooth/audio/vcp.h
@@ -163,12 +163,14 @@
* bt_vcp_vol_rend_get_state(), or if the state is changed by either
* the Volume Renderer or a remote Volume Controller.
*
+ * @param conn Pointer to the connection to a remote device if
+ * the change was caused by it, otherwise NULL.
* @param err Error value. 0 on success, GATT error on positive value
* or errno on negative value.
* @param volume The volume of the Volume Control Service server.
* @param mute The mute setting of the Volume Control Service server.
*/
- void (*state)(int err, uint8_t volume, uint8_t mute);
+ void (*state)(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute);
/**
* @brief Callback function for Volume Control Service flags.
@@ -177,11 +179,13 @@
* Called when the value is remotely read as the client.
* Called if the value is changed by either the server or client.
*
+ * @param conn Pointer to the connection to a remote device if
+ * the change was caused by it, otherwise NULL.
* @param err Error value. 0 on success, GATT error on positive value
* or errno on negative value.
* @param flags The flags of the Volume Control Service server.
*/
- void (*flags)(int err, uint8_t flags);
+ void (*flags)(struct bt_conn *conn, int err, uint8_t flags);
};
/**
diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h
index 943dedb..1523a4f 100644
--- a/include/zephyr/bluetooth/bluetooth.h
+++ b/include/zephyr/bluetooth/bluetooth.h
@@ -2294,6 +2294,7 @@
*
* @return Zero on success or error code otherwise, positive in case of
* protocol error or negative (POSIX) in case of stack internal error.
+ * @retval -EBUSY if the scanner is already being started in a different thread.
*/
int bt_le_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb);
diff --git a/include/zephyr/bluetooth/byteorder.h b/include/zephyr/bluetooth/byteorder.h
index 8ac17da..d8432c5 100644
--- a/include/zephyr/bluetooth/byteorder.h
+++ b/include/zephyr/bluetooth/byteorder.h
@@ -107,6 +107,78 @@
BT_BYTES_LIST_LE32(_v), \
BT_BYTES_LIST_LE32((_v) >> 32) \
+/** @brief Encode 16-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 16-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 2 times.
+ *
+ * @param _v 16-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 16-bit value.
+ */
+#define BT_BYTES_LIST_BE16(_v) (((_v) >> 8) & 0xFFU), (((_v) >> 0) & 0xFFU)
+
+/** @brief Encode 24-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 24-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 3 times.
+ *
+ * @param _v 24-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 24-bit value.
+ */
+#define BT_BYTES_LIST_BE24(_v) (((_v) >> 16) & 0xFFU), BT_BYTES_LIST_BE16(_v)
+
+/** @brief Encode 32-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 32-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 4 times.
+ *
+ * @param _v 32-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 32-bit value.
+ */
+#define BT_BYTES_LIST_BE32(_v) (((_v) >> 24) & 0xFFU), BT_BYTES_LIST_BE24(_v)
+
+/** @brief Encode 40-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 40-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 5 times.
+ *
+ * @param _v 40-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 40-bit value.
+ */
+#define BT_BYTES_LIST_BE40(_v) BT_BYTES_LIST_BE16((_v) >> 24), BT_BYTES_LIST_BE24(_v)
+
+/** @brief Encode 48-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 48-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 6 times.
+ *
+ * @param _v 48-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 48-bit value.
+ */
+#define BT_BYTES_LIST_BE48(_v) BT_BYTES_LIST_BE16((_v) >> 32), BT_BYTES_LIST_BE32(_v)
+
+/** @brief Encode 64-bit value into array values in big-endian format.
+ *
+ * Helper macro to encode 64-bit values into comma separated values.
+ *
+ * @note @p _v is evaluated 8 times.
+ *
+ * @param _v 64-bit integer in host endianness.
+ *
+ * @return The comma separated values for the 64-bit value.
+ */
+#define BT_BYTES_LIST_BE64(_v) BT_BYTES_LIST_BE32((_v) >> 32), BT_BYTES_LIST_BE32(_v)
+
/**
* @}
*/
diff --git a/include/zephyr/bluetooth/gatt.h b/include/zephyr/bluetooth/gatt.h
index 78a6aab..347dba3 100644
--- a/include/zephyr/bluetooth/gatt.h
+++ b/include/zephyr/bluetooth/gatt.h
@@ -130,10 +130,25 @@
/** @typedef bt_gatt_attr_read_func_t
* @brief Attribute read callback
*
- * The callback can also be used locally to read the contents of the
- * attribute in which case no connection will be set.
+ * This is the type of the bt_gatt_attr.read() method.
*
- * @param conn The connection that is requesting to read
+ * This function may safely assume the Attribute Permissions
+ * are satisfied for this read. Callers are responsible for
+ * this.
+ *
+ * Callers may set @p conn to emulate a GATT client read, or
+ * leave it NULL for local reads.
+ *
+ * @note GATT server relies on this method to handle read
+ * operations from remote GATT clients. But this method is not
+ * reserved for the GATT server. E.g. You can lookup attributes
+ * in the local ATT database and invoke this method.
+ *
+ * @note The GATT server propagates the return value from this
+ * method back to the remote client.
+ *
+ * @param conn The connection that is requesting to read.
+ * NULL if local.
* @param attr The attribute that's being read
* @param buf Buffer to place the read result in
* @param len Length of data to read
@@ -148,7 +163,32 @@
uint16_t offset);
/** @typedef bt_gatt_attr_write_func_t
- * @brief Attribute write callback
+ * @brief Attribute Value write implementation
+ *
+ * This is the type of the bt_gatt_attr.write() method.
+ *
+ * This function may safely assume the Attribute Permissions
+ * are satisfied for this write. Callers are responsible for
+ * this.
+ *
+ * Callers may set @p conn to emulate a GATT client write, or
+ * leave it NULL for local writes.
+ *
+ * If @p flags contains @ref BT_GATT_WRITE_FLAG_PREPARE, then
+ * the method shall not perform a write, but instead only check
+ * if the write is authorized and return an error code if not.
+ *
+ * Attribute Value write implementations can and often do have
+ * side effects besides potentially storing the value. E.g.
+ * togging an LED.
+ *
+ * @note GATT server relies on this method to handle write
+ * operations from remote GATT clients. But this method is not
+ * reserved for the GATT server. E.g. You can lookup attributes
+ * in the local ATT database and invoke this method.
+ *
+ * @note The GATT server propagates the return value from this
+ * method back to the remote client.
*
* @param conn The connection that is requesting to write
* @param attr The attribute that's being written
@@ -165,21 +205,97 @@
const void *buf, uint16_t len,
uint16_t offset, uint8_t flags);
-/** @brief GATT Attribute structure. */
+/** @brief GATT Attribute
+ *
+ * This type primarily represents an ATT Attribute that may be
+ * an entry in the local ATT database. The objects of this type
+ * must be part of an array that forms a GATT service.
+ *
+ * While the formed GATT service is registered with the local
+ * GATT server, pointers to this type can typically be given to
+ * GATT server APIs, like bt_gatt_notify().
+ *
+ * @note This type is given as an argument to the
+ * bt_gatt_discover() application callback, but it's not a
+ * proper object of this type. The field @ref perm, and methods
+ * read() and write() are not available, and it's unsound to
+ * pass the pointer to GATT server APIs.
+ */
struct bt_gatt_attr {
- /** Attribute UUID */
- const struct bt_uuid *uuid;
- /** Attribute read callback */
- bt_gatt_attr_read_func_t read;
- /** Attribute write callback */
- bt_gatt_attr_write_func_t write;
- /** Attribute user data */
- void *user_data;
- /** Attribute handle */
- uint16_t handle;
- /** @brief Attribute permissions.
+ /** @brief Attribute Type, aka. "UUID"
*
- * Will be 0 if returned from ``bt_gatt_discover()``.
+ * The Attribute Type determines the interface that can
+ * be expected from the read() and write() methods and
+ * the possible permission configurations.
+ *
+ * E.g. Attribute of type @ref BT_UUID_GATT_CPF will act as a
+ * GATT Characteristic Presentation Format descriptor as
+ * specified in Core Specification 3.G.3.3.3.5.
+ *
+ * You can define a new Attribute Type.
+ */
+ const struct bt_uuid *uuid;
+
+ /** @brief Attribute Value read method
+ *
+ * Readable Attributes must implement this method.
+ *
+ * Must be NULL if the attribute is not readable.
+ *
+ * The behavior of this method is determined by the Attribute
+ * Type.
+ *
+ * See @ref bt_gatt_attr_read_func_t.
+ */
+ bt_gatt_attr_read_func_t read;
+
+ /** @brief Attribute Value write method
+ *
+ * Writeable Attributes must implement this method.
+ *
+ * Must be NULL if the attribute is not writable.
+ *
+ * The behavior of this method is determined by the Attribute
+ * Type.
+ *
+ * See @ref bt_gatt_attr_write_func_t.
+ */
+ bt_gatt_attr_write_func_t write;
+
+ /** @brief Private data for read() and write() implementation
+ *
+ * The meaning of this field varies and is not specified here.
+ *
+ * @note Attributes may have the same Attribute Type but have
+ * different implementations, with incompatible user data.
+ * Attribute Type alone must not be used to infer the type of
+ * the user data.
+ *
+ * @sa bt_gatt_discover_func_t about this field.
+ */
+ void *user_data;
+
+ /** @brief Attribute Handle or zero, maybe?
+ *
+ * The meaning of this field varies and is not specified here.
+ * Some APIs use this field as input/output. It does not always
+ * contain the Attribute Handle.
+ *
+ * @note Use bt_gatt_attr_get_handle() for attributes in the
+ * local ATT database.
+ *
+ * @sa bt_gatt_discover_func_t about this field.
+ */
+ uint16_t handle;
+
+ /** @brief Attribute Permissions
+ *
+ * Bit field of @ref bt_gatt_perm.
+ *
+ * The permissions are security requirements that must be
+ * satisfied before calling read() or write().
+ *
+ * @sa bt_gatt_discover_func_t about this field.
*/
uint16_t perm;
};
@@ -578,7 +694,8 @@
/** @brief Get Attribute handle.
*
- * @param attr Attribute object.
+ * @param attr An attribute object currently registered in the
+ * local ATT server.
*
* @return Handle of the corresponding attribute or zero if the attribute
* could not be found.
@@ -1371,6 +1488,23 @@
*/
uint16_t bt_gatt_get_mtu(struct bt_conn *conn);
+/** @brief Get Unenhanced ATT (UATT) MTU for a connection
+ *
+ * Get UATT connection MTU.
+ *
+ * The ATT_MTU defines the largest size of an ATT PDU, encompassing the ATT
+ * opcode, additional fields, and any attribute value payload. Consequently,
+ * the maximum size of a value payload is less and varies based on the type
+ * of ATT PDU. For example, in an ATT_HANDLE_VALUE_NTF PDU, the Attribute Value
+ * field can contain up to ATT_MTU - 3 octets (size of opcode and handle).
+ *
+ * @param conn Connection object.
+ *
+ * @return 0 if @p conn does not have an UATT ATT_MTU (e.g: disconnected).
+ * @return Current UATT ATT_MTU.
+ */
+uint16_t bt_gatt_get_uatt_mtu(struct bt_conn *conn);
+
/** @} */
/**
diff --git a/include/zephyr/bluetooth/l2cap.h b/include/zephyr/bluetooth/l2cap.h
index 064b974..0117da5 100644
--- a/include/zephyr/bluetooth/l2cap.h
+++ b/include/zephyr/bluetooth/l2cap.h
@@ -272,7 +272,10 @@
struct k_fifo _pdu_tx_queue;
};
-/** @brief L2CAP Channel operations structure. */
+/** @brief L2CAP Channel operations structure.
+ *
+ * The object has to stay valid and constant for the lifetime of the channel.
+ */
struct bt_l2cap_chan_ops {
/** @brief Channel connected callback
*
@@ -342,6 +345,10 @@
* @param chan The channel receiving data.
* @param buf Buffer containing incoming data.
*
+ * @note This callback is mandatory, unless
+ * @kconfig{CONFIG_BT_L2CAP_SEG_RECV} is enabled and seg_recv is
+ * supplied.
+ *
* @return 0 in case of success or negative value in case of error.
* @return -EINPROGRESS in case where user has to confirm once the data
* has been processed by calling
@@ -462,6 +469,9 @@
* This callback is called whenever a new incoming connection requires
* authorization.
*
+ * @warning It is the responsibility of this callback to zero out the
+ * parent of the chan object.
+ *
* @param conn The connection that is requesting authorization
* @param server Pointer to the server structure this callback relates to
* @param chan Pointer to received the allocated channel
@@ -516,6 +526,9 @@
* each channel connected() callback will be called. If the connection is
* rejected disconnected() callback is called instead.
*
+ * @warning It is the responsibility of the caller to zero out the
+ * parents of the chan objects.
+ *
* @param conn Connection object.
* @param chans Array of channel objects.
* @param psm Channel PSM to connect to.
@@ -551,6 +564,9 @@
* the location (address) of bt_l2cap_chan type object which is a member
* of both transport dedicated objects.
*
+ * @warning It is the responsibility of the caller to zero out the
+ * parent of the chan object.
+ *
* @param conn Connection object.
* @param chan Channel object.
* @param psm Channel PSM to connect to.
diff --git a/include/zephyr/bluetooth/mesh/blob_srv.h b/include/zephyr/bluetooth/mesh/blob_srv.h
index 92c809b..8a0c6b6 100644
--- a/include/zephyr/bluetooth/mesh/blob_srv.h
+++ b/include/zephyr/bluetooth/mesh/blob_srv.h
@@ -127,7 +127,7 @@
const struct bt_mesh_blob_io **io);
};
-/** @brief BLOB Transfer Server instance. */
+/** @brief BLOB Transfer Server model instance. */
struct bt_mesh_blob_srv {
/** Event handler callbacks. */
const struct bt_mesh_blob_srv_cb *cb;
diff --git a/include/zephyr/bluetooth/services/bas.h b/include/zephyr/bluetooth/services/bas.h
index 5941334..67932d4 100644
--- a/include/zephyr/bluetooth/services/bas.h
+++ b/include/zephyr/bluetooth/services/bas.h
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2024 Demant A/S
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2016 Intel Corporation
*
@@ -19,11 +20,173 @@
*/
#include <stdint.h>
+#include <zephyr/sys/util.h>
#ifdef __cplusplus
extern "C" {
#endif
+/**
+ * @brief Battery Level Status Characteristic flags.
+ *
+ * Enumeration for the flags indicating the presence
+ * of various fields in the Battery Level Status characteristic.
+ */
+enum bt_bas_bls_flags {
+ /** Bit indicating that the Battery Level Status identifier is present. */
+ BT_BAS_BLS_FLAG_IDENTIFIER_PRESENT = BIT(0),
+
+ /** Bit indicating that the Battery Level is present. */
+ BT_BAS_BLS_FLAG_BATTERY_LEVEL_PRESENT = BIT(1),
+
+ /** Bit indicating that additional status information is present. */
+ BT_BAS_BLS_FLAG_ADDITIONAL_STATUS_PRESENT = BIT(2),
+};
+
+/** @brief Battery Present Status
+ *
+ * Enumeration for the presence of the battery.
+ */
+enum bt_bas_bls_battery_present {
+ /** Battery is not present. */
+ BT_BAS_BLS_BATTERY_NOT_PRESENT = 0,
+
+ /** Battery is present. */
+ BT_BAS_BLS_BATTERY_PRESENT = 1
+};
+
+/** @brief Wired External Power Source Status
+ *
+ * Enumeration for the status of the wired external power source.
+ */
+enum bt_bas_bls_wired_power_source {
+ /** Wired external power source is not connected. */
+ BT_BAS_BLS_WIRED_POWER_NOT_CONNECTED = 0,
+
+ /** Wired external power source is connected. */
+ BT_BAS_BLS_WIRED_POWER_CONNECTED = 1,
+
+ /** Wired external power source status is unknown. */
+ BT_BAS_BLS_WIRED_POWER_UNKNOWN = 2
+};
+
+/** @brief Wireless External Power Source Status
+ *
+ * Enumeration for the status of the wireless external power source.
+ */
+enum bt_bas_bls_wireless_power_source {
+ /** Wireless external power source is not connected. */
+ BT_BAS_BLS_WIRELESS_POWER_NOT_CONNECTED = 0,
+
+ /** Wireless external power source is connected. */
+ BT_BAS_BLS_WIRELESS_POWER_CONNECTED = 1,
+
+ /** Wireless external power source status is unknown. */
+ BT_BAS_BLS_WIRELESS_POWER_UNKNOWN = 2
+};
+
+/** @brief Battery Charge State
+ *
+ * Enumeration for the charge state of the battery.
+ */
+enum bt_bas_bls_battery_charge_state {
+ /** Battery charge state is unknown. */
+ BT_BAS_BLS_CHARGE_STATE_UNKNOWN = 0,
+
+ /** Battery is currently charging. */
+ BT_BAS_BLS_CHARGE_STATE_CHARGING = 1,
+
+ /** Battery is discharging actively. */
+ BT_BAS_BLS_CHARGE_STATE_DISCHARGING_ACTIVE = 2,
+
+ /** Battery is discharging but inactive. */
+ BT_BAS_BLS_CHARGE_STATE_DISCHARGING_INACTIVE = 3
+};
+
+/** @brief Battery Charge Level
+ *
+ * Enumeration for the level of charge in the battery.
+ */
+enum bt_bas_bls_battery_charge_level {
+ /** Battery charge level is unknown. */
+ BT_BAS_BLS_CHARGE_LEVEL_UNKNOWN = 0,
+
+ /** Battery charge level is good. */
+ BT_BAS_BLS_CHARGE_LEVEL_GOOD = 1,
+
+ /** Battery charge level is low. */
+ BT_BAS_BLS_CHARGE_LEVEL_LOW = 2,
+
+ /** Battery charge level is critical. */
+ BT_BAS_BLS_CHARGE_LEVEL_CRITICAL = 3
+};
+
+/** @brief Battery Charge Type
+ *
+ * Enumeration for the type of charging applied to the battery.
+ */
+enum bt_bas_bls_battery_charge_type {
+ /** Battery charge type is unknown or not charging. */
+ BT_BAS_BLS_CHARGE_TYPE_UNKNOWN = 0,
+
+ /** Battery is charged using constant current. */
+ BT_BAS_BLS_CHARGE_TYPE_CONSTANT_CURRENT = 1,
+
+ /** Battery is charged using constant voltage. */
+ BT_BAS_BLS_CHARGE_TYPE_CONSTANT_VOLTAGE = 2,
+
+ /** Battery is charged using trickle charge. */
+ BT_BAS_BLS_CHARGE_TYPE_TRICKLE = 3,
+
+ /** Battery is charged using float charge. */
+ BT_BAS_BLS_CHARGE_TYPE_FLOAT = 4
+};
+
+/** @brief Charging Fault Reason
+ *
+ * Enumeration for the reasons of charging faults.
+ */
+enum bt_bas_bls_charging_fault_reason {
+ /** No charging fault. */
+ BT_BAS_BLS_FAULT_REASON_NONE = 0,
+
+ /** Charging fault due to battery issue. */
+ BT_BAS_BLS_FAULT_REASON_BATTERY = BIT(0),
+
+ /** Charging fault due to external power source issue. */
+ BT_BAS_BLS_FAULT_REASON_EXTERNAL_POWER = BIT(1),
+
+ /** Charging fault for other reasons. */
+ BT_BAS_BLS_FAULT_REASON_OTHER = BIT(2)
+};
+
+/** @brief Service Required Status
+ *
+ * Enumeration for whether the service is required.
+ */
+enum bt_bas_bls_service_required {
+ /** Service is not required. */
+ BT_BAS_BLS_SERVICE_REQUIRED_FALSE = 0,
+
+ /** Service is required. */
+ BT_BAS_BLS_SERVICE_REQUIRED_TRUE = 1,
+
+ /** Service requirement is unknown. */
+ BT_BAS_BLS_SERVICE_REQUIRED_UNKNOWN = 2
+};
+
+/** @brief Battery Fault Status
+ *
+ * Enumeration for the fault status of the battery.
+ */
+enum bt_bas_bls_battery_fault {
+ /** No battery fault. */
+ BT_BAS_BLS_BATTERY_FAULT_NO = 0,
+
+ /** Battery fault present. */
+ BT_BAS_BLS_BATTERY_FAULT_YES = 1
+};
+
/** @brief Read battery level value.
*
* Read the characteristic value of the battery level
@@ -43,6 +206,81 @@
*/
int bt_bas_set_battery_level(uint8_t level);
+/**
+ * @brief Set the battery present status.
+ *
+ * @param present The battery present status to set.
+ */
+void bt_bas_bls_set_battery_present(enum bt_bas_bls_battery_present present);
+
+/**
+ * @brief Set the wired external power source status.
+ *
+ * @param source The wired external power source status to set.
+ */
+void bt_bas_bls_set_wired_external_power_source(enum bt_bas_bls_wired_power_source source);
+
+/**
+ * @brief Set the wireless external power source status.
+ *
+ * @param source The wireless external power source status to set.
+ */
+void bt_bas_bls_set_wireless_external_power_source(enum bt_bas_bls_wireless_power_source source);
+
+/**
+ * @brief Set the battery charge state.
+ *
+ * @param state The battery charge state to set.
+ */
+void bt_bas_bls_set_battery_charge_state(enum bt_bas_bls_battery_charge_state state);
+
+/**
+ * @brief Set the battery charge level.
+ *
+ * @param level The battery charge level to set.
+ */
+void bt_bas_bls_set_battery_charge_level(enum bt_bas_bls_battery_charge_level level);
+
+/**
+ * @brief Set the battery charge type.
+ *
+ * @param type The battery charge type to set.
+ */
+void bt_bas_bls_set_battery_charge_type(enum bt_bas_bls_battery_charge_type type);
+
+/**
+ * @brief Set the charging fault reason.
+ *
+ * @param reason The charging fault reason to set.
+ */
+void bt_bas_bls_set_charging_fault_reason(enum bt_bas_bls_charging_fault_reason reason);
+
+/**
+ * @brief Set the identifier of the battery.
+ *
+ * kconfig_dep{CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT}
+ *
+ * @param identifier Identifier to set.
+ */
+void bt_bas_bls_set_identifier(uint16_t identifier);
+
+/**
+ * @brief Set the service required status.
+ *
+ * kconfig_dep{CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT}
+ *
+ * @param value Service required status to set.
+ */
+void bt_bas_bls_set_service_required(enum bt_bas_bls_service_required value);
+
+/**
+ * @brief Set the battery fault status.
+ *
+ * kconfig_dep{CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT}
+ *
+ * @param value Battery fault status to set.
+ */
+void bt_bas_bls_set_battery_fault(enum bt_bas_bls_battery_fault value);
#ifdef __cplusplus
}
diff --git a/include/zephyr/data/json.h b/include/zephyr/data/json.h
index f140a8b..a93eb42 100644
--- a/include/zephyr/data/json.h
+++ b/include/zephyr/data/json.h
@@ -42,6 +42,7 @@
JSON_TOK_OPAQUE = '2',
JSON_TOK_OBJ_ARRAY = '3',
JSON_TOK_ENCODED_OBJ = '4',
+ JSON_TOK_INT64 = '5',
JSON_TOK_TRUE = 't',
JSON_TOK_FALSE = 'f',
JSON_TOK_NULL = 'n',
diff --git a/include/zephyr/device.h b/include/zephyr/device.h
index cc72cb1..52b8604 100644
--- a/include/zephyr/device.h
+++ b/include/zephyr/device.h
@@ -1075,24 +1075,16 @@
Z_DEVICE_SECTION_NAME(level, prio), DEVICE_NAME_GET(dev_id)) = \
Z_DEVICE_INIT(name, pm, data, config, api, state, deps, node_id, dev_id)
-/* deprecated device initialization levels */
-#define Z_DEVICE_LEVEL_DEPRECATED_EARLY \
- __WARN("EARLY device driver level is deprecated")
-#define Z_DEVICE_LEVEL_DEPRECATED_PRE_KERNEL_1
-#define Z_DEVICE_LEVEL_DEPRECATED_PRE_KERNEL_2
-#define Z_DEVICE_LEVEL_DEPRECATED_POST_KERNEL
-#define Z_DEVICE_LEVEL_DEPRECATED_APPLICATION \
- __WARN("APPLICATION device driver level is deprecated")
-#define Z_DEVICE_LEVEL_DEPRECATED_SMP \
- __WARN("SMP device driver level is deprecated")
-
/**
- * @brief Issue a warning if the given init level is deprecated.
+ * @brief Issue an error if the given init level is not supported.
*
* @param level Init level
*/
-#define Z_DEVICE_LEVEL_CHECK_DEPRECATED_LEVEL(level) \
- Z_DEVICE_LEVEL_DEPRECATED_##level
+#define Z_DEVICE_CHECK_INIT_LEVEL(level) \
+ COND_CODE_1(Z_INIT_PRE_KERNEL_1_##level, (), \
+ (COND_CODE_1(Z_INIT_PRE_KERNEL_2_##level, (), \
+ (COND_CODE_1(Z_INIT_POST_KERNEL_##level, (), \
+ (ZERO_OR_COMPILE_ERROR(0)))))))
/**
* @brief Define the init entry for a device.
@@ -1105,7 +1097,7 @@
* @param prio Initialization priority.
*/
#define Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn_, level, prio) \
- Z_DEVICE_LEVEL_CHECK_DEPRECATED_LEVEL(level) \
+ Z_DEVICE_CHECK_INIT_LEVEL(level) \
\
static const Z_DECL_ALIGN(struct init_entry) __used __noasan Z_INIT_ENTRY_SECTION( \
level, prio, Z_DEVICE_INIT_SUB_PRIO(node_id)) \
diff --git a/include/zephyr/drivers/clock_control/esp32_clock_control.h b/include/zephyr/drivers/clock_control/esp32_clock_control.h
index aa83d78..eb6bebc 100644
--- a/include/zephyr/drivers/clock_control/esp32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/esp32_clock_control.h
@@ -13,6 +13,8 @@
#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
+#elif defined(CONFIG_SOC_SERIES_ESP32C2)
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
#elif defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
diff --git a/include/zephyr/drivers/dai.h b/include/zephyr/drivers/dai.h
index e5f6c97..7af4157 100644
--- a/include/zephyr/drivers/dai.h
+++ b/include/zephyr/drivers/dai.h
@@ -477,8 +477,9 @@
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
- if (!api->ts_config)
+ if (!api->ts_config) {
return -EINVAL;
+ }
return api->ts_config(dev, cfg);
}
@@ -496,8 +497,9 @@
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
- if (!api->ts_start)
+ if (!api->ts_start) {
return -EINVAL;
+ }
return api->ts_start(dev, cfg);
}
@@ -515,8 +517,9 @@
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
- if (!api->ts_stop)
+ if (!api->ts_stop) {
return -EINVAL;
+ }
return api->ts_stop(dev, cfg);
}
@@ -536,8 +539,9 @@
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
- if (!api->ts_get)
+ if (!api->ts_get) {
return -EINVAL;
+ }
return api->ts_get(dev, cfg, tsd);
}
diff --git a/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h b/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h
index 1ec5ada..0d85c07 100644
--- a/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h
+++ b/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h
@@ -11,7 +11,7 @@
#include <zephyr/drivers/clock_control.h>
/* Different platforms named the peripheral different in the register definitions */
-#ifdef CONFIG_SOC_FAMILY_NXP_MCX
+#ifdef CONFIG_SOC_SERIES_MCXN
#undef ENET
#define ENET_QOS_NAME ENET
#define ENET_QOS_ALIGNMENT 4
diff --git a/include/zephyr/drivers/firmware/scmi/clk.h b/include/zephyr/drivers/firmware/scmi/clk.h
new file mode 100644
index 0000000..e56fc9d
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/clk.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI clock protocol helpers
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_
+
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+
+#define SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK GENMASK(1, 0)
+#define SCMI_CLK_CONFIG_ENABLE_DISABLE(x)\
+ ((uint32_t)(x) & SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK)
+
+#define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0))
+
+/**
+ * @struct scmi_clock_config
+ *
+ * @brief Describes the parameters for the CLOCK_CONFIG_SET
+ * command
+ */
+struct scmi_clock_config {
+ uint32_t clk_id;
+ uint32_t attributes;
+ uint32_t extended_cfg_val;
+};
+
+/**
+ * @brief Clock protocol command message IDs
+ */
+enum scmi_clock_message {
+ SCMI_CLK_MSG_PROTOCOL_VERSION = 0x0,
+ SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES = 0x1,
+ SCMI_CLK_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
+ SCMI_CLK_MSG_CLOCK_ATTRIBUTES = 0x3,
+ SCMI_CLK_MSG_CLOCK_DESCRIBE_RATES = 0x4,
+ SCMI_CLK_MSG_CLOCK_RATE_SET = 0x5,
+ SCMI_CLK_MSG_CLOCK_RATE_GET = 0x6,
+ SCMI_CLK_MSG_CLOCK_CONFIG_SET = 0x7,
+ SCMI_CLK_MSG_CLOCK_NAME_GET = 0x8,
+ SCMI_CLK_MSG_CLOCK_RATE_NOTIFY = 0x9,
+ SCMI_CLK_MSG_CLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 0xa,
+ SCMI_CLK_MSG_CLOCK_CONFIG_GET = 0xb,
+ SCMI_CLK_MSG_CLOCK_POSSIBLE_PARENTS_GET = 0xc,
+ SCMI_CLK_MSG_CLOCK_PARENT_SET = 0xd,
+ SCMI_CLK_MSG_CLOCK_PARENT_GET = 0xe,
+ SCMI_CLK_MSG_CLOCK_GET_PERMISSIONS = 0xf,
+ SCMI_CLK_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
+};
+
+/**
+ * @brief Send the PROTOCOL_ATTRIBUTES command and get its reply
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param attributes pointer to attributes to be set via
+ * this command
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_protocol_attributes(struct scmi_protocol *proto,
+ uint32_t *attributes);
+
+/**
+ * @brief Send the CLOCK_CONFIG_SET command and get its reply
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param cfg pointer to structure containing configuration
+ * to be set
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_config_set(struct scmi_protocol *proto,
+ struct scmi_clock_config *cfg);
+/**
+ * @brief Query the rate of a clock
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param clk_id ID of the clock for which the query is done
+ * @param rate pointer to rate to be set via this command
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_rate_get(struct scmi_protocol *proto,
+ uint32_t clk_id, uint32_t *rate);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/pinctrl.h b/include/zephyr/drivers/firmware/scmi/pinctrl.h
new file mode 100644
index 0000000..3906b91
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/pinctrl.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI pinctrl protocol helpers
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_
+
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+
+#define ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE (10 * 2)
+
+#define SCMI_PINCTRL_NO_FUNCTION 0xFFFFFFFF
+
+#define SCMI_PINCTRL_CONFIG_ATTRIBUTES(fid_valid, cfg_num, selector) \
+ (SCMI_FIELD_MAKE(fid_valid, BIT(1), 10) | \
+ SCMI_FIELD_MAKE(cfg_num, GENMASK(7, 0), 2) | \
+ SCMI_FIELD_MAKE(selector, GENMASK(1, 0), 0))
+
+#define SCMI_PINCTRL_SELECTOR_PIN 0x0
+#define SCMI_PINCTRL_SELECTOR_GROUP 0x1
+
+#define SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(attributes)\
+ (((attributes) & GENMASK(9, 2)) >> 2)
+
+/**
+ * @brief Pinctrl protocol command message IDs
+ */
+enum scmi_pinctrl_message {
+ SCMI_PINCTRL_MSG_PROTOCOL_VERSION = 0x0,
+ SCMI_PINCTRL_MSG_PROTOCOL_ATTRIBUTES = 0x1,
+ SCMI_PINCTRL_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
+ SCMI_PINCTRL_MSG_PINCTRL_ATTRIBUTES = 0x3,
+ SCMI_PINCTRL_MSG_PINCTRL_LIST_ASSOCIATIONS = 0x4,
+ SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_GET = 0x5,
+ SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_CONFIGURE = 0x6,
+ SCMI_PINCTRL_MSG_PINCTRL_REQUEST = 0x7,
+ SCMI_PINCTRL_MSG_PINCTRL_RELEASE = 0x8,
+ SCMI_PINCTRL_MSG_PINCTRL_NAME_GET = 0x9,
+ SCMI_PINCTRL_MSG_PINCTRL_SET_PERMISSIONS = 0xa,
+ SCMI_PINCTRL_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
+};
+
+/**
+ * @brief Pinctrl configurations
+ */
+enum scmi_pinctrl_config {
+ SCMI_PINCTRL_DEFAULT = 0,
+ SCMI_PINCTRL_BIAS_BUS_HOLD = 1,
+ SCMI_PINCTRL_BIAS_DISABLE = 2,
+ SCMI_PINCTRL_BIAS_HIGH_Z = 3,
+ SCMI_PINCTRL_BIAS_PULL_UP = 4,
+ SCMI_PINCTRL_BIAS_PULL_DEFAULT = 5,
+ SCMI_PINCTRL_BIAS_PULL_DOWN = 6,
+ SCMI_PINCTRL_DRIVE_OPEN_DRAIN = 7,
+ SCMI_PINCTRL_DRIVE_OPEN_SOURCE = 8,
+ SCMI_PCINTRL_DRIVE_PUSH_PULL = 9,
+ SCMI_PCINTRL_DRIVE_STRENGTH = 10,
+ SCMI_PINCTRL_INPUT_DEBOUNCE = 11,
+ SCMI_PINCTRL_INPUT_MODE = 12,
+ SCMI_PINCTRL_PULL_MODE = 13,
+ SCMI_PINCTRL_INPUT_VALUE = 14,
+ SCMI_PINCTRL_INPUT_SCHMITT = 15,
+ SCMI_PINCTRL_LP_MODE = 16,
+ SCMI_PINCTRL_OUTPUT_MODE = 17,
+ SCMI_PINCTRL_OUTPUT_VALUE = 18,
+ SCMI_PINCTRL_POWER_SOURCE = 19,
+ SCMI_PINCTRL_SLEW_RATE = 20,
+ SCMI_PINCTRL_RESERVED_START = 21,
+ SCMI_PINCTRL_RESERVED_END = 191,
+ SCMI_PINCTRL_VENDOR_START = 192,
+};
+
+/**
+ * @struct scmi_pinctrl_settings
+ *
+ * @brief Describes the parameters for the PINCTRL_SETTINGS_CONFIGURE
+ * command
+ */
+struct scmi_pinctrl_settings {
+ uint32_t id;
+ uint32_t function;
+ uint32_t attributes;
+ uint32_t config[ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE];
+};
+
+/**
+ * @brief Send the PINCTRL_SETTINGS_CONFIGURE command and get its reply
+ *
+ * @param settings pointer to settings to be applied
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/protocol.h b/include/zephyr/drivers/firmware/scmi/protocol.h
new file mode 100644
index 0000000..13ac8ba
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/protocol.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI protocol generic functions and structures
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/firmware/scmi/util.h>
+#include <stdint.h>
+#include <errno.h>
+
+/**
+ * @brief Build an SCMI message header
+ *
+ * Builds an SCMI message header based on the
+ * fields that make it up.
+ *
+ * @param id message ID
+ * @param type message type
+ * @param proto protocol ID
+ * @param token message token
+ */
+#define SCMI_MESSAGE_HDR_MAKE(id, type, proto, token) \
+ (SCMI_FIELD_MAKE(id, GENMASK(7, 0), 0) | \
+ SCMI_FIELD_MAKE(type, GENMASK(1, 0), 8) | \
+ SCMI_FIELD_MAKE(proto, GENMASK(7, 0), 10) | \
+ SCMI_FIELD_MAKE(token, GENMASK(9, 0), 18))
+
+struct scmi_channel;
+
+/**
+ * @brief SCMI message type
+ */
+enum scmi_message_type {
+ /** command message */
+ SCMI_COMMAND = 0x0,
+ /** delayed reply message */
+ SCMI_DELAYED_REPLY = 0x2,
+ /** notification message */
+ SCMI_NOTIFICATION = 0x3,
+};
+
+/**
+ * @brief SCMI status codes
+ */
+enum scmi_status_code {
+ SCMI_SUCCESS = 0,
+ SCMI_NOT_SUPPORTED = -1,
+ SCMI_INVALID_PARAMETERS = -2,
+ SCMI_DENIED = -3,
+ SCMI_NOT_FOUND = -4,
+ SCMI_OUT_OF_RANGE = -5,
+ SCMI_BUSY = -6,
+ SCMI_COMMS_ERROR = -7,
+ SCMI_GENERIC_ERROR = -8,
+ SCMI_HARDWARE_ERROR = -9,
+ SCMI_PROTOCOL_ERROR = -10,
+ SCMI_IN_USE = -11,
+};
+
+/**
+ * @struct scmi_protocol
+ *
+ * @brief SCMI protocol structure
+ */
+struct scmi_protocol {
+ /** protocol ID */
+ uint32_t id;
+ /** TX channel */
+ struct scmi_channel *tx;
+ /** transport layer device */
+ const struct device *transport;
+ /** protocol private data */
+ void *data;
+};
+
+/**
+ * @struct scmi_message
+ *
+ * @brief SCMI message structure
+ */
+struct scmi_message {
+ uint32_t hdr;
+ uint32_t len;
+ void *content;
+};
+
+/**
+ * @brief Convert an SCMI status code to its Linux equivalent (if possible)
+ *
+ * @param scmi_status SCMI status code as shown in `enum scmi_status_code`
+ *
+ * @retval Linux equivalent status code
+ */
+int scmi_status_to_errno(int scmi_status);
+
+/**
+ * @brief Send an SCMI message and wait for its reply
+ *
+ * Blocking function used to send an SCMI message over
+ * a given channel and wait for its reply
+ *
+ * @param proto pointer to SCMI protocol
+ * @param msg pointer to SCMI message to send
+ * @param reply pointer to SCMI message in which the reply is to be
+ * written
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_send_message(struct scmi_protocol *proto,
+ struct scmi_message *msg, struct scmi_message *reply);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/shmem.h b/include/zephyr/drivers/firmware/scmi/shmem.h
new file mode 100644
index 0000000..a655a36
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/shmem.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI SHMEM API
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_
+
+#include <zephyr/device.h>
+#include <zephyr/arch/cpu.h>
+#include <errno.h>
+
+#define SCMI_SHMEM_CHAN_STATUS_BUSY_BIT BIT(0)
+#define SCMI_SHMEM_CHAN_FLAG_IRQ_BIT BIT(0)
+
+struct scmi_message;
+
+/**
+ * @brief Write a message in the SHMEM area
+ *
+ * @param shmem pointer to shmem device
+ * @param msg message to write
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_shmem_write_message(const struct device *shmem,
+ struct scmi_message *msg);
+
+/**
+ * @brief Read a message from a SHMEM area
+ *
+ * @param shmem pointer to shmem device
+ * @param msg message to write the data into
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_shmem_read_message(const struct device *shmem,
+ struct scmi_message *msg);
+
+/**
+ * @brief Update the channel flags
+ *
+ * @param shmem pointer to shmem device
+ * @param mask value to negate and bitwise-and the old
+ * channel flags value
+ * @param val value to bitwise and with the mask and
+ * bitwise-or with the masked old value
+ */
+void scmi_shmem_update_flags(const struct device *shmem,
+ uint32_t mask, uint32_t val);
+
+/**
+ * @brief Read a channel's status
+ *
+ * @param shmem pointer to shmem device
+ */
+uint32_t scmi_shmem_channel_status(const struct device *shmem);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/transport.h b/include/zephyr/drivers/firmware/scmi/transport.h
new file mode 100644
index 0000000..7f52b0d
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/transport.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Public APIs for the SCMI transport layer drivers
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_
+
+#include <zephyr/device.h>
+#include <zephyr/sys/mutex.h>
+
+struct scmi_message;
+struct scmi_channel;
+
+/**
+ * @typedef scmi_channel_cb
+ *
+ * @brief Callback function for message replies
+ *
+ * This function should be called by the transport layer
+ * driver whenever a reply to a previously sent message
+ * has been received. Its purpose is to notifying the SCMI
+ * core of the reply's arrival so that proper action can
+ * be taken.
+ *
+ * @param chan pointer to SCMI channel on which the reply
+ * arrived
+ */
+typedef void (*scmi_channel_cb)(struct scmi_channel *chan);
+
+/**
+ * @struct scmi_channel
+ * @brief SCMI channel structure
+ *
+ * An SCMI channel is a medium through which a protocol
+ * is able to transmit/receive messages. Each of the SCMI
+ * channels is represented by a `struct scmi_channel`.
+ */
+struct scmi_channel {
+ /**
+ * channel lock. This is meant to be initialized
+ * and used only by the SCMI core to assure that
+ * only one protocol can send/receive messages
+ * through a channel at a given moment.
+ */
+ struct k_mutex lock;
+ /**
+ * binary semaphore. This is meant to be initialized
+ * and used only by the SCMI core. Its purpose is to
+ * signal that a reply has been received.
+ */
+ struct k_sem sem;
+ /** channel private data */
+ void *data;
+ /**
+ * callback function. This is meant to be set by
+ * the SCMI core and should be called by the SCMI
+ * transport layer driver whenever a reply has
+ * been received.
+ */
+ scmi_channel_cb cb;
+ /** is the channel ready to be used by a protocol? */
+ bool ready;
+};
+
+struct scmi_transport_api {
+ int (*init)(const struct device *transport);
+ int (*send_message)(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg);
+ int (*setup_chan)(const struct device *transport,
+ struct scmi_channel *chan,
+ bool tx);
+ int (*read_message)(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg);
+ bool (*channel_is_free)(const struct device *transport,
+ struct scmi_channel *chan);
+ struct scmi_channel *(*request_channel)(const struct device *transport,
+ uint32_t proto, bool tx);
+};
+
+/**
+ * @brief Request an SCMI channel dynamically
+ *
+ * Whenever the SCMI transport layer driver doesn't support
+ * static channel allocation, the SCMI core will try to bind
+ * a channel to a protocol dynamically using this function.
+ * Note that no setup needs to be performed on the channel
+ * in this function as the core will also call the channel
+ * setup() function.
+ *
+ * @param transport pointer to the device structure for the
+ * transport layer
+ * @param proto ID of the protocol for which the core is
+ * requesting the channel
+ * @param tx true if the channel is TX, false if RX
+ *
+ * @retval pointer to SCMI channel that's to be bound
+ * to the protocol
+ * @retval NULL if operation was not successful
+ */
+static inline struct scmi_channel *
+scmi_transport_request_channel(const struct device *transport,
+ uint32_t proto, bool tx)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (api->request_channel) {
+ return api->request_channel(transport, proto, tx);
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief Perform initialization for the transport layer driver
+ *
+ * The transport layer driver can't be initialized directly
+ * (i.e via a call to its init() function) during system initialization.
+ * This is because the macro used to define an SCMI transport places
+ * `scmi_core_transport_init()` in the init section instead of the
+ * driver's init() function. As such, `scmi_core_transport_init()`
+ * needs to call this function to perfrom transport layer driver
+ * initialization if required.
+ *
+ * This operation is optional.
+ *
+ * @param transport pointer to the device structure for the
+ * transport layer
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+static inline int scmi_transport_init(const struct device *transport)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (api->init) {
+ return api->init(transport);
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Setup an SCMI channel
+ *
+ * Before being able to send/receive messages, an SCMI channel needs
+ * to be prepared, which is what this function does. If it returns
+ * successfully, an SCMI protocol will be able to use this channel
+ * to send/receive messages.
+ *
+ * @param transport pointer to the device structure for the
+ * transport layer
+ * @param chan pointer to SCMI channel to be prepared
+ * @param tx true if the channel is TX, false if RX
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+static inline int scmi_transport_setup_chan(const struct device *transport,
+ struct scmi_channel *chan,
+ bool tx)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (!api || !api->setup_chan) {
+ return -ENOSYS;
+ }
+
+ return api->setup_chan(transport, chan, tx);
+}
+
+/**
+ * @brief Send an SCMI channel
+ *
+ * Send an SCMI message using given SCMI channel. This function is
+ * not allowed to block.
+ *
+ * @param transport pointer to the device structure for the
+ * transport layer
+ * @param chan pointer to SCMI channel on which the message
+ * is to be sent
+ * @param msg pointer to message the caller wishes to send
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+static inline int scmi_transport_send_message(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (!api || !api->send_message) {
+ return -ENOSYS;
+ }
+
+ return api->send_message(transport, chan, msg);
+}
+
+/**
+ * @brief Read an SCMI message
+ *
+ * @param transport pointer to the device structure for the
+ * transport layer
+ * @param chan pointer to SCMI channel on which the message
+ * is to be read
+ * @param msg pointer to message the caller wishes to read
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+static inline int scmi_transport_read_message(const struct device *transport,
+ struct scmi_channel *chan,
+ struct scmi_message *msg)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (!api || !api->read_message) {
+ return -ENOSYS;
+ }
+
+ return api->read_message(transport, chan, msg);
+}
+
+/**
+ * @brief Check if an SCMI channel is free
+ *
+ * @param transport pointer to the device structure for
+ * the transport layer
+ * @param chan pointer to SCMI channel the query is to be
+ * performed on
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+static inline bool scmi_transport_channel_is_free(const struct device *transport,
+ struct scmi_channel *chan)
+{
+ const struct scmi_transport_api *api =
+ (const struct scmi_transport_api *)transport->api;
+
+ if (!api || !api->channel_is_free) {
+ return -ENOSYS;
+ }
+
+ return api->channel_is_free(transport, chan);
+}
+
+/**
+ * @brief Perfrom SCMI core initialization
+ *
+ * @param transport pointer to the device structure for
+ * the transport layer
+ *
+ * @retval 0 if successful
+ * @retval negative errno code if failure
+ */
+int scmi_core_transport_init(const struct device *transport);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/util.h b/include/zephyr/drivers/firmware/scmi/util.h
new file mode 100644
index 0000000..ac22b10
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/util.h
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM SCMI utility header
+ *
+ * Contains various utility macros and macros used for protocol and
+ * transport "registration".
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_
+
+/**
+ * @brief Build protocol name from its ID
+ *
+ * Given a protocol ID, this macro builds the protocol
+ * name. This is done by concatenating the scmi_protocol_
+ * construct with the given protocol ID.
+ *
+ * @param proto protocol ID in decimal format
+ *
+ * @return protocol name
+ */
+#define SCMI_PROTOCOL_NAME(proto) CONCAT(scmi_protocol_, proto)
+
+#ifdef CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS
+
+#ifdef CONFIG_ARM_SCMI_MAILBOX_TRANSPORT
+/** @brief Check if a protocol node has an associated channel
+ *
+ * This macro, when applied to a protocol node, checks if
+ * the node has a dedicated static channel allocated to it.
+ * This definition is specific to the mailbox driver and
+ * each new transport layer driver should define its own
+ * version of this macro based on the devicetree properties
+ * that indicate the presence of a dedicated channel.
+ *
+ * @param node_id protocol node identifier
+ * @idx channel index. Should be 0 for TX channels and 1 for
+ * RX channels
+ */
+#define DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, idx)\
+ DT_PROP_HAS_IDX(node_id, shmem, idx)
+#else /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */
+#error "Transport with static channels needs to define HAS_CHAN macro"
+#endif /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */
+
+#define SCMI_TRANSPORT_CHAN_NAME(proto, idx) CONCAT(scmi_channel_, proto, _, idx)
+
+/**
+ * @brief Declare a TX SCMI channel
+ *
+ * Given a node_id for a protocol, this macro declares the SCMI
+ * TX channel statically bound to said protocol via the "extern"
+ * qualifier. This is useful when the transport layer driver
+ * supports static channels since all channel structures are
+ * defined inside the transport layer driver.
+ *
+ * @param node_id protocol node identifier
+ */
+#define DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \
+ COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \
+ (extern struct scmi_channel \
+ SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR(node_id), 0);), \
+ (extern struct scmi_channel \
+ SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0);)) \
+
+/**
+ * @brief Declare SCMI TX/RX channels
+ *
+ * Given a node_id for a protocol, this macro declares the
+ * SCMI TX and RX channels statically bound to said protocol via
+ * the "extern" qualifier. Since RX channels are currently not
+ * supported, this is equivalent to DT_SCMI_TRANSPORT_TX_CHAN_DECLARE().
+ * Despite this, users should opt for this macro instead of the TX-specific
+ * one.
+ *
+ * @param node_id protocol node identifier
+ */
+#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
+ DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \
+
+/**
+ * @brief Declare SCMI TX/RX channels using node instance number
+ *
+ * Same as DT_SCMI_TRANSPORT_CHANNELS_DECLARE() but uses the
+ * protocol's node instance number and the DT_DRV_COMPAT macro.
+ *
+ * @param protocol node instance number
+ */
+#define DT_INST_SCMI_TRANSPORT_CHANNELS_DECLARE(inst) \
+ DT_SCMI_TRANSPORT_CHANNELS_DECLARE(DT_INST(inst, DT_DRV_COMPAT))
+
+/**
+ * @brief Get a reference to a protocol's SCMI TX channel
+ *
+ * Given a node_id for a protocol, this macro returns a
+ * reference to an SCMI TX channel statically bound to said
+ * protocol.
+ *
+ * @param node_id protocol node identifier
+ *
+ * @return reference to the struct scmi_channel of the TX channel
+ * bound to the protocol identifier by node_id
+ */
+#define DT_SCMI_TRANSPORT_TX_CHAN(node_id) \
+ COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \
+ (&SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR(node_id), 0)), \
+ (&SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0)))
+
+/**
+ * @brief Define an SCMI channel for a protocol
+ *
+ * This macro defines a struct scmi_channel for a given protocol.
+ * This should be used by the transport layer driver to statically
+ * define SCMI channels for the protocols.
+ *
+ * @param node_id protocol node identifier
+ * @param idx channel index. Should be 0 for TX channels and 1
+ * for RX channels
+ * @param proto protocol ID in decimal format
+ */
+#define DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, pdata) \
+ struct scmi_channel SCMI_TRANSPORT_CHAN_NAME(proto, idx) = \
+ { \
+ .data = pdata, \
+ }
+
+/**
+ * @brief Define an SCMI protocol's data
+ *
+ * Each SCMI protocol is identified by a struct scmi_protocol
+ * placed in a linker section called scmi_protocol. Each protocol
+ * driver is required to use this macro for "registration". Using
+ * this macro directly is higly discouraged and users should opt
+ * for macros such as DT_SCMI_PROTOCOL_DEFINE_NODEV() or
+ * DT_SCMI_PROTOCOL_DEFINE(), which also takes care of the static
+ * channel declaration (if applicable).
+ *
+ * @param node_id protocol node identifier
+ * @param proto protocol ID in decimal format
+ * @param pdata protocol private data
+ */
+#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \
+ STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \
+ { \
+ .id = proto, \
+ .tx = DT_SCMI_TRANSPORT_TX_CHAN(node_id), \
+ .data = pdata, \
+ }
+
+#else /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */
+
+#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id)
+
+#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \
+ STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \
+ { \
+ .id = proto, \
+ .data = pdata, \
+ }
+
+#endif /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */
+
+/**
+ * @brief Define an SCMI transport driver
+ *
+ * This is merely a wrapper over DEVICE_DT_INST_DEFINE(), but is
+ * required since transport layer drivers are not allowed to place
+ * their own init() function in the init section. Instead, transport
+ * layer drivers place the scmi_core_transport_init() function in the
+ * init section, which, in turn, will call the transport layer driver
+ * init() function. This is required because the SCMI core needs to
+ * perform channel binding and setup during the transport layer driver's
+ * initialization.
+ */
+#define DT_INST_SCMI_TRANSPORT_DEFINE(inst, pm, data, config, level, prio, api) \
+ DEVICE_DT_INST_DEFINE(inst, &scmi_core_transport_init, \
+ pm, data, config, level, prio, api)
+
+/**
+ * @brief Define an SCMI protocol
+ *
+ * This macro performs three important functions:
+ * 1) It defines a `struct scmi_protocol`, which is
+ * needed by all protocol drivers to work with the SCMI API.
+ *
+ * 2) It declares the static channels bound to the protocol.
+ * This is only applicable if the transport layer driver
+ * supports static channels.
+ *
+ * 3) It creates a `struct device` a sets the `data` field
+ * to the newly defined `struct scmi_protocol`. This is
+ * needed because the protocol driver needs to work with the
+ * SCMI API **and** the subsystem API.
+ *
+ * @param node_id protocol node identifier
+ * @param init_fn pointer to protocol's initialization function
+ * @param api pointer to protocol's subsystem API
+ * @param pm pointer to the protocol's power management resources
+ * @param data pointer to protocol's private data
+ * @param config pointer to protocol's private constant data
+ * @param level protocol initialization level
+ * @param prio protocol's priority within its initialization level
+ */
+#define DT_SCMI_PROTOCOL_DEFINE(node_id, init_fn, pm, data, config, \
+ level, prio, api) \
+ DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
+ DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR(node_id), data); \
+ DEVICE_DT_DEFINE(node_id, init_fn, pm, \
+ &SCMI_PROTOCOL_NAME(DT_REG_ADDR(node_id)), \
+ config, level, prio, api)
+
+/**
+ * @brief Just like DT_SCMI_PROTOCOL_DEFINE(), but uses an instance
+ * of a `DT_DRV_COMPAT` compatible instead of a node identifier
+ *
+ * @param inst instance number
+ * @param ... other parameters as expected by DT_SCMI_PROTOCOL_DEFINE()
+ */
+#define DT_INST_SCMI_PROTOCOL_DEFINE(inst, init_fn, pm, data, config, \
+ level, prio, api) \
+ DT_SCMI_PROTOCOL_DEFINE(DT_INST(inst, DT_DRV_COMPAT), init_fn, pm, \
+ data, config, level, prio, api)
+
+/**
+ * @brief Define an SCMI protocol with no device
+ *
+ * Variant of DT_SCMI_PROTOCOL_DEFINE(), but no `struct device` is
+ * created and no initialization function is called during system
+ * initialization. This is useful for protocols that are not really
+ * part of a subsystem with an API (e.g: pinctrl).
+ *
+ * @param node_id protocol node identifier
+ * @param data protocol private data
+ */
+#define DT_SCMI_PROTOCOL_DEFINE_NODEV(node_id, data) \
+ DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \
+ DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR(node_id), data)
+
+/**
+ * @brief Create an SCMI message field
+ *
+ * Data might not necessarily be encoded in the first
+ * x bits of an SCMI message parameter/return value.
+ * This comes in handy when building said parameters/
+ * return values.
+ *
+ * @param x value to encode
+ * @param mask value to perform bitwise-and with `x`
+ * @param shift value to left-shift masked `x`
+ */
+#define SCMI_FIELD_MAKE(x, mask, shift)\
+ (((uint32_t)(x) & (mask)) << (shift))
+
+/**
+ * @brief SCMI protocol IDs
+ *
+ * Each SCMI protocol is identified by an ID. Each
+ * of these IDs needs to be in decimal since they
+ * might be used to build protocol and static channel
+ * names.
+ */
+#define SCMI_PROTOCOL_BASE 16
+#define SCMI_PROTOCOL_POWER_DOMAIN 17
+#define SCMI_PROTOCOL_SYSTEM 18
+#define SCMI_PROTOCOL_PERF 19
+#define SCMI_PROTOCOL_CLOCK 20
+#define SCMI_PROTOCOL_SENSOR 21
+#define SCMI_PROTOCOL_RESET_DOMAIN 22
+#define SCMI_PROTOCOL_VOLTAGE_DOMAIN 23
+#define SCMI_PROTOCOL_PCAP_MONITOR 24
+#define SCMI_PROTOCOL_PINCTRL 25
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_ */
diff --git a/include/zephyr/drivers/hwspinlock.h b/include/zephyr/drivers/hwspinlock.h
index c6e5b48..c1e6c02 100644
--- a/include/zephyr/drivers/hwspinlock.h
+++ b/include/zephyr/drivers/hwspinlock.h
@@ -78,8 +78,9 @@
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
- if (api->trylock == NULL)
+ if (api->trylock == NULL) {
return -ENOSYS;
+ }
return api->trylock(dev, id);
}
@@ -100,8 +101,9 @@
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
- if (api->lock != NULL)
+ if (api->lock != NULL) {
api->lock(dev, id);
+ }
}
/**
@@ -120,8 +122,9 @@
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
- if (api->unlock != NULL)
+ if (api->unlock != NULL) {
api->unlock(dev, id);
+ }
}
/**
@@ -142,8 +145,9 @@
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
- if (api->get_max_id == NULL)
+ if (api->get_max_id == NULL) {
return 0;
+ }
return api->get_max_id(dev);
}
diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h
index 1f9e121..581d588 100644
--- a/include/zephyr/drivers/i2c.h
+++ b/include/zephyr/drivers/i2c.h
@@ -35,6 +35,8 @@
#include <zephyr/sys/slist.h>
#include <zephyr/rtio/rtio.h>
+#line 39
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -480,15 +482,27 @@
* @brief Check if the current message is a read operation
*
* @param msg The message to check
- * @return true if the I2C message is sa read operation
+ * @return true if the I2C message is a read operation
* @return false if the I2C message is a write operation
*/
-static inline bool i2c_is_read_op(struct i2c_msg *msg)
+static inline bool i2c_is_read_op(const struct i2c_msg *msg)
{
return (msg->flags & I2C_MSG_READ) == I2C_MSG_READ;
}
/**
+ * @brief Check if the current message includes a stop.
+ *
+ * @param msg The message to check
+ * @return true if the I2C message includes a stop
+ * @return false if the I2C message includes a stop
+ */
+static inline bool i2c_is_stop_op(const struct i2c_msg *msg)
+{
+ return (msg->flags & I2C_MSG_STOP) == I2C_MSG_STOP;
+}
+
+/**
* @brief Dump out an I2C message
*
* Dumps out a list of I2C messages. For any that are writes (W), the data is
diff --git a/include/zephyr/drivers/interrupt_controller/intc_esp32.h b/include/zephyr/drivers/interrupt_controller/intc_esp32.h
index c1e8606..7ebe7fd 100644
--- a/include/zephyr/drivers/interrupt_controller/intc_esp32.h
+++ b/include/zephyr/drivers/interrupt_controller/intc_esp32.h
@@ -45,6 +45,17 @@
ESP_INTR_FLAG_NMI)
/*
+ * Get the interrupt flags from the supplied priority.
+ */
+#define ESP_PRIO_TO_FLAGS(priority) \
+ ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0)
+
+/*
+ * Check interrupt flags from input and filter unallowed values.
+ */
+#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED)
+
+/*
* The esp_intr_alloc* functions can allocate an int for all *_INTR_SOURCE int sources that
* are routed through the interrupt mux. Apart from these sources, each core also has some internal
* sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
@@ -295,7 +306,6 @@
*/
void esp_intr_noniram_disable(void);
-
/**
* @brief Re-enable interrupts disabled by esp_intr_noniram_disable
*/
diff --git a/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h b/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h
index 775a2e3..6ca5eda 100644
--- a/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h
+++ b/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h
@@ -40,6 +40,18 @@
ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
ESP_INTR_FLAG_NMI)
+/*
+ * Get the interrupt flags from the supplied priority.
+ */
+#define ESP_PRIO_TO_FLAGS(priority) \
+ ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0)
+
+/*
+ * Check interrupt flags from input and filter unallowed values.
+ */
+#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED)
+
+
/* Function prototype for interrupt handler function */
typedef void (*isr_handler_t)(const void *arg);
diff --git a/include/zephyr/drivers/mipi_dbi.h b/include/zephyr/drivers/mipi_dbi.h
index d6ffcaf..dfd017b 100644
--- a/include/zephyr/drivers/mipi_dbi.h
+++ b/include/zephyr/drivers/mipi_dbi.h
@@ -138,7 +138,7 @@
const uint8_t *framebuf,
struct display_buffer_descriptor *desc,
enum display_pixel_format pixfmt);
- int (*reset)(const struct device *dev, uint32_t delay);
+ int (*reset)(const struct device *dev, k_timeout_t delay);
int (*release)(const struct device *dev,
const struct mipi_dbi_config *config);
};
@@ -247,13 +247,13 @@
*
* Resets the attached display controller.
* @param dev mipi dbi controller
- * @param delay duration to set reset signal for, in milliseconds
+ * @param delay_ms duration to set reset signal for, in milliseconds
* @retval 0 reset succeeded
* @retval -EIO I/O error
* @retval -ENOSYS not implemented
* @retval -ENOTSUP not supported
*/
-static inline int mipi_dbi_reset(const struct device *dev, uint32_t delay)
+static inline int mipi_dbi_reset(const struct device *dev, uint32_t delay_ms)
{
const struct mipi_dbi_driver_api *api =
(const struct mipi_dbi_driver_api *)dev->api;
@@ -261,7 +261,7 @@
if (api->reset == NULL) {
return -ENOSYS;
}
- return api->reset(dev, delay);
+ return api->reset(dev, K_MSEC(delay_ms));
}
/**
diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h b/include/zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h
new file mode 100644
index 0000000..b8bb211
--- /dev/null
+++ b/include/zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2022, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * @file
+ * NXP Kinetis SOC specific helpers for pinctrl driver
+ */
+
+
+#ifndef ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
+
+/** @cond INTERNAL_HIDDEN */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef uint32_t pinctrl_soc_pin_t;
+
+/* Kinetis KW/KL/KE series does not support open drain. Define macros to have no effect
+ * Note: KW22 and KW24 do support open drain, rest of KW series does not
+ */
+/* clang-format off */
+#if (defined(CONFIG_SOC_SERIES_KINETIS_KWX) && \
+ !(defined(CONFIG_SOC_MKW24D5) || defined(CONFIG_SOC_MKW22D5))) || \
+ defined(CONFIG_SOC_SERIES_KINETIS_KL2X) || defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || \
+ defined(CONFIG_SOC_SERIES_KE1XZ)
+#define PORT_PCR_ODE(x) 0x0
+#define PORT_PCR_ODE_MASK 0x0
+#endif
+/* clang-format on */
+
+/* Kinetis KE series does not support slew rate. Define macros to have no effect */
+#if defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || defined(CONFIG_SOC_SERIES_KE1XZ)
+#define PORT_PCR_SRE(x) 0x0
+#define PORT_PCR_SRE_MASK 0x0
+#endif
+
+#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
+ (PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
+ PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
+ PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
+ PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
+ PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
+ PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
+ PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
+
+#define Z_PINCTRL_KINETIS_PCR_MASK \
+ (PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | \
+ PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
+
+#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
+ DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
+ {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
+ Z_PINCTRL_STATE_PIN_INIT)};
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @endcond */
+
+#endif /* ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ */
diff --git a/include/zephyr/drivers/rtc/rtc_fake.h b/include/zephyr/drivers/rtc/rtc_fake.h
index ad3a275..d421a56 100644
--- a/include/zephyr/drivers/rtc/rtc_fake.h
+++ b/include/zephyr/drivers/rtc/rtc_fake.h
@@ -19,19 +19,19 @@
#ifdef CONFIG_RTC_ALARM
DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_supported_fields, const struct device *, uint16_t,
- uint16_t);
+ uint16_t *);
DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_time, const struct device *, uint16_t, uint16_t,
- constr struct rtc_time *);
-DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t,
+ const struct rtc_time *);
+DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t *,
struct rtc_time *);
DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_is_pending, const struct device *, uint16_t);
-DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *uint16_t,
+DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *, uint16_t,
rtc_alarm_callback, void *);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
-DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *rtc_alarm_callback,
- void *);
+DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *,
+ rtc_update_callback, void *);
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
diff --git a/include/zephyr/drivers/sensor.h b/include/zephyr/drivers/sensor.h
index b1bd243..62a6adc 100644
--- a/include/zephyr/drivers/sensor.h
+++ b/include/zephyr/drivers/sensor.h
@@ -349,7 +349,10 @@
/** Hardware batch duration in ticks */
SENSOR_ATTR_BATCH_DURATION,
-
+ /* Configure the gain of a sensor. */
+ SENSOR_ATTR_GAIN,
+ /* Configure the resolution of a sensor. */
+ SENSOR_ATTR_RESOLUTION,
/**
* Number of all common sensor attributes.
*/
diff --git a/include/zephyr/drivers/sensor/tsl2540.h b/include/zephyr/drivers/sensor/tsl2540.h
index 63a2adf..b0306e9 100644
--- a/include/zephyr/drivers/sensor/tsl2540.h
+++ b/include/zephyr/drivers/sensor/tsl2540.h
@@ -22,10 +22,8 @@
#endif
enum sensor_attribute_tsl2540 {
- /* Sensor Gain */
- SENSOR_ATTR_GAIN = SENSOR_ATTR_PRIV_START + 1,
/* Sensor Integration Time (in ms) */
- SENSOR_ATTR_INTEGRATION_TIME,
+ SENSOR_ATTR_INTEGRATION_TIME = SENSOR_ATTR_PRIV_START + 1,
/* Sensor ALS interrupt persistence filters */
SENSOR_ATTR_INT_APERS,
/* Shutdown the sensor */
diff --git a/include/zephyr/drivers/usb/udc.h b/include/zephyr/drivers/usb/udc.h
index 15f70a7..7910d8c 100644
--- a/include/zephyr/drivers/usb/udc.h
+++ b/include/zephyr/drivers/usb/udc.h
@@ -76,6 +76,8 @@
uint32_t bulk : 1;
/** ISO transfer capable endpoint */
uint32_t iso : 1;
+ /** High-Bandwidth (interrupt or iso) capable endpoint */
+ uint32_t high_bandwidth : 1;
/** IN transfer capable endpoint */
uint32_t in : 1;
/** OUT transfer capable endpoint */
@@ -725,6 +727,18 @@
}
/**
+ * @brief Get endpoint size from UDC endpoint configuration
+ *
+ * @param[in] cfg Pointer to UDC endpoint configuration
+ *
+ * @return Endpoint size
+ */
+static inline uint16_t udc_mps_ep_size(const struct udc_ep_config *const cfg)
+{
+ return USB_MPS_EP_SIZE(cfg->mps);
+}
+
+/**
* @}
*/
diff --git a/include/zephyr/dt-bindings/clock/esp32c2_clock.h b/include/zephyr/dt-bindings/clock/esp32c2_clock.h
new file mode 100644
index 0000000..03b66cf
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/esp32c2_clock.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
+
+/* Supported CPU clock Sources */
+#define ESP32_CPU_CLK_SRC_XTAL 0U
+#define ESP32_CPU_CLK_SRC_PLL 1U
+#define ESP32_CLK_SRC_RC_FAST 2U
+
+/* Supported CPU frequencies */
+#define ESP32_CLK_CPU_PLL_40M 40000000
+#define ESP32_CLK_CPU_PLL_60M 60000000
+#define ESP32_CLK_CPU_PLL_80M 80000000
+#define ESP32_CLK_CPU_PLL_120M 120000000
+#define ESP32_CLK_CPU_RC_FAST_FREQ 8750000
+
+/* Supported XTAL frequencies */
+#define ESP32_CLK_XTAL_26M 26000000
+#define ESP32_CLK_XTAL_32M 32000000
+#define ESP32_CLK_XTAL_40M 40000000
+
+/* Supported RTC fast clock sources */
+#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0
+#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1
+
+/* Supported RTC slow clock sources */
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
+#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW 1
+#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2
+
+/* RTC slow clock frequencies */
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
+#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ 32768
+#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359
+
+/* Modules IDs
+ * These IDs are actually offsets in CLK and RST Control registers.
+ * These IDs shouldn't be changed unless there is a Hardware change
+ * from Espressif.
+ *
+ * Basic Modules
+ * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
+ */
+#define ESP32_LEDC_MODULE 0
+#define ESP32_UART0_MODULE 1
+#define ESP32_UART1_MODULE 2
+#define ESP32_I2C0_MODULE 3
+#define ESP32_TIMG0_MODULE 4
+#define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */
+#define ESP32_UHCI0_MODULE 6
+#define ESP32_SPI_MODULE 7 /* SPI1 */
+#define ESP32_SPI2_MODULE 8 /* SPI2 */
+#define ESP32_RNG_MODULE 9
+#define ESP32_WIFI_MODULE 10
+#define ESP32_BT_MODULE 11
+#define ESP32_WIFI_BT_COMMON_MODULE 12
+#define ESP32_BT_BASEBAND_MODULE 13
+#define ESP32_BT_LC_MODULE 14
+#define ESP32_AES_MODULE 15
+#define ESP32_SHA_MODULE 16
+#define ESP32_ECC_MODULE 17
+#define ESP32_GDMA_MODULE 18
+#define ESP32_SYSTIMER_MODULE 19
+#define ESP32_SARADC_MODULE 20
+#define ESP32_TEMPSENSOR_MODULE 21
+#define ESP32_MODEM_RPA_MODULE 22
+#define ESP32_MODULE_MAX 23
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ */
diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
index 18c44ca..3f1544e 100644
--- a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
+++ b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
@@ -23,11 +23,17 @@
/* LPUART */
#define IMX_CCM_LPUART_CLK 0x300UL
#define IMX_CCM_LPUART1_CLK 0x300UL
+#define IMX_CCM_LPUART0102_CLK 0x300UL
#define IMX_CCM_LPUART2_CLK 0x301UL
+#define IMX_CCM_LPUART0304_CLK 0x301UL
#define IMX_CCM_LPUART3_CLK 0x302UL
+#define IMX_CCM_LPUART0506_CLK 0x302UL
#define IMX_CCM_LPUART4_CLK 0x303UL
+#define IMX_CCM_LPUART0708_CLK 0x303UL
#define IMX_CCM_LPUART5_CLK 0x304UL
+#define IMX_CCM_LPUART0910_CLK 0x304UL
#define IMX_CCM_LPUART6_CLK 0x305UL
+#define IMX_CCM_LPUART1112_CLK 0x305UL
#define IMX_CCM_LPUART7_CLK 0x306UL
#define IMX_CCM_LPUART8_CLK 0x307UL
#define IMX_CCM_LPUART9_CLK 0x308UL
@@ -37,12 +43,16 @@
/* LPI2C */
#define IMX_CCM_LPI2C_CLK 0x400UL
+#define IMX_CCM_LPI2C0102_CLK 0x400UL
#define IMX_CCM_LPI2C1_CLK 0x400UL
#define IMX_CCM_LPI2C2_CLK 0x401UL
+#define IMX_CCM_LPI2C0304_CLK 0x401UL
#define IMX_CCM_LPI2C3_CLK 0x402UL
#define IMX_CCM_LPI2C4_CLK 0x403UL
+#define IMX_CCM_LPI2C0506_CLK 0x402UL
#define IMX_CCM_LPI2C5_CLK 0x404UL
#define IMX_CCM_LPI2C6_CLK 0x405UL
+#define IMX_CCM_LPI2C0708_CLK 0x403UL
#define IMX_CCM_LPI2C7_CLK 0x406UL
#define IMX_CCM_LPI2C8_CLK 0x407UL
diff --git a/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h
index fab7f65..85f411c 100644
--- a/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h
+++ b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h
@@ -271,4 +271,17 @@
#define NUMAKER_LPADC0_MODULE 0xB5431218
#define NUMAKER_OPA_MODULE 0xA000001B
+#define NUMAKER_CLK_PMUCTL_PDMSEL_PD 0x00000000
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD0 0x00000000
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD1 0x00000001
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD2 0x00000002
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD3 0x00000003
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD4 0x00000004
+#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD5 0x00000005
+#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD0 0x00000008
+#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD1 0x00000009
+#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD2 0x0000000A
+#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD0 0x0000000C
+#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD1 0x0000000D
+
#endif
diff --git a/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h b/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
index 6471a2c..b19e44e 100644
--- a/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
+++ b/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -292,9 +292,5 @@
#define NXP_S32_SPI9_CLK 284U
#define NXP_S32_SRX0_CLK 285U
#define NXP_S32_SRX1_CLK 286U
-#define NXP_S32_CORE_PLL_REFCLKOUT 287U
-#define NXP_S32_CORE_PLL_FBCLKOUT 288U
-#define NXP_S32_PERIPH_PLL_REFCLKOUT 289U
-#define NXP_S32_PERIPH_PLL_FBCLKOUT 290U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h
index 765b6ed..024f4d5 100644
--- a/include/zephyr/dt-bindings/clock/ra_clock.h
+++ b/include/zephyr/dt-bindings/clock/ra_clock.h
@@ -117,6 +117,26 @@
#define RA_I3C_CLOCK_DIV_6 3
#define RA_I3C_CLOCK_DIV_8 4
+/* LCD clock divider options. */
+#define RA_LCD_CLOCK_DIV_1 0
+#define RA_LCD_CLOCK_DIV_2 1
+#define RA_LCD_CLOCK_DIV_3 5
+#define RA_LCD_CLOCK_DIV_4 2
+#define RA_LCD_CLOCK_DIV_5 6
+#define RA_LCD_CLOCK_DIV_6 3
+#define RA_LCD_CLOCK_DIV_8 4
+
+/* SDADC clock divider options. */
+#define RA_SDADC_CLOCK_DIV_1 0
+#define RA_SDADC_CLOCK_DIV_2 1
+#define RA_SDADC_CLOCK_DIV_3 2
+#define RA_SDADC_CLOCK_DIV_4 3
+#define RA_SDADC_CLOCK_DIV_5 4
+#define RA_SDADC_CLOCK_DIV_6 5
+#define RA_SDADC_CLOCK_DIV_8 6
+#define RA_SDADC_CLOCK_DIV_12 7
+#define RA_SDADC_CLOCK_DIV_16 8
+
#define MSTPA 0x40203000
#define MSTPB 0x40203004
#define MSTPC 0x40203008
diff --git a/include/zephyr/dt-bindings/dma/max32662_dma.h b/include/zephyr/dt-bindings/dma/max32662_dma.h
new file mode 100644
index 0000000..4ba582b
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max32662_dma.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
+
+#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
+#define MAX32_DMA_SLOT_SPI0_RX 0x01U
+#define MAX32_DMA_SLOT_SPI1_RX 0x02U
+#define MAX32_DMA_SLOT_UART0_RX 0x04U
+#define MAX32_DMA_SLOT_UART1_RX 0x05U
+#define MAX32_DMA_SLOT_CAN_RX 0x06U
+#define MAX32_DMA_SLOT_I2C0_RX 0x07U
+#define MAX32_DMA_SLOT_I2C1_RX 0x08U
+#define MAX32_DMA_SLOT_ADC 0x09U
+#define MAX32_DMA_SLOT_I2S_RX 0x1EU
+#define MAX32_DMA_SLOT_SPI0_TX 0x21U
+#define MAX32_DMA_SLOT_SPI1_TX 0x22U
+#define MAX32_DMA_SLOT_UART0_TX 0x24U
+#define MAX32_DMA_SLOT_UART1_TX 0x25U
+#define MAX32_DMA_SLOT_CAN_TX 0x26U
+#define MAX32_DMA_SLOT_I2C0_TX 0x27U
+#define MAX32_DMA_SLOT_I2C1_TX 0x28U
+#define MAX32_DMA_SLOT_I2S_TX 0x3EU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/max32666_dma.h b/include/zephyr/dt-bindings/dma/max32666_dma.h
new file mode 100644
index 0000000..8296e02
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max32666_dma.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_
+
+#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
+#define MAX32_DMA_SLOT_SPI1_RX 0x01U
+#define MAX32_DMA_SLOT_SPI2_RX 0x02U
+#define MAX32_DMA_SLOT_UART0_RX 0x04U
+#define MAX32_DMA_SLOT_UART1_RX 0x05U
+#define MAX32_DMA_SLOT_I2C0_RX 0x07U
+#define MAX32_DMA_SLOT_I2C1_RX 0x08U
+#define MAX32_DMA_SLOT_ADC 0x09U
+#define MAX32_DMA_SLOT_I2C2_RX 0x0AU
+#define MAX32_DMA_SLOT_UART2_RX 0x0EU
+#define MAX32_DMA_SLOT_SPI0_RX 0x0FU
+#define MAX32_DMA_SLOT_SPI1_TX 0x21U
+#define MAX32_DMA_SLOT_SPI2_TX 0x21U
+#define MAX32_DMA_SLOT_UART0_TX 0x24U
+#define MAX32_DMA_SLOT_UART1_TX 0x25U
+#define MAX32_DMA_SLOT_I2C0_TX 0x27U
+#define MAX32_DMA_SLOT_I2C1_TX 0x28U
+#define MAX32_DMA_SLOT_I2C2_TX 0x2AU
+#define MAX32_DMA_SLOT_UART2_TX 0x2EU
+#define MAX32_DMA_SLOT_SPI0_TX 0x2FU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/max32675_dma.h b/include/zephyr/dt-bindings/dma/max32675_dma.h
new file mode 100644
index 0000000..e627637
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max32675_dma.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_
+
+#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
+#define MAX32_DMA_SLOT_SPI0_RX 0x01U
+#define MAX32_DMA_SLOT_SPI1_RX 0x02U
+#define MAX32_DMA_SLOT_UART0_RX 0x04U
+#define MAX32_DMA_SLOT_I2C0_RX 0x07U
+#define MAX32_DMA_SLOT_I2C2_RX 0x0AU
+#define MAX32_DMA_SLOT_UART2_RX 0x0EU
+#define MAX32_DMA_SLOT_AES_RX 0x10U
+#define MAX32_DMA_SLOT_I2S_RX 0x1EU
+#define MAX32_DMA_SLOT_SPI0_TX 0x21U
+#define MAX32_DMA_SLOT_SPI1_TX 0x22U
+#define MAX32_DMA_SLOT_UART0_TX 0x24U
+#define MAX32_DMA_SLOT_I2C0_TX 0x27U
+#define MAX32_DMA_SLOT_I2C2_TX 0x2AU
+#define MAX32_DMA_SLOT_CRC 0x2CU
+#define MAX32_DMA_SLOT_UART2_TX 0x2EU
+#define MAX32_DMA_SLOT_AES_TX 0x30U
+#define MAX32_DMA_SLOT_I2S_TX 0x3EU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h b/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h
new file mode 100644
index 0000000..335f4b1
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
+
+#define RENESAS_GPIO_DS_POS (8)
+#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS)
+/* GPIO Drive strength */
+#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS)
+#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS)
+#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS)
+#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h
deleted file mode 100644
index aa511e9..0000000
--- a/include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_
-
-#define RENESAS_GPIO_DS_POS (8)
-#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS)
-/* GPIO Drive strength */
-#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS)
-#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS)
-#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS)
-#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS)
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
new file mode 100644
index 0000000..5f4cd79
--- /dev/null
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
+
+#define WIFI_MAC_INTR_SOURCE 0
+#define WIFI_MAC_NMI_SOURCE 1
+#define WIFI_PWR_INTR_SOURCE 2
+#define WIFI_BB_INTR_SOURCE 3
+#define BT_MAC_INTR_SOURCE 4
+#define BT_BB_INTR_SOURCE 5
+#define BT_BB_NMI_SOURCE 6
+#define LP_TIMER_SOURCE 7
+#define COEX_SOURCE 8
+#define BLE_TIMER_SOURCE 9
+#define BLE_SEC_SOURCE 10
+#define I2C_MASTER_SOURCE 11
+#define APB_CTRL_INTR_SOURCE 12
+#define GPIO_INTR_SOURCE 13
+#define GPIO_NMI_SOURCE 14
+#define SPI1_INTR_SOURCE 15
+#define SPI2_INTR_SOURCE 16
+#define UART0_INTR_SOURCE 17
+#define UART1_INTR_SOURCE 18
+#define LEDC_INTR_SOURCE 19
+#define EFUSE_INTR_SOURCE 20
+#define RTC_CORE_INTR_SOURCE 21
+#define I2C_EXT0_INTR_SOURCE 22
+#define TG0_T0_LEVEL_INTR_SOURCE 23
+#define TG0_WDT_LEVEL_INTR_SOURCE 24
+#define CACHE_IA_INTR_SOURCE 25
+#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26
+#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27
+#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28
+#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29
+#define ICACHE_PRELOAD0_INTR_SOURCE 30
+#define ICACHE_SYNC0_INTR_SOURCE 31
+#define APB_ADC_INTR_SOURCE 32
+#define DMA_CH0_INTR_SOURCE 33
+#define SHA_INTR_SOURCE 34
+#define ECC_INTR_SOURCE 35
+#define FROM_CPU_INTR0_SOURCE 36
+#define FROM_CPU_INTR1_SOURCE 37
+#define FROM_CPU_INTR2_SOURCE 38
+#define FROM_CPU_INTR3_SOURCE 39
+#define ASSIST_DEBUG_INTR_SOURCE 40
+#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41
+#define CACHE_CORE0_ACS_INTR_SOURCE 42
+
+/* RISC-V supports priority values from 1 (lowest) to 15.
+ * As interrupt controller for Xtensa and RISC-V is shared, this is
+ * set to an intermediate and compatible value.
+ */
+#define IRQ_DEFAULT_PRIORITY 3
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
+#endif
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
index f5e2cd6..f605900 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
@@ -70,4 +70,12 @@
#define BAK_PMS_VIOLATE_INTR_SOURCE 60
#define CACHE_CORE0_ACS_INTR_SOURCE 61
+/* RISC-V supports priority values from 1 (lowest) to 15.
+ * As interrupt controller for Xtensa and RISC-V is shared, this is
+ * set to an intermediate and compatible value.
+ */
+#define IRQ_DEFAULT_PRIORITY 3
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
#endif
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
index 644d8cf..24b5550 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
@@ -86,4 +86,12 @@
#define ECC_INTR_SOURCE 76 /* interrupt of ECC accelerator, level*/
#define MAX_INTR_SOURCE 77
+/* RISC-V supports priority values from 1 (lowest) to 15.
+ * As interrupt controller for Xtensa and RISC-V is shared, this is
+ * set to an intermediate and compatible value.
+ */
+#define IRQ_DEFAULT_PRIORITY 3
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
index d065771..32194e6 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
@@ -79,4 +79,11 @@
#define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */
#define MAX_INTR_SOURCE 69 /* total number of interrupt sources */
+/* For Xtensa architecture, zero will allocate low/medium
+ * levels of priority (ESP_INTR_FLAG_LOWMED)
+ */
+#define IRQ_DEFAULT_PRIORITY 0
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
#endif
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
index fd63ea5..383f9a6 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
@@ -106,4 +106,11 @@
#define ICACHE_SYNC_INTR_SOURCE 94 /* instruction cache sync done, level */
#define MAX_INTR_SOURCE 95 /* total number of interrupt sources */
+/* For Xtensa architecture, zero will allocate low/medium
+ * levels of priority (ESP_INTR_FLAG_LOWMED)
+ */
+#define IRQ_DEFAULT_PRIORITY 0
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
#endif
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
index e2b94e5..87c6906 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
@@ -104,4 +104,11 @@
#define DMA_EXTMEM_REJECT_SOURCE 98
#define MAX_INTR_SOURCE 99 /* number of interrupt sources */
+/* For Xtensa architecture, zero will allocate low/medium
+ * levels of priority (ESP_INTR_FLAG_LOWMED)
+ */
+#define IRQ_DEFAULT_PRIORITY 0
+
+#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
+
#endif
diff --git a/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h b/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h
new file mode 100644
index 0000000..8e4e175
--- /dev/null
+++ b/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_
+
+#define NRF_DOMAIN_ID_APPLICATION 2
+#define NRF_DOMAIN_ID_RADIOCORE 3
+#define NRF_DOMAIN_ID_CELLCORE 4
+#define NRF_DOMAIN_ID_GLOBALFAST 12
+#define NRF_DOMAIN_ID_GLOBALSLOW 13
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ */
diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h
new file mode 100644
index 0000000..aec1950
--- /dev/null
+++ b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* autogenerated using Nordic HAL utils/gen_offsets.py script */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_
+
+#define NRF_FICR_BLE_ADDRTYPE 0x00CU
+#define NRF_FICR_BLE_ADDR_0 0x010U
+#define NRF_FICR_BLE_ADDR_1 0x014U
+#define NRF_FICR_BLE_ER_0 0x018U
+#define NRF_FICR_BLE_ER_1 0x01CU
+#define NRF_FICR_BLE_ER_2 0x020U
+#define NRF_FICR_BLE_ER_3 0x024U
+#define NRF_FICR_BLE_IR_0 0x028U
+#define NRF_FICR_BLE_IR_1 0x02CU
+#define NRF_FICR_BLE_IR_2 0x030U
+#define NRF_FICR_BLE_IR_3 0x034U
+#define NRF_FICR_INFO_CONFIGID 0x050U
+#define NRF_FICR_INFO_PART 0x054U
+#define NRF_FICR_INFO_VARIANT 0x058U
+#define NRF_FICR_INFO_PACKAGE 0x05CU
+#define NRF_FICR_INFO_RAM 0x060U
+#define NRF_FICR_INFO_MRAM 0x064U
+#define NRF_FICR_INFO_CODEPAGESIZE 0x068U
+#define NRF_FICR_INFO_CODESIZE 0x06CU
+#define NRF_FICR_INFO_DEVICETYPE 0x070U
+#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG 0x0A4U
+#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG 0x0A8U
+#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL 0x0ACU
+#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG 0x0B0U
+#define NRF_FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG 0x0B4U
+#define NRF_FICR_SIPINFO_PARTNO 0x080U
+#define NRF_FICR_SIPINFO_HWREVISION_0 0x084U
+#define NRF_FICR_SIPINFO_HWREVISION_1 0x085U
+#define NRF_FICR_SIPINFO_HWREVISION_2 0x086U
+#define NRF_FICR_SIPINFO_HWREVISION_3 0x087U
+#define NRF_FICR_SIPINFO_VARIANT_0 0x088U
+#define NRF_FICR_SIPINFO_VARIANT_1 0x089U
+#define NRF_FICR_SIPINFO_VARIANT_2 0x08AU
+#define NRF_FICR_SIPINFO_VARIANT_3 0x08BU
+#define NRF_FICR_SIPINFO_PMICVERSION 0x08CU
+#define NRF_FICR_SIPINFO_TESTSITE_0 0x090U
+#define NRF_FICR_SIPINFO_TESTSITE_1 0x091U
+#define NRF_FICR_SIPINFO_TESTSITE_2 0x092U
+#define NRF_FICR_SIPINFO_TESTSITE_3 0x093U
+#define NRF_FICR_SIPINFO_LOT 0x094U
+#define NRF_FICR_SIPINFO_TESTPROGRAMID_0 0x098U
+#define NRF_FICR_SIPINFO_TESTPROGRAMID_1 0x099U
+#define NRF_FICR_SIPINFO_TESTPROGRAMID_2 0x09AU
+#define NRF_FICR_SIPINFO_TESTPROGRAMID_3 0x09BU
+#define NRF_FICR_SIPINFO_OSATPARTNO 0x09CU
+#define NRF_FICR_SIPINFO_HWBUILDVERSION_0 0x0A0U
+#define NRF_FICR_SIPINFO_HWBUILDVERSION_1 0x0A1U
+#define NRF_FICR_SIPINFO_HWBUILDVERSION_2 0x0A2U
+#define NRF_FICR_SIPINFO_HWBUILDVERSION_3 0x0A3U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREF 0x344U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_0 0x348U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_1 0x34CU
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_2 0x350U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALOFFSET 0x354U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x358U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x35CU
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x360U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x364U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x368U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x36CU
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALIREF 0x370U
+#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREFTC 0x374U
+#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x380U
+#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x390U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x398U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x39CU
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3A0U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3A4U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3A8U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3ACU
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3B0U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3B4U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3B8U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3BCU
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x3C0U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x3C4U
+#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x3C8U
+#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x3CCU
+#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x3D0U
+#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x3D4U
+#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_3_TRIM 0x3D8U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x3DCU
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x3E0U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x3E4U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x3E8U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x3ECU
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x3F0U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x3F4U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x3F8U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x3FCU
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x400U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x404U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x408U
+#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x40CU
+#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x410U
+#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x414U
+#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x418U
+#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_3_TRIM 0x41CU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ */
diff --git a/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h b/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h
new file mode 100644
index 0000000..6d9a8f2
--- /dev/null
+++ b/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_
+
+#define NRF_OWNER_ID_NONE 0
+#define NRF_OWNER_ID_APPLICATION 2
+#define NRF_OWNER_ID_RADIOCORE 3
+#define NRF_OWNER_ID_CELL 4
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h b/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h
new file mode 100644
index 0000000..4f6331f
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
+
+#define ESP_NOSIG ESP_SIG_INVAL
+
+#define ESP_SPICLK_OUT_MUX ESP_SPICLK_OUT
+#define ESP_SPIQ_IN 0
+#define ESP_SPIQ_OUT 0
+#define ESP_SPID_IN 1
+#define ESP_SPID_OUT 1
+#define ESP_SPIHD_IN 2
+#define ESP_SPIHD_OUT 2
+#define ESP_SPIWP_IN 3
+#define ESP_SPIWP_OUT 3
+#define ESP_SPICLK_OUT 4
+#define ESP_SPICS0_OUT 5
+#define ESP_U0RXD_IN 6
+#define ESP_U0TXD_OUT 6
+#define ESP_U0CTS_IN 7
+#define ESP_U0RTS_OUT 7
+#define ESP_U0DSR_IN 8
+#define ESP_U0DTR_OUT 8
+#define ESP_U1RXD_IN 9
+#define ESP_U1TXD_OUT 9
+#define ESP_U1CTS_IN 10
+#define ESP_U1RTS_OUT 10
+#define ESP_U1DSR_IN 11
+#define ESP_U1DTR_OUT 11
+#define ESP_SPIQ_MONITOR 15
+#define ESP_SPID_MONITOR 16
+#define ESP_SPIHD_MONITOR 17
+#define ESP_SPIWP_MONITOR 18
+#define ESP_SPICS1_OUT 19
+#define ESP_CPU_TESTBUS0 20
+#define ESP_CPU_TESTBUS1 21
+#define ESP_CPU_TESTBUS2 22
+#define ESP_CPU_TESTBUS3 23
+#define ESP_CPU_TESTBUS4 24
+#define ESP_CPU_TESTBUS5 25
+#define ESP_CPU_TESTBUS6 26
+#define ESP_CPU_TESTBUS7 27
+#define ESP_CPU_GPIO_IN0 28
+#define ESP_CPU_GPIO_OUT0 28
+#define ESP_CPU_GPIO_IN1 29
+#define ESP_CPU_GPIO_OUT1 29
+#define ESP_CPU_GPIO_IN2 30
+#define ESP_CPU_GPIO_OUT2 30
+#define ESP_CPU_GPIO_IN3 31
+#define ESP_CPU_GPIO_OUT3 31
+#define ESP_CPU_GPIO_IN4 32
+#define ESP_CPU_GPIO_OUT4 32
+#define ESP_CPU_GPIO_IN5 33
+#define ESP_CPU_GPIO_OUT5 33
+#define ESP_CPU_GPIO_IN6 34
+#define ESP_CPU_GPIO_OUT6 34
+#define ESP_CPU_GPIO_IN7 35
+#define ESP_CPU_GPIO_OUT7 35
+#define ESP_EXT_ADC_START 45
+#define ESP_LEDC_LS_SIG_OUT0 45
+#define ESP_LEDC_LS_SIG_OUT1 46
+#define ESP_LEDC_LS_SIG_OUT2 47
+#define ESP_LEDC_LS_SIG_OUT3 48
+#define ESP_LEDC_LS_SIG_OUT4 49
+#define ESP_LEDC_LS_SIG_OUT5 50
+#define ESP_RMT_SIG_IN0 51
+#define ESP_RMT_SIG_OUT0 51
+#define ESP_RMT_SIG_IN1 52
+#define ESP_RMT_SIG_OUT1 52
+#define ESP_I2CEXT0_SCL_IN 53
+#define ESP_I2CEXT0_SCL_OUT 53
+#define ESP_I2CEXT0_SDA_IN 54
+#define ESP_I2CEXT0_SDA_OUT 54
+#define ESP_FSPICLK_IN 63
+#define ESP_FSPICLK_OUT 63
+#define ESP_FSPIQ_IN 64
+#define ESP_FSPIQ_OUT 64
+#define ESP_FSPID_IN 65
+#define ESP_FSPID_OUT 65
+#define ESP_FSPIHD_IN 66
+#define ESP_FSPIHD_OUT 66
+#define ESP_FSPIWP_IN 67
+#define ESP_FSPIWP_OUT 67
+#define ESP_FSPICS0_IN 68
+#define ESP_FSPICS0_OUT 68
+#define ESP_FSPICS1_OUT 69
+#define ESP_FSPICS2_OUT 70
+#define ESP_FSPICS3_OUT 71
+#define ESP_FSPICS4_OUT 72
+#define ESP_FSPICS5_OUT 73
+#define ESP_EXTERN_PRIORITY_I 77
+#define ESP_EXTERN_PRIORITY_O 77
+#define ESP_EXTERN_ACTIVE_I 78
+#define ESP_EXTERN_ACTIVE_O 78
+#define ESP_GPIO_EVENT_MATRIX_IN0 79
+#define ESP_GPIO_TASK_MATRIX_OUT0 79
+#define ESP_GPIO_EVENT_MATRIX_IN1 80
+#define ESP_GPIO_TASK_MATRIX_OUT1 80
+#define ESP_GPIO_EVENT_MATRIX_IN2 81
+#define ESP_GPIO_TASK_MATRIX_OUT2 81
+#define ESP_GPIO_EVENT_MATRIX_IN3 82
+#define ESP_GPIO_TASK_MATRIX_OUT3 82
+#define ESP_BB_DIAG8_OUT 83
+#define ESP_BB_DIAG9_OUT 84
+#define ESP_BB_DIAG10_OUT 85
+#define ESP_BB_DIAG11_OUT 86
+#define ESP_BB_DIAG12_OUT 87
+#define ESP_BB_DIAG13_OUT 88
+#define ESP_ANT_SEL0 89
+#define ESP_ANT_SEL1 90
+#define ESP_ANT_SEL2 91
+#define ESP_ANT_SEL3 92
+#define ESP_ANT_SEL4 93
+#define ESP_ANT_SEL5 94
+#define ESP_ANT_SEL6 95
+#define ESP_ANT_SEL7 96
+#define ESP_SIG_IN_FUNC_97 97
+#define ESP_SIG_IN_FUNC97 97
+#define ESP_SIG_IN_FUNC_98 98
+#define ESP_SIG_IN_FUNC98 98
+#define ESP_SIG_IN_FUNC_99 99
+#define ESP_SIG_IN_FUNC99 99
+#define ESP_SIG_IN_FUNC_100 100
+#define ESP_SIG_IN_FUNC100 100
+#define ESP_BLE_DBG_SYNCERR 101
+#define ESP_BLE_DBG_SYNC_FOUND 102
+#define ESP_BLE_DBG_CH_IDX 103
+#define ESP_BLE_DBG_SYNC_WINDOW 104
+#define ESP_BLE_DBG_DATA_EN 105
+#define ESP_BLE_DBG_DATA 106
+#define ESP_BLE_DBG_PKT_TX_ON 107
+#define ESP_BLE_DBG_PKT_RX_ON 108
+#define ESP_BLE_DBG_TXRU_ON 109
+#define ESP_BLE_DBG_RXRU_ON 110
+#define ESP_BLE_DBG_LELC_ST0 111
+#define ESP_BLE_DBG_LELC_ST1 112
+#define ESP_BLE_DBG_LELC_ST2 113
+#define ESP_BLE_DBG_LELC_ST3 114
+#define ESP_BLE_DBG_CRCOK 115
+#define ESP_BLE_DBG_CLK_GPIO 116
+#define ESP_BLE_DBG_RADIO_START 117
+#define ESP_BLE_DBG_SEQUENCE_ON 118
+#define ESP_BLE_DBG_COEX_BT_ON 119
+#define ESP_BLE_DBG_COEX_WIFI_ON 120
+#define ESP_CLK_OUT_OUT1 123
+#define ESP_CLK_OUT_OUT2 124
+#define ESP_CLK_OUT_OUT3 125
+#define ESP_SIG_GPIO_OUT 128
+#define ESP_GPIO_MAP_DATE 0x2106190
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h
new file mode 100644
index 0000000..f89d448
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h
@@ -0,0 +1,529 @@
+/*
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * NOTE: Autogenerated file using esp_genpinctrl.py
+ */
+
+#ifndef INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_
+#define INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_
+
+/* UART0_CTS */
+#define UART0_CTS_GPIO0 \
+ ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO1 \
+ ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO2 \
+ ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO3 \
+ ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO4 \
+ ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO5 \
+ ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO6 \
+ ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO7 \
+ ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO8 \
+ ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO9 \
+ ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO10 \
+ ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO18 \
+ ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO19 \
+ ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG)
+
+#define UART0_CTS_GPIO20 \
+ ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG)
+
+/* UART0_DSR */
+#define UART0_DSR_GPIO0 \
+ ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO1 \
+ ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO2 \
+ ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO3 \
+ ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO4 \
+ ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO5 \
+ ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO6 \
+ ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO7 \
+ ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO8 \
+ ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO9 \
+ ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO10 \
+ ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO18 \
+ ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO19 \
+ ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG)
+
+#define UART0_DSR_GPIO20 \
+ ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG)
+
+/* UART0_DTR */
+#define UART0_DTR_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT)
+
+#define UART0_DTR_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT)
+
+/* UART0_RTS */
+#define UART0_RTS_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT)
+
+#define UART0_RTS_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT)
+
+/* UART0_RX */
+#define UART0_RX_GPIO0 \
+ ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO1 \
+ ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO2 \
+ ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO3 \
+ ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO4 \
+ ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO5 \
+ ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO6 \
+ ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO7 \
+ ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO8 \
+ ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO9 \
+ ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO10 \
+ ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO18 \
+ ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO19 \
+ ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG)
+
+#define UART0_RX_GPIO20 \
+ ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG)
+
+/* UART0_TX */
+#define UART0_TX_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT)
+
+#define UART0_TX_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT)
+
+/* UART1_CTS */
+#define UART1_CTS_GPIO0 \
+ ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO1 \
+ ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO2 \
+ ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO3 \
+ ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO4 \
+ ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO5 \
+ ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO6 \
+ ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO7 \
+ ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO8 \
+ ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO9 \
+ ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO10 \
+ ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO18 \
+ ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO19 \
+ ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG)
+
+#define UART1_CTS_GPIO20 \
+ ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG)
+
+/* UART1_DSR */
+#define UART1_DSR_GPIO0 \
+ ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO1 \
+ ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO2 \
+ ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO3 \
+ ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO4 \
+ ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO5 \
+ ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO6 \
+ ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO7 \
+ ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO8 \
+ ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO9 \
+ ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO10 \
+ ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO18 \
+ ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO19 \
+ ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG)
+
+#define UART1_DSR_GPIO20 \
+ ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG)
+
+/* UART1_DTR */
+#define UART1_DTR_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT)
+
+#define UART1_DTR_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT)
+
+/* UART1_RTS */
+#define UART1_RTS_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT)
+
+#define UART1_RTS_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT)
+
+/* UART1_RX */
+#define UART1_RX_GPIO0 \
+ ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO1 \
+ ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO2 \
+ ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO3 \
+ ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO4 \
+ ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO5 \
+ ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO6 \
+ ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO7 \
+ ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO8 \
+ ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO9 \
+ ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO10 \
+ ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO18 \
+ ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO19 \
+ ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG)
+
+#define UART1_RX_GPIO20 \
+ ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG)
+
+/* UART1_TX */
+#define UART1_TX_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT)
+
+#define UART1_TX_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
+
+
+#endif /* INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
index f8713be..d08232b 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
@@ -7897,6 +7897,2182 @@
#define PCNT3_CH1SIG_GPIO48 \
ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+/* SDHC0_CD */
+#define SDHC0_CD_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG)
+
+/* SDHC0_CLKOUT */
+#define SDHC0_CLKOUT_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO11 \
+ ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO12 \
+ ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO13 \
+ ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO14 \
+ ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO15 \
+ ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO16 \
+ ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO17 \
+ ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO21 \
+ ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO26 \
+ ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO27 \
+ ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO28 \
+ ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO29 \
+ ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO30 \
+ ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO31 \
+ ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO32 \
+ ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO33 \
+ ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO34 \
+ ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO35 \
+ ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO36 \
+ ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO37 \
+ ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO38 \
+ ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO39 \
+ ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO40 \
+ ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO41 \
+ ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO42 \
+ ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO43 \
+ ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO44 \
+ ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO45 \
+ ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO46 \
+ ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO47 \
+ ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+#define SDHC0_CLKOUT_GPIO48 \
+ ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1)
+
+/* SDHC0_CMD */
+#define SDHC0_CMD_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+#define SDHC0_CMD_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1)
+
+/* SDHC0_DATA0 */
+#define SDHC0_DATA0_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+#define SDHC0_DATA0_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10)
+
+/* SDHC0_DATA1 */
+#define SDHC0_DATA1_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+#define SDHC0_DATA1_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11)
+
+/* SDHC0_DATA2 */
+#define SDHC0_DATA2_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+#define SDHC0_DATA2_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12)
+
+/* SDHC0_DATA3 */
+#define SDHC0_DATA3_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+#define SDHC0_DATA3_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13)
+
+/* SDHC0_WP */
+#define SDHC0_WP_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG)
+
+/* SDHC1_CD */
+#define SDHC1_CD_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC1_CD_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+/* SDHC1_CLKOUT */
+#define SDHC1_CLKOUT_GPIO0 \
+ ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO1 \
+ ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO2 \
+ ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO3 \
+ ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO4 \
+ ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO5 \
+ ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO6 \
+ ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO7 \
+ ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO8 \
+ ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO9 \
+ ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO10 \
+ ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO11 \
+ ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO12 \
+ ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO13 \
+ ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO14 \
+ ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO15 \
+ ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO16 \
+ ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO17 \
+ ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO18 \
+ ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO19 \
+ ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO20 \
+ ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO21 \
+ ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO26 \
+ ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO27 \
+ ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO28 \
+ ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO29 \
+ ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO30 \
+ ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO31 \
+ ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO32 \
+ ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO33 \
+ ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO34 \
+ ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO35 \
+ ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO36 \
+ ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO37 \
+ ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO38 \
+ ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO39 \
+ ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO40 \
+ ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO41 \
+ ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO42 \
+ ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO43 \
+ ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO44 \
+ ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO45 \
+ ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO46 \
+ ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO47 \
+ ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+#define SDHC1_CLKOUT_GPIO48 \
+ ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2)
+
+/* SDHC1_CMD */
+#define SDHC1_CMD_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+#define SDHC1_CMD_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2)
+
+/* SDHC1_DATA0 */
+#define SDHC1_DATA0_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+#define SDHC1_DATA0_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20)
+
+/* SDHC1_DATA1 */
+#define SDHC1_DATA1_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+#define SDHC1_DATA1_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21)
+
+/* SDHC1_DATA2 */
+#define SDHC1_DATA2_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+#define SDHC1_DATA2_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22)
+
+/* SDHC1_DATA3 */
+#define SDHC1_DATA3_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+#define SDHC1_DATA3_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23)
+
+/* SDHC1_WP */
+#define SDHC1_WP_GPIO0 \
+ ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO1 \
+ ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO2 \
+ ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO3 \
+ ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO4 \
+ ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO5 \
+ ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO6 \
+ ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO7 \
+ ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO8 \
+ ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO9 \
+ ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO10 \
+ ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO11 \
+ ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO12 \
+ ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO13 \
+ ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO14 \
+ ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO15 \
+ ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO16 \
+ ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO17 \
+ ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO18 \
+ ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO19 \
+ ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO20 \
+ ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO21 \
+ ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO26 \
+ ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO27 \
+ ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO28 \
+ ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO29 \
+ ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO30 \
+ ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO31 \
+ ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO32 \
+ ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO33 \
+ ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO34 \
+ ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO35 \
+ ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO36 \
+ ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO37 \
+ ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO38 \
+ ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO39 \
+ ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO40 \
+ ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO41 \
+ ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO42 \
+ ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO43 \
+ ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO44 \
+ ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO45 \
+ ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO46 \
+ ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO47 \
+ ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC1_WP_GPIO48 \
+ ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
/* SPIM2_CSEL */
#define SPIM2_CSEL_GPIO0 \
ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT)
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
new file mode 100644
index 0000000..5d88ea6
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
+#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
+
+#define RA_PORT_NUM_POS 0
+#define RA_PORT_NUM_MASK 0xf
+
+#define RA_PIN_NUM_POS 4
+#define RA_PIN_NUM_MASK 0xf
+
+#define RA_PSEL_HIZ_JTAG_SWD 0x0
+#define RA_PSEL_AGT 0x1
+#define RA_PSEL_GPT0 0x2
+#define RA_PSEL_GPT1 0x3
+#define RA_PSEL_SCI_0 0x4
+#define RA_PSEL_SCI_2 0x4
+#define RA_PSEL_SCI_4 0x4
+#define RA_PSEL_SCI_6 0x4
+#define RA_PSEL_SCI_8 0x4
+#define RA_PSEL_SCI_1 0x5
+#define RA_PSEL_SCI_3 0x5
+#define RA_PSEL_SCI_5 0x5
+#define RA_PSEL_SCI_7 0x5
+#define RA_PSEL_SCI_9 0x5
+#define RA_PSEL_SPI 0x6
+#define RA_PSEL_I2C 0x7
+#define RA_PSEL_CLKOUT_RTC 0x9
+#define RA_PSEL_CAC_ADC 0xa
+#define RA_PSEL_BUS 0xb
+#define RA_PSEL_CANFD 0x10
+#define RA_PSEL_QSPI 0x11
+#define RA_PSEL_SSIE 0x12
+#define RA_PSEL_USBFS 0x13
+#define RA_PSEL_USBHS 0x14
+#define RA_PSEL_SDHI 0x15
+#define RA_PSEL_ETH_MII 0x16
+#define RA_PSEL_ETH_RMII 0x17
+#define RA_PSEL_GLCDC 0x19
+#define RA_PSEL_OSPI 0x1c
+#define RA_PSEL_ADC 0x00
+
+#define RA_PSEL_POS 8
+#define RA_PSEL_MASK 0x1f
+
+#define RA_MODE_POS 13
+#define RA_MODE_MASK 0x1
+
+#define RA_PSEL(psel, port_num, pin_num) \
+ (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \
+ pin_num << RA_PIN_NUM_POS)
+
+#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h
deleted file mode 100644
index a977c6e..0000000
--- a/include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
-#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
-
-#define RA_PORT_NUM_POS 0
-#define RA_PORT_NUM_MASK 0xf
-
-#define RA_PIN_NUM_POS 4
-#define RA_PIN_NUM_MASK 0xf
-
-#define RA_PSEL_HIZ_JTAG_SWD 0x0
-#define RA_PSEL_AGT 0x1
-#define RA_PSEL_GPT0 0x2
-#define RA_PSEL_GPT1 0x3
-#define RA_PSEL_SCI_0 0x4
-#define RA_PSEL_SCI_2 0x4
-#define RA_PSEL_SCI_4 0x4
-#define RA_PSEL_SCI_6 0x4
-#define RA_PSEL_SCI_8 0x4
-#define RA_PSEL_SCI_1 0x5
-#define RA_PSEL_SCI_3 0x5
-#define RA_PSEL_SCI_5 0x5
-#define RA_PSEL_SCI_7 0x5
-#define RA_PSEL_SCI_9 0x5
-#define RA_PSEL_SPI 0x6
-#define RA_PSEL_I2C 0x7
-#define RA_PSEL_CLKOUT_RTC 0x9
-#define RA_PSEL_CAC_ADC 0xa
-#define RA_PSEL_BUS 0xb
-#define RA_PSEL_CANFD 0x10
-#define RA_PSEL_QSPI 0x11
-#define RA_PSEL_SSIE 0x12
-#define RA_PSEL_USBFS 0x13
-#define RA_PSEL_USBHS 0x14
-#define RA_PSEL_SDHI 0x15
-#define RA_PSEL_ETH_MII 0x16
-#define RA_PSEL_ETH_RMII 0x17
-#define RA_PSEL_GLCDC 0x19
-#define RA_PSEL_OSPI 0x1c
-
-#define RA_PSEL_POS 8
-#define RA_PSEL_MASK 0x1f
-
-#define RA_MODE_POS 13
-#define RA_MODE_MASK 0x1
-
-#define RA_PSEL(psel, port_num, pin_num) \
- (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \
- pin_num << RA_PIN_NUM_POS)
-
-#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */
diff --git a/include/zephyr/dt-bindings/pm/imx_spc.h b/include/zephyr/dt-bindings/power/imx_spc.h
similarity index 100%
rename from include/zephyr/dt-bindings/pm/imx_spc.h
rename to include/zephyr/dt-bindings/power/imx_spc.h
diff --git a/include/zephyr/linker/common-ram.ld b/include/zephyr/linker/common-ram.ld
index ecca311..1eef183 100644
--- a/include/zephyr/linker/common-ram.ld
+++ b/include/zephyr/linker/common-ram.ld
@@ -12,6 +12,10 @@
#endif
#endif /* NETWORKING */
+#ifdef CONFIG_ARM_SCMI
+ITERABLE_SECTION_RAM(scmi_protocol, Z_LINK_ITERABLE_SUBALIGN)
+#endif /* CONFIG_ARM_SCMI */
+
#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)
SECTION_DATA_PROLOGUE(sw_isr_table,,)
{
diff --git a/include/zephyr/linker/section_tags.h b/include/zephyr/linker/section_tags.h
index 4c588f7..546ba4e 100644
--- a/include/zephyr/linker/section_tags.h
+++ b/include/zephyr/linker/section_tags.h
@@ -44,6 +44,7 @@
#define __imx_boot_data_section Z_GENERIC_SECTION(_IMX_BOOT_DATA_SECTION_NAME)
#define __imx_boot_ivt_section Z_GENERIC_SECTION(_IMX_BOOT_IVT_SECTION_NAME)
#define __imx_boot_dcd_section Z_GENERIC_SECTION(_IMX_BOOT_DCD_SECTION_NAME)
+#define __imx_boot_container_section Z_GENERIC_SECTION(_IMX_BOOT_CONTAINER_SECTION_NAME)
#define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME)
#define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME)
#define __stm32_backup_sram_section Z_GENERIC_SECTION(_STM32_BACKUP_SRAM_SECTION_NAME)
diff --git a/include/zephyr/linker/sections.h b/include/zephyr/linker/sections.h
index 14aa4c2..1557d72 100644
--- a/include/zephyr/linker/sections.h
+++ b/include/zephyr/linker/sections.h
@@ -67,6 +67,7 @@
#define _IMX_BOOT_DATA_SECTION_NAME .boot_hdr.data
#define _IMX_BOOT_IVT_SECTION_NAME .boot_hdr.ivt
#define _IMX_BOOT_DCD_SECTION_NAME .boot_hdr.dcd_data
+#define _IMX_BOOT_CONTAINER_SECTION_NAME .boot_hdr.container
#define _STM32_SDRAM1_SECTION_NAME .stm32_sdram1
#define _STM32_SDRAM2_SECTION_NAME .stm32_sdram2
diff --git a/include/zephyr/logging/log.h b/include/zephyr/logging/log.h
index f92be9b..7edfca9 100644
--- a/include/zephyr/logging/log.h
+++ b/include/zephyr/logging/log.h
@@ -328,8 +328,7 @@
log_source_const_data, \
Z_LOG_ITEM_CONST_DATA(_name)) = \
{ \
- .name = IS_ENABLED(CONFIG_LOG_FMT_SECTION_STRIP) ? NULL : \
- COND_CODE_1(CONFIG_LOG_FMT_SECTION, \
+ .name = COND_CODE_1(CONFIG_LOG_FMT_SECTION, \
(UTIL_CAT(_name, _str)), (STRINGIFY(_name))), \
.level = (_level) \
}
diff --git a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
index a9e05b5..ac6f01c 100644
--- a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
+++ b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
@@ -8,6 +8,10 @@
#ifndef H_MCUMGR_IMG_MGMT_CALLBACKS_
#define H_MCUMGR_IMG_MGMT_CALLBACKS_
+#include <stdbool.h>
+#include <stdint.h>
+#include <zcbor_common.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -38,6 +42,20 @@
};
/**
+ * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE notification callback: This
+ * callback function is used to allow applications or modules append custom fields to the image
+ * slot state response.
+ */
+struct img_mgmt_state_slot_encode {
+ bool *ok;
+ zcbor_state_t *zse;
+ const uint32_t slot;
+ const char *version;
+ const uint8_t *hash;
+ const int flags;
+};
+
+/**
* @}
*/
diff --git a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
index 194c384..b29bae0 100644
--- a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
+++ b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
@@ -180,6 +180,9 @@
/** Callback when an image write command has finished writing to flash. */
MGMT_EVT_OP_IMG_MGMT_DFU_CHUNK_WRITE_COMPLETE = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 5),
+ /** Callback when an image slot's state is encoded for a response. */
+ MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 6),
+
/** Used to enable all img_mgmt_group events. */
MGMT_EVT_OP_IMG_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_IMG),
};
diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h
index 66ff8d8..88152bc 100644
--- a/include/zephyr/net/buf.h
+++ b/include/zephyr/net/buf.h
@@ -1049,7 +1049,7 @@
/** @endcond */
};
- /** System metadata for this buffer. */
+ /** System metadata for this buffer. Cleared on allocation. */
uint8_t user_data[] __net_buf_align;
};
@@ -1437,8 +1437,7 @@
/**
* @brief Get a buffer from a FIFO.
*
- * This function is NOT thread-safe if the buffers in the FIFO contain
- * fragments.
+ * @deprecated Use @a k_fifo_get() instead.
*
* @param fifo Which FIFO to take the buffer from.
* @param timeout Affects the action taken should the FIFO be empty.
@@ -1448,14 +1447,14 @@
* @return New buffer or NULL if the FIFO is empty.
*/
#if defined(CONFIG_NET_BUF_LOG)
-struct net_buf * __must_check net_buf_get_debug(struct k_fifo *fifo,
- k_timeout_t timeout,
- const char *func, int line);
+__deprecated struct net_buf * __must_check net_buf_get_debug(struct k_fifo *fifo,
+ k_timeout_t timeout,
+ const char *func, int line);
#define net_buf_get(_fifo, _timeout) \
net_buf_get_debug(_fifo, _timeout, __func__, __LINE__)
#else
-struct net_buf * __must_check net_buf_get(struct k_fifo *fifo,
- k_timeout_t timeout);
+__deprecated struct net_buf * __must_check net_buf_get(struct k_fifo *fifo,
+ k_timeout_t timeout);
#endif
/**
@@ -1503,9 +1502,6 @@
/**
* @brief Put a buffer into a list
*
- * If the buffer contains follow-up fragments this function will take care of
- * inserting them as well into the list.
- *
* @param list Which list to append the buffer to.
* @param buf Buffer.
*/
@@ -1514,9 +1510,6 @@
/**
* @brief Get a buffer from a list.
*
- * If the buffer had any fragments, these will automatically be recovered from
- * the list as well and be placed to the buffer's fragment list.
- *
* @param list Which list to take the buffer from.
*
* @return New buffer or NULL if the FIFO is empty.
@@ -1526,13 +1519,12 @@
/**
* @brief Put a buffer to the end of a FIFO.
*
- * If the buffer contains follow-up fragments this function will take care of
- * inserting them as well into the FIFO.
+ * @deprecated Use @a k_fifo_put() instead.
*
* @param fifo Which FIFO to put the buffer to.
* @param buf Buffer.
*/
-void net_buf_put(struct k_fifo *fifo, struct net_buf *buf);
+__deprecated void net_buf_put(struct k_fifo *fifo, struct net_buf *buf);
/**
* @brief Decrements the reference count of a buffer.
diff --git a/include/zephyr/net/lwm2m.h b/include/zephyr/net/lwm2m.h
index ca843fa..d69e508 100644
--- a/include/zephyr/net/lwm2m.h
+++ b/include/zephyr/net/lwm2m.h
@@ -915,21 +915,6 @@
int lwm2m_set_u32(const struct lwm2m_obj_path *path, uint32_t value);
/**
- * @brief Set resource (instance) value (u64)
- *
- * @deprecated Unsigned 64bit value type does not exits.
- * This is internally handled as a int64_t.
- * Use lwm2m_set_s64() instead.
- *
- * @param[in] path LwM2M path as a struct
- * @param[in] value u64 value
- *
- * @return 0 for success or negative in case of error.
- */
-__deprecated
-int lwm2m_set_u64(const struct lwm2m_obj_path *path, uint64_t value);
-
-/**
* @brief Set resource (instance) value (s8)
*
* @param[in] path LwM2M path as a struct
@@ -1108,21 +1093,6 @@
int lwm2m_get_u32(const struct lwm2m_obj_path *path, uint32_t *value);
/**
- * @brief Get resource (instance) value (u64)
- *
- * @deprecated Unsigned 64bit value type does not exits.
- * This is internally handled as a int64_t.
- * Use lwm2m_get_s64() instead.
-
- * @param[in] path LwM2M path as a struct
- * @param[out] value u64 buffer to copy data into
- *
- * @return 0 for success or negative in case of error.
- */
-__deprecated
-int lwm2m_get_u64(const struct lwm2m_obj_path *path, uint64_t *value);
-
-/**
* @brief Get resource (instance) value (s8)
*
* @param[in] path LwM2M path as a struct
diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h
index f3675ab..88a376f 100644
--- a/include/zephyr/net/net_pkt.h
+++ b/include/zephyr/net/net_pkt.h
@@ -123,7 +123,8 @@
struct net_ptp_time timestamp;
#endif
-#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS)
+#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) || \
+ defined(CONFIG_TRACING_NET_CORE)
struct {
/** Create time in cycles */
uint32_t create_time;
@@ -1107,7 +1108,9 @@
}
#endif /* CONFIG_NET_PKT_TIMESTAMP || CONFIG_NET_PKT_TXTIME */
-#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS)
+#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) || \
+ defined(CONFIG_TRACING_NET_CORE)
+
static inline uint32_t net_pkt_create_time(struct net_pkt *pkt)
{
return pkt->create_time;
@@ -1132,7 +1135,9 @@
ARG_UNUSED(pkt);
ARG_UNUSED(create_time);
}
-#endif /* CONFIG_NET_PKT_RXTIME_STATS || CONFIG_NET_PKT_TXTIME_STATS */
+#endif /* CONFIG_NET_PKT_RXTIME_STATS || CONFIG_NET_PKT_TXTIME_STATS ||
+ * CONFIG_TRACING_NET_CORE
+ */
/**
* @deprecated Use @ref net_pkt_timestamp or @ref net_pkt_timestamp_ns instead.
diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h
index ee84bf6..f719ebf 100644
--- a/include/zephyr/net/wifi.h
+++ b/include/zephyr/net/wifi.h
@@ -48,10 +48,18 @@
WIFI_SECURITY_TYPE_PSK_SHA256,
/** WPA3-SAE security. */
WIFI_SECURITY_TYPE_SAE,
+ /** WPA3-SAE security with hunting-and-pecking loop. */
+ WIFI_SECURITY_TYPE_SAE_HNP = WIFI_SECURITY_TYPE_SAE,
+ /** WPA3-SAE security with hash-to-element. */
+ WIFI_SECURITY_TYPE_SAE_H2E,
+ /** WPA3-SAE security with both hunting-and-pecking loop and hash-to-element enabled. */
+ WIFI_SECURITY_TYPE_SAE_AUTO,
/** GB 15629.11-2003 WAPI security. */
WIFI_SECURITY_TYPE_WAPI,
/** EAP security - Enterprise. */
WIFI_SECURITY_TYPE_EAP,
+ /** EAP TLS security - Enterprise. */
+ WIFI_SECURITY_TYPE_EAP_TLS = WIFI_SECURITY_TYPE_EAP,
/** WEP security. */
WIFI_SECURITY_TYPE_WEP,
/** WPA-PSK security. */
@@ -120,6 +128,10 @@
#define WIFI_SAE_PSWD_MAX_LEN 128
/** MAC address length */
#define WIFI_MAC_ADDR_LEN 6
+/** Max enterprise identity length */
+#define WIFI_ENT_IDENTITY_MAX_LEN 64
+/** Max enterprise password length */
+#define WIFI_ENT_PSWD_MAX_LEN 128
/** Minimum channel number */
#define WIFI_CHANNEL_MIN 1
@@ -486,6 +498,20 @@
};
/** @endcond */
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+/** IEEE 802.11v BTM (BSS transition management) Query reasons.
+ * Refer to IEEE Std 802.11v-2011 - Table 7-43x-Transition and Transition Query reasons table.
+ */
+enum wifi_btm_query_reason {
+ /** Unspecified. */
+ WIFI_BTM_QUERY_REASON_UNSPECIFIED = 0,
+ /** Low RSSI. */
+ WIFI_BTM_QUERY_REASON_LOW_RSSI = 16,
+ /** Leaving ESS. */
+ WIFI_BTM_QUERY_REASON_LEAVING_ESS = 20,
+};
+#endif
+
/** Helper function to get user-friendly power save error code name. */
static inline const char *wifi_ps_get_config_err_code_str(int16_t err_no)
{
diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h
index 17425b8..ce03e3d 100644
--- a/include/zephyr/net/wifi_mgmt.h
+++ b/include/zephyr/net/wifi_mgmt.h
@@ -88,12 +88,22 @@
NET_REQUEST_WIFI_CMD_AP_STA_DISCONNECT,
/** Get Wi-Fi driver and Firmware versions */
NET_REQUEST_WIFI_CMD_VERSION,
+ /** Get Wi-Fi latest connection parameters */
+ NET_REQUEST_WIFI_CMD_CONN_PARAMS,
/** Set RTS threshold */
NET_REQUEST_WIFI_CMD_RTS_THRESHOLD,
/** Configure AP parameter */
NET_REQUEST_WIFI_CMD_AP_CONFIG_PARAM,
/** DPP actions */
NET_REQUEST_WIFI_CMD_DPP,
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+ /** BSS transition management query */
+ NET_REQUEST_WIFI_CMD_BTM_QUERY,
+#endif
+ /** Flush PMKSA cache entries */
+ NET_REQUEST_WIFI_CMD_PMKSA_FLUSH,
+ /** Set enterprise mode credential */
+ NET_REQUEST_WIFI_CMD_ENTERPRISE_CREDS,
/** @cond INTERNAL_HIDDEN */
NET_REQUEST_WIFI_CMD_MAX
/** @endcond */
@@ -189,6 +199,12 @@
NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_VERSION);
+/** Request a Wi-Fi connection parameters */
+#define NET_REQUEST_WIFI_CONN_PARAMS \
+ (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_CONN_PARAMS)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_CONN_PARAMS);
+
/** Request a Wi-Fi RTS threshold */
#define NET_REQUEST_WIFI_RTS_THRESHOLD \
(_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_RTS_THRESHOLD)
@@ -207,6 +223,25 @@
NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_DPP);
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+/** Request a Wi-Fi BTM query */
+#define NET_REQUEST_WIFI_BTM_QUERY (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_BTM_QUERY)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_BTM_QUERY);
+#endif
+
+/** Request a Wi-Fi PMKSA cache entries flush */
+#define NET_REQUEST_WIFI_PMKSA_FLUSH \
+ (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_PMKSA_FLUSH)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_PMKSA_FLUSH);
+
+/** Set Wi-Fi enterprise mode CA/client Cert and key */
+#define NET_REQUEST_WIFI_ENTERPRISE_CREDS \
+ (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_ENTERPRISE_CREDS)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_ENTERPRISE_CREDS);
+
/** @brief Wi-Fi management events */
enum net_event_wifi_cmd {
/** Scan results available */
@@ -411,6 +446,14 @@
uint8_t bssid[WIFI_MAC_ADDR_LEN];
/** Connect timeout in seconds, SYS_FOREVER_MS for no timeout */
int timeout;
+ /** anonymous identity */
+ const uint8_t *anon_id;
+ /** anon_id length */
+ uint8_t aid_length; /* Max 64 */
+ /** Private key passwd for enterprise mode */
+ const uint8_t *key_passwd;
+ /** Private key passwd length */
+ uint8_t key_passwd_length; /* Max 128 */
};
/** @brief Wi-Fi connect result codes. To be overlaid on top of \ref wifi_status
@@ -634,6 +677,22 @@
uint32_t twt_wake_ahead_duration;
};
+/** Wi-Fi enterprise mode credentials */
+struct wifi_enterprise_creds_params {
+ /** CA certification */
+ uint8_t *ca_cert;
+ /** CA certification length */
+ uint32_t ca_cert_len;
+ /** Client certification */
+ uint8_t *client_cert;
+ /** Client certification length */
+ uint32_t client_cert_len;
+ /** Client key */
+ uint8_t *client_key;
+ /** Client key length */
+ uint32_t client_key_len;
+};
+
/** @brief Wi-Fi power save configuration */
struct wifi_ps_config {
/** Number of TWT flows */
@@ -1110,6 +1169,16 @@
* @return 0 if ok, < 0 if error
*/
int (*channel)(const struct device *dev, struct wifi_channel_info *channel);
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+ /** Send BTM query
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reason query reason
+ *
+ * @return 0 if ok, < 0 if error
+ */
+ int (*btm_query)(const struct device *dev, uint8_t reason);
+#endif
/** Get Version of WiFi driver and Firmware
*
* The driver that implements the get_version function must not use stack to allocate the
@@ -1123,6 +1192,14 @@
* @return 0 if ok, < 0 if error
*/
int (*get_version)(const struct device *dev, struct wifi_version *params);
+ /** Get Wi-Fi connection parameters recently used
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param params the Wi-Fi connection parameters recently used
+ *
+ * @return 0 if ok, < 0 if error
+ */
+ int (*get_conn_params)(const struct device *dev, struct wifi_connect_req_params *params);
/** Set RTS threshold value
*
* @param dev Pointer to the device structure for the driver instance.
@@ -1147,6 +1224,24 @@
* @return 0 if ok, < 0 if error
*/
int (*dpp_dispatch)(const struct device *dev, struct wifi_dpp_params *params);
+ /** Flush PMKSA cache entries
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @return 0 if ok, < 0 if error
+ */
+ int (*pmksa_flush)(const struct device *dev);
+ /** Set Wi-Fi enterprise mode CA/client Cert and key
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param creds Pointer to the CA/client Cert and key.
+ *
+ * @return 0 if ok, < 0 if error
+ */
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+ int (*enterprise_creds)(const struct device *dev,
+ struct wifi_enterprise_creds_params *creds);
+#endif
};
/** Wi-Fi management offload API */
diff --git a/include/zephyr/posix/unistd.h b/include/zephyr/posix/unistd.h
index 2d1e024..96ea524 100644
--- a/include/zephyr/posix/unistd.h
+++ b/include/zephyr/posix/unistd.h
@@ -44,6 +44,7 @@
int unlink(const char *path);
int stat(const char *path, struct stat *buf);
int mkdir(const char *path, mode_t mode);
+int rmdir(const char *path);
FUNC_NORETURN void _exit(int status);
diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h
index 1bb3a84..54e3c7f 100644
--- a/include/zephyr/rtio/rtio.h
+++ b/include/zephyr/rtio/rtio.h
@@ -253,30 +253,36 @@
union {
- /** OP_TX, OP_RX */
+ /** OP_TX */
struct {
uint32_t buf_len; /**< Length of buffer */
- uint8_t *buf; /**< Buffer to use*/
- };
+ const uint8_t *buf; /**< Buffer to write from */
+ } tx;
+
+ /** OP_RX */
+ struct {
+ uint32_t buf_len; /**< Length of buffer */
+ uint8_t *buf; /**< Buffer to read into */
+ } rx;
/** OP_TINY_TX */
struct {
- uint8_t tiny_buf_len; /**< Length of tiny buffer */
- uint8_t tiny_buf[7]; /**< Tiny buffer */
- };
+ uint8_t buf_len; /**< Length of tiny buffer */
+ uint8_t buf[7]; /**< Tiny buffer */
+ } tiny_tx;
/** OP_CALLBACK */
struct {
rtio_callback_t callback;
void *arg0; /**< Last argument given to callback */
- };
+ } callback;
/** OP_TXRX */
struct {
- uint32_t txrx_buf_len;
- uint8_t *tx_buf;
- uint8_t *rx_buf;
- };
+ uint32_t buf_len; /**< Length of tx and rx buffers */
+ const uint8_t *tx_buf; /**< Buffer to write from */
+ uint8_t *rx_buf; /**< Buffer to read into */
+ } txrx;
/** OP_I2C_CONFIGURE */
uint32_t i2c_config;
@@ -504,8 +510,8 @@
sqe->op = RTIO_OP_RX;
sqe->prio = prio;
sqe->iodev = iodev;
- sqe->buf_len = len;
- sqe->buf = buf;
+ sqe->rx.buf_len = len;
+ sqe->rx.buf = buf;
sqe->userdata = userdata;
}
@@ -536,7 +542,7 @@
static inline void rtio_sqe_prep_write(struct rtio_sqe *sqe,
const struct rtio_iodev *iodev,
int8_t prio,
- uint8_t *buf,
+ const uint8_t *buf,
uint32_t len,
void *userdata)
{
@@ -544,8 +550,8 @@
sqe->op = RTIO_OP_TX;
sqe->prio = prio;
sqe->iodev = iodev;
- sqe->buf_len = len;
- sqe->buf = buf;
+ sqe->tx.buf_len = len;
+ sqe->tx.buf = buf;
sqe->userdata = userdata;
}
@@ -566,14 +572,14 @@
uint8_t tiny_write_len,
void *userdata)
{
- __ASSERT_NO_MSG(tiny_write_len <= sizeof(sqe->tiny_buf));
+ __ASSERT_NO_MSG(tiny_write_len <= sizeof(sqe->tiny_tx.buf));
memset(sqe, 0, sizeof(struct rtio_sqe));
sqe->op = RTIO_OP_TINY_TX;
sqe->prio = prio;
sqe->iodev = iodev;
- sqe->tiny_buf_len = tiny_write_len;
- memcpy(sqe->tiny_buf, tiny_write_data, tiny_write_len);
+ sqe->tiny_tx.buf_len = tiny_write_len;
+ memcpy(sqe->tiny_tx.buf, tiny_write_data, tiny_write_len);
sqe->userdata = userdata;
}
@@ -594,8 +600,8 @@
sqe->op = RTIO_OP_CALLBACK;
sqe->prio = 0;
sqe->iodev = NULL;
- sqe->callback = callback;
- sqe->arg0 = arg0;
+ sqe->callback.callback = callback;
+ sqe->callback.arg0 = arg0;
sqe->userdata = userdata;
}
@@ -605,7 +611,7 @@
static inline void rtio_sqe_prep_transceive(struct rtio_sqe *sqe,
const struct rtio_iodev *iodev,
int8_t prio,
- uint8_t *tx_buf,
+ const uint8_t *tx_buf,
uint8_t *rx_buf,
uint32_t buf_len,
void *userdata)
@@ -614,9 +620,9 @@
sqe->op = RTIO_OP_TXRX;
sqe->prio = prio;
sqe->iodev = iodev;
- sqe->txrx_buf_len = buf_len;
- sqe->tx_buf = tx_buf;
- sqe->rx_buf = rx_buf;
+ sqe->txrx.buf_len = buf_len;
+ sqe->txrx.tx_buf = tx_buf;
+ sqe->txrx.rx_buf = rx_buf;
sqe->userdata = userdata;
}
@@ -696,6 +702,10 @@
return 0;
}
+ if (bytes <= block_size) {
+ break;
+ }
+
bytes -= block_size;
} while (bytes >= min_sz);
@@ -1036,9 +1046,9 @@
if (iodev_sqe->sqe.op == RTIO_OP_RX && iodev_sqe->sqe.flags & RTIO_SQE_MEMPOOL_BUFFER) {
struct rtio *r = iodev_sqe->r;
struct sys_mem_blocks *mem_pool = r->block_pool;
- int blk_index = (iodev_sqe->sqe.buf - mem_pool->buffer) >>
+ int blk_index = (iodev_sqe->sqe.rx.buf - mem_pool->buffer) >>
mem_pool->info.blk_sz_shift;
- int blk_count = iodev_sqe->sqe.buf_len >> mem_pool->info.blk_sz_shift;
+ int blk_count = iodev_sqe->sqe.rx.buf_len >> mem_pool->info.blk_sz_shift;
flags = RTIO_CQE_FLAG_PREP_MEMPOOL(blk_index, blk_count);
}
@@ -1185,19 +1195,19 @@
if (sqe->op == RTIO_OP_RX && sqe->flags & RTIO_SQE_MEMPOOL_BUFFER) {
struct rtio *r = iodev_sqe->r;
- if (sqe->buf != NULL) {
- if (sqe->buf_len < min_buf_len) {
+ if (sqe->rx.buf != NULL) {
+ if (sqe->rx.buf_len < min_buf_len) {
return -ENOMEM;
}
- *buf = sqe->buf;
- *buf_len = sqe->buf_len;
+ *buf = sqe->rx.buf;
+ *buf_len = sqe->rx.buf_len;
return 0;
}
int rc = rtio_block_pool_alloc(r, min_buf_len, max_buf_len, buf, buf_len);
if (rc == 0) {
- sqe->buf = *buf;
- sqe->buf_len = *buf_len;
+ sqe->rx.buf = *buf;
+ sqe->rx.buf_len = *buf_len;
return 0;
}
@@ -1207,12 +1217,12 @@
ARG_UNUSED(max_buf_len);
#endif
- if (sqe->buf_len < min_buf_len) {
+ if (sqe->rx.buf_len < min_buf_len) {
return -ENOMEM;
}
- *buf = sqe->buf;
- *buf_len = sqe->buf_len;
+ *buf = sqe->rx.buf;
+ *buf_len = sqe->rx.buf_len;
return 0;
}
@@ -1381,12 +1391,7 @@
cqe = K_TIMEOUT_EQ(timeout, K_FOREVER) ? rtio_cqe_consume_block(r)
: rtio_cqe_consume(r);
if (cqe == NULL) {
-#ifdef CONFIG_BOARD_NATIVE_POSIX
- /* Native posix fakes the clock and only moves it forward when sleeping. */
- k_sleep(K_TICKS(1));
-#else
- Z_SPIN_DELAY(1);
-#endif
+ Z_SPIN_DELAY(25);
continue;
}
cqes[copied++] = *cqe;
diff --git a/include/zephyr/shell/shell.h b/include/zephyr/shell/shell.h
index fb811cc..7c88231 100644
--- a/include/zephyr/shell/shell.h
+++ b/include/zephyr/shell/shell.h
@@ -191,7 +191,7 @@
char **argv, void *data);
/* When entries are added to the memory section a padding is applied for
- * native_posix_64 and x86_64 targets. Adding padding to allow handle data
+ * the posix architecture with 64bits builds and x86_64 targets. Adding padding to allow handle data
* in the memory section as array.
*/
#if (defined(CONFIG_ARCH_POSIX) && defined(CONFIG_64BIT)) || defined(CONFIG_X86_64)
diff --git a/include/zephyr/sys/sys_heap.h b/include/zephyr/sys/sys_heap.h
index a6a868b..f01bae1 100644
--- a/include/zephyr/sys/sys_heap.h
+++ b/include/zephyr/sys/sys_heap.h
@@ -10,6 +10,7 @@
#include <stdbool.h>
#include <zephyr/types.h>
#include <zephyr/sys/mem_stats.h>
+#include <zephyr/toolchain.h>
#ifdef __cplusplus
extern "C" {
@@ -209,7 +210,15 @@
* @param heap Heap to validate
* @return true, if the heap is valid, otherwise false
*/
+#ifdef CONFIG_SYS_HEAP_VALIDATE
bool sys_heap_validate(struct sys_heap *heap);
+#else
+static inline bool sys_heap_validate(struct sys_heap *heap)
+{
+ ARG_UNUSED(heap);
+ return true;
+}
+#endif
/** @brief sys_heap stress test rig
*
diff --git a/include/zephyr/sys/util.h b/include/zephyr/sys/util.h
index a542e3f..ce44e18 100644
--- a/include/zephyr/sys/util.h
+++ b/include/zephyr/sys/util.h
@@ -377,13 +377,6 @@
((((n) < 0) ^ ((d) < 0)) ? ((n) - ((d) / 2)) / (d) : \
((n) + ((d) / 2)) / (d))
-/**
- * @brief Ceiling function applied to @p numerator / @p divider as a fraction.
- * @deprecated Use DIV_ROUND_UP() instead.
- */
-#define ceiling_fraction(numerator, divider) __DEPRECATED_MACRO \
- DIV_ROUND_UP(numerator, divider)
-
#ifndef MAX
/**
* @brief Obtain the maximum of two values.
diff --git a/include/zephyr/toolchain/gcc.h b/include/zephyr/toolchain/gcc.h
index 9af23fb..b592eb0 100644
--- a/include/zephyr/toolchain/gcc.h
+++ b/include/zephyr/toolchain/gcc.h
@@ -250,6 +250,9 @@
#ifndef __deprecated
#define __deprecated __attribute__((deprecated))
+/* When adding this, remember to follow the instructions in
+ * https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated
+ */
#endif
#ifndef __attribute_const__
@@ -312,6 +315,9 @@
/* Generic message */
#ifndef __DEPRECATED_MACRO
#define __DEPRECATED_MACRO __WARN("Macro is deprecated")
+/* When adding this, remember to follow the instructions in
+ * https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated
+ */
#endif
/* These macros allow having ARM asm functions callable from thumb */
diff --git a/include/zephyr/tracing/tracing.h b/include/zephyr/tracing/tracing.h
index 3e1f998..e969c4e 100644
--- a/include/zephyr/tracing/tracing.h
+++ b/include/zephyr/tracing/tracing.h
@@ -2029,6 +2029,56 @@
/** @} */ /* end of subsys_tracing_apis_pm_device_runtime */
/**
+ * @brief Network Core Tracing APIs
+ * @defgroup subsys_tracing_apis_net Network Core Tracing APIs
+ * @{
+ */
+
+/**
+ * @brief Trace network data receive
+ * @param iface Network interface
+ * @param pkt Received network packet
+ */
+#define sys_port_trace_net_recv_data_enter(iface, pkt)
+
+/**
+ * @brief Trace network data receive attempt
+ * @param iface Network interface
+ * @param pkt Received network packet
+ * @param ret Return value
+ */
+#define sys_port_trace_net_recv_data_exit(iface, pkt, ret)
+
+/**
+ * @brief Trace network data send
+ * @param pkt Network packet to send
+ */
+#define sys_port_trace_net_send_data_enter(pkt)
+
+/**
+ * @brief Trace network data send attempt
+ * @param pkt Received network packet
+ * @param ret Return value
+ */
+#define sys_port_trace_net_send_data_exit(pkt, ret)
+
+/**
+ * @brief Trace network data receive time
+ * @param pkt Received network packet
+ * @param end_time When the RX processing stopped for this pkt (in ticks)
+ */
+#define sys_port_trace_net_rx_time(pkt, end_time)
+
+/**
+ * @brief Trace network data sent time
+ * @param pkt Sent network packet
+ * @param end_time When the TX processing stopped for this pkt (in ticks)
+ */
+#define sys_port_trace_net_tx_time(pkt, end_time)
+
+/** @} */ /* end of subsys_tracing_apis_net */
+
+/**
* @brief Network Socket Tracing APIs
* @defgroup subsys_tracing_apis_socket Network Socket Tracing APIs
* @{
diff --git a/include/zephyr/tracing/tracing_macros.h b/include/zephyr/tracing/tracing_macros.h
index 80eed3d..7e6c8d7 100644
--- a/include/zephyr/tracing/tracing_macros.h
+++ b/include/zephyr/tracing/tracing_macros.h
@@ -185,12 +185,18 @@
#define sys_port_trace_pm_is_disabled 1
#endif
-#if defined(CONFIG_TRACING_NETWORKING)
+#if defined(CONFIG_TRACING_NET_SOCKETS)
#define sys_port_trace_type_mask_socket(trace_call) trace_call
#else
#define sys_port_trace_type_mask_socket(trace_call)
#endif
+#if defined(CONFIG_TRACING_NET_CORE)
+ #define sys_port_trace_type_mask_net(trace_call) trace_call
+#else
+ #define sys_port_trace_type_mask_net(trace_call)
+#endif
+
/*
* We cannot positively enumerate all traced APIs, as applications may trace
* arbitrary custom APIs we know nothing about. Therefore we demand that tracing
diff --git a/include/zephyr/usb/msos_desc.h b/include/zephyr/usb/msos_desc.h
index 372c8aa..895675d 100644
--- a/include/zephyr/usb/msos_desc.h
+++ b/include/zephyr/usb/msos_desc.h
@@ -99,4 +99,33 @@
'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, \
'D', 0x00, 's', 0x00, 0x00, 0x00
+/* Microsoft OS 2.0 minimum USB resume time descriptor */
+struct msosv2_resume_time {
+ uint16_t wLength;
+ uint16_t wDescriptorType;
+ uint8_t bResumeRecoveryTime;
+ uint8_t bResumeSignalingTime;
+} __packed;
+
+/* Microsoft OS 2.0 model ID descriptor */
+struct msosv2_model_id {
+ uint16_t wLength;
+ uint16_t wDescriptorType;
+ uint8_t ModelID[16];
+} __packed;
+
+/* Microsoft OS 2.0 CCGP device descriptor */
+struct msosv2_ccgp_device {
+ uint16_t wLength;
+ uint16_t wDescriptorType;
+} __packed;
+
+/* Microsoft OS 2.0 vendor revision descriptor */
+struct msosv2_vendor_revision {
+ uint16_t wLength;
+ uint16_t wDescriptorType;
+ uint16_t VendorRevision;
+} __packed;
+
+
#endif /* ZEPHYR_INCLUDE_USB_MSOS_DESC_H */
diff --git a/include/zephyr/usb/usb_ch9.h b/include/zephyr/usb/usb_ch9.h
index dccc744..ecd9705e 100644
--- a/include/zephyr/usb/usb_ch9.h
+++ b/include/zephyr/usb/usb_ch9.h
@@ -348,6 +348,29 @@
/** Calculate high speed isochronous endpoint bInterval from a value in microseconds */
#define USB_HS_ISO_EP_INTERVAL(us) CLAMP((ilog2((us) / 125U) + 1U), 1U, 16U)
+/** Get endpoint size field from Max Packet Size value */
+#define USB_MPS_EP_SIZE(mps) ((mps) & BIT_MASK(11))
+
+/** Get number of additional transactions per microframe from Max Packet Size value */
+#define USB_MPS_ADDITIONAL_TRANSACTIONS(mps) (((mps) & 0x1800) >> 11)
+
+/** Calculate total payload length from Max Packet Size value */
+#define USB_MPS_TO_TPL(mps) \
+ ((1 + USB_MPS_ADDITIONAL_TRANSACTIONS(mps)) * USB_MPS_EP_SIZE(mps))
+
+/** Calculate Max Packet Size value from total payload length */
+#define USB_TPL_TO_MPS(tpl) \
+ (((tpl) > 2048) ? ((2 << 11) | ((tpl) / 3)) : \
+ ((tpl) > 1024) ? ((1 << 11) | ((tpl) / 2)) : \
+ (tpl))
+
+/** Determine whether total payload length value is valid according to USB 2.0 */
+#define USB_TPL_IS_VALID(tpl) \
+ (((tpl) > 3072) ? false : \
+ ((tpl) > 2048) ? ((tpl) % 3 == 0) : \
+ ((tpl) > 1024) ? ((tpl) % 2 == 0) : \
+ ((tpl) >= 0))
+
#ifdef __cplusplus
}
#endif
diff --git a/include/zephyr/usb/usbd_msg.h b/include/zephyr/usb/usbd_msg.h
index 13d0f01..cec39dc 100644
--- a/include/zephyr/usb/usbd_msg.h
+++ b/include/zephyr/usb/usbd_msg.h
@@ -40,6 +40,8 @@
USBD_MSG_SUSPEND,
/** Bus reset detected */
USBD_MSG_RESET,
+ /** Device changed configuration */
+ USBD_MSG_CONFIGURATION,
/** Non-correctable UDC error message */
USBD_MSG_UDC_ERROR,
/** Unrecoverable device stack error message */
@@ -61,6 +63,7 @@
"Device resumed",
"Device suspended",
"Bus reset",
+ "New device configuration",
"Controller error",
"Stack error",
"CDC ACM line coding",
diff --git a/kernel/mmu.c b/kernel/mmu.c
index 5b080dd..a61c6dc 100644
--- a/kernel/mmu.c
+++ b/kernel/mmu.c
@@ -575,29 +575,35 @@
uint8_t *pos;
bool uninit = (flags & K_MEM_MAP_UNINIT) != 0U;
- __ASSERT(!(((flags & K_MEM_PERM_USER) != 0U) &&
- ((flags & K_MEM_MAP_UNINIT) != 0U)),
- "user access to anonymous uninitialized pages is forbidden");
- __ASSERT(size % CONFIG_MMU_PAGE_SIZE == 0U,
- "unaligned size %zu passed to %s", size, __func__);
- __ASSERT(size != 0, "zero sized memory mapping");
__ASSERT(!is_anon || (is_anon && page_frames_initialized),
"%s called too early", __func__);
__ASSERT((flags & K_MEM_CACHE_MASK) == 0U,
"%s does not support explicit cache settings", __func__);
- CHECKIF(size_add_overflow(size, CONFIG_MMU_PAGE_SIZE * 2, &total_size)) {
+ if (((flags & K_MEM_PERM_USER) != 0U) &&
+ ((flags & K_MEM_MAP_UNINIT) != 0U)) {
+ LOG_ERR("user access to anonymous uninitialized pages is forbidden");
+ return NULL;
+ }
+ if ((size % CONFIG_MMU_PAGE_SIZE) != 0U) {
+ LOG_ERR("unaligned size %zu passed to %s", size, __func__);
+ return NULL;
+ }
+ if (size == 0) {
+ LOG_ERR("zero sized memory mapping");
+ return NULL;
+ }
+
+ /* Need extra for the guard pages (before and after) which we
+ * won't map.
+ */
+ if (size_add_overflow(size, CONFIG_MMU_PAGE_SIZE * 2, &total_size)) {
LOG_ERR("too large size %zu passed to %s", size, __func__);
return NULL;
}
key = k_spin_lock(&z_mm_lock);
- /* Need extra for the guard pages (before and after) which we
- * won't map.
- */
- total_size = size + (CONFIG_MMU_PAGE_SIZE * 2);
-
dst = virt_region_alloc(total_size, CONFIG_MMU_PAGE_SIZE);
if (dst == NULL) {
/* Address space has no free region */
@@ -881,8 +887,9 @@
num_bits = adjusted_sz / CONFIG_MMU_PAGE_SIZE;
offset = virt_to_bitmap_offset(adjusted_start, adjusted_sz);
if (sys_bitarray_test_and_set_region(
- &virt_region_bitmap, num_bits, offset, true))
+ &virt_region_bitmap, num_bits, offset, true)) {
goto fail;
+ }
}
} else {
/* Obtain an appropriately sized chunk of virtual memory */
diff --git a/kernel/msg_q.c b/kernel/msg_q.c
index 0c46109..0397504 100644
--- a/kernel/msg_q.c
+++ b/kernel/msg_q.c
@@ -4,6 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 12
+
/**
* @file
* @brief Message queues.
diff --git a/kernel/poll.c b/kernel/poll.c
index 502e975..076f695 100644
--- a/kernel/poll.c
+++ b/kernel/poll.c
@@ -5,6 +5,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
+/*
+ * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
+ * #line marks the *next* line, so it is off by one.
+ */
+#line 13
+
/**
* @file
*
diff --git a/lib/crc/crc24_sw.c b/lib/crc/crc24_sw.c
index 3e9b48f..78c2c05 100644
--- a/lib/crc/crc24_sw.c
+++ b/lib/crc/crc24_sw.c
@@ -22,8 +22,9 @@
crc ^= (*data++) << 16;
for (i = 0; i < 8; i++) {
crc <<= 1;
- if (crc & 0x01000000)
+ if (crc & 0x01000000) {
crc ^= CRC24_PGP_POLY;
+ }
}
}
diff --git a/lib/libc/common/CMakeLists.txt b/lib/libc/common/CMakeLists.txt
index 64fe33d..ed3d28f 100644
--- a/lib/libc/common/CMakeLists.txt
+++ b/lib/libc/common/CMakeLists.txt
@@ -5,7 +5,10 @@
zephyr_library()
zephyr_library_property(ALLOW_EMPTY TRUE)
zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_ABORT source/stdlib/abort.c)
+zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_ASCTIME source/time/asctime.c)
zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_GMTIME_R source/time/gmtime_r.c)
+zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_LOCALTIME_R_UTC source/time/localtime_r_utc.c)
+zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_CTIME source/time/ctime.c)
zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_TIME source/time/time.c)
zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_MALLOC source/stdlib/malloc.c)
zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_STRNLEN source/string/strnlen.c)
@@ -16,6 +19,7 @@
source/thrd/thrd.c
source/thrd/tss.c
)
+zephyr_library_sources_ifdef(CONFIG_COMMON_LIBC_REMOVE source/stdio/remove.c)
# Prevent compiler from optimizing calloc into an infinite recursive call
zephyr_library_compile_options($<TARGET_PROPERTY:compiler,no_builtin_malloc>)
diff --git a/lib/libc/common/Kconfig b/lib/libc/common/Kconfig
index ea0d686..1e65ce3 100644
--- a/lib/libc/common/Kconfig
+++ b/lib/libc/common/Kconfig
@@ -6,11 +6,44 @@
help
common implementation of abort().
+config COMMON_LIBC_ASCTIME
+ bool
+ help
+ common implementation of asctime().
+
+config COMMON_LIBC_ASCTIME_R
+ bool "Thread-safe version of asctime()"
+ default y if POSIX_THREAD_SAFE_FUNCTIONS
+ select COMMON_LIBC_ASCTIME
+ help
+ common implementation of asctime_r().
+
+config COMMON_LIBC_CTIME
+ bool
+ select COMMON_LIBC_LOCALTIME_R_UTC
+ help
+ common implementation of ctime().
+
+config COMMON_LIBC_CTIME_R
+ bool "Thread-safe version of ctime()"
+ default y if POSIX_THREAD_SAFE_FUNCTIONS
+ select COMMON_LIBC_CTIME
+ help
+ common implementation of ctime_r().
+
config COMMON_LIBC_GMTIME_R
bool
help
common implementation of gmtime_r().
+config COMMON_LIBC_LOCALTIME_R_UTC
+ bool
+ select COMMON_LIBC_GMTIME_R
+ help
+ Simple implementation of localtime() & localtime_r().
+ This option just wraps around the gmtime(), the result is always expressed as
+ Coordinated Universal Time (UTC).
+
config COMMON_LIBC_TIME
bool
help
@@ -82,3 +115,10 @@
default y
help
Common implementation of C11 <threads.h> API.
+
+config COMMON_LIBC_REMOVE
+ bool "Common C library remove"
+ depends on !SEMIHOST
+ default y if FILE_SYSTEM
+ help
+ Common implementation of remove().
diff --git a/lib/libc/common/source/stdio/remove.c b/lib/libc/common/source/stdio/remove.c
new file mode 100644
index 0000000..5616920
--- /dev/null
+++ b/lib/libc/common/source/stdio/remove.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024 Linumiz.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <zephyr/fs/fs.h>
+#include <zephyr/sys/util_macro.h>
+
+/**
+ *
+ * @brief deletes a name from the filesystem
+ *
+ * @return On success, zero is returned. On error, -1 is returned
+ * and errno is set to indicate the error.
+ */
+
+int remove(const char *path)
+{
+ if (!IS_ENABLED(CONFIG_FILE_SYSTEM)) {
+ errno = ENOTSUP;
+ return -1;
+ }
+
+ int ret = fs_unlink(path);
+
+ if (ret < 0) {
+ errno = -ret;
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/lib/libc/common/source/time/asctime.c b/lib/libc/common/source/time/asctime.c
new file mode 100644
index 0000000..aea84cf
--- /dev/null
+++ b/lib/libc/common/source/time/asctime.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+
+#include <zephyr/sys/util.h>
+
+#define DATE_STRING_BUF_SZ 26U
+#define DATE_WDAY_STRING_SZ 7U
+#define DATE_MON_STRING_SZ 12U
+#define DATE_TM_YEAR_BASE 1900
+
+static char *asctime_impl(const struct tm *tp, char *buf)
+{
+ static const char wday_str[DATE_WDAY_STRING_SZ][3] = {
+ "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat",
+ };
+ static const char mon_str[DATE_MON_STRING_SZ][3] = {
+ "Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec",
+ };
+
+ if ((buf == NULL) || (tp == NULL) || ((unsigned int)tp->tm_wday >= DATE_WDAY_STRING_SZ) ||
+ ((unsigned int)tp->tm_mon >= DATE_MON_STRING_SZ)) {
+ return NULL;
+ }
+
+ unsigned int n = (unsigned int)snprintf(
+ buf, DATE_STRING_BUF_SZ, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n", wday_str[tp->tm_wday],
+ mon_str[tp->tm_mon], tp->tm_mday, tp->tm_hour, tp->tm_min, tp->tm_sec,
+ DATE_TM_YEAR_BASE + tp->tm_year);
+
+ if (n >= DATE_STRING_BUF_SZ) {
+ return NULL;
+ }
+
+ return buf;
+}
+
+char *asctime(const struct tm *tp)
+{
+ static char buf[DATE_STRING_BUF_SZ];
+
+ return asctime_impl(tp, buf);
+}
+
+#if defined(CONFIG_COMMON_LIBC_ASCTIME_R)
+char *asctime_r(const struct tm *tp, char *buf)
+{
+ return asctime_impl(tp, buf);
+}
+#endif /* CONFIG_COMMON_LIBC_ASCTIME_R */
diff --git a/lib/libc/common/source/time/ctime.c b/lib/libc/common/source/time/ctime.c
new file mode 100644
index 0000000..454feb3
--- /dev/null
+++ b/lib/libc/common/source/time/ctime.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <time.h>
+
+/**
+ * `ctime()` is equivalent to `asctime(localtime(clock))`
+ * See: https://pubs.opengroup.org/onlinepubs/009695399/functions/ctime.html
+ */
+
+char *ctime(const time_t *clock)
+{
+ return asctime(localtime(clock));
+}
+
+#if defined(CONFIG_COMMON_LIBC_CTIME_R)
+char *ctime_r(const time_t *clock, char *buf)
+{
+ struct tm tmp;
+
+ return asctime_r(localtime_r(clock, &tmp), buf);
+}
+#endif /* CONFIG_COMMON_LIBC_CTIME_R */
diff --git a/lib/libc/common/source/time/localtime_r_utc.c b/lib/libc/common/source/time/localtime_r_utc.c
new file mode 100644
index 0000000..7a17dcf
--- /dev/null
+++ b/lib/libc/common/source/time/localtime_r_utc.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <time.h>
+
+struct tm *localtime_r(const time_t *timer, struct tm *result)
+{
+ return gmtime_r(timer, result);
+}
+
+struct tm *localtime(const time_t *timer)
+{
+ return gmtime(timer);
+}
diff --git a/lib/libc/minimal/Kconfig b/lib/libc/minimal/Kconfig
index 40aa95a..0b99994 100644
--- a/lib/libc/minimal/Kconfig
+++ b/lib/libc/minimal/Kconfig
@@ -39,6 +39,9 @@
bool "Time functions"
select COMMON_LIBC_TIME if POSIX_TIMERS
select COMMON_LIBC_GMTIME_R
+ select COMMON_LIBC_ASCTIME
+ select COMMON_LIBC_LOCALTIME_R_UTC
+ select COMMON_LIBC_CTIME
default y
help
Enable time() and gmtime_r() for the minimal libc.
diff --git a/lib/libc/minimal/include/stdio.h b/lib/libc/minimal/include/stdio.h
index db3c897..12b53ae 100644
--- a/lib/libc/minimal/include/stdio.h
+++ b/lib/libc/minimal/include/stdio.h
@@ -60,6 +60,7 @@
int fputs(const char *ZRESTRICT s, FILE *ZRESTRICT stream);
size_t fwrite(const void *ZRESTRICT ptr, size_t size, size_t nitems,
FILE *ZRESTRICT stream);
+int remove(const char *path);
#define putc(c, stream) fputc(c, stream)
#define putchar(c) putc(c, stdout)
diff --git a/lib/libc/minimal/include/time.h b/lib/libc/minimal/include/time.h
index e0dae58..62ec45b 100644
--- a/lib/libc/minimal/include/time.h
+++ b/lib/libc/minimal/include/time.h
@@ -45,12 +45,22 @@
/*
* Conversion between civil time and UNIX time. The companion
- * localtime() and inverse mktime() are not provided here since they
+ * mktime() is not provided here since it
* require access to time zone information.
+ *
+ * The localtime() & localtime_r() simply
+ * wraps around the gmtime() & gmtime_r() functions, the
+ * results are always expressed as UTC.
*/
struct tm *gmtime(const time_t *timep);
struct tm *gmtime_r(const time_t *ZRESTRICT timep,
struct tm *ZRESTRICT result);
+char *asctime(const struct tm *timeptr);
+struct tm *localtime(const time_t *timer);
+char *ctime(const time_t *clock);
+char *asctime_r(const struct tm *ZRESTRICT tp, char *ZRESTRICT buf);
+char *ctime_r(const time_t *clock, char *buf);
+struct tm *localtime_r(const time_t *ZRESTRICT timer, struct tm *ZRESTRICT result);
time_t time(time_t *tloc);
diff --git a/lib/posix/options/Kconfig b/lib/posix/options/Kconfig
index f3b6bda..f453f52 100644
--- a/lib/posix/options/Kconfig
+++ b/lib/posix/options/Kconfig
@@ -10,6 +10,7 @@
rsource "Kconfig.aio"
rsource "Kconfig.barrier"
+rsource "Kconfig.c_lang_r"
rsource "Kconfig.c_lib_ext"
rsource "Kconfig.device_io"
rsource "Kconfig.fd_mgmt"
diff --git a/lib/posix/options/Kconfig.c_lang_r b/lib/posix/options/Kconfig.c_lang_r
new file mode 100644
index 0000000..d8d0f4a
--- /dev/null
+++ b/lib/posix/options/Kconfig.c_lang_r
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+# Copyright (c) 2024 Meta Platforms
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config POSIX_C_LANG_SUPPORT_R
+ bool "Thread-Safe General ISO C Library"
+ select COMMON_LIBC_ASCTIME_R
+ select COMMON_LIBC_CTIME_R
+ select COMMON_LIBC_GMTIME_R
+ select COMMON_LIBC_LOCALTIME_R_UTC
+ help
+ Select 'y' here and Zephyr will provide an implementation of the POSIX_C_LANG_SUPPORT_R
+ Option Group, consisting of asctime_r(), ctime_r(), gmtime_r(), localtime_r(), rand_r(),
+ strerror_r(), and strtok_r()
+
+ For more informnation, please see
+ https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
diff --git a/lib/posix/options/Kconfig.fs b/lib/posix/options/Kconfig.fs
index 663d706..4cfcc5b 100644
--- a/lib/posix/options/Kconfig.fs
+++ b/lib/posix/options/Kconfig.fs
@@ -17,4 +17,13 @@
help
Select 'y' here and Zephyr will provide an alias for fstat() as _fstat().
+config POSIX_FILE_SYSTEM_R
+ bool "Thread-Safe File System"
+ help
+ Select 'y' here and Zephyr will provide an implementation of the POSIX_FILE_SYSTEM_R
+ Option Group, consisting of readdir_r().
+
+ For more informnation, please see
+ https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
+
endif # POSIX_FILE_SYSTEM
diff --git a/lib/posix/options/Kconfig.pthread b/lib/posix/options/Kconfig.pthread
index ec38286..f821d9d 100644
--- a/lib/posix/options/Kconfig.pthread
+++ b/lib/posix/options/Kconfig.pthread
@@ -156,6 +156,8 @@
config POSIX_THREAD_SAFE_FUNCTIONS
bool "POSIX thread-safe functions"
+ select POSIX_FILE_SYSTEM_R if POSIX_FILE_SYSTEM
+ select POSIX_C_LANG_SUPPORT_R
help
Select 'y' here to enable POSIX thread-safe functions including asctime_r(), ctime_r(),
flockfile(), ftrylockfile(), funlockfile(), getc_unlocked(), getchar_unlocked(),
diff --git a/lib/posix/options/fs.c b/lib/posix/options/fs.c
index 825ccc1..9cba57f 100644
--- a/lib/posix/options/fs.c
+++ b/lib/posix/options/fs.c
@@ -314,7 +314,7 @@
return &pdirent;
}
-#ifdef CONFIG_POSIX_THREAD_SAFE_FUNCTIONS
+#ifdef CONFIG_POSIX_FILE_SYSTEM_R
int readdir_r(DIR *dirp, struct dirent *entry, struct dirent **result)
{
struct dirent *dir;
@@ -346,7 +346,7 @@
return 0;
}
-#endif /* CONFIG_POSIX_THREAD_SAFE_FUNCTIONS */
+#endif /* CONFIG_POSIX_FILE_SYSTEM_R */
/**
* @brief Rename a file.
@@ -462,3 +462,13 @@
#ifdef CONFIG_POSIX_FILE_SYSTEM_ALIAS_FSTAT
FUNC_ALIAS(fstat, _fstat, int);
#endif
+
+/**
+ * @brief Remove a directory.
+ *
+ * See IEEE 1003.1
+ */
+int rmdir(const char *path)
+{
+ return unlink(path);
+}
diff --git a/lib/utils/json.c b/lib/utils/json.c
index de43a5d..c1170fc 100644
--- a/lib/utils/json.c
+++ b/lib/utils/json.c
@@ -308,6 +308,7 @@
case JSON_TOK_ARRAY_START:
case JSON_TOK_STRING:
case JSON_TOK_NUMBER:
+ case JSON_TOK_INT64:
case JSON_TOK_FLOAT:
case JSON_TOK_OPAQUE:
case JSON_TOK_OBJ_ARRAY:
@@ -444,6 +445,30 @@
return 0;
}
+static int decode_int64(const struct json_token *token, int64_t *num)
+{
+ char *endptr;
+ char prev_end;
+
+ prev_end = *token->end;
+ *token->end = '\0';
+
+ errno = 0;
+ *num = strtoll(token->start, &endptr, 10);
+
+ *token->end = prev_end;
+
+ if (errno != 0) {
+ return -errno;
+ }
+
+ if (endptr != token->end) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static bool equivalent_types(enum json_tokens type1, enum json_tokens type2)
{
if (type1 == JSON_TOK_TRUE || type1 == JSON_TOK_FALSE) {
@@ -454,6 +479,10 @@
return true;
}
+ if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_INT64) {
+ return true;
+ }
+
if (type1 == JSON_TOK_STRING && type2 == JSON_TOK_OPAQUE) {
return true;
}
@@ -511,6 +540,11 @@
return decode_num(value, num);
}
+ case JSON_TOK_INT64: {
+ int64_t *num = field;
+
+ return decode_int64(value, num);
+ }
case JSON_TOK_OPAQUE:
case JSON_TOK_FLOAT: {
struct json_obj_token *obj_token = field;
@@ -537,6 +571,8 @@
switch (descr->type) {
case JSON_TOK_NUMBER:
return sizeof(int32_t);
+ case JSON_TOK_INT64:
+ return sizeof(int64_t);
case JSON_TOK_OPAQUE:
case JSON_TOK_FLOAT:
case JSON_TOK_OBJ_ARRAY:
@@ -982,6 +1018,23 @@
return append_bytes(buf, (size_t)ret, data);
}
+static int int64_encode(const int64_t *num, json_append_bytes_t append_bytes,
+ void *data)
+{
+ char buf[sizeof("-9223372036854775808")];
+ int ret;
+
+ ret = snprintk(buf, sizeof(buf), "%" PRId64, *num);
+ if (ret < 0) {
+ return ret;
+ }
+ if (ret >= (int)sizeof(buf)) {
+ return -ENOMEM;
+ }
+
+ return append_bytes(buf, (size_t)ret, data);
+}
+
static int float_ascii_encode(struct json_obj_token *num, json_append_bytes_t append_bytes,
void *data)
{
@@ -1044,6 +1097,8 @@
ptr, append_bytes, data);
case JSON_TOK_NUMBER:
return num_encode(ptr, append_bytes, data);
+ case JSON_TOK_INT64:
+ return int64_encode(ptr, append_bytes, data);
case JSON_TOK_FLOAT:
return float_ascii_encode(ptr, append_bytes, data);
case JSON_TOK_OPAQUE:
diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux
index f3be02b..6e70a13 100644
--- a/modules/Kconfig.mcux
+++ b/modules/Kconfig.mcux
@@ -370,6 +370,12 @@
The firmware loader is used to load firmwares to embedded tranceivers.
It is needed to enable connectivity features.
+config NXP_MONOLITHIC_WIFI
+ bool "WiFi firmware monolithic build"
+ help
+ If enabled, the WiFi firmware used by the device will be linked with the
+ application directly.
+
config NXP_MONOLITHIC_BT
bool "BT firmware monolithic build"
help
diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas_fsp
index 54d659b..54d9e82 100644
--- a/modules/Kconfig.renesas_fsp
+++ b/modules/Kconfig.renesas_fsp
@@ -17,3 +17,34 @@
bool
help
Enable RA FSP DTC driver
+
+config USE_RA_FSP_I2C_IIC
+ bool
+ help
+ Enable Renesas RA I2C IIC Master driver
+
+config USE_RA_FSP_SCI_UART
+ bool
+ help
+ Enable RA FSP SCI UART driver
+
+config USE_RA_FSP_ADC
+ bool
+ help
+ Enable RA FSP ADC driver
+
+config USE_RA_FSP_SCE
+ bool
+ help
+ Enable RA FSP SCE driver
+
+if USE_RA_FSP_SCE
+
+config HAS_RENESAS_RA_RSIP_E51A
+ bool
+ default y
+ depends on ENTROPY_RENESAS_RA_RSIP_E51A_TRNG
+ help
+ Includes RSIP-E51A implementation for SCE driver
+
+endif
diff --git a/modules/hal_ambiq/Kconfig b/modules/hal_ambiq/Kconfig
index 10d3f78..326d6ba 100644
--- a/modules/hal_ambiq/Kconfig
+++ b/modules/hal_ambiq/Kconfig
@@ -55,4 +55,9 @@
help
Use the BLEIF driver from Ambiq HAL
+config AMBIQ_HAL_USE_ADC
+ bool
+ help
+ Use the ADC driver from Ambiq HAL
+
endif # AMBIQ_HAL
diff --git a/modules/hal_nordic/Kconfig b/modules/hal_nordic/Kconfig
index 13ab8d9..dd4e0a0 100644
--- a/modules/hal_nordic/Kconfig
+++ b/modules/hal_nordic/Kconfig
@@ -204,6 +204,7 @@
config NRF_802154_CARRIER_FUNCTIONS
bool "nRF 802.15.4 carrier functions"
+ default y if OPENTHREAD_DIAG
help
This option enables functions such as modulated carrier and continuous carrier.
If this option is modified on a multicore SoC, its remote counterpart must be set to the exact same value.
diff --git a/modules/hal_nordic/Kconfig.nrf_regtool b/modules/hal_nordic/Kconfig.nrf_regtool
index 81659bcf..7919714 100644
--- a/modules/hal_nordic/Kconfig.nrf_regtool
+++ b/modules/hal_nordic/Kconfig.nrf_regtool
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
menu "nrf-regtool options"
- depends on SOC_SERIES_NRF54HX
+ depends on SOC_SERIES_NRF54HX || SOC_SERIES_NRF92X
config NRF_REGTOOL_GENERATE_UICR
bool "Generate UICR"
diff --git a/modules/hal_nordic/nrfs/Kconfig b/modules/hal_nordic/nrfs/Kconfig
index b4f6715..b027feb 100644
--- a/modules/hal_nordic/nrfs/Kconfig
+++ b/modules/hal_nordic/nrfs/Kconfig
@@ -36,7 +36,7 @@
config NRFS
bool "nRF Services Support"
- select NRFS_LOCAL_DOMAIN if (SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD)
+ select NRFS_LOCAL_DOMAIN if (SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD || SOC_NRF9280_CPUAPP || SOC_NRF9280_CPURAD)
depends on HAS_NRFS
help
This option enables the nRF Services library.
@@ -95,7 +95,7 @@
config NRFS_DVFS_SERVICE_ENABLED
bool "DVFS service"
depends on NRFS_HAS_DVFS_SERVICE
- default y if SOC_NRF54H20_CPUAPP
+ default y if SOC_NRF54H20_CPUAPP || SOC_NRF9280_CPUAPP
config NRFS_DIAG_SERVICE_ENABLED
bool "System Diagnostics service (only for development purposes)"
diff --git a/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c b/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c
index 047d961..78c67ff 100644
--- a/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c
+++ b/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c
@@ -264,7 +264,7 @@
uint8_t freq_trim = get_dvfs_oppoint_data(oppoint)->new_f_trim_entry;
-#ifdef CONFIG_SOC_NRF54H20_CPUAPP
+#if defined(CONFIG_SOC_NRF54H20_CPUAPP) || defined(CONFIG_SOC_NRF9280_CPUAPP)
hsfll_trim.vsup = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.VSUP;
hsfll_trim.coarse = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.COARSE[freq_trim];
hsfll_trim.fine = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.FINE[freq_trim];
diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt
index d44bac9..942b712 100644
--- a/modules/hal_nordic/nrfx/CMakeLists.txt
+++ b/modules/hal_nordic/nrfx/CMakeLists.txt
@@ -52,6 +52,13 @@
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP NRF9230_ENGB_XXAA
+ NRF_APPLICATION)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD NRF9230_ENGB_XXAA
+ NRF_RADIOCORE)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR NRF9230_ENGB_XXAA
+ NRF_PPR)
+
zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_LOCK
ENABLE_APPROTECT)
zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_USER_HANDLING
@@ -85,11 +92,13 @@
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54HX ${MDK_DIR}/system_nrf54h.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54LX ${MDK_DIR}/system_nrf54l.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF91X ${MDK_DIR}/system_nrf91.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF92X ${MDK_DIR}/system_nrf92.c)
zephyr_library_sources(nrfx_glue.c)
zephyr_library_sources(${HELPERS_DIR}/nrfx_flag32_allocator.c)
-zephyr_library_sources_ifdef(CONFIG_NRFX_DPPI ${HELPERS_DIR}/nrfx_gppi_dppi.c)
-zephyr_library_sources_ifdef(CONFIG_NRFX_PPI ${HELPERS_DIR}/nrfx_gppi_ppi.c)
+zephyr_library_sources_ifdef(CONFIG_RETAINED_MEM_NRF_RAM_CTRL ${HELPERS_DIR}/nrfx_ram_ctrl.c)
+zephyr_library_sources_ifdef(CONFIG_NRFX_DPPI ${HELPERS_DIR}/nrfx_gppi_dppi.c)
+zephyr_library_sources_ifdef(CONFIG_NRFX_PPI ${HELPERS_DIR}/nrfx_gppi_ppi.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_PRS ${SRC_DIR}/prs/nrfx_prs.c)
@@ -202,3 +211,6 @@
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR nrf54l15_enga_flpr.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd)
mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP nrf9230_engb_application.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR nrf9230_engb_ppr.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD nrf9230_engb_radiocore.svd)
diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h
index 22d5988..4b3979f 100644
--- a/modules/hal_nordic/nrfx/nrfx_config.h
+++ b/modules/hal_nordic/nrfx/nrfx_config.h
@@ -1049,6 +1049,12 @@
#include <nrfx_config_nrf54l15_enga_flpr.h>
#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
#include <nrfx_config_nrf91.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_APPLICATION)
+ #include <nrfx_config_nrf9230_engb_application.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_RADIOCORE)
+ #include <nrfx_config_nrf9230_engb_radiocore.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_PPR)
+ #include <nrfx_config_nrf9230_engb_ppr.h>
#else
#error "Unknown device."
#endif
diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h
new file mode 100644
index 0000000..a7905c1
--- /dev/null
+++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h
@@ -0,0 +1,1973 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__
+#define NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD_ENABLED
+#define NRFX_BELLBOARD_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD0_ENABLED
+#define NRFX_BELLBOARD0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD1_ENABLED
+#define NRFX_BELLBOARD1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD2_ENABLED
+#define NRFX_BELLBOARD2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD3_ENABLED
+#define NRFX_BELLBOARD3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_ENABLED
+#define NRFX_DPPI_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
+#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
+#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0
+#endif
+
+/**
+ * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e
+#endif
+
+/**
+ * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020
+#endif
+
+/**
+ * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040
+#endif
+
+/**
+ * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081
+#endif
+
+/**
+ * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f
+#endif
+
+/**
+ * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1
+#endif
+
+/**
+ * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df
+#endif
+
+/**
+ * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf
+#endif
+
+/**
+ * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e
+#endif
+
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_EGU130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU130_ENABLED
+#define NRFX_EGU130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0. Maximum: 15.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_GPIOTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE130_ENABLED
+#define NRFX_GPIOTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE131_ENABLED
+#define NRFX_GPIOTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_ENABLED
+#define NRFX_GRTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOEN
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOEN
+#define NRFX_GRTC_CONFIG_AUTOEN 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOSTART
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOSTART
+#define NRFX_GRTC_CONFIG_AUTOSTART 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+ *
+ * Integer value.
+ */
+#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+ */
+#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0
+#endif
+
+/**
+ * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED
+#define NRFX_GRTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL
+#define NRFX_GRTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S130_ENABLED
+#define NRFX_I2S130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S131_ENABLED
+#define NRFX_I2S131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_MVDMA_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA_ENABLED
+#define NRFX_MVDMA_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA120_ENABLED
+#define NRFX_MVDMA120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA121_ENABLED
+#define NRFX_MVDMA121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_4_ENABLED
+#define NRFX_PRS_BOX_4_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_5_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_5_ENABLED
+#define NRFX_PRS_BOX_5_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_6_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_6_ENABLED
+#define NRFX_PRS_BOX_6_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_7_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_7_ENABLED
+#define NRFX_PRS_BOX_7_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_8_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_8_ENABLED
+#define NRFX_PRS_BOX_8_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_9_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_9_ENABLED
+#define NRFX_PRS_BOX_9_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PWM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM120_ENABLED
+#define NRFX_PWM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM130_ENABLED
+#define NRFX_PWM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM131_ENABLED
+#define NRFX_PWM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM132_ENABLED
+#define NRFX_PWM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM133_ENABLED
+#define NRFX_PWM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_QDEC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC130_ENABLED
+#define NRFX_QDEC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC131_ENABLED
+#define NRFX_QDEC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC130_ENABLED
+#define NRFX_RTC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC131_ENABLED
+#define NRFX_RTC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM120_ENABLED
+#define NRFX_SPIM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM121_ENABLED
+#define NRFX_SPIM121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM130_ENABLED
+#define NRFX_SPIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM131_ENABLED
+#define NRFX_SPIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM132_ENABLED
+#define NRFX_SPIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM133_ENABLED
+#define NRFX_SPIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM134_ENABLED
+#define NRFX_SPIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM135_ENABLED
+#define NRFX_SPIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM136_ENABLED
+#define NRFX_SPIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM137_ENABLED
+#define NRFX_SPIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIS120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS120_ENABLED
+#define NRFX_SPIS120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS130_ENABLED
+#define NRFX_SPIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS131_ENABLED
+#define NRFX_SPIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS132_ENABLED
+#define NRFX_SPIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS133_ENABLED
+#define NRFX_SPIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS134_ENABLED
+#define NRFX_SPIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS135_ENABLED
+#define NRFX_SPIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS136_ENABLED
+#define NRFX_SPIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS137_ENABLED
+#define NRFX_SPIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER120_ENABLED
+#define NRFX_TIMER120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER121_ENABLED
+#define NRFX_TIMER121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER130_ENABLED
+#define NRFX_TIMER130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER131_ENABLED
+#define NRFX_TIMER131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER132_ENABLED
+#define NRFX_TIMER132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER133_ENABLED
+#define NRFX_TIMER133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER134_ENABLED
+#define NRFX_TIMER134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER135_ENABLED
+#define NRFX_TIMER135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER136_ENABLED
+#define NRFX_TIMER136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER137_ENABLED
+#define NRFX_TIMER137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM130_ENABLED
+#define NRFX_TWIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM131_ENABLED
+#define NRFX_TWIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM132_ENABLED
+#define NRFX_TWIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM133_ENABLED
+#define NRFX_TWIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM134_ENABLED
+#define NRFX_TWIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM135_ENABLED
+#define NRFX_TWIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM136_ENABLED
+#define NRFX_TWIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM137_ENABLED
+#define NRFX_TWIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+ *
+ * Assume that any instance would be initialized only once.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS130_ENABLED
+#define NRFX_TWIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS131_ENABLED
+#define NRFX_TWIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS132_ENABLED
+#define NRFX_TWIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS133_ENABLED
+#define NRFX_TWIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS134_ENABLED
+#define NRFX_TWIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS135_ENABLED
+#define NRFX_TWIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS136_ENABLED
+#define NRFX_TWIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS137_ENABLED
+#define NRFX_TWIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+ *
+ * If enabled, support for configuring GPIO pins is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+ *
+ * If enabled, support for configuring PSEL registers is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_TX_LINK
+#define NRFX_UARTE_CONFIG_TX_LINK 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+ *
+ * Integer value. Minimum: 0. Maximum: 255.
+ */
+#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171
+#endif
+
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_UARTE120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE120_ENABLED
+#define NRFX_UARTE120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE130_ENABLED
+#define NRFX_UARTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE131_ENABLED
+#define NRFX_UARTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE132_ENABLED
+#define NRFX_UARTE132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE133_ENABLED
+#define NRFX_UARTE133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE134_ENABLED
+#define NRFX_UARTE134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE135_ENABLED
+#define NRFX_UARTE135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE136_ENABLED
+#define NRFX_UARTE136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE137_ENABLED
+#define NRFX_UARTE137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_WDT010_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT010_ENABLED
+#define NRFX_WDT010_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT011_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT011_ENABLED
+#define NRFX_WDT011_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT131_ENABLED
+#define NRFX_WDT131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT132_ENABLED
+#define NRFX_WDT132_ENABLED 0
+#endif
+
+#endif /* NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__ */
diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h
new file mode 100644
index 0000000..ae1f931
--- /dev/null
+++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h
@@ -0,0 +1,1910 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef NRFX_CONFIG_NRF9230_ENGB_PPR_H__
+#define NRFX_CONFIG_NRF9230_ENGB_PPR_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 0
+#endif
+
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_COREDEP_VPR_LEGACY
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COREDEP_VPR_LEGACY
+#define NRFX_COREDEP_VPR_LEGACY 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_ENABLED
+#define NRFX_DPPI_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
+#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
+#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030
+#endif
+
+/**
+ * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e
+#endif
+
+/**
+ * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020
+#endif
+
+/**
+ * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040
+#endif
+
+/**
+ * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081
+#endif
+
+/**
+ * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1
+#endif
+
+/**
+ * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df
+#endif
+
+/**
+ * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf
+#endif
+
+/**
+ * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e
+#endif
+
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_EGU130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU130_ENABLED
+#define NRFX_EGU130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0. Maximum: 15.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_GPIOTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE130_ENABLED
+#define NRFX_GPIOTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE131_ENABLED
+#define NRFX_GPIOTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_ENABLED
+#define NRFX_GRTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOEN
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOEN
+#define NRFX_GRTC_CONFIG_AUTOEN 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOSTART
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOSTART
+#define NRFX_GRTC_CONFIG_AUTOSTART 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+ *
+ * Integer value.
+ */
+#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+ */
+#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0
+#endif
+
+/**
+ * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED
+#define NRFX_GRTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL
+#define NRFX_GRTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S130_ENABLED
+#define NRFX_I2S130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S131_ENABLED
+#define NRFX_I2S131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_MVDMA_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA_ENABLED
+#define NRFX_MVDMA_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA120_ENABLED
+#define NRFX_MVDMA120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA121_ENABLED
+#define NRFX_MVDMA121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_4_ENABLED
+#define NRFX_PRS_BOX_4_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_5_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_5_ENABLED
+#define NRFX_PRS_BOX_5_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_6_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_6_ENABLED
+#define NRFX_PRS_BOX_6_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_7_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_7_ENABLED
+#define NRFX_PRS_BOX_7_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_8_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_8_ENABLED
+#define NRFX_PRS_BOX_8_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_9_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_9_ENABLED
+#define NRFX_PRS_BOX_9_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PWM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM120_ENABLED
+#define NRFX_PWM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM130_ENABLED
+#define NRFX_PWM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM131_ENABLED
+#define NRFX_PWM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM132_ENABLED
+#define NRFX_PWM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM133_ENABLED
+#define NRFX_PWM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_QDEC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC130_ENABLED
+#define NRFX_QDEC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC131_ENABLED
+#define NRFX_QDEC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC130_ENABLED
+#define NRFX_RTC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC131_ENABLED
+#define NRFX_RTC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM120_ENABLED
+#define NRFX_SPIM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM121_ENABLED
+#define NRFX_SPIM121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM130_ENABLED
+#define NRFX_SPIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM131_ENABLED
+#define NRFX_SPIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM132_ENABLED
+#define NRFX_SPIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM133_ENABLED
+#define NRFX_SPIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM134_ENABLED
+#define NRFX_SPIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM135_ENABLED
+#define NRFX_SPIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM136_ENABLED
+#define NRFX_SPIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM137_ENABLED
+#define NRFX_SPIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIS120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS120_ENABLED
+#define NRFX_SPIS120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS130_ENABLED
+#define NRFX_SPIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS131_ENABLED
+#define NRFX_SPIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS132_ENABLED
+#define NRFX_SPIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS133_ENABLED
+#define NRFX_SPIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS134_ENABLED
+#define NRFX_SPIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS135_ENABLED
+#define NRFX_SPIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS136_ENABLED
+#define NRFX_SPIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS137_ENABLED
+#define NRFX_SPIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER120_ENABLED
+#define NRFX_TIMER120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER121_ENABLED
+#define NRFX_TIMER121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER130_ENABLED
+#define NRFX_TIMER130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER131_ENABLED
+#define NRFX_TIMER131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER132_ENABLED
+#define NRFX_TIMER132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER133_ENABLED
+#define NRFX_TIMER133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER134_ENABLED
+#define NRFX_TIMER134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER135_ENABLED
+#define NRFX_TIMER135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER136_ENABLED
+#define NRFX_TIMER136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER137_ENABLED
+#define NRFX_TIMER137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM130_ENABLED
+#define NRFX_TWIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM131_ENABLED
+#define NRFX_TWIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM132_ENABLED
+#define NRFX_TWIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM133_ENABLED
+#define NRFX_TWIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM134_ENABLED
+#define NRFX_TWIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM135_ENABLED
+#define NRFX_TWIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM136_ENABLED
+#define NRFX_TWIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM137_ENABLED
+#define NRFX_TWIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+ *
+ * Assume that any instance would be initialized only once.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS130_ENABLED
+#define NRFX_TWIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS131_ENABLED
+#define NRFX_TWIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS132_ENABLED
+#define NRFX_TWIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS133_ENABLED
+#define NRFX_TWIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS134_ENABLED
+#define NRFX_TWIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS135_ENABLED
+#define NRFX_TWIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS136_ENABLED
+#define NRFX_TWIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS137_ENABLED
+#define NRFX_TWIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+ *
+ * If enabled, support for configuring GPIO pins is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+ *
+ * If enabled, support for configuring PSEL registers is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_TX_LINK
+#define NRFX_UARTE_CONFIG_TX_LINK 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+ *
+ * Integer value. Minimum: 0. Maximum: 255.
+ */
+#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171
+#endif
+
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_UARTE120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE120_ENABLED
+#define NRFX_UARTE120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE130_ENABLED
+#define NRFX_UARTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE131_ENABLED
+#define NRFX_UARTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE132_ENABLED
+#define NRFX_UARTE132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE133_ENABLED
+#define NRFX_UARTE133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE134_ENABLED
+#define NRFX_UARTE134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE135_ENABLED
+#define NRFX_UARTE135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE136_ENABLED
+#define NRFX_UARTE136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE137_ENABLED
+#define NRFX_UARTE137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_VEVIF_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_VEVIF_ENABLED
+#define NRFX_VEVIF_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 3.
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_WDT131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT131_ENABLED
+#define NRFX_WDT131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT132_ENABLED
+#define NRFX_WDT132_ENABLED 0
+#endif
+
+#endif /* NRFX_CONFIG_NRF9230_ENGB_PPR_H__ */
diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h
new file mode 100644
index 0000000..84a0a75
--- /dev/null
+++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h
@@ -0,0 +1,2040 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__
+#define NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD_ENABLED
+#define NRFX_BELLBOARD_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD0_ENABLED
+#define NRFX_BELLBOARD0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD1_ENABLED
+#define NRFX_BELLBOARD1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD2_ENABLED
+#define NRFX_BELLBOARD2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_BELLBOARD3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_BELLBOARD3_ENABLED
+#define NRFX_BELLBOARD3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_ENABLED
+#define NRFX_DPPI_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
+#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
+#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0
+#endif
+
+/**
+ * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e
+#endif
+
+/**
+ * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020
+#endif
+
+/**
+ * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040
+#endif
+
+/**
+ * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081
+#endif
+
+/**
+ * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f
+#endif
+
+/**
+ * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff
+#endif
+
+/**
+ * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1
+#endif
+
+/**
+ * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df
+#endif
+
+/**
+ * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf
+#endif
+
+/**
+ * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e
+#endif
+
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_EGU020_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU020_ENABLED
+#define NRFX_EGU020_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_EGU130_ENABLED
+#define NRFX_EGU130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0. Maximum: 15.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_GPIOTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE130_ENABLED
+#define NRFX_GPIOTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GPIOTE131_ENABLED
+#define NRFX_GPIOTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_ENABLED
+#define NRFX_GRTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED
+#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOEN
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOEN
+#define NRFX_GRTC_CONFIG_AUTOEN 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_AUTOSTART
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_AUTOSTART
+#define NRFX_GRTC_CONFIG_AUTOSTART 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+ *
+ * Integer value.
+ */
+#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS
+#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+ */
+#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
+#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00
+#endif
+
+/**
+ * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED
+#define NRFX_GRTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GRTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL
+#define NRFX_GRTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S130_ENABLED
+#define NRFX_I2S130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_I2S131_ENABLED
+#define NRFX_I2S131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030
+#endif
+
+/**
+ * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c
+#endif
+
+/**
+ * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0
+#endif
+
+/**
+ * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0
+#endif
+
+/**
+ * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+ */
+#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK
+#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_MVDMA_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA_ENABLED
+#define NRFX_MVDMA_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA120_ENABLED
+#define NRFX_MVDMA120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_MVDMA121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_MVDMA121_ENABLED
+#define NRFX_MVDMA121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_4_ENABLED
+#define NRFX_PRS_BOX_4_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_5_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_5_ENABLED
+#define NRFX_PRS_BOX_5_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_6_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_6_ENABLED
+#define NRFX_PRS_BOX_6_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_7_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_7_ENABLED
+#define NRFX_PRS_BOX_7_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_8_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_8_ENABLED
+#define NRFX_PRS_BOX_8_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_9_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_9_ENABLED
+#define NRFX_PRS_BOX_9_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PWM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM120_ENABLED
+#define NRFX_PWM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM130_ENABLED
+#define NRFX_PWM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM131_ENABLED
+#define NRFX_PWM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM132_ENABLED
+#define NRFX_PWM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_PWM133_ENABLED
+#define NRFX_PWM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_QDEC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC130_ENABLED
+#define NRFX_QDEC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_QDEC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_QDEC131_ENABLED
+#define NRFX_QDEC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC130_ENABLED
+#define NRFX_RTC130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_RTC131_ENABLED
+#define NRFX_RTC131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM120_ENABLED
+#define NRFX_SPIM120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM121_ENABLED
+#define NRFX_SPIM121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM130_ENABLED
+#define NRFX_SPIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM131_ENABLED
+#define NRFX_SPIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM132_ENABLED
+#define NRFX_SPIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM133_ENABLED
+#define NRFX_SPIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM134_ENABLED
+#define NRFX_SPIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM135_ENABLED
+#define NRFX_SPIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM136_ENABLED
+#define NRFX_SPIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIM137_ENABLED
+#define NRFX_SPIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIS120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS120_ENABLED
+#define NRFX_SPIS120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS130_ENABLED
+#define NRFX_SPIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS131_ENABLED
+#define NRFX_SPIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS132_ENABLED
+#define NRFX_SPIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS133_ENABLED
+#define NRFX_SPIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS134_ENABLED
+#define NRFX_SPIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS135_ENABLED
+#define NRFX_SPIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS136_ENABLED
+#define NRFX_SPIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SPIS137_ENABLED
+#define NRFX_SPIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER020_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER020_ENABLED
+#define NRFX_TIMER020_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER021_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER021_ENABLED
+#define NRFX_TIMER021_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER022_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER022_ENABLED
+#define NRFX_TIMER022_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER120_ENABLED
+#define NRFX_TIMER120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER121_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER121_ENABLED
+#define NRFX_TIMER121_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER130_ENABLED
+#define NRFX_TIMER130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER131_ENABLED
+#define NRFX_TIMER131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER132_ENABLED
+#define NRFX_TIMER132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER133_ENABLED
+#define NRFX_TIMER133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER134_ENABLED
+#define NRFX_TIMER134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER135_ENABLED
+#define NRFX_TIMER135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER136_ENABLED
+#define NRFX_TIMER136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TIMER137_ENABLED
+#define NRFX_TIMER137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIM130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM130_ENABLED
+#define NRFX_TWIM130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM131_ENABLED
+#define NRFX_TWIM131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM132_ENABLED
+#define NRFX_TWIM132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM133_ENABLED
+#define NRFX_TWIM133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM134_ENABLED
+#define NRFX_TWIM134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM135_ENABLED
+#define NRFX_TWIM135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM136_ENABLED
+#define NRFX_TWIM136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIM137_ENABLED
+#define NRFX_TWIM137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+ *
+ * Assume that any instance would be initialized only once.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIS130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS130_ENABLED
+#define NRFX_TWIS130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS131_ENABLED
+#define NRFX_TWIS131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS132_ENABLED
+#define NRFX_TWIS132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS133_ENABLED
+#define NRFX_TWIS133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS134_ENABLED
+#define NRFX_TWIS134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS135_ENABLED
+#define NRFX_TWIS135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS136_ENABLED
+#define NRFX_TWIS136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_TWIS137_ENABLED
+#define NRFX_TWIS137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+ *
+ * If enabled, support for configuring GPIO pins is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+ *
+ * If enabled, support for configuring PSEL registers is removed from the driver.
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG
+#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers.
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_TX_LINK
+#define NRFX_UARTE_CONFIG_TX_LINK 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
+#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1
+#endif
+
+/**
+ * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+ *
+ * Integer value. Minimum: 0. Maximum: 255.
+ */
+#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
+#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171
+#endif
+
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_UARTE120_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE120_ENABLED
+#define NRFX_UARTE120_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE130_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE130_ENABLED
+#define NRFX_UARTE130_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE131_ENABLED
+#define NRFX_UARTE131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE132_ENABLED
+#define NRFX_UARTE132_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE133_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE133_ENABLED
+#define NRFX_UARTE133_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE134_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE134_ENABLED
+#define NRFX_UARTE134_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE135_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE135_ENABLED
+#define NRFX_UARTE135_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE136_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE136_ENABLED
+#define NRFX_UARTE136_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE137_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_UARTE137_ENABLED
+#define NRFX_UARTE137_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0. Maximum: 7.
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_WDT010_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT010_ENABLED
+#define NRFX_WDT010_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT011_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT011_ENABLED
+#define NRFX_WDT011_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT131_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT131_ENABLED
+#define NRFX_WDT131_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT132_ENABLED
+ *
+ * Boolean. Accepted values: 0 and 1.
+ */
+#ifndef NRFX_WDT132_ENABLED
+#define NRFX_WDT132_ENABLED 0
+#endif
+
+#endif /* NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__ */
diff --git a/modules/hal_nxp/usb/usb_device_config.h b/modules/hal_nxp/usb/usb_device_config.h
index a97d918..0fc3070 100644
--- a/modules/hal_nxp/usb/usb_device_config.h
+++ b/modules/hal_nxp/usb/usb_device_config.h
@@ -101,7 +101,18 @@
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
/*! @brief How many the DTD are supported. */
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
+
+#ifndef CONFIG_UDC_BUF_FORCE_NOCACHE
+#ifdef CONFIG_NOCACHE_MEMORY
+#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U)
#endif
+#endif
+#endif
+
+/* TODO: After Kconfig item that enable/disable sof is added,
+ * use the Kconfig item to control this macro.
+ */
+#define USB_DEVICE_CONFIG_SOF_NOTIFICATIONS (1U)
#endif
diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt
index 026fcfb..f5e83a9 100644
--- a/modules/hostap/CMakeLists.txt
+++ b/modules/hostap/CMakeLists.txt
@@ -484,4 +484,10 @@
zephyr_library_link_libraries_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE
mbedTLS)
+if(CONFIG_SAE_PWE_EARLY_EXIT)
+ message(WARNING "CONFIG_SAE_PWE_EARLY_EXIT is enabled, "
+ "this is not secure and is a workaround for low resource systems, "
+ "please use it carefully and do not use it production.")
+endif()
+
endif()
diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig
index f74ec35..75d1189 100644
--- a/modules/hostap/Kconfig
+++ b/modules/hostap/Kconfig
@@ -24,6 +24,7 @@
if WIFI_NM_WPA_SUPPLICANT
config COMMON_LIBC_MALLOC_ARENA_SIZE
+ default 85000 if WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE && !MBEDTLS_ENABLE_HEAP
default 40000 if WIFI_NM_WPA_SUPPLICANT_AP
# 8192 for MbedTLS heap
default 21808 if MBEDTLS_ENABLE_HEAP
@@ -136,6 +137,11 @@
select MBEDTLS
select MBEDTLS_CIPHER_MODE_CTR_ENABLED
select MBEDTLS_CIPHER_MODE_CBC_ENABLED
+ select MBEDTLS_CIPHER_AES_ENABLED
+ select MBEDTLS_CIPHER_DES_ENABLED
+ select MBEDTLS_SHA1
+ select MBEDTLS_ENTROPY_ENABLED
+ select MBEDTLS_CIPHER
select MBEDTLS_ECP_C
select MBEDTLS_ECP_ALL_ENABLED
select MBEDTLS_CMAC
@@ -164,6 +170,7 @@
config WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
bool "Enterprise Crypto support for WiFi"
+ select MBEDTLS_PEM_CERTIFICATE_FORMAT
depends on !WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE
config WIFI_NM_WPA_SUPPLICANT_WPA3
@@ -185,6 +192,7 @@
config WIFI_NM_WPA_SUPPLICANT_EAPOL
bool "EAPoL supplicant"
+ default y if WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
config WIFI_NM_WPA_SUPPLICANT_CLI
bool "CLI support for wpa_supplicant"
@@ -222,6 +230,16 @@
select MBEDTLS_X509_CSR_WRITE_C
select MBEDTLS_X509_CSR_PARSE_C
+config WPA_CLI
+ bool "WPA CLI support"
+ help
+ Enable WPA CLI support for wpa_supplicant.
+
+if WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+ config MBEDTLS_SSL_MAX_CONTENT_LEN
+ default 16384
+endif
+
# Create hidden config options that are used in hostap. This way we do not need
# to mark them as allowed for CI checks, and also someone else cannot use the
# same name options.
@@ -393,9 +411,6 @@
bool
default y if WIFI_NM_WPA_SUPPLICANT_WEP
-config WPA_CLI
- bool
-
config WPA_CRYPTO
bool
@@ -447,4 +462,12 @@
endchoice
+config SAE_PWE_EARLY_EXIT
+ bool "Exit early if PWE if found"
+ help
+ In order to mitigate side channel attacks, even if the PWE is found the WPA
+ supplicant goes through full iterations, but in some low-resource systems
+ this can be intensive, so, add an option to exit early.
+ Note that this is highly insecure and shouldn't be used in production
+
endif # WIFI_NM_WPA_SUPPLICANT
diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c
index 56c957d..393a33e 100644
--- a/modules/hostap/src/supp_api.c
+++ b/modules/hostap/src/supp_api.c
@@ -25,6 +25,9 @@
extern struct k_sem wpa_supplicant_ready_sem;
extern struct wpa_global *global;
+/* save the last wifi connection parameters */
+static struct wifi_connect_req_params last_wifi_conn_params;
+
enum requested_ops {
CONNECT = 0,
DISCONNECT
@@ -43,6 +46,10 @@
#define DISCONNECT_TIMEOUT_MS 5000
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+static struct wifi_enterprise_creds_params enterprise_creds;
+#endif
+
K_MUTEX_DEFINE(wpa_supplicant_mutex);
extern struct k_work_q *get_workq(void);
@@ -321,6 +328,61 @@
}
}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+int supplicant_add_enterprise_creds(const struct device *dev,
+ struct wifi_enterprise_creds_params *creds)
+{
+ int ret = 0;
+
+ if (!creds) {
+ ret = -1;
+ wpa_printf(MSG_ERROR, "enterprise creds is NULL");
+ goto out;
+ }
+
+ memcpy((void *)&enterprise_creds, (void *)creds,
+ sizeof(struct wifi_enterprise_creds_params));
+
+out:
+ return ret;
+}
+
+static int wpas_config_process_blob(struct wpa_config *config, char *name, uint8_t *data,
+ uint32_t data_len)
+{
+ struct wpa_config_blob *blob;
+
+ if (!data || !data_len) {
+ return -1;
+ }
+
+ blob = os_zalloc(sizeof(*blob));
+ if (blob == NULL) {
+ return -1;
+ }
+
+ blob->data = os_zalloc(data_len);
+ if (blob->data == NULL) {
+ os_free(blob);
+ return -1;
+ }
+
+ blob->name = os_strdup(name);
+
+ if (blob->name == NULL) {
+ wpa_config_free_blob(blob);
+ return -1;
+ }
+
+ os_memcpy(blob->data, data, data_len);
+ blob->len = data_len;
+
+ wpa_config_set_blob(config, blob);
+
+ return 0;
+}
+#endif
+
static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s,
struct wifi_connect_req_params *params,
bool mode_ap)
@@ -399,7 +461,9 @@
}
}
- if (params->security == WIFI_SECURITY_TYPE_SAE) {
+ if (params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
+ params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
+ params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
if (params->sae_password) {
if (!wpa_cli_cmd_v("set_network %d sae_password \"%s\"",
resp.network_id, params->sae_password)) {
@@ -412,6 +476,16 @@
}
}
+ if (params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
+ params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
+ if (!wpa_cli_cmd_v("set sae_pwe %d",
+ (params->security == WIFI_SECURITY_TYPE_SAE_H2E)
+ ? 1
+ : 2)) {
+ goto out;
+ }
+ }
+
if (!wpa_cli_cmd_v("set_network %d key_mgmt SAE", resp.network_id)) {
goto out;
}
@@ -443,6 +517,66 @@
goto out;
}
}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+ } else if (params->security == WIFI_SECURITY_TYPE_EAP_TLS) {
+ if (!wpa_cli_cmd_v("set_network %d key_mgmt WPA-EAP",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d proto RSN",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d eap TLS",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d anonymous_identity \"%s\"",
+ resp.network_id, params->anon_id)) {
+ goto out;
+ }
+
+ if (wpas_config_process_blob(wpa_s->conf, "ca_cert",
+ enterprise_creds.ca_cert,
+ enterprise_creds.ca_cert_len)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d ca_cert \"blob://ca_cert\"",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (wpas_config_process_blob(wpa_s->conf, "client_cert",
+ enterprise_creds.client_cert,
+ enterprise_creds.client_cert_len)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d client_cert \"blob://client_cert\"",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (wpas_config_process_blob(wpa_s->conf, "private_key",
+ enterprise_creds.client_key,
+ enterprise_creds.client_key_len)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d private_key \"blob://private_key\"",
+ resp.network_id)) {
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("set_network %d private_key_passwd \"%s\"",
+ resp.network_id, params->key_passwd)) {
+ goto out;
+ }
+#endif
} else {
ret = -1;
wpa_printf(MSG_ERROR, "Unsupported security type: %d",
@@ -520,6 +654,8 @@
goto out;
}
+ memset(&last_wifi_conn_params, 0, sizeof(struct wifi_connect_req_params));
+ memcpy((void *)&last_wifi_conn_params, params, sizeof(struct wifi_connect_req_params));
return 0;
rem_net:
@@ -832,6 +968,31 @@
}
#endif /* CONFIG_NET_STATISTICS_WIFI */
+int supplicant_pmksa_flush(const struct device *dev)
+{
+ struct wpa_supplicant *wpa_s;
+ int ret = 0;
+
+ k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
+
+ wpa_s = get_wpa_s_handle(dev);
+ if (!wpa_s) {
+ ret = -1;
+ wpa_printf(MSG_ERROR, "Device %s not found", dev->name);
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("pmksa_flush")) {
+ ret = -1;
+ wpa_printf(MSG_ERROR, "pmksa_flush failed");
+ goto out;
+ }
+
+out:
+ k_mutex_unlock(&wpa_supplicant_mutex);
+ return ret;
+}
+
int supplicant_set_power_save(const struct device *dev, struct wifi_ps_params *params)
{
const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev);
@@ -918,6 +1079,55 @@
return wifi_mgmt_api->channel(dev, channel);
}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+int supplicant_btm_query(const struct device *dev, uint8_t reason)
+{
+ struct wpa_supplicant *wpa_s;
+ int ret = -1;
+
+ k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
+
+ wpa_s = get_wpa_s_handle(dev);
+ if (!wpa_s) {
+ ret = -1;
+ wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+ goto out;
+ }
+
+ if (!wpa_cli_cmd_v("wnm_bss_query %d", reason)) {
+ goto out;
+ }
+
+ ret = 0;
+
+out:
+ k_mutex_unlock(&wpa_supplicant_mutex);
+
+ return ret;
+}
+#endif
+
+int supplicant_get_wifi_conn_params(const struct device *dev,
+ struct wifi_connect_req_params *params)
+{
+ struct wpa_supplicant *wpa_s;
+ int ret = 0;
+
+ k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
+
+ wpa_s = get_wpa_s_handle(dev);
+ if (!wpa_s) {
+ ret = -1;
+ wpa_printf(MSG_ERROR, "Device %s not found", dev->name);
+ goto out;
+ }
+
+ memcpy(params, &last_wifi_conn_params, sizeof(struct wifi_connect_req_params));
+out:
+ k_mutex_unlock(&wpa_supplicant_mutex);
+ return ret;
+}
+
#ifdef CONFIG_AP
int supplicant_ap_enable(const struct device *dev,
struct wifi_connect_req_params *params)
diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h
index 98a413b..f954e89 100644
--- a/modules/hostap/src/supp_api.h
+++ b/modules/hostap/src/supp_api.h
@@ -84,6 +84,14 @@
int supplicant_get_stats(const struct device *dev, struct net_stats_wifi *stats);
#endif /* CONFIG_NET_STATISTICS_WIFI || __DOXYGEN__ */
+/** Flush PMKSA cache entries
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int supplicant_pmksa_flush(const struct device *dev);
+
/**
* @brief Set Wi-Fi power save configuration
*
@@ -130,6 +138,18 @@
*/
int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode);
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+/** Set Wi-Fi enterprise mode CA/client Cert and key
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param file Pointer to the CA/client Cert and key.
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int supplicant_add_enterprise_creds(const struct device *dev,
+ struct wifi_enterprise_creds_params *creds);
+#endif
+
/**
* @brief Set Wi-Fi packet filter for sniffing operation
*
@@ -148,6 +168,27 @@
*/
int supplicant_channel(const struct device *dev, struct wifi_channel_info *channel);
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+/** Send bss transition query
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reason query reason
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int supplicant_btm_query(const struct device *dev, uint8_t reason);
+#endif
+
+/** Get Wi-Fi connection parameters recently used
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param params the Wi-Fi connection parameters recently used
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int supplicant_get_wifi_conn_params(const struct device *dev,
+ struct wifi_connect_req_params *params);
+
#ifdef CONFIG_AP
/**
* @brief Set Wi-Fi AP configuration
diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c
index 70d1c07..c2fdef5 100644
--- a/modules/hostap/src/supp_main.c
+++ b/modules/hostap/src/supp_main.c
@@ -61,12 +61,20 @@
.mode = supplicant_mode,
.filter = supplicant_filter,
.channel = supplicant_channel,
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+ .btm_query = supplicant_btm_query,
+#endif
+ .get_conn_params = supplicant_get_wifi_conn_params,
#ifdef CONFIG_AP
.ap_enable = supplicant_ap_enable,
.ap_disable = supplicant_ap_disable,
.ap_sta_disconnect = supplicant_ap_sta_disconnect,
#endif /* CONFIG_AP */
.dpp_dispatch = supplicant_dpp_dispatch,
+ .pmksa_flush = supplicant_pmksa_flush,
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+ .enterprise_creds = supplicant_add_enterprise_creds,
+#endif
};
DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops);
diff --git a/modules/openthread/Kconfig.features b/modules/openthread/Kconfig.features
index 32f451c..eb71323 100644
--- a/modules/openthread/Kconfig.features
+++ b/modules/openthread/Kconfig.features
@@ -17,6 +17,8 @@
bool "Version 1.3"
config OPENTHREAD_THREAD_VERSION_1_3_1
bool "Version 1.3.1"
+config OPENTHREAD_THREAD_VERSION_1_4
+ bool "Version 1.4"
endchoice # OPENTHREAD_STACK_VERSION
config OPENTHREAD_THREAD_VERSION
@@ -25,6 +27,7 @@
default "1.2" if OPENTHREAD_THREAD_VERSION_1_2
default "1.3" if OPENTHREAD_THREAD_VERSION_1_3
default "1.3.1" if OPENTHREAD_THREAD_VERSION_1_3_1
+ default "1.4" if OPENTHREAD_THREAD_VERSION_1_4
default "unknown"
config OPENTHREAD_ANYCAST_LOCATOR
diff --git a/samples/bluetooth/hap_ha/prj.conf b/samples/bluetooth/hap_ha/prj.conf
index c492cde..83d6f70 100644
--- a/samples/bluetooth/hap_ha/prj.conf
+++ b/samples/bluetooth/hap_ha/prj.conf
@@ -56,4 +56,9 @@
CONFIG_BT_TBS_CLIENT_CCID=y
CONFIG_BT_TBS_CLIENT_STATUS_FLAGS=y
+CONFIG_BT_BAS_BLS=y
+CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT=y
+CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT=y
+CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT=y
+
CONFIG_LOG=y
diff --git a/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c b/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
index 73e49a0..4e2c477 100644
--- a/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
+++ b/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
@@ -18,7 +18,7 @@
static struct bt_vcp_included vcp_included;
-static void vcs_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcs_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
if (err) {
printk("VCS state get failed (%d)\n", err);
@@ -27,7 +27,7 @@
}
}
-static void vcs_flags_cb(int err, uint8_t flags)
+static void vcs_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
if (err) {
printk("VCS flags get failed (%d)\n", err);
diff --git a/samples/bluetooth/hci_ipc/src/main.c b/samples/bluetooth/hci_ipc/src/main.c
index 6e1f275..38b8a1a 100644
--- a/samples/bluetooth/hci_ipc/src/main.c
+++ b/samples/bluetooth/hci_ipc/src/main.c
@@ -192,7 +192,7 @@
}
if (buf) {
- net_buf_put(&tx_queue, buf);
+ k_fifo_put(&tx_queue, buf);
LOG_HEXDUMP_DBG(buf->data, buf->len, "Final net buffer:");
}
@@ -205,7 +205,7 @@
int err;
/* Wait until a buffer is available */
- buf = net_buf_get(&tx_queue, K_FOREVER);
+ buf = k_fifo_get(&tx_queue, K_FOREVER);
/* Pass buffer to the stack */
err = bt_send(buf);
if (err) {
@@ -412,7 +412,7 @@
while (1) {
struct net_buf *buf;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
hci_ipc_send(buf, HCI_REGULAR_MSG);
}
return 0;
diff --git a/samples/bluetooth/hci_spi/src/main.c b/samples/bluetooth/hci_spi/src/main.c
index a4b3f4e..f7d477e 100644
--- a/samples/bluetooth/hci_spi/src/main.c
+++ b/samples/bluetooth/hci_spi/src/main.c
@@ -317,7 +317,7 @@
}
while (1) {
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
err = spi_send(buf);
if (err) {
LOG_ERR("Failed to send");
diff --git a/samples/bluetooth/hci_uart/src/main.c b/samples/bluetooth/hci_uart/src/main.c
index 5832f10..2e42205 100644
--- a/samples/bluetooth/hci_uart/src/main.c
+++ b/samples/bluetooth/hci_uart/src/main.c
@@ -179,7 +179,7 @@
if (remaining == 0) {
/* Packet received */
LOG_DBG("putting RX packet in queue.");
- net_buf_put(&tx_queue, buf);
+ k_fifo_put(&tx_queue, buf);
state = ST_IDLE;
}
break;
@@ -212,7 +212,7 @@
int len;
if (!buf) {
- buf = net_buf_get(&uart_tx_queue, K_NO_WAIT);
+ buf = k_fifo_get(&uart_tx_queue, K_NO_WAIT);
if (!buf) {
uart_irq_tx_disable(hci_uart_dev);
return;
@@ -253,7 +253,7 @@
int err;
/* Wait until a buffer is available */
- buf = net_buf_get(&tx_queue, K_FOREVER);
+ buf = k_fifo_get(&tx_queue, K_FOREVER);
/* Pass buffer to the stack */
err = bt_send(buf);
if (err) {
@@ -273,7 +273,7 @@
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf),
buf->len);
- net_buf_put(&uart_tx_queue, buf);
+ k_fifo_put(&uart_tx_queue, buf);
uart_irq_tx_enable(hci_uart_dev);
return 0;
@@ -403,7 +403,7 @@
while (1) {
struct net_buf *buf;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
err = h4_send(buf);
if (err) {
LOG_ERR("Failed to send");
diff --git a/samples/bluetooth/hci_uart_3wire/src/main.c b/samples/bluetooth/hci_uart_3wire/src/main.c
index 9c8a66e..7e1f105 100644
--- a/samples/bluetooth/hci_uart_3wire/src/main.c
+++ b/samples/bluetooth/hci_uart_3wire/src/main.c
@@ -211,7 +211,7 @@
LOG_DBG("Need to remove %u packet from the queue", number_removed);
while (number_removed) {
- struct net_buf *buf = net_buf_get(&h5.unack_queue, K_NO_WAIT);
+ struct net_buf *buf = k_fifo_get(&h5.unack_queue, K_NO_WAIT);
if (!buf) {
LOG_ERR("Unack queue is empty");
@@ -341,22 +341,22 @@
k_fifo_init(&tmp_queue);
/* Queue to temporary queue */
- while ((buf = net_buf_get(&h5.tx_queue, K_NO_WAIT))) {
- net_buf_put(&tmp_queue, buf);
+ while ((buf = k_fifo_get(&h5.tx_queue, K_NO_WAIT))) {
+ k_fifo_put(&tmp_queue, buf);
}
/* Queue unack packets to the beginning of the queue */
- while ((buf = net_buf_get(&h5.unack_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&h5.unack_queue, K_NO_WAIT))) {
/* include also packet type */
net_buf_push(buf, sizeof(uint8_t));
- net_buf_put(&h5.tx_queue, buf);
+ k_fifo_put(&h5.tx_queue, buf);
h5.tx_seq = (h5.tx_seq - 1) & 0x07;
unack_queue_len--;
}
/* Queue saved packets from temp queue */
- while ((buf = net_buf_get(&tmp_queue, K_NO_WAIT))) {
- net_buf_put(&h5.tx_queue, buf);
+ while ((buf = k_fifo_get(&tmp_queue, K_NO_WAIT))) {
+ k_fifo_put(&h5.tx_queue, buf);
}
}
@@ -400,13 +400,13 @@
net_buf_unref(buf);
break;
case HCI_3WIRE_LINK_PKT:
- net_buf_put(&h5.rx_queue, buf);
+ k_fifo_put(&h5.rx_queue, buf);
break;
case HCI_COMMAND_PKT:
case HCI_ACLDATA_PKT:
case HCI_ISODATA_PKT:
hexdump("=> ", buf->data, buf->len);
- net_buf_put(&tx_queue, buf);
+ k_fifo_put(&tx_queue, buf);
break;
}
}
@@ -563,7 +563,7 @@
{
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
- net_buf_put(&h5.tx_queue, buf);
+ k_fifo_put(&h5.tx_queue, buf);
return 0;
}
@@ -597,7 +597,7 @@
case K_POLL_STATE_FIFO_DATA_AVAILABLE:
if (ev->tag == 0) {
/* Wait until a buffer is available */
- buf = net_buf_get(&tx_queue, K_NO_WAIT);
+ buf = k_fifo_get(&tx_queue, K_NO_WAIT);
__ASSERT_NO_MSG(buf);
/* Pass buffer to the stack */
@@ -607,7 +607,7 @@
net_buf_unref(buf);
}
} else if (ev->tag == 2) {
- buf = net_buf_get(&h5.tx_queue, K_FOREVER);
+ buf = k_fifo_get(&h5.tx_queue, K_FOREVER);
__ASSERT_NO_MSG(buf);
type = h5_get_type(buf);
@@ -616,7 +616,7 @@
/* buf is dequeued from tx_queue and queued to unack
* queue.
*/
- net_buf_put(&h5.unack_queue, buf);
+ k_fifo_put(&h5.unack_queue, buf);
unack_queue_len++;
k_work_reschedule(&retx_work, H5_TX_ACK_TIMEOUT);
@@ -684,19 +684,19 @@
while (true) {
struct net_buf *buf, *cache;
- buf = net_buf_get(&h5.rx_queue, K_FOREVER);
+ buf = k_fifo_get(&h5.rx_queue, K_FOREVER);
hexdump("=> ", buf->data, buf->len);
if (!memcmp(buf->data, sync_req, sizeof(sync_req))) {
if (h5.link_state == ACTIVE) {
- while ((cache = net_buf_get(&h5.unack_queue, K_NO_WAIT))) {
+ while ((cache = k_fifo_get(&h5.unack_queue, K_NO_WAIT))) {
net_buf_unref(cache);
}
unack_queue_len = 0;
- while ((cache = net_buf_get(&h5.tx_queue, K_NO_WAIT))) {
+ while ((cache = k_fifo_get(&h5.tx_queue, K_NO_WAIT))) {
net_buf_unref(cache);
}
@@ -810,7 +810,7 @@
while (1) {
struct net_buf *buf;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
err = h5_queue(buf);
if (err) {
LOG_ERR("Failed to send");
diff --git a/samples/bluetooth/hci_uart_async/src/hci_uart_async.c b/samples/bluetooth/hci_uart_async/src/hci_uart_async.c
index 856ebc4..6954327 100644
--- a/samples/bluetooth/hci_uart_async/src/hci_uart_async.c
+++ b/samples/bluetooth/hci_uart_async/src/hci_uart_async.c
@@ -155,7 +155,7 @@
net_buf_add_mem(buf, hci_evt_hw_err, sizeof(hci_evt_hw_err));
/* Inject the message into the c2h queue. */
- net_buf_put(&c2h_queue, buf);
+ k_fifo_put(&c2h_queue, buf);
/* The c2h thread will send the message at some point. The host
* will receive it and reset the controller.
@@ -376,7 +376,7 @@
for (;;) {
struct net_buf *buf;
- buf = net_buf_get(&c2h_queue, K_FOREVER);
+ buf = k_fifo_get(&c2h_queue, K_FOREVER);
uart_c2h_tx(buf->data, buf->len);
net_buf_unref(buf);
}
diff --git a/samples/bluetooth/mtu_update/central/prj.conf b/samples/bluetooth/mtu_update/central/prj.conf
index ba93104..1838348 100644
--- a/samples/bluetooth/mtu_update/central/prj.conf
+++ b/samples/bluetooth/mtu_update/central/prj.conf
@@ -1,6 +1,7 @@
CONFIG_BT=y
CONFIG_BT_CENTRAL=y
CONFIG_BT_DEVICE_NAME="Zephyr Central MTU Update Sample"
+CONFIG_BT_MAX_CONN=1
CONFIG_BT_GATT_CLIENT=y
diff --git a/samples/bluetooth/mtu_update/peripheral/prj.conf b/samples/bluetooth/mtu_update/peripheral/prj.conf
index 3d7a2d6..36010a6 100644
--- a/samples/bluetooth/mtu_update/peripheral/prj.conf
+++ b/samples/bluetooth/mtu_update/peripheral/prj.conf
@@ -1,6 +1,7 @@
CONFIG_BT=y
CONFIG_BT_PERIPHERAL=y
CONFIG_BT_DEVICE_NAME="Zephyr Peripheral MTU Update Sample"
+CONFIG_BT_MAX_CONN=1
CONFIG_LOG=y
CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y
diff --git a/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c b/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
index 46ea497..1cb9980 100644
--- a/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
+++ b/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
@@ -11,11 +11,15 @@
#include <zephyr/sys/printk.h>
#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
#include <zephyr/bluetooth/uuid.h>
#include <zephyr/sys/util.h>
#define MTU_TEST_SERVICE_TYPE BT_UUID_128_ENCODE(0x2e2b8dc3, 0x06e0, 0x4f93, 0x9bb2, 0x734091c356f0)
+/* Overhead: opcode (u8) + handle (u16) */
+#define ATT_NTF_SIZE(payload_len) (1 + 2 + payload_len)
+
static const struct bt_uuid_128 mtu_test_service = BT_UUID_INIT_128(MTU_TEST_SERVICE_TYPE);
static const struct bt_uuid_128 notify_characteristic_uuid =
@@ -27,6 +31,8 @@
BT_DATA(BT_DATA_NAME_COMPLETE, CONFIG_BT_DEVICE_NAME, sizeof(CONFIG_BT_DEVICE_NAME) - 1),
};
+static struct bt_conn *default_conn;
+
static void ccc_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
{
ARG_UNUSED(attr);
@@ -46,7 +52,29 @@
printk("Updated MTU: TX: %d RX: %d bytes\n", tx, rx);
}
-static struct bt_gatt_cb gatt_callbacks = {.att_mtu_updated = mtu_updated};
+static struct bt_gatt_cb gatt_callbacks = {
+ .att_mtu_updated = mtu_updated,
+};
+
+static void connected(struct bt_conn *conn, uint8_t err)
+{
+ if (err != 0) {
+ return;
+ }
+
+ default_conn = bt_conn_ref(conn);
+}
+
+static void disconnected(struct bt_conn *conn, uint8_t reason)
+{
+ bt_conn_unref(conn);
+ default_conn = NULL;
+}
+
+BT_CONN_CB_DEFINE(conn_callbacks) = {
+ .connected = connected,
+ .disconnected = disconnected,
+};
void run_peripheral_sample(uint8_t *notify_data, size_t notify_data_size, uint16_t seconds)
{
@@ -69,6 +97,14 @@
for (int i = 0; (i < seconds) || infinite; i++) {
k_sleep(K_SECONDS(1));
- bt_gatt_notify(NULL, notify_crch, notify_data, notify_data_size);
+ /* Only send the notification if the UATT MTU supports the required length */
+ if (bt_gatt_get_uatt_mtu(default_conn) >= ATT_NTF_SIZE(notify_data_size)) {
+ bt_gatt_notify(default_conn, notify_crch, notify_data, notify_data_size);
+ } else {
+ printk("Skipping notification since UATT MTU is not sufficient."
+ "Required: %d, Actual: %d\n",
+ ATT_NTF_SIZE(notify_data_size),
+ bt_gatt_get_uatt_mtu(default_conn));
+ }
}
}
diff --git a/samples/bluetooth/tmap_bmr/src/vcp_vol_renderer.c b/samples/bluetooth/tmap_bmr/src/vcp_vol_renderer.c
index a87bd37..ed7c970 100644
--- a/samples/bluetooth/tmap_bmr/src/vcp_vol_renderer.c
+++ b/samples/bluetooth/tmap_bmr/src/vcp_vol_renderer.c
@@ -19,7 +19,7 @@
static struct bt_vcp_included vcp_included;
-static void vcs_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcs_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
if (err) {
printk("VCS state get failed (%d)\n", err);
@@ -28,7 +28,7 @@
}
}
-static void vcs_flags_cb(int err, uint8_t flags)
+static void vcs_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
if (err) {
printk("VCS flags get failed (%d)\n", err);
diff --git a/samples/bluetooth/tmap_peripheral/src/main.c b/samples/bluetooth/tmap_peripheral/src/main.c
index af6076e..083682d 100644
--- a/samples/bluetooth/tmap_peripheral/src/main.c
+++ b/samples/bluetooth/tmap_peripheral/src/main.c
@@ -298,8 +298,9 @@
if (peer_is_ums) {
/* Play media with MCP */
err = mcp_send_cmd(BT_MCS_OPC_PLAY);
- if (err != 0)
+ if (err != 0) {
printk("Error sending media play command!\n");
+ }
/* Start timer to send media pause command */
k_work_schedule(&media_pause_set_work, K_MSEC(2000));
diff --git a/samples/bluetooth/tmap_peripheral/src/vcp_vol_renderer.c b/samples/bluetooth/tmap_peripheral/src/vcp_vol_renderer.c
index a87bd37..ed7c970 100644
--- a/samples/bluetooth/tmap_peripheral/src/vcp_vol_renderer.c
+++ b/samples/bluetooth/tmap_peripheral/src/vcp_vol_renderer.c
@@ -19,7 +19,7 @@
static struct bt_vcp_included vcp_included;
-static void vcs_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcs_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
if (err) {
printk("VCS state get failed (%d)\n", err);
@@ -28,7 +28,7 @@
}
}
-static void vcs_flags_cb(int err, uint8_t flags)
+static void vcs_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
if (err) {
printk("VCS flags get failed (%d)\n", err);
diff --git a/samples/boards/esp32/deep_sleep/Kconfig b/samples/boards/esp32/deep_sleep/Kconfig
index 3cde5e7..540963e 100644
--- a/samples/boards/esp32/deep_sleep/Kconfig
+++ b/samples/boards/esp32/deep_sleep/Kconfig
@@ -7,17 +7,18 @@
bool "Enable wakeup from GPIO"
depends on !SOC_SERIES_ESP32C3
help
- This option enables wake up from deep sleep from GPIO2 and
- GPIO4. They should be connected to LOW to avoid floating pins.
- When triggering a wake up, connect one or both of the pins to
- HIGH. Note that floating pins may trigger a wake up.
+ This option enables wake-up from deep sleep using GPIO2 and
+ GPIO4. The sample enables internal pull-down on EXT1 pins to
+ avoid random wake-ups. Otherwise, external pull-down should
+ be used for the same purpose. To trigger a wake-up, connect
+ one or both of the pins to HIGH.
config EXAMPLE_GPIO_WAKEUP
bool "Enable wakeup from GPIO"
depends on SOC_SERIES_ESP32C3
help
- This option enables wake up from GPIO, only GPIO0~5 can be used
- to wake up. Be aware that when low level is used to trigger wakeup,
- an external pull-up resistance must be used.
+ This option enables wake-up from GPIO. Only GPIO0~5 can be used
+ as wake-up source. Be aware that when low level is used to trigger
+ wake-up, an external pull-up resistance is necessary.
source "Kconfig.zephyr"
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.conf b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 2ce9f6b..0000000
--- a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_EXAMPLE_GPIO_WAKEUP=y
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.overlay b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index 6235a93..0000000
--- a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- aliases {
- /* On ESP32-C3, only GPIO0~5 can be used
- * as wake-up sources
- */
- wakeup-button = &sample_button;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- sample_button: sample_button {
- gpios = <&gpio0 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
- };
- };
-};
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.conf b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 2ce9f6b..0000000
--- a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_EXAMPLE_GPIO_WAKEUP=y
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index 6235a93..0000000
--- a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- aliases {
- /* On ESP32-C3, only GPIO0~5 can be used
- * as wake-up sources
- */
- wakeup-button = &sample_button;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- sample_button: sample_button {
- gpios = <&gpio0 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
- };
- };
-};
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c6_devkitc.conf b/samples/boards/esp32/deep_sleep/boards/esp32c6_devkitc.conf
new file mode 100644
index 0000000..a235720
--- /dev/null
+++ b/samples/boards/esp32/deep_sleep/boards/esp32c6_devkitc.conf
@@ -0,0 +1,2 @@
+# Enables GPIO2 and GPIO4 as wakeup sources
+CONFIG_EXAMPLE_EXT1_WAKEUP=y
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_devkitm.conf b/samples/boards/esp32/deep_sleep/socs/esp32c3.conf
similarity index 100%
rename from samples/boards/esp32/deep_sleep/boards/esp32c3_devkitm.conf
rename to samples/boards/esp32/deep_sleep/socs/esp32c3.conf
diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_devkitm.overlay b/samples/boards/esp32/deep_sleep/socs/esp32c3.overlay
similarity index 100%
rename from samples/boards/esp32/deep_sleep/boards/esp32c3_devkitm.overlay
rename to samples/boards/esp32/deep_sleep/socs/esp32c3.overlay
diff --git a/samples/boards/esp32/deep_sleep/src/main.c b/samples/boards/esp32/deep_sleep/src/main.c
index 20d52bd..edf8b55 100644
--- a/samples/boards/esp32/deep_sleep/src/main.c
+++ b/samples/boards/esp32/deep_sleep/src/main.c
@@ -6,7 +6,8 @@
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/poweroff.h>
-#include "esp_sleep.h"
+#include <esp_sleep.h>
+#include <driver/rtc_io.h>
#define WAKEUP_TIME_SEC (20)
@@ -81,6 +82,12 @@
ext_wakeup_pin_1, ext_wakeup_pin_2);
esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask,
ESP_EXT1_WAKEUP_ANY_HIGH);
+
+ /* enable pull-down on ext1 pins to avoid random wake-ups */
+ rtc_gpio_pullup_dis(EXT_WAKEUP_PIN_1);
+ rtc_gpio_pulldown_en(EXT_WAKEUP_PIN_1);
+ rtc_gpio_pullup_dis(EXT_WAKEUP_PIN_2);
+ rtc_gpio_pulldown_en(EXT_WAKEUP_PIN_2);
#endif /* CONFIG_EXAMPLE_EXT1_WAKEUP */
#ifdef CONFIG_EXAMPLE_GPIO_WAKEUP
if (!gpio_is_ready_dt(&wakeup_button)) {
diff --git a/samples/boards/nrf/nrf53_sync_rtc/net/prj.conf b/samples/boards/nrf/nrf53_sync_rtc/net/prj.conf
index 3dab7fc..48abb73 100644
--- a/samples/boards/nrf/nrf53_sync_rtc/net/prj.conf
+++ b/samples/boards/nrf/nrf53_sync_rtc/net/prj.conf
@@ -1,6 +1,5 @@
CONFIG_LOG=y
CONFIG_NRF53_SYNC_RTC=y
CONFIG_MBOX=y
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_IPM=n
diff --git a/samples/boards/nrf/nrf53_sync_rtc/prj.conf b/samples/boards/nrf/nrf53_sync_rtc/prj.conf
index bd3897e..d71e101 100644
--- a/samples/boards/nrf/nrf53_sync_rtc/prj.conf
+++ b/samples/boards/nrf/nrf53_sync_rtc/prj.conf
@@ -3,4 +3,3 @@
CONFIG_NRF53_SYNC_RTC=y
CONFIG_IPM=n
CONFIG_MBOX=y
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/boards/nrf/system_off/CMakeLists.txt b/samples/boards/nrf/system_off/CMakeLists.txt
index 9f5e9ef..1cff779 100644
--- a/samples/boards/nrf/system_off/CMakeLists.txt
+++ b/samples/boards/nrf/system_off/CMakeLists.txt
@@ -5,4 +5,6 @@
project(nrf_system_off)
target_sources(app PRIVATE src/main.c)
-target_sources_ifdef(CONFIG_APP_RETENTION app PRIVATE src/retained.c)
+if (CONFIG_APP_USE_NRF_RETENTION OR CONFIG_APP_USE_RETAINED_MEM)
+ target_sources(app PRIVATE src/retained.c)
+endif()
diff --git a/samples/boards/nrf/system_off/Kconfig b/samples/boards/nrf/system_off/Kconfig
index b85b012..5d26d75 100644
--- a/samples/boards/nrf/system_off/Kconfig
+++ b/samples/boards/nrf/system_off/Kconfig
@@ -3,12 +3,22 @@
mainmenu "Nordic SYSTEM_OFF demo"
-config APP_RETENTION
- bool "State retention in system off"
+choice
+ prompt "Use retention"
+ optional
+
+config APP_USE_NRF_RETENTION
+ bool "Use state retention in system off using nRF POWER"
depends on SOC_COMPATIBLE_NRF52X && CRC
help
On some Nordic chips this application supports retaining
- memory while in system off. Select this to enable the
- feature.
+ memory while in system off using POWER peripheral.
+ Select this to enable the feature.
+
+config APP_USE_RETAINED_MEM
+ bool "Use state retention in system off using retained_mem driver"
+ depends on RETAINED_MEM
+
+endchoice
source "Kconfig.zephyr"
diff --git a/samples/boards/nrf/system_off/README.rst b/samples/boards/nrf/system_off/README.rst
index fa1bacb..83aeb56 100644
--- a/samples/boards/nrf/system_off/README.rst
+++ b/samples/boards/nrf/system_off/README.rst
@@ -12,16 +12,16 @@
RAM Retention
=============
-On nRF52 platforms this also can demonstrate RAM retention. By selecting
-``CONFIG_APP_RETENTION=y`` state related to number of boots, number of times
-system off was entered, and total uptime since initial power-on are retained
-in a checksummed data structure. The POWER peripheral is configured to keep
-the containing RAM section powered while in system-off mode.
+This sample can also can demonstrate RAM retention. By selecting
+``CONFIG_APP_USE_NRF_RETENTION=y`` or ``CONFIG_APP_USE_RETAINED_MEM=y``
+state related to number of boots, number of times system off was entered,
+and total uptime since initial power-on are retained in a checksummed data structure.
+RAM is configured to keep the containing section powered while in system-off mode.
Requirements
************
-This application uses nRF51 DK or nRF52 DK board for the demo.
+This application uses nRF51 DK, nRF52 DK or nRF54L15 PDK board for the demo.
Sample Output
=============
diff --git a/samples/boards/nrf/system_off/boards/nrf54l15pdk_nrf54l15_cpuapp_retained_mem.overlay b/samples/boards/nrf/system_off/boards/nrf54l15pdk_nrf54l15_cpuapp_retained_mem.overlay
new file mode 100644
index 0000000..838f039
--- /dev/null
+++ b/samples/boards/nrf/system_off/boards/nrf54l15pdk_nrf54l15_cpuapp_retained_mem.overlay
@@ -0,0 +1,23 @@
+/ {
+ cpuapp_sram@2002e000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ reg = <0x2002e000 DT_SIZE_K(4)>;
+ zephyr,memory-region = "RetainedMem";
+ status = "okay";
+
+ retainedmem0: retainedmem {
+ compatible = "zephyr,retained-ram";
+ status = "okay";
+ };
+ };
+
+ aliases {
+ retainedmemdevice = &retainedmem0;
+ };
+};
+
+&cpuapp_sram {
+ /* Shrink SRAM size to avoid overlap with retained memory region */
+ reg = <0x20000000 DT_SIZE_K(184)>;
+ ranges = <0x0 0x20000000 0x2e000>;
+};
diff --git a/samples/boards/nrf/system_off/sample.yaml b/samples/boards/nrf/system_off/sample.yaml
index 0a58d8f..da000dc 100644
--- a/samples/boards/nrf/system_off/sample.yaml
+++ b/samples/boards/nrf/system_off/sample.yaml
@@ -2,19 +2,30 @@
name: Low Power State Sample for nRF5x
common:
tags: power
- integration_platforms:
- - nrf52840dk/nrf52840
tests:
sample.boards.nrf.system_off:
build_only: true
+ integration_platforms:
+ - nrf52840dk/nrf52840
platform_allow:
+ - nrf54l15pdk/nrf54l15/cpuapp
- nrf52840dk/nrf52840
- nrf52dk/nrf52832
- nrf51dk/nrf51822
- sample.boards.nrf.system_off.retained:
+ sample.boards.nrf.system_off.nrf_retained:
build_only: true
+ integration_platforms:
+ - nrf52840dk/nrf52840
platform_allow:
- nrf52840dk/nrf52840
- nrf52dk/nrf52832
extra_configs:
- - CONFIG_APP_RETENTION=y
+ - CONFIG_APP_USE_NRF_RETENTION=y
+ sample.boards.nrf.system_off.retained_mem:
+ extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_retained_mem.overlay"
+ build_only: true
+ platform_allow:
+ - nrf54l15pdk/nrf54l15/cpuapp
+ extra_configs:
+ - CONFIG_APP_USE_RETAINED_MEM=y
+ - CONFIG_RETAINED_MEM=y
diff --git a/samples/boards/nrf/system_off/src/main.c b/samples/boards/nrf/system_off/src/main.c
index 83ae620..6e1683c 100644
--- a/samples/boards/nrf/system_off/src/main.c
+++ b/samples/boards/nrf/system_off/src/main.c
@@ -30,7 +30,7 @@
printf("\n%s system off demo\n", CONFIG_BOARD);
- if (IS_ENABLED(CONFIG_APP_RETENTION)) {
+ if (IS_ENABLED(CONFIG_APP_USE_NRF_RETENTION) || IS_ENABLED(CONFIG_APP_USE_RETAINED_MEM)) {
bool retained_ok = retained_validate();
/* Increment for this boot attempt and update. */
@@ -66,7 +66,7 @@
return 0;
}
- if (IS_ENABLED(CONFIG_APP_RETENTION)) {
+ if (IS_ENABLED(CONFIG_APP_USE_NRF_RETENTION) || IS_ENABLED(CONFIG_APP_USE_RETAINED_MEM)) {
/* Update the retained state */
retained.off_count += 1;
retained_update();
diff --git a/samples/boards/nrf/system_off/src/retained.c b/samples/boards/nrf/system_off/src/retained.c
index e418780..66f6a35 100644
--- a/samples/boards/nrf/system_off/src/retained.c
+++ b/samples/boards/nrf/system_off/src/retained.c
@@ -11,9 +11,11 @@
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
+#include <zephyr/drivers/retained_mem.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/crc.h>
+#if CONFIG_APP_USE_NRF_RETENTION
#include <hal/nrf_power.h>
/* nRF52 RAM (really, RAM AHB slaves) are partitioned as:
@@ -52,12 +54,12 @@
/* Size of a controllable RAM section in large blocks */
#define LARGE_SECTION_SIZE 32768
+#elif CONFIG_APP_USE_RETAINED_MEM
+const static struct device *retained_mem_device = DEVICE_DT_GET(DT_ALIAS(retainedmemdevice));
+#endif
+
/* Set or clear RAM retention in SYSTEM_OFF for the provided object.
*
- * @note This only works for nRF52 with the POWER module. The other
- * Nordic chips use a different low-level API, which is not currently
- * used by this function.
- *
* @param ptr pointer to the start of the retainable object
*
* @param len length of the retainable object
@@ -68,6 +70,13 @@
size_t len,
bool enable)
{
+ int rc = 0;
+
+#if CONFIG_APP_USE_NRF_RETENTION
+ /* This only works for nRF52 with the POWER module.
+ * The other Nordic chips use a different low-level API,
+ * which is not currently used by this variant.
+ */
uintptr_t addr = (uintptr_t)ptr;
uintptr_t addr_end = addr + len;
@@ -124,12 +133,21 @@
/* Move to the first address in the next section. */
addr += section_size - (addr % section_size);
} while (addr < addr_end);
+#elif CONFIG_APP_USE_RETAINED_MEM
+ /* Retention setting cannot be controlled runtime with retained_mem API */
+ (void)enable;
+ rc = retained_mem_write(retained_mem_device, 0, ptr, len);
+#else
+ #error "Unsupported retention setting"
+#endif
- return 0;
+ return rc;
}
/* Retained data must be defined in a no-init section to prevent the C
* runtime initialization from zeroing it before anybody can see it.
+ * It is not necesarry when retained_mem driver is utilized
+ * as in this case retained data is stored in an area not initialized in runtime.
*/
__noinit struct retained_data retained;
diff --git a/samples/boards/steval_stwinbx1/sensors/CMakeLists.txt b/samples/boards/steval_stwinbx1/sensors/CMakeLists.txt
new file mode 100644
index 0000000..b08f580
--- /dev/null
+++ b/samples/boards/steval_stwinbx1/sensors/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(steval_stwinbx1)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/steval_stwinbx1/sensors/README.rst b/samples/boards/steval_stwinbx1/sensors/README.rst
new file mode 100644
index 0000000..810c5af
--- /dev/null
+++ b/samples/boards/steval_stwinbx1/sensors/README.rst
@@ -0,0 +1,79 @@
+.. _steval_stwinbx1_sample_sensors:
+
+STWIN.box on-board sensors test
+###############################
+
+Overview
+********
+This sample provides an example of how to read sensors data
+from the STWIN.box board.
+
+This sample enables all sensors of STWIN.box board, and then
+periodically reads and displays data on the console from the following
+sensors:
+
+- STTS22H: Digital temperature sensor
+- IIS2MDC: 3-axis magnetometer
+- ISM330DHCX: IMU, 3D accelerometer and 3D gyroscope with Machine Learning Core and Finite State Machine
+- IIS2DLPC: high-performance ultra-low-power 3-axis accelerometer for industrial applications
+- IIS2ICLX: high-accuracy, high-resolution, low-power, 2-axis digital inclinometer with Machine Learning Core
+
+Requirements
+************
+
+The application requires a STWIN.box board connected to the PC
+through USB. The board shows up as a USB CDC class standard device.
+
+References
+**********
+
+- :ref:`steval_stwinbx1_board`
+
+Building and Running
+********************
+
+Build and flash the sample in the following way:
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/boards/steval_stwinbx1/sensors
+ :board: steval_stwinbx1
+ :goals: build flash
+
+Please note that flashing the board requires a few preliminary steps described
+in :ref:`steval_stwinbx1_board`.
+
+Then, power cycle the board by disconnecting and reconnecting the USB cable.
+Run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+ $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the correct device path automatically created on
+the host after the STWIN.box board gets connected to it,
+usually :code:`/dev/ttyUSBx` or :code:`/dev/ttyACMx` (with x being 0, 1, 2, ...).
+The ``-b`` option sets baud rate ignoring the value from config.
+
+Sample Output
+=============
+
+The sample code outputs sensors data on the STWIN.box console.
+
+ .. code-block:: console
+
+ STWIN.box dashboard
+
+ STTS22H: Temperature: 24.4 C
+ IIS2DLPC: Accel (m.s-2): x: -5.590, y: -0.536, z: 8.040
+ IIS2MDC: Magn (gauss): x: 0.420, y: -0.116, z: -0.103
+ IIS2MDC: Temperature: 21.0 C
+ ISM330DHCX: Accel (m.s-2): x: 0.000, y: 5.704, z: 7.982
+ ISM330DHCX: Gyro (dps): x: 0.026, y: -0.006, z: -0.008
+ IIS2ICLX: Accel (m.s-2): x: -0.157, y: 5.699
+ 1:: iis2dlpc trig 2021
+ 1:: iis2mdc trig 993
+ 1:: ism330dhcx acc trig 4447
+ 1:: ism330dhcx gyr trig 2223
+ 1:: iis2iclx trig 2091
+
+ <repeats endlessly every 2s>
diff --git a/samples/boards/steval_stwinbx1/sensors/prj.conf b/samples/boards/steval_stwinbx1/sensors/prj.conf
new file mode 100644
index 0000000..1b1258d
--- /dev/null
+++ b/samples/boards/steval_stwinbx1/sensors/prj.conf
@@ -0,0 +1,16 @@
+CONFIG_LOG=y
+CONFIG_PRINTK=y
+CONFIG_SPI=y
+CONFIG_I2C=y
+CONFIG_GPIO=y
+
+# config sensors
+CONFIG_SENSOR=y
+CONFIG_SENSOR_LOG_LEVEL_DBG=y
+CONFIG_STTS22H_TRIGGER_NONE=y
+CONFIG_IIS2MDC_TRIGGER_OWN_THREAD=y
+CONFIG_IIS2DLPC_TRIGGER_OWN_THREAD=y
+CONFIG_ISM330DHCX_TRIGGER_OWN_THREAD=y
+CONFIG_IIS2ICLX_TRIGGER_OWN_THREAD=y
+
+CONFIG_CBPRINTF_FP_SUPPORT=y
diff --git a/samples/boards/steval_stwinbx1/sensors/sample.yaml b/samples/boards/steval_stwinbx1/sensors/sample.yaml
new file mode 100644
index 0000000..28d5692
--- /dev/null
+++ b/samples/boards/steval_stwinbx1/sensors/sample.yaml
@@ -0,0 +1,12 @@
+sample:
+ description: STWIN.box board testing
+ name: STWIN.box board test
+tests:
+ sample.board.steval_stwinbx1.sensors:
+ harness: sensor
+ platform_allow: steval_stwinbx1
+ tags: sensors
+ depends_on:
+ - i2c
+ - spi
+ - gpio
diff --git a/samples/boards/steval_stwinbx1/sensors/src/main.c b/samples/boards/steval_stwinbx1/sensors/src/main.c
new file mode 100644
index 0000000..5e4131e
--- /dev/null
+++ b/samples/boards/steval_stwinbx1/sensors/src/main.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/led.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/sensor.h>
+
+#include <stdio.h>
+
+#ifdef CONFIG_STTS22H_TRIGGER
+static int stts22h_trig_cnt;
+
+static void stts22h_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ stts22h_trig_cnt++;
+}
+#endif
+
+#ifdef CONFIG_IIS2DLPC_TRIGGER
+static int iis2dlpc_trig_cnt;
+
+static void iis2dlpc_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ sensor_sample_fetch_chan(dev, SENSOR_CHAN_ACCEL_XYZ);
+ iis2dlpc_trig_cnt++;
+}
+#endif
+
+#ifdef CONFIG_IIS2MDC_TRIGGER
+static int iis2mdc_trig_cnt;
+
+static void iis2mdc_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ sensor_sample_fetch_chan(dev, SENSOR_CHAN_ALL);
+ iis2mdc_trig_cnt++;
+}
+#endif
+
+#ifdef CONFIG_ISM330DHCX_TRIGGER
+static int ism330dhcx_acc_trig_cnt;
+static int ism330dhcx_gyr_trig_cnt;
+
+static void ism330dhcx_acc_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ sensor_sample_fetch_chan(dev, SENSOR_CHAN_ACCEL_XYZ);
+ ism330dhcx_acc_trig_cnt++;
+}
+
+static void ism330dhcx_gyr_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ sensor_sample_fetch_chan(dev, SENSOR_CHAN_GYRO_XYZ);
+ ism330dhcx_gyr_trig_cnt++;
+}
+#endif
+
+#ifdef CONFIG_IIS2ICLX_TRIGGER
+static int iis2iclx_trig_cnt;
+
+static void iis2iclx_trigger_handler(const struct device *dev,
+ const struct sensor_trigger *trig)
+{
+ sensor_sample_fetch_chan(dev, SENSOR_CHAN_ACCEL_XYZ);
+ iis2iclx_trig_cnt++;
+}
+#endif
+
+static void stts22h_config(const struct device *stts22h)
+{
+ struct sensor_value odr_attr;
+
+ /* set STTS22H sampling frequency to 100 Hz */
+ odr_attr.val1 = 100;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(stts22h, SENSOR_CHAN_AMBIENT_TEMP,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for STTS22H\n");
+ return;
+ }
+
+#ifdef CONFIG_STTS22H_TRIGGER
+ struct sensor_trigger trig;
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_AMBIENT_TEMP;
+ sensor_trigger_set(stts22h, &trig, stts22h_trigger_handler);
+#endif
+}
+
+static void iis2dlpc_config(const struct device *iis2dlpc)
+{
+ struct sensor_value odr_attr, fs_attr;
+
+ /* set IIS2DLPC accel/gyro sampling frequency to 100 Hz */
+ odr_attr.val1 = 200;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(iis2dlpc, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for IIS2DLPC accel\n");
+ return;
+ }
+
+ sensor_g_to_ms2(16, &fs_attr);
+
+ if (sensor_attr_set(iis2dlpc, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_FULL_SCALE, &fs_attr) < 0) {
+ printk("Cannot set full scale for IIS2DLPC accel\n");
+ return;
+ }
+
+#ifdef CONFIG_IIS2DLPC_TRIGGER
+ struct sensor_trigger trig;
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_ACCEL_XYZ;
+ sensor_trigger_set(iis2dlpc, &trig, iis2dlpc_trigger_handler);
+#endif
+}
+
+static void iis2iclx_config(const struct device *iis2iclx)
+{
+ struct sensor_value odr_attr, fs_attr;
+
+ /* set IIS2ICLX accel/gyro sampling frequency to 200 Hz */
+ odr_attr.val1 = 200;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(iis2iclx, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for IIS2ICLX accel\n");
+ return;
+ }
+
+ sensor_g_to_ms2(2, &fs_attr);
+
+ if (sensor_attr_set(iis2iclx, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_FULL_SCALE, &fs_attr) < 0) {
+ printk("Cannot set full scale for IIS2ICLX accel\n");
+ return;
+ }
+
+#ifdef CONFIG_IIS2ICLX_TRIGGER
+ struct sensor_trigger trig;
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_ACCEL_XYZ;
+ sensor_trigger_set(iis2iclx, &trig, iis2iclx_trigger_handler);
+#endif
+}
+
+static void iis2mdc_config(const struct device *iis2mdc)
+{
+ struct sensor_value odr_attr;
+
+ /* set IIS2MDC sampling frequency to 100 Hz */
+ odr_attr.val1 = 100;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(iis2mdc, SENSOR_CHAN_ALL,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for IIS2MDC\n");
+ return;
+ }
+
+#ifdef CONFIG_IIS2MDC_TRIGGER
+ struct sensor_trigger trig;
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_MAGN_XYZ;
+ sensor_trigger_set(iis2mdc, &trig, iis2mdc_trigger_handler);
+#endif
+}
+
+static void ism330dhcx_config(const struct device *ism330dhcx)
+{
+ struct sensor_value odr_attr, fs_attr;
+
+ /* set ISM330DHCX sampling frequency to 416 Hz */
+ odr_attr.val1 = 416;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(ism330dhcx, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for ISM330DHCX accel\n");
+ return;
+ }
+
+ sensor_g_to_ms2(16, &fs_attr);
+
+ if (sensor_attr_set(ism330dhcx, SENSOR_CHAN_ACCEL_XYZ,
+ SENSOR_ATTR_FULL_SCALE, &fs_attr) < 0) {
+ printk("Cannot set sampling frequency for ISM330DHCX accel\n");
+ return;
+ }
+
+ /* set ISM330DHCX gyro sampling frequency to 208 Hz */
+ odr_attr.val1 = 208;
+ odr_attr.val2 = 0;
+
+ if (sensor_attr_set(ism330dhcx, SENSOR_CHAN_GYRO_XYZ,
+ SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) {
+ printk("Cannot set sampling frequency for ISM330DHCX gyro\n");
+ return;
+ }
+
+ sensor_degrees_to_rad(250, &fs_attr);
+
+ if (sensor_attr_set(ism330dhcx, SENSOR_CHAN_GYRO_XYZ,
+ SENSOR_ATTR_FULL_SCALE, &fs_attr) < 0) {
+ printk("Cannot set fs for ISM330DHCX gyro\n");
+ return;
+ }
+
+#ifdef CONFIG_ISM330DHCX_TRIGGER
+ struct sensor_trigger trig;
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_ACCEL_XYZ;
+ sensor_trigger_set(ism330dhcx, &trig, ism330dhcx_acc_trigger_handler);
+
+ trig.type = SENSOR_TRIG_DATA_READY;
+ trig.chan = SENSOR_CHAN_GYRO_XYZ;
+ sensor_trigger_set(ism330dhcx, &trig, ism330dhcx_gyr_trigger_handler);
+#endif
+}
+
+static int led_pattern_out(void)
+{
+ const struct gpio_dt_spec led0_gpio = GPIO_DT_SPEC_GET(DT_ALIAS(led0), gpios);
+ const struct gpio_dt_spec led1_gpio = GPIO_DT_SPEC_GET(DT_ALIAS(led1), gpios);
+ int i;
+
+ /* led 0 */
+ if (!gpio_is_ready_dt(&led0_gpio)) {
+ printk("%s: device not ready.\n", led0_gpio.port->name);
+ return -1;
+ }
+ gpio_pin_configure_dt(&led0_gpio, GPIO_OUTPUT_INACTIVE);
+
+ /* led 1 */
+ if (!gpio_is_ready_dt(&led1_gpio)) {
+ printk("%s: device not ready.\n", led1_gpio.port->name);
+ return -1;
+ }
+ gpio_pin_configure_dt(&led1_gpio, GPIO_OUTPUT_INACTIVE);
+
+ /* output led alternate pattern */
+ for (i = 0; i < 8; i++) {
+ gpio_pin_set_dt(&led0_gpio, ((i % 2) == 0) ? 1 : 0);
+ gpio_pin_set_dt(&led1_gpio, ((i % 2) == 1) ? 1 : 0);
+ k_msleep(100);
+ }
+
+ /* output led in sync pattern */
+ for (i = 0; i < 6; i++) {
+ gpio_pin_set_dt(&led0_gpio, ((i % 2) == 0) ? 1 : 0);
+ gpio_pin_set_dt(&led1_gpio, ((i % 2) == 0) ? 1 : 0);
+ k_msleep(250);
+ }
+
+ /* turn all leds off */
+ gpio_pin_set_dt(&led0_gpio, 0);
+ gpio_pin_set_dt(&led1_gpio, 0);
+
+ return 0;
+}
+
+int main(void)
+{
+ int cnt = 1;
+
+ /* signal that sample is started */
+ if (led_pattern_out() < 0) {
+ return -1;
+ }
+
+ printk("STWIN.box board sensor test\n");
+
+ const struct device *const stts22h = DEVICE_DT_GET_ONE(st_stts22h);
+ const struct device *const iis2mdc = DEVICE_DT_GET_ONE(st_iis2mdc);
+ const struct device *const ism330dhcx = DEVICE_DT_GET_ONE(st_ism330dhcx);
+ const struct device *const iis2dlpc = DEVICE_DT_GET_ONE(st_iis2dlpc);
+ const struct device *const iis2iclx = DEVICE_DT_GET_ONE(st_iis2iclx);
+
+ if (!device_is_ready(stts22h)) {
+ printk("%s: device not ready.\n", stts22h->name);
+ return 0;
+ }
+ if (!device_is_ready(iis2mdc)) {
+ printk("%s: device not ready.\n", iis2mdc->name);
+ return 0;
+ }
+ if (!device_is_ready(ism330dhcx)) {
+ printk("%s: device not ready.\n", ism330dhcx->name);
+ return 0;
+ }
+ if (!device_is_ready(iis2dlpc)) {
+ printk("%s: device not ready.\n", iis2dlpc->name);
+ return 0;
+ }
+ if (!device_is_ready(iis2iclx)) {
+ printk("%s: device not ready.\n", iis2iclx->name);
+ return 0;
+ }
+
+ stts22h_config(stts22h);
+ iis2mdc_config(iis2mdc);
+ ism330dhcx_config(ism330dhcx);
+ iis2dlpc_config(iis2dlpc);
+ iis2iclx_config(iis2iclx);
+
+ while (1) {
+ struct sensor_value stts22h_temp;
+ struct sensor_value iis2dlpc_accel[3];
+ struct sensor_value iis2mdc_magn[3];
+ struct sensor_value iis2mdc_temp;
+ struct sensor_value ism330dhcx_accel[3];
+ struct sensor_value ism330dhcx_gyro[3];
+ struct sensor_value iis2iclx_accel[2];
+
+#ifndef CONFIG_STTS22H_TRIGGER
+ if (sensor_sample_fetch(stts22h) < 0) {
+ printf("STTS22H Sensor sample update error\n");
+ return 0;
+ }
+#endif
+#ifndef CONFIG_IIS2MDC_TRIGGER
+ if (sensor_sample_fetch(iis2mdc) < 0) {
+ printf("IIS2MDC Magn Sensor sample update error\n");
+ return 0;
+ }
+#endif
+#ifndef CONFIG_ISM330DHCX_TRIGGER
+ if (sensor_sample_fetch(ism330dhcx) < 0) {
+ printf("ISM330DHCX IMU Sensor sample update error\n");
+ return 0;
+ }
+#endif
+#ifndef CONFIG_IIS2DLPC_TRIGGER
+ if (sensor_sample_fetch(iis2dlpc) < 0) {
+ printf("IIS2DLPC Sensor sample update error\n");
+ return 0;
+ }
+#endif
+#ifndef CONFIG_IIS2ICLX_TRIGGER
+ if (sensor_sample_fetch(iis2iclx) < 0) {
+ printf("IIS2ICLX Sensor sample update error\n");
+ return 0;
+ }
+#endif
+
+ sensor_channel_get(stts22h, SENSOR_CHAN_AMBIENT_TEMP, &stts22h_temp);
+ sensor_channel_get(iis2dlpc, SENSOR_CHAN_ACCEL_XYZ, iis2dlpc_accel);
+ sensor_channel_get(iis2mdc, SENSOR_CHAN_MAGN_XYZ, iis2mdc_magn);
+ sensor_channel_get(iis2mdc, SENSOR_CHAN_DIE_TEMP, &iis2mdc_temp);
+ sensor_channel_get(ism330dhcx, SENSOR_CHAN_ACCEL_XYZ, ism330dhcx_accel);
+ sensor_channel_get(ism330dhcx, SENSOR_CHAN_GYRO_XYZ, ism330dhcx_gyro);
+ sensor_channel_get(iis2iclx, SENSOR_CHAN_ACCEL_XYZ, iis2iclx_accel);
+
+ /* Display sensor data */
+
+ /* Clear terminal (ANSI ESC-C) */
+ printf("\0033\014");
+
+ printf("STWIN.box dashboard\n\n");
+
+ /* STTS22H temperature */
+ printf("STTS22H: Temperature: %.1f C\n",
+ sensor_value_to_double(&stts22h_temp));
+
+ /* iis2dlpc */
+ printf("IIS2DLPC: Accel (m.s-2): x: %.3f, y: %.3f, z: %.3f\n",
+ sensor_value_to_double(&iis2dlpc_accel[0]),
+ sensor_value_to_double(&iis2dlpc_accel[1]),
+ sensor_value_to_double(&iis2dlpc_accel[2]));
+
+ /* iis2mdc */
+ printf("IIS2MDC: Magn (gauss): x: %.3f, y: %.3f, z: %.3f\n",
+ sensor_value_to_double(&iis2mdc_magn[0]),
+ sensor_value_to_double(&iis2mdc_magn[1]),
+ sensor_value_to_double(&iis2mdc_magn[2]));
+
+ printf("IIS2MDC: Temperature: %.1f C\n",
+ sensor_value_to_double(&iis2mdc_temp));
+
+ /* ism330dhcx */
+ printf("ISM330DHCX: Accel (m.s-2): x: %.3f, y: %.3f, z: %.3f\n",
+ sensor_value_to_double(&ism330dhcx_accel[0]),
+ sensor_value_to_double(&ism330dhcx_accel[1]),
+ sensor_value_to_double(&ism330dhcx_accel[2]));
+
+ printf("ISM330DHCX: Gyro (dps): x: %.3f, y: %.3f, z: %.3f\n",
+ sensor_value_to_double(&ism330dhcx_gyro[0]),
+ sensor_value_to_double(&ism330dhcx_gyro[1]),
+ sensor_value_to_double(&ism330dhcx_gyro[2]));
+
+ /* iis2iclx */
+ printf("IIS2ICLX: Accel (m.s-2): x: %.3f, y: %.3f\n",
+ sensor_value_to_double(&iis2iclx_accel[0]),
+ sensor_value_to_double(&iis2iclx_accel[1]));
+
+#ifdef CONFIG_STTS22H_TRIGGER
+ printk("%d:: stts22h trig %d\n", cnt, stts22h_trig_cnt);
+#endif
+
+#ifdef CONFIG_IIS2DLPC_TRIGGER
+ printk("%d:: iis2dlpc trig %d\n", cnt, iis2dlpc_trig_cnt);
+#endif
+
+#if defined(CONFIG_IIS2MDC_TRIGGER)
+ printk("%d:: iis2mdc trig %d\n", cnt, iis2mdc_trig_cnt);
+#endif
+
+#ifdef CONFIG_ISM330DHCX_TRIGGER
+ printk("%d:: ism330dhcx acc trig %d\n", cnt, ism330dhcx_acc_trig_cnt);
+ printk("%d:: ism330dhcx gyr trig %d\n", cnt, ism330dhcx_gyr_trig_cnt);
+#endif
+
+#ifdef CONFIG_IIS2ICLX_TRIGGER
+ printk("%d:: iis2iclx trig %d\n", cnt, iis2iclx_trig_cnt);
+#endif
+
+ k_msleep(2000);
+ }
+}
diff --git a/samples/boards/stm32/bluetooth/interactive_gui/src/main.c b/samples/boards/stm32/bluetooth/interactive_gui/src/main.c
index 82d008e..fa41fd5 100644
--- a/samples/boards/stm32/bluetooth/interactive_gui/src/main.c
+++ b/samples/boards/stm32/bluetooth/interactive_gui/src/main.c
@@ -314,7 +314,7 @@
if (remaining == 0) {
/* Packet received */
LOG_DBG("putting RX packet in queue.");
- net_buf_put(&tx_queue, buf);
+ k_fifo_put(&tx_queue, buf);
state = ST_IDLE;
}
break;
@@ -343,7 +343,7 @@
int len;
if (!buf) {
- buf = net_buf_get(&uart_tx_queue, K_NO_WAIT);
+ buf = k_fifo_get(&uart_tx_queue, K_NO_WAIT);
if (!buf) {
uart_irq_tx_disable(hci_uart_dev);
return;
@@ -384,7 +384,7 @@
uint8_t response[16];
/* Wait until a buffer is available */
- buf = net_buf_get(&tx_queue, K_FOREVER);
+ buf = k_fifo_get(&tx_queue, K_FOREVER);
buf_type = bt_buf_get_type(buf);
if (buf_type == H4_ST_VND_CMD) {
len = parse_cmd(buf->data, buf->len, response);
@@ -411,7 +411,7 @@
static int h4_send(struct net_buf *buf)
{
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
- net_buf_put(&uart_tx_queue, buf);
+ k_fifo_put(&uart_tx_queue, buf);
uart_irq_tx_enable(hci_uart_dev);
return 0;
}
@@ -450,7 +450,7 @@
while (1) {
struct net_buf *buf;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
err = h4_send(buf);
if (err) {
LOG_ERR("Failed to send");
diff --git a/samples/drivers/adc/adc_dt/boards/apollo3_evb.conf b/samples/drivers/adc/adc_dt/boards/apollo3_evb.conf
new file mode 100644
index 0000000..5df721f
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/apollo3_evb.conf
@@ -0,0 +1 @@
+CONFIG_MAIN_STACK_SIZE=4096
diff --git a/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay b/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay
new file mode 100644
index 0000000..2b8732f
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+ zephyr,user {
+ io-channels = <&adc0 4>, <&adc0 7>;
+ };
+};
+
+&adc0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+};
diff --git a/samples/drivers/adc/adc_dt/boards/apollo3p_evb.conf b/samples/drivers/adc/adc_dt/boards/apollo3p_evb.conf
new file mode 100644
index 0000000..5df721f
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/apollo3p_evb.conf
@@ -0,0 +1 @@
+CONFIG_MAIN_STACK_SIZE=4096
diff --git a/samples/drivers/adc/adc_dt/boards/apollo3p_evb.overlay b/samples/drivers/adc/adc_dt/boards/apollo3p_evb.overlay
new file mode 100644
index 0000000..2b8732f
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/apollo3p_evb.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+ zephyr,user {
+ io-channels = <&adc0 4>, <&adc0 7>;
+ };
+};
+
+&adc0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+};
diff --git a/samples/drivers/adc/adc_sequence/src/main.c b/samples/drivers/adc/adc_sequence/src/main.c
index 0e401f9..60bde60 100644
--- a/samples/drivers/adc/adc_sequence/src/main.c
+++ b/samples/drivers/adc/adc_sequence/src/main.c
@@ -10,6 +10,9 @@
/* ADC node from the devicetree. */
#define ADC_NODE DT_ALIAS(adc0)
+/* Auxiliary macro to obtain channel vref, if available. */
+#define CHANNEL_VREF(node_id) DT_PROP_OR(node_id, zephyr_vref_mv, 0)
+
/* Data of ADC device specified in devicetree. */
static const struct device *adc = DEVICE_DT_GET(ADC_NODE);
@@ -17,6 +20,9 @@
static const struct adc_channel_cfg channel_cfgs[] = {
DT_FOREACH_CHILD_SEP(ADC_NODE, ADC_CHANNEL_CFG_DT, (,))};
+/* Data array of ADC channel voltage references. */
+static uint32_t vrefs_mv[] = {DT_FOREACH_CHILD_SEP(ADC_NODE, CHANNEL_VREF, (,))};
+
/* Get the number of channels defined on the DTS. */
#define CHANNEL_COUNT ARRAY_SIZE(channel_cfgs)
@@ -54,6 +60,9 @@
printf("Could not setup channel #%d (%d)\n", i, err);
return 0;
}
+ if (channel_cfgs[i].reference == ADC_REF_INTERNAL) {
+ vrefs_mv[i] = adc_ref_internal(adc);
+ }
}
#ifndef CONFIG_COVERAGE
@@ -82,12 +91,12 @@
val_mv = channel_reading[sample_index][channel_index];
printf("- - %" PRId32, val_mv);
- err = adc_raw_to_millivolts(channel_cfgs[channel_index].reference,
+ err = adc_raw_to_millivolts(vrefs_mv[channel_index],
channel_cfgs[channel_index].gain,
CONFIG_SEQUENCE_RESOLUTION, &val_mv);
/* conversion to mV may not be supported, skip if not */
- if ((err < 0) || channel_cfgs[channel_index].reference == 0) {
+ if ((err < 0) || vrefs_mv[channel_index] == 0) {
printf(" (value in mV not available)\n");
} else {
printf(" = %" PRId32 "mV\n", val_mv);
diff --git a/samples/drivers/counter/alarm/boards/esp32c3_luatos_core.overlay b/samples/drivers/counter/alarm/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index 241947b..0000000
--- a/samples/drivers/counter/alarm/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,3 +0,0 @@
-&timer0 {
- status = "okay";
-};
diff --git a/samples/drivers/counter/alarm/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/samples/drivers/counter/alarm/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index 241947b..0000000
--- a/samples/drivers/counter/alarm/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,3 +0,0 @@
-&timer0 {
- status = "okay";
-};
diff --git a/samples/drivers/counter/alarm/boards/esp32c3_devkitm.overlay b/samples/drivers/counter/alarm/socs/esp32c3.overlay
similarity index 100%
rename from samples/drivers/counter/alarm/boards/esp32c3_devkitm.overlay
rename to samples/drivers/counter/alarm/socs/esp32c3.overlay
diff --git a/samples/drivers/flash_shell/sample.yaml b/samples/drivers/flash_shell/sample.yaml
index 65d2ed6..1e07d99 100644
--- a/samples/drivers/flash_shell/sample.yaml
+++ b/samples/drivers/flash_shell/sample.yaml
@@ -13,6 +13,7 @@
- gd32f350r_eval
- arduino_portenta_h7/stm32h747xx/m4
- arduino_giga_r1/stm32h747xx/m4
+ - nucleo_h755zi_q/stm32h755xx/m4
harness: keyboard
min_ram: 12
integration_platforms:
diff --git a/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.conf
index 83d68d0..569f94a 100644
--- a/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,2 +1 @@
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_SOC_NRF53_CPUNET_ENABLE=y
diff --git a/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.conf b/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
index 665e456..e57e7e2 100644
--- a/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
+++ b/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
@@ -1,2 +1 @@
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_BUILD_OUTPUT_EXE=n
diff --git a/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.conf
deleted file mode 100644
index a1ab15f..0000000
--- a/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index 899a7cb..a3ee9c3 100644
--- a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -18,3 +18,7 @@
&cpurad_bellboard {
status = "okay";
};
+
+&uart136 {
+ /delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
index 049f243..2ad53d2 100644
--- a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
+++ b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
@@ -18,3 +18,7 @@
&cpuppr_vevif {
status = "okay";
};
+
+&uart135 {
+ /delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay b/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
index cf23243..20ce53c 100644
--- a/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
+++ b/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
@@ -18,3 +18,7 @@
&cpuflpr_vevif_tx {
status = "okay";
};
+
+&uart30 {
+ /delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay b/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
index cf23243..20ce53c 100644
--- a/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
+++ b/samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
@@ -18,3 +18,7 @@
&cpuflpr_vevif_tx {
status = "okay";
};
+
+&uart30 {
+ /delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/virtualization/ivshmem/doorbell/src/ivshmem.c b/samples/drivers/virtualization/ivshmem/doorbell/src/ivshmem.c
index 82f7c2b..b039ef7 100644
--- a/samples/drivers/virtualization/ivshmem/doorbell/src/ivshmem.c
+++ b/samples/drivers/virtualization/ivshmem/doorbell/src/ivshmem.c
@@ -197,8 +197,9 @@
int ret;
ret = setup_ivshmem(true);
- if (ret < 0)
+ if (ret < 0) {
return;
+ }
ivshmem_event_loop(&shmem_ctx);
/*
* if ivshmem_event_loop() returns, it means the function failed
diff --git a/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay
new file mode 100644
index 0000000..94e0d71
--- /dev/null
+++ b/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+ status = "okay";
+};
diff --git a/samples/net/cellular_modem/boards/mg100.conf b/samples/net/cellular_modem/boards/mg100.conf
index c19245d..3b6ae6e 100644
--- a/samples/net/cellular_modem/boards/mg100.conf
+++ b/samples/net/cellular_modem/boards/mg100.conf
@@ -1,2 +1,3 @@
CONFIG_MODEM_HL7800=n
-CONFIG_UART_ASYNC_API=y
+CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=255
+CONFIG_NET_BUF_TX_COUNT=32
diff --git a/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf b/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf
index c19245d..3b6ae6e 100644
--- a/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf
+++ b/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf
@@ -1,2 +1,3 @@
CONFIG_MODEM_HL7800=n
-CONFIG_UART_ASYNC_API=y
+CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=255
+CONFIG_NET_BUF_TX_COUNT=32
diff --git a/samples/net/ptp/README.rst b/samples/net/ptp/README.rst
index 7134393..33d21d4 100644
--- a/samples/net/ptp/README.rst
+++ b/samples/net/ptp/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: ptp
:name: PTP
- :relevant-api: ptp ptp_time ptp_clock
+ :relevant-api: ptp
Enable PTP support and monitor messages and events via logging.
diff --git a/samples/net/sockets/coap_client/README.rst b/samples/net/sockets/coap_client/README.rst
index ffcd819..e5f9f87 100644
--- a/samples/net/sockets/coap_client/README.rst
+++ b/samples/net/sockets/coap_client/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: coap-client
:name: CoAP client
- :relevant-api: coap udp
+ :relevant-api: coap
Use the CoAP library to implement a client that fetches a resource.
diff --git a/samples/net/sockets/coap_download/README.rst b/samples/net/sockets/coap_download/README.rst
index 458256d..fb1b06b 100644
--- a/samples/net/sockets/coap_download/README.rst
+++ b/samples/net/sockets/coap_download/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: coap-download
:name: CoAP download
- :relevant-api: coap_client_interface
+ :relevant-api: coap
Use the CoAP client API to download data via a GET request
diff --git a/samples/net/sockets/coap_server/README.rst b/samples/net/sockets/coap_server/README.rst
index a2962b9..9aadbea 100644
--- a/samples/net/sockets/coap_server/README.rst
+++ b/samples/net/sockets/coap_server/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: coap-server
:name: CoAP service
- :relevant-api: coap coap_service udp
+ :relevant-api: coap coap_service
Use the CoAP server subsystem to register CoAP resources.
diff --git a/samples/net/wifi/boards/rd_rw612_bga.conf b/samples/net/wifi/boards/rd_rw612_bga.conf
index ec87bf4..f517d49 100644
--- a/samples/net/wifi/boards/rd_rw612_bga.conf
+++ b/samples/net/wifi/boards/rd_rw612_bga.conf
@@ -55,6 +55,7 @@
CONFIG_NET_IPV6_FRAGMENT_MAX_COUNT=3
CONFIG_NET_IPV6_FRAGMENT_MAX_PKT=8
CONFIG_NET_IPV6_FRAGMENT_TIMEOUT=3
+CONFIG_NET_DHCPV4_SERVER_ICMP_PROBE_TIMEOUT=100
# net threads priority
CONFIG_NET_TC_THREAD_PRIO_CUSTOM=y
@@ -74,6 +75,7 @@
CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_MBEDTLS_PSA=y
CONFIG_WIFI_NM_WPA_SUPPLICANT_INF_MON=n
CONFIG_WIFI_NM_MAX_MANAGED_INTERFACES=2
+CONFIG_SAE_PWE_EARLY_EXIT=y
# Enable mbedtls
CONFIG_MBEDTLS=y
diff --git a/samples/net/wifi/test_certs/ca.pem b/samples/net/wifi/test_certs/ca.pem
new file mode 100644
index 0000000..70a234d
--- /dev/null
+++ b/samples/net/wifi/test_certs/ca.pem
@@ -0,0 +1,29 @@
+-----BEGIN CERTIFICATE-----
+MIIE9zCCA9+gAwIBAgIUNX/wAWvB0xblUUghlsoear4f6kkwDQYJKoZIhvcNAQEL
+BQAwgZIxCzAJBgNVBAYTAkZSMQ8wDQYDVQQIDAZSYWRpdXMxEjAQBgNVBAcMCVNv
+bWV3aGVyZTEUMBIGA1UECgwLRXhhbXBsZSBJbmMxIDAeBgkqhkiG9w0BCQEWEWFk
+bWluQGV4YW1wbGUub3JnMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRpZmljYXRlIEF1
+dGhvcml0eTAeFw0yNDA4MDcxODQzMDZaFw0yNDEwMDYxODQzMDZaMIGSMQswCQYD
+VQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hlcmUxFDAS
+BgNVBAoMC0V4YW1wbGUgSW5jMSAwHgYJKoZIhvcNAQkBFhFhZG1pbkBleGFtcGxl
+Lm9yZzEmMCQGA1UEAwwdRXhhbXBsZSBDZXJ0aWZpY2F0ZSBBdXRob3JpdHkwggEi
+MA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCzR3RL3+70yN+1Nx0bAXT60qqf
+AxCk/NXphq5cxUT5skXc97KUUnIQ1SaLAin8WHRS8Idajywlo0ULpCeoOj35aPI/
+kTUu4P2Rx5p1DYgquTGjW6fS4p5c65y75BWoukng5DQp/kVpo4OcRMUncexGxBET
+1IkpuXGlvQyEKB5I+TgYe4eEXpdn+0A2Nytw9kpSzrd26JofWOO2ZtVCgISnj7ID
+B7ErVzStuHg+rMKVI2SU966CH78lNuIIQFKrg8NoWRQI1zMMouU7hj6EL7cZcvA/
+MW9SIFpzkfC4xq0EnOMzg/D3p4k8ah6MikHf8FqDdBBfPUcYU0rG9+zpQdb3AgMB
+AAGjggFBMIIBPTAdBgNVHQ4EFgQUQl34Jn7xx5zTXckus4k09ScmfUYwgdIGA1Ud
+IwSByjCBx4AUQl34Jn7xx5zTXckus4k09ScmfUahgZikgZUwgZIxCzAJBgNVBAYT
+AkZSMQ8wDQYDVQQIDAZSYWRpdXMxEjAQBgNVBAcMCVNvbWV3aGVyZTEUMBIGA1UE
+CgwLRXhhbXBsZSBJbmMxIDAeBgkqhkiG9w0BCQEWEWFkbWluQGV4YW1wbGUub3Jn
+MSYwJAYDVQQDDB1FeGFtcGxlIENlcnRpZmljYXRlIEF1dGhvcml0eYIUNX/wAWvB
+0xblUUghlsoear4f6kkwDwYDVR0TAQH/BAUwAwEB/zA2BgNVHR8ELzAtMCugKaAn
+hiVodHRwOi8vd3d3LmV4YW1wbGUuY29tL2V4YW1wbGVfY2EuY3JsMA0GCSqGSIb3
+DQEBCwUAA4IBAQCP4qUyKkYD6hXaozV29opSo1sOdQ+voCe9lCTMnFEaCvCO22IX
+ViyvNyR6cDt/wa2eeXCRzhOr8vXLyxUOZg0gMDuOxhMBWhdJUNowNrk5jLw2RdFG
+OOB53m2JW2E7JNVsheRzKa+98xW7BFjkZKjrowFptZFDrtPFbGg1ETy+mPY74RVj
+T+ebESqd/Q/hQUQYfvLUgbcVUF28nXzQ3EWxSL64wpheFDbYEdE97h3Z4tJX7MYi
+nOdw+Hn8jss8xCjijk99MgI08GYqgYqCZP7Xka9tyOmD7FYFVnderU+aTCxEYbK3
+9/R7Y+PEaqamKZKXhYh8isjZz/EOiHYz2YjU
+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/client-key.pem b/samples/net/wifi/test_certs/client-key.pem
new file mode 100644
index 0000000..20ca079
--- /dev/null
+++ b/samples/net/wifi/test_certs/client-key.pem
@@ -0,0 +1,30 @@
+-----BEGIN ENCRYPTED PRIVATE KEY-----
+MIIFHDBOBgkqhkiG9w0BBQ0wQTApBgkqhkiG9w0BBQwwHAQIKh6bYnzze8sCAggA
+MAwGCCqGSIb3DQIJBQAwFAYIKoZIhvcNAwcECNtt6KHyCgBPBIIEyPOdtbZFuRkf
+NoEhloVT9ZbxSfYUOoD86w6OUgLW9I9zgH7v1lZ+Q6YnZ6lPxi+NthUvZZNd0M4f
+rEAkJMeVqCImk9C5DYUdsEyVxxbWCiBKuO+j14S8RaetKvTVlYZjdkdbwW4chwLs
+joPtKUtRMhWdQ5XF9qtVhmKjqHHTEFhOXP/VMCd6bNOkjzneuUDlLj+EOl8K1NVZ
+tpZUi6D2p0tksrMokgl3n0Esee4W6XKemJ8KyLkA34QGG/c2MQyQnBzqo+9FnLvr
+uX5DmApiichLMYDMssQjfyVUsDTz1bolTCWZcY2gz7zoHSJ3Twa4uf0D/Syi/pU5
+c4m1DvfY+BDt7GPG9S6eQHEIp/7m6jCKX90jYi297nEcJjYkXVUDe4Nx7a+oZkc4
+OIKP7VTVnhuUSjbN5h0UB1yNMA9t65IsXLPVVtn4b+eC/4RZyJAYuzJD8xpb9u4r
+bXl0qMW1bPyU2qdC5oheM2oLIvuSBKuRf2vvqKt7c5mahTWIUxNckkNeSQghJxw5
+uEgG/ji+ggL9YfPQiMt8Ps4754/mtOfzXGX3UTniuSpo7ddonqDQpHBvNiRdy6Dl
+pQTJczykNOe5HaMsfa/hyu22AVVKWQDLacFLvRqqps5JiH2A1dzBfU/GVeGYcl84
+BZUVO56tGMY64t/StqADVrW7AxTLB0tV90uNSg16oRQkRDIx5R5/Q9xlILCSPdvN
+i8qR6jY0wLgEot5hweCnbYjQ79n7H8NKAHe52TNbYts/S6jjqdWNu19JpNHV8Z7v
+aGlf5Puk4U+A8MhyjTVgWoOW+GNmyEiMXOTz66nrhtDFy3nzPjwQcMQtj3yTzHnS
+0P80cdY/k2tfBPT4BTbIoKbuuuXLXKQ0jZ0AETu1Z12Q7G6C5f0fOJ5m97qLOvbE
+dMgYPeeulbLr6Gw7CYfTE1wSj795z2d4SpbRSVNyN+iFccFD4tXhWk+lf8ym4/A2
+hsI2SS9TxBR93Fje6oTdeAlC0DIpY8117W4GhU+IZm9HqpD+DVcnLOAzRIl7urlW
+jqpEkZXce+CV9L614hdAjUHQZOj43P3Q/zXEr/ZcVP6+yuLFCf+JbRXUglUgpdQh
+McGVV09tL+Qbb/28yEygiw2m8HFAoUgMc2st4IkkO7XKX3Q8WVDSgqE4olAVE74g
+1OB8w2R96+conCWYJfLCGM5lwsGeB1z8Q/NncKToulnqTKft7Rg8SFyMxVlzygPr
+P9AMhS+wqXHbzhYb+dwD+DsbAtKl0Urp1ZjHSQrOrVtctDCnEX1Bx5ek+AgNExNp
+tv2yBnsBcCLXy5UZYw9rAH+m7t8dAjGOYV3he4GotjCjyq+VcZgpzG2iWCHOhfob
+1xtm030/Xuc4TfX76rWithXggSeKEhuqL2ERa/+OOC/JjE4omdmL9GVrr4vxt37U
+MeJpxymYEP05QfRxcbvJB1L+cGv4Tgy3XgikK8ClUQqKvPntXIoX4cga8O5FE5KB
+5H714hGK/JplhbCDDomi/hRHZHxae2MLnHgq4Rj7JWZ+iTUvLncfMdBBFdHF4qkr
+ZbhwJ3KIAbCcSvXFoYJy1oOOitYhgoAKksyVNrzOMiYMfQ3YKc+6sF6lHOFllawD
+RYTUnfN5ztaxB8OpKaPtig==
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/client.pem b/samples/net/wifi/test_certs/client.pem
new file mode 100644
index 0000000..0de5748
--- /dev/null
+++ b/samples/net/wifi/test_certs/client.pem
@@ -0,0 +1,64 @@
+Bag Attributes
+ localKeyID: DF 33 79 D4 52 3A 61 87 BF DD 0C BC BB 90 F5 1D 8C D0 02 1E
+subject=C = FR, ST = Radius, O = Example Inc, CN = Example user, emailAddress = user.example@example.org
+issuer=C = FR, ST = Radius, L = Somewhere, O = Example Inc, emailAddress = admin@example.org, CN = Example Certificate Authority
+-----BEGIN CERTIFICATE-----
+MIIEgTCCA2mgAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBkjELMAkGA1UEBhMCRlIx
+DzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQKDAtF
+eGFtcGxlIEluYzEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5vcmcxJjAk
+BgNVBAMMHUV4YW1wbGUgQ2VydGlmaWNhdGUgQXV0aG9yaXR5MB4XDTI0MDgwNzE4
+NDMwN1oXDTI0MTAwNjE4NDMwN1owdDELMAkGA1UEBhMCRlIxDzANBgNVBAgMBlJh
+ZGl1czEUMBIGA1UECgwLRXhhbXBsZSBJbmMxFTATBgNVBAMMDEV4YW1wbGUgdXNl
+cjEnMCUGCSqGSIb3DQEJARYYdXNlci5leGFtcGxlQGV4YW1wbGUub3JnMIIBIjAN
+BgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAz6mI+213GsAcquAlq0/MMUDbbpjz
+PxurB+9NoQ6xNpoUzK8x8hhC8tORkXi2stCbZbIFISMdtuDzshZ7BBLA32lX5/q0
+YNCS6czcuxnkbFgunfaA6VupK/dx+9GULTMKa7TVNyIhid9NQBowz2BB8n4lHQjS
+g3fkZgR771e3xqZ8xaEKlA8+/lCRHUtjiUtzSFMbQDBA+Liu9cRpb+4xk93CNOk6
+WmHI7reGzJrC8YPc3ngFRvp1ujw0BHlp+AYfwnPPTn7mWYBgJQwfrkECzt/vTIhS
+CJgsvM2bMI/HK30EvCLJb3NheSfZFo5fzkmWk8NK8B1p/d6/SPoul8L2QQIDAQAB
+o4H+MIH7MAkGA1UdEwQCMAAwCwYDVR0PBAQDAgXgMBMGA1UdJQQMMAoGCCsGAQUF
+BwMCMDYGA1UdHwQvMC0wK6ApoCeGJWh0dHA6Ly93d3cuZXhhbXBsZS5jb20vZXhh
+bXBsZV9jYS5jcmwwNwYIKwYBBQUHAQEEKzApMCcGCCsGAQUFBzABhhtodHRwOi8v
+d3d3LmV4YW1wbGUub3JnL29jc3AwGwYDVR0RBBQwEoEQdXNlckBleGFtcGxlLm9y
+ZzAdBgNVHQ4EFgQUpBSja2rvRXhlulUyZ8ZEDLS0j4AwHwYDVR0jBBgwFoAUQl34
+Jn7xx5zTXckus4k09ScmfUYwDQYJKoZIhvcNAQELBQADggEBAENOA88x6RMfT73L
+hBQBT45qqvLK4GRGhqXDcj/E4hiZ0fX39r5PSUA+rbVbWjlJzW+gnsHWIdDASg4H
+ZlMSYCgU6PN7hhJ1gmc0736V1t1vS63x6502fzNG7TMEvyWP3iadVjkn+sH8Q83d
+AHwJjaKEq0SQYQof4QZZcxaBVLwh0buck4QLpeBYKeGpEiRK+AWireJMNFmBRHpG
+R2E0I/B/duICWoL/8E/PCK7Ys7fUcGtIekEOCToDPW39uoU79mTjXrv+F3NO6Z6p
+CwY9WqlHV0jLrfpdEMQuN2Pl0Qi8N2R0vJLrXRxbSrIkQbZtKyUG11XQBPgl5ZPz
+KbHL9JU=
+-----END CERTIFICATE-----
+Bag Attributes
+ localKeyID: DF 33 79 D4 52 3A 61 87 BF DD 0C BC BB 90 F5 1D 8C D0 02 1E
+Key Attributes: <No Attributes>
+-----BEGIN ENCRYPTED PRIVATE KEY-----
+MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIj62qIYenEeYCAggA
+MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBD+aD/Nfhvs8bsr44gG36xRBIIE
+0OA3BuJdNL3yo5SOVFXMbWeMj13B5yvQwqLRCPJmDesNSy6I2OLVQKr571IiuwBf
+xNytF8MNfZ/OAI7FcMDqf/so9s9zQZlgR5jZKzoR8c0d6NiXboW7HHlO1tk7PhwW
+T2dSFBcmfI0N4zug5vTYGVnOBtwk9F0BlFs8HZwa/5wXfdLnJVXT4l8enIU45Ssb
+MJXrLNZ8SRMSjnsatrPqPhRMtLharGhOAItj4uQ770WbjdMgPejeZOMQ6NAEl1CL
+NPeikRKZQzeBCBYnbAfOSTPNy0i2q28vKzc5e0gHPzqWg6r41/XsCGiKi/4pkwxE
+ZDhbBCLeGdlB7KX4cv6KTp5PtBKMrh4BxGsWrAALqOdt/nsNl8oPBe8j6/iSWDDw
+xJbemI8nFXAI6jAiz4RZS516eHJQT9uEpYdPUfluT17PPOotmjwkL2XuaMDjYOjD
+LOFSIX1Y8L7DPhayViY7hGyBWFDgozIl+us7H7q27SIJQAtoG4gS6w2qTE6UmDbG
+xqxluuQadfnrhtenpVJMwRQzf24txRsuHDTB/6EY3lqZhOvGZzwUV4RqJgg7G5Ix
+YUCiRrNrWGgbViTGpR87GkhBc84pXlTdIVb/bxl1myJ4QFya2oG4PjMK+wxlGJ3q
+8Ght0sz3xvDXLzoh3NYBBhqOj1zKHcUoVMLmxd+GinAy4FENc3cbZjAaTDprPbze
+1368MvGQkcwgxHmqhPIRaz+GPtLhxjPO/SDIkZdzwAGvy8AKS5HTAGcSvbcjcjXE
+3cY4DObY19MwUfsedXYcDzyEKS6OTgNSbfXPStBhijKA+joOzUKf36xEipV3J9fa
+9YtXf5MALkUcLqGKCa4OybAktvN/VBnZfieOyCM3vcTHimmyDhuyjxzJptMTjiH3
+BaBxgZpm0FJVKjTJ3+xkmIeMA8p475Aocs8F7aHqIO/MEMHDB5MuCui3h+Mzccha
+eR2e4Ldv5v8yFR+3Q+MIq8rELtIeNgG/ANldJEWt7paLsRXMXzNah1rdHb6oaDLa
+iou8ZcOKI6kBxj6GxcGN2HicWbqAXgoHAVN59siVOSUGI2rmCxxj1v38oY61IahZ
+k9nde23oAhTnO02ovRXkVNArBE3cEQPbBqwv09rrO/HQqHXRVNu/qFuA/oEopzjI
+lZFUel4IjUQJgk7+1pY/OQzJQR9wfEXMOW4fXG+tL90sIypv115CbYXiUy3tOFcs
+XX5QhDnrSo69Be4ZJQBBY9JEtOPlZCA9C+6Q0zxpNctfj091N7e8nWg2a+DHzpFz
+Vdoa+xGCUMkJZopsnjEStfSTYqgCuPRSRIf8a1i9U2QnLXOFjmu2YUfa06JuQIXK
+lpJxyMmUmd07KiTH3Da0/3V9W++zSlVpT4hHD6zvZ/OzpPKL74cGgtNFMOVkFCjr
+KUcrg7JCxrVb1zZ/Y6CIdpRMFv5/94M67D8hX7aSiPgzGXwwuUzZlygbOZa97s3U
+nKc7ZgVqiNCR6HH2Vhc2A2fuu9aErdnqr6tcbxiWTVORSQxIHCchX/+5+4XtKrHm
+EOPmhwehDEsyFqHwBd/T8xdz/wb8ct+ce1HbzRe8UXjeGsTSPQVuMF4wjHP1MvEl
+0BTRDQlqETtBvtxzZJ7cABWpZqdrZEUtrdD90jd6ZQrF
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/server-key.pem b/samples/net/wifi/test_certs/server-key.pem
new file mode 100644
index 0000000..c9defa1
--- /dev/null
+++ b/samples/net/wifi/test_certs/server-key.pem
@@ -0,0 +1,30 @@
+-----BEGIN ENCRYPTED PRIVATE KEY-----
+MIIFHDBOBgkqhkiG9w0BBQ0wQTApBgkqhkiG9w0BBQwwHAQIU44Xbg9l+1kCAggA
+MAwGCCqGSIb3DQIJBQAwFAYIKoZIhvcNAwcECBx6SOeZLPFiBIIEyBbU4bj1/Sq0
+W5O13hWtq34nTHG+HtgOG61u8659V+0Txbd6E6gBlMTUDtczKCb2BS7D2uugSwTR
+Xj1CeLha1qfsWT3IEe38KB/r+TXA1CESblkHBeYjHYOhOoRSNjg8e+QddFim4uuN
+6eCqgia4jJjC4jT7gLhoUgMtLKxGiw/iVsLme//p1czB2sNNy441Cp2smwvP6GqC
+rymGKgmmEa3pqFm72jO77kev71gUYxPJLXg6bGJ3HBBD0iN79rlCgMTru4s/C/G6
+VoTLCxJrYNiRGsCNu1PM4DtZgQtL32il+u/thZzE6cmh6Yqzkv9G8JXRIakoZctN
+JOwOgbyQLwbAV/0OpZcX0rWKGbO2AO1RmayEJrTBp98qbOW1SrJf2HVAqzevaxOy
+ZqyLbq80x+6wH1sg200tnfwGO/2nz1U7yDTJ4tMuMeJYvAHB5luXYOBrL7AmUJjZ
+CLY/BaN90amz3h1/ZeooMslB1ldjNznLYfrmYc7E1UKWUd5CRjbh6f+k/iYp1wuw
+W2O9qW/aatQyrcWMLboJLTs9XarTFXYSA66bvhPfP/lP4BPm4eQM1xCS7qSjbJMK
+OuTX9J++ZzNIiUJjFTAWW4cIEKkJ+PpljTgdcfnwUCGUcxuqJaVbWVrPstc2tyjJ
+8Ravtr5Fp79dYsD5xSB31ATiAVehp0Zn7lorwmFZ1fhZNMOaFjDk0e3GJPrWgTGY
+DUyeN2Ec/lY76+nTKLqpCPmP/aM3uOEsKEXmtuiYONnz1ZcRSXqAfZKW0Sv9iEQA
+IK31lNuU6CULXM6aUn0lwdoYKZ1S7SPwK6UmqSimBb/5FF5zaZPgzHKhClsnd6EN
+ToMDw18YD1rY6jaAxZdXiaI70i7V9S3RkfjlYkiaLEmjO44yg6Ae7xL0KbOut8iB
+ZCyMHRjobFCLWPTdplQux0xzPD0FXrl8GgJBmiY8SkiFh9NKDNyB6SodjVKXsIhe
+BPsdmh9E66XfHkI16LkkoK5eKgtVDpXVAJBAI2wURIwfIzfzOJ6SExQd3capXqfr
+HpC+sJJjAPy0hHTkv3RnzX1NHqYK5gHq/WCSda/4cl8ZepF5eoyJ8h+9TJzlTDJX
+REyt5iUvKbFT3bQ3WYwWUW6lEei16KK9Cm8ivZsEQqbeG0kP6lO3pG+WNsAYRXlE
+aXg8wgFLJRS/7llaB8xiZHZ0mMsj9UAwZd7gUkp1EjDt7A6f1KlYEtIXtQ9TVXhS
+kegWYMvJOpzJoOTcZ2Yu/wNUEAnnOnXzCrr5EAD3aHUwaSHfj75y44uHrYtEKEyO
+Q1bhRhSC5rFcEEomHofy7PlJqoynxMxOd6VZdSpMr2fSDKO36aY8bGD7ST0hpHrs
+6NNbywy23G68YX6QREwcuT4EDzIQOQsl7GCSx8KVibubsYcGSuXSVlBMI9sLOtsA
+AwSAXOyGoVrmms79ekp4O4Pzq4vqE61KEh8K0/h5qDJ8+c2kqQl5eeDkDwtBYwjD
+oYKRlmCkKzoo7qW4uIeVy4ZeQIuzWcCWnSZumtBa2mLlo4w9njmwgPR0wtDU8daW
++0CL828/eNfIN3awo0VeAJ8nbZlKL2ioyND9KNXjJ2fJNuwyrWv9c5fz/NeWgv9O
+Z2S6ZI0xPgZJNQ6rLcPigA==
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/server.pem b/samples/net/wifi/test_certs/server.pem
new file mode 100644
index 0000000..12b9a54
--- /dev/null
+++ b/samples/net/wifi/test_certs/server.pem
@@ -0,0 +1,68 @@
+Bag Attributes
+ localKeyID: 70 E4 1E 20 0B 8A 3E 65 06 98 99 29 C2 A4 26 33 38 D8 94 23
+subject=C = FR, ST = Radius, O = Example Inc, CN = Example Server Certificate, emailAddress = admin@example.org
+issuer=C = FR, ST = Radius, L = Somewhere, O = Example Inc, emailAddress = admin@example.org, CN = Example Certificate Authority
+-----BEGIN CERTIFICATE-----
+MIIFZzCCBE+gAwIBAgIBATANBgkqhkiG9w0BAQsFADCBkjELMAkGA1UEBhMCRlIx
+DzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQKDAtF
+eGFtcGxlIEluYzEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5vcmcxJjAk
+BgNVBAMMHUV4YW1wbGUgQ2VydGlmaWNhdGUgQXV0aG9yaXR5MB4XDTI0MDgwNzE4
+NDMwNloXDTI0MTAwNjE4NDMwNlowezELMAkGA1UEBhMCRlIxDzANBgNVBAgMBlJh
+ZGl1czEUMBIGA1UECgwLRXhhbXBsZSBJbmMxIzAhBgNVBAMMGkV4YW1wbGUgU2Vy
+dmVyIENlcnRpZmljYXRlMSAwHgYJKoZIhvcNAQkBFhFhZG1pbkBleGFtcGxlLm9y
+ZzCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKtkktsya+B8p8x5/P7t
+IDIVcc0E6PPUklUmrcAzBuLNdnHH0FCbzqqsE+28L36gyriNv+l0EOvvnV3LJJdc
+RO/6Ee4NHjO/GKcmTCDOC1KSl7yP+IaPog/f86UJ1rTOQpnpCi/uB3Gd3ZocZ+s+
+5fnPCVFdAaRfLs8fVbJ3Lt79E/FiVhXXjG4/wFMGHg/6P3fsq5B+VqUww8xUjfZ9
+MUuo+MYP5CPYJHfhuIwNHsunGKsmjMtQ4nR84huTOKy9+YVsKr+GRzGy4aC3ElCb
+HTU+axLVcVPRgpsdCaFzXLAg5L//rufgWI7NKIV16t+6q/3euFWPHYW3lqdAWMD4
+yssCAwEAAaOCAdwwggHYMB0GA1UdDgQWBBT5kdLsBRD8WBlzoAmLWRMZf6PvOjCB
+0gYDVR0jBIHKMIHHgBRCXfgmfvHHnNNdyS6ziTT1JyZ9RqGBmKSBlTCBkjELMAkG
+A1UEBhMCRlIxDzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQw
+EgYDVQQKDAtFeGFtcGxlIEluYzEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBs
+ZS5vcmcxJjAkBgNVBAMMHUV4YW1wbGUgQ2VydGlmaWNhdGUgQXV0aG9yaXR5ghQ1
+f/ABa8HTFuVRSCGWyh5qvh/qSTAJBgNVHRMEAjAAMAsGA1UdDwQEAwIF4DAdBgNV
+HSUEFjAUBggrBgEFBQcDAQYIKwYBBQUHAw4wNgYDVR0fBC8wLTAroCmgJ4YlaHR0
+cDovL3d3dy5leGFtcGxlLmNvbS9leGFtcGxlX2NhLmNybDA3BggrBgEFBQcBAQQr
+MCkwJwYIKwYBBQUHMAGGG2h0dHA6Ly93d3cuZXhhbXBsZS5vcmcvb2NzcDA6BgNV
+HREEMzAxghJyYWRpdXMuZXhhbXBsZS5vcmegGwYIKwYBBQUHCAigDwwNKi5leGFt
+cGxlLmNvbTANBgkqhkiG9w0BAQsFAAOCAQEAX5O3aUlupNs8C0blKzGJosqKoEP1
+D0/RUESK6443TlK2hAImSE/qz9JGQ4tMSO1bfnYUS9Mnk4hStlG4gg6F/B4nV1eZ
+qbHEFWCyhCAlUUeDF+8Lz2G6wYXrw9pPe1GpQSFdHLTV2WKVK0IaRaote8bCQHBm
+bgNbfZVXK4JJKX0Wg+ECNQv8bGA/WwZ+QKOcjemaa1kxwi9PFRNOIOdFfk1zKXHz
+D6Ex0hFzl2dt+aSpmb93Fo4wDz1rtCJ7HGo1TtUbDdDwDoZv8SKsAI7XtDmrqqP/
+MZa+lI5xVXCsSBDppGZb6BVkl3AfUIIhbCDqj1MT9vXqjtaWsyG4F3iHuw==
+-----END CERTIFICATE-----
+Bag Attributes
+ localKeyID: 70 E4 1E 20 0B 8A 3E 65 06 98 99 29 C2 A4 26 33 38 D8 94 23
+Key Attributes: <No Attributes>
+-----BEGIN ENCRYPTED PRIVATE KEY-----
+MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQI0/IqoquZd2sCAggA
+MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBA3/HwadBWDheQI/8p1u6j+BIIE
+0N7R2UwLzLVPv/QR/hfYtK56iUtq0j5dqW/1Yos5IpkmUhOdXa149OGmzUkM6JQ/
+GaYQ5TbCn0+/HZx0k1nLIHL0fOUlorW/6i/pfw+KMR0bZrPUoZJyukG7iFIcD5yB
+Pq6Q/QXVIH0qzB2lTTEa6TNSzM4PtcGd24Ivt7GwX8vz/bbW+gPCnAEbFKTrn1aP
+Dr5LRIn9MOStPox/PmCEysdrdgJ8W9BD9J7iviUOmfJckl7hc10j87SvqHDYuPIP
+a5QZnGanbsdOfYRCtg6jkLPiR7f3kS+aeITGx1iKdm+wqpcp1JelYmg3b9a0mSGk
+fLgOS8z0hmdPrPT4yZtU1MvjxPpbVcpP+S5idWWD30bit2c7lqW3shXjan+voA4R
+gYbJewXiJbjFCElj/EnvX5dFaJyBdeRcaIZcKhEwsTGJ/GI6S7nFdDNao4dXUESX
+CWgVQNcdqiK/OJ8blQR6+1vxajJNLqx5GwbLJdMbN7d+o8m0O7O+lygF3BiDYpp0
+niLrB+qTM2H5jGRe2Vwhs5HxU1b0uN85xqUHRppeFmNB4mEcpT0XZ0a5kZZhuCQg
+P48ONl46i1DAAKOAQ+WSiSQUBO+AmMlzNquCNstkSrEis4szfDOT/RQmlMwLEyb9
+3aXZwsHzZREi7gojsyEHyadeKhsblBITSD79MmVpPBhym6sok8QWgk4R4+Xsckll
+cxqhsczmGv/tSz71/Soqql6KXmtk7YUAWDM1YtF1K2pb4zF9q0/mp3MgUB7sjcfm
+HMFDD3KSMFGfP9ex4MTUlEFXoBS0jM1rC+L0OtSDsBs23BOJvgi3JArZD2WPUPeR
+1dxcrtqYFy1DGkCMZ8+24GmqXbaL+iG/vgyAyhjcgWet2Xk8BHpuYPWSoGlnmJTP
+tqLC13jU0to8S8H7vsrbUP5m+XN/sVXkYE86AOsMO+/g+1fcqQOu0fSdSOvNvw5c
+/56yHA/+bJJfcQyqoEpPrpR2npazcG0cop3FOP9eTvNERRO6ayXJjrq1Tl9Ok39v
+DRQy/TLt6tQtHjiTFDgiZI+PI7FVzSudCGa2oMKTyf8qDWUN65825oSL7e7jggFM
+8VFf1MBXb1lCIFIrukNnXuXnYMWtQYjvHS/vN3jP/BGnVW+rEupj/hq4gtv1J2Pu
+B5Qn8Q+szCz8ha6ziA9+iVt57SRakK87bZ7qEIIy4XTJBnCGHTVjQOn+aMHJ/76H
+wiw8CPgKKQMwx0JyySMfZih+LgxlibPpk76zNIw0eYLM4DQEwmx9LGXZ4TIPCyAg
+GiWeKYn4zD0ub634DBFRTmX5XGQhqmKSkCIKOs4/8yzmX3649vess85RJN4DjjGN
+njzxuInblVxVg0YvzlGQHXwwCJuG48yoTa3UPvqft67kOoBLh8Kky1kMPPtPm8yR
+ZT8E8VdYSg2ssyCpyfaV3RCnxsMpnFUER+JU0g6IxTpDqxA4zK5XS6Wt/KsdnU+1
+locA7O1+lcsDXf2FyDFtwPwNZIjchV1UDXSYr/fKyn10TDoSMeRTZsC0vwm2/9bW
+peH+nk/x93j29VZVzGk6hlpLC9MBRq/qGhNqIwklxtfIKLr0l5oMcWwm4h4dAVBR
+HUC0MTfbSTrC8mAsOglVa87dF9v1gnA2FVlRZEHJCGwe
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/sensor/accel_polling/sample.yaml b/samples/sensor/accel_polling/sample.yaml
index 3dac247..a684fd9 100644
--- a/samples/sensor/accel_polling/sample.yaml
+++ b/samples/sensor/accel_polling/sample.yaml
@@ -17,6 +17,7 @@
- lpcxpresso55s28 # mma8652fc
- bbc_microbit # mmc8653fc
- frdm_k64f # fxos8700
+ - mimxrt1040_evk # fxls8974
- sparkfun_thing_plus/nrf9160 # lis2dh
- thingy52/nrf52832 # lis2dh12
- stm32f411e_disco # lsm303agr_accel
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.conf b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 5ab7306..0000000
--- a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_REQUIRES_FULL_LIBC=y
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.overlay b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index a122910..0000000
--- a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2023, Hiroki Tada
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Application overlay for creating temperature sensor device instance
- */
-
-&coretemp {
- status = "okay";
-};
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.conf b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 5ab7306..0000000
--- a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_REQUIRES_FULL_LIBC=y
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index a122910..0000000
--- a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2023, Hiroki Tada
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Application overlay for creating temperature sensor device instance
- */
-
-&coretemp {
- status = "okay";
-};
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_devkitm.conf b/samples/sensor/die_temp_polling/socs/esp32c3.conf
similarity index 100%
rename from samples/sensor/die_temp_polling/boards/esp32c3_devkitm.conf
rename to samples/sensor/die_temp_polling/socs/esp32c3.conf
diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_devkitm.overlay b/samples/sensor/die_temp_polling/socs/esp32c3.overlay
similarity index 100%
rename from samples/sensor/die_temp_polling/boards/esp32c3_devkitm.overlay
rename to samples/sensor/die_temp_polling/socs/esp32c3.overlay
diff --git a/samples/sensor/sensor_shell/boards/mimxrt1040_evk.conf b/samples/sensor/sensor_shell/boards/mimxrt1040_evk.conf
new file mode 100644
index 0000000..a0a62a7
--- /dev/null
+++ b/samples/sensor/sensor_shell/boards/mimxrt1040_evk.conf
@@ -0,0 +1,2 @@
+CONFIG_FXLS8974_TRIGGER_OWN_THREAD=n
+CONFIG_FXLS8974_TRIGGER_NONE=y
diff --git a/samples/shields/x_nucleo_iks01a3/standard/src/main.c b/samples/shields/x_nucleo_iks01a3/standard/src/main.c
index 023b7ea..fa3e378 100644
--- a/samples/shields/x_nucleo_iks01a3/standard/src/main.c
+++ b/samples/shields/x_nucleo_iks01a3/standard/src/main.c
@@ -341,8 +341,9 @@
stts751_config(stts751);
lis2dw12_config(lis2dw12);
lsm6dso_config(lsm6dso);
- if (lis2de12_on_dil24)
+ if (lis2de12_on_dil24) {
lis2de12_config(lis2de12);
+ }
while (1) {
/* Get sensor samples */
diff --git a/samples/subsys/debug/debugmon/src/main.c b/samples/subsys/debug/debugmon/src/main.c
index 8c0c8bc..c52a9be 100644
--- a/samples/subsys/debug/debugmon/src/main.c
+++ b/samples/subsys/debug/debugmon/src/main.c
@@ -51,8 +51,9 @@
printk("Entered debug monitor interrupt\n");
/* Spin in breakpoint. Other, higher-priority interrupts will continue to execute */
- while (true)
+ while (true) {
;
+ }
}
int main(void)
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.conf
index fdcda87..569f94a 100644
--- a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,2 +1 @@
CONFIG_SOC_NRF53_CPUNET_ENABLE=y
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.conf
deleted file mode 100644
index a1ab15f..0000000
--- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.conf
index fdcda87..569f94a 100644
--- a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,2 +1 @@
CONFIG_SOC_NRF53_CPUNET_ENABLE=y
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.conf
deleted file mode 100644
index a1ab15f..0000000
--- a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.conf
index fdcda87..569f94a 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,2 +1 @@
CONFIG_SOC_NRF53_CPUNET_ENABLE=y
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.conf
deleted file mode 100644
index a1ab15f..0000000
--- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_MBOX_NRFX_IPC=y
diff --git a/samples/subsys/llext/edk/README.rst b/samples/subsys/llext/edk/README.rst
index 22e678c..0926002 100644
--- a/samples/subsys/llext/edk/README.rst
+++ b/samples/subsys/llext/edk/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: llext-edk
:name: Linkable loadable extensions EDK
- :relevant-api: llext
+ :relevant-api: llext_apis
Enable linkable loadable extension development outside the Zephyr tree using
LLEXT EDK (Extension Development Kit).
diff --git a/samples/subsys/llext/modules/README.rst b/samples/subsys/llext/modules/README.rst
index a825d1c..8f3edec 100644
--- a/samples/subsys/llext/modules/README.rst
+++ b/samples/subsys/llext/modules/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: llext-modules
:name: Linkable loadable extensions "module" sample
- :relevant-api: llext
+ :relevant-api: llext_apis
Call a function in a loadable extension module,
either built-in or loaded at runtime.
diff --git a/samples/subsys/llext/shell_loader/README.rst b/samples/subsys/llext/shell_loader/README.rst
index 5062222..ec6d842 100644
--- a/samples/subsys/llext/shell_loader/README.rst
+++ b/samples/subsys/llext/shell_loader/README.rst
@@ -1,6 +1,6 @@
.. zephyr:code-sample:: llext-shell-loader
:name: Linkable loadable extensions shell module
- :relevant-api: llext
+ :relevant-api: llext_apis
Manage loadable extensions using shell commands.
diff --git a/samples/subsys/logging/multidomain/boards/nrf5340bsim_nrf5340_cpuapp.conf b/samples/subsys/logging/multidomain/boards/nrf5340bsim_nrf5340_cpuapp.conf
index f14ca9e..7dd3005 100644
--- a/samples/subsys/logging/multidomain/boards/nrf5340bsim_nrf5340_cpuapp.conf
+++ b/samples/subsys/logging/multidomain/boards/nrf5340bsim_nrf5340_cpuapp.conf
@@ -1,4 +1,3 @@
-CONFIG_MBOX_NRFX_IPC=y
# For the mailbox to be initialized logger initialization is delayed like in real HW
CONFIG_LOG_PROCESS_THREAD=y
CONFIG_LOG_MODE_DEFERRED=y
diff --git a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.conf
index 41ee9e5..c4bcfad 100644
--- a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,5 +1,4 @@
CONFIG_SOC_NRF53_CPUNET_ENABLE=y
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_LOG_BACKEND_UART_ASYNC=y
CONFIG_UART_ASYNC_API=y
CONFIG_UART_0_ASYNC=y
diff --git a/samples/subsys/logging/multidomain/remote/boards/nrf5340bsim_nrf5340_cpunet.conf b/samples/subsys/logging/multidomain/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
index 2d6de6e..58323e5 100644
--- a/samples/subsys/logging/multidomain/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
+++ b/samples/subsys/logging/multidomain/remote/boards/nrf5340bsim_nrf5340_cpunet.conf
@@ -1,4 +1,3 @@
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_BUILD_OUTPUT_EXE=n
# For the mailbox to be initialized logger initialization is delayed like in real HW
CONFIG_LOG_PROCESS_THREAD=y
diff --git a/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.conf
index cb04b37..b7b68aa 100644
--- a/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.conf
+++ b/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.conf
@@ -1,2 +1 @@
-CONFIG_MBOX_NRFX_IPC=y
CONFIG_MPU_STACK_GUARD=y
diff --git a/samples/subsys/nvs/boards/esp32c3_luatos_core.conf b/samples/subsys/nvs/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 26d5270..0000000
--- a/samples/subsys/nvs/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=256
diff --git a/samples/subsys/nvs/boards/esp32c3_luatos_core_esp32c3_usb.conf b/samples/subsys/nvs/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 26d5270..0000000
--- a/samples/subsys/nvs/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=256
diff --git a/samples/subsys/nvs/boards/esp32c3_devkitm.conf b/samples/subsys/nvs/socs/esp32c3.conf
similarity index 100%
rename from samples/subsys/nvs/boards/esp32c3_devkitm.conf
rename to samples/subsys/nvs/socs/esp32c3.conf
diff --git a/samples/subsys/profiling/perf/CMakeLists.txt b/samples/subsys/profiling/perf/CMakeLists.txt
new file mode 100644
index 0000000..f21d250
--- /dev/null
+++ b/samples/subsys/profiling/perf/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(perf)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/subsys/profiling/perf/README.rst b/samples/subsys/profiling/perf/README.rst
new file mode 100644
index 0000000..b5e0c10
--- /dev/null
+++ b/samples/subsys/profiling/perf/README.rst
@@ -0,0 +1,72 @@
+.. zephyr:code-sample:: profiling-perf
+ :name: Perf tool
+
+ Send perf samples to the host with console support
+
+This application can be used to understand how to use the :ref:`profiling-perf`
+tool.
+
+Requirements
+************
+
+The Perf tool is currently implemented only for RISC-V and x86_64 architectures.
+
+Usage example
+*************
+
+* Build and run the sample with:
+
+ .. zephyr-app-commands::
+ :zephyr-app: samples/subsys/profiling/perf
+ :board: qemu_riscv64
+ :goals: run
+ :compact:
+
+* After the sample has started, enter the shell command:
+
+ .. code-block:: console
+
+ uart:~$ perf record <duration> <frequency>
+
+ This command will start a timer for *duration* milliseconds at *frequency* Hz.
+
+* Wait for the completion message ``perf done!``, or ``perf buf override!`` if
+ the perf buffer size is smaller than required.
+
+* Print the samples captured by perf in the terminal with the shell command:
+
+ .. code-block:: console
+
+ uart:~$ perf printbuf
+
+ The output should be similar to:
+
+ .. code-block:: console
+
+ Perf buf length 2046
+ 0000000000000004
+ 00000000001056b2
+ 0000000000108192
+ 000000000010052f
+ 0000000000000000
+ ....
+ 000000000010052f
+ 0000000000000000
+
+* Copy the output into a file, for example :file:`perf_buf`.
+
+* Generate :file:`graph.svg` with
+ :zephyr_file:`scripts/profiling/stackcollapse.py` and `FlameGraph`_:
+
+ .. _FlameGraph: https://github.com/brendangregg/FlameGraph/
+
+ .. code-block:: shell
+
+ python scripts/perf/stackcollapse.py perf_buf build/zephyr/zephyr.elf | <flamegraph_dir_path>/flamegraph.pl > graph.svg
+
+Graph example
+=============
+
+.. image:: images/graph_example.svg
+ :align: center
+ :alt: graph example
diff --git a/samples/subsys/profiling/perf/images/graph_example.svg b/samples/subsys/profiling/perf/images/graph_example.svg
new file mode 100644
index 0000000..19c2e8d
--- /dev/null
+++ b/samples/subsys/profiling/perf/images/graph_example.svg
@@ -0,0 +1,521 @@
+<?xml version="1.0" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
+<svg version="1.1" width="1200" height="214" onload="init(evt)" viewBox="0 0 1200 214" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
+<!-- Flame graph stack visualization. See https://github.com/brendangregg/FlameGraph for latest version, and http://www.brendangregg.com/flamegraphs.html for examples. -->
+<!-- NOTES: -->
+<defs>
+ <linearGradient id="background" y1="0" y2="1" x1="0" x2="0" >
+ <stop stop-color="#eeeeee" offset="5%" />
+ <stop stop-color="#eeeeb0" offset="95%" />
+ </linearGradient>
+</defs>
+<style type="text/css">
+ text { font-family:Verdana; font-size:12px; fill:rgb(0,0,0); }
+ #search, #ignorecase { opacity:0.1; cursor:pointer; }
+ #search:hover, #search.show, #ignorecase:hover, #ignorecase.show { opacity:1; }
+ #subtitle { text-anchor:middle; font-color:rgb(160,160,160); }
+ #title { text-anchor:middle; font-size:17px}
+ #unzoom { cursor:pointer; }
+ #frames > *:hover { stroke:black; stroke-width:0.5; cursor:pointer; }
+ .hide { display:none; }
+ .parent { opacity:0.5; }
+</style>
+<script type="text/ecmascript">
+<![CDATA[
+ "use strict";
+ var details, searchbtn, unzoombtn, matchedtxt, svg, searching, currentSearchTerm, ignorecase, ignorecaseBtn;
+ function init(evt) {
+ details = document.getElementById("details").firstChild;
+ searchbtn = document.getElementById("search");
+ ignorecaseBtn = document.getElementById("ignorecase");
+ unzoombtn = document.getElementById("unzoom");
+ matchedtxt = document.getElementById("matched");
+ svg = document.getElementsByTagName("svg")[0];
+ searching = 0;
+ currentSearchTerm = null;
+
+ // use GET parameters to restore a flamegraphs state.
+ var params = get_params();
+ if (params.x && params.y)
+ zoom(find_group(document.querySelector('[x="' + params.x + '"][y="' + params.y + '"]')));
+ if (params.s) search(params.s);
+ }
+
+ // event listeners
+ window.addEventListener("click", function(e) {
+ var target = find_group(e.target);
+ if (target) {
+ if (target.nodeName == "a") {
+ if (e.ctrlKey === false) return;
+ e.preventDefault();
+ }
+ if (target.classList.contains("parent")) unzoom(true);
+ zoom(target);
+ if (!document.querySelector('.parent')) {
+ // we have basically done a clearzoom so clear the url
+ var params = get_params();
+ if (params.x) delete params.x;
+ if (params.y) delete params.y;
+ history.replaceState(null, null, parse_params(params));
+ unzoombtn.classList.add("hide");
+ return;
+ }
+
+ // set parameters for zoom state
+ var el = target.querySelector("rect");
+ if (el && el.attributes && el.attributes.y && el.attributes._orig_x) {
+ var params = get_params()
+ params.x = el.attributes._orig_x.value;
+ params.y = el.attributes.y.value;
+ history.replaceState(null, null, parse_params(params));
+ }
+ }
+ else if (e.target.id == "unzoom") clearzoom();
+ else if (e.target.id == "search") search_prompt();
+ else if (e.target.id == "ignorecase") toggle_ignorecase();
+ }, false)
+
+ // mouse-over for info
+ // show
+ window.addEventListener("mouseover", function(e) {
+ var target = find_group(e.target);
+ if (target) details.nodeValue = "Function: " + g_to_text(target);
+ }, false)
+
+ // clear
+ window.addEventListener("mouseout", function(e) {
+ var target = find_group(e.target);
+ if (target) details.nodeValue = ' ';
+ }, false)
+
+ // ctrl-F for search
+ // ctrl-I to toggle case-sensitive search
+ window.addEventListener("keydown",function (e) {
+ if (e.keyCode === 114 || (e.ctrlKey && e.keyCode === 70)) {
+ e.preventDefault();
+ search_prompt();
+ }
+ else if (e.ctrlKey && e.keyCode === 73) {
+ e.preventDefault();
+ toggle_ignorecase();
+ }
+ }, false)
+
+ // functions
+ function get_params() {
+ var params = {};
+ var paramsarr = window.location.search.substr(1).split('&');
+ for (var i = 0; i < paramsarr.length; ++i) {
+ var tmp = paramsarr[i].split("=");
+ if (!tmp[0] || !tmp[1]) continue;
+ params[tmp[0]] = decodeURIComponent(tmp[1]);
+ }
+ return params;
+ }
+ function parse_params(params) {
+ var uri = "?";
+ for (var key in params) {
+ uri += key + '=' + encodeURIComponent(params[key]) + '&';
+ }
+ if (uri.slice(-1) == "&")
+ uri = uri.substring(0, uri.length - 1);
+ if (uri == '?')
+ uri = window.location.href.split('?')[0];
+ return uri;
+ }
+ function find_child(node, selector) {
+ var children = node.querySelectorAll(selector);
+ if (children.length) return children[0];
+ }
+ function find_group(node) {
+ var parent = node.parentElement;
+ if (!parent) return;
+ if (parent.id == "frames") return node;
+ return find_group(parent);
+ }
+ function orig_save(e, attr, val) {
+ if (e.attributes["_orig_" + attr] != undefined) return;
+ if (e.attributes[attr] == undefined) return;
+ if (val == undefined) val = e.attributes[attr].value;
+ e.setAttribute("_orig_" + attr, val);
+ }
+ function orig_load(e, attr) {
+ if (e.attributes["_orig_"+attr] == undefined) return;
+ e.attributes[attr].value = e.attributes["_orig_" + attr].value;
+ e.removeAttribute("_orig_"+attr);
+ }
+ function g_to_text(e) {
+ var text = find_child(e, "title").firstChild.nodeValue;
+ return (text)
+ }
+ function g_to_func(e) {
+ var func = g_to_text(e);
+ // if there's any manipulation we want to do to the function
+ // name before it's searched, do it here before returning.
+ return (func);
+ }
+ function update_text(e) {
+ var r = find_child(e, "rect");
+ var t = find_child(e, "text");
+ var w = parseFloat(r.attributes.width.value) -3;
+ var txt = find_child(e, "title").textContent.replace(/\([^(]*\)$/,"");
+ t.attributes.x.value = parseFloat(r.attributes.x.value) + 3;
+
+ // Smaller than this size won't fit anything
+ if (w < 2 * 12 * 0.59) {
+ t.textContent = "";
+ return;
+ }
+
+ t.textContent = txt;
+ var sl = t.getSubStringLength(0, txt.length);
+ // check if only whitespace or if we can fit the entire string into width w
+ if (/^ *$/.test(txt) || sl < w)
+ return;
+
+ // this isn't perfect, but gives a good starting point
+ // and avoids calling getSubStringLength too often
+ var start = Math.floor((w/sl) * txt.length);
+ for (var x = start; x > 0; x = x-2) {
+ if (t.getSubStringLength(0, x + 2) <= w) {
+ t.textContent = txt.substring(0, x) + "..";
+ return;
+ }
+ }
+ t.textContent = "";
+ }
+
+ // zoom
+ function zoom_reset(e) {
+ if (e.attributes != undefined) {
+ orig_load(e, "x");
+ orig_load(e, "width");
+ }
+ if (e.childNodes == undefined) return;
+ for (var i = 0, c = e.childNodes; i < c.length; i++) {
+ zoom_reset(c[i]);
+ }
+ }
+ function zoom_child(e, x, ratio) {
+ if (e.attributes != undefined) {
+ if (e.attributes.x != undefined) {
+ orig_save(e, "x");
+ e.attributes.x.value = (parseFloat(e.attributes.x.value) - x - 10) * ratio + 10;
+ if (e.tagName == "text")
+ e.attributes.x.value = find_child(e.parentNode, "rect[x]").attributes.x.value + 3;
+ }
+ if (e.attributes.width != undefined) {
+ orig_save(e, "width");
+ e.attributes.width.value = parseFloat(e.attributes.width.value) * ratio;
+ }
+ }
+
+ if (e.childNodes == undefined) return;
+ for (var i = 0, c = e.childNodes; i < c.length; i++) {
+ zoom_child(c[i], x - 10, ratio);
+ }
+ }
+ function zoom_parent(e) {
+ if (e.attributes) {
+ if (e.attributes.x != undefined) {
+ orig_save(e, "x");
+ e.attributes.x.value = 10;
+ }
+ if (e.attributes.width != undefined) {
+ orig_save(e, "width");
+ e.attributes.width.value = parseInt(svg.width.baseVal.value) - (10 * 2);
+ }
+ }
+ if (e.childNodes == undefined) return;
+ for (var i = 0, c = e.childNodes; i < c.length; i++) {
+ zoom_parent(c[i]);
+ }
+ }
+ function zoom(node) {
+ var attr = find_child(node, "rect").attributes;
+ var width = parseFloat(attr.width.value);
+ var xmin = parseFloat(attr.x.value);
+ var xmax = parseFloat(xmin + width);
+ var ymin = parseFloat(attr.y.value);
+ var ratio = (svg.width.baseVal.value - 2 * 10) / width;
+
+ // XXX: Workaround for JavaScript float issues (fix me)
+ var fudge = 0.0001;
+
+ unzoombtn.classList.remove("hide");
+
+ var el = document.getElementById("frames").children;
+ for (var i = 0; i < el.length; i++) {
+ var e = el[i];
+ var a = find_child(e, "rect").attributes;
+ var ex = parseFloat(a.x.value);
+ var ew = parseFloat(a.width.value);
+ var upstack;
+ // Is it an ancestor
+ if (0 == 0) {
+ upstack = parseFloat(a.y.value) > ymin;
+ } else {
+ upstack = parseFloat(a.y.value) < ymin;
+ }
+ if (upstack) {
+ // Direct ancestor
+ if (ex <= xmin && (ex+ew+fudge) >= xmax) {
+ e.classList.add("parent");
+ zoom_parent(e);
+ update_text(e);
+ }
+ // not in current path
+ else
+ e.classList.add("hide");
+ }
+ // Children maybe
+ else {
+ // no common path
+ if (ex < xmin || ex + fudge >= xmax) {
+ e.classList.add("hide");
+ }
+ else {
+ zoom_child(e, xmin, ratio);
+ update_text(e);
+ }
+ }
+ }
+ search();
+ }
+ function unzoom(dont_update_text) {
+ unzoombtn.classList.add("hide");
+ var el = document.getElementById("frames").children;
+ for(var i = 0; i < el.length; i++) {
+ el[i].classList.remove("parent");
+ el[i].classList.remove("hide");
+ zoom_reset(el[i]);
+ if(!dont_update_text) update_text(el[i]);
+ }
+ search();
+ }
+ function clearzoom() {
+ unzoom();
+
+ // remove zoom state
+ var params = get_params();
+ if (params.x) delete params.x;
+ if (params.y) delete params.y;
+ history.replaceState(null, null, parse_params(params));
+ }
+
+ // search
+ function toggle_ignorecase() {
+ ignorecase = !ignorecase;
+ if (ignorecase) {
+ ignorecaseBtn.classList.add("show");
+ } else {
+ ignorecaseBtn.classList.remove("show");
+ }
+ reset_search();
+ search();
+ }
+ function reset_search() {
+ var el = document.querySelectorAll("#frames rect");
+ for (var i = 0; i < el.length; i++) {
+ orig_load(el[i], "fill")
+ }
+ var params = get_params();
+ delete params.s;
+ history.replaceState(null, null, parse_params(params));
+ }
+ function search_prompt() {
+ if (!searching) {
+ var term = prompt("Enter a search term (regexp " +
+ "allowed, eg: ^ext4_)"
+ + (ignorecase ? ", ignoring case" : "")
+ + "\nPress Ctrl-i to toggle case sensitivity", "");
+ if (term != null) search(term);
+ } else {
+ reset_search();
+ searching = 0;
+ currentSearchTerm = null;
+ searchbtn.classList.remove("show");
+ searchbtn.firstChild.nodeValue = "Search"
+ matchedtxt.classList.add("hide");
+ matchedtxt.firstChild.nodeValue = ""
+ }
+ }
+ function search(term) {
+ if (term) currentSearchTerm = term;
+
+ var re = new RegExp(currentSearchTerm, ignorecase ? 'i' : '');
+ var el = document.getElementById("frames").children;
+ var matches = new Object();
+ var maxwidth = 0;
+ for (var i = 0; i < el.length; i++) {
+ var e = el[i];
+ var func = g_to_func(e);
+ var rect = find_child(e, "rect");
+ if (func == null || rect == null)
+ continue;
+
+ // Save max width. Only works as we have a root frame
+ var w = parseFloat(rect.attributes.width.value);
+ if (w > maxwidth)
+ maxwidth = w;
+
+ if (func.match(re)) {
+ // highlight
+ var x = parseFloat(rect.attributes.x.value);
+ orig_save(rect, "fill");
+ rect.attributes.fill.value = "rgb(230,0,230)";
+
+ // remember matches
+ if (matches[x] == undefined) {
+ matches[x] = w;
+ } else {
+ if (w > matches[x]) {
+ // overwrite with parent
+ matches[x] = w;
+ }
+ }
+ searching = 1;
+ }
+ }
+ if (!searching)
+ return;
+ var params = get_params();
+ params.s = currentSearchTerm;
+ history.replaceState(null, null, parse_params(params));
+
+ searchbtn.classList.add("show");
+ searchbtn.firstChild.nodeValue = "Reset Search";
+
+ // calculate percent matched, excluding vertical overlap
+ var count = 0;
+ var lastx = -1;
+ var lastw = 0;
+ var keys = Array();
+ for (k in matches) {
+ if (matches.hasOwnProperty(k))
+ keys.push(k);
+ }
+ // sort the matched frames by their x location
+ // ascending, then width descending
+ keys.sort(function(a, b){
+ return a - b;
+ });
+ // Step through frames saving only the biggest bottom-up frames
+ // thanks to the sort order. This relies on the tree property
+ // where children are always smaller than their parents.
+ var fudge = 0.0001; // JavaScript floating point
+ for (var k in keys) {
+ var x = parseFloat(keys[k]);
+ var w = matches[keys[k]];
+ if (x >= lastx + lastw - fudge) {
+ count += w;
+ lastx = x;
+ lastw = w;
+ }
+ }
+ // display matched percent
+ matchedtxt.classList.remove("hide");
+ var pct = 100 * count / maxwidth;
+ if (pct != 100) pct = pct.toFixed(1)
+ matchedtxt.firstChild.nodeValue = "Matched: " + pct + "%";
+ }
+]]>
+</script>
+<rect x="0.0" y="0" width="1200.0" height="214.0" fill="url(#background)" />
+<text id="title" x="600.00" y="24" >Flame Graph</text>
+<text id="details" x="10.00" y="197" > </text>
+<text id="unzoom" x="10.00" y="24" class="hide">Reset Zoom</text>
+<text id="search" x="1090.00" y="24" >Search</text>
+<text id="ignorecase" x="1174.00" y="24" >ic</text>
+<text id="matched" x="1090.00" y="197" > </text>
+<g id="frames">
+<g >
+<title>z_impl_k_busy_wait (60 samples, 23.26%)</title><rect x="375.9" y="69" width="274.4" height="15.0" fill="rgb(239,158,37)" rx="2" ry="2" />
+<text x="378.89" y="79.5" >z_impl_k_busy_wait</text>
+</g>
+<g >
+<title>sys_clock_cycle_get_32 (40 samples, 15.50%)</title><rect x="467.4" y="53" width="182.9" height="15.0" fill="rgb(225,96,23)" rx="2" ry="2" />
+<text x="470.36" y="63.5" >sys_clock_cycle_get_32</text>
+</g>
+<g >
+<title>all (258 samples, 100%)</title><rect x="10.0" y="165" width="1180.0" height="15.0" fill="rgb(213,39,9)" rx="2" ry="2" />
+<text x="13.00" y="175.5" ></text>
+</g>
+<g >
+<title>sys_clock_cycle_get_32 (20 samples, 7.75%)</title><rect x="284.4" y="53" width="91.5" height="15.0" fill="rgb(225,96,23)" rx="2" ry="2" />
+<text x="287.42" y="63.5" >sys_clock_..</text>
+</g>
+<g >
+<title>sys_clock_cycle_get_32 (20 samples, 7.75%)</title><rect x="10.0" y="37" width="91.5" height="15.0" fill="rgb(225,96,23)" rx="2" ry="2" />
+<text x="13.00" y="47.5" >sys_clock_..</text>
+</g>
+<g >
+<title>z_impl_k_busy_wait (78 samples, 30.23%)</title><rect x="650.3" y="69" width="356.8" height="15.0" fill="rgb(239,158,37)" rx="2" ry="2" />
+<text x="653.31" y="79.5" >z_impl_k_busy_wait</text>
+</g>
+<g >
+<title>sys_clock_cycle_get_32 (40 samples, 15.50%)</title><rect x="101.5" y="37" width="182.9" height="15.0" fill="rgb(225,96,23)" rx="2" ry="2" />
+<text x="104.47" y="47.5" >sys_clock_cycle_get_32</text>
+</g>
+<g >
+<title>z_impl_k_busy_wait (20 samples, 7.75%)</title><rect x="284.4" y="69" width="91.5" height="15.0" fill="rgb(239,158,37)" rx="2" ry="2" />
+<text x="287.42" y="79.5" >z_impl_k_b..</text>
+</g>
+<g >
+<title>func_0 (80 samples, 31.01%)</title><rect x="10.0" y="85" width="365.9" height="15.0" fill="rgb(224,91,21)" rx="2" ry="2" />
+<text x="13.00" y="95.5" >func_0</text>
+</g>
+<g >
+<title>sys_clock_cycle_get_32 (59 samples, 22.87%)</title><rect x="737.2" y="53" width="269.9" height="15.0" fill="rgb(225,96,23)" rx="2" ry="2" />
+<text x="740.21" y="63.5" >sys_clock_cycle_get_32</text>
+</g>
+<g >
+<title>z_impl_k_busy_wait (40 samples, 15.50%)</title><rect x="101.5" y="53" width="182.9" height="15.0" fill="rgb(239,158,37)" rx="2" ry="2" />
+<text x="104.47" y="63.5" >z_impl_k_busy_wait</text>
+</g>
+<g >
+<title>main (218 samples, 84.50%)</title><rect x="10.0" y="101" width="997.1" height="15.0" fill="rgb(243,179,42)" rx="2" ry="2" />
+<text x="13.00" y="111.5" >main</text>
+</g>
+<g >
+<title>func_0_1 (40 samples, 15.50%)</title><rect x="101.5" y="69" width="182.9" height="15.0" fill="rgb(244,182,43)" rx="2" ry="2" />
+<text x="104.47" y="79.5" >func_0_1</text>
+</g>
+<g >
+<title>idle (40 samples, 15.50%)</title><rect x="1007.1" y="117" width="182.9" height="15.0" fill="rgb(239,157,37)" rx="2" ry="2" />
+<text x="1010.05" y="127.5" >idle</text>
+</g>
+<g >
+<title>func_1 (60 samples, 23.26%)</title><rect x="375.9" y="85" width="274.4" height="15.0" fill="rgb(218,62,14)" rx="2" ry="2" />
+<text x="378.89" y="95.5" >func_1</text>
+</g>
+<g >
+<title>arch_cpu_idle (40 samples, 15.50%)</title><rect x="1007.1" y="101" width="182.9" height="15.0" fill="rgb(218,62,14)" rx="2" ry="2" />
+<text x="1010.05" y="111.5" >arch_cpu_idle</text>
+</g>
+<g >
+<title>z_thread_entry (258 samples, 100.00%)</title><rect x="10.0" y="133" width="1180.0" height="15.0" fill="rgb(234,137,32)" rx="2" ry="2" />
+<text x="13.00" y="143.5" >z_thread_entry</text>
+</g>
+<g >
+<title>bg_thread_main (218 samples, 84.50%)</title><rect x="10.0" y="117" width="997.1" height="15.0" fill="rgb(235,140,33)" rx="2" ry="2" />
+<text x="13.00" y="127.5" >bg_thread_main</text>
+</g>
+<g >
+<title>func_0_0 (20 samples, 7.75%)</title><rect x="10.0" y="69" width="91.5" height="15.0" fill="rgb(251,212,50)" rx="2" ry="2" />
+<text x="13.00" y="79.5" >func_0_0</text>
+</g>
+<g >
+<title>z_impl_k_busy_wait (20 samples, 7.75%)</title><rect x="10.0" y="53" width="91.5" height="15.0" fill="rgb(239,158,37)" rx="2" ry="2" />
+<text x="13.00" y="63.5" >z_impl_k_b..</text>
+</g>
+<g >
+<title>func_2 (78 samples, 30.23%)</title><rect x="650.3" y="85" width="356.8" height="15.0" fill="rgb(212,32,7)" rx="2" ry="2" />
+<text x="653.31" y="95.5" >func_2</text>
+</g>
+<g >
+<title>[unknown] (258 samples, 100.00%)</title><rect x="10.0" y="149" width="1180.0" height="15.0" fill="rgb(210,24,5)" rx="2" ry="2" />
+<text x="13.00" y="159.5" >[unknown]</text>
+</g>
+</g>
+</svg>
diff --git a/samples/subsys/profiling/perf/prj.conf b/samples/subsys/profiling/perf/prj.conf
new file mode 100644
index 0000000..e93083d
--- /dev/null
+++ b/samples/subsys/profiling/perf/prj.conf
@@ -0,0 +1,6 @@
+CONFIG_PROFILING=y
+CONFIG_PROFILING_PERF=y
+CONFIG_THREAD_STACK_INFO=y
+CONFIG_SMP=n
+CONFIG_SHELL=y
+CONFIG_FRAME_POINTER=y
diff --git a/samples/subsys/profiling/perf/pytest/test_perf.py b/samples/subsys/profiling/perf/pytest/test_perf.py
new file mode 100755
index 0000000..1bb4c6a
--- /dev/null
+++ b/samples/subsys/profiling/perf/pytest/test_perf.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import logging
+import re
+
+from twister_harness import Shell
+from twister_harness import DeviceAdapter
+
+logger = logging.getLogger(__name__)
+
+
+def test_shell_perf(dut: DeviceAdapter, shell: Shell):
+
+ shell.base_timeout=10
+
+ logger.info('send "perf record 200 99" command')
+ lines = shell.exec_command('perf record 200 99')
+ assert 'Enabled perf' in lines, 'expected response not found'
+ lines = dut.readlines_until(regex='.*Perf done!', print_output=True)
+ logger.info('response is valid')
+
+ logger.info('send "perf printbuf" command')
+ lines = shell.exec_command('perf printbuf')
+ lines = lines[1:-1]
+ match = re.match(r"Perf buf length (\d+)", lines[0])
+ assert match is not None, 'expected response not found'
+ length = int(match.group(1))
+ lines = lines[1:]
+ assert length != 0, '0 length'
+ assert length == len(lines), 'length dose not match with count of lines'
+
+ i = 0
+ while i < length:
+ i += int(lines[i], 16) + 1
+ assert i <= length, 'one of the samples is not true to size'
diff --git a/samples/subsys/profiling/perf/sample.yaml b/samples/subsys/profiling/perf/sample.yaml
new file mode 100644
index 0000000..261c2f9
--- /dev/null
+++ b/samples/subsys/profiling/perf/sample.yaml
@@ -0,0 +1,18 @@
+sample:
+ description: Sample, that can be used for testing profiling perf tool
+ name: perf sample
+
+tests:
+ sample.perf:
+ tags:
+ - perf
+ - profiling
+ extra_configs:
+ - CONFIG_PROFILING_PERF_BUFFER_SIZE=128
+ filter: CONFIG_RISCV or CONFIG_X86
+ integration_platforms:
+ - qemu_riscv64
+ - qemu_riscv32
+ - qemu_x86_64
+ - qemu_x86
+ harness: pytest
diff --git a/samples/subsys/profiling/perf/src/main.c b/samples/subsys/profiling/perf/src/main.c
new file mode 100644
index 0000000..7576e19
--- /dev/null
+++ b/samples/subsys/profiling/perf/src/main.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2023 KNS Group LLC (YADRO)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <stdio.h>
+
+#define WAIT_KOEF 10000
+
+#define NOINLINE __attribute__((noinline))
+
+int NOINLINE func_0_0(void)
+{
+ k_busy_wait(1*WAIT_KOEF);
+ return 0;
+}
+
+int NOINLINE func_0_1(void)
+{
+ k_busy_wait(2*WAIT_KOEF);
+ return 0;
+}
+
+int NOINLINE func_0(void)
+{
+ k_busy_wait(1*WAIT_KOEF);
+ func_0_0();
+ func_0_1();
+ return 0;
+}
+
+int NOINLINE func_1(void)
+{
+ k_busy_wait(3*WAIT_KOEF);
+ return 0;
+}
+
+int NOINLINE func_2(void)
+{
+ k_busy_wait(4*WAIT_KOEF);
+ return 0;
+}
+
+int main(void)
+{
+ while (1) {
+ k_usleep(1000);
+ func_0();
+ func_1();
+ func_2();
+ }
+ return 0;
+}
diff --git a/samples/subsys/profiling/profiling.rst b/samples/subsys/profiling/profiling.rst
new file mode 100644
index 0000000..a976551
--- /dev/null
+++ b/samples/subsys/profiling/profiling.rst
@@ -0,0 +1,10 @@
+.. _profiling-samples:
+
+Profiling subsystem samples
+###########################
+
+.. toctree::
+ :maxdepth: 1
+ :glob:
+
+ **/*
diff --git a/samples/subsys/settings/boards/esp32c3_luatos_core.conf b/samples/subsys/settings/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 498fb07..0000000
--- a/samples/subsys/settings/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=256
-CONFIG_NVS=y
-CONFIG_SETTINGS_NVS=y
-CONFIG_MPU_ALLOW_FLASH_WRITE=y
diff --git a/samples/subsys/settings/boards/esp32c3_luatos_core_esp32c3_usb.conf b/samples/subsys/settings/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 498fb07..0000000
--- a/samples/subsys/settings/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=256
-CONFIG_NVS=y
-CONFIG_SETTINGS_NVS=y
-CONFIG_MPU_ALLOW_FLASH_WRITE=y
diff --git a/samples/subsys/settings/boards/esp32c3_devkitm.conf b/samples/subsys/settings/socs/esp32c3.conf
similarity index 100%
rename from samples/subsys/settings/boards/esp32c3_devkitm.conf
rename to samples/subsys/settings/socs/esp32c3.conf
diff --git a/samples/subsys/usb/hid-keyboard/src/main.c b/samples/subsys/usb/hid-keyboard/src/main.c
index 7f423c8..14f360b 100644
--- a/samples/subsys/usb/hid-keyboard/src/main.c
+++ b/samples/subsys/usb/hid-keyboard/src/main.c
@@ -149,6 +149,10 @@
{
LOG_INF("USBD message: %s", usbd_msg_type_string(msg->type));
+ if (msg->type == USBD_MSG_CONFIGURATION) {
+ LOG_INF("\tConfiguration value %d", msg->status);
+ }
+
if (usbd_can_detect_vbus(usbd_ctx)) {
if (msg->type == USBD_MSG_VBUS_READY) {
if (usbd_enable(usbd_ctx)) {
diff --git a/samples/userspace/shared_mem/boards/frdm_mcxn236.overlay b/samples/userspace/shared_mem/boards/frdm_mcxn236.overlay
new file mode 100644
index 0000000..f1be3ed
--- /dev/null
+++ b/samples/userspace/shared_mem/boards/frdm_mcxn236.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&sramx {
+ status = "disabled";
+};
diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py
index d2024f8..ab124e6 100755
--- a/scripts/ci/check_compliance.py
+++ b/scripts/ci/check_compliance.py
@@ -11,6 +11,7 @@
import logging
import os
from pathlib import Path
+import platform
import re
import subprocess
import sys
@@ -19,6 +20,7 @@
import shlex
import shutil
import textwrap
+import unidiff
from yamllint import config, linter
@@ -219,6 +221,13 @@
r'^\s*#(\d+):\s*FILE:\s*(.+):(\d+):'
matches = re.findall(regex, output, re.MULTILINE)
+
+ # add a guard here for excessive number of errors, do not try and
+ # process each one of them and instead push this as one failure.
+ if len(matches) > 500:
+ self.failure(output)
+ return
+
for m in matches:
self.fmtd_failure(m[1].lower(), m[2], m[5], m[6], col=None,
desc=m[3])
@@ -262,6 +271,46 @@
for file in path.glob("**/board.yml"):
self.check_board_file(file, vendor_prefixes)
+
+class ClangFormatCheck(ComplianceTest):
+ """
+ Check if clang-format reports any issues
+ """
+ name = "ClangFormat"
+ doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details."
+ path_hint = "<git-top>"
+
+ def run(self):
+ exe = f"clang-format-diff.{'exe' if platform.system() == 'Windows' else 'py'}"
+
+ for file in get_files():
+ if Path(file).suffix not in ['.c', '.h']:
+ continue
+
+ diff = subprocess.Popen(('git', 'diff', '-U0', '--no-color', COMMIT_RANGE, '--', file),
+ stdout=subprocess.PIPE,
+ cwd=GIT_TOP)
+ try:
+ subprocess.run((exe, '-p1'),
+ check=True,
+ stdin=diff.stdout,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT,
+ cwd=GIT_TOP)
+
+ except subprocess.CalledProcessError as ex:
+ patchset = unidiff.PatchSet.from_string(ex.output, encoding="utf-8")
+ for patch in patchset:
+ for hunk in patch:
+ # Strip the before and after context
+ msg = "".join([str(l) for l in hunk[3:-3]])
+ # show the hunk at the last line
+ self.fmtd_failure("notice",
+ "You may want to run clang-format on this change",
+ file, line=hunk.source_start + hunk.source_length - 3,
+ desc=f'\r\n{msg}')
+
+
class DevicetreeBindingsCheck(ComplianceTest):
"""
Checks if we are introducing any unwanted properties in Devicetree Bindings.
@@ -802,7 +851,7 @@
undef_to_locs = collections.defaultdict(list)
# Warning: Needs to work with both --perl-regexp and the 're' module
- regex = r"\bCONFIG_[A-Z0-9_]+\b(?!\s*##|[$@{*])"
+ regex = r"\bCONFIG_[A-Z0-9_]+\b(?!\s*##|[$@{(.*])"
# Skip doc/releases and doc/security/vulnerabilities.rst, which often
# reference removed symbols
@@ -845,7 +894,7 @@
/* CONFIG_FOO_*_... */), then please use exactly that form (with the '*'). The
CI check knows not to flag it.
-More generally, a reference followed by $, @, {{, *, or ## will never be
+More generally, a reference followed by $, @, {{, (, ., *, or ## will never be
flagged.
{undef_desc}""")
diff --git a/scripts/ci/coverage/coverage_analysis.py b/scripts/ci/coverage/coverage_analysis.py
index 8238a51..7596907 100644
--- a/scripts/ci/coverage/coverage_analysis.py
+++ b/scripts/ci/coverage/coverage_analysis.py
@@ -52,7 +52,7 @@
for element in parser:
for testsuite in element:
for testcase in testsuite['testcases']:
- if testcase['status'] is None:
+ if testcase['status'] == 'None':
testcase_name = testcase['identifier']
component_name = testcase_name[:testcase_name.find('.')]
component = {
diff --git a/scripts/ci/guideline_check.py b/scripts/ci/guideline_check.py
index 57c878f..00e0b3c 100755
--- a/scripts/ci/guideline_check.py
+++ b/scripts/ci/guideline_check.py
@@ -11,11 +11,18 @@
if "ZEPHYR_BASE" not in os.environ:
exit("$ZEPHYR_BASE environment variable undefined.")
-coccinelle_scripts = ["/scripts/coccinelle/reserved_names.cocci",
+RESERVED_NAMES_SCRIPT = "/scripts/coccinelle/reserved_names.cocci"
+
+coccinelle_scripts = [RESERVED_NAMES_SCRIPT,
"/scripts/coccinelle/same_identifier.cocci",
#"/scripts/coccinelle/identifier_length.cocci",
]
+coccinelle_reserved_names_exclude_regex = [
+ r"lib/libc/.*",
+ r"lib/posix/.*",
+ r"include/zephyr/posix/.*",
+]
def parse_coccinelle(contents: str, violations: dict):
reg = re.compile("([a-zA-Z0-9_/]*\\.[ch]:[0-9]*)(:[0-9\\-]*: )(.*)")
@@ -69,7 +76,18 @@
continue
for script in coccinelle_scripts:
- script_path = os.getenv("ZEPHYR_BASE") + "/" + script
+
+ skip_reserved_names = False
+ if script == RESERVED_NAMES_SCRIPT:
+ for path in coccinelle_reserved_names_exclude_regex:
+ if re.match(path, f.path):
+ skip_reserved_names = True
+ break
+
+ if skip_reserved_names:
+ continue
+
+ script_path =zephyr_base + "/" + script
print(f"Running {script} on {f.path}")
try:
cocci = sh.coccicheck(
diff --git a/scripts/coccinelle/symbols.txt b/scripts/coccinelle/symbols.txt
index 02bd93e..e0c1424 100644
--- a/scripts/coccinelle/symbols.txt
+++ b/scripts/coccinelle/symbols.txt
@@ -31,6 +31,7 @@
div
erf
erfc
+errno
exit
exp
fabs
diff --git a/scripts/kconfig/hardenconfig.py b/scripts/kconfig/hardenconfig.py
index cf42074..3bad4d3 100755
--- a/scripts/kconfig/hardenconfig.py
+++ b/scripts/kconfig/hardenconfig.py
@@ -1,6 +1,6 @@
#!/usr/bin/env python3
-# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2019-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
import csv
@@ -53,6 +53,11 @@
current = None
options.append(Option(name=name, current=current,
recommended=recommended, symbol=symbol))
+ for node in kconf.node_iter():
+ for select in node.selects:
+ if kconf.syms["EXPERIMENTAL"] in select or kconf.syms["DEPRECATED"] in select:
+ options.append(Option(name=node.item.name, current=node.item.str_value, recommended='n', symbol=node.item))
+
return options
diff --git a/scripts/kconfig/hardened.csv b/scripts/kconfig/hardened.csv
index 84d24dd..d91029a 100644
--- a/scripts/kconfig/hardened.csv
+++ b/scripts/kconfig/hardened.csv
@@ -47,84 +47,6 @@
X86_MMU,y
ZTEST,n
-# Experimental options
-
-BT_A2DP,n,experimental
-BT_AUDIO,n,experimental
-BT_AVDTP,n,experimental
-BT_CLASSIC,n,experimental
-BT_CTLR_ADV_DATA_CHAIN,n,experimental
-BT_CTLR_DTM_HCI_DF_IQ_REPORT,n,experimental
-BT_CTLR_SET_HOST_FEATURE,n,experimental
-BT_DF,n,experimental
-BT_EAD,n,experimental
-BT_EATT,n,experimental
-BT_H5,n,experimental,
-BT_HFP_HF,n,experimental
-BT_IAS,n,experimental
-BT_IAS_CLIENT,n,experimental
-BT_ISO_BROADCASTER,n,experimental
-BT_ISO_PERIPHERAL,n,experimental
-BT_ISO_SYNC_RECEIVER,n,experimental
-BT_MESH_USES_MBEDTLS_PSA,n,experimental
-BT_MESH_V1d1,n,experimental
-BT_OTS,n,experimental
-BT_OTS_CLIENT,n,experimental
-BT_PASSKEY_KEYPRESS,n,experimental
-BT_PER_ADV_RSP,n,experimental
-BT_PER_ADV_SYNC_RSP,n,experimental
-BT_RFCOMM,n,experimental
-CAN_NET,n,experimental
-CRYPTO_MBEDTLS_SHIM,n,experimental
-CRYPTO_TINYCRYPT_SHIM,n,experimental
-DEMAND_PAGING,n,experimental
-ETH_E1000_PTP_CLOCK,n,experimental
-GPIO_ENABLE_DISABLE_INTERRUPT,n,experimental
-GPIO_GET_CONFIG,n,experimental
-GPIO_GET_DIRECTION,n,experimental
-HTTP_CLIENT,n,experimental
-HTTP_SERVER,n,experimental
-ICE40_FPGA,n,experimental
-ISOTP,n,experimental
-LOG_BACKEND_BLE,n,experimental
-LORA,n,experimental
-LORAWAN,n,experimental
-LWM2M_FIRMWARE_UPDATE_OBJ_SUPPORT_MULTIPLE,n,experimental
-LWM2M_GATEWAY_OBJ_SUPPORT,n,experimental
-MEMC,n,experimental
-MIPI_DSI,n,experimental
-MM_DRV,n,experimental
-MODEM_CONTEXT,n,experimental
-MQTT_SN_LIB,n,experimental
-NET_BUF_VARIABLE_DATA_SIZE,n,experimental
-NET_CONNECTION_MANAGER,n,experimental
-NET_GPTP,n,experimental
-NET_IPV4_AUTO,n,experimental
-NET_L2_IEEE802154_SECURITY,n,experimental
-NET_PROMISCUOUS_MODE,n,experimental
-NET_SOCKETS_CAN,n,experimental
-NET_SOCKETS_ENABLE_DTLS,n,experimental
-NET_SOCKETS_NET_MGMT,n,experimental
-NET_SOCKETS_SOCKOPT_TLS,n,experimental
-NET_TC_THREAD_PREEMPTIVE,n,experimental
-OPENTHREAD_MLE_LONG_ROUTES,n,experimental
-SHELL_TELNET_SUPPORT_COMMAND,n,experimental
-SPI_EXTENDED_MODES,n,experimental
-SPI_RTIO,n,experimental
-SPI_SLAVE,n,experimental
-STM32_LPTIM_TIMER,n,experimental
-TFTP_LIB,n,experimental
-THRIFT,n,experimental
-UART_EMUL,n,experimental
-UDC_DRIVER,n,experimental
-UHC_DRIVER,n,experimental
-USBD_CDC_ACM_CLASS,n,experimental
-USBD_MSC_CLASS,n,experimental
-USB_DEVICE_AUDIO,n,experimental
-USB_DEVICE_STACK_NEXT,n,experimental
-USB_HOST_STACK,n,experimental
-WEBSOCKET_CLIENT,n,experimental
-
# Debug options
ASSERT,n
diff --git a/scripts/profiling/stackcollapse.py b/scripts/profiling/stackcollapse.py
new file mode 100644
index 0000000..3808852
--- /dev/null
+++ b/scripts/profiling/stackcollapse.py
@@ -0,0 +1,65 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+# Copyright (c) 2020 Yonatan Goldschmidt <yon.goldschmidt@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+"""
+Stack compressor for FlameGraph
+
+This translate stack samples captured by perf subsystem into format
+used by flamegraph.pl. Translation uses .elf file to get function names
+from addresses
+
+Usage:
+ ./script/perf/stackcollapse.py <file with perf printbuf output> <ELF file>
+"""
+
+import re
+import sys
+import struct
+import binascii
+from functools import lru_cache
+from elftools.elf.elffile import ELFFile
+
+
+@lru_cache(maxsize=None)
+def addr_to_sym(addr, elf):
+ symtab = elf.get_section_by_name(".symtab")
+ for sym in symtab.iter_symbols():
+ if sym.entry.st_info.type == "STT_FUNC" and sym.entry.st_value <= addr < sym.entry.st_value + sym.entry.st_size:
+ return sym.name
+ if addr == 0:
+ return "nullptr"
+ return "[unknown]"
+
+
+def collapse(buf, elf):
+ while buf:
+ count, = struct.unpack_from(">Q", buf)
+ assert count > 0
+ addrs = struct.unpack_from(f">{count}Q", buf, 8)
+
+ func_trace = reversed(list(map(lambda a: addr_to_sym(a, elf), addrs)))
+ prev_func = next(func_trace)
+ line = prev_func
+ # merge dublicate functions
+ for func in func_trace:
+ if prev_func != func:
+ prev_func = func
+ line += ";" + func
+
+ print(line, 1)
+ buf = buf[8 + 8 * count:]
+
+
+if __name__ == "__main__":
+ elf = ELFFile(open(sys.argv[2], "rb"))
+ with open(sys.argv[1], "r") as f:
+ inp = f.read()
+
+ lines = inp.splitlines()
+ assert int(re.match(r"Perf buf length (\d+)", lines[0]).group(1)) == len(lines) - 1
+ buf = binascii.unhexlify("".join(lines[1:]))
+ collapse(buf, elf)
diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
index a058c2a..2289ffb 100644
--- a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
+++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
@@ -86,7 +86,7 @@
extra_args.append("--cmd-pre-init")
extra_args.append(f'adapter serial {board_id}')
elif runner == 'jlink':
- base_args.append(f'--tool-opt=-SelectEmuBySN {board_id}')
+ base_args.append(f'--dev-id {board_id}')
elif runner == 'stm32cubeprogrammer':
base_args.append(f'--tool-opt=sn={board_id}')
elif runner == 'linkserver':
diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py
index c4c15d4..ddafadc 100644
--- a/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py
+++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py
@@ -46,6 +46,15 @@
@pytest.fixture(scope=determine_scope)
+def unlaunched_dut(request: pytest.FixtureRequest, device_object: DeviceAdapter) -> Generator[DeviceAdapter, None, None]:
+ """Return device object - with logs connected, but not run"""
+ device_object.initialize_log_files(request.node.name)
+ try:
+ yield device_object
+ finally: # to make sure we close all running processes execution
+ device_object.close()
+
+@pytest.fixture(scope=determine_scope)
def dut(request: pytest.FixtureRequest, device_object: DeviceAdapter) -> Generator[DeviceAdapter, None, None]:
"""Return launched device - with run application."""
device_object.initialize_log_files(request.node.name)
diff --git a/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py b/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py
index 214a608..fc77d6e 100644
--- a/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py
+++ b/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py
@@ -99,7 +99,7 @@
assert isinstance(device.command, list)
assert device.command == [
'west', 'flash', '--skip-rebuild', '--build-dir', 'build', '--runner', 'jlink',
- '--tool-opt=-SelectEmuBySN p_id'
+ '--dev-id p_id'
]
diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py
index b9c036f..7219e67 100644
--- a/scripts/pylib/twister/twisterlib/environment.py
+++ b/scripts/pylib/twister/twisterlib/environment.py
@@ -5,17 +5,19 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: Apache-2.0
-import os
-import pkg_resources
-import sys
-from pathlib import Path
+import argparse
import json
import logging
-import subprocess
-import shutil
+import os
import re
-import argparse
+import shutil
+import subprocess
+import sys
from datetime import datetime, timezone
+from importlib import metadata
+from pathlib import Path
+from typing import Generator, List
+
from twisterlib.coverage import supported_coverage_formats
logger = logging.getLogger('twister')
@@ -40,13 +42,22 @@
# Note "normalization" is different from canonicalization, see os.path.
canonical_zephyr_base = os.path.realpath(ZEPHYR_BASE)
-installed_packages = [pkg.project_name for pkg in pkg_resources.working_set] # pylint: disable=not-an-iterable
+
+def _get_installed_packages() -> Generator[str, None, None]:
+ """Return list of installed python packages."""
+ for dist in metadata.distributions():
+ yield dist.metadata['Name']
+
+
+installed_packages: List[str] = list(_get_installed_packages())
PYTEST_PLUGIN_INSTALLED = 'pytest-twister-harness' in installed_packages
+
def norm_path(astring):
newstring = os.path.normpath(astring).replace(os.sep, '/')
return newstring
+
def add_parse_arguments(parser = None):
if parser is None:
parser = argparse.ArgumentParser(
@@ -223,7 +234,7 @@
parser.add_argument(
"--pytest-args", action="append",
help="""Pass additional arguments to the pytest subprocess. This parameter
- will override the pytest_args from the harness_config in YAML file.
+ will extend the pytest_args from the harness_config in YAML file.
""")
valgrind_asan_group.add_argument(
diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py
index 15f1a7c..dab77fc 100755
--- a/scripts/pylib/twister/twisterlib/handlers.py
+++ b/scripts/pylib/twister/twisterlib/handlers.py
@@ -460,33 +460,40 @@
def device_is_available(self, instance):
device = instance.platform.name
fixture = instance.testsuite.harness_config.get("fixture")
- dut_found = False
+ duts_found = []
for d in self.duts:
if fixture and fixture not in map(lambda f: f.split(sep=':')[0], d.fixtures):
continue
if d.platform != device or (d.serial is None and d.serial_pty is None):
continue
- dut_found = True
+ duts_found.append(d)
+
+ if not duts_found:
+ raise TwisterException(f"No device to serve as {device} platform.")
+
+ # Select an available DUT with less failures
+ for d in sorted(duts_found, key=lambda _dut: _dut.failures):
d.lock.acquire()
avail = False
if d.available:
d.available = 0
- d.counter += 1
+ d.counter_increment()
avail = True
+ logger.debug(f"Retain DUT:{d.platform}, Id:{d.id}, "
+ f"counter:{d.counter}, failures:{d.failures}")
d.lock.release()
if avail:
return d
- if not dut_found:
- raise TwisterException(f"No device to serve as {device} platform.")
-
return None
- def make_device_available(self, serial):
- for d in self.duts:
- if serial in [d.serial_pty, d.serial]:
- d.available = 1
+ def make_dut_available(self, dut):
+ if self.instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]:
+ dut.failures_increment()
+ logger.debug(f"Release DUT:{dut.platform}, Id:{dut.id}, "
+ f"counter:{dut.counter}, failures:{dut.failures}")
+ dut.available = 1
@staticmethod
def run_custom_script(script, timeout):
@@ -540,7 +547,8 @@
command_extra_args.append("--cmd-pre-init")
command_extra_args.append("adapter serial %s" % board_id)
elif runner == "jlink":
- command.append("--tool-opt=-SelectEmuBySN %s" % board_id)
+ command.append("--dev-id")
+ command.append(board_id)
elif runner == "linkserver":
# for linkserver
# --probe=#<number> select by probe index
@@ -586,7 +594,7 @@
logger.debug(f"Terminated serial-pty:'{ser_pty}'")
#
- def _create_serial_connection(self, serial_device, hardware_baud,
+ def _create_serial_connection(self, dut, serial_device, hardware_baud,
flash_timeout, serial_pty, ser_pty_process):
try:
ser = serial.Serial(
@@ -599,28 +607,34 @@
timeout=max(flash_timeout, self.get_test_timeout())
)
except serial.SerialException as e:
- self.instance.status = TwisterStatus.FAIL
- self.instance.reason = "Serial Device Error"
- logger.error("Serial device error: %s" % (str(e)))
-
- self.instance.add_missing_case_status(TwisterStatus.BLOCK, "Serial Device Error")
- if serial_pty and ser_pty_process:
- self._terminate_pty(serial_pty, ser_pty_process)
-
- if serial_pty:
- self.make_device_available(serial_pty)
- else:
- self.make_device_available(serial_device)
+ self._handle_serial_exception(e, dut, serial_pty, ser_pty_process)
raise
return ser
+
+ def _handle_serial_exception(self, exception, dut, serial_pty, ser_pty_process):
+ self.instance.status = TwisterStatus.FAIL
+ self.instance.reason = "Serial Device Error"
+ logger.error("Serial device error: %s" % (str(exception)))
+
+ self.instance.add_missing_case_status(TwisterStatus.BLOCK, "Serial Device Error")
+ if serial_pty and ser_pty_process:
+ self._terminate_pty(serial_pty, ser_pty_process)
+
+ self.make_dut_available(dut)
+
+
def get_hardware(self):
hardware = None
try:
hardware = self.device_is_available(self.instance)
+ in_waiting = 0
while not hardware:
time.sleep(1)
+ in_waiting += 1
+ if in_waiting%60 == 0:
+ logger.debug(f"Waiting for a DUT to run {self.instance.name}")
hardware = self.device_is_available(self.instance)
except TwisterException as error:
self.instance.status = TwisterStatus.FAIL
@@ -659,7 +673,7 @@
hardware = self.get_hardware()
if hardware:
self.instance.dut = hardware.id
- if not hardware:
+ else:
return
runner = hardware.runner or self.options.west_runner
@@ -688,6 +702,7 @@
try:
ser = self._create_serial_connection(
+ hardware,
serial_port,
hardware.baud,
flash_timeout,
@@ -748,7 +763,8 @@
logger.debug(f"Attach serial device {serial_device} @ {hardware.baud} baud")
ser.port = serial_device
ser.open()
- except serial.SerialException:
+ except serial.SerialException as e:
+ self._handle_serial_exception(e, hardware, serial_pty, ser_pty_process)
return
if not flash_error:
@@ -780,10 +796,7 @@
if post_script:
self.run_custom_script(post_script, 30)
- if serial_pty:
- self.make_device_available(serial_pty)
- else:
- self.make_device_available(serial_device)
+ self.make_dut_available(hardware)
class QEMUHandler(Handler):
diff --git a/scripts/pylib/twister/twisterlib/hardwaremap.py b/scripts/pylib/twister/twisterlib/hardwaremap.py
index c07e777..979366d 100644
--- a/scripts/pylib/twister/twisterlib/hardwaremap.py
+++ b/scripts/pylib/twister/twisterlib/hardwaremap.py
@@ -58,6 +58,7 @@
self.serial_pty = serial_pty
self._counter = Value("i", 0)
self._available = Value("i", 1)
+ self._failures = Value("i", 0)
self.connected = connected
self.pre_script = pre_script
self.id = id
@@ -96,9 +97,27 @@
with self._counter.get_lock():
self._counter.value = value
+ def counter_increment(self, value=1):
+ with self._counter.get_lock():
+ self._counter.value += value
+
+ @property
+ def failures(self):
+ with self._failures.get_lock():
+ return self._failures.value
+
+ @failures.setter
+ def failures(self, value):
+ with self._failures.get_lock():
+ self._failures.value = value
+
+ def failures_increment(self, value=1):
+ with self._failures.get_lock():
+ self._failures.value += value
+
def to_dict(self):
d = {}
- exclude = ['_available', '_counter', 'match']
+ exclude = ['_available', '_counter', '_failures', 'match']
v = vars(self)
for k in v.keys():
if k not in exclude and v[k]:
@@ -125,7 +144,8 @@
'Microchip Technology Inc.',
'FTDI',
'Digilent',
- 'Microsoft'
+ 'Microsoft',
+ 'Nuvoton'
]
runner_mapping = {
@@ -204,10 +224,10 @@
def summary(self, selected_platforms):
print("\nHardware distribution summary:\n")
table = []
- header = ['Board', 'ID', 'Counter']
+ header = ['Board', 'ID', 'Counter', 'Failures']
for d in self.duts:
if d.connected and d.platform in selected_platforms:
- row = [d.platform, d.id, d.counter]
+ row = [d.platform, d.id, d.counter, d.failures]
table.append(row)
print(tabulate(table, headers=header, tablefmt="github"))
diff --git a/scripts/pylib/twister/twisterlib/harness.py b/scripts/pylib/twister/twisterlib/harness.py
index 6f31ccb..3c23c44 100644
--- a/scripts/pylib/twister/twisterlib/harness.py
+++ b/scripts/pylib/twister/twisterlib/harness.py
@@ -16,6 +16,7 @@
import shutil
import json
+from pytest import ExitCode
from twisterlib.reports import ReportStatus
from twisterlib.error import ConfigurationError
from twisterlib.environment import ZEPHYR_BASE, PYTEST_PLUGIN_INSTALLED
@@ -353,7 +354,8 @@
self.source_dir = instance.testsuite.source_dir
self.report_file = os.path.join(self.running_dir, 'report.xml')
self.pytest_log_file_path = os.path.join(self.running_dir, 'twister_harness.log')
- self.reserved_serial = None
+ self.reserved_dut = None
+ self._output = []
def pytest_run(self, timeout):
try:
@@ -364,10 +366,10 @@
self.status = TwisterStatus.FAIL
self.instance.reason = str(pytest_exception)
finally:
- if self.reserved_serial:
- self.instance.handler.make_device_available(self.reserved_serial)
- self.instance.record(self.recording)
- self._update_test_status()
+ self.instance.record(self.recording)
+ self._update_test_status()
+ if self.reserved_dut:
+ self.instance.handler.make_dut_available(self.reserved_dut)
def generate_command(self):
config = self.instance.testsuite.harness_config
@@ -383,7 +385,8 @@
f'--junit-xml={self.report_file}',
'--log-file-level=DEBUG',
'--log-file-format=%(asctime)s.%(msecs)d:%(levelname)s:%(name)s: %(message)s',
- f'--log-file={self.pytest_log_file_path}'
+ f'--log-file={self.pytest_log_file_path}',
+ f'--platform={self.instance.platform.name}'
]
command.extend([os.path.normpath(os.path.join(
self.source_dir, os.path.expanduser(os.path.expandvars(src)))) for src in pytest_root])
@@ -418,12 +421,8 @@
if handler.options.pytest_args:
command.extend(handler.options.pytest_args)
- if pytest_args_yaml:
- logger.warning(f'The pytest_args ({handler.options.pytest_args}) specified '
- 'in the command line will override the pytest_args defined '
- f'in the YAML file {pytest_args_yaml}')
- else:
- command.extend(pytest_args_yaml)
+
+ command.extend(pytest_args_yaml)
return command
@@ -435,7 +434,7 @@
# update the instance with the device id to have it in the summary report
self.instance.dut = hardware.id
- self.reserved_serial = hardware.serial_pty or hardware.serial
+ self.reserved_dut = hardware
if hardware.serial_pty:
command.append(f'--device-serial-pty={hardware.serial_pty}')
else:
@@ -487,7 +486,7 @@
env=env
) as proc:
try:
- reader_t = threading.Thread(target=self._output_reader, args=(proc, self), daemon=True)
+ reader_t = threading.Thread(target=self._output_reader, args=(proc,), daemon=True)
reader_t.start()
reader_t.join(timeout)
if reader_t.is_alive():
@@ -501,6 +500,13 @@
self.status = TwisterStatus.FAIL
proc.kill()
+ if proc.returncode in (ExitCode.INTERRUPTED, ExitCode.USAGE_ERROR, ExitCode.INTERNAL_ERROR):
+ self.status = TwisterStatus.ERROR
+ self.instance.reason = f'Pytest error - return code {proc.returncode}'
+ with open(self.pytest_log_file_path, 'w') as log_file:
+ log_file.write(shlex.join(cmd) + '\n\n')
+ log_file.write('\n'.join(self._output))
+
@staticmethod
def _update_command_with_env_dependencies(cmd):
'''
@@ -523,14 +529,15 @@
return cmd, env
- @staticmethod
- def _output_reader(proc, harness):
+ def _output_reader(self, proc):
+ self._output = []
while proc.stdout.readable() and proc.poll() is None:
line = proc.stdout.readline().decode().strip()
if not line:
continue
+ self._output.append(line)
logger.debug('PYTEST: %s', line)
- harness.parse_record(line)
+ self.parse_record(line)
proc.communicate()
def _update_test_status(self):
@@ -589,11 +596,16 @@
class Gtest(Harness):
ANSI_ESCAPE = re.compile(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])')
- TEST_START_PATTERN = r".*\[ RUN \] (?P<suite_name>[a-zA-Z_][a-zA-Z0-9_]*)\.(?P<test_name>[a-zA-Z_][a-zA-Z0-9_]*)"
- TEST_PASS_PATTERN = r".*\[ OK \] (?P<suite_name>[a-zA-Z_][a-zA-Z0-9_]*)\.(?P<test_name>[a-zA-Z_][a-zA-Z0-9_]*)"
- TEST_SKIP_PATTERN = r".*\[ DISABLED \] (?P<suite_name>[a-zA-Z_][a-zA-Z0-9_]*)\.(?P<test_name>[a-zA-Z_][a-zA-Z0-9_]*)"
- TEST_FAIL_PATTERN = r".*\[ FAILED \] (?P<suite_name>[a-zA-Z_][a-zA-Z0-9_]*)\.(?P<test_name>[a-zA-Z_][a-zA-Z0-9_]*)"
- FINISHED_PATTERN = r".*\[==========\] Done running all tests\."
+ _NAME_PATTERN = "[a-zA-Z_][a-zA-Z0-9_]*"
+ _SUITE_TEST_NAME_PATTERN = f"(?P<suite_name>{_NAME_PATTERN})\\.(?P<test_name>{_NAME_PATTERN})"
+ TEST_START_PATTERN = f".*\\[ RUN \\] {_SUITE_TEST_NAME_PATTERN}"
+ TEST_PASS_PATTERN = f".*\\[ OK \\] {_SUITE_TEST_NAME_PATTERN}"
+ TEST_SKIP_PATTERN = f".*\\[ DISABLED \\] {_SUITE_TEST_NAME_PATTERN}"
+ TEST_FAIL_PATTERN = f".*\\[ FAILED \\] {_SUITE_TEST_NAME_PATTERN}"
+ FINISHED_PATTERN = (
+ ".*(?:\\[==========\\] Done running all tests\\.|"
+ + "\\[----------\\] Global test environment tear-down)"
+ )
def __init__(self):
super().__init__()
@@ -695,6 +707,7 @@
class Test(Harness):
+ __test__ = False # for pytest to skip this class when collects tests
RUN_PASSED = "PROJECT EXECUTION SUCCESSFUL"
RUN_FAILED = "PROJECT EXECUTION FAILED"
test_suite_start_pattern = r"Running TESTSUITE (?P<suite_name>.*)"
diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py
index a09fde9..780f05f 100644
--- a/scripts/pylib/twister/twisterlib/reports.py
+++ b/scripts/pylib/twister/twisterlib/reports.py
@@ -36,7 +36,7 @@
'deny_suite': ['footprint']
},
'footprint.json': {
- 'deny_status': ['filtered'],
+ 'deny_status': ['FILTER'],
'deny_suite': ['testcases', 'execution_time', 'recording', 'retries', 'runnable']
}
}
@@ -400,8 +400,7 @@
if instance.recording is not None:
suite['recording'] = instance.recording
- if (instance.status
- and instance.status not in [TwisterStatus.ERROR, TwisterStatus.FILTER]
+ if (instance.status not in [TwisterStatus.NONE, TwisterStatus.ERROR, TwisterStatus.FILTER]
and self.env.options.create_rom_ram_report
and self.env.options.footprint_report is not None):
# Init as empty data preparing for filtering properties.
diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py
index 05957a9..44862cd 100755
--- a/scripts/pylib/twister/twisterlib/testplan.py
+++ b/scripts/pylib/twister/twisterlib/testplan.py
@@ -77,7 +77,9 @@
levels = []
scenarios = []
+
class TestPlan:
+ __test__ = False # for pytest to skip this class when collects tests
config_re = re.compile('(CONFIG_[A-Za-z0-9_]+)[=]\"?([^\"]*)\"?$')
dt_re = re.compile('([A-Za-z0-9_]+)[=]\"?([^\"]*)\"?$')
diff --git a/scripts/requirements-base.txt b/scripts/requirements-base.txt
index a232e82..3938fa7 100644
--- a/scripts/requirements-base.txt
+++ b/scripts/requirements-base.txt
@@ -17,10 +17,12 @@
canopen
packaging
progress
+patool
psutil
pylink-square
pyserial
requests
+semver
# for ram/rom reports
anytree
diff --git a/scripts/requirements-compliance.txt b/scripts/requirements-compliance.txt
index 68469fc..62e51c8 100644
--- a/scripts/requirements-compliance.txt
+++ b/scripts/requirements-compliance.txt
@@ -1,9 +1,11 @@
# COMPLIANCE: required by the compliance scripts
# used by ci/check_compliance
+clang-format
python-magic
python-magic-bin; sys_platform == "win32"
lxml
junitparser>=2
pylint>=3
+unidiff
yamllint
diff --git a/scripts/requirements-extras.txt b/scripts/requirements-extras.txt
index a026343..795c378 100644
--- a/scripts/requirements-extras.txt
+++ b/scripts/requirements-extras.txt
@@ -9,9 +9,6 @@
# helper for developers
junit2html
-# helper for developers - code formatter
-clang-format>=15.0.0
-
# Script used to build firmware images for NXP LPC MCUs.
lpc_checksum
diff --git a/scripts/tests/twister/pytest_integration/test_harness_pytest.py b/scripts/tests/twister/pytest_integration/test_harness_pytest.py
index f7c78c1..e4382d5 100644
--- a/scripts/tests/twister/pytest_integration/test_harness_pytest.py
+++ b/scripts/tests/twister/pytest_integration/test_harness_pytest.py
@@ -74,7 +74,7 @@
def test_pytest_command_extra_args_in_options(testinstance: TestInstance):
pytest_harness = Pytest()
- pytest_args_from_yaml = '-k test_from_yaml'
+ pytest_args_from_yaml = '--extra-option'
pytest_args_from_cmd = ['-k', 'test_from_cmd']
testinstance.testsuite.harness_config['pytest_args'] = [pytest_args_from_yaml]
testinstance.handler.options.pytest_args = pytest_args_from_cmd
@@ -82,7 +82,7 @@
command = pytest_harness.generate_command()
assert pytest_args_from_cmd[0] in command
assert pytest_args_from_cmd[1] in command
- assert pytest_args_from_yaml not in command
+ assert pytest_args_from_yaml in command
@pytest.mark.parametrize(
diff --git a/scripts/tests/twister/test_handlers.py b/scripts/tests/twister/test_handlers.py
index b4901ab..4d5505a 100644
--- a/scripts/tests/twister/test_handlers.py
+++ b/scripts/tests/twister/test_handlers.py
@@ -33,7 +33,9 @@
QEMUHandler,
SimulationHandler
)
-
+from twisterlib.hardwaremap import (
+ DUT
+)
@pytest.fixture
def mocked_instance(tmp_path):
@@ -736,12 +738,16 @@
fixtures=[],
platform='dummy_platform',
available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
counter=0
),
mock.Mock(
fixtures=['dummy fixture'],
platform='another_platform',
available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
counter=0
),
mock.Mock(
@@ -750,6 +756,8 @@
serial_pty=None,
serial=None,
available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
counter=0
),
mock.Mock(
@@ -757,6 +765,17 @@
platform='dummy_platform',
serial_pty=mock.Mock(),
available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
+ counter=0
+ ),
+ mock.Mock(
+ fixtures=['dummy fixture'],
+ platform='dummy_platform',
+ serial_pty=mock.Mock(),
+ available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
counter=0
)
],
@@ -765,6 +784,57 @@
(
'dummy_platform',
'dummy fixture',
+ [
+ mock.Mock(
+ fixtures=[],
+ platform='dummy_platform',
+ available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
+ counter=0
+ ),
+ mock.Mock(
+ fixtures=['dummy fixture'],
+ platform='another_platform',
+ available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
+ counter=0
+ ),
+ mock.Mock(
+ fixtures=['dummy fixture'],
+ platform='dummy_platform',
+ serial_pty=None,
+ serial=None,
+ available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
+ counter=0
+ ),
+ mock.Mock(
+ fixtures=['dummy fixture'],
+ platform='dummy_platform',
+ serial_pty=mock.Mock(),
+ available=1,
+ failures=1,
+ counter_increment=mock.Mock(),
+ counter=0
+ ),
+ mock.Mock(
+ fixtures=['dummy fixture'],
+ platform='dummy_platform',
+ serial_pty=mock.Mock(),
+ available=1,
+ failures=0,
+ counter_increment=mock.Mock(),
+ counter=0
+ )
+ ],
+ 4
+ ),
+ (
+ 'dummy_platform',
+ 'dummy fixture',
[],
TwisterException
),
@@ -776,24 +846,32 @@
fixtures=['dummy fixture'],
platform='dummy_platform',
serial_pty=mock.Mock(),
+ counter_increment=mock.Mock(),
+ failures=0,
available=0
),
mock.Mock(
fixtures=['another fixture'],
platform='dummy_platform',
serial_pty=mock.Mock(),
+ counter_increment=mock.Mock(),
+ failures=0,
available=0
),
mock.Mock(
fixtures=['dummy fixture'],
platform='dummy_platform',
serial=mock.Mock(),
+ counter_increment=mock.Mock(),
+ failures=0,
available=0
),
mock.Mock(
fixtures=['another fixture'],
platform='dummy_platform',
serial=mock.Mock(),
+ counter_increment=mock.Mock(),
+ failures=0,
available=0
)
],
@@ -804,7 +882,9 @@
@pytest.mark.parametrize(
'platform_name, fixture, duts, expected',
TESTDATA_10,
- ids=['one good dut', 'exception - no duts', 'no available duts']
+ ids=['two good duts, select the first one',
+ 'two duts, the first was failed once, select the second not failed',
+ 'exception - no duts', 'no available duts']
)
def test_devicehandler_device_is_available(
mocked_instance,
@@ -824,7 +904,7 @@
assert device == duts[expected]
assert device.available == 0
- assert device.counter == 1
+ device.counter_increment.assert_called_once()
elif expected is None:
device = handler.device_is_available(mocked_instance)
@@ -836,7 +916,7 @@
assert False
-def test_devicehandler_make_device_available(mocked_instance):
+def test_devicehandler_make_dut_available(mocked_instance):
serial = mock.Mock(name='dummy_serial')
duts = [
mock.Mock(available=0, serial=serial, serial_pty=None),
@@ -851,7 +931,13 @@
handler = DeviceHandler(mocked_instance, 'build')
handler.duts = duts
- handler.make_device_available(serial)
+ handler.make_dut_available(duts[1])
+
+ assert len([None for d in handler.duts if d.available == 1]) == 1
+ assert handler.duts[0].available == 0
+ assert handler.duts[2].available == 0
+
+ handler.make_dut_available(duts[0])
assert len([None for d in handler.duts if d.available == 1]) == 2
assert handler.duts[2].available == 0
@@ -1031,7 +1117,7 @@
'jlink',
'product',
['west', 'flash', '--skip-rebuild', '-d', '$build_dir',
- '--runner', 'jlink', '--tool-opt=-SelectEmuBySN 12345', # 2x space
+ '--runner', 'jlink', '--dev-id', 12345,
'param1', 'param2']
),
(
@@ -1166,14 +1252,15 @@
return expected_result
handler = DeviceHandler(mocked_instance, 'build')
- handler.make_device_available = mock.Mock()
missing_mock = mock.Mock()
handler.instance.add_missing_case_status = missing_mock
- available_mock = mock.Mock()
- handler.make_device_available = available_mock
handler.options = mock.Mock(timeout_multiplier=1)
twisterlib.handlers.terminate_process = mock.Mock()
+ dut = DUT()
+ dut.available = 0
+ dut.failures = 0
+
hardware_baud = 14400
flash_timeout = 60
serial_mock = mock.Mock(side_effect=mock_serial)
@@ -1181,26 +1268,25 @@
with mock.patch('serial.Serial', serial_mock), \
pytest.raises(expected_exception) if expected_exception else \
nullcontext():
- result = handler._create_serial_connection(serial_device, hardware_baud,
+ result = handler._create_serial_connection(dut, serial_device, hardware_baud,
flash_timeout, serial_pty,
ser_pty_process)
if expected_result:
assert result is not None
+ assert dut.failures == 0
if expected_exception:
assert handler.instance.status == TwisterStatus.FAIL
assert handler.instance.reason == 'Serial Device Error'
-
+ assert dut.available == 1
+ assert dut.failures == 1
missing_mock.assert_called_once_with('blocked', 'Serial Device Error')
if terminate_ser_pty_process:
twisterlib.handlers.terminate_process.assert_called_once()
ser_pty_process.communicate.assert_called_once()
- if make_available:
- available_mock.assert_called_once_with(make_available)
-
TESTDATA_16 = [
('dummy1 dummy2', None, 'slave name'),
@@ -1355,7 +1441,7 @@
handler.terminate = mock.Mock(side_effect=mock_terminate)
handler._update_instance_info = mock.Mock()
handler._final_handle_actions = mock.Mock()
- handler.make_device_available = mock.Mock()
+ handler.make_dut_available = mock.Mock()
twisterlib.handlers.terminate_process = mock.Mock()
handler.instance.platform.name = 'IPName'
@@ -1393,9 +1479,7 @@
if expected_status:
assert handler.instance.status == expected_status
- handler.make_device_available.assert_called_once_with(
- 'Serial PTY' if use_pty else 'dummy serial device'
- )
+ handler.make_dut_available.assert_called_once_with(hardware)
TESTDATA_18 = [
diff --git a/scripts/tests/twister/test_hardwaremap.py b/scripts/tests/twister/test_hardwaremap.py
index 6544036..8bb0c27 100644
--- a/scripts/tests/twister/test_hardwaremap.py
+++ b/scripts/tests/twister/test_hardwaremap.py
@@ -213,10 +213,10 @@
expected = """
Hardware distribution summary:
-| Board | ID | Counter |
-|---------|------|-----------|
-| p1 | 1 | 0 |
-| p7 | 7 | 0 |
+| Board | ID | Counter | Failures |
+|---------|------|-----------|------------|
+| p1 | 1 | 0 | 0 |
+| p7 | 7 | 0 | 0 |
"""
out, err = capfd.readouterr()
diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py
index 5f9ee6a..c0a135f 100644
--- a/scripts/tests/twister/test_harness.py
+++ b/scripts/tests/twister/test_harness.py
@@ -13,8 +13,9 @@
import re
import logging as logger
-#ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
+# ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
from conftest import ZEPHYR_BASE
+
sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/twister"))
from twisterlib.harness import (
@@ -26,7 +27,7 @@
Pytest,
PytestHarnessException,
Robot,
- Test
+ Test,
)
from twisterlib.statuses import TwisterStatus
from twisterlib.testinstance import TestInstance
@@ -38,10 +39,19 @@
SAMPLE_GTEST_START = (
"[00:00:00.000,000] [0m<inf> label: [==========] Running all tests.[0m"
)
-SAMPLE_GTEST_FMT = "[00:00:00.000,000] [0m<inf> label: [{state}] {suite}.{test} (0ms)[0m"
+SAMPLE_GTEST_FMT = (
+ "[00:00:00.000,000] [0m<inf> label: [{state}] {suite}.{test} (0ms)[0m"
+)
+SAMPLE_GTEST_FMT_FAIL_WITH_PARAM = (
+ "[00:00:00.000,000] [0m<inf> label: "
+ + "[{state}] {suite}.{test}, where GetParam() = 8-byte object <0B-00 00-00 00-9A 80-F7> (0 ms total)[0m"
+)
SAMPLE_GTEST_END = (
"[00:00:00.000,000] [0m<inf> label: [==========] Done running all tests.[0m"
)
+SAMPLE_GTEST_END_VARIANT = (
+ "[00:00:00.000,000] [0m<inf> label: [----------] Global test environment tear-down[0m"
+)
def process_logs(harness, logs):
@@ -50,39 +60,86 @@
TEST_DATA_RECORDING = [
- ([''], "^START:(?P<foo>.*):END", [], None),
- (['START:bar:STOP'], "^START:(?P<foo>.*):END", [], None),
- (['START:bar:END'], "^START:(?P<foo>.*):END", [{'foo':'bar'}], None),
- (['START:bar:baz:END'], "^START:(?P<foo>.*):(?P<boo>.*):END", [{'foo':'bar', 'boo':'baz'}], None),
- (['START:bar:baz:END','START:may:jun:END'], "^START:(?P<foo>.*):(?P<boo>.*):END",
- [{'foo':'bar', 'boo':'baz'}, {'foo':'may', 'boo':'jun'}], None),
- (['START:bar:END'], "^START:(?P<foo>.*):END", [{'foo':'bar'}], []),
- (['START:bar:END'], "^START:(?P<foo>.*):END", [{'foo':'bar'}], ['boo']),
- (['START:bad_json:END'], "^START:(?P<foo>.*):END",
- [{'foo':{'ERROR':{'msg':'Expecting value: line 1 column 1 (char 0)', 'doc':'bad_json'}}}], ['foo']),
- (['START::END'], "^START:(?P<foo>.*):END", [{'foo':{}}], ['foo']),
- (['START: {"one":1, "two":2} :END'], "^START:(?P<foo>.*):END", [{'foo':{'one':1, 'two':2}}], ['foo']),
- (['START: {"one":1, "two":2} :STOP:oops:END'], "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
- [{'foo':{'one':1, 'two':2},'boo':'oops'}], ['foo']),
- (['START: {"one":1, "two":2} :STOP:{"oops":0}:END'], "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
- [{'foo':{'one':1, 'two':2},'boo':{'oops':0}}], ['foo','boo']),
- ]
+ ([""], "^START:(?P<foo>.*):END", [], None),
+ (["START:bar:STOP"], "^START:(?P<foo>.*):END", [], None),
+ (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], None),
+ (
+ ["START:bar:baz:END"],
+ "^START:(?P<foo>.*):(?P<boo>.*):END",
+ [{"foo": "bar", "boo": "baz"}],
+ None,
+ ),
+ (
+ ["START:bar:baz:END", "START:may:jun:END"],
+ "^START:(?P<foo>.*):(?P<boo>.*):END",
+ [{"foo": "bar", "boo": "baz"}, {"foo": "may", "boo": "jun"}],
+ None,
+ ),
+ (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], []),
+ (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], ["boo"]),
+ (
+ ["START:bad_json:END"],
+ "^START:(?P<foo>.*):END",
+ [
+ {
+ "foo": {
+ "ERROR": {
+ "msg": "Expecting value: line 1 column 1 (char 0)",
+ "doc": "bad_json",
+ }
+ }
+ }
+ ],
+ ["foo"],
+ ),
+ (["START::END"], "^START:(?P<foo>.*):END", [{"foo": {}}], ["foo"]),
+ (
+ ['START: {"one":1, "two":2} :END'],
+ "^START:(?P<foo>.*):END",
+ [{"foo": {"one": 1, "two": 2}}],
+ ["foo"],
+ ),
+ (
+ ['START: {"one":1, "two":2} :STOP:oops:END'],
+ "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
+ [{"foo": {"one": 1, "two": 2}, "boo": "oops"}],
+ ["foo"],
+ ),
+ (
+ ['START: {"one":1, "two":2} :STOP:{"oops":0}:END'],
+ "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
+ [{"foo": {"one": 1, "two": 2}, "boo": {"oops": 0}}],
+ ["foo", "boo"],
+ ),
+]
+
+
@pytest.mark.parametrize(
"lines, pattern, expected_records, as_json",
TEST_DATA_RECORDING,
- ids=["empty", "no match", "match 1 field", "match 2 fields", "match 2 records",
- "as_json empty", "as_json no such field", "error parsing json", "empty json value", "simple json",
- "plain field and json field", "two json fields"
- ]
+ ids=[
+ "empty",
+ "no match",
+ "match 1 field",
+ "match 2 fields",
+ "match 2 records",
+ "as_json empty",
+ "as_json no such field",
+ "error parsing json",
+ "empty json value",
+ "simple json",
+ "plain field and json field",
+ "two json fields",
+ ],
)
def test_harness_parse_record(lines, pattern, expected_records, as_json):
harness = Harness()
- harness.record = { 'regex': pattern }
+ harness.record = {"regex": pattern}
harness.record_pattern = re.compile(pattern)
harness.record_as_json = as_json
if as_json is not None:
- harness.record['as_json'] = as_json
+ harness.record["as_json"] = as_json
assert not harness.recording
@@ -92,32 +149,43 @@
assert harness.recording == expected_records
-TEST_DATA_1 = [('RunID: 12345', False, False, False, TwisterStatus.NONE, True),
- ('PROJECT EXECUTION SUCCESSFUL', False, False, False, TwisterStatus.PASS, False),
- ('PROJECT EXECUTION SUCCESSFUL', True, False, False, TwisterStatus.FAIL, False),
- ('PROJECT EXECUTION FAILED', False, False, False, TwisterStatus.FAIL, False),
- ('ZEPHYR FATAL ERROR', False, True, False, TwisterStatus.NONE, False),
- ('GCOV_COVERAGE_DUMP_START', None, None, True, TwisterStatus.NONE, False),
- ('GCOV_COVERAGE_DUMP_END', None, None, False, TwisterStatus.NONE, False),]
+TEST_DATA_1 = [
+ ("RunID: 12345", False, False, False, TwisterStatus.NONE, True),
+ ("PROJECT EXECUTION SUCCESSFUL", False, False, False, TwisterStatus.PASS, False),
+ ("PROJECT EXECUTION SUCCESSFUL", True, False, False, TwisterStatus.FAIL, False),
+ ("PROJECT EXECUTION FAILED", False, False, False, TwisterStatus.FAIL, False),
+ ("ZEPHYR FATAL ERROR", False, True, False, TwisterStatus.NONE, False),
+ ("GCOV_COVERAGE_DUMP_START", None, None, True, TwisterStatus.NONE, False),
+ ("GCOV_COVERAGE_DUMP_END", None, None, False, TwisterStatus.NONE, False),
+]
+
@pytest.mark.parametrize(
"line, fault, fail_on_fault, cap_cov, exp_stat, exp_id",
TEST_DATA_1,
- ids=["match id", "passed passed", "passed failed", "failed failed", "fail on fault", "GCOV START", "GCOV END"]
+ ids=[
+ "match id",
+ "passed passed",
+ "passed failed",
+ "failed failed",
+ "fail on fault",
+ "GCOV START",
+ "GCOV END",
+ ],
)
def test_harness_process_test(line, fault, fail_on_fault, cap_cov, exp_stat, exp_id):
- #Arrange
+ # Arrange
harness = Harness()
harness.run_id = 12345
harness.status = TwisterStatus.NONE
harness.fault = fault
harness.fail_on_fault = fail_on_fault
- mock.patch.object(Harness, 'parse_record', return_value=None)
+ mock.patch.object(Harness, "parse_record", return_value=None)
- #Act
+ # Act
harness.process_test(line)
- #Assert
+ # Assert
assert harness.matched_run_id == exp_id
assert harness.status == exp_stat
assert harness.capture_coverage == cap_cov
@@ -125,60 +193,64 @@
def test_robot_configure(tmp_path):
- #Arrange
+ # Arrange
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
instance.testsuite.harness_config = {
- 'robot_testsuite': '/path/to/robot/test',
- 'robot_option': 'test_option'
+ "robot_testsuite": "/path/to/robot/test",
+ "robot_option": "test_option",
}
robot_harness = Robot()
- #Act
+ # Act
robot_harness.configure(instance)
- #Assert
+ # Assert
assert robot_harness.instance == instance
- assert robot_harness.path == '/path/to/robot/test'
- assert robot_harness.option == 'test_option'
+ assert robot_harness.path == "/path/to/robot/test"
+ assert robot_harness.option == "test_option"
def test_robot_handle(tmp_path):
- #Arrange
+ # Arrange
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
handler = Robot()
handler.instance = instance
- handler.id = 'test_case_1'
+ handler.id = "test_case_1"
- line = 'Test case passed'
+ line = "Test case passed"
- #Act
+ # Act
handler.handle(line)
- tc = instance.get_case_or_create('test_case_1')
+ tc = instance.get_case_or_create("test_case_1")
- #Assert
+ # Assert
assert instance.status == TwisterStatus.PASS
assert tc.status == TwisterStatus.PASS
@@ -187,10 +259,10 @@
("", 0, TwisterStatus.PASS),
("Robot test failure: sourcedir for mock_platform", 1, TwisterStatus.FAIL),
]
+
+
@pytest.mark.parametrize(
- "exp_out, returncode, expected_status",
- TEST_DATA_2,
- ids=["passed", "failed"]
+ "exp_out, returncode, expected_status", TEST_DATA_2, ids=["passed", "failed"]
)
def test_robot_run_robot_test(tmp_path, caplog, exp_out, returncode, expected_status):
# Arrange
@@ -207,14 +279,16 @@
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [mock.Mock()])
+ mock_testsuite = mock.Mock(id="id", testcases=[mock.Mock()])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
instance.build_dir = "build_dir"
open_mock = mock.mock_open()
@@ -224,19 +298,19 @@
robot.option = option
robot.instance = instance
proc_mock = mock.Mock(
- returncode = returncode,
- communicate = mock.Mock(return_value=(b"output", None))
+ returncode=returncode, communicate=mock.Mock(return_value=(b"output", None))
)
- popen_mock = mock.Mock(return_value = mock.Mock(
- __enter__ = mock.Mock(return_value = proc_mock),
- __exit__ = mock.Mock()
- ))
+ popen_mock = mock.Mock(
+ return_value=mock.Mock(
+ __enter__=mock.Mock(return_value=proc_mock), __exit__=mock.Mock()
+ )
+ )
# Act
- with mock.patch("subprocess.Popen", popen_mock) as mock.mock_popen, \
- mock.patch("builtins.open", open_mock):
- robot.run_robot_test(command,handler)
-
+ with mock.patch("subprocess.Popen", popen_mock) as mock.mock_popen, mock.patch(
+ "builtins.open", open_mock
+ ):
+ robot.run_robot_test(command, handler)
# Assert
assert instance.status == expected_status
@@ -244,68 +318,92 @@
assert exp_out in caplog.text
-TEST_DATA_3 = [('one_line', None), ('multi_line', 2),]
+TEST_DATA_3 = [
+ ("one_line", None),
+ ("multi_line", 2),
+]
+
+
@pytest.mark.parametrize(
- "type, num_patterns",
- TEST_DATA_3,
- ids=["one line", "multi line"]
+ "type, num_patterns", TEST_DATA_3, ids=["one line", "multi line"]
)
def test_console_configure(tmp_path, type, num_patterns):
- #Arrange
+ # Arrange
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
instance.testsuite.harness_config = {
- 'type': type,
- 'regex': ['pattern1', 'pattern2']
+ "type": type,
+ "regex": ["pattern1", "pattern2"],
}
console = Console()
- #Act
+ # Act
console.configure(instance)
- #Assert
+ # Assert
if num_patterns == 2:
assert len(console.patterns) == num_patterns
- assert [pattern.pattern for pattern in console.patterns] == ['pattern1', 'pattern2']
+ assert [pattern.pattern for pattern in console.patterns] == [
+ "pattern1",
+ "pattern2",
+ ]
else:
- assert console.pattern.pattern == 'pattern1'
+ assert console.pattern.pattern == "pattern1"
-TEST_DATA_4 = [("one_line", True, TwisterStatus.PASS, "line", False, False),
- ("multi_line", True, TwisterStatus.PASS, "line", False, False),
- ("multi_line", False, TwisterStatus.PASS, "line", False, False),
- ("invalid_type", False, TwisterStatus.NONE, "line", False, False),
- ("invalid_type", False, TwisterStatus.NONE, "ERROR", True, False),
- ("invalid_type", False, TwisterStatus.NONE, "COVERAGE_START", False, True),
- ("invalid_type", False, TwisterStatus.NONE, "COVERAGE_END", False, False)]
+TEST_DATA_4 = [
+ ("one_line", True, TwisterStatus.PASS, "line", False, False),
+ ("multi_line", True, TwisterStatus.PASS, "line", False, False),
+ ("multi_line", False, TwisterStatus.PASS, "line", False, False),
+ ("invalid_type", False, TwisterStatus.NONE, "line", False, False),
+ ("invalid_type", False, TwisterStatus.NONE, "ERROR", True, False),
+ ("invalid_type", False, TwisterStatus.NONE, "COVERAGE_START", False, True),
+ ("invalid_type", False, TwisterStatus.NONE, "COVERAGE_END", False, False),
+]
+
+
@pytest.mark.parametrize(
"line_type, ordered_val, exp_state, line, exp_fault, exp_capture",
TEST_DATA_4,
- ids=["one line", "multi line ordered", "multi line not ordered", "logger error", "fail on fault", "GCOV START", "GCOV END"]
+ ids=[
+ "one line",
+ "multi line ordered",
+ "multi line not ordered",
+ "logger error",
+ "fail on fault",
+ "GCOV START",
+ "GCOV END",
+ ],
)
-def test_console_handle(tmp_path, line_type, ordered_val, exp_state, line, exp_fault, exp_capture):
+def test_console_handle(
+ tmp_path, line_type, ordered_val, exp_state, line, exp_fault, exp_capture
+):
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
console = Console()
console.instance = instance
@@ -324,7 +422,7 @@
console.regex = ["regex1", "regex2"]
console.id = "test_case_1"
- instance.get_case_or_create('test_case_1')
+ instance.get_case_or_create("test_case_1")
instance.testsuite.id = "test_suite_1"
console.next_pattern = 0
@@ -344,124 +442,128 @@
assert console.capture_coverage == exp_capture
-TEST_DATA_5 = [("serial_pty", 0), (None, 0),(None, 1)]
-@pytest.mark.parametrize(
- "pty_value, hardware_value",
- TEST_DATA_5,
- ids=["hardware pty", "hardware", "non hardware"]
-)
+TEST_DATA_5 = [("serial_pty", 0), (None, 0), (None, 1)]
+
+@pytest.mark.parametrize(
+ "pty_value, hardware_value",
+ TEST_DATA_5,
+ ids=["hardware pty", "hardware", "non hardware"],
+)
def test_pytest__generate_parameters_for_hardware(tmp_path, pty_value, hardware_value):
- #Arrange
+ # Arrange
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
handler = mock.Mock()
handler.instance = instance
hardware = mock.Mock()
hardware.serial_pty = pty_value
- hardware.serial = 'serial'
+ hardware.serial = "serial"
hardware.baud = 115200
hardware.runner = "runner"
hardware.runner_params = ["--runner-param1", "runner-param2"]
- hardware.fixtures = ['fixture1:option1', 'fixture2']
+ hardware.fixtures = ["fixture1:option1", "fixture2"]
options = handler.options
options.west_flash = "args"
- hardware.probe_id = '123'
- hardware.product = 'product'
- hardware.pre_script = 'pre_script'
- hardware.post_flash_script = 'post_flash_script'
- hardware.post_script = 'post_script'
+ hardware.probe_id = "123"
+ hardware.product = "product"
+ hardware.pre_script = "pre_script"
+ hardware.post_flash_script = "post_flash_script"
+ hardware.post_script = "post_script"
pytest_test = Pytest()
pytest_test.configure(instance)
- #Act
+ # Act
if hardware_value == 0:
handler.get_hardware.return_value = hardware
command = pytest_test._generate_parameters_for_hardware(handler)
else:
handler.get_hardware.return_value = None
- #Assert
+ # Assert
if hardware_value == 1:
with pytest.raises(PytestHarnessException) as exinfo:
pytest_test._generate_parameters_for_hardware(handler)
- assert str(exinfo.value) == 'Hardware is not available'
+ assert str(exinfo.value) == "Hardware is not available"
else:
- assert '--device-type=hardware' in command
+ assert "--device-type=hardware" in command
if pty_value == "serial_pty":
- assert '--device-serial-pty=serial_pty' in command
+ assert "--device-serial-pty=serial_pty" in command
else:
- assert '--device-serial=serial' in command
- assert '--device-serial-baud=115200' in command
- assert '--runner=runner' in command
- assert '--runner-params=--runner-param1' in command
- assert '--runner-params=runner-param2' in command
- assert '--west-flash-extra-args=args' in command
- assert '--device-id=123' in command
- assert '--device-product=product' in command
- assert '--pre-script=pre_script' in command
- assert '--post-flash-script=post_flash_script' in command
- assert '--post-script=post_script' in command
- assert '--twister-fixture=fixture1:option1' in command
- assert '--twister-fixture=fixture2' in command
+ assert "--device-serial=serial" in command
+ assert "--device-serial-baud=115200" in command
+ assert "--runner=runner" in command
+ assert "--runner-params=--runner-param1" in command
+ assert "--runner-params=runner-param2" in command
+ assert "--west-flash-extra-args=args" in command
+ assert "--device-id=123" in command
+ assert "--device-product=product" in command
+ assert "--pre-script=pre_script" in command
+ assert "--post-flash-script=post_flash_script" in command
+ assert "--post-script=post_script" in command
+ assert "--twister-fixture=fixture1:option1" in command
+ assert "--twister-fixture=fixture2" in command
def test__update_command_with_env_dependencies():
- cmd = ['cmd']
+ cmd = ["cmd"]
pytest_test = Pytest()
- mock.patch.object(Pytest, 'PYTEST_PLUGIN_INSTALLED', False)
+ mock.patch.object(Pytest, "PYTEST_PLUGIN_INSTALLED", False)
# Act
result_cmd, _ = pytest_test._update_command_with_env_dependencies(cmd)
# Assert
- assert result_cmd == ['cmd', '-p', 'twister_harness.plugin']
+ assert result_cmd == ["cmd", "-p", "twister_harness.plugin"]
def test_pytest_run(tmp_path, caplog):
# Arrange
timeout = 10
- cmd=['command']
- exp_out = 'Support for handler handler_type not implemented yet'
+ cmd = ["command"]
+ exp_out = "Support for handler handler_type not implemented yet"
harness = Pytest()
harness = mock.create_autospec(harness)
- mock.patch.object(Pytest, 'generate_command', return_value=cmd)
- mock.patch.object(Pytest, 'run_command')
+ mock.patch.object(Pytest, "generate_command", return_value=cmd)
+ mock.patch.object(Pytest, "run_command")
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [], source_dir = 'source_dir', harness_config = {})
+ mock_testsuite = mock.Mock(
+ id="id", testcases=[], source_dir="source_dir", harness_config={}
+ )
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- handler = mock.Mock(
- options = mock.Mock(verbose= 0),
- type_str = 'handler_type'
- )
+ handler = mock.Mock(options=mock.Mock(verbose=0), type_str="handler_type")
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
instance.handler = handler
test_obj = Pytest()
@@ -474,59 +576,107 @@
assert exp_out in caplog.text
-TEST_DATA_6 = [(None), ('Test')]
-@pytest.mark.parametrize(
- "name",
- TEST_DATA_6,
- ids=["no name", "provided name"]
-)
+TEST_DATA_6 = [(None), ("Test")]
+
+
+@pytest.mark.parametrize("name", TEST_DATA_6, ids=["no name", "provided name"])
def test_get_harness(name):
- #Arrange
+ # Arrange
harnessimporter = HarnessImporter()
harness_name = name
- #Act
+ # Act
harness_class = harnessimporter.get_harness(harness_name)
- #Assert
+ # Assert
assert isinstance(harness_class, Test)
-TEST_DATA_7 = [("", "Running TESTSUITE suite_name", ['suite_name'], TwisterStatus.NONE, True, TwisterStatus.NONE),
- ("", "START - test_testcase", [], TwisterStatus.STARTED, True, TwisterStatus.NONE),
- ("", "PASS - test_example in 0 seconds", [], TwisterStatus.PASS, True, TwisterStatus.NONE),
- ("", "SKIP - test_example in 0 seconds", [], TwisterStatus.SKIP, True, TwisterStatus.NONE),
- ("", "FAIL - test_example in 0 seconds", [], TwisterStatus.FAIL, True, TwisterStatus.NONE),
- ("not a ztest and no state for test_id", "START - test_testcase", [], TwisterStatus.PASS, False, TwisterStatus.PASS),
- ("not a ztest and no state for test_id", "START - test_testcase", [], TwisterStatus.FAIL, False, TwisterStatus.FAIL)]
+TEST_DATA_7 = [
+ (
+ "",
+ "Running TESTSUITE suite_name",
+ ["suite_name"],
+ TwisterStatus.NONE,
+ True,
+ TwisterStatus.NONE,
+ ),
+ ("", "START - test_testcase", [], TwisterStatus.STARTED, True, TwisterStatus.NONE),
+ (
+ "",
+ "PASS - test_example in 0 seconds",
+ [],
+ TwisterStatus.PASS,
+ True,
+ TwisterStatus.NONE,
+ ),
+ (
+ "",
+ "SKIP - test_example in 0 seconds",
+ [],
+ TwisterStatus.SKIP,
+ True,
+ TwisterStatus.NONE,
+ ),
+ (
+ "",
+ "FAIL - test_example in 0 seconds",
+ [],
+ TwisterStatus.FAIL,
+ True,
+ TwisterStatus.NONE,
+ ),
+ (
+ "not a ztest and no state for test_id",
+ "START - test_testcase",
+ [],
+ TwisterStatus.PASS,
+ False,
+ TwisterStatus.PASS,
+ ),
+ (
+ "not a ztest and no state for test_id",
+ "START - test_testcase",
+ [],
+ TwisterStatus.FAIL,
+ False,
+ TwisterStatus.FAIL,
+ ),
+]
+
+
@pytest.mark.parametrize(
- "exp_out, line, exp_suite_name, exp_status, ztest, state",
- TEST_DATA_7,
- ids=['testsuite', 'testcase', 'pass', 'skip', 'failed', 'ztest pass', 'ztest fail']
+ "exp_out, line, exp_suite_name, exp_status, ztest, state",
+ TEST_DATA_7,
+ ids=["testsuite", "testcase", "pass", "skip", "failed", "ztest pass", "ztest fail"],
)
-def test_test_handle(tmp_path, caplog, exp_out, line, exp_suite_name, exp_status, ztest, state):
+def test_test_handle(
+ tmp_path, caplog, exp_out, line, exp_suite_name, exp_status, ztest, state
+):
# Arrange
line = line
mock_platform = mock.Mock()
mock_platform.name = "mock_platform"
mock_platform.normalized_name = "mock_platform"
- mock_testsuite = mock.Mock(id = 'id', testcases = [])
+ mock_testsuite = mock.Mock(id="id", testcases=[])
mock_testsuite.name = "mock_testsuite"
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
test_obj = Test()
test_obj.configure(instance)
test_obj.id = "test_id"
test_obj.ztest = ztest
test_obj.status = state
- test_obj.id = 'test_id'
- #Act
+ test_obj.id = "test_id"
+ # Act
test_obj.handle(line)
# Assert
@@ -549,10 +699,12 @@
mock_testsuite.id = "id"
mock_testsuite.testcases = []
mock_testsuite.harness_config = {}
- outdir = tmp_path / 'gtest_out'
+ outdir = tmp_path / "gtest_out"
outdir.mkdir()
- instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir)
+ instance = TestInstance(
+ testsuite=mock_testsuite, platform=mock_platform, outdir=outdir
+ )
harness = Gtest()
harness.configure(instance)
@@ -580,7 +732,8 @@
assert gtest.detected_suite_names[0] == "suite_name"
assert gtest.instance.get_case_by_name("id.suite_name.test_name") is not None
assert (
- gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.STARTED
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.STARTED
)
@@ -600,8 +753,13 @@
assert gtest.status == TwisterStatus.NONE
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
- assert gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.PASS
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.PASS
+ )
def test_gtest_failed(gtest):
@@ -620,8 +778,13 @@
assert gtest.status == TwisterStatus.NONE
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
- assert gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.FAIL
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.FAIL
+ )
def test_gtest_skipped(gtest):
@@ -640,8 +803,13 @@
assert gtest.status == TwisterStatus.NONE
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
- assert gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.SKIP
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.SKIP
+ )
def test_gtest_all_pass(gtest):
@@ -661,8 +829,34 @@
assert gtest.status == TwisterStatus.PASS
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
- assert gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.PASS
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.PASS
+ )
+
+
+def test_gtest_all_pass_with_variant(gtest):
+ process_logs(
+ gtest,
+ [
+ SAMPLE_GTEST_START,
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_START_STATE, suite="suite_name", test="test_name"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_PASS_STATE, suite="suite_name", test="test_name"
+ ),
+ SAMPLE_GTEST_END_VARIANT,
+ ],
+ )
+ assert gtest.status == "passed"
+ assert len(gtest.detected_suite_names) == 1
+ assert gtest.detected_suite_names[0] == "suite_name"
+ assert gtest.instance.get_case_by_name("id.suite_name.test_name") is not None
+ assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == "passed"
def test_gtest_one_skipped(gtest):
@@ -688,10 +882,21 @@
assert gtest.status == TwisterStatus.PASS
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
- assert gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name").status == TwisterStatus.PASS
- assert gtest.instance.get_case_by_name("id.suite_name.test_name1") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test_name1").status == TwisterStatus.SKIP
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name") != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name").status
+ == TwisterStatus.PASS
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name1")
+ != TwisterStatus.NONE
+ )
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test_name1").status
+ == TwisterStatus.SKIP
+ )
def test_gtest_one_fail(gtest):
@@ -718,9 +923,73 @@
assert len(gtest.detected_suite_names) == 1
assert gtest.detected_suite_names[0] == "suite_name"
assert gtest.instance.get_case_by_name("id.suite_name.test0") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test0").status == TwisterStatus.PASS
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test0").status
+ == TwisterStatus.PASS
+ )
assert gtest.instance.get_case_by_name("id.suite_name.test1") != TwisterStatus.NONE
- assert gtest.instance.get_case_by_name("id.suite_name.test1").status == TwisterStatus.FAIL
+ assert (
+ gtest.instance.get_case_by_name("id.suite_name.test1").status
+ == TwisterStatus.FAIL
+ )
+
+
+def test_gtest_one_fail_with_variant(gtest):
+ process_logs(
+ gtest,
+ [
+ SAMPLE_GTEST_START,
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_START_STATE, suite="suite_name", test="test0"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_PASS_STATE, suite="suite_name", test="test0"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_START_STATE, suite="suite_name", test="test1"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_FAIL_STATE, suite="suite_name", test="test1"
+ ),
+ SAMPLE_GTEST_END_VARIANT,
+ ],
+ )
+ assert gtest.status == "failed"
+ assert len(gtest.detected_suite_names) == 1
+ assert gtest.detected_suite_names[0] == "suite_name"
+ assert gtest.instance.get_case_by_name("id.suite_name.test0") is not None
+ assert gtest.instance.get_case_by_name("id.suite_name.test0").status == "passed"
+ assert gtest.instance.get_case_by_name("id.suite_name.test1") is not None
+ assert gtest.instance.get_case_by_name("id.suite_name.test1").status == "failed"
+
+
+def test_gtest_one_fail_with_variant_and_param(gtest):
+ process_logs(
+ gtest,
+ [
+ SAMPLE_GTEST_START,
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_START_STATE, suite="suite_name", test="test0"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_PASS_STATE, suite="suite_name", test="test0"
+ ),
+ SAMPLE_GTEST_FMT.format(
+ state=GTEST_START_STATE, suite="suite_name", test="test1"
+ ),
+ SAMPLE_GTEST_FMT_FAIL_WITH_PARAM.format(
+ state=GTEST_FAIL_STATE, suite="suite_name", test="test1"
+ ),
+ SAMPLE_GTEST_END_VARIANT,
+ ],
+ )
+ assert gtest.status == "failed"
+ assert len(gtest.detected_suite_names) == 1
+ assert gtest.detected_suite_names[0] == "suite_name"
+ assert gtest.instance.get_case_by_name("id.suite_name.test0") is not None
+ assert gtest.instance.get_case_by_name("id.suite_name.test0").status == "passed"
+ assert gtest.instance.get_case_by_name("id.suite_name.test1") is not None
+ assert gtest.instance.get_case_by_name("id.suite_name.test1").status == "failed"
def test_gtest_missing_result(gtest):
@@ -810,26 +1079,26 @@
def test_bsim_build(monkeypatch, tmp_path):
mocked_instance = mock.Mock()
- build_dir = tmp_path / 'build_dir'
+ build_dir = tmp_path / "build_dir"
os.makedirs(build_dir)
mocked_instance.build_dir = str(build_dir)
- mocked_instance.name = 'platform_name/test/dummy.test'
+ mocked_instance.name = "platform_name/test/dummy.test"
mocked_instance.testsuite.harness_config = {}
harness = Bsim()
harness.instance = mocked_instance
- monkeypatch.setenv('BSIM_OUT_PATH', str(tmp_path))
- os.makedirs(os.path.join(tmp_path, 'bin'), exist_ok=True)
- zephyr_exe_path = os.path.join(build_dir, 'zephyr', 'zephyr.exe')
+ monkeypatch.setenv("BSIM_OUT_PATH", str(tmp_path))
+ os.makedirs(os.path.join(tmp_path, "bin"), exist_ok=True)
+ zephyr_exe_path = os.path.join(build_dir, "zephyr", "zephyr.exe")
os.makedirs(os.path.dirname(zephyr_exe_path), exist_ok=True)
- with open(zephyr_exe_path, 'w') as file:
- file.write('TEST_EXE')
+ with open(zephyr_exe_path, "w") as file:
+ file.write("TEST_EXE")
harness.build()
- new_exe_path = os.path.join(tmp_path, 'bin', 'bs_platform_name_test_dummy_test')
+ new_exe_path = os.path.join(tmp_path, "bin", "bs_platform_name_test_dummy_test")
assert os.path.exists(new_exe_path)
- with open(new_exe_path, 'r') as file:
+ with open(new_exe_path, "r") as file:
exe_content = file.read()
- assert 'TEST_EXE' in exe_content
+ assert "TEST_EXE" in exe_content
diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_fail/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/always_fail/dummy/test_data.yaml
index af7ba6f..db29b1a 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/always_fail/dummy/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/always_fail/dummy/test_data.yaml
@@ -1,8 +1,8 @@
tests:
always_fail.dummy:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_timeout/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/always_timeout/dummy/test_data.yaml
index 3c758a3..eea858f 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/always_timeout/dummy/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/always_timeout/dummy/test_data.yaml
@@ -3,8 +3,8 @@
tests:
always_timeout.dummy:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml
index ae60a90..a2fa9f6 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml
@@ -3,8 +3,8 @@
tests:
always_warning.dummy:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup1/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup1/test_data.yaml
index 035c275..a85e834 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup1/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup1/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_one_pass.agnostic.group1.subgroup1:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup2/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup2/test_data.yaml
index a07e7e2..43bb824 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup2/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_one_pass/agnostic/group1/subgroup2/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_one_pass.agnostic.group1.subgroup2:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup1/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup1/test_data.yaml
index e42250e..45e7b39 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup1/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup1/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_two_error_one_pass.agnostic.group1.subgroup1:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup2/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup2/test_data.yaml
index b2813ad..d997ebc 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup2/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup2/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_two_error_one_pass.agnostic.group1.subgroup2:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup3/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup3/test_data.yaml
index c5c9486..25d9055 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup3/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup3/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_two_error_one_pass.agnostic.group1.subgroup3:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup4/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup4/test_data.yaml
index a4957e6..1acf5b5 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup4/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/one_fail_two_error_one_pass/agnostic/group1/subgroup4/test_data.yaml
@@ -1,11 +1,11 @@
tests:
one_fail_two_error_one_pass.agnostic.group1.subgroup4:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
tags:
- agnostic
- subgrouped
diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml
index 2a77394..70f8c2b 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml
+++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml
@@ -1,8 +1,8 @@
tests:
always_overflow.dummy:
platform_allow:
- - native_posix
+ - native_sim
- qemu_x86
- qemu_x86_64
integration_platforms:
- - native_posix
+ - native_sim
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c
deleted file mode 100644
index f2ee6dc18..0000000
--- a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2024 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/ztest.h>
-
-
-ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL);
-
-/**
- * @brief Test Asserts
- *
- * This test verifies various assert macros provided by ztest.
- *
- */
-ZTEST(a1_1_tests, test_assert)
-{
- zassert_true(0, "1 was false");
- zassert_false(1, "0 was true");
-}
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml
deleted file mode 100644
index a1d7518..0000000
--- a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml
+++ /dev/null
@@ -1,6 +0,0 @@
-tests:
- seed_native_posix.dummy:
- platform_allow:
- - native_posix
- integration_platforms:
- - native_posix
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/CMakeLists.txt
similarity index 100%
rename from scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt
rename to scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/CMakeLists.txt
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig
similarity index 100%
rename from scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig
rename to scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf
similarity index 100%
rename from scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf
rename to scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/src/main.c
new file mode 100644
index 0000000..f41c0f8
--- /dev/null
+++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/src/main.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL);
+
+/**
+ * @brief Test Asserts
+ *
+ * This test verifies various assert macros provided by ztest.
+ *
+ */
+ZTEST(a1_1_tests, test_assert)
+{
+ zassert_true(0, "1 was false");
+ zassert_false(1, "0 was true");
+}
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/test_data.yaml
new file mode 100644
index 0000000..4813260
--- /dev/null
+++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/test_data.yaml
@@ -0,0 +1,6 @@
+tests:
+ seed_native_sim.dummy:
+ platform_allow:
+ - native_sim
+ integration_platforms:
+ - native_sim
diff --git a/scripts/tests/twister_blackbox/test_device.py b/scripts/tests/twister_blackbox/test_device.py
index f84dd76..0ec9ae0 100644
--- a/scripts/tests/twister_blackbox/test_device.py
+++ b/scripts/tests/twister_blackbox/test_device.py
@@ -53,8 +53,8 @@
@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock)
def test_seed(self, capfd, out_path, seed):
- test_platforms = ['native_posix']
- path = os.path.join(TEST_DATA, 'tests', 'seed_native_posix')
+ test_platforms = ['native_sim']
+ path = os.path.join(TEST_DATA, 'tests', 'seed_native_sim')
args = ['--outdir', out_path, '-i', '-T', path, '-vv',] + \
['--seed', f'{seed[0]}'] + \
[val for pair in zip(
@@ -71,5 +71,5 @@
assert str(sys_exit.value) == '1'
- expected_line = r'seed_native_posix.dummy FAILED Failed \(native (\d+\.\d+)s/seed: {}\)'.format(seed[0])
+ expected_line = r'seed_native_sim.dummy FAILED Failed \(native (\d+\.\d+)s/seed: {}\)'.format(seed[0])
assert re.search(expected_line, err)
diff --git a/scripts/west-commands.yml b/scripts/west-commands.yml
index 24bbddb..6b7835e 100644
--- a/scripts/west-commands.yml
+++ b/scripts/west-commands.yml
@@ -76,3 +76,8 @@
- name: simulate
class: Simulate
help: simulate board
+ - file: scripts/west_commands/sdk.py
+ commands:
+ - name: sdk
+ class: Sdk
+ help: manage Zephyr SDK
diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash
index 3a528cd..d6e1f13 100644
--- a/scripts/west_commands/completion/west-completion.bash
+++ b/scripts/west_commands/completion/west-completion.bash
@@ -1142,6 +1142,53 @@
esac
}
+__comp_west_sdk()
+{
+ local bool_opts="
+ --interactive -i
+ --no-toolchains -T
+ --no-hosttools -H
+ "
+
+ local dir_opts="
+ --install-dir -d
+ --install-base -b
+ "
+
+ local other_opts="
+ --version
+ --toolchains -t
+ --personal-access-token
+ --api-url
+ "
+
+ all_opts="$bool_opts $dir_opts $other_opts"
+
+ case "$prev" in
+ sdk)
+ __set_comp "list install"
+ return
+ ;;
+ list)
+ return
+ ;;
+ $(__west_to_extglob "$dir_opts") )
+ __set_comp_dirs
+ return
+ ;;
+ # We don't know how to autocomplete those
+ $(__west_to_extglob "$other_opts") )
+ return
+ ;;
+ esac
+
+ case "$cur" in
+ -*)
+ __set_comp $all_opts
+ ;;
+ esac
+}
+
__comp_west()
{
local previous_extglob_setting=$(shopt -p extglob)
@@ -1176,6 +1223,7 @@
spdx
blobs
twister
+ sdk
)
local cmds=(${builtin_cmds[*]} ${zephyr_ext_cmds[*]})
diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish
index 817c5f7..cb3c49e 100644
--- a/scripts/west_commands/completion/west-completion.fish
+++ b/scripts/west_commands/completion/west-completion.fish
@@ -179,7 +179,8 @@
"attach" "interactively debug a board" \
"zephyr-export" "export Zephyr installation as a CMake config package" \
"spdx" "create SPDX bill of materials" \
- "blobs" "work with binary blobs"
+ "blobs" "work with binary blobs" \
+ "sdk" "manage SDKs"
set -l nb_ext_cmds (count $ext_cmds)
if __zephyr_west_check_if_in_workspace
@@ -501,3 +502,16 @@
complete -c west -n "__zephyr_west_seen_subcommand_from blobs; and not __fish_seen_subcommand_from list fetch clean" -ra "list\t'list binary blobs' fetch\t'fetch binary blobs' clean\t'clean working tree of binary blobs'"
complete -c west -n "__zephyr_west_seen_subcommand_from blobs; and __fish_seen_subcommand_from list fetch clean" -ra "(__zephyr_west_complete_projects)"
complete -c west -n "__zephyr_west_seen_subcommand_from blobs; and not __fish_seen_subcommand_from fetch clean" -o f -l format -r -d "format string"
+
+# sdk
+complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra sdk -d "manage SDKs"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and not __fish_seen_subcommand_from list install" -ra "list\t'list installed SDKs' install\t'install SDK'"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -l version -d "version of the Zephyr SDK to install"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o b -l install-base -d "SDK isntall base directory"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o d -l install-dir -d "SDK isntall destination directory"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o i -l interactive -d "interactive"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o t -l toolchains -d "toolchain(s) to install"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o T -l no-toolchains -d "do not install toolchains"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -o H -l no-hosttools -d "do not install host-tools"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -l personal-access-token -d "GitHub personal access token"
+complete -c west -n "__zephyr_west_seen_subcommand_from sdk; and __fish_seen_subcommand_from install" -l api-url -d "GitHub releases API endpoint URL"
diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh
index e1a0119..0ca7e82 100644
--- a/scripts/west_commands/completion/west-completion.zsh
+++ b/scripts/west_commands/completion/west-completion.zsh
@@ -34,6 +34,7 @@
'zephyr-export[export Zephyr installation as a CMake config package]'
'spdx[create SPDX bill of materials]'
'blobs[work with binary blobs]'
+ 'sdk[manage SDKs]'
)
local -a all_cmds=(${builtin_cmds} ${zephyr_ext_cmds})
diff --git a/scripts/west_commands/runners/jlink.py b/scripts/west_commands/runners/jlink.py
index 5670cd3..fd4022d 100644
--- a/scripts/west_commands/runners/jlink.py
+++ b/scripts/west_commands/runners/jlink.py
@@ -320,10 +320,12 @@
raise ValueError(err)
else:
- # use hex or bin file provided by the buildsystem, preferring .hex over .bin
+ # Use hex, bin or elf file provided by the buildsystem.
+ # Preferring .hex over .bin and .elf
if self.hex_name is not None and os.path.isfile(self.hex_name):
flash_file = self.hex_name
flash_cmd = f'loadfile "{self.hex_name}"'
+ # Preferring .bin over .elf
elif self.bin_name is not None and os.path.isfile(self.bin_name):
if self.dt_flash:
flash_addr = self.flash_address_from_build_conf(self.build_conf)
@@ -331,9 +333,12 @@
flash_addr = 0
flash_file = self.bin_name
flash_cmd = f'loadfile "{self.bin_name}" 0x{flash_addr:x}'
+ elif self.elf_name is not None and os.path.isfile(self.elf_name):
+ flash_file = self.elf_name
+ flash_cmd = f'loadfile "{self.elf_name}"'
else:
- err = 'Cannot flash; no hex ({}) or bin ({}) files found.'
- raise ValueError(err.format(self.hex_name, self.bin_name))
+ err = 'Cannot flash; no hex ({}), bin ({}) or elf ({}) files found.'
+ raise ValueError(err.format(self.hex_name, self.bin_name, self.elf_name))
# Flash the selected build artifact
lines.append(flash_cmd)
diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py
index fad78f8..35f1f53 100644
--- a/scripts/west_commands/runners/nrf_common.py
+++ b/scripts/west_commands/runners/nrf_common.py
@@ -70,7 +70,7 @@
def do_add_parser(cls, parser):
parser.add_argument('--nrf-family',
choices=['NRF51', 'NRF52', 'NRF53', 'NRF54L',
- 'NRF54H', 'NRF91'],
+ 'NRF54H', 'NRF91', 'NRF92'],
help='''MCU family; still accepted for
compatibility only''')
parser.add_argument('--softreset', required=False,
@@ -178,6 +178,8 @@
self.family = 'NRF54H_FAMILY'
elif self.build_conf.getboolean('CONFIG_SOC_SERIES_NRF91X'):
self.family = 'NRF91_FAMILY'
+ elif self.build_conf.getboolean('CONFIG_SOC_SERIES_NRF92X'):
+ self.family = 'NRF92_FAMILY'
else:
raise RuntimeError(f'unknown nRF; update {__file__}')
@@ -229,7 +231,7 @@
def recover_target(self):
- if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY'):
+ if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY', 'NRF92_FAMILY'):
self.logger.info(
'Recovering and erasing flash memory for both the network '
'and application cores.')
@@ -242,7 +244,7 @@
# keeps the debug access port open, recovering the network core last
# would result in that small image being deleted from the app core.
# In the case of the 54H, the order is indifferent.
- if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY'):
+ if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY', 'NRF92_FAMILY'):
self.exec_op('recover', core='NRFDL_DEVICE_CORE_NETWORK')
self.exec_op('recover')
@@ -254,9 +256,12 @@
# What type of erase/core arguments should we pass to the tool?
core = None
- if self.family == 'NRF54H_FAMILY':
+ if self.family in ('NRF54H_FAMILY', 'NRF92_FAMILY'):
erase_arg = 'ERASE_NONE'
+ cpuapp = self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP') or self.build_conf.getboolean('CONFIG_SOC_NRF9280_CPUAPP')
+ cpurad = self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD') or self.build_conf.getboolean('CONFIG_SOC_NRF9280_CPURAD')
+
if self.erase:
self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION')
self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK')
@@ -279,18 +284,18 @@
# Handle SUIT root manifest if application manifests are not used.
# If an application firmware is built, the root envelope is merged with other application manifests
# as well as the output HEX file.
- if not self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP') and self.sysbuild_conf.get('SB_CONFIG_SUIT_ENVELOPE'):
+ if not cpuapp and self.sysbuild_conf.get('SB_CONFIG_SUIT_ENVELOPE'):
app_root_envelope_hex_file = os.fspath(
mpi_hex_dir / 'suit_installed_envelopes_application_merged.hex')
self.op_program(app_root_envelope_hex_file, 'ERASE_NONE', None, defer=True, core='NRFDL_DEVICE_CORE_APPLICATION')
- if self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP'):
+ if cpuapp:
if not self.erase and self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR'):
self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION',
option={'chip_erase_mode': 'ERASE_UICR',
'qspi_erase_mode': 'ERASE_NONE'})
core = 'NRFDL_DEVICE_CORE_APPLICATION'
- elif self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD'):
+ elif cpurad:
if not self.erase and self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR'):
self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK',
option={'chip_erase_mode': 'ERASE_UICR',
diff --git a/scripts/west_commands/sdk.py b/scripts/west_commands/sdk.py
new file mode 100755
index 0000000..396edc9
--- /dev/null
+++ b/scripts/west_commands/sdk.py
@@ -0,0 +1,574 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import hashlib
+import os
+import patoolib
+import platform
+import re
+import requests
+import semver
+import shutil
+import subprocess
+import tempfile
+import textwrap
+import zcmake
+from pathlib import Path
+
+from west.commands import WestCommand
+
+
+class Sdk(WestCommand):
+ def __init__(self):
+ super().__init__(
+ "sdk",
+ "manage Zephyr SDK",
+ "List and Install Zephyr SDK",
+ )
+
+ def do_add_parser(self, parser_adder):
+ parser = parser_adder.add_parser(
+ self.name,
+ help=self.help,
+ description=self.description,
+ formatter_class=argparse.RawDescriptionHelpFormatter,
+ epilog=textwrap.dedent(
+ """
+ Listing SDKs:
+
+ Run 'west sdk' or 'west sdk list' to list installed SDKs.
+ See 'west sdk list --help' for details.
+
+
+ Installing SDK:
+
+ Run 'west sdk install' to install Zephyr SDK.
+ See 'west sdk install --help' for details.
+ """
+ ),
+ )
+
+ subparsers_gen = parser.add_subparsers(
+ metavar="<subcommand>",
+ dest="subcommand",
+ help="select a subcommand. If omitted, treat it as the 'list' selected.",
+ )
+
+ subparsers_gen.add_parser(
+ "list",
+ help="list installed Zephyr SDKs",
+ formatter_class=argparse.RawDescriptionHelpFormatter,
+ epilog=textwrap.dedent(
+ """
+ Listing SDKs:
+
+ Run 'west sdk' or 'west sdk list' command information about available SDKs is displayed.
+ """
+ ),
+ )
+
+ install_args_parser = subparsers_gen.add_parser(
+ "install",
+ help="install Zephyr SDK",
+ formatter_class=argparse.RawDescriptionHelpFormatter,
+ epilog=textwrap.dedent(
+ """
+ Installing SDK:
+
+ Run 'west sdk install' to install Zephyr SDK.
+
+ Set --version option to install a specific version of the SDK.
+ If not specified, the install version is detected from "${ZEPHYR_BASE}/SDK_VERSION file.
+ SDKs older than 0.14.1 are not supported.
+
+ You can specify the installation directory with --install-dir or --install-base.
+ If the specified version of the SDK is already installed,
+ the already installed SDK will be used regardless of the settings of
+ --install-dir and --install-base.
+
+ Typically, Zephyr SDK archives contain only one directory named zephyr-sdk-<version>
+ at the top level.
+ The SDK archive is extracted to the home directory if both --install-dir and --install-base
+ are not specified.
+ In this case, SDK will install into ${HOME}/zephyr-sdk-<version>.
+ If --install-base is specified, the archive will be extracted under the specified path.
+ In this case, SDK will install into <BASE>/zephyr-sdk-<version> .
+ If --install-dir is specified, the directory contained in the archive will be renamed
+ and placed to the specified location.
+
+ --interactive, --toolchains, --no-toolchains and --no-hosttools options
+ specify the behavior of the installer. Please see the description of each option.
+
+ --personal-access-token specifies the GitHub personal access token.
+ This helps to relax the limits on the number of REST API calls.
+
+ --api-url specifies the REST API endpoint for GitHub releases information
+ when installing the SDK from a different GitHub repository.
+ """
+ ),
+ )
+
+ install_args_parser.add_argument(
+ "--version",
+ default=None,
+ nargs="?",
+ metavar="SDK_VER",
+ help="version of the Zephyr SDK to install. "
+ "If not specified, the install version is detected from "
+ "${ZEPHYR_BASE}/SDK_VERSION file.",
+ )
+ install_args_parser.add_argument(
+ "-b",
+ "--install-base",
+ default=None,
+ metavar="BASE",
+ help="Base directory to SDK install. "
+ "The subdirectory created by extracting the archive in <BASE> will be the SDK installation directory. "
+ "For example, -b /foo/bar will install the SDK in `/foo/bar/zephyr-sdk-<version>'."
+ )
+ install_args_parser.add_argument(
+ "-d",
+ "--install-dir",
+ default=None,
+ metavar="DIR",
+ help="SDK install destination directory. "
+ "The SDK will be installed on the specified path. "
+ "The directory contained in the archive will be renamed and installed for the specified directory. "
+ "For example, if you specify -b /foo/bar/baz, The archive's zephyr-sdk-<version> directory will be renamed baz and placed under /foo/bar. "
+ "If this option is specified, the --install-base option is ignored. "
+ )
+ install_args_parser.add_argument(
+ "-i",
+ "--interactive",
+ action="store_true",
+ help="launches installer in interactive mode. "
+ "--toolchains, --no-toolchains and --no-hosttools will be ignored if this option is enabled.",
+ )
+ install_args_parser.add_argument(
+ "-t",
+ "--toolchains",
+ metavar="toolchain_name",
+ nargs="+",
+ help="toolchain(s) to install (e.g. 'arm-zephyr-eabi'). "
+ "If this option is not given, toolchains for all architectures will be installed.",
+ )
+ install_args_parser.add_argument(
+ "-T",
+ "--no-toolchains",
+ action="store_true",
+ help="do not install toolchains. "
+ "--toolchains will be ignored if this option is enabled.",
+ )
+ install_args_parser.add_argument(
+ "-H",
+ "--no-hosttools",
+ action="store_true",
+ help="do not install host-tools.",
+ )
+ install_args_parser.add_argument(
+ "--personal-access-token", help="GitHub personal access token."
+ )
+ install_args_parser.add_argument(
+ "--api-url",
+ default="https://api.github.com/repos/zephyrproject-rtos/sdk-ng/releases",
+ help="GitHub releases API endpoint used to look for Zephyr SDKs.",
+ )
+
+ return parser
+
+ def os_arch_name(self):
+ system = platform.system()
+ machine = platform.machine()
+
+ if system == "Linux":
+ osname = "linux"
+ elif system == "Darwin":
+ osname = "macos"
+ elif system == "Windows":
+ osname = "windows"
+ else:
+ self.die(f"Unsupported system: {system}")
+
+ if machine in ["aarch64", "arm64"]:
+ arch = "aarch64"
+ elif machine in ["x86_64", "AMD64"]:
+ arch = "x86_64"
+ else:
+ self.die(f"Unsupported machine: {machine}")
+
+ return (osname, arch)
+
+ def detect_version(self, args):
+ if args.version:
+ version = args.version
+ else:
+ if os.environ["ZEPHYR_BASE"]:
+ zephyr_base = Path(os.environ["ZEPHYR_BASE"])
+ else:
+ zephyr_base = Path(__file__).parents[2]
+
+ sdk_version_file = zephyr_base / "SDK_VERSION"
+
+ if not sdk_version_file.exists():
+ self.die(f"{str(sdk_version_file)} does not exist.")
+
+ with open(sdk_version_file) as f:
+ version = f.readlines()[0].strip()
+ self.inf(
+ f"Found '{str(sdk_version_file)}', installing version {version}."
+ )
+
+ try:
+ semver.Version.parse(version)
+ except Exception:
+ self.die(f"Invalid version format: {version}")
+
+ if semver.compare(version, "0.14.1") < 0:
+ self.die(f"Versions older than v0.14.1 are not supported.")
+
+ return version
+
+ def fetch_releases(self, url, req_headers):
+ """fetch releases data via GitHub REST API"""
+
+ releases = []
+ page = 1
+
+ while True:
+ params = {"page": page, "per_page": 100}
+ resp = requests.get(url, headers=req_headers, params=params)
+ if resp.status_code != 200:
+ raise Exception(f"Failed to fetch: {resp.status_code}, {resp.text}")
+
+ data = resp.json()
+ if not data:
+ break
+
+ releases.extend(data)
+ page += 1
+
+ return releases
+
+ def minimal_sdk_filename(self, release):
+ (osname, arch) = self.os_arch_name()
+ version = re.sub(r"^v", "", release["tag_name"])
+
+ if semver.compare(version, "0.16.0") < 0:
+ if osname == "windows":
+ ext = ".zip"
+ else:
+ ext = ".tar.gz"
+ else:
+ if osname == "windows":
+ ext = ".7z"
+ else:
+ ext = ".tar.xz"
+
+ return f"zephyr-sdk-{version}_{osname}-{arch}_minimal{ext}"
+
+ def minimal_sdk_sha256(self, sha256_list, release):
+ name = self.minimal_sdk_filename(release)
+ tuples = [(re.split(r"\s+", t)) for t in sha256_list.splitlines()]
+ hashtable = {t[1]: t[0] for t in tuples}
+
+ return hashtable[name]
+
+ def minimal_sdk_url(self, release):
+ name = self.minimal_sdk_filename(release)
+ assets = release.get("assets", [])
+ minimal_sdk_asset = next(filter(lambda x: x["name"] == name, assets))
+
+ return minimal_sdk_asset["browser_download_url"]
+
+ def sha256_sum_url(self, release):
+ assets = release.get("assets", [])
+ minimal_sdk_asset = next(filter(lambda x: x["name"] == "sha256.sum", assets))
+
+ return minimal_sdk_asset["browser_download_url"]
+
+ def download_and_extract(self, base_dir, dir_name, target_release, req_headers):
+ self.inf("Fetching sha256...")
+ sha256_url = self.sha256_sum_url(target_release)
+ resp = requests.get(sha256_url, headers=req_headers, stream=True)
+ if resp.status_code != 200:
+ raise Exception(f"Failed to download {sha256_url}: {resp.status_code}")
+
+ sha256 = self.minimal_sdk_sha256(resp.content.decode("UTF-8"), target_release)
+
+ archive_url = self.minimal_sdk_url(target_release)
+ self.inf(f"Downloading {archive_url}...")
+ resp = requests.get(archive_url, headers=req_headers, stream=True)
+ if resp.status_code != 200:
+ raise Exception(f"Failed to download {archive_url}: {resp.status_code}")
+
+ try:
+ Path(base_dir).mkdir(parents=True, exist_ok=True)
+
+ with tempfile.TemporaryDirectory(dir=base_dir) as tempdir:
+ # download archive file
+ filename = Path(tempdir) / re.sub(r"^.*/", "", archive_url)
+ file = open(filename, mode="wb")
+ total_length = int(resp.headers["Content-Length"])
+ count = 0
+
+ for chunk in resp.iter_content(chunk_size=8192):
+ file.write(chunk)
+ count = count + len(chunk)
+ self.inf(f"\r {count}/{total_length}", end="")
+ self.inf()
+ self.inf(f"Downloaded: {file.name}")
+ file.close()
+
+ # check sha256 hash
+ with open(file.name, "rb") as sha256file:
+ digest = hashlib.sha256(sha256file.read()).hexdigest()
+ if sha256 != digest:
+ raise Exception(f"sha256 mismatched: {sha256}:{digest}")
+
+ # extract archive file
+ self.inf(f"Extract: {file.name}")
+ patoolib.extract_archive(file.name, outdir=tempdir)
+
+ # We expect that only the zephyr-sdk-x.y.z directory will be present in the archive.
+ extracted_dirs = [d for d in Path(tempdir).iterdir() if d.is_dir()]
+ if len(extracted_dirs) != 1:
+ raise Exception("Unexpected archive format")
+
+ # move to destination dir
+ if dir_name:
+ dest_dir = Path(base_dir / dir_name)
+ else:
+ dest_dir = Path(base_dir / extracted_dirs[0].name)
+
+ Path(dest_dir).parent.mkdir(parents=True, exist_ok=True)
+
+ self.inf(f"Move: {str(extracted_dirs[0])} to {dest_dir}.")
+ shutil.move(extracted_dirs[0], dest_dir)
+
+ return dest_dir
+ except PermissionError as pe:
+ self.die(pe)
+
+ def run_setup(self, args, sdk_dir):
+ if "Windows" == platform.system():
+ setup = Path(sdk_dir) / "setup.cmd"
+ optsep = "/"
+ else:
+ setup = Path(sdk_dir) / "setup.sh"
+ optsep = "-"
+
+ # Associate installed SDK so that it can be found.
+ cmds_cmake_pkg = [str(setup), f"{optsep}c"]
+ self.dbg("Run: ", cmds_cmake_pkg)
+ result = subprocess.run(cmds_cmake_pkg)
+ if result.returncode != 0:
+ self.die(f"command \"{' '.join(cmds_cmake_pkg)}\" failed")
+
+ cmds = [str(setup)]
+
+ if not args.interactive and not args.no_toolchains:
+ if not args.toolchains:
+ cmds.extend([f"{optsep}t", "all"])
+ else:
+ for tc in args.toolchains:
+ cmds.extend([f"{optsep}t", tc])
+
+ if not args.interactive and not args.no_hosttools:
+ cmds.extend([f"{optsep}h"])
+
+ if args.interactive or len(cmds) != 1:
+ self.dbg("Run: ", cmds)
+ result = subprocess.run(cmds)
+ if result.returncode != 0:
+ self.die(f"command \"{' '.join(cmds)}\" failed")
+
+ def install_sdk(self, args, user_args):
+ version = self.detect_version(args)
+ (osname, arch) = self.os_arch_name()
+
+ if args.personal_access_token:
+ req_headers = {
+ "Authorization": f"Bearer {args.personal_access_token}",
+ }
+ else:
+ req_headers = {}
+
+ self.inf("Fetching Zephyr SDK list...")
+ releases = self.fetch_releases(args.api_url, req_headers)
+ self.dbg("releases: ", "\n".join([x["tag_name"] for x in releases]))
+
+ # checking version
+ def check_semver(version):
+ try:
+ semver.Version.parse(version)
+ return True
+ except Exception:
+ return False
+
+ available_versions = [
+ re.sub(r"^v", "", x["tag_name"])
+ for x in releases
+ if check_semver(re.sub(r"^v", "", x["tag_name"]))
+ ]
+
+ if not version in available_versions:
+ self.die(
+ f"Unavailable SDK version: {version}."
+ + "Please select from the list below:\n"
+ + "\n".join(available_versions)
+ )
+
+ target_release = [x for x in releases if x["tag_name"] == f"v{version}"][0]
+
+ # checking toolchains parameters
+ assets = target_release["assets"]
+ self.dbg("assets: ", "\n".join([x["browser_download_url"] for x in assets]))
+
+ prefix = f"toolchain_{osname}-{arch}_"
+ available_toolchains = [
+ re.sub(r"\..*", "", x["name"].replace(prefix, ""))
+ for x in assets
+ if x["name"].startswith(prefix)
+ ]
+
+ if args.toolchains:
+ for tc in args.toolchains:
+ if not tc in available_toolchains:
+ self.die(
+ f"toolchain {tc} is not available.\n"
+ + "Please select from the list below:\n"
+ + "\n".join(available_toolchains)
+ )
+
+ installed_info = [v for (k, v) in self.fetch_sdk_info().items() if k == version]
+ if len(installed_info) == 0:
+ if args.install_dir:
+ base_dir = Path(args.install_dir).parent
+ dir_name = Path(args.install_dir).name
+ elif args.install_base:
+ base_dir = Path(args.install_base)
+ dir_name = None
+ else:
+ base_dir = Path("~").expanduser()
+ dir_name = None
+
+ sdk_dir = self.download_and_extract(
+ base_dir, dir_name, target_release, req_headers
+ )
+ else:
+ sdk_dir = Path(installed_info[0]["path"])
+ self.inf(
+ f"Zephyr SDK version {version} is already installed at {str(sdk_dir)}. Using it."
+ )
+
+ self.run_setup(args, sdk_dir)
+
+ def fetch_sdk_info(self):
+ sdk_lines = []
+ try:
+ cmds = [
+ "-P",
+ str(Path(__file__).parent / "sdk" / "listsdk.cmake"),
+ ]
+
+ output = zcmake.run_cmake(cmds, capture_output=True)
+ if output:
+ # remove '-- Zephyr-sdk,' leader
+ sdk_lines = [l[15:] for l in output if l.startswith("-- Zephyr-sdk,")]
+ else:
+ sdk_lines = []
+
+ except Exception as e:
+ self.die(e)
+
+ def parse_sdk_entry(line):
+ class SdkEntry:
+ def __init__(self):
+ self.version = None
+ self.path = None
+
+ info = SdkEntry()
+ for ent in line.split(","):
+ kv = ent.split("=")
+ if kv[0].strip() == "ver":
+ info.version = kv[1].strip()
+ elif kv[0].strip() == "dir":
+ info.path = kv[1].strip()
+
+ return info
+
+ sdk_info = {}
+ for sdk_ent in [parse_sdk_entry(l) for l in reversed(sdk_lines)]:
+ entry = {}
+
+ ver = None
+ sdk_path = Path(sdk_ent.path)
+ sdk_version_path = sdk_path / "sdk_version"
+ if sdk_version_path.exists():
+ with open(str(sdk_version_path)) as f:
+ ver = f.readline().strip()
+ else:
+ continue
+
+ entry["path"] = sdk_path
+
+ if (sdk_path / "sysroots").exists():
+ entry["hosttools"] = "installed"
+
+ # Identify toolchain directory by the existence of <toolchain>/bin/<toolchain>-gcc
+ if "Windows" == platform.system():
+ gcc_postfix = "-gcc.exe"
+ else:
+ gcc_postfix = "-gcc"
+
+ toolchains = [
+ tc.name
+ for tc in sdk_path.iterdir()
+ if (sdk_path / tc / "bin" / (tc.name + gcc_postfix)).exists()
+ ]
+
+ if len(toolchains) > 0:
+ entry["toolchains"] = toolchains
+
+ if ver:
+ sdk_info[ver] = entry
+
+ return sdk_info
+
+ def list_sdk(self):
+ sdk_info = self.fetch_sdk_info()
+
+ if len(sdk_info) == 0:
+ self.die("No Zephyr SDK installed.")
+
+ for k, v in sdk_info.items():
+ self.inf(f"{k}:")
+ self.inf(f" path: {v['path']}")
+ if "hosttools" in v:
+ self.inf(f" hosttools: {v['hosttools']}")
+ if "toolchains" in v:
+ self.inf(" installed-toolchains:")
+ for tc in v["toolchains"]:
+ self.inf(f" - {tc}")
+
+ # Since version 0.15.2, the sdk_toolchains file is included,
+ # so we can get information about available toolchains from there.
+ if (Path(v["path"]) / "sdk_toolchains").exists():
+ with open(Path(v["path"]) / "sdk_toolchains") as f:
+ all_tcs = [l.strip() for l in f.readlines()]
+
+ self.inf(" available-toolchains:")
+ for tc in all_tcs:
+ if tc not in v["toolchains"]:
+ self.inf(f" - {tc}")
+
+ self.inf()
+
+ def do_run(self, args, user_args):
+ self.dbg("args: ", args)
+ if args.subcommand == "install":
+ self.install_sdk(args, user_args)
+ elif args.subcommand == "list" or not args.subcommand:
+ self.list_sdk()
diff --git a/scripts/west_commands/sdk/listsdk.cmake b/scripts/west_commands/sdk/listsdk.cmake
new file mode 100644
index 0000000..e084c59
--- /dev/null
+++ b/scripts/west_commands/sdk/listsdk.cmake
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+set(ZEPHYR_BASE $ENV{ZEPHYR_BASE} CACHE PATH "Zephyr base")
+set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${ZEPHYR_BASE}/cmake/modules)
+
+find_package(Zephyr-sdk COMPONENTS LIST)
diff --git a/soc/Kconfig b/soc/Kconfig
index 51af859..af32c5c 100644
--- a/soc/Kconfig
+++ b/soc/Kconfig
@@ -58,6 +58,8 @@
the Zephyr release that the SoC configuration will be removed.
When set, any build for that SoC will generate a clearly visible
deprecation warning.
+ When adding this to a SOC, remember to follow the instructions in
+ https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated
config SOC_HAS_TIMING_FUNCTIONS
bool
diff --git a/soc/ambiq/apollo3x/CMakeLists.txt b/soc/ambiq/apollo3x/CMakeLists.txt
index 4d73e4e..e83284c 100644
--- a/soc/ambiq/apollo3x/CMakeLists.txt
+++ b/soc/ambiq/apollo3x/CMakeLists.txt
@@ -5,6 +5,7 @@
zephyr_sources(soc.c)
zephyr_include_directories(.)
+zephyr_sources_ifdef(CONFIG_PM power.c)
zephyr_linker_sources(SECTIONS shared_ram.ld)
diff --git a/soc/ambiq/apollo3x/Kconfig b/soc/ambiq/apollo3x/Kconfig
index de93bd9..ad9fb25 100644
--- a/soc/ambiq/apollo3x/Kconfig
+++ b/soc/ambiq/apollo3x/Kconfig
@@ -10,3 +10,4 @@
select CPU_HAS_ARM_MPU
select HAS_SWO
select AMBIQ_HAL
+ select HAS_PM
diff --git a/soc/ambiq/apollo3x/Kconfig.defconfig b/soc/ambiq/apollo3x/Kconfig.defconfig
index abac3c9..95e84ae 100644
--- a/soc/ambiq/apollo3x/Kconfig.defconfig
+++ b/soc/ambiq/apollo3x/Kconfig.defconfig
@@ -6,4 +6,9 @@
rsource "Kconfig.defconfig.apollo3*"
+# Need to enlarge the IDLE stack size because the power
+# management operations are executed in the idle task
+config IDLE_STACK_SIZE
+ default 2048 if PM
+
endif # SOC_SERIES_APOLLO3X
diff --git a/soc/ambiq/apollo3x/power.c b/soc/ambiq/apollo3x/power.c
new file mode 100644
index 0000000..630a346
--- /dev/null
+++ b/soc/ambiq/apollo3x/power.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+
+/* ambiq-sdk includes */
+#include <am_mcu_apollo.h>
+
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+ ARG_UNUSED(substate_id);
+
+ __disable_irq();
+ __set_BASEPRI(0);
+
+ switch (state) {
+ case PM_STATE_SUSPEND_TO_IDLE:
+ /* Put ARM core to normal sleep. */
+ am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL);
+ break;
+ case PM_STATE_SUSPEND_TO_RAM:
+ /* Put ARM core to deep sleep. */
+ /* Cotex-m: power down, register value preserve.*/
+ /* Cache: power down*/
+ /* Flash: power down*/
+ /* Sram: retention*/
+ am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
+ break;
+ default:
+ LOG_DBG("Unsupported power state %u", state);
+ break;
+ }
+}
+
+/**
+ * @brief PM State Exit Post Operations
+ *
+ * For PM_STATE_SUSPEND_TO_IDLE:
+ * Nothing is needed after soc woken up.
+ *
+ * For PM_STATE_SUSPEND_TO_RAM:
+ * Flash, cache, sram automatically switch
+ * to active state on wake up
+ *
+ * @param state PM State
+ * @param substate_id Unused
+ *
+ */
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+ ARG_UNUSED(substate_id);
+
+ __enable_irq();
+ irq_unlock(0);
+}
+
+static int ambiq_power_init(void)
+{
+ /* Enable flash.
+ * Currently all flash area is powered on, but we should only enable the used flash area and
+ * put unused flash in power down mode.
+ */
+ if (am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEM_FLASH_MAX)) {
+ __ASSERT(0, "Failed to enable FLASH!");
+ }
+
+ /* Enable SRAM.
+ * Currently all SRAM area is powered on, but we should only enable the used ram area and
+ * put unused ram in power down mode.
+ */
+ if (am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEM_SRAM_MAX)) {
+ __ASSERT(0, "Failed to enable SRAM!");
+ }
+
+ /* For optimal Deep Sleep current, configure cache to be powered-down in deepsleep. */
+ am_hal_pwrctrl_memory_deepsleep_powerdown(AM_HAL_PWRCTRL_MEM_CACHE);
+
+ /* Power off all flash area, when go to deep sleep.*/
+ am_hal_pwrctrl_memory_deepsleep_powerdown(AM_HAL_PWRCTRL_MEM_FLASH_MAX);
+
+ /* Keep the used SRAM area in retention mode. */
+ am_hal_pwrctrl_memory_deepsleep_powerdown(AM_HAL_PWRCTRL_MEM_SRAM_MAX);
+ am_hal_pwrctrl_memory_deepsleep_retain(AM_HAL_PWRCTRL_MEM_SRAM_MAX);
+
+#if defined(CONFIG_SOC_APOLLO3P_BLUE)
+ /*
+ * If user has enabled AM_HAL_SYSCTRL_DEEPSLEEP_WA in am_hal_sysctrl.h
+ * this will allow user to acheive lower current draw in deepsleep
+ */
+ am_hal_sysctrl_control(AM_HAL_SYSCTRL_CONTROL_DEEPSLEEP_MINPWR_EN, 0);
+#endif
+
+ return 0;
+}
+
+SYS_INIT(ambiq_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/ambiq/apollo3x/soc.c b/soc/ambiq/apollo3x/soc.c
index d10b4a5..c76dda6 100644
--- a/soc/ambiq/apollo3x/soc.c
+++ b/soc/ambiq/apollo3x/soc.c
@@ -10,6 +10,12 @@
static int arm_apollo3_init(void)
{
+ /* Set the clock frequency. */
+ am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
+
+ /* Enable Flash cache.*/
+ am_hal_cachectrl_config(&am_hal_cachectrl_defaults);
+ am_hal_cachectrl_enable();
/* Initialize for low power in the power control block */
am_hal_pwrctrl_low_power_init();
diff --git a/soc/ambiq/apollo4x/power.c b/soc/ambiq/apollo4x/power.c
index 8fe8557..3095043 100644
--- a/soc/ambiq/apollo4x/power.c
+++ b/soc/ambiq/apollo4x/power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024 Ambiq LLC
+ * Copyright (c) 2024 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/soc/aspeed/ast10x0/soc.c b/soc/aspeed/ast10x0/soc.c
index b7f74ef..f443fcd 100644
--- a/soc/aspeed/ast10x0/soc.c
+++ b/soc/aspeed/ast10x0/soc.c
@@ -107,10 +107,11 @@
/* ABR enable */
if (sys_read32(HW_STRAP2_SCU510) & BIT(11)) {
printk("FMC ABR: Enable");
- if (sys_read32(HW_STRAP2_SCU510) & BIT(12))
+ if (sys_read32(HW_STRAP2_SCU510) & BIT(12)) {
printk(", Single flash");
- else
+ } else {
printk(", Dual flashes");
+ }
printk(", Source: %s (%d)",
(sys_read32(ASPEED_FMC_WDT2_CTRL) & BIT(4)) ? "Alternate" : "Primary",
diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig
index 381a7e3..b474c8c 100644
--- a/soc/espressif/common/Kconfig.defconfig
+++ b/soc/espressif/common/Kconfig.defconfig
@@ -1,7 +1,7 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
-if SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
+if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
config GEN_ISR_TABLES
default y
@@ -22,7 +22,8 @@
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
- default 16000000
+ default 12000000 if SOC_SERIES_ESP32C2
+ default 16000000 if SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
config SYS_CLOCK_TICKS_PER_SEC
default 1000
@@ -49,7 +50,7 @@
endif # BOOTLOADER_MCUBOOT
-endif # SOC_SERIES_ESP32C3
+endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
diff --git a/soc/espressif/common/Kconfig.esptool b/soc/espressif/common/Kconfig.esptool
index f7c6e7b..5235a20 100644
--- a/soc/espressif/common/Kconfig.esptool
+++ b/soc/espressif/common/Kconfig.esptool
@@ -81,6 +81,7 @@
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32
+ default ESPTOOLPY_FLASHFREQ_60M if SOC_SERIES_ESP32C2
default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
config ESPTOOLPY_FLASHFREQ_120M
@@ -99,6 +100,8 @@
config ESPTOOLPY_FLASHFREQ_80M
bool "80 MHz"
+config ESPTOOLPY_FLASHFREQ_60M
+ bool "60 MHz"
config ESPTOOLPY_FLASHFREQ_40M
bool "40 MHz"
config ESPTOOLPY_FLASHFREQ_26M
@@ -121,6 +124,7 @@
# We currently define this to `80m`.
default '80m' if ESPTOOLPY_FLASHFREQ_120M
default '80m' if ESPTOOLPY_FLASHFREQ_80M
+ default '60m' if ESPTOOLPY_FLASHFREQ_60M
default '40m' if ESPTOOLPY_FLASHFREQ_40M
default '26m' if ESPTOOLPY_FLASHFREQ_26M
default '20m' if ESPTOOLPY_FLASHFREQ_20M
diff --git a/soc/espressif/common/Kconfig.flash b/soc/espressif/common/Kconfig.flash
index 71eb970..6b89e80 100644
--- a/soc/espressif/common/Kconfig.flash
+++ b/soc/espressif/common/Kconfig.flash
@@ -94,7 +94,7 @@
choice BOOTLOADER_VDDSDIO_BOOST
bool "VDDSDIO LDO voltage"
default BOOTLOADER_VDDSDIO_BOOST_1_9V
- depends on !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
+ depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
help
If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse
or MTDI bootstrapping pin), bootloader will change LDO settings to
diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c
index 7700b7d..111fff5 100644
--- a/soc/espressif/common/loader.c
+++ b/soc/espressif/common/loader.c
@@ -38,11 +38,6 @@
#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr))
-#define BOOT_LOG_INF(_fmt, ...) \
- ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
-#define BOOT_LOG_ERR(_fmt, ...) \
- ets_printf("[" CONFIG_SOC_SERIES "] [ERR] " _fmt "\n\r", ##__VA_ARGS__)
-
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
void __start(void);
@@ -94,7 +89,7 @@
if (spi_flash_read(offset, &segment_hdr,
sizeof(esp_image_segment_header_t)) != ESP_OK) {
- BOOT_LOG_ERR("Failed to read segment header at %x", offset);
+ ESP_EARLY_LOGE(TAG, "Failed to read segment header at %x", offset);
abort();
}
@@ -104,7 +99,7 @@
break;
}
- BOOT_LOG_INF("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)",
+ ESP_EARLY_LOGI(TAG, "%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)",
IS_NONE(segment_hdr.load_addr) ? "???" :
IS_MMAP(segment_hdr.load_addr) ?
IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP" :
@@ -135,11 +130,11 @@
}
}
if (segments == 0 || segments == 16) {
- BOOT_LOG_ERR("Error parsing segments");
+ ESP_EARLY_LOGE(TAG, "Error parsing segments");
abort();
}
- BOOT_LOG_INF("Image with %d segments", segments - 1);
+ ESP_EARLY_LOGI(TAG, "Image with %d segments", segments - 1);
#endif /* !CONFIG_BOOTLOADER_MCUBOOT */
#if CONFIG_SOC_SERIES_ESP32
@@ -172,7 +167,7 @@
rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned,
app_irom_start_aligned, 64, irom_page_count);
if (rc != 0) {
- BOOT_LOG_ERR("Failed to setup XIP, aborting");
+ ESP_EARLY_LOGE(TAG, "Failed to setup XIP, aborting");
abort();
}
#else
@@ -216,12 +211,15 @@
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#endif
/* Show map segments continue using same log format as during MCUboot phase */
- BOOT_LOG_INF("DROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map",
+ ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map",
+ "DROM",
app_drom_start_aligned, app_drom_vaddr_aligned,
app_drom_size, app_drom_size);
- BOOT_LOG_INF("IROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map\r\n",
+ ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map",
+ "IROM",
app_irom_start_aligned, app_irom_vaddr_aligned,
app_irom_size, app_irom_size);
+ ets_printf("\n\r");
esp_rom_uart_tx_wait_idle(0);
}
@@ -241,7 +239,7 @@
#ifndef CONFIG_BOOTLOADER_MCUBOOT
/* Init fundamental components */
if (bootloader_init()) {
- BOOT_LOG_ERR("HW init failed, aborting");
+ ESP_EARLY_LOGE(TAG, "HW init failed, aborting");
abort();
}
#endif
diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c
index ca2de23..1c60064 100644
--- a/soc/espressif/esp32/esp32-mp.c
+++ b/soc/espressif/esp32/esp32-mp.c
@@ -276,14 +276,18 @@
cpus_active[0] = true;
cpus_active[cpu_num] = true;
- esp_intr_alloc(DT_IRQN(DT_NODELABEL(ipi0)),
- ESP_INTR_FLAG_IRAM,
+ esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(ipi0), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(ipi0), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(ipi0), 0, flags)) |
+ ESP_INTR_FLAG_IRAM,
esp_crosscore_isr,
NULL,
NULL);
- esp_intr_alloc(DT_IRQN(DT_NODELABEL(ipi1)),
- ESP_INTR_FLAG_IRAM,
+ esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(ipi1), 0, irq),
+ ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(ipi1), 0, priority)) |
+ ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(ipi1), 0, flags)) |
+ ESP_INTR_FLAG_IRAM,
esp_crosscore_isr,
NULL,
NULL);
diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c
index 0240a10..390c8b2 100644
--- a/soc/espressif/esp32/soc.c
+++ b/soc/espressif/esp32/soc.c
@@ -41,6 +41,9 @@
#endif /* CONFIG_SOC_ENABLE_APPCPU */
#include <zephyr/sys/printk.h>
+#include "esp_log.h"
+
+#define TAG "boot.esp32"
#if CONFIG_ESP_SPIRAM
extern int _ext_ram_bss_start;
@@ -155,17 +158,17 @@
esp_err_t err = esp_psram_init();
if (err != ESP_OK) {
- printk("Failed to Initialize SPIRAM, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "Failed to Initialize SPIRAM, aborting.");
abort();
}
if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
- printk("SPIRAM size is less than configured size, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "SPIRAM size is less than configured size, aborting.");
abort();
}
if (esp_psram_is_initialized()) {
if (!esp_psram_extram_test()) {
- printk("External RAM failed memory test!");
+ ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
abort();
}
}
diff --git a/soc/espressif/esp32c2/CMakeLists.txt b/soc/espressif/esp32c2/CMakeLists.txt
new file mode 100644
index 0000000..c7d671b
--- /dev/null
+++ b/soc/espressif/esp32c2/CMakeLists.txt
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+ vectors.S
+ soc_irq.S
+ soc_irq.c
+ soc.c
+ ../common/loader.c
+ )
+
+zephyr_include_directories(.)
+
+# get flash size to use in esptool as string
+math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
+
+if(NOT CONFIG_BOOTLOADER_MCUBOOT)
+
+ if(CONFIG_BUILD_OUTPUT_BIN)
+ # make ESP ROM loader compatible image
+ message("ESP-IDF path: ${ESP_IDF_PATH}")
+
+ set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
+ message("esptool path: ${ESPTOOL_PY}")
+
+ set(ELF2IMAGE_ARG "")
+ if(NOT CONFIG_MCUBOOT)
+ set(ELF2IMAGE_ARG "--ram-only-header")
+ endif()
+
+ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+ COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
+ ARGS --chip esp32c2 elf2image ${ELF2IMAGE_ARG}
+ --flash_mode dio --flash_freq 60m --flash_size ${esptoolpy_flashsize}MB
+ -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
+ ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
+ endif()
+
+endif()
+
+# get code-partition slot0 address
+dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
+dt_reg_addr(img_0_off PATH ${dts_partition_path})
+
+# get code-partition boot address
+dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
+dt_reg_addr(boot_off PATH ${dts_partition_path})
+
+# C2 uses specific values for flash frequency and UART baudrate
+board_runner_args(esp32 "--esp-flash-freq=60m")
+board_runner_args(esp32 "--esp-monitor-baud=74880")
+
+if(CONFIG_ESP_SIMPLE_BOOT)
+ board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
+else()
+ board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
+endif()
+
+if(CONFIG_MCUBOOT)
+ # search from cross references between bootloader sections
+ message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
+ set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+ COMMAND
+ ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
+ ARGS
+ --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
+ --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
+ find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
+ --exit-code)
+endif()
+
+if(CONFIG_MCUBOOT)
+ set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
+else()
+ set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
+endif()
diff --git a/soc/espressif/esp32c2/Kconfig b/soc/espressif/esp32c2/Kconfig
new file mode 100644
index 0000000..2ff6734
--- /dev/null
+++ b/soc/espressif/esp32c2/Kconfig
@@ -0,0 +1,28 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32C2
+ select RISCV
+ select RISCV_GP
+ select DYNAMIC_INTERRUPTS
+ select CLOCK_CONTROL
+ select PINCTRL
+ select RISCV_ISA_RV32I
+ select RISCV_ISA_EXT_M
+ select RISCV_ISA_EXT_C
+ select RISCV_ISA_EXT_ZICSR
+ select HAS_ESPRESSIF_HAL
+ select XIP if !MCUBOOT
+
+if SOC_SERIES_ESP32C2
+
+config MAC_BB_PD
+ bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
+ depends on SOC_SERIES_ESP32C2 && TICKLESS_KERNEL
+ help
+ If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
+ down when PHY is disabled. Enabling this setting reduces power consumption
+ by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
+ 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
+
+endif # SOC_SERIES_ESP32C2
diff --git a/soc/espressif/esp32c2/Kconfig.defconfig b/soc/espressif/esp32c2/Kconfig.defconfig
new file mode 100644
index 0000000..36604de
--- /dev/null
+++ b/soc/espressif/esp32c2/Kconfig.defconfig
@@ -0,0 +1,17 @@
+# ESP32C2 SoC configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32C2
+
+config NUM_IRQS
+ default 43
+
+config FLASH_SIZE
+ default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
+
+config FLASH_BASE_ADDRESS
+ default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
+
+endif # SOC_SERIES_ESP32C2
diff --git a/soc/espressif/esp32c2/Kconfig.mac b/soc/espressif/esp32c2/Kconfig.mac
new file mode 100644
index 0000000..85b20dd
--- /dev/null
+++ b/soc/espressif/esp32c2/Kconfig.mac
@@ -0,0 +1,48 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32C2
+
+choice ESP32C2_UNIVERSAL_MAC_ADDRESSES
+ bool "Number of universally administered (by IEEE) MAC address"
+ default ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
+ help
+ Configure the number of universally administered (by IEEE) MAC addresses.
+ During initialization, MAC addresses for each network interface are generated or derived from a
+ single base MAC address.
+ If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
+ Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
+ sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
+ If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
+ receive a universally administered MAC address. These are generated sequentially by adding 0
+ and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
+ receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
+ addresses, respectively.
+ When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
+ a custom universal MAC address range, the correct setting will depend on the allocation of MAC
+ addresses in this range (either 2 or 4 per device.)
+ Note that ESP32-C6 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
+ API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
+
+config ESP32C2_UNIVERSAL_MAC_ADDRESSES_TWO
+ bool "Two"
+ select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
+ select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+ select ESP_MAC_ADDR_UNIVERSE_BT
+
+config ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
+ bool "Four"
+ select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
+ select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+ select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
+ select ESP_MAC_ADDR_UNIVERSE_BT
+ select ESP_MAC_ADDR_UNIVERSE_ETH
+
+endchoice # ESP32C2_UNIVERSAL_MAC_ADDRESSES
+
+config ESP32C2_UNIVERSAL_MAC_ADDRESSES
+ int
+ default 2 if ESP32C2_UNIVERSAL_MAC_ADDRESSES_TWO
+ default 4 if ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
+
+endif # SOC_SERIES_ESP32C2
diff --git a/soc/espressif/esp32c2/Kconfig.soc b/soc/espressif/esp32c2/Kconfig.soc
new file mode 100644
index 0000000..c507068
--- /dev/null
+++ b/soc/espressif/esp32c2/Kconfig.soc
@@ -0,0 +1,38 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32C2
+ bool
+ select SOC_FAMILY_ESPRESSIF_ESP32
+
+config SOC_ESP8684_MINI_H2
+ bool
+ select SOC_ESP32C2
+
+config SOC_ESP8684_MINI_H4
+ bool
+ select SOC_ESP32C2
+
+config SOC_ESP8684_WROOM_H2
+ bool
+ select SOC_ESP32C2
+
+config SOC_ESP8684_WROOM_H4
+ bool
+ select SOC_ESP32C2
+
+config SOC_ESP32C2
+ bool
+ select SOC_SERIES_ESP32C2
+
+config SOC_SERIES
+ default "esp32c2" if SOC_SERIES_ESP32C2
+
+config SOC
+ default "esp32c2" if SOC_ESP32C2
+
+config SOC_PART_NUMBER
+ default "ESP8684_MINI_1_H2" if SOC_ESP8684_MINI_H2
+ default "ESP8684_MINI_1_H4" if SOC_ESP8684_MINI_H4
+ default "ESP8684_WROOM_01C_H2" if SOC_ESP8684_WROOM_H2
+ default "ESP8684_WROOM_01C_H4" if SOC_ESP8684_WROOM_H4
diff --git a/soc/espressif/esp32c2/default.ld b/soc/espressif/esp32c2/default.ld
new file mode 100644
index 0000000..5b62444
--- /dev/null
+++ b/soc/espressif/esp32c2/default.ld
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+
+#include "memory.h"
+
+/* The "user_iram_end" represents the 2nd stage bootloader
+ * "iram_loader_seg" start address (that should not be overlapped).
+ * If no bootloader is used, we can extend it to gain more user ram.
+ */
+#ifdef CONFIG_ESP_SIMPLE_BOOT
+user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET);
+#else
+user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
+#endif
+
+/* User available SRAM memory segments */
+user_iram_seg_org = SRAM1_IRAM_START;
+user_dram_seg_org = SRAM1_DRAM_START;
+user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET);
+user_idram_size = (user_dram_end - user_dram_seg_org);
+user_iram_seg_len = user_idram_size;
+user_dram_seg_len = user_idram_size;
+
+/* Aliases */
+#define FLASH_CODE_REGION irom0_0_seg
+#define RODATA_REGION drom0_0_seg
+#define IRAM_REGION iram0_0_seg
+#define DRAM_REGION dram0_0_seg
+#define RAMABLE_REGION dram0_0_seg
+#define ROMABLE_REGION FLASH
+
+/* Flash segments (rodata and text) should be mapped in the virtual address spaces.
+ * Executing directly from LMA is not possible. */
+#undef GROUP_ROM_LINK_IN
+#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
+
+/* Make sure new sections have consistent alignment between input and output sections */
+#undef SECTION_PROLOGUE
+#define SECTION_PROLOGUE SECTION_DATA_PROLOGUE
+
+/* Global symbols required for espressif hal build */
+MEMORY
+{
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+ mcuboot_hdr (R): org = 0x0, len = 0x20
+ metadata (R): org = 0x20, len = 0x20
+ FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40
+#else
+ /* Make safety margin in the FLASH memory size so the
+ * (esp_img_header + (n*esp_seg_headers)) would fit */
+ FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
+#endif
+
+ iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len
+ dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len
+
+ irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
+ drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
+
+#ifdef CONFIG_GEN_ISR_TABLES
+ IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
+#endif
+}
+
+/* Default entry point: */
+ENTRY(CONFIG_KERNEL_ENTRY)
+
+_rom_store_table = 0;
+
+_iram_dram_offset = IRAM_DRAM_OFFSET;
+
+SECTIONS
+{
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+ /* Reserve space for MCUboot header in the binary */
+ .mcuboot_header :
+ {
+ QUAD(0x0)
+ QUAD(0x0)
+ QUAD(0x0)
+ QUAD(0x0)
+ } > mcuboot_hdr
+ .metadata :
+ {
+ /* 0. Magic byte for load header */
+ LONG(0xace637d3)
+
+ /* 1. Application entry point address */
+ KEEP(*(.entry_addr))
+
+ /* IRAM metadata:
+ * 2. Destination address (VMA) for IRAM region
+ * 3. Flash offset (LMA) for start of IRAM region
+ * 4. Size of IRAM region
+ */
+ LONG(ADDR(.iram0.text))
+ LONG(LOADADDR(.iram0.text))
+ LONG(LOADADDR(.iram0.data) - LOADADDR(.iram0.text))
+
+ /* DRAM metadata:
+ * 5. Destination address (VMA) for DRAM region
+ * 6. Flash offset (LMA) for start of DRAM region
+ * 7. Size of DRAM region
+ */
+ LONG(ADDR(.dram0.data))
+ LONG(LOADADDR(.dram0.data))
+ LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data))
+ } > metadata
+#endif /* CONFIG_BOOTLOADER_MCUBOOT */
+
+ iram_vma = ADDR(.iram0.text);
+ iram_lma = LOADADDR(.iram0.text);
+ iram_size_field = LOADADDR(.iram0.data) - LOADADDR(.iram0.text);
+
+ dram_vma = ADDR(.dram0.data);
+ dram_lma = LOADADDR(.dram0.data);
+ dram_size_field = LOADADDR(.dram0.end) - LOADADDR(.dram0.data);
+
+ #include <zephyr/linker/rel-sections.ld>
+
+#ifdef CONFIG_LLEXT
+ #include <zephyr/linker/llext-sections.ld>
+#endif
+
+ /* --- START OF IRAM --- */
+
+ .iram0.text : ALIGN(4)
+ {
+ /* Vectors go to IRAM */
+ _iram_start = ABSOLUTE(.);
+ _init_start = ABSOLUTE(.);
+
+ KEEP(*(.exception_vectors.text));
+ . = ALIGN(256);
+
+ _invalid_pc_placeholder = ABSOLUTE(.);
+
+ KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
+ *(.exception.other*)
+ . = ALIGN(4);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ . = ALIGN(4);
+
+ _init_end = ABSOLUTE(.);
+ _iram_text_start = ABSOLUTE(.);
+
+ *(.iram1 .iram1.*)
+ *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+ *libzephyr.a:panic.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:loader.*(.literal .text .literal.* .text.*)
+ *libarch__riscv__core.a:(.literal .text .literal.* .text.*)
+ *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
+ *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
+ *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)
+ *libsubsys__net.a:(.literal .text .literal.* .text.*)
+ *libkernel.a:(.literal .text .literal.* .text.*)
+ *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
+ *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
+ *libdrivers__timer.a:esp32c2_sys_timer.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
+ *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
+ *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
+ *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*)
+ *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
+ *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
+ *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+ *libgcov.a:(.literal .text .literal.* .text.*)
+ *libphy.a:( .phyiram .phyiram.*)
+ *libc.a:*(.literal .text .literal.* .text.*)
+
+ /* [mapping:hal] */
+ *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
+
+ /* [mapping:soc] */
+ *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*)
+
+ /* [mapping:log] */
+ *(.literal.esp_log_write .text.esp_log_write)
+ *(.literal.esp_log_timestamp .text.esp_log_timestamp)
+ *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
+ *(.literal.esp_log_impl_lock .text.esp_log_impl_lock)
+ *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout)
+ *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock)
+
+ /* [mapping:spi_flash] */
+ *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*)
+
+ /* [mapping:esp_system] */
+ *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*)
+ *(.literal.esp_system_abort .text.esp_system_abort)
+
+ /* [mapping:esp_hw_support] */
+ *(.literal.esp_cpu_stall .text.esp_cpu_stall)
+ *(.literal.esp_cpu_unstall .text.esp_cpu_unstall)
+ *(.literal.esp_cpu_reset .text.esp_cpu_reset)
+ *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr)
+ *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set)
+ *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins)
+ *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved)
+ *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config)
+ *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
+ *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:systimer.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
+ *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
+
+ /* [mapping:soc_pm] */
+ *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK)
+
+ /* [mapping:esp_rom] */
+ *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*)
+
+ /* [mapping:esp_mm] */
+ *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*)
+
+ *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+ *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+
+#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
+ *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
+ *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
+ *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*)
+
+ /* [mapping:esp_wifi] */
+ *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
+ *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper)
+
+ /* [mapping:esp_phy] */
+ *(.literal.esp_phy_enable .text.esp_phy_enable)
+ *(.literal.esp_phy_disable .text.esp_phy_disable)
+ *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off)
+#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
+
+#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
+ *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
+ *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
+#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */
+
+ . = ALIGN(4) + 16;
+
+ } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
+
+#ifdef CONFIG_ESP_SIMPLE_BOOT
+ .loader.text :
+ {
+ . = ALIGN(4);
+ _loader_text_start = ABSOLUTE(.);
+ *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_esp32c2.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_flash_config_esp32c2.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
+
+ *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_ops_esp32c2.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*)
+ *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*)
+
+ *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+
+ *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*)
+
+ /* ??? */
+ *libzephyr.a:esp_gpio_reserve.*(.literal .text .literal.* .text.*)
+
+ . = ALIGN(0x10) + 0x10;
+ _loader_text_end = ABSOLUTE(.);
+ } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
+#endif /* CONFIG_ESP_SIMPLE_BOOT */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ /* C2 memprot requires 512 B alignment for split lines */
+ . = ALIGN (16);
+ _iram_text_end = ABSOLUTE(.);
+ } GROUP_LINK_IN(IRAM_REGION)
+
+ .iram0.data :
+ {
+ . = ALIGN(16);
+ *(.iram.data)
+ *(.iram.data*)
+ } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(16);
+ *(.iram.bss)
+ *(.iram.bss*)
+
+ . = ALIGN(16);
+ _iram_end = ABSOLUTE(.);
+ } GROUP_LINK_IN(IRAM_REGION)
+
+ /* --- END OF IRAM --- */
+
+ /* --- START OF DRAM --- */
+
+ .dram0.dummy (NOLOAD):
+ {
+ /* Spacer section is required to skip .iram0.text area because
+ * iram0_0_seg and dram0_0_seg reflect the same address space on different buses.
+ */
+ . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org;
+ . = ALIGN(16) + 16;
+ } GROUP_LINK_IN(RAMABLE_REGION)
+
+ .dram0.data :
+ {
+ . = ALIGN(4);
+ _data_start = ABSOLUTE(.);
+ __data_start = ABSOLUTE(.);
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.data1)
+
+#ifdef CONFIG_RISCV_GP
+ . = ALIGN(8);
+ __global_pointer$ = . + 0x800;
+#endif /* CONFIG_RISCV_GP */
+
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+
+ /* All dependent functions should be placed in DRAM to avoid issue
+ * when flash cache is disabled */
+ *libkernel.a:fatal.*(.rodata .rodata.* .srodata .srodata.*)
+ *libkernel.a:init.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:cbprintf_complete*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:log_core.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:log_backend_uart.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:log_output.*(.rodata .rodata.* .srodata .srodata.*)
+ *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.* .srodata .srodata.*)
+ *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:loader.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*)
+
+ /* [mapping:hal] */
+ *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:cache_hal.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:systimer_hal.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .srodata .srodata.*)
+
+ /* [mapping:soc] */
+ *libzephyr.a:lldesc.*(.rodata .rodata.* .srodata .srodata.*)
+
+ /* [mapping:log] */
+ *(.rodata.esp_log_write)
+ *(.rodata.esp_log_timestamp)
+ *(.rodata.esp_log_early_timestamp)
+ *(.rodata.esp_log_impl_lock)
+ *(.rodata.esp_log_impl_lock_timeout)
+ *(.rodata.esp_log_impl_unlock)
+
+ /* [mapping:spi_flash] */
+ *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.* .srodata .srodata.*)
+
+ /* [mapping:esp_mm] */
+ *libzephyr.a:esp_cache.*(.rodata .rodata.* .srodata .srodata.*)
+
+ /* [mapping:esp_hw_support] */
+ *(.rodata.esp_cpu_stall)
+ *(.rodata.esp_cpu_unstall)
+ *(.rodata.esp_cpu_reset)
+ *(.rodata.esp_cpu_wait_for_intr)
+ *(.rodata.esp_cpu_compare_and_set)
+ *(.rodata.esp_gpio_reserve_pins)
+ *(.rodata.esp_gpio_is_pin_reserved)
+ *(.rodata.rtc_vddsdio_get_config)
+ *(.rodata.rtc_vddsdio_set_config)
+ *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:rtc_clk.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:systimer.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:mspi_timing_config.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.* .srodata .srodata.*)
+ *(.rodata.sar_periph_ctrl_power_enable)
+
+ /* [mapping:esp_system] */
+ *libzephyr.a:esp_err.*(.rodata .rodata.*)
+ *(.rodata.esp_system_abort)
+
+ . = ALIGN(4);
+ #include <snippets-rwdata.ld>
+ . = ALIGN(4);
+
+ KEEP(*(.jcr))
+ *(.dram1 .dram1.*)
+ . = ALIGN(4);
+ } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+#ifdef CONFIG_ESP_SIMPLE_BOOT
+ /* Secondary loader sections */
+ .loader.data :
+ {
+ . = ALIGN(4);
+ _loader_data_start = ABSOLUTE(.);
+ *libzephyr.a:bootloader_soc.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_init.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_flash.*(.srodata .srodata.* .rodata .rodata.*)
+ *libzephyr.a:bootloader_flash_config_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_clock_loader.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:bootloader_panic.*(.rodata .rodata.* .srodata .srodata.*)
+
+ *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:clk.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:esp_clk.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:flash_mmap.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:flash_ops.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:flash_ops_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
+
+ *libzephyr.a:esp_gpio_reserve.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .srodata .srodata.*)
+ *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .srodata .srodata.*)
+
+ . = ALIGN(16);
+ _loader_data_end = ABSOLUTE(.);
+ } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+#endif /* CONFIG_ESP_SIMPLE_BOOT */
+
+ #include <snippets-data-sections.ld>
+ #include <zephyr/linker/common-ram.ld>
+ #include <snippets-ram-sections.ld>
+ #include <zephyr/linker/cplusplus-ram.ld>
+
+ /* logging sections should be placed in RAM area to avoid flash cache disabled issues */
+ #pragma push_macro("GROUP_ROM_LINK_IN")
+ #undef GROUP_ROM_LINK_IN
+ #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
+ #include <zephyr/linker/common-rom/common-rom-logging.ld>
+ #pragma pop_macro("GROUP_ROM_LINK_IN")
+
+ .dram0.end :
+ {
+ . = ALIGN(4);
+ _data_end = ABSOLUTE(.);
+ __data_end = ABSOLUTE(.);
+ } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+ .dram0.noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ *(.noinit)
+ *(.noinit.*)
+ . = ALIGN(4);
+ } GROUP_LINK_IN(RAMABLE_REGION)
+
+ /* Shared RAM */
+ .dram0.bss (NOLOAD) :
+ {
+ . = ALIGN (8);
+ __bss_start = ABSOLUTE(.);
+ _bss_start = ABSOLUTE(.);
+
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (16);
+ __bss_end = ABSOLUTE(.);
+ _bss_end = ABSOLUTE(.);
+ } GROUP_LINK_IN(RAMABLE_REGION)
+
+ /* Provide total SRAM usage, including IRAM and DRAM */
+ _image_ram_start = _iram_start - IRAM_DRAM_OFFSET;
+ #include <zephyr/linker/ram-end.ld>
+
+ ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
+
+ /* --- END OF DRAM --- */
+
+ /* --- START OF .flash.text --- */
+
+ .flash.text_dummy (NOLOAD):
+ {
+ . = ALIGN(CACHE_ALIGN);
+ } GROUP_LINK_IN(ROMABLE_REGION)
+
+ /* Symbols used during the application memory mapping */
+ _image_irom_start = LOADADDR(.flash.text);
+ _image_irom_size = SIZEOF(.flash.text);
+ _image_irom_vaddr = ADDR(.flash.text);
+
+ .flash.text : ALIGN(CACHE_ALIGN)
+ {
+ _stext = .;
+ _instruction_reserved_start = ABSOLUTE(.);
+ _text_start = ABSOLUTE(.);
+ _instruction_reserved_start = ABSOLUTE(.);
+ __text_region_start = ABSOLUTE(.);
+ __rom_region_start = ABSOLUTE(.);
+
+#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
+ *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
+ *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
+#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
+
+#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
+ *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
+ *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
+#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */
+
+ *(.literal .text .literal.* .text.*)
+ *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+
+ *(.fini.literal)
+ *(.fini)
+
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of
+ * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+ . += 16;
+
+ _instruction_reserved_end = ABSOLUTE(.);
+ _text_end = ABSOLUTE(.);
+ _instruction_reserved_end = ABSOLUTE(.);
+ __text_region_end = ABSOLUTE(.);
+ __rom_region_end = ABSOLUTE(.);
+ _etext = .;
+
+ } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
+
+ /* --- END OF .flash.text --- */
+
+ /* --- START OF .rodata --- */
+
+ /* Align next section to 64k to allow mapping */
+ .flash.dummy (NOLOAD) :
+ {
+ . = ALIGN(CACHE_ALIGN);
+ } GROUP_LINK_IN(ROMABLE_REGION)
+
+ .flash.rodata_dummy (NOLOAD) :
+ {
+ /* Spacer in the IROM address to avoid interfering with the DROM address
+ * because DROM and IROM regions share the same address space */
+ . += SIZEOF(.flash.text);
+ . = ALIGN(CACHE_ALIGN);
+ } GROUP_LINK_IN(RODATA_REGION)
+
+ /* Symbols used during the application memory mapping */
+ _image_drom_start = LOADADDR(.flash.rodata);
+ _image_drom_size = _image_rodata_end - _image_rodata_start;
+ _image_drom_vaddr = ADDR(.flash.rodata);
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _rodata_reserved_start = ABSOLUTE(.);
+ _image_rodata_start = ABSOLUTE(.);
+
+ *(.rodata_desc .rodata_desc.*)
+ *(.rodata_custom_desc .rodata_custom_desc.*)
+
+ __rodata_region_start = ABSOLUTE(.);
+
+ . = ALIGN(4);
+ #include <snippets-rodata.ld>
+
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table .gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ . = (. + 3) & ~ 3;
+ __eh_frame = ABSOLUTE(.);
+ KEEP(*(.eh_frame))
+ . = (. + 7) & ~ 3;
+
+ /* C++ exception handlers table: */
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ __rodata_region_end = ABSOLUTE(.);
+ _rodata_end = ABSOLUTE(.);
+ /* Literals are also RO data. */
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ *(.srodata)
+ *(.srodata.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata_wlog)
+ *(.rodata_wlog*)
+ . = ALIGN(4);
+ } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
+
+ #include <zephyr/linker/cplusplus-rom.ld>
+ #include <zephyr/linker/common-rom/common-rom-init.ld>
+ #include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
+ #include <zephyr/linker/common-rom/common-rom-ztest.ld>
+ #include <zephyr/linker/common-rom/common-rom-net.ld>
+ #include <zephyr/linker/common-rom/common-rom-bt.ld>
+ #include <zephyr/linker/common-rom/common-rom-debug.ld>
+ #include <zephyr/linker/common-rom/common-rom-misc.ld>
+ #include <zephyr/linker/thread-local-storage.ld>
+ #include <snippets-sections.ld>
+
+ /* Create an explicit section at the end of all the data that shall be mapped into drom.
+ * This is used to calculate the size of the _image_drom_size variable */
+ .flash.rodata_end : ALIGN(0x10)
+ {
+ . = ALIGN(4);
+
+#ifdef CONFIG_THREAD_LOCAL_STORAGE
+ /* create explicit symbol for __tdata_start so that it is loaded
+ * into proper DROM region atributted by AT keyword below
+ */
+ __tdata_start = ADDR(tdata);
+#endif
+
+ _rodata_reserved_end = ABSOLUTE(.);
+ _image_rodata_end = ABSOLUTE(.);
+ } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
+
+ /* --- END OF .rodata --- */
+
+#ifdef CONFIG_GEN_ISR_TABLES
+ #include <zephyr/linker/intlist.ld>
+#endif
+
+ #include <zephyr/linker/debug-sections.ld>
+ /DISCARD/ : { *(.note.GNU-stack) }
+
+ SECTION_PROLOGUE(.riscv.attributes, 0,)
+ {
+ KEEP(*(.riscv.attributes))
+ KEEP(*(.gnu.attributes))
+ }
+}
diff --git a/soc/espressif/esp32c2/mcuboot.ld b/soc/espressif/esp32c2/mcuboot.ld
new file mode 100644
index 0000000..4d66262
--- /dev/null
+++ b/soc/espressif/esp32c2/mcuboot.ld
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+
+#include "memory.h"
+
+#ifdef CONFIG_XIP
+#error "ESP32C2 bootloader cannot use XIP"
+#endif /* CONFIG_XIP */
+
+/* Disable all romable LMA */
+#udef GROUP_DATA_LINK_IN
+#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
+
+#define RAMABLE_REGION dram_seg
+#define RODATA_REGION dram_seg
+#define ROMABLE_REGION dram_seg
+
+/* Global symbols required for espressif hal build */
+MEMORY
+{
+ iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START,
+ len = BOOTLOADER_IRAM_SEG_LEN
+ iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START,
+ len = BOOTLOADER_IRAM_LOADER_SEG_LEN
+ dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START,
+ len = BOOTLOADER_DRAM_SEG_LEN
+
+#ifdef CONFIG_GEN_ISR_TABLES
+ IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
+#endif
+}
+
+/* Default entry point: */
+ENTRY(CONFIG_KERNEL_ENTRY)
+
+SECTIONS
+{
+ .iram0.loader_text :
+ {
+ . = ALIGN (16);
+ _loader_text_start = ABSOLUTE(.);
+ *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+
+ /* TODO: cross-segments calls in the libzephyr.a:device.* */
+
+ *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
+
+ *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
+
+ *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
+ *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
+
+ *(.literal.bootloader_mmap .text.bootloader_mmap)
+ *(.literal.bootloader_munmap .text.bootloader_munmap)
+
+ *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
+ *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
+
+ *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
+ *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
+ *(.literal.esp_log_timestamp .text.esp_log_timestamp)
+ *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
+ *(.literal.esp_system_abort .text.esp_system_abort)
+
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+ _loader_text_end = ABSOLUTE(.);
+ _iram_end = ABSOLUTE(.);
+ } > iram_loader_seg
+
+ .iram0.text :
+ {
+ /* Vectors go to IRAM */
+ _iram_start = ABSOLUTE(.);
+ _init_start = ABSOLUTE(.);
+ __text_region_start = ABSOLUTE(.);
+
+ KEEP(*(.exception_vectors.text));
+ . = ALIGN(256);
+
+ _invalid_pc_placeholder = ABSOLUTE(.);
+
+ _iram_text_start = ABSOLUTE(.);
+
+ KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
+ *(.exception.other*)
+ . = ALIGN(4);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ . = ALIGN(4);
+ *(.iram1 .iram1.*)
+ *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+
+ /* C2 memprot requires 512 B alignment for split lines */
+ . = ALIGN (16);
+ _init_end = ABSOLUTE(.);
+ . = ALIGN(16);
+ *(.iram.data)
+ *(.iram.data*)
+ . = ALIGN(16);
+ *(.iram.bss)
+ *(.iram.bss*)
+
+ . = ALIGN(16);
+
+ *(.literal .text .literal.* .text.*)
+ *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of
+ * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+ . += 16;
+
+ _text_end = ABSOLUTE(.);
+ __text_region_end = ABSOLUTE(.);
+ _etext = .;
+
+ /* Similar to _iram_start, this symbol goes here so it is
+ * resolved by addr2line in preference to the first symbol in
+ * the flash.text segment.
+ */
+ _flash_cache_start = ABSOLUTE(0);
+ } > iram_seg
+
+ .dram0.data :
+ {
+ . = ALIGN(4);
+ __data_start = ABSOLUTE(.);
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.data1)
+#ifdef CONFIG_RISCV_GP
+ __global_pointer$ = . + 0x800;
+#endif /* CONFIG_RISCV_GP */
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
+ *libzephyr.a:rtc_clk.*(.rodata .rodata.*)
+ KEEP(*(.jcr))
+ *(.dram1 .dram1.*)
+ . = ALIGN(4);
+
+ #include <snippets-rwdata.ld>
+ . = ALIGN(4);
+
+ *(.rodata_desc .rodata_desc.*)
+ *(.rodata_custom_desc .rodata_custom_desc.*)
+
+ . = ALIGN(4);
+ #include <snippets-rodata.ld>
+ . = ALIGN(4);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table .gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ . = (. + 3) & ~ 3;
+ __eh_frame = ABSOLUTE(.);
+ KEEP(*(.eh_frame))
+ . = (. + 7) & ~ 3;
+
+ /* C++ exception handlers table: */
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ __rodata_region_end = .;
+ _rodata_end = ABSOLUTE(.);
+ /* Literals are also RO data. */
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ _thread_local_start = ABSOLUTE(.);
+ *(.tdata)
+ *(.tdata.*)
+ *(.tbss)
+ *(.tbss.*)
+ *(.srodata)
+ *(.srodata.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata_wlog)
+ *(.rodata_wlog*)
+ _thread_local_end = ABSOLUTE(.);
+ /* _rodata_reserved_end = ABSOLUTE(.); */
+ . = ALIGN(4);
+ } > dram_seg
+
+ #include <zephyr/linker/common-rom/common-rom-init.ld>
+ #include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
+ #include <zephyr/linker/common-rom/common-rom-debug.ld>
+ #include <zephyr/linker/common-rom/common-rom-misc.ld>
+ #include <snippets-sections.ld>
+
+ #include <zephyr/linker/cplusplus-rom.ld>
+ #include <zephyr/linker/thread-local-storage.ld>
+ #include <snippets-data-sections.ld>
+ #include <zephyr/linker/common-ram.ld>
+ #include <snippets-ram-sections.ld>
+ #include <zephyr/linker/cplusplus-ram.ld>
+
+ #include <zephyr/linker/common-rom/common-rom-logging.ld>
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ *(.noinit)
+ *(.noinit.*)
+ . = ALIGN(4);
+ } > dram_seg
+
+ /* Shared RAM */
+ .bss (NOLOAD):
+ {
+ . = ALIGN (8);
+ _bss_start = ABSOLUTE(.);
+ __bss_start = ABSOLUTE(.);
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ __bss_end = ABSOLUTE(.);
+ _bss_end = ABSOLUTE(.);
+ } > dram_seg
+
+ /* linker rel sections*/
+ #include <zephyr/linker/rel-sections.ld>
+
+#ifdef CONFIG_GEN_ISR_TABLES
+ #include <zephyr/linker/intlist.ld>
+#endif
+
+#include <zephyr/linker/debug-sections.ld>
+ /DISCARD/ : { *(.note.GNU-stack) }
+
+ SECTION_PROLOGUE(.riscv.attributes, 0,)
+ {
+ KEEP(*(.riscv.attributes))
+ KEEP(*(.gnu.attributes))
+ }
+}
diff --git a/soc/espressif/esp32c2/memory.h b/soc/espressif/esp32c2/memory.h
new file mode 100644
index 0000000..2ff5637
--- /dev/null
+++ b/soc/espressif/esp32c2/memory.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+/* SRAM0 (16kB) memory */
+#define SRAM0_IRAM_START 0x4037c000
+#define SRAM0_SIZE 0x4000
+/* SRAM1 (256kB) memory */
+#define SRAM1_DRAM_START 0x3fca0000
+#define SRAM1_IRAM_START 0x40380000
+/* ICache size is fixed to 16KB on ESP32-C2 */
+#define ICACHE_SIZE SRAM0_SIZE
+
+/** Simplified memory map for the bootloader.
+ * Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ * ESP32-C2 ROM static data usage is as follows:
+ * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
+ * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
+ *
+ * The 2nd stage bootloader can take space up to the end of ROM shared
+ * buffers area (0x3fcdc710).
+ */
+
+/* The offset between Dbus and Ibus.
+ * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
+ */
+#define IRAM_DRAM_OFFSET SRAM1_IRAM_START - SRAM1_DRAM_START
+#define DRAM_BUFFERS_START 0x3fccae00
+#define DRAM_STACK_START 0x3fcdc710
+#define DRAM_ROM_BSS_DATA_START 0x3fcde710
+
+/* Base address used for calculating memory layout
+ * counted from Dbus backwards and back to the Ibus
+ */
+#define BOOTLOADER_USER_DRAM_END DRAM_BUFFERS_START
+
+/* For safety margin between bootloader data section and startup stacks */
+#define BOOTLOADER_STACK_OVERHEAD 0x0
+/* These lengths can be adjusted, if necessary: */
+#define BOOTLOADER_DRAM_SEG_LEN 0x9800
+#define BOOTLOADER_IRAM_SEG_LEN 0x9800
+#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+#define BOOTLOADER_IRAM_LOADER_SEG_END (BOOTLOADER_USER_DRAM_END + \
+ BOOTLOADER_STACK_OVERHEAD + IRAM_DRAM_OFFSET)
+#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_END - \
+ BOOTLOADER_IRAM_LOADER_SEG_LEN)
+#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
+#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET - \
+ BOOTLOADER_DRAM_SEG_LEN)
+
+/* Flash */
+#ifdef CONFIG_FLASH_SIZE
+#define FLASH_SIZE CONFIG_FLASH_SIZE
+#else
+#define FLASH_SIZE 0x400000
+#endif
+
+/* Cached memory */
+#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
+#define IROM_SEG_ORG 0x42000000
+#define IROM_SEG_LEN FLASH_SIZE
+#define DROM_SEG_ORG 0x3c000000
+#define DROM_SEG_LEN FLASH_SIZE
diff --git a/soc/espressif/esp32c2/pinctrl_soc.h b/soc/espressif/esp32c2/pinctrl_soc.h
new file mode 100644
index 0000000..17b4905
--- /dev/null
+++ b/soc/espressif/esp32c2/pinctrl_soc.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * ESP32C2 SoC specific helpers for pinctrl driver
+ */
+
+#ifndef ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+
+/** @cond INTERNAL_HIDDEN */
+
+/** Type for ESP32 pin. */
+typedef struct pinctrl_soc_pin {
+ /** Pinmux settings (pin, direction and signal). */
+ uint32_t pinmux;
+ /** Pincfg settings (bias). */
+ uint32_t pincfg;
+} pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
+ *
+ * @param node_id Node identifier.
+ */
+#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
+
+/**
+ * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
+ *
+ * @param node_id Node identifier.
+ */
+#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
+ (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
+ ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
+ ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
+ ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
+ ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
+ ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
+ ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
+ ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
+ ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
+ {.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
+ .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
+ { \
+ DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
+ Z_PINCTRL_STATE_PIN_INIT) \
+ }
+
+/** @endcond */
+
+#endif /* ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_ */
diff --git a/soc/espressif/esp32c2/soc.c b/soc/espressif/esp32c2/soc.c
new file mode 100644
index 0000000..c1cc3e3
--- /dev/null
+++ b/soc/espressif/esp32c2/soc.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Include esp-idf headers first to avoid redefining BIT() macro */
+#include <soc/rtc_cntl_reg.h>
+#include <soc/timer_group_reg.h>
+#include <soc/ext_mem_defs.h>
+#include <soc/gpio_reg.h>
+#include <soc/syscon_reg.h>
+#include <soc/system_reg.h>
+#include "hal/wdt_hal.h"
+#include "esp_cpu.h"
+#include "hal/soc_hal.h"
+#include "hal/cpu_hal.h"
+#include "esp_timer.h"
+#include "esp_private/system_internal.h"
+#include "esp_clk_internal.h"
+#include <soc/interrupt_reg.h>
+#include <esp_private/spi_flash_os.h>
+#include "esp_private/esp_mmu_map_private.h"
+
+#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+
+#include <zephyr/kernel_structs.h>
+#include <kernel_internal.h>
+#include <string.h>
+#include <zephyr/toolchain.h>
+#include <soc.h>
+
+extern void esp_reset_reason_init(void);
+
+/*
+ * This is written in C rather than assembly since, during the port bring up,
+ * Zephyr is being booted by the Espressif bootloader. With it, the C stack
+ * is already set up.
+ */
+void __attribute__((section(".iram1"))) __esp_platform_start(void)
+{
+ __asm__ __volatile__("la t0, _esp32c2_vector_table\n"
+ "csrw mtvec, t0\n");
+
+ z_bss_zero();
+
+ /* Disable normal interrupts. */
+ csr_read_clear(mstatus, MSTATUS_MIE);
+
+ esp_reset_reason_init();
+
+#ifndef CONFIG_MCUBOOT
+ /* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
+ * related issues in application. Hence disable that as we are about to start
+ * Zephyr environment.
+ */
+ wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+
+ wdt_hal_write_protect_disable(&rtc_wdt_ctx);
+ wdt_hal_disable(&rtc_wdt_ctx);
+ wdt_hal_write_protect_enable(&rtc_wdt_ctx);
+
+ /* Enable wireless phy subsystem clock,
+ * This needs to be done before the kernel starts
+ */
+ REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
+ SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
+
+#ifdef CONFIG_SOC_FLASH_ESP32
+ esp_mspi_pin_init();
+
+ /**
+ * This function initialise the Flash chip to the user-defined settings.
+ *
+ * In bootloader, we only init Flash (and MSPI) to a preliminary
+ * state, for being flexible to different chips.
+ * In this stage, we re-configure the Flash (and MSPI) to required configuration
+ */
+ spi_flash_init_chip_state();
+
+ esp_mmu_map_init();
+
+#endif /*CONFIG_SOC_FLASH_ESP32*/
+
+ esp_timer_early_init();
+
+#if CONFIG_SOC_FLASH_ESP32
+ spi_flash_guard_set(&g_flash_guard_default_ops);
+#endif
+
+#endif /* !CONFIG_MCUBOOT */
+
+ /*Initialize the esp32c2 interrupt controller */
+ esp_intr_initialize();
+
+ /* Start Zephyr */
+ z_cstart();
+
+ CODE_UNREACHABLE;
+}
+
+/* Boot-time static default printk handler, possibly to be overridden later. */
+int IRAM_ATTR arch_printk_char_out(int c)
+{
+ if (c == '\n') {
+ esp_rom_uart_tx_one_char('\r');
+ }
+ esp_rom_uart_tx_one_char(c);
+ return 0;
+}
+
+void sys_arch_reboot(int type)
+{
+ esp_restart_noos();
+}
diff --git a/soc/espressif/esp32c2/soc.h b/soc/espressif/esp32c2/soc.h
new file mode 100644
index 0000000..da96d9f
--- /dev/null
+++ b/soc/espressif/esp32c2/soc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#ifndef _ASMLANGUAGE
+#include <soc/soc.h>
+#include <rom/ets_sys.h>
+#include <rom/spi_flash.h>
+#include <zephyr/types.h>
+#include <stdbool.h>
+#include <esp_private/esp_clk.h>
+#endif
+
+#ifndef _ASMLANGUAGE
+
+void __esp_platform_start(void);
+
+static inline uint32_t esp_core_id(void)
+{
+ return 0;
+}
+
+extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+extern void esp_rom_uart_attach(void);
+extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
+extern int esp_rom_uart_tx_one_char(uint8_t chr);
+extern int esp_rom_uart_rx_one_char(uint8_t *chr);
+extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted);
+extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
+ bool out_invrted, bool out_enabled_inverted);
+extern void esp_rom_ets_set_user_start(uint32_t start);
+extern void esprv_intc_int_set_threshold(int priority_threshold);
+uint32_t soc_intr_get_next_source(void);
+extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
+extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
+extern uint32_t esp_rom_Cache_Suspend_ICache(void);
+extern void esp_rom_Cache_Invalidate_ICache_All(void);
+extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
+ uint32_t psize, uint32_t num, uint32_t fixed);
+extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
+ uint32_t psize, uint32_t num, uint32_t fixed);
+extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
+extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
+ bool inverted);
+extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
+ bool out_inverted,
+ bool out_enabled_inverted);
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* __SOC_H__ */
diff --git a/soc/espressif/esp32c2/soc_irq.S b/soc/espressif/esp32c2/soc_irq.S
new file mode 100644
index 0000000..b970b84
--- /dev/null
+++ b/soc/espressif/esp32c2/soc_irq.S
@@ -0,0 +1,20 @@
+/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/offsets.h>
+#include <zephyr/toolchain.h>
+
+/* Exports */
+GTEXT(__soc_handle_irq)
+GTEXT(soc_intr_get_next_source)
+
+SECTION_FUNC(exception.other, __soc_handle_irq)
+ addi sp, sp,-4
+ sw ra, 0x00(sp)
+ la t1, soc_intr_get_next_source
+ jalr ra, t1, 0
+ lw ra, 0x00(sp)
+ addi sp, sp, 4
+ ret
diff --git a/soc/espressif/esp32c2/soc_irq.c b/soc/espressif/esp32c2/soc_irq.c
new file mode 100644
index 0000000..713dfc9
--- /dev/null
+++ b/soc/espressif/esp32c2/soc_irq.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc/rtc_cntl_reg.h>
+#include <soc/timer_group_reg.h>
+#include <soc/ext_mem_defs.h>
+#include <soc/gpio_reg.h>
+#include <soc/syscon_reg.h>
+#include <soc/system_reg.h>
+#include <riscv/interrupt.h>
+#include <soc/interrupt_reg.h>
+#include <soc/periph_defs.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+
+#include <zephyr/kernel_structs.h>
+#include <string.h>
+#include <zephyr/toolchain.h>
+#include <soc.h>
+#include <zephyr/arch/riscv/arch.h>
+
+#define ESP32C2_INTSTATUS_SLOT1_THRESHOLD 32
+
+void arch_irq_enable(unsigned int irq)
+{
+ esp_intr_enable(irq);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+ esp_intr_disable(irq);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+ bool res = false;
+ uint32_t key = irq_lock();
+
+ if (irq < 32) {
+ res = esp_intr_get_enabled_intmask(0) & BIT(irq);
+ } else {
+ res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
+ }
+
+ irq_unlock(key);
+
+ return res;
+}
+
+uint32_t soc_intr_get_next_source(void)
+{
+ uint32_t status;
+ uint32_t source;
+
+ status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) &
+ esp_intr_get_enabled_intmask(0);
+
+ if (status) {
+ source = __builtin_ffs(status) - 1;
+ } else {
+ status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) &
+ esp_intr_get_enabled_intmask(1);
+ source = (__builtin_ffs(status) - 1 + ESP32C2_INTSTATUS_SLOT1_THRESHOLD);
+ }
+
+ return source;
+}
diff --git a/soc/espressif/esp32c2/vectors.S b/soc/espressif/esp32c2/vectors.S
new file mode 100644
index 0000000..e8f8f02
--- /dev/null
+++ b/soc/espressif/esp32c2/vectors.S
@@ -0,0 +1,35 @@
+/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc.h"
+#include "soc/interrupt_reg.h"
+#include "riscv/rvruntime-frames.h"
+#include "soc/soc_caps.h"
+#include <zephyr/toolchain.h>
+
+/* Imports */
+GTEXT(_isr_wrapper)
+
+ /* This is the vector table. MTVEC points here.
+ *
+ * Use 4-byte intructions here. 1 instruction = 1 entry of the table.
+ * The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
+ * and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
+ *
+ * Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
+ * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
+ */
+
+ .global _esp32c2_vector_table
+ .section .exception_vectors.text
+ .balign 0x100
+ .type _esp32c2_vector_table, @function
+
+_esp32c2_vector_table:
+ .option push
+ .option norvc
+ .rept (32)
+ j _isr_wrapper /* 32 identical entries, all pointing to the interrupt handler */
+ .endr
diff --git a/soc/espressif/esp32c6/Kconfig b/soc/espressif/esp32c6/Kconfig
index 0bb4aa5..c33528a 100644
--- a/soc/espressif/esp32c6/Kconfig
+++ b/soc/espressif/esp32c6/Kconfig
@@ -14,6 +14,8 @@
select RISCV_ISA_EXT_ZICSR
select HAS_ESPRESSIF_HAL
select XIP if !MCUBOOT
+ select HAS_PM
+ select HAS_POWEROFF
if SOC_SERIES_ESP32C6
diff --git a/soc/espressif/esp32c6/power.c b/soc/espressif/esp32c6/power.c
new file mode 100644
index 0000000..b3d9782
--- /dev/null
+++ b/soc/espressif/esp32c6/power.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/pm/pm.h>
+#include <zephyr/irq.h>
+#include <esp_sleep.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Invoke Low Power/System Off specific Tasks */
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+ ARG_UNUSED(substate_id);
+
+ switch (state) {
+ case PM_STATE_STANDBY:
+ /* Nothing to do. */
+ break;
+ default:
+ LOG_DBG("Unsupported power state %u", state);
+ break;
+ }
+}
+
+/* Handle SOC specific activity after Low Power Mode Exit */
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+ ARG_UNUSED(substate_id);
+
+ switch (state) {
+ case PM_STATE_STANDBY:
+ irq_unlock(MSTATUS_IEN);
+ __asm__ volatile("wfi");
+ esp_light_sleep_start();
+ break;
+ default:
+ LOG_DBG("Unsupported power state %u", state);
+ break;
+ }
+}
diff --git a/soc/espressif/esp32c6/poweroff.c b/soc/espressif/esp32c6/poweroff.c
new file mode 100644
index 0000000..9889ff5
--- /dev/null
+++ b/soc/espressif/esp32c6/poweroff.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/poweroff.h>
+
+#include <esp_sleep.h>
+
+void z_sys_poweroff(void)
+{
+ /* Forces RTC domain to be always on */
+ esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+ esp_deep_sleep_start();
+}
diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c
index 1911304..a3d0170 100644
--- a/soc/espressif/esp32s2/soc.c
+++ b/soc/espressif/esp32s2/soc.c
@@ -36,6 +36,9 @@
#include <esp_err.h>
#include <esp_clk_internal.h>
#include <zephyr/sys/printk.h>
+#include "esp_log.h"
+
+#define TAG "boot.esp32s2"
extern void rtc_clk_cpu_freq_set_xtal(void);
extern void esp_reset_reason_init(void);
@@ -110,17 +113,17 @@
esp_err_t err = esp_psram_init();
if (err != ESP_OK) {
- printk("Failed to Initialize SPIRAM, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "Failed to Initialize SPIRAM, aborting.");
abort();
}
if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
- printk("SPIRAM size is less than configured size, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "SPIRAM size is less than configured size, aborting.");
abort();
}
if (esp_psram_is_initialized()) {
if (!esp_psram_extram_test()) {
- printk("External RAM failed memory test!");
+ ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
abort();
}
}
diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c
index 7cf39b3..2c45f2e 100644
--- a/soc/espressif/esp32s3/soc.c
+++ b/soc/espressif/esp32s3/soc.c
@@ -46,6 +46,9 @@
#include <esp_app_format.h>
#include <zephyr/sys/printk.h>
+#include "esp_log.h"
+
+#define TAG "boot.esp32s3"
#if CONFIG_ESP_SPIRAM
extern int _ext_ram_bss_start;
@@ -161,18 +164,18 @@
esp_err_t err = esp_psram_init();
if (err != ESP_OK) {
- printk("Failed to Initialize external RAM, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "Failed to Initialize external RAM, aborting.");
abort();
}
if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
- printk("External RAM size is less than configured, aborting.\n");
+ ESP_EARLY_LOGE(TAG, "External RAM size is less than configured, aborting.");
abort();
}
if (esp_psram_is_initialized()) {
if (!esp_psram_extram_test()) {
- printk("External RAM failed memory test!");
+ ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
abort();
}
}
diff --git a/soc/espressif/soc.yml b/soc/espressif/soc.yml
index c553b3e..1ec21c8 100644
--- a/soc/espressif/soc.yml
+++ b/soc/espressif/soc.yml
@@ -16,6 +16,9 @@
cpuclusters:
- name: procpu
- name: appcpu
+ - name: esp32c2
+ socs:
+ - name: esp32c2
- name: esp32c3
socs:
- name: esp32c3
diff --git a/soc/intel/intel_adsp/Kconfig.defconfig b/soc/intel/intel_adsp/Kconfig.defconfig
index d76faf0..5a2ff34 100644
--- a/soc/intel/intel_adsp/Kconfig.defconfig
+++ b/soc/intel/intel_adsp/Kconfig.defconfig
@@ -48,4 +48,7 @@
default ARCH_CACHE
endchoice
+config DCACHE_LINE_SIZE
+ default 64
+
endif # SOC_FAMILY_INTEL_ADSP
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
index c9c536f..447cc60 100644
--- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
+++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
@@ -6,4 +6,11 @@
config MP_MAX_NUM_CPUS
default 3
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 393216000 if XTENSA_TIMER
+ default 38400000 if INTEL_ADSP_TIMER
+
+config XTENSA_CCOUNT_HZ
+ default 393216000
+
endif
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl
index 2a70da4..2c7defc 100644
--- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl
+++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl
@@ -6,4 +6,11 @@
config MP_MAX_NUM_CPUS
default 5
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 393216000 if XTENSA_TIMER
+ default 38400000 if INTEL_ADSP_TIMER
+
+config XTENSA_CCOUNT_HZ
+ default 393216000
+
endif
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl
index f7e0f19..9bb3d2e 100644
--- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl
+++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl
@@ -7,6 +7,13 @@
config MP_MAX_NUM_CPUS
default 5
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 442368000 if XTENSA_TIMER
+ default 38400000 if INTEL_ADSP_TIMER
+
+config XTENSA_CCOUNT_HZ
+ default 442368000
+
config CPU_HAS_MMU
def_bool y
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
index e96c890..eddd5ea 100644
--- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
+++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
@@ -40,16 +40,9 @@
config XTENSA_TIMER_ID
default 0
-config SYS_CLOCK_HW_CYCLES_PER_SEC
- default 393216000 if XTENSA_TIMER
- default 38400000 if INTEL_ADSP_TIMER
-
config SYS_CLOCK_TICKS_PER_SEC
default 12000
-config XTENSA_CCOUNT_HZ
- default 393216000
-
config INTEL_ADSP_TIMER
default y
diff --git a/soc/intel/intel_adsp/ace/comm_widget_messages.c b/soc/intel/intel_adsp/ace/comm_widget_messages.c
index be33fb5..50465ca 100644
--- a/soc/intel/intel_adsp/ace/comm_widget_messages.c
+++ b/soc/intel/intel_adsp/ace/comm_widget_messages.c
@@ -16,8 +16,9 @@
*/
int adsp_comm_widget_pmc_send_ipc(uint16_t banks)
{
- if (!cw_upstream_ready())
+ if (!cw_upstream_ready()) {
return -EBUSY;
+ }
uint32_t iface = FIELD_PREP(CW_PMC_IPC_OP_CODE, CW_PMC_OPC_SRAM_CONFIG) |
FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) |
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h
index e28e6f3..7f4aad7 100644
--- a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h
+++ b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h
@@ -106,6 +106,9 @@
#define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
+#define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0)
+#define ACE_CRODIV_CARCDS(x) ((x) & ACE_CRODIV_CARCDS_MASK)
+
#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c
index 43bbca3..9319160 100644
--- a/soc/intel/intel_adsp/ace/power.c
+++ b/soc/intel/intel_adsp/ace/power.c
@@ -43,7 +43,7 @@
#if CONFIG_SOC_INTEL_ACE15_MTPM
*((__sparse_force uint32_t *)sys_cache_cached_ptr_get(&adsp_pending_buffer)) =
INTEL_ADSP_ACE15_MAGIC_KEY;
- cache_data_flush_range((__sparse_force void *)
+ sys_cache_data_flush_range((__sparse_force void *)
sys_cache_cached_ptr_get(&adsp_pending_buffer),
sizeof(adsp_pending_buffer));
#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */
diff --git a/soc/intel/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c
index f9a35a3..3cb4b0e 100644
--- a/soc/intel/intel_adsp/common/clk.c
+++ b/soc/intel/intel_adsp/common/clk.c
@@ -96,6 +96,11 @@
} else {
platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
}
+#if CONFIG_SOC_INTEL_ACE30_PTL
+ /* Set the Cardinal clock divider to 18 to get 24.576MHz */
+ ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK;
+ ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12);
+#endif
#else
CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO;
if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO) {
diff --git a/soc/intel/intel_adsp/common/include/soc_util.h b/soc/intel/intel_adsp/common/include/soc_util.h
index 19d9a4c..9de2efb 100644
--- a/soc/intel/intel_adsp/common/include/soc_util.h
+++ b/soc/intel/intel_adsp/common/include/soc_util.h
@@ -15,8 +15,9 @@
volatile uint32_t *s = (uint32_t *)src;
sys_cache_data_invd_range(src, bytes);
- for (size_t i = 0; i < (bytes >> 2); i++)
+ for (size_t i = 0; i < (bytes >> 2); i++) {
d[i] = s[i];
+ }
sys_cache_data_flush_range(dest, bytes);
}
@@ -26,8 +27,9 @@
{
volatile uint32_t *d = (uint32_t *)dest;
- for (size_t i = 0; i < (bytes >> 2); i++)
+ for (size_t i = 0; i < (bytes >> 2); i++) {
d[i] = 0;
+ }
sys_cache_data_flush_range(dest, bytes);
}
diff --git a/soc/litex/litex_vexriscv/soc.h b/soc/litex/litex_vexriscv/soc.h
index 4334be4..060110b 100644
--- a/soc/litex/litex_vexriscv/soc.h
+++ b/soc/litex/litex_vexriscv/soc.h
@@ -103,6 +103,27 @@
#endif
}
+static inline void litex_write64(uint64_t value, unsigned long addr)
+{
+#if CONFIG_LITEX_CSR_DATA_WIDTH == 8
+ sys_write8(value >> 56, addr);
+ sys_write8(value >> 48, addr + 0x4);
+ sys_write8(value >> 40, addr + 0x8);
+ sys_write8(value >> 32, addr + 0xC);
+ sys_write8(value >> 24, addr + 0x10);
+ sys_write8(value >> 16, addr + 0x14);
+ sys_write8(value >> 8, addr + 0x18);
+ sys_write8(value, addr + 0x1C);
+#elif CONFIG_LITEX_CSR_DATA_WIDTH == 32
+ sys_write32(value >> 32, addr);
+ sys_write32(value, addr + 0x4);
+#elif CONFIG_LITEX_CSR_DATA_WIDTH >= 64
+ sys_write64(value, addr);
+#else
+#error Unsupported CSR data width
+#endif
+}
+
/*
* Operates on uint32_t values only
* Size is in bytes and meaningful are 1, 2 or 4
diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig
index fc42c43..c26aaf7 100644
--- a/soc/nordic/Kconfig
+++ b/soc/nordic/Kconfig
@@ -18,6 +18,7 @@
config NRF_SOC_SECURE_SUPPORTED
def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM)
depends on !SOC_SERIES_NRF54HX
+ depends on !SOC_SERIES_NRF92X
help
Hidden function to indicate that the soc_secure functions are
available.
@@ -170,4 +171,11 @@
Unit) for tracing using a hardware probe. If disabled, the trace
pins will be used as GPIO.
+config NRF_PLATFORM_HALTIUM
+ bool
+ help
+ SoC series based on the Nordic nRF Haltium platform need to select
+ this option. This allows to easily enable common functionality on
+ SoCs based on the Haltium platform.
+
endif # SOC_FAMILY_NORDIC_NRF
diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig
index 5e7e9c5..0ac3c5e 100644
--- a/soc/nordic/Kconfig.defconfig
+++ b/soc/nordic/Kconfig.defconfig
@@ -11,7 +11,7 @@
if SYS_CLOCK_EXISTS
config CLOCK_CONTROL
- default y if !SOC_SERIES_NRF54HX
+ default y if (!SOC_SERIES_NRF54HX && !SOC_SERIES_NRF92X)
endif # SYS_CLOCK_EXISTS
diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc
index 2e47fcb..6851c25 100644
--- a/soc/nordic/Kconfig.soc
+++ b/soc/nordic/Kconfig.soc
@@ -14,6 +14,7 @@
default "nrf54h" if SOC_SERIES_NRF54HX
default "nrf54l" if SOC_SERIES_NRF54LX
default "nrf91" if SOC_SERIES_NRF91X
+ default "nrf92" if SOC_SERIES_NRF92X
config SOC_FAMILY_NORDIC_NRF
bool
@@ -56,4 +57,10 @@
help
Enable support for NRF91 MCU series
+config SOC_SERIES_NRF92X
+ bool
+ select SOC_FAMILY_NORDIC_NRF
+ help
+ Enable support for NRF92 MCU series
+
rsource "*/Kconfig.soc"
diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt
index 513a3a9..37f27e2 100644
--- a/soc/nordic/common/CMakeLists.txt
+++ b/soc/nordic/common/CMakeLists.txt
@@ -13,6 +13,10 @@
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+if((CONFIG_SOC_SERIES_NRF54HX OR CONFIG_SOC_SERIES_NRF92X) AND CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS)
+ zephyr_library_sources(nrf54hx_nrf92x_mpu_regions.c)
+endif()
+
zephyr_include_directories(.)
if(CONFIG_HAS_NORDIC_DMM)
diff --git a/soc/nordic/common/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals
index a6d7308..2e77e7b 100644
--- a/soc/nordic/common/Kconfig.peripherals
+++ b/soc/nordic/common/Kconfig.peripherals
@@ -102,9 +102,6 @@
config HAS_HW_NRF_I2S20
def_bool $(dt_nodelabel_enabled_with_compat,i2s20,$(DT_COMPAT_NORDIC_NRF_I2S))
-config HAS_HW_NRF_IPC
- def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_IPC))
-
config HAS_HW_NRF_KMU
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_KMU))
diff --git a/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
new file mode 100644
index 0000000..6665958
--- /dev/null
+++ b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+#define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
+#define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
+
+#define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram)
+#define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \
+ DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can)
+
+#define CAN121_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can121), message_ram)
+#define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \
+ DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can)
+
+static struct arm_mpu_region mpu_regions[] = {
+ MPU_REGION_ENTRY("FLASH_0",
+ CONFIG_FLASH_BASE_ADDRESS,
+ REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS,
+ CONFIG_FLASH_SIZE * 1024)),
+ MPU_REGION_ENTRY("SRAM_0",
+ CONFIG_SRAM_BASE_ADDRESS,
+ REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS,
+ CONFIG_SRAM_SIZE * 1024)),
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usbhs), okay)
+ MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
+ REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
+#endif
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(can120), okay)
+ MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE,
+ REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)),
+#endif
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(can121), okay)
+ MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE,
+ REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)),
+#endif
+};
+
+const struct arm_mpu_config mpu_config = {
+ .num_regions = ARRAY_SIZE(mpu_regions),
+ .mpu_regions = mpu_regions,
+};
diff --git a/soc/nordic/common/vpr/Kconfig.sysbuild b/soc/nordic/common/vpr/Kconfig.sysbuild
index 5266613..4fd5f25 100644
--- a/soc/nordic/common/vpr/Kconfig.sysbuild
+++ b/soc/nordic/common/vpr/Kconfig.sysbuild
@@ -4,7 +4,7 @@
config VPR_LAUNCHER
bool "VPR launcher"
default y
- depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_ENGA_CPUFLPR)
+ depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_ENGA_CPUFLPR || SOC_NRF9280_CPUPPR)
help
Include VPR launcher in build.
VPR launcher is a minimal sample built for an ARM core that starts given VPR core.
diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt
index 88e45de..1aa4723 100644
--- a/soc/nordic/nrf54h/CMakeLists.txt
+++ b/soc/nordic/nrf54h/CMakeLists.txt
@@ -5,8 +5,6 @@
zephyr_library_sources(soc.c)
endif()
-zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c)
-
zephyr_include_directories(.)
# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig
index a4995f5..ac2e913 100644
--- a/soc/nordic/nrf54h/Kconfig
+++ b/soc/nordic/nrf54h/Kconfig
@@ -7,6 +7,7 @@
select HAS_NRFS
select HAS_NRFX
select HAS_NORDIC_DRIVERS
+ select NRF_PLATFORM_HALTIUM
config SOC_NRF54H20_CPUAPP
select ARM
diff --git a/soc/nordic/nrf54h/mpu_regions.c b/soc/nordic/nrf54h/mpu_regions.c
deleted file mode 100644
index a86161f..0000000
--- a/soc/nordic/nrf54h/mpu_regions.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/devicetree.h>
-#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
-
-#define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
-#define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
-
-#define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram)
-#define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \
- DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can)
-
-static struct arm_mpu_region mpu_regions[] = {
- MPU_REGION_ENTRY("FLASH_0",
- CONFIG_FLASH_BASE_ADDRESS,
- REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS,
- CONFIG_FLASH_SIZE * 1024)),
- MPU_REGION_ENTRY("SRAM_0",
- CONFIG_SRAM_BASE_ADDRESS,
- REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS,
- CONFIG_SRAM_SIZE * 1024)),
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(usbhs), okay)
- MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
- REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(can120), okay)
- MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE,
- REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)),
-#endif
-};
-
-const struct arm_mpu_config mpu_config = {
- .num_regions = ARRAY_SIZE(mpu_regions),
- .mpu_regions = mpu_regions,
-};
diff --git a/soc/nordic/nrf92/CMakeLists.txt b/soc/nordic/nrf92/CMakeLists.txt
new file mode 100644
index 0000000..1aa4723
--- /dev/null
+++ b/soc/nordic/nrf92/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_ARM)
+ zephyr_library_sources(soc.c)
+endif()
+
+zephyr_include_directories(.)
+
+# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
+# for the image correctly
+zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
diff --git a/soc/nordic/nrf92/Kconfig b/soc/nordic/nrf92/Kconfig
new file mode 100644
index 0000000..c3dd3a3
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig
@@ -0,0 +1,47 @@
+# Nordic Semiconductor nRF92 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NRF92X
+ select HAS_NRFS
+ select HAS_NRFX
+ select HAS_NORDIC_DRIVERS
+ select NRF_PLATFORM_HALTIUM
+
+config SOC_NRF9230_ENGB_CPUAPP
+ select ARM
+ select ARMV8_M_DSP
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_ARM_SAU
+ select CPU_HAS_DCACHE
+ select CPU_HAS_ICACHE
+ select CPU_HAS_FPU
+ select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+ select HAS_NORDIC_DMM
+ select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+ select NRFS_HAS_CLOCK_SERVICE
+ select NRFS_HAS_DVFS_SERVICE
+ select NRFS_HAS_MRAM_SERVICE
+ select NRFS_HAS_TEMP_SERVICE
+ select NRFS_HAS_VBUS_DETECTOR_SERVICE
+
+config SOC_NRF9230_ENGB_CPURAD
+ select ARM
+ select ARMV8_M_DSP
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_ARM_SAU
+ select CPU_HAS_DCACHE
+ select CPU_HAS_ICACHE
+ select CPU_HAS_FPU
+ select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+ select HAS_NORDIC_DMM
+ select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+ select NRFS_HAS_CLOCK_SERVICE
+ select NRFS_HAS_MRAM_SERVICE
+ select NRFS_HAS_TEMP_SERVICE
+
+config SOC_NRF9230_ENGB_CPUPPR
+ depends on RISCV_CORE_NORDIC_VPR
diff --git a/soc/nordic/nrf92/Kconfig.defconfig b/soc/nordic/nrf92/Kconfig.defconfig
new file mode 100644
index 0000000..5d1b638
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig.defconfig
@@ -0,0 +1,41 @@
+# Nordic Semiconductor nRF92 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NRF92X
+
+rsource "Kconfig.defconfig.nrf92*"
+
+if ARM
+
+config CACHE_NRF_CACHE
+ default y if EXTERNAL_CACHE
+
+endif # ARM
+
+if RISCV
+
+DT_CHOSEN_Z_SRAM = zephyr,sram
+DT_CHOSEN_Z_CODE = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+ depends on !XIP
+ default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \
+ $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))"
+
+config BUILD_OUTPUT_HEX
+ default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 1000000 if NRF_GRTC_TIMER
+
+endif # RISCV
+
+config SPI_DW_HSSI
+ default y if SPI_DW
+
+config SPI_DW_ACCESS_WORD_ONLY
+ default y if SPI_DW
+
+endif # SOC_SERIES_NRF92X
diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp
new file mode 100644
index 0000000..350f44b
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp
@@ -0,0 +1,14 @@
+# Nordic Semiconductor nRF9280 Application MCU
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPUAPP
+
+config NUM_IRQS
+ default 471
+
+config NRF_REGTOOL_GENERATE_UICR
+ default y
+
+endif # SOC_NRF9280_CPUAPP
diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr
new file mode 100644
index 0000000..9c29f6d
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPUPPR
+
+config NUM_IRQS
+ default 496
+
+config SYS_CLOCK_TICKS_PER_SEC
+ default 1000
+
+endif # SOC_NRF9280_CPUPPR
diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad
new file mode 100644
index 0000000..9b17a6b
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad
@@ -0,0 +1,14 @@
+# Nordic Semiconductor nRF9280 Radio MCU
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPURAD
+
+config NUM_IRQS
+ default 471
+
+config NRF_REGTOOL_GENERATE_UICR
+ default y
+
+endif # SOC_NRF9280_CPURAD
diff --git a/soc/nordic/nrf92/Kconfig.soc b/soc/nordic/nrf92/Kconfig.soc
new file mode 100644
index 0000000..99fc286
--- /dev/null
+++ b/soc/nordic/nrf92/Kconfig.soc
@@ -0,0 +1,66 @@
+# Nordic Semiconductor nRF9280 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Similarly to other nRF91 family products, the nRF9280 is a
+# SiP (System-in-Package) consisting of the nRF9230 SoC and
+# additional components such as PMIC and others.
+# Additionally, the nRF9230 contains several CPUs, similarly
+# to the nRF54h20 SoC.
+#
+# Like it's done for the nRF91 family, let the nRF9280 SiP
+# be represented by nRF9280 "SoC" in top-level SoC definitions
+# and user-configurable Kconfigs, since that's what visible to users.
+#
+# Keep a nRF9230 Kconfig for the SoC under the hood, complete with
+# the engineering version, because that's what the MDK/nrfx expects
+# as build target, and so that its definition can also be re-used
+# for other SiPs.
+
+config SOC_NRF9230_ENGB
+ bool
+ select SOC_SERIES_NRF92X
+
+config SOC_NRF9230_ENGB_CPUAPP
+ bool
+ select SOC_NRF9230_ENGB
+
+config SOC_NRF9230_ENGB_CPURAD
+ bool
+ select SOC_NRF9230_ENGB
+
+config SOC_NRF9230_ENGB_CPUPPR
+ bool
+ select SOC_NRF9230_ENGB
+
+# The SiP selects the actual SoC complete with engineer revision and appropriate CPU
+config SOC_NRF9280
+ bool
+ select SOC_NRF9230_ENGB_CPUAPP if SOC_NRF9280_CPUAPP
+ select SOC_NRF9230_ENGB_CPURAD if SOC_NRF9280_CPURAD
+ select SOC_NRF9230_ENGB_CPUPPR if SOC_NRF9280_CPUPPR
+ help
+ nRF9280 SiP
+
+# The CPU select the "SoC" (SiP)
+config SOC_NRF9280_CPUAPP
+ bool
+ select SOC_NRF9280
+ help
+ nRF9280 CPUAPP
+
+config SOC_NRF9280_CPURAD
+ bool
+ select SOC_NRF9280
+ help
+ nRF9280 CPURAD
+
+config SOC_NRF9280_CPUPPR
+ bool
+ select SOC_NRF9280
+ help
+ nRF9280 CPUPPR
+
+config SOC
+ default "nrf9280" if SOC_NRF9280
diff --git a/soc/nordic/nrf92/align.ld b/soc/nordic/nrf92/align.ld
new file mode 100644
index 0000000..0905aa7
--- /dev/null
+++ b/soc/nordic/nrf92/align.ld
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.align16,,)
+{
+ . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1;
+ BYTE(0);
+} GROUP_LINK_IN(ROMABLE_REGION)
diff --git a/soc/nordic/nrf92/soc.c b/soc/nordic/nrf92/soc.c
new file mode 100644
index 0000000..1a40bb5
--- /dev/null
+++ b/soc/nordic/nrf92/soc.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/cache.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <hal/nrf_hsfll.h>
+#include <hal/nrf_lrcconf.h>
+#include <hal/nrf_spu.h>
+#include <soc/nrfx_coredep.h>
+
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#if defined(NRF_APPLICATION)
+#define HSFLL_NODE DT_NODELABEL(cpuapp_hsfll)
+#elif defined(NRF_RADIOCORE)
+#define HSFLL_NODE DT_NODELABEL(cpurad_hsfll)
+#endif
+
+#define FICR_ADDR_GET(node_id, name) \
+ DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) + \
+ DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset)
+
+#define SPU_INSTANCE_GET(p_addr) \
+ ((NRF_SPU_Type *)((p_addr) & (ADDRESS_REGION_Msk | \
+ ADDRESS_SECURITY_Msk | \
+ ADDRESS_DOMAIN_Msk | \
+ ADDRESS_BUS_Msk)))
+
+static void power_domain_init(void)
+{
+ /*
+ * Set:
+ * - LRCCONF010.POWERON.MAIN: 1
+ * - LRCCONF010.POWERON.ACT: 1
+ * - LRCCONF010.RETAIN.MAIN: 1
+ * - LRCCONF010.RETAIN.ACT: 1
+ *
+ * This is done here at boot so that when the idle routine will hit
+ * WFI the power domain will be correctly retained.
+ */
+
+ nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
+ nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
+
+ nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
+ nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
+}
+
+static int trim_hsfll(void)
+{
+#if defined(HSFLL_NODE)
+
+ NRF_HSFLL_Type *hsfll = (NRF_HSFLL_Type *)DT_REG_ADDR(HSFLL_NODE);
+ nrf_hsfll_trim_t trim = {
+ .vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)),
+ .coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)),
+ .fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine))
+ };
+
+ LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup);
+ LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse);
+ LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine);
+
+ nrf_hsfll_clkctrl_mult_set(hsfll,
+ DT_PROP(HSFLL_NODE, clock_frequency) /
+ DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency));
+ nrf_hsfll_trim_set(hsfll, &trim);
+
+ nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
+
+ LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
+ LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
+ LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE);
+
+#endif /* defined(HSFLL_NODE) */
+
+ return 0;
+}
+
+static int nordicsemi_nrf92_init(void)
+{
+ sys_cache_instr_enable();
+ sys_cache_data_enable();
+
+ power_domain_init();
+
+ trim_hsfll();
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay)
+ /* DMASEC is set to non-secure by default, which prevents CCM from
+ * accessing secure memory. Change DMASEC to secure.
+ */
+ uint32_t ccm030_addr = DT_REG_ADDR(DT_NODELABEL(ccm030));
+ NRF_SPU_Type *spu = SPU_INSTANCE_GET(ccm030_addr);
+
+ nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true);
+#endif
+
+ return 0;
+}
+
+void arch_busy_wait(uint32_t time_us)
+{
+ nrfx_coredep_delay_us(time_us);
+}
+
+SYS_INIT(nordicsemi_nrf92_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/nordic/nrf92/soc.h b/soc/nordic/nrf92/soc.h
new file mode 100644
index 0000000..4a495cf
--- /dev/null
+++ b/soc/nordic/nrf92/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_
+#define SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_
+
+#include <soc_nrf_common.h>
+
+#endif /* SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_ */
diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml
index 58cb74e..9c43764 100644
--- a/soc/nordic/soc.yml
+++ b/soc/nordic/soc.yml
@@ -39,6 +39,13 @@
- name: nrf9151
- name: nrf9160
- name: nrf9161
+ - name: nrf92
+ socs:
+ - name: nrf9280
+ cpuclusters:
+ - name: cpuapp
+ - name: cpurad
+ - name: cpuppr
# Recovery/erase is only needed once per core. Prevent resetting the cores whilst flashing
# multiple images until all images for each core have been flashed, this allows security
@@ -91,6 +98,10 @@
- nrf54h20/cpuapp
- nrf54h20/cpurad
- nrf54h20/cpuppr
+ - qualifiers:
+ - nrf9280/cpuapp
+ - nrf9280/cpurad
+ - nrf9280/cpuppr
'--erase':
- runners:
- nrfjprog
@@ -138,6 +149,10 @@
- nrf54h20/cpuapp
- nrf54h20/cpurad
- nrf54h20/cpuppr
+ - qualifiers:
+ - nrf9280/cpuapp
+ - nrf9280/cpurad
+ - nrf9280/cpuppr
'--reset':
- runners:
- nrfjprog
@@ -185,3 +200,7 @@
- nrf54h20/cpuapp
- nrf54h20/cpurad
- nrf54h20/cpuppr
+ - qualifiers:
+ - nrf9280/cpuapp
+ - nrf9280/cpurad
+ - nrf9280/cpuppr
diff --git a/soc/nordic/timing.c b/soc/nordic/timing.c
index 402e97f..9d75cd4 100644
--- a/soc/nordic/timing.c
+++ b/soc/nordic/timing.c
@@ -47,14 +47,14 @@
{
#if defined(CONFIG_SOC_SERIES_NRF51X)
#define COUNTER_SPAN BIT(16)
+#else
+#define COUNTER_SPAN BIT64(32)
+#endif
if (*end >= *start) {
return (*end - *start);
} else {
return COUNTER_SPAN + *end - *start;
}
-#else
- return (*end - *start);
-#endif
}
uint64_t soc_timing_freq_get(void)
diff --git a/soc/nuvoton/npcm/CMakeLists.txt b/soc/nuvoton/npcm/CMakeLists.txt
new file mode 100644
index 0000000..c5f9703
--- /dev/null
+++ b/soc/nuvoton/npcm/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(common)
+add_subdirectory(${SOC_SERIES})
diff --git a/soc/nuvoton/npcm/Kconfig b/soc/nuvoton/npcm/Kconfig
new file mode 100644
index 0000000..4debfc5
--- /dev/null
+++ b/soc/nuvoton/npcm/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_NPCM
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_NPCM
diff --git a/soc/nuvoton/npcm/Kconfig.defconfig b/soc/nuvoton/npcm/Kconfig.defconfig
new file mode 100644
index 0000000..aa7662f
--- /dev/null
+++ b/soc/nuvoton/npcm/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_NPCM
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_NPCM
diff --git a/soc/nuvoton/npcm/Kconfig.soc b/soc/nuvoton/npcm/Kconfig.soc
new file mode 100644
index 0000000..4e8d780
--- /dev/null
+++ b/soc/nuvoton/npcm/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_NPCM
+ bool
+
+config SOC_FAMILY
+ default "npcm" if SOC_FAMILY_NPCM
+
+rsource "*/Kconfig.soc"
diff --git a/soc/nuvoton/npcm/common/CMakeLists.txt b/soc/nuvoton/npcm/common/CMakeLists.txt
new file mode 100644
index 0000000..a219484
--- /dev/null
+++ b/soc/nuvoton/npcm/common/CMakeLists.txt
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+set(NPCM_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcm.bin)
+string(TOUPPER "${SOC_NAME}" soc_name_upper)
+
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+ COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/common/esiost/esiost.py
+ -i ${KERNEL_BIN_NAME}
+ -o ${NPCM_BIN_NAME}
+ -v
+ )
diff --git a/soc/nuvoton/npcm/common/esiost/esiost.py b/soc/nuvoton/npcm/common/esiost/esiost.py
new file mode 100755
index 0000000..cb346ff
--- /dev/null
+++ b/soc/nuvoton/npcm/common/esiost/esiost.py
@@ -0,0 +1,596 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2024 Nuvoton Technology Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# This script will append/paste specific header to tell ROM code (Booter) of
+# NPCM eSIO series how to load the firmware from flash to code ram
+# Usage python3 ${ZEPHYR_BASE}/scripts/esiost.py
+# -i in_file.bin -o out_file.bin
+# [-chip <name>] [-v]
+
+import sys
+import hashlib
+from colorama import init, Fore
+from esiost_args import EsiostArgs, exit_with_failure
+from pathlib import Path
+
+# ESIOST
+ESIOST_VER = "1.0.0"
+
+# Offsets inside the header
+HDR_ANCHOR_OFFSET = 0x0
+HDR_FW_ENTRY_POINT_OFFSET = 0x21C
+HDR_FW_FLASH_ADDR_START_LOAD_OFFSET = 0x220
+HDR_FW_FLASH_ADDR_END_LOAD_OFFSET = 0x224
+HDR_FW_LOAD_START_ADDR_OFFSET = 0x228
+HDR_FW_LENGTH_OFFSET = 0x22C
+HDR_FW_LOAD_HASH_OFFSET = 0x480
+HDR_FW_SEG1_START_OFFSET = 0x4C0
+HDR_FW_SEG1_SIZE_OFFSET = 0x4C4
+HDR_FW_SEG2_START_OFFSET = 0x4C8
+HDR_FW_SEG2_SIZE_OFFSET = 0x4CC
+HDR_FW_SEG3_START_OFFSET = 0x4D0
+HDR_FW_SEG3_SIZE_OFFSET = 0x4D4
+HDR_FW_SEG4_START_OFFSET = 0x4D8
+HDR_FW_SEG4_SIZE_OFFSET = 0x4DC
+HDR_FW_SEG1_HASH_OFFSET = 0x500
+HDR_FW_SEG2_HASH_OFFSET = 0x540
+HDR_FW_SEG3_HASH_OFFSET = 0x580
+HDR_FW_SEG4_HASH_OFFSET = 0x5C0
+FW_IMAGE_OFFSET = 0x600
+
+ARM_FW_ENTRY_POINT_OFFSET = 0x004
+
+# Header field known values
+FW_HDR_ANCHOR = '%FiMg94@'
+FW_HDR_SEG1_START = 0x210
+FW_HDR_SEG1_SIZE = 0x2F0
+FW_HDR_SEG2_START = 0x0
+FW_HDR_SEG2_SIZE = 0x0
+FW_HDR_SEG3_START = 0x600
+FW_HDR_SEG4_START = 0x0
+FW_HDR_SEG4_SIZE = 0x0
+
+# Header fields default values.
+ADDR_16_BYTES_ALIGNED_MASK = 0x0000000f
+ADDR_4_BYTES_ALIGNED_MASK = 0x00000003
+ADDR_4K_BYTES_ALIGNED_MASK = 0x00000fff
+
+INVALID_INPUT = -1
+HEADER_SIZE = FW_IMAGE_OFFSET
+
+# Verbose related values
+NO_VERBOSE = 0
+REG_VERBOSE = 0
+
+# Success/failure codes
+EXIT_SUCCESS_STATUS = 0
+EXIT_FAILURE_STATUS = 1
+
+def _bt_mode_handler(esiost_args):
+ """creates the bootloader table using the provided arguments.
+
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ output_file = _set_input_and_output(esiost_args)
+ _check_chip(output_file, esiost_args)
+
+ _copy_image(output_file, esiost_args)
+ _set_anchor(output_file, esiost_args)
+ _set_firmware_load_start_address(output_file, esiost_args)
+ _set_firmware_entry_point(output_file, esiost_args)
+ _set_firmware_length(output_file, esiost_args)
+ _set_firmware_load_hash(output_file, esiost_args)
+ _set_firmware_segment(output_file, esiost_args)
+ _set_firmware_segment_hash(output_file, esiost_args)
+
+ _exit_with_success()
+
+def _set_input_and_output(esiost_args):
+ """checks the input file and output and sets the output file.
+
+ checks input file existence, creates an output file according
+ to the 'output' argument.
+
+ Note: input file size has to be greater than 0, and named differently
+ from output file
+
+ :param esiost_args: the object representing the command line arguments.
+
+ :returns: output file path object, or -1 if fails
+ """
+ input_file = esiost_args.input
+ output = esiost_args.output
+ input_file_size = 0
+
+ if not input_file:
+ exit_with_failure("Define input file, using -i flag")
+
+ input_file_path = Path(input_file)
+
+ if not input_file_path.exists():
+ exit_with_failure(f'Cannot open {input_file}')
+ elif input_file_path.stat().st_size == 0:
+ exit_with_failure(f'BIN Input file ({input_file}) is empty')
+ else:
+ input_file_size = input_file_path.stat().st_size
+
+ if not output:
+ output_file = Path("out_" + input_file_path.name)
+ else:
+ output_file = Path(output)
+
+ if output_file.exists():
+ if output_file.samefile(input_file_path):
+ exit_with_failure(f'Input file name {input_file} '
+ f'should be differed from'
+ f' Output file name {output}')
+ output_file.unlink()
+
+ output_file.touch()
+
+ if esiost_args.verbose == REG_VERBOSE:
+ print(Fore.LIGHTCYAN_EX + f'\nBIN file: {input_file}, size:'
+ f' {input_file_size} bytes')
+ print(f'Output file name: {output_file.name} \n')
+
+ return output_file
+
+def _check_chip(output, esiost_args):
+ """checks if the chip entered is a legal chip, generates an error
+ and closes the application, deletes the output file if the chip name
+ is illegal.
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ if esiost_args.chip_name == INVALID_INPUT:
+ message = f'Invalid chip name, '
+ message += "should be npcm400."
+ _exit_with_failure_delete_file(output, message)
+
+def _set_anchor(output, esiost_args):
+ """writes the anchor value to the output file
+
+ :param output: the output file object.
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ if len(FW_HDR_ANCHOR) > 8:
+ message = f'ANCHOR max support 8 bytes'
+ _exit_with_failure_delete_file(output, message)
+
+ with output.open("r+b") as output_file:
+ output_file.seek(HDR_ANCHOR_OFFSET)
+ anchor_hex = FW_HDR_ANCHOR.encode('ascii')
+ output_file.write(anchor_hex)
+ if esiost_args.verbose == REG_VERBOSE:
+ print(f'- HDR - FW Header ANCHOR - Offset '
+ f'{HDR_ANCHOR_OFFSET} - %s' % FW_HDR_ANCHOR)
+
+ output_file.close()
+
+def _set_firmware_load_start_address(output, esiost_args):
+ """writes the fw load address to the output file
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+ input_file_path = Path(esiost_args.input)
+
+ start_ram = esiost_args.chip_ram_address
+ end_ram = start_ram + esiost_args.chip_ram_size
+ fw_load_addr = esiost_args.firmware_load_address
+ fw_length = esiost_args.firmware_length
+ fw_end_addr = fw_load_addr + fw_length
+ start_flash_addr = esiost_args.chip_flash_address + HEADER_SIZE
+ end_flash_addr = start_flash_addr + fw_length
+
+ start_ram_to_print = _hex_print_format(start_ram)
+ end_ram_to_print = _hex_print_format(end_ram)
+ fw_load_addr_to_print = _hex_print_format(fw_load_addr)
+ fw_end_addr_to_print = _hex_print_format(fw_end_addr)
+
+ if fw_length == INVALID_INPUT:
+ message = f'Cannot read firmware length'
+ _exit_with_failure_delete_file(output, message)
+
+ if fw_load_addr is INVALID_INPUT:
+ message = f'Cannot read FW Load start address'
+ _exit_with_failure_delete_file(output, message)
+
+ if fw_load_addr & ADDR_16_BYTES_ALIGNED_MASK != 0:
+ message = f'Firmware load address ({fw_load_addr_to_print}) ' \
+ f'is not 16 bytes aligned'
+ _exit_with_failure_delete_file(output, message)
+
+ if (fw_load_addr > end_ram) or (fw_load_addr < start_ram):
+ message = f'Firmware load address ({fw_load_addr_to_print}) ' \
+ f'should be between start ({start_ram_to_print}) '\
+ f'and end ({end_ram_to_print}) of RAM'
+ _exit_with_failure_delete_file(output, message)
+
+ with output.open("r+b") as output_file:
+ # check fw_entry pt location in flash or not
+ with input_file_path.open("r+b") as input_file:
+ input_file.seek(ARM_FW_ENTRY_POINT_OFFSET)
+ fw_arm_entry_byte = input_file.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+
+ if fw_arm_entry_pt == 0:
+ input_file.seek(ARM_FW_ENTRY_POINT_OFFSET + HEADER_SIZE)
+ fw_arm_entry_byte = input_file.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+ else:
+ if fw_end_addr > end_ram:
+ message = f'Firmware end address ({fw_end_addr_to_print}) should be '
+ message += f'less than end of RAM address ({end_ram_to_print})'
+ _exit_with_failure_delete_file(output, message)
+
+ if start_flash_addr < fw_arm_entry_pt < end_flash_addr:
+ fw_load_addr = 0x0
+ start_flash_addr = 0x0
+ end_flash_addr = 0x0
+
+ input_file.close()
+
+ # set start load flash address
+ output_file.seek(HDR_FW_FLASH_ADDR_START_LOAD_OFFSET)
+ output_file.write(start_flash_addr.to_bytes(4, "little"))
+
+ # set end load flash address
+ output_file.seek(HDR_FW_FLASH_ADDR_END_LOAD_OFFSET)
+ output_file.write(end_flash_addr.to_bytes(4, "little"))
+
+ # set load start address (RAM)
+ output_file.seek(HDR_FW_LOAD_START_ADDR_OFFSET)
+ output_file.write(fw_load_addr.to_bytes(4, "little"))
+
+ if esiost_args.verbose == REG_VERBOSE:
+ print(f'- HDR - FW load start address - Offset '
+ f'{HDR_FW_LOAD_START_ADDR_OFFSET} - '
+ f'{_hex_print_format(fw_load_addr)}')
+ print(f'- HDR - flash load start address - Offset '
+ f'{HDR_FW_FLASH_ADDR_START_LOAD_OFFSET} - '
+ f'{_hex_print_format(start_flash_addr)}')
+ print(f'- HDR - flash load end address - Offset '
+ f'{HDR_FW_FLASH_ADDR_END_LOAD_OFFSET} - '
+ f'{_hex_print_format(end_flash_addr)}')
+
+ output_file.close()
+
+def _set_firmware_entry_point(output, esiost_args):
+ """writes the fw entry point to the output file.
+ proportions:
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+ input_file_path = Path(esiost_args.input)
+ fw_entry_pt = esiost_args.firmware_entry_point
+ start_flash_addr = esiost_args.chip_flash_address + HEADER_SIZE
+ end_flash_addr = start_flash_addr + esiost_args.chip_flash_size
+
+ # check if fwep flag wasn't set and set it to fw load address if needed
+ if fw_entry_pt is None:
+ fw_entry_pt = esiost_args.firmware_load_address
+
+ # check fw_entry pt location in flash or not
+ with input_file_path.open("r+b") as input_file:
+ input_file.seek(ARM_FW_ENTRY_POINT_OFFSET)
+ fw_arm_entry_byte = input_file.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+
+ if fw_arm_entry_pt == 0:
+ input_file.seek(ARM_FW_ENTRY_POINT_OFFSET + HEADER_SIZE)
+ fw_arm_entry_byte = input_file.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+
+ if start_flash_addr < fw_arm_entry_pt < end_flash_addr:
+ fw_entry_pt = start_flash_addr
+
+ input_file.close()
+
+ with output.open("r+b") as output_file:
+ output_file.seek(HDR_FW_ENTRY_POINT_OFFSET)
+ output_file.write(fw_entry_pt.to_bytes(4, "little"))
+ output_file.close()
+
+ if esiost_args.verbose == REG_VERBOSE:
+ print(f'- HDR - FW Entry point - Offset '
+ f'{HDR_FW_ENTRY_POINT_OFFSET} - '
+ f'{_hex_print_format(fw_entry_pt)}')
+
+def _openssl_digest(filepath):
+ """Computes the SHA-256 digest of a file using hashlib.
+
+ :param filepath: Path to the file to digest.
+ :return: The SHA-256 digest of the file as a bytearray.
+ """
+ sha256_hash = hashlib.sha256()
+ with open(filepath, "rb") as f:
+ # Read and update hash string value in blocks of 4K
+ for byte_block in iter(lambda: f.read(4096), b""):
+ sha256_hash.update(byte_block)
+ return bytearray(sha256_hash.digest())
+
+def _set_firmware_length(output, esiost_args):
+ """writes the flash size value to the output file
+ Note: the firmware length value has already been checked before
+ this method
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ fw_length = esiost_args.firmware_length
+ fw_length_to_print = _hex_print_format(fw_length)
+
+ with output.open("r+b") as output_file:
+ output_file.seek(HDR_FW_LENGTH_OFFSET)
+ output_file.write(fw_length.to_bytes(4, "big"))
+ if esiost_args.verbose == REG_VERBOSE:
+ print(f'- HDR - FW Length - Offset '
+ f'{HDR_FW_LENGTH_OFFSET} - '
+ f'{fw_length_to_print}')
+ output_file.close()
+
+def _set_firmware_load_hash(output, esiost_args):
+ """writes the load hash value to the output file
+ Note: the firmware length value has already been checked before
+ this method
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+ sha256_hash = hashlib.sha256()
+ with output.open("r+b") as f:
+ f.seek(HEADER_SIZE)
+ # Read and update hash string value in blocks of 4K
+ for byte_block in iter(lambda: f.read(4096), b""):
+ sha256_hash.update(byte_block)
+
+ hash_data = bytearray(sha256_hash.digest())
+
+ with output.open("r+b") as output_file:
+ output_file.seek(HDR_FW_LOAD_HASH_OFFSET)
+ output_file.write(hash_data)
+ output_file.close()
+
+def _set_firmware_segment(output, esiost_args):
+ """writes the segment start and size value to the output file
+ Note: the firmware length value has already been checked before
+ this method
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ fw_length = esiost_args.firmware_length
+
+ with output.open("r+b") as output_file:
+ # set segment_1 start and size
+ output_file.seek(HDR_FW_SEG1_START_OFFSET)
+ output_file.write(FW_HDR_SEG1_START.to_bytes(4, "little"))
+ output_file.seek(HDR_FW_SEG1_SIZE_OFFSET)
+ output_file.write(FW_HDR_SEG1_SIZE.to_bytes(4, "little"))
+
+ # set segment_2 start and size
+ output_file.seek(HDR_FW_SEG2_START_OFFSET)
+ output_file.write(FW_HDR_SEG2_START.to_bytes(4, "little"))
+ output_file.seek(HDR_FW_SEG2_SIZE_OFFSET)
+ output_file.write(FW_HDR_SEG2_SIZE.to_bytes(4, "little"))
+
+ # set segment_3 start and size
+ output_file.seek(HDR_FW_SEG3_START_OFFSET)
+ output_file.write(FW_HDR_SEG3_START.to_bytes(4, "little"))
+ output_file.seek(HDR_FW_SEG3_SIZE_OFFSET)
+ output_file.write(fw_length.to_bytes(4, "little"))
+
+ # set segment_4 start and size
+ output_file.seek(HDR_FW_SEG4_START_OFFSET)
+ output_file.write(FW_HDR_SEG4_START.to_bytes(4, "little"))
+ output_file.seek(HDR_FW_SEG4_SIZE_OFFSET)
+ output_file.write(FW_HDR_SEG4_SIZE.to_bytes(4, "little"))
+
+ segment1_start_to_print = _hex_print_format(FW_HDR_SEG1_START)
+ segment1_size_to_print = _hex_print_format(FW_HDR_SEG1_SIZE)
+ segment2_start_to_print = _hex_print_format(FW_HDR_SEG2_START)
+ segment2_size_to_print = _hex_print_format(FW_HDR_SEG2_SIZE)
+ segment3_start_to_print = _hex_print_format(FW_HDR_SEG3_START)
+ segment3_size_to_print = _hex_print_format(fw_length)
+ segment4_start_to_print = _hex_print_format(FW_HDR_SEG4_START)
+ segment4_size_to_print = _hex_print_format(FW_HDR_SEG4_SIZE)
+
+ if esiost_args.verbose == REG_VERBOSE:
+ print(f'- HDR - Segment1 start address - Offset '
+ f'{HDR_FW_SEG1_START_OFFSET} - '
+ f'{segment1_start_to_print}')
+ print(f'- HDR - Segment1 size - Offset '
+ f'{HDR_FW_SEG1_SIZE_OFFSET} - '
+ f'{segment1_size_to_print}')
+ print(f'- HDR - Segment2 start address - Offset '
+ f'{HDR_FW_SEG2_START_OFFSET} - '
+ f'{segment2_start_to_print}')
+ print(f'- HDR - Segment2 size - Offset '
+ f'{HDR_FW_SEG2_SIZE_OFFSET} - '
+ f'{segment2_size_to_print}')
+ print(f'- HDR - Segment3 start address - Offset '
+ f'{HDR_FW_SEG3_START_OFFSET} - '
+ f'{segment3_start_to_print}')
+ print(f'- HDR - Segment3 size - Offset '
+ f'{HDR_FW_SEG3_SIZE_OFFSET} - '
+ f'{segment3_size_to_print}')
+ print(f'- HDR - Segment4 start address - Offset '
+ f'{HDR_FW_SEG4_START_OFFSET} - '
+ f'{segment4_start_to_print}')
+ print(f'- HDR - Segment4 size - Offset '
+ f'{HDR_FW_SEG4_SIZE_OFFSET} - '
+ f'{segment4_size_to_print}')
+
+ output_file.close()
+
+def _clearup_tempfiles(output, esiost_args):
+ """clearup the tempfiles
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ output_file = Path(output)
+
+ seg1_file = Path("seg1_" + output_file.name)
+ if seg1_file.exists():
+ seg1_file.unlink()
+
+def _set_firmware_segment_hash(output, esiost_args):
+ """Writes the segment hash value to the output file.
+ Note: the firmware length value has already been checked before this method.
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ # Generate segment files
+ with output.open("r+b") as output_file:
+ # seg1
+ output_file.seek(HDR_FW_SEG1_START_OFFSET)
+ seg1_start = int.from_bytes(output_file.read(4), "little")
+ output_file.seek(HDR_FW_SEG1_SIZE_OFFSET)
+ seg1_size = int.from_bytes(output_file.read(4), "little")
+ output_file.seek(seg1_start)
+
+ seg1_data = output_file.read(seg1_size)
+
+ seg1_file_path = Path("seg1_" + output_file.name)
+ with seg1_file_path.open("wb") as seg1_file:
+ seg1_file.write(seg1_data)
+
+ # set hash
+
+ # seg1 hash
+ hash_data = _openssl_digest(seg1_file_path)
+ output_file.seek(HDR_FW_SEG1_HASH_OFFSET)
+ output_file.write(hash_data)
+
+ # seg3 hash
+ sha256_hash = hashlib.sha256()
+ output_file.seek(HEADER_SIZE)
+ # Read and update hash string value in blocks of 4K
+ for byte_block in iter(lambda: output_file.read(4096), b""):
+ sha256_hash.update(byte_block)
+
+ hash_data = bytearray(sha256_hash.digest())
+
+ output_file.seek(HDR_FW_SEG3_HASH_OFFSET)
+ output_file.write(hash_data)
+
+ _clearup_tempfiles(output, esiost_args)
+
+def _copy_image(output, esiost_args):
+ """copies the fw image from the input file to the output file
+ if firmware header offset is defined, just copies the input file to the
+ output file
+
+ :param output: the output file object,
+ :param esiost_args: the object representing the command line arguments.
+ """
+
+ # check input file offset
+ with open(esiost_args.input, "rb") as firmware_image:
+ firmware_image.seek(ARM_FW_ENTRY_POINT_OFFSET)
+ fw_arm_entry_byte = firmware_image.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+ if fw_arm_entry_pt != 0:
+ image_offset = 0
+ input_file_size = Path(esiost_args.input).stat().st_size
+ else:
+ firmware_image.seek(ARM_FW_ENTRY_POINT_OFFSET + HEADER_SIZE)
+ fw_arm_entry_byte = firmware_image.read(4)
+ fw_arm_entry_pt = int.from_bytes(fw_arm_entry_byte, "little")
+ if fw_arm_entry_pt == 0:
+ sys.exit(EXIT_FAILURE_STATUS)
+ else:
+ image_offset = 1
+ input_file_size = Path(esiost_args.input).stat().st_size - HEADER_SIZE
+
+ firmware_image.close()
+
+ with open(esiost_args.input, "rb") as firmware_image:
+ with open(output, "r+b") as output_file:
+ if image_offset == 0:
+ output_file.seek(HEADER_SIZE)
+ for line in firmware_image:
+ output_file.write(line)
+ output_file.close()
+ firmware_image.close()
+
+ # update firmware length if needed
+ fw_length = esiost_args.firmware_length
+ if fw_length is None:
+ esiost_args.firmware_length = input_file_size
+
+def _hex_print_format(value):
+ """hex representation of an integer
+
+ :param value: an integer to be represented in hex
+ """
+ return "0x{:08x}".format(value)
+
+def _exit_with_failure_delete_file(output, message):
+ """formatted failure message printer, prints the
+ relevant error message, deletes the output file,
+ and exits the application.
+
+ :param message: the error message to be printed
+ """
+ output_file = Path(output)
+ if output_file.exists():
+ output_file.unlink()
+
+ message = '\n' + message
+ message += '\n'
+ message += '******************************\n'
+ message += '*** FAILED ***\n'
+ message += '******************************\n'
+ print(Fore.RED + message)
+
+ sys.exit(EXIT_FAILURE_STATUS)
+
+def _exit_with_success():
+ """formatted success message printer, prints the
+ success message and exits the application.
+ """
+ message = '\n'
+ message += '******************************\n'
+ message += '*** SUCCESS ***\n'
+ message += '******************************\n'
+ print(Fore.GREEN + message)
+
+ sys.exit(EXIT_SUCCESS_STATUS)
+
+def main():
+ """main of the application
+ """
+ init() # colored print initialization for windows
+
+ if len(sys.argv) < 2:
+ sys.exit(EXIT_FAILURE_STATUS)
+
+ esiost_obj = EsiostArgs()
+
+ if esiost_obj.error_args:
+ for err_arg in esiost_obj.error_args:
+ message = f'unKnown flag: {err_arg}'
+ exit_with_failure(message)
+ sys.exit(EXIT_SUCCESS_STATUS)
+
+ # Start to handle booter header table
+ _bt_mode_handler(esiost_obj)
+
+if __name__ == '__main__':
+ main()
diff --git a/soc/nuvoton/npcm/common/esiost/esiost_args.py b/soc/nuvoton/npcm/common/esiost/esiost_args.py
new file mode 100755
index 0000000..16e468e
--- /dev/null
+++ b/soc/nuvoton/npcm/common/esiost/esiost_args.py
@@ -0,0 +1,130 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2024 Nuvoton Technology Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# This file contains general functions for ESIOST application
+
+import sys
+import argparse
+import colorama
+from colorama import Fore
+
+INVALID_INPUT = -1
+EXIT_FAILURE_STATUS = 1
+
+# Verbose related values
+NO_VERBOSE = 0
+REG_VERBOSE = 1
+
+# argument default values.
+DEFAULT_VERBOSE = NO_VERBOSE
+
+# Chips: convert from name to index.
+CHIPS_INFO = {
+ 'npcm400': {'flash_address': 0x80000, 'flash_size': 0x20000, 'ram_address': 0x10008000, 'ram_size': 0xC0000},
+}
+
+DEFAULT_CHIP = 'npcm400'
+
+class EsiostArgs:
+ """creates an arguments object for the ESIOST,
+ the arguments are taken from the command line and/or
+ argument file
+ """
+ error_args = None
+
+ help = False
+ verbose = DEFAULT_VERBOSE
+ input = None
+ output = None
+ args_file = None
+ chip_name = DEFAULT_CHIP
+ chip_ram_address = CHIPS_INFO[DEFAULT_CHIP]['ram_address']
+ chip_ram_size = CHIPS_INFO[DEFAULT_CHIP]['ram_address']
+ chip_flash_address = CHIPS_INFO[DEFAULT_CHIP]['flash_address']
+ chip_flash_size = CHIPS_INFO[DEFAULT_CHIP]['flash_size']
+ firmware_load_address = None
+ firmware_entry_point = None
+ firmware_length = None
+
+ def __init__(self):
+
+ arguments = _create_parser("")
+ valid_arguments = arguments[0]
+ invalid_arguments = arguments[1]
+ self.error_args = invalid_arguments
+
+ _populate_args(self, valid_arguments)
+ _populate_chip_fields(self)
+
+def _populate_chip_fields(self):
+ """populate the chip related fields for the esiost"""
+ self.chip_name = self.chip_name
+ chip = str(self.chip_name).lower()
+
+ if chip not in CHIPS_INFO:
+ self.chip_name = INVALID_INPUT
+ return
+
+ self.chip_ram_address = CHIPS_INFO[chip]['ram_address']
+ self.chip_ram_size = CHIPS_INFO[chip]['ram_size']
+ self.chip_flash_address = CHIPS_INFO[DEFAULT_CHIP]['flash_address']
+ self.chip_flash_size = CHIPS_INFO[DEFAULT_CHIP]['flash_size']
+ if self.firmware_load_address is None:
+ self.firmware_load_address = self.chip_ram_address
+
+def _populate_args(self, argument_list):
+ """populate the esiost arguments according to the command line/ args file"""
+ for arg in vars(argument_list):
+ if (arg == "input") & (argument_list.input is not None):
+ self.input = argument_list.input
+
+ elif (arg == "output") & (argument_list.output is not None):
+ self.output = argument_list.output
+
+ elif (arg == "chip") & (argument_list.chip is not None):
+ self.chip_name = argument_list.chip
+ _populate_chip_fields(self)
+
+ elif (arg == "verbose") & argument_list.verbose:
+ self.verbose = REG_VERBOSE
+
+def _create_parser(arg_list):
+ """create argument parser according to pre-defined arguments
+
+ :param arg_list: when empty, parses command line arguments,
+ else parses the given string
+ """
+
+ parser = argparse.ArgumentParser(conflict_handler='resolve', allow_abbrev=False)
+ parser.add_argument("-i", nargs='?', dest="input")
+ parser.add_argument("-o", nargs='?', dest="output")
+ parser.add_argument("-chip", dest="chip")
+ parser.add_argument("-v", action="store_true", dest="verbose")
+
+ args = parser.parse_known_args(arg_list.split())
+
+ if arg_list == "":
+ args = parser.parse_known_args()
+
+ return args
+
+def exit_with_failure(message):
+ """formatted failure message printer, prints the
+ relevant error message and exits the application.
+
+ :param message: the error message to be printed
+ """
+
+ message = '\n' + message
+ message += '\n'
+ message += '******************************\n'
+ message += '*** FAILED ***\n'
+ message += '******************************\n'
+ print(Fore.RED + message)
+
+ sys.exit(EXIT_FAILURE_STATUS)
+
+colorama.init()
diff --git a/soc/nuvoton/npcm/npcm4/CMakeLists.txt b/soc/nuvoton/npcm/npcm4/CMakeLists.txt
new file mode 100644
index 0000000..9a246a4
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/CMakeLists.txt
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(
+ .
+ ${ZEPHYR_BASE}/drivers
+)
+
+zephyr_sources(
+ soc.c
+)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/nuvoton/npcm/npcm4/Kconfig b/soc/nuvoton/npcm/npcm4/Kconfig
new file mode 100644
index 0000000..a393fad
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NPCM4
+ select ARM
+ select CPU_CORTEX_M4
+ select CPU_CORTEX_M_HAS_DWT
+ select CORTEX_M_SYSTICK
+ select CPU_HAS_ARM_MPU
diff --git a/soc/nuvoton/npcm/npcm4/Kconfig.defconfig b/soc/nuvoton/npcm/npcm4/Kconfig.defconfig
new file mode 100644
index 0000000..a398896
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/Kconfig.defconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NPCM4
+
+config NUM_IRQS
+ default 82
+
+config ROM_START_OFFSET
+ default 0x600 if XIP
+ default 0x0 if !XIP
+
+endif # SOC_SERIES_NPCM4
diff --git a/soc/nuvoton/npcm/npcm4/Kconfig.soc b/soc/nuvoton/npcm/npcm4/Kconfig.soc
new file mode 100644
index 0000000..3d4cb6b
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/Kconfig.soc
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NPCM4
+ bool
+ select SOC_FAMILY_NPCM
+ help
+ Enable support for Nuvoton NPCM4 series
+
+config SOC_NPCM400
+ bool
+ select SOC_SERIES_NPCM4
+
+config SOC_SERIES
+ default "npcm4" if SOC_SERIES_NPCM4
+
+config SOC
+ default "npcm400" if SOC_NPCM400
diff --git a/soc/nuvoton/npcm/npcm4/soc.c b/soc/nuvoton/npcm/npcm4/soc.c
new file mode 100644
index 0000000..4253654
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/soc.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+static int soc_npcm4_init(void)
+{
+ return 0;
+}
+
+SYS_INIT(soc_npcm4_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/nuvoton/npcm/npcm4/soc.h b/soc/nuvoton/npcm/npcm4/soc.h
new file mode 100644
index 0000000..6449769
--- /dev/null
+++ b/soc/nuvoton/npcm/npcm4/soc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCM_SOC_H_
+#define _NUVOTON_NPCM_SOC_H_
+
+/* CMSIS required definitions */
+#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
+#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
+
+/* Add include for DTS generated information */
+#include <zephyr/devicetree.h>
+#include <cmsis_core_m_defaults.h>
+
+#endif /* _NUVOTON_NPCM_SOC_H_ */
diff --git a/soc/nuvoton/npcm/soc.yml b/soc/nuvoton/npcm/soc.yml
new file mode 100644
index 0000000..df9c8da
--- /dev/null
+++ b/soc/nuvoton/npcm/soc.yml
@@ -0,0 +1,6 @@
+family:
+- name: npcm
+ series:
+ - name: npcm4
+ socs:
+ - name: npcm400
diff --git a/soc/nuvoton/npcx/common/scfg.c b/soc/nuvoton/npcx/common/scfg.c
index fd287ce..6dac027 100644
--- a/soc/nuvoton/npcx/common/scfg.c
+++ b/soc/nuvoton/npcx/common/scfg.c
@@ -145,6 +145,11 @@
/* Pin-control driver registration */
static int npcx_scfg_init(void)
{
+ /* If booter doesn't set the host interface type */
+ if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
+ npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
+ }
+
/* Change all pads whose default functionality isn't IO to GPIO */
for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
npcx_pinctrl_alt_sel(&def_alts[i], 0);
diff --git a/soc/nuvoton/numaker/m2l31x/CMakeLists.txt b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt
index c1295bf..6466b0b 100644
--- a/soc/nuvoton/numaker/m2l31x/CMakeLists.txt
+++ b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt
@@ -6,4 +6,6 @@
zephyr_include_directories(.)
+zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig b/soc/nuvoton/numaker/m2l31x/Kconfig
index 58d3041..350913a 100644
--- a/soc/nuvoton/numaker/m2l31x/Kconfig
+++ b/soc/nuvoton/numaker/m2l31x/Kconfig
@@ -8,6 +8,7 @@
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ARM_MPU
+ select HAS_POWEROFF
config SOC_M2L31XXX
select HAS_NUMAKER_HAL
diff --git a/soc/nuvoton/numaker/m2l31x/poweroff.c b/soc/nuvoton/numaker/m2l31x/poweroff.c
new file mode 100644
index 0000000..9423382
--- /dev/null
+++ b/soc/nuvoton/numaker/m2l31x/poweroff.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/poweroff.h>
+#include <NuMicro.h>
+
+void z_sys_poweroff(void)
+{
+ SYS_UnlockReg();
+
+ /* Clear all wake-up flag */
+ CLK->PMUSTS |= CLK_PMUSTS_CLRWK_Msk;
+
+ /* Select Power-down mode */
+ CLK_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, CLK_PMUCTL_PDMSEL_SPD0));
+
+ /* Enable RTC wake-up */
+ CLK_ENABLE_RTCWK();
+
+ /* Enter to Power-down mode */
+ CLK_PowerDown();
+
+ k_cpu_idle();
+
+ CODE_UNREACHABLE;
+}
diff --git a/soc/nuvoton/numaker/m2l31x/soc.c b/soc/nuvoton/numaker/m2l31x/soc.c
index e766b27..f327450 100644
--- a/soc/nuvoton/numaker/m2l31x/soc.c
+++ b/soc/nuvoton/numaker/m2l31x/soc.c
@@ -16,6 +16,9 @@
/* Unlock protected registers */
SYS_UnlockReg();
+ /* Release I/O hold status */
+ CLK->IOPDCTL = 1;
+
/*
* -------------------
* Init System Clock
diff --git a/soc/nuvoton/numaker/m46x/soc.c b/soc/nuvoton/numaker/m46x/soc.c
index d62a8bf..889e93c 100644
--- a/soc/nuvoton/numaker/m46x/soc.c
+++ b/soc/nuvoton/numaker/m46x/soc.c
@@ -57,14 +57,14 @@
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
-#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
- /* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
- if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
- CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
- /* Wait for HIRC48 clock ready */
- CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
- } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
- CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48m)
+ /* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48M) */
+ if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_ENABLE) {
+ CLK_EnableXtalRC(CLK_PWRCTL_HIRC48MEN_Msk);
+ /* Wait for HIRC48M clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HIRC48MSTB_Msk);
+ } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_DISABLE) {
+ CLK_DisableXtalRC(CLK_PWRCTL_HIRC48MEN_Msk);
}
#endif
diff --git a/soc/nxp/common/Kconfig.flexspi_xip b/soc/nxp/common/Kconfig.flexspi_xip
new file mode 100644
index 0000000..a067f0a
--- /dev/null
+++ b/soc/nxp/common/Kconfig.flexspi_xip
@@ -0,0 +1,41 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+DT_COMPAT_FLEXSPI := nxp,imx-flexspi
+
+DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
+DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
+
+DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
+DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
+
+config FLASH_BASE_ADDRESS
+ default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
+ if $(DT_FLASH_PARENT_IS_FLEXSPI)
+ default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config FLASH_SIZE
+ default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
+ if $(DT_FLASH_HAS_SIZE_PROP)
+ default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_MCUX_FLEXSPI_XIP
+ bool
+ default $(DT_FLASH_PARENT_IS_FLEXSPI)
+ select XIP
+ help
+ Allows REfor the soc to safely initialize the clocks for the
+ FlexSpi when planning to execute code in FlexSpi Memory.
+
+config CODE_DATA_RELOCATION_SRAM
+ default y if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
+
+config FLASH_MCUX_FLEXSPI_XIP_MEM
+ string
+ prompt "Flexspi drivers memory location"
+ default "RAM"
+ depends on MEMC_MCUX_FLEXSPI && FLASH_MCUX_FLEXSPI_XIP
+ help
+ Select the location to run the FlexSPI drivers when using
+ the flash API.
diff --git a/soc/nxp/common/Kconfig.rom_loader b/soc/nxp/common/Kconfig.rom_loader
new file mode 100644
index 0000000..9efcdff
--- /dev/null
+++ b/soc/nxp/common/Kconfig.rom_loader
@@ -0,0 +1,21 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config NXP_FLEXSPI_ROM_RAMLOADER
+ bool "Create output image that NXP ROM can load from FlexSPI to ram"
+ select BUILD_OUTPUT_HEX
+ depends on !FLASH_MCUX_FLEXSPI_XIP
+ help
+ Builds an output image that the BootROM can load from the
+ FlexSPI boot device into RAM region. The image will be loaded
+ from FLEXSPI into the region specified by `zephyr,flash` node.
+
+if NXP_FLEXSPI_ROM_RAMLOADER
+
+FLASH_CHOSEN := zephyr,flash
+FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
+FLEXSPI_BASE := $(dt_nodelabel_reg_addr_hex,flexspi,1)
+config BUILD_OUTPUT_ADJUST_LMA
+ default "$(FLEXSPI_BASE) - $(FLASH_BASE)"
+
+endif # NXP_FLEXSPI_ROM_RAMLOADER
diff --git a/soc/nxp/imx/imx6sx/soc.c b/soc/nxp/imx/imx6sx/soc.c
index cccff03..a968e5d 100644
--- a/soc/nxp/imx/imx6sx/soc.c
+++ b/soc/nxp/imx/imx6sx/soc.c
@@ -159,8 +159,9 @@
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
/* Wait until the command completes */
- while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
+ while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK) {
;
+ }
/* Enable system bus cache, enable write buffer */
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
barrier_isync_fence_full();
@@ -172,8 +173,9 @@
LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
- while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
+ while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK) {
;
+ }
/* Enable code bus cache, enable write buffer */
LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
barrier_isync_fence_full();
diff --git a/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h b/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
index daa9cfe..808b58b 100644
--- a/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
+++ b/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
@@ -104,12 +104,13 @@
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
- for (i = 0; i <= 31; i++)
+ for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
+ }
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
diff --git a/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h b/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
index daa9cfe..808b58b 100644
--- a/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
+++ b/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
@@ -104,12 +104,13 @@
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
- for (i = 0; i <= 31; i++)
+ for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
+ }
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
diff --git a/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
index daa9cfe..808b58b 100644
--- a/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
+++ b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
@@ -104,12 +104,13 @@
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
- for (i = 0; i <= 31; i++)
+ for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
+ }
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt
index dc7d191..bc4ddc2 100644
--- a/soc/nxp/imx/imx9/CMakeLists.txt
+++ b/soc/nxp/imx/imx9/CMakeLists.txt
@@ -7,4 +7,8 @@
zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/a55/linker.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_MIMX9352_M33)
+ zephyr_include_directories(.)
+ zephyr_include_directories(m33)
+ set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
endif()
diff --git a/soc/nxp/imx/imx9/Kconfig b/soc/nxp/imx/imx9/Kconfig
index a8e51c4..87de1fb 100644
--- a/soc/nxp/imx/imx9/Kconfig
+++ b/soc/nxp/imx/imx9/Kconfig
@@ -10,5 +10,18 @@
select HAS_MCUX_IOMUXC if PINCTRL
select HAS_MCUX_CACHE
+config SOC_MIMX9352_M33
+ select ARM
+ select CPU_CORTEX_M33
+ select CPU_HAS_FPU
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_ARM_SAU
+ select ARM_MPU
+ select ARMV8_M_DSP
+ select HAS_MCUX
+ select HAS_MCUX_IOMUXC if PINCTRL
+ select HAS_MCUX_CACHE
+
config MCUX_CORE_SUFFIX
default "_ca55" if SOC_MIMX9352_A55
+ default "_cm33" if SOC_MIMX9352_M33
diff --git a/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.m33 b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.m33
new file mode 100644
index 0000000..977b748
--- /dev/null
+++ b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.m33
@@ -0,0 +1,22 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX9352_M33
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+ default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+ default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config NUM_IRQS
+ int
+ default 268
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ int
+ default 200000000
+
+endif
diff --git a/soc/nxp/imx/imx9/Kconfig.soc b/soc/nxp/imx/imx9/Kconfig.soc
index 667e3fc..8742c2f 100644
--- a/soc/nxp/imx/imx9/Kconfig.soc
+++ b/soc/nxp/imx/imx9/Kconfig.soc
@@ -15,15 +15,29 @@
help
NXP i.MX93 A55
-config SOC_PART_NUMBER_MIMX9352CVUXK
+config SOC_MIMX9352_M33
+ bool
+ select SOC_MIMX9352
+ help
+ NXP i.MX93 M33
+
+config SOC_PART_NUMBER_MIMX9352CVVXM
bool
-config SOC_PART_NUMBER_MIMX9352DVUXM
+config SOC_PART_NUMBER_MIMX9352DVVXM
+ bool
+
+config SOC_PART_NUMBER_MIMX9352AVTXM
+ bool
+
+config SOC_PART_NUMBER_MIMX9352XVVXM
bool
config SOC_PART_NUMBER
- default "MIMX9352CVUXK" if SOC_PART_NUMBER_MIMX9352CVUXK
- default "MIMX9352DVUXM" if SOC_PART_NUMBER_MIMX9352DVUXM
+ default "MIMX9352CVVXM" if SOC_PART_NUMBER_MIMX9352CVVXM
+ default "MIMX9352DVVXM" if SOC_PART_NUMBER_MIMX9352DVVXM
+ default "MIMX9352AVTXM" if SOC_PART_NUMBER_MIMX9352AVTXM
+ default "MIMX9352XVVXM" if SOC_PART_NUMBER_MIMX9352XVVXM
config SOC
default "mimx9352" if SOC_MIMX9352
diff --git a/soc/nxp/imx/imx9/m33/soc.h b/soc/nxp/imx/imx9/m33/soc.h
new file mode 100644
index 0000000..dd04a57
--- /dev/null
+++ b/soc/nxp/imx/imx9/m33/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_NXP_IMX_IMX93_M33_SOC_H_
+#define _SOC_NXP_IMX_IMX93_M33_SOC_H_
+
+#include <fsl_device_registers.h>
+
+#endif /* _SOC_NXP_IMX_IMX93_M33_SOC_H_ */
diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt
index 371938f..0755d95 100644
--- a/soc/nxp/imxrt/CMakeLists.txt
+++ b/soc/nxp/imxrt/CMakeLists.txt
@@ -37,6 +37,24 @@
zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
endif()
+if(CONFIG_SOC_SERIES_IMXRT118X)
+ zephyr_linker_section_configure(
+ SECTION .rom_start
+ INPUT ".boot_hdr.conf"
+ OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET}
+ KEEP
+ PRIO 10
+ )
+ zephyr_linker_section_configure(
+ SECTION .rom_start
+ INPUT ".boot_hdr.container"
+ OFFSET ${CONFIG_IMAGE_CONTAINER_OFFSET}
+ KEEP
+ PRIO 11
+ )
+ zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
+endif()
+
if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX)
zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld)
@@ -45,3 +63,7 @@
if(CONFIG_MEMC)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
endif()
+
+if(CONFIG_SOC_SERIES_IMXRT118X)
+ zephyr_linker_sources_ifdef(CONFIG_SOC_SERIES_IMXRT118X SECTIONS container.ld)
+endif()
diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig
index 2ab29a5..b707e7d 100644
--- a/soc/nxp/imxrt/Kconfig
+++ b/soc/nxp/imxrt/Kconfig
@@ -10,46 +10,7 @@
# can override the defaults given here
rsource "*/Kconfig"
-# Used for default value in FLASH_MCUX_FLEXSPI_XIP
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
-# Macros to shorten Kconfig definitions
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
-
-config FLASH_MCUX_FLEXSPI_XIP
- bool "MCUX FlexSPI flash access with xip"
- default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
- select XIP
- help
- Allows for the soc to safely initialize the clocks for the
- FlexSpi when planning to execute code in FlexSpi Memory.
-
-if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
-
-choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
- prompt "FlexSPI drivers relocation target"
- default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
- help
- Select the location to run the FlexSPI drivers when using
- the flash API.
-
-config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
- bool "ITCM"
- select CODE_DATA_RELOCATION
-
-config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
- bool "RAM"
- select CODE_DATA_RELOCATION_SRAM
-
-endchoice
-
-config FLASH_MCUX_FLEXSPI_XIP_MEM
- string
- default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
- default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
-
-endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
+rsource "../common/Kconfig.flexspi_xip"
# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
# should be set elsewhere, since the determination of which SOC core
@@ -64,6 +25,8 @@
if NXP_IMXRT_BOOT_HEADER
+rsource "../common/Kconfig.rom_loader"
+
choice BOOT_DEVICE
prompt "Boot device"
default BOOT_FLEXSPI_NOR
@@ -88,8 +51,8 @@
config FLEXSPI_CONFIG_BLOCK_OFFSET
hex "FlexSPI config block offset"
- default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX || SOC_MIMXRT1011
default 0x0 if BOOT_FLEXSPI_NOR
+ default 0x400
help
FlexSPI configuration block consists of parameters regarding specific
flash devices including read command sequence, quad mode enablement
@@ -113,7 +76,6 @@
useful if your application expects components like SDRAM to be
initialized at boot time.
-
config EXTERNAL_MEM_CONFIG_DATA
bool "External Memory Configuration Data"
depends on !DEVICE_CONFIGURATION_DATA
@@ -143,23 +105,6 @@
an MPU region will be defined to disable cached access to the
SDRAM memory space.
-config NXP_IMX_RT_ROM_RAMLOADER
- depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER
- # Required so that debugger will load image to correct offset
- select BUILD_OUTPUT_HEX
- bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
- help
- Builds an output image that the IMX RT BootROM can load from the
- FlexSPI boot device into RAM region. The image will be loaded
- from FLEXSPI into the region specified by `zephyr,flash` node.
-
-# Setup LMA adjustment if using the RAMLOADER feature of ROM
-FLASH_CHOSEN := zephyr,flash
-FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
-FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
-config BUILD_OUTPUT_ADJUST_LMA
- default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
-
config SECOND_CORE_MCUX
bool "Dual core operation on the RT11xx series"
depends on SOC_SERIES_IMXRT11XX
@@ -171,12 +116,7 @@
generated header specifying the VMA and LMA of each memory section
to load
-
-config FLEXSPI_CONFIG_BLOCK_OFFSET
- hex
- default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
-
-if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
config PM_MCUX_GPC
bool "MCUX general power controller driver"
@@ -206,6 +146,6 @@
config INIT_SYS_PLL
bool "Initialize System PLL"
-endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
endif # SOC_FAMILY_NXP_IMXRT
diff --git a/soc/nxp/imxrt/Kconfig.defconfig b/soc/nxp/imxrt/Kconfig.defconfig
index 36f048c..68dbc89 100644
--- a/soc/nxp/imxrt/Kconfig.defconfig
+++ b/soc/nxp/imxrt/Kconfig.defconfig
@@ -7,11 +7,7 @@
# can override the defaults given here
rsource "*/Kconfig.defconfig"
-if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
-
-config SERIAL_INIT_PRIORITY
- default 55 if SERIAL
- depends on SERIAL
+if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT
@@ -75,11 +71,7 @@
endif # ETH_NXP_ENET
config MEMC
- default y
-
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_EHCI
-endchoice
+ default y if !SOC_SERIES_IMXRT118X # RT118X lacks FLEXRAM
DT_CHOSEN_Z_DTCM := zephyr,dtcm
@@ -111,42 +103,22 @@
default 1024
endif # MBEDTLS
+if CPU_CORTEX_M7
+# defaults specific for the M7 core
+
# Enable cache management features when using M7 core, since these parts
# have L1 instruction and data caches that should be enabled at boot
config CACHE_MANAGEMENT
- default y if CPU_CORTEX_M7
+ default y
-endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+config FLASH_MCUX_FLEXSPI_XIP_MEM
+ default "ITCM"
-# Logic to set flash size for all IMXRT parts
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
+config CODE_DATA_RELOCATION_SRAM
+ default n
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
+endif # CPU_CORTEX_M7
-DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
-DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
-
-config FLASH_BASE_ADDRESS
- default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
- if $(DT_FLASH_PARENT_IS_FLEXSPI)
-
-config FLASH_SIZE
- default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
- if $(DT_FLASH_HAS_SIZE_PROP)
-
-if FLASH_MCUX_FLEXSPI_XIP
-
-# Avoid RWW hazards by defaulting logging to disabled
-choice FLASH_LOG_LEVEL_CHOICE
- default FLASH_LOG_LEVEL_OFF
-endchoice
-
-choice MEMC_LOG_LEVEL_CHOICE
- default MEMC_LOG_LEVEL_OFF
-endchoice
-
-endif
+endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
endif # SOC_FAMILY_NXP_IMXRT
diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld
index b96e5e5..f91d159 100644
--- a/soc/nxp/imxrt/boot_header.ld
+++ b/soc/nxp/imxrt/boot_header.ld
@@ -4,15 +4,25 @@
* SPDX-License-Identifier: Apache-2.0
*/
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+__VECTOR_TABLE = CONFIG_ROM_START_OFFSET;
+__Vectors = __VECTOR_TABLE;
+#endif
+
. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
-#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
+#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X)
KEEP(*(.boot_hdr.conf))
#endif
#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX)
KEEP(*(.flash_conf))
#endif
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+. = CONFIG_IMAGE_CONTAINER_OFFSET;
+KEEP(*(.boot_hdr.container))
+#else
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
KEEP(*(.boot_hdr.ivt))
+#endif
#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
KEEP(*(.boot_hdr.data))
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
diff --git a/soc/nxp/imxrt/container.ld b/soc/nxp/imxrt/container.ld
new file mode 100644
index 0000000..c40a088
--- /dev/null
+++ b/soc/nxp/imxrt/container.ld
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if defined(CONFIG_SOC_SERIES_IMXRT118X) && CONFIG_NXP_IMXRT_BOOT_HEADER
+__CONTAINER_IMG_OFFSET = CONFIG_CONTAINER_USER_IMAGE_OFFSET;
+__CONTAINER_IMG_SIZE = _flash_used;
+#endif
diff --git a/soc/nxp/imxrt/flexspi_nor_config.h b/soc/nxp/imxrt/flexspi_nor_config.h
index 34ce949..1e08366 100644
--- a/soc/nxp/imxrt/flexspi_nor_config.h
+++ b/soc/nxp/imxrt/flexspi_nor_config.h
@@ -12,105 +12,102 @@
#include <zephyr/types.h>
#include "fsl_common.h"
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
-#define FLEXSPI_CFG_BLK_SIZE (512)
+#define FLEXSPI_CFG_BLK_SIZE (512)
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
+#define CMD_INDEX_WRITE 4
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
+#define CMD_LUT_SEQ_IDX_WRITE 9
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
+#define JMP_ON_CS 0x1F
+#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
- (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
- FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
- FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \
+ FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
/* For flexspi_mem_config.serialClkFreq */
#if defined(CONFIG_SOC_MIMXRT1011)
enum {
- kFlexSpiSerialClk_30MHz = 1,
- kFlexSpiSerialClk_50MHz = 2,
- kFlexSpiSerialClk_60MHz = 3,
- kFlexSpiSerialClk_75MHz = 4,
- kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
};
-#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
+#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
defined(CONFIG_SOC_MIMXRT1024)
enum {
- kFlexSpiSerialClk_30MHz = 1,
- kFlexSpiSerialClk_50MHz = 2,
- kFlexSpiSerialClk_60MHz = 3,
- kFlexSpiSerialClk_75MHz = 4,
- kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
};
-#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \
- defined(CONFIG_SOC_SERIES_IMXRT11XX)
+#elif defined(CONFIG_SOC_MIMXRT1052) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
enum {
- kFlexSpiSerialClk_30MHz = 1,
- kFlexSpiSerialClk_50MHz = 2,
- kFlexSpiSerialClk_60MHz = 3,
- kFlexSpiSerialClk_75MHz = 4,
- kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
};
-#elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \
- defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064)
+#elif defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064)
enum {
- kFlexSpiSerialClk_30MHz = 1,
- kFlexSpiSerialClk_50MHz = 2,
- kFlexSpiSerialClk_60MHz = 3,
- kFlexSpiSerialClk_75MHz = 4,
- kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
@@ -131,7 +128,7 @@
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
- kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
};
/* For flexspi_mem_config.controllerMiscOption */
@@ -139,15 +136,15 @@
/* !< Bit for Differential clock enable */
kFlexSpiMiscOffset_DiffClkEnable = 0,
/* !< Bit for CK2 enable */
- kFlexSpiMiscOffset_Ck2Enable = 1,
+ kFlexSpiMiscOffset_Ck2Enable = 1,
/* !< Bit for Parallel mode enable */
kFlexSpiMiscOffset_ParallelEnable = 2,
/* !< Bit for Word Addressable enable */
- kFlexSpiMiscOffset_WordAddressableEnable = 3,
+ kFlexSpiMiscOffset_WordAddressableEnable = 3,
/* !< Bit for Safe Configuration Frequency enable */
- kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
/* !< Bit for Pad setting override enable */
- kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
/* !< Bit for DDR clock configuration indication. */
kFlexSpiMiscOffset_DdrModeEnable = 6,
};
@@ -155,20 +152,20 @@
/* For flexspi_mem_config.deviceType */
enum {
/* !< Flash devices are Serial NOR */
- kFlexSpiDeviceType_SerialNOR = 1,
+ kFlexSpiDeviceType_SerialNOR = 1,
/* !< Flash devices are Serial NAND */
- kFlexSpiDeviceType_SerialNAND = 2,
+ kFlexSpiDeviceType_SerialNAND = 2,
/* !< Flash devices are Serial RAM/HyperFLASH */
- kFlexSpiDeviceType_SerialRAM = 3,
+ kFlexSpiDeviceType_SerialRAM = 3,
/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
- kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
};
/* For flexspi_mem_config.sflashPadType */
enum {
- kSerialFlash_1Pad = 1,
+ kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
@@ -290,27 +287,27 @@
uint32_t reserved4[4];
};
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
#define NOR_CMD_INDEX_ERASESECTOR 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
-#define NOR_CMD_INDEX_CHIPERASE 5
-#define NOR_CMD_INDEX_DUMMY 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7
+#define NOR_CMD_INDEX_CHIPERASE 5
+#define NOR_CMD_INDEX_DUMMY 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
struct flexspi_nor_config_t {
/* !< Common memory configuration info via FlexSPI */
diff --git a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
index 5eb0d46..0689025 100644
--- a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
+++ b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
@@ -18,7 +18,7 @@
if(CONFIG_MEMC_MCUX_FLEXSPI)
zephyr_sources(flexspi.c)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
- zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT)
+ zephyr_code_relocate(FILES flexspi.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
endif()
endif()
diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig
index aa5e5e7..689abea 100644
--- a/soc/nxp/imxrt/imxrt10xx/Kconfig
+++ b/soc/nxp/imxrt/imxrt10xx/Kconfig
@@ -72,16 +72,6 @@
select INIT_ARM_PLL
select INIT_SYS_PLL
-config SOC_MIMXRT1051
- select HAS_MCUX_ENET
- select HAS_MCUX_SEMC
- select CPU_HAS_FPU_DOUBLE_PRECISION
- select CPU_HAS_ARM_MPU
- select INIT_ARM_PLL
- select HAS_MCUX_USDHC1
- select HAS_MCUX_USDHC2
- select HAS_MCUX_FLEXCAN
-
config SOC_MIMXRT1052
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
@@ -98,16 +88,6 @@
select HAS_MCUX_SRC
select HAS_MCUX_XBARA
-config SOC_MIMXRT1061
- select HAS_MCUX_ENET
- select HAS_MCUX_SEMC
- select CPU_HAS_FPU_DOUBLE_PRECISION
- select CPU_HAS_ARM_MPU
- select INIT_ARM_PLL
- select HAS_MCUX_USDHC1
- select HAS_MCUX_USDHC2
- select HAS_MCUX_FLEXCAN
-
config SOC_MIMXRT1062
select HAS_MCUX_ELCDIF
select HAS_MCUX_ENET
diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig.soc b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc
index 4aa203c..4787d28 100644
--- a/soc/nxp/imxrt/imxrt10xx/Kconfig.soc
+++ b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc
@@ -28,18 +28,10 @@
bool
select SOC_SERIES_IMXRT10XX
-config SOC_MIMXRT1051
- bool
- select SOC_SERIES_IMXRT10XX
-
config SOC_MIMXRT1052
bool
select SOC_SERIES_IMXRT10XX
-config SOC_MIMXRT1061
- bool
- select SOC_SERIES_IMXRT10XX
-
config SOC_MIMXRT1062
bool
select SOC_SERIES_IMXRT10XX
@@ -54,9 +46,7 @@
default "mimxrt1021" if SOC_MIMXRT1021
default "mimxrt1024" if SOC_MIMXRT1024
default "mimxrt1042" if SOC_MIMXRT1042
- default "mimxrt1051" if SOC_MIMXRT1051
default "mimxrt1052" if SOC_MIMXRT1052
- default "mimxrt1061" if SOC_MIMXRT1061
default "mimxrt1062" if SOC_MIMXRT1062
default "mimxrt1064" if SOC_MIMXRT1064
@@ -100,22 +90,6 @@
bool
select SOC_MIMXRT1024
-config SOC_PART_NUMBER_MIMXRT1041DFP6B
- bool
- select SOC_MIMXRT1042
-
-config SOC_PART_NUMBER_MIMXRT1041DJM6B
- bool
- select SOC_MIMXRT1042
-
-config SOC_PART_NUMBER_MIMXRT1041XFP5B
- bool
- select SOC_MIMXRT1042
-
-config SOC_PART_NUMBER_MIMXRT1041XJM5B
- bool
- select SOC_MIMXRT1042
-
config SOC_PART_NUMBER_MIMXRT1042DFP6B
bool
select SOC_MIMXRT1042
@@ -132,14 +106,6 @@
bool
select SOC_MIMXRT1042
-config SOC_PART_NUMBER_MIMXRT1051CVL5A
- bool
- select SOC_MIMXRT1051
-
-config SOC_PART_NUMBER_MIMXRT1051DVL6A
- bool
- select SOC_MIMXRT1051
-
config SOC_PART_NUMBER_MIMXRT1052CVJ5B
bool
select SOC_MIMXRT1052
@@ -164,14 +130,6 @@
bool
select SOC_MIMXRT1052
-config SOC_PART_NUMBER_MIMXRT1061CVL5A
- bool
- select SOC_MIMXRT1061
-
-config SOC_PART_NUMBER_MIMXRT1061DVL6A
- bool
- select SOC_MIMXRT1061
-
config SOC_PART_NUMBER_MIMXRT1062CVJ5A
bool
select SOC_MIMXRT1062
@@ -211,24 +169,16 @@
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A
- default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B
- default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B
- default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B
- default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B
default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B
default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B
default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B
default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B
- default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
- default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B
- default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
- default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
diff --git a/soc/nxp/imxrt/imxrt118x/CMakeLists.txt b/soc/nxp/imxrt/imxrt118x/CMakeLists.txt
new file mode 100644
index 0000000..17ace76
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/CMakeLists.txt
@@ -0,0 +1,11 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(soc.c)
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig b/soc/nxp/imxrt/imxrt118x/Kconfig
new file mode 100644
index 0000000..c0cfb0b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig
@@ -0,0 +1,73 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMXRT118X
+ select CPU_CORTEX_M_HAS_DWT
+ select PLATFORM_SPECIFIC_INIT
+ select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
+ select ARM
+ select CLOCK_CONTROL
+ select HAS_MCUX_CACHE
+ select ARMV8_M_DSP if SOC_MIMXRT1189_CM33
+ select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
+ select HAS_MCUX
+ select CPU_HAS_ARM_MPU
+ select INIT_ARM_PLL
+ select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
+ select CPU_HAS_ICACHE if SOC_MIMXRT1189_CM7
+ select CPU_HAS_DCACHE if SOC_MIMXRT1189_CM7
+ select CPU_HAS_FPU
+ select CPU_HAS_FPU_DOUBLE_PRECISION if SOC_MIMXRT1189_CM7
+ select HAS_MCUX_IOMUXC
+ select HAS_SWO
+ select HAS_MCUX_FLEXSPI
+
+config SOC_MIMXRT1189_CM33
+ select CPU_CORTEX_M33
+
+config SOC_MIMXRT1189_CM7
+ select CPU_CORTEX_M7
+
+if SOC_SERIES_IMXRT118X
+
+config IMAGE_CONTAINER_OFFSET
+ hex "Image container"
+ default 0x1000
+ help
+ Image container is a boot image format that is used by ROM. Container
+ format consists container header, image arrary entry, signature block
+ and user program images and data. The boot ROM expects container data
+ to be saved in external memory.
+
+# Note- This config present the offest between container header and user
+# image. If ROM_START_OFFSET changed, you also need to change CONTAINER_USER_IMAGE_OFFSET
+# value. CONTAINER_USER_IMAGE_OFFSET = ROM_START_OFFSET - IMAGE_CONTAINER_OFFSET.
+config CONTAINER_USER_IMAGE_OFFSET
+ hex "The offset between container header and user image"
+ default 0xA000
+ help
+ The offset between container and user image. IF change the user image
+ start address, please don't forget to modify CONTAINER_USER_IMAGE_OFFSET
+ value, this will make ROM could get the user image start address.
+
+config MCUX_CORE_SUFFIX
+ default "_cm7" if SOC_MIMXRT1189_CM7
+ default "_cm33" if SOC_MIMXRT1189_CM33
+
+config TRDC_MCUX_TRDC
+ default y
+ bool "Use TRDC MCUX Driver"
+
+config S3MU_MCUX_S3MU
+ default y
+ bool "Use S3MU MCUX Driver"
+
+config IMXRT118X_CM33_XCACHE_PS
+ bool "Use CM33 XCACHE_PS"
+ default y if SOC_MIMXRT1189_CM33
+ help
+ Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been
+ enabled in SystemInit function. If this Kconfig is cleared,
+ the XCACHE controller won't be enabled during SOC init
+
+endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
new file mode 100644
index 0000000..ee93054
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
@@ -0,0 +1,37 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_IMXRT118X
+
+config NUM_IRQS
+ default 239
+
+config GPIO
+ default y
+
+if CORTEX_M_SYSTICK
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 240000000 if SOC_MIMXRT1189_CM33
+ default 792000000 if SOC_MIMXRT1189_CM7
+
+endif # CORTEX_M_SYSTICK
+
+config DCDC_VALUE
+ default 0x13
+
+config FLEXSPI_CONFIG_BLOCK_OFFSET
+ default 0x400 if BOOT_FLEXSPI_NOR
+
+config ROM_START_OFFSET
+ default 0xb000 if BOOT_FLEXSPI_NOR
+
+if SECOND_CORE_MCUX
+
+# RT Boot header is only needed on primary core
+config NXP_IMXRT_BOOT_HEADER
+ depends on !CPU_CORTEX_M7
+
+endif # SECOND_CORE_MCUX
+
+endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig.soc b/soc/nxp/imxrt/imxrt118x/Kconfig.soc
new file mode 100644
index 0000000..0d2774b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig.soc
@@ -0,0 +1,62 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMXRT118X
+ bool
+ select SOC_FAMILY_NXP_IMXRT
+
+config SOC_SERIES
+ default "imxrt118x" if SOC_SERIES_IMXRT118X
+
+config SOC_MIMXRT1189
+ bool
+ select SOC_SERIES_IMXRT118X
+
+config SOC_MIMXRT1189_CM33
+ bool
+ select SOC_MIMXRT1189
+
+config SOC_MIMXRT1189_CM7
+ bool
+ select SOC_MIMXRT1189
+
+config SOC
+ default "mimxrt1189" if SOC_MIMXRT1189
+
+config SOC_PART_NUMBER_MIMXRT1189CVM8B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1189XVM8B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1187AVM8B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1187CVM8B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1187XVM8B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1182CVP2B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1182XVP2B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1181CVP2B
+ bool
+
+config SOC_PART_NUMBER_MIMXRT1181XVP2B
+ bool
+
+config SOC_PART_NUMBER
+ default "MIMXRT1189CVM8B" if SOC_PART_NUMBER_MIMXRT1189CVM8B
+ default "MIMXRT1189XVM8B" if SOC_PART_NUMBER_MIMXRT1189XVM8B
+ default "MIMXRT1187AVM8B" if SOC_PART_NUMBER_MIMXRT1187AVM8B
+ default "MIMXRT1187CVM8B" if SOC_PART_NUMBER_MIMXRT1187CVM8B
+ default "MIMXRT1187XVM8B" if SOC_PART_NUMBER_MIMXRT1187XVM8B
+ default "MIMXRT1182CVP2B" if SOC_PART_NUMBER_MIMXRT1182CVP2B
+ default "MIMXRT1182XVP2B" if SOC_PART_NUMBER_MIMXRT1182XVP2B
+ default "MIMXRT1181CVP2B" if SOC_PART_NUMBER_MIMXRT1181CVP2B
+ default "MIMXRT1181XVP2B" if SOC_PART_NUMBER_MIMXRT1181XVP2B
diff --git a/soc/nxp/imxrt/imxrt118x/linker.ld b/soc/nxp/imxrt/imxrt118x/linker.ld
new file mode 100644
index 0000000..a7e5123
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/linker.ld
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+
+
+#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
+
+MEMORY
+ {
+
+#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
+ SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))
+#endif
+
+ }
+
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
diff --git a/soc/nxp/imxrt/imxrt118x/pinctrl_soc.h b/soc/nxp/imxrt/imxrt118x/pinctrl_soc.h
new file mode 100644
index 0000000..797e62e
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/pinctrl_soc.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
+#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+#include "fsl_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MCUX_IMX_ODE_SHIFT 4
+#define MCUX_IMX_PUS_SHIFT 3
+#define MCUX_IMX_PUE_SHIFT 2
+#define MCUX_IMX_DSE_SHIFT 1
+#define MCUX_IMX_SRE_SHIFT 0
+#define MCUX_IMX_PULL_SHIFT 2
+#define MCUX_IMX_PULL_PULLDOWN 0x2
+#define MCUX_IMX_PULL_PULLUP 0x1
+#define MCUX_IMX_PDRV_SHIFT 1
+#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
+#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
+
+
+/*
+ * RT11xx has multiple types of register layouts defined for pin configuration
+ * registers. There are four types defined:
+ * pdrv_pull: registers lack a slew rate and pus field
+ * pue_pus: registers have a slew rate and ode field
+ * pue_pus_lpsr: in low power state retention domain, shifted ode field
+ * pue_pus_snvs: in SNVS domain, shifted ode field
+ */
+
+#define MCUX_IMX_PUS_PUE 0
+#define MCUX_IMX_PDRV_PULL 1
+#define MCUX_IMX_LPSR 2
+#define MCUX_IMX_SNVS 3
+
+/*
+ * Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two
+ * properties are false
+ */
+#define MCUX_IMX_NOPULL(node_id) \
+ ((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
+ (0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \
+
+#define Z_PINCTRL_MCUX_IMX_PDRV(node_id) \
+ IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
+ (MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |) \
+ IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
+ (MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |) \
+ (MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) | \
+ (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_PDRV_SHIFT) | \
+ (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
+ (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
+
+#define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id) \
+ (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
+ ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
+ << MCUX_IMX_PUE_SHIFT) | \
+ (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
+ (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
+ (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
+ (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
+
+/* This struct must be present. It is used by the mcux gpio driver */
+struct pinctrl_soc_pinmux {
+ uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
+ uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
+ uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
+ uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
+ uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
+ uint8_t pue_mux: 1; /* Is pinmux reg pue type */
+ uint8_t pdrv_mux: 1; /* Is pinmux reg pdrv type */
+};
+
+struct pinctrl_soc_pin {
+ struct pinctrl_soc_pinmux pinmux;
+ uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
+};
+
+typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/* This definition must be present. It is used by the mcux gpio driver */
+#define MCUX_IMX_PINMUX(node_id) \
+ { \
+ .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
+ .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
+ .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
+ .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
+ .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
+ .pue_mux = DT_PROP(node_id, pin_pue), \
+ .pdrv_mux = DT_PROP(node_id, pin_pdrv), \
+ }
+
+#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
+ MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+
+#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
+ { \
+ .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
+IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
+ (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),)) \
+IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \
+ (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),)) \
+ },
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
+ {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
+ DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_ */
diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c
new file mode 100644
index 0000000..d721b83
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/soc.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/linker-defs.h>
+#if defined(CONFIG_SOC_MIMXRT1189_CM7)
+#include <zephyr/cache.h>
+#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
+#include <fsl_cache.h>
+#endif
+#include <fsl_clock.h>
+#include <fsl_gpc.h>
+#include <fsl_pmu.h>
+#include <fsl_dcdc.h>
+#include <fsl_ele_base_api.h>
+#include <fsl_trdc.h>
+#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
+#include <cmsis_core.h>
+
+/*
+ * Set ELE_STICK_FAILED_STS to 0 when ELE status check is not required,
+ * which is useful when debug reset, where the core has already get the
+ * TRDC ownership at first time and ELE is not able to release TRDC
+ * ownership again for the following TRDC ownership request.
+ */
+#define ELE_STICK_FAILED_STS 1
+
+#if ELE_STICK_FAILED_STS
+#define ELE_IS_FAILED(x) (x != kStatus_Success)
+#else
+#define ELE_IS_FAILED(x) false
+#endif
+
+#define ELE_TRDC_AON_ID 0x74
+#define ELE_TRDC_WAKEUP_ID 0x78
+#define ELE_CORE_CM33_ID 0x1
+#define ELE_CORE_CM7_ID 0x2
+
+#ifdef CONFIG_INIT_ARM_PLL
+static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33) || defined(CONFIG_SOC_MIMXRT1189_CM7)
+ /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+ .postDivider = kCLOCK_PllPostDiv2,
+ /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+ .loopDivider = 132,
+#else
+ #error "Unknown SOC, no pll configuration defined"
+#endif
+};
+#endif
+
+const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = {
+ /* Enable Sys Pll1 divide-by-2 clock or not */
+ .pllDiv2En = 1,
+ /* Enable Sys Pll1 divide-by-5 clock or not */
+ .pllDiv5En = 1,
+ /* Spread spectrum parameter */
+ .ss = NULL,
+ /* Enable spread spectrum or not */
+ .ssEnable = false,
+};
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = {
+ /* Denominator of spread spectrum */
+ .mfd = 268435455,
+ /* Spread spectrum parameter */
+ .ss = NULL,
+ /* Enable spread spectrum or not */
+ .ssEnable = false,
+};
+
+/**
+ * @brief Initialize the system clock
+ */
+static ALWAYS_INLINE void clock_init(void)
+{
+ clock_root_config_t rootCfg = {0};
+
+ /* Init OSC RC 400M */
+ CLOCK_OSC_EnableOscRc400M();
+ CLOCK_OSC_GateOscRc400M(false);
+
+#if CONFIG_CPU_CORTEX_M7
+ /* Switch both core to OscRC400M first */
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M33
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M7
+ DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE0, kDCDC_1P0Target1P1V);
+ DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE1, kDCDC_1P0Target1P1V);
+ /* FBB need to be enabled in OverDrive(OD) mode */
+ PMU_EnableFBB(ANADIG_PMU, true);
+#endif
+
+ /* Config CLK_1M */
+ CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+ /* Init OSC RC 24M */
+ CLOCK_OSC_EnableOscRc24M(true);
+
+ /* Config OSC 24M */
+ ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |
+ ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) |
+ ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+
+ /* Wait for 24M OSC to be stable. */
+ while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+ (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
+ }
+
+#ifdef CONFIG_INIT_ARM_PLL
+ /* Init Arm Pll. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+#endif
+
+ /* Init Sys Pll1. */
+ CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
+
+ /* Init Sys Pll2. */
+ CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+ /* Init System Pll2 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+ /* Init System Pll2 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+ /* Init System Pll2 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+ /* Init System Pll2 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+ /* Init Sys Pll3. */
+ CLOCK_InitSysPll3();
+ /* Init System Pll3 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22);
+ /* Init System Pll3 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33);
+ /* Init System Pll3 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22);
+ /* Init System Pll3 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18);
+
+ /* Bypass Audio Pll. */
+ CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+ /* DeInit Audio Pll. */
+ CLOCK_DeinitAudioPll();
+
+#if defined(CONFIG_SOC_MIMXRT1189_CM7)
+ /* Module clock root configurations. */
+ /* Configure M7 using ARM_PLL_CLK */
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+ /* Configure M33 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+ /* Configure BUS_AON using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg);
+
+ /* Configure BUS_WAKEUP using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg);
+
+ /* Configure WAKEUP_AXI using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg);
+
+ /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg);
+
+#if CONFIG_CPU_CORTEX_M33
+ /* Configure M33_SYSTICK using OSC_24M */
+ rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M7
+ /* Configure M7_SYSTICK using OSC_24M */
+ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+#if defined(CONFIG_UART_MCUX_LPUART) && \
+ (DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) \
+ || DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay))
+ /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+#endif
+
+#if defined(CONFIG_I2C_MCUX_LPI2C) && \
+ (DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) \
+ || DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c2), okay))
+ /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg);
+#endif
+
+#if defined(CONFIG_I2C_MCUX_LPI2C) && \
+ (DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c3), okay) \
+ || DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c4), okay))
+ /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg);
+#endif
+
+#if defined(CONFIG_I2C_MCUX_LPI2C) && \
+ (DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c5), okay) \
+ || DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c6), okay))
+ /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
+#endif
+
+#if defined(CONFIG_SPI_MCUX_LPSPI) && \
+ (DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) \
+ || DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi2), okay))
+ /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
+ rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
+#endif
+
+ /* Keep core clock ungated during WFI */
+ CCM->LPCG[1].LPM0 = 0x33333333;
+ CCM->LPCG[1].LPM1 = 0x33333333;
+ /* Keep the system clock running so SYSTICK can wake up
+ * the system from wfi.
+ */
+ GPC_CM_SetNextCpuMode(0, kGPC_RunMode);
+ GPC_CM_SetNextCpuMode(1, kGPC_RunMode);
+ GPC_CM_EnableCpuSleepHold(0, false);
+ GPC_CM_EnableCpuSleepHold(1, false);
+
+#if !defined(CONFIG_PM)
+ /* Enable the AHB clock while the CM7 is sleeping to allow debug access
+ * to TCM
+ */
+ BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;
+#endif
+}
+
+/**
+ * @brief Initialize the system clock
+ */
+static ALWAYS_INLINE void trdc_enable_all_access(void)
+{
+ status_t sts;
+ uint8_t i, j;
+
+ /* Get ELE FW status */
+ do {
+ uint32_t ele_fw_sts;
+
+ sts = ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts);
+ } while (sts != kStatus_Success);
+
+ do {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+ /* Release TRDC A to CM33 core */
+ sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM33_ID);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+ /* Release TRDC A to CM7 core */
+ sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM7_ID);
+#endif
+ } while (ELE_IS_FAILED(sts));
+
+ /* Release TRDC W to CM33 core */
+ do {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+ /* Release TRDC A to CM33 core */
+ sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM33_ID);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+ /* Release TRDC A to CM7 core */
+ sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM7_ID);
+#endif
+ } while (ELE_IS_FAILED(sts));
+
+ /* Enable all access modes for MBC and MRC of TRDCA and TRDCW */
+ trdc_hardware_config_t hwConfig;
+ trdc_memory_access_control_config_t memAccessConfig;
+
+ (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
+ memAccessConfig.nonsecureUsrX = 1U;
+ memAccessConfig.nonsecureUsrW = 1U;
+ memAccessConfig.nonsecureUsrR = 1U;
+ memAccessConfig.nonsecurePrivX = 1U;
+ memAccessConfig.nonsecurePrivW = 1U;
+ memAccessConfig.nonsecurePrivR = 1U;
+ memAccessConfig.secureUsrX = 1U;
+ memAccessConfig.secureUsrW = 1U;
+ memAccessConfig.secureUsrR = 1U;
+ memAccessConfig.securePrivX = 1U;
+ memAccessConfig.securePrivW = 1U;
+ memAccessConfig.securePrivR = 1U;
+
+ TRDC_GetHardwareConfig(TRDC1, &hwConfig);
+ for (i = 0U; i < hwConfig.mrcNumber; i++) {
+ for (j = 0U; j < 8; j++) {
+ TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+ }
+ }
+
+ for (i = 0U; i < hwConfig.mbcNumber; i++) {
+ for (j = 0U; j < 8; j++) {
+ TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+ }
+ }
+
+ TRDC_GetHardwareConfig(TRDC2, &hwConfig);
+ for (i = 0U; i < hwConfig.mrcNumber; i++) {
+ for (j = 0U; j < 8; j++) {
+ TRDC_MrcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
+ }
+ }
+
+ for (i = 0U; i < hwConfig.mbcNumber; i++) {
+ for (j = 0U; j < 8; j++) {
+ TRDC_MbcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
+ }
+ }
+}
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ * If dual core operation is enabled, the second core image will be loaded to RAM
+ *
+ * @return 0
+ */
+
+static int imxrt_init(void)
+{
+ /* Initialize system clock */
+ clock_init();
+ /* Get trdc and enable all access modes for MBC and MRC of TRDCA and TRDCW */
+ trdc_enable_all_access();
+
+ /* Enable data cache */
+#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
+ XCACHE_EnableCache(XCACHE_PS);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+ sys_cache_data_enable();
+#endif
+ __ISB();
+ __DSB();
+
+ return 0;
+}
+
+#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+void z_arm_platform_init(void)
+{
+ SystemInit();
+}
+#endif
+
+SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);
diff --git a/soc/nxp/imxrt/imxrt118x/soc.h b/soc/nxp/imxrt/imxrt118x/soc.h
new file mode 100644
index 0000000..272227b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/soc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+
+#include <fsl_common.h>
+
+/* Add include for DTS generated information */
+#include <zephyr/devicetree.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */
diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig
index 9bd7440..7751ddf 100644
--- a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig
@@ -33,4 +33,5 @@
depends on !(CPU_CORTEX_M4 || BOOTLOADER_MCUBOOT)
endif
+
endif
diff --git a/soc/nxp/imxrt/imxrt11xx/power.c b/soc/nxp/imxrt/imxrt11xx/power.c
index af7ee9d..04209b8 100644
--- a/soc/nxp/imxrt/imxrt11xx/power.c
+++ b/soc/nxp/imxrt/imxrt11xx/power.c
@@ -8,7 +8,7 @@
#include <zephyr/pm/pm.h>
#include <fsl_dcdc.h>
#include <fsl_gpc.h>
-#include <zephyr/dt-bindings/pm/imx_spc.h>
+#include <zephyr/dt-bindings/power/imx_spc.h>
#include "power.h"
#include <zephyr/logging/log.h>
diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c
index b8c685a..b13f7df 100644
--- a/soc/nxp/imxrt/imxrt11xx/soc.c
+++ b/soc/nxp/imxrt/imxrt11xx/soc.c
@@ -264,12 +264,14 @@
#ifdef CONFIG_INIT_ENET_PLL
CLOCK_InitSysPll1(&sysPll1Config);
#else
+#ifndef CONFIG_SECOND_CORE_MCUX
/* Bypass Sys Pll1. */
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
/* DeInit Sys Pll1. */
CLOCK_DeinitSysPll1();
#endif
+#endif
/* Init Sys Pll2. */
CLOCK_InitSysPll2(&sysPll2Config);
@@ -284,11 +286,7 @@
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
/* Init System Pll2 pfd3. */
-#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
- CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
-#else
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
-#endif
/* Init Sys Pll3. */
CLOCK_InitSysPll3();
@@ -330,17 +328,16 @@
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
- /* Configure BUS using SYS_PLL3_CLK */
-#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
- /* Configure root bus clock at 198M */
- rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
- rootCfg.div = 2;
- CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
-#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
+#if CONFIG_SOC_MIMXRT1176_CM7
/* Keep root bus clock at default 240M */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
+#elif defined(CONFIG_SOC_MIMXRT1166_CM7)
+ /* Configure root bus clock at 200M */
+ rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
#endif
/* Configure BUS_LPSR using SYS_PLL3_CLK */
diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
index e99289a..a93f307 100644
--- a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
@@ -14,10 +14,6 @@
config ZTEST_NO_YIELD
default y if (PM && ZTEST)
-# Code relocation is needed for flash clock setup
-config CODE_DATA_RELOCATION_SRAM
- default y
-
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
@@ -50,10 +46,6 @@
endif # CORTEX_M_SYSTICK
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
if PM_DEVICE
# Enable the MEMC FlexSPI driver when using device power
# management so we can reconfigure the FlexSPI pins to
diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
index c47971c..dc952c5 100644
--- a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
+++ b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
@@ -10,10 +10,9 @@
zephyr_include_directories(.)
-zephyr_sources(
- soc.c
- flash_clock_setup.c
- )
+zephyr_sources(soc.c)
+
+zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c)
zephyr_sources_ifdef(CONFIG_PM power.c)
diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig
index 48a8d4c..151e99d 100644
--- a/soc/nxp/imxrt/imxrt6xx/Kconfig
+++ b/soc/nxp/imxrt/imxrt6xx/Kconfig
@@ -6,7 +6,6 @@
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_DWT
select CLOCK_CONTROL
- select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP
select PLATFORM_SPECIFIC_INIT
select HAS_PM
select CPU_HAS_ARM_SAU
diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
index 83d9604..9aa1542 100644
--- a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
@@ -28,53 +28,6 @@
config ZTEST_NO_YIELD
default y if (ZTEST && PM)
-# Setup LMA adjustment if using the RAMLOADER feature of ROM
-FLASH_CHOSEN := zephyr,flash
-FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
-FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
-config BUILD_OUTPUT_ADJUST_LMA
- default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
-
-# The base address is determined from the zephyr,flash node with the following
-# precedence:
-# FlexSPI base address (if flash node is on a FlexSPI bus)
-# node reg property (used for memory regions such as SRAM)
-
-# Workaround for not being able to have commas in macro arguments
-
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
-
-# Macros to shorten Kconfig definitions
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
-
-config FLASH_BASE_ADDRESS
- default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
- if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
- default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
-
-# The RT6xx has no internal flash. If the flash node has a size property,
-# use that over the reg property. This is used for the external flash
-# present on the board. Otherwise, fallback to the reg property
-config FLASH_SIZE
- default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
- if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
- default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
-
-if FLASH_MCUX_FLEXSPI_XIP
-
-# Avoid RWW hazards by defaulting logging to disabled
-choice FLASH_LOG_LEVEL_CHOICE
- default FLASH_LOG_LEVEL_OFF
-endchoice
-
-choice MEMC_LOG_LEVEL_CHOICE
- default MEMC_LOG_LEVEL_OFF
-endchoice
-
-endif
-
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
@@ -110,8 +63,4 @@
endif # CORTEX_M_SYSTICK
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
endif # SOC_MIMXRT685S_CM33
diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml
index 3b8b3e0..2fd2a0d 100644
--- a/soc/nxp/imxrt/soc.yml
+++ b/soc/nxp/imxrt/soc.yml
@@ -8,9 +8,7 @@
- name: mimxrt1021
- name: mimxrt1024
- name: mimxrt1042
- - name: mimxrt1051
- name: mimxrt1052
- - name: mimxrt1061
- name: mimxrt1062
- name: mimxrt1064
- name: imxrt11xx
@@ -23,6 +21,12 @@
cpuclusters:
- name: cm7
- name: cm4
+ - name: imxrt118x
+ socs:
+ - name: mimxrt1189
+ cpuclusters:
+ - name: cm33
+ - name: cm7
- name: imxrt5xx
socs:
- name: mimxrt595s
diff --git a/soc/nxp/kinetis/Kconfig.defconfig b/soc/nxp/kinetis/Kconfig.defconfig
index 33f477c..42d803d 100644
--- a/soc/nxp/kinetis/Kconfig.defconfig
+++ b/soc/nxp/kinetis/Kconfig.defconfig
@@ -3,14 +3,6 @@
if SOC_FAMILY_KINETIS
-config SERIAL_INIT_PRIORITY
- default 55
- depends on SERIAL
-
-config ADC_INIT_PRIORITY
- default 80 if ADC_MCUX_ADC16_ENABLE_EDMA
- depends on ADC
-
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_KINETIS
diff --git a/soc/nxp/kinetis/common/pinctrl_soc.h b/soc/nxp/kinetis/common/pinctrl_soc.h
index 9caa761..9a6c343 100644
--- a/soc/nxp/kinetis/common/pinctrl_soc.h
+++ b/soc/nxp/kinetis/common/pinctrl_soc.h
@@ -1,72 +1,7 @@
/*
- * Copyright (c) 2022, 2024 NXP
+ * Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
-/*
- * @file
- * NXP Kinetis SOC specific helpers for pinctrl driver
- */
-
-#ifndef ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
-#define ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
-
-#include <zephyr/devicetree.h>
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @cond INTERNAL_HIDDEN */
-
-typedef uint32_t pinctrl_soc_pin_t;
-
-/* Kinetis KW/KL/KE series does not support open drain. Define macros to have no effect
- * Note: KW22 and KW24 do support open drain, rest of KW series does not
- */
-#if (defined(CONFIG_SOC_SERIES_KINETIS_KWX) && \
- !(defined(CONFIG_SOC_MKW24D5) || \
- defined(CONFIG_SOC_MKW22D5))) || \
- defined(CONFIG_SOC_SERIES_KINETIS_KL2X) || \
- defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || \
- defined(CONFIG_SOC_SERIES_KE1XZ)
-#define PORT_PCR_ODE(x) 0x0
-#define PORT_PCR_ODE_MASK 0x0
-#endif
-
-/* Kinetis KE series does not support slew rate. Define macros to have no effect */
-#if defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || \
- defined(CONFIG_SOC_SERIES_KE1XZ)
-#define PORT_PCR_SRE(x) 0x0
-#define PORT_PCR_SRE_MASK 0x0
-#endif
-
-#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
- (PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
- PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
- PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
- PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
- PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
- PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
- PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
-
-#define Z_PINCTRL_KINETIS_PCR_MASK \
- (PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | \
- PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | \
- PORT_PCR_PS_MASK)
-
-
-#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
- DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
-
-#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
- {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
- DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ */
+#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
diff --git a/soc/nxp/kinetis/ke1xz/CMakeLists.txt b/soc/nxp/kinetis/ke1xz/CMakeLists.txt
index 116e67f..5c46d06 100644
--- a/soc/nxp/kinetis/ke1xz/CMakeLists.txt
+++ b/soc/nxp/kinetis/ke1xz/CMakeLists.txt
@@ -8,6 +8,11 @@
soc.c
)
+zephyr_sources_ifdef(
+ CONFIG_PM
+ power.c
+)
+
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
zephyr_include_directories(.)
diff --git a/soc/nxp/kinetis/ke1xz/Kconfig b/soc/nxp/kinetis/ke1xz/Kconfig
index 9e01b9e..751257f 100644
--- a/soc/nxp/kinetis/ke1xz/Kconfig
+++ b/soc/nxp/kinetis/ke1xz/Kconfig
@@ -12,3 +12,4 @@
select CLOCK_CONTROL
select HAS_MCUX
select PLATFORM_SPECIFIC_INIT
+ select HAS_PM
diff --git a/soc/nxp/kinetis/ke1xz/Kconfig.defconfig b/soc/nxp/kinetis/ke1xz/Kconfig.defconfig
index 3077b6e..a3df8c2 100644
--- a/soc/nxp/kinetis/ke1xz/Kconfig.defconfig
+++ b/soc/nxp/kinetis/ke1xz/Kconfig.defconfig
@@ -6,8 +6,15 @@
if SOC_SERIES_KE1XZ
+config MCUX_LPTMR_TIMER
+ default y if PM
+
+config CORTEX_M_SYSTICK
+ default n if MCUX_LPTMR_TIMER
+
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+ default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER
config NUM_IRQS
default 32
diff --git a/soc/nxp/kinetis/ke1xz/power.c b/soc/nxp/kinetis/ke1xz/power.c
new file mode 100644
index 0000000..43aef2e
--- /dev/null
+++ b/soc/nxp/kinetis/ke1xz/power.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021 Vestas Wind Systems A/S
+ * Copyright 2021, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/pm.h>
+#include <soc.h>
+
+LOG_MODULE_DECLARE(power, CONFIG_PM_LOG_LEVEL);
+
+__ramfunc static void wait_for_flash_prefetch_and_idle(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < 8; i++) {
+ arch_nop();
+ }
+
+ k_cpu_idle();
+}
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+ switch (state) {
+ case PM_STATE_RUNTIME_IDLE:
+ k_cpu_idle();
+ break;
+ case PM_STATE_SUSPEND_TO_IDLE:
+ /* Set partial stop mode and enable deep sleep */
+ SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(substate_id);
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ if (IS_ENABLED(CONFIG_XIP)) {
+ wait_for_flash_prefetch_and_idle();
+ } else {
+ k_cpu_idle();
+ }
+ if (SMC->PMCTRL & SMC_PMCTRL_STOPA_MASK) {
+ LOG_DBG("partial stop aborted");
+ }
+ break;
+ default:
+ LOG_WRN("Unsupported power state %u", state);
+ break;
+ }
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+ ARG_UNUSED(substate_id);
+
+ if (state == PM_STATE_SUSPEND_TO_IDLE) {
+ /* Disable deep sleep upon exit */
+ SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
+ }
+
+ irq_unlock(0);
+}
diff --git a/soc/nxp/lpc/Kconfig.defconfig b/soc/nxp/lpc/Kconfig.defconfig
index ca61dec..125f3ea 100644
--- a/soc/nxp/lpc/Kconfig.defconfig
+++ b/soc/nxp/lpc/Kconfig.defconfig
@@ -3,9 +3,6 @@
if SOC_FAMILY_LPC
-config SERIAL_INIT_PRIORITY
- default 55 if SERIAL
-
config BUILD_WITH_TFM
default y if TRUSTED_EXECUTION_NONSECURE
diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig b/soc/nxp/lpc/lpc55xxx/Kconfig
index cc643ed..351b2bb 100644
--- a/soc/nxp/lpc/lpc55xxx/Kconfig
+++ b/soc/nxp/lpc/lpc55xxx/Kconfig
@@ -31,6 +31,18 @@
select HAS_MCUX_MCAN
select HAS_MCUX_RNG
+config SOC_LPC55S26
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_SAU
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select HAS_MCUX_IAP
+ select HAS_MCUX_LPADC
+ select HAS_MCUX_LPC_DMA
+ select HAS_MCUX_RNG
+ select HAS_MCUX_SCTIMER
+
config SOC_LPC55S28
select CPU_CORTEX_M33
select CPU_HAS_ARM_SAU
@@ -41,6 +53,7 @@
select HAS_MCUX_LPADC
select HAS_MCUX_LPC_DMA
select HAS_MCUX_RNG
+ select HAS_MCUX_SCTIMER
config SOC_LPC55S36
select CPU_CORTEX_M33
diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig
index fa7c9d6..0decc5a 100644
--- a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig
+++ b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig
@@ -19,7 +19,6 @@
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
-
# Move the LMA for the second core image to be in the flash region of primary
# core, so that JLink flash will load it correctly.
config BUILD_OUTPUT_ADJUST_LMA
@@ -52,28 +51,8 @@
default y
depends on CAN
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
endif # SOC_LPC55S16
-if SOC_LPC55S28
-
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
-endif # SOC_LPC55S28
-
-if SOC_LPC55S36
-
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
-endif # SOC_LPC55S36
-
if SOC_LPC55S69
config SOC_FLASH_MCUX
@@ -81,10 +60,6 @@
depends on FLASH
depends on !TRUSTED_EXECUTION_NONSECURE
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_LPCIP3511
-endchoice
-
config I2S_MCUX_FLEXCOMM
select INIT_PLL0
@@ -92,7 +67,6 @@
if SOC_LPC55S69_CPU1
-
config GPIO
default y
diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.soc b/soc/nxp/lpc/lpc55xxx/Kconfig.soc
index e5b668b..f05b751 100644
--- a/soc/nxp/lpc/lpc55xxx/Kconfig.soc
+++ b/soc/nxp/lpc/lpc55xxx/Kconfig.soc
@@ -16,6 +16,10 @@
bool
select SOC_SERIES_LPC55XXX
+config SOC_LPC55S26
+ bool
+ select SOC_SERIES_LPC55XXX
+
config SOC_LPC55S28
bool
select SOC_SERIES_LPC55XXX
@@ -40,6 +44,7 @@
default "lpc55s69" if SOC_LPC55S69_CPU0 || SOC_LPC55S69_CPU1
default "lpc55s06" if SOC_LPC55S06
default "lpc55s16" if SOC_LPC55S16
+ default "lpc55s26" if SOC_LPC55S26
default "lpc55s28" if SOC_LPC55S28
default "lpc55s36" if SOC_LPC55S36
@@ -52,6 +57,12 @@
config SOC_PART_NUMBER_LPC55S16JBD100
bool
+config SOC_PART_NUMBER_LPC55S26JBD64
+ bool
+
+config SOC_PART_NUMBER_LPC55S26JBD100
+ bool
+
config SOC_PART_NUMBER_LPC55S28JBD100
bool
@@ -68,6 +79,8 @@
default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64
default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64
default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100
+ default "LPC55S26JBD64" if SOC_PART_NUMBER_LPC55S26JBD64
+ default "LPC55S26JBD100" if SOC_PART_NUMBER_LPC55S26JBD100
default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100
default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100
default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
diff --git a/soc/nxp/lpc/lpc55xxx/soc.c b/soc/nxp/lpc/lpc55xxx/soc.c
index 1dad08a..f920168 100644
--- a/soc/nxp/lpc/lpc55xxx/soc.c
+++ b/soc/nxp/lpc/lpc55xxx/soc.c
@@ -88,8 +88,8 @@
#endif
#if defined(CONFIG_SOC_LPC55S06) || defined(CONFIG_SOC_LPC55S16) || \
- defined(CONFIG_SOC_LPC55S28) || defined(CONFIG_SOC_LPC55S36) || \
- defined(CONFIG_SOC_LPC55S69_CPU0)
+ defined(CONFIG_SOC_LPC55S26) || defined(CONFIG_SOC_LPC55S28) || \
+ defined(CONFIG_SOC_LPC55S36) || defined(CONFIG_SOC_LPC55S69_CPU0)
/* Set up the clock sources */
/* Configure FRO192M */
/* Ensure FRO is on */
@@ -269,6 +269,8 @@
DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
+DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
+
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay))
#if defined(CONFIG_SOC_LPC55S36)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom6Clk, 0U, true);
diff --git a/soc/nxp/lpc/soc.yml b/soc/nxp/lpc/soc.yml
index be9d9c9..7d970af 100644
--- a/soc/nxp/lpc/soc.yml
+++ b/soc/nxp/lpc/soc.yml
@@ -19,6 +19,7 @@
socs:
- name: lpc55s06
- name: lpc55s16
+ - name: lpc55s26
- name: lpc55s28
- name: lpc55s36
- name: lpc55s69
diff --git a/soc/nxp/mcx/Kconfig b/soc/nxp/mcx/Kconfig
index 3bf1d3a..ea81009 100644
--- a/soc/nxp/mcx/Kconfig
+++ b/soc/nxp/mcx/Kconfig
@@ -1,46 +1,15 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
-config SOC_FAMILY_NXP_MCX
- select HAS_SEGGER_RTT
- select CLOCK_CONTROL
- select ARM
+# Do NOT select anything from the MCX family kconfig,
+# and do not make it a dependency of anything else.
+# If there is some similarity between series,
+# use if SERIES_A || SERIES_B or something of that
+# effect rather than the family config.
+# This is because MCX series is expected to be very diverse.
if SOC_FAMILY_NXP_MCX
rsource "*/Kconfig"
-if FLASH_MCUX_FLEXSPI_XIP
-
-# Avoid RWW hazards by defaulting logging to disabled
-choice FLASH_LOG_LEVEL_CHOICE
- default FLASH_LOG_LEVEL_OFF
-endchoice
-
-choice MEMC_LOG_LEVEL_CHOICE
- default MEMC_LOG_LEVEL_OFF
-endchoice
-
-endif
-
-if FLASH_MCUX_FLEXSPI_XIP
-
-# Code relocation is needed when FLASH_MCUX_FLEXSPI_XIP is enabled
-config CODE_DATA_RELOCATION_SRAM
- default y
-
-config FLASH_MCUX_FLEXSPI_XIP_MEM
- string
- default "RAM"
-
-endif # FLASH_MCUX_FLEXSPI_XIP
-
-config MFD
- default y
- depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED
-
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_EHCI
-endchoice
-
endif # SOC_FAMILY_NXP_MCX
diff --git a/soc/nxp/mcx/Kconfig.defconfig b/soc/nxp/mcx/Kconfig.defconfig
index 9e41c34..245cef6 100644
--- a/soc/nxp/mcx/Kconfig.defconfig
+++ b/soc/nxp/mcx/Kconfig.defconfig
@@ -1,12 +1,15 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
+#
+# Do NOT select anything from the MCX family kconfig,
+# and do not make it a dependency of anything else.
+# If there is some similarity between series,
+# use if SERIES_A || SERIES_B or something of that
+# effect rather than the family config.
+# This is because MCX series is expected to be very diverse.
if SOC_FAMILY_NXP_MCX
-config SERIAL_INIT_PRIORITY
- default 55
- depends on SERIAL
-
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_NXP_MCX
diff --git a/soc/nxp/mcx/mcxnx4x/CMakeLists.txt b/soc/nxp/mcx/mcxn/CMakeLists.txt
similarity index 100%
rename from soc/nxp/mcx/mcxnx4x/CMakeLists.txt
rename to soc/nxp/mcx/mcxn/CMakeLists.txt
diff --git a/soc/nxp/mcx/mcxn/Kconfig b/soc/nxp/mcx/mcxn/Kconfig
new file mode 100644
index 0000000..04b41f7
--- /dev/null
+++ b/soc/nxp/mcx/mcxn/Kconfig
@@ -0,0 +1,54 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXN
+ select HAS_SEGGER_RTT
+ select CLOCK_CONTROL
+ select ARM
+ select HAS_MCUX
+ select HAS_MCUX_FLEXCOMM
+ select CPU_CORTEX_M_HAS_SYSTICK
+ select CPU_CORTEX_M_HAS_DWT
+ select PLATFORM_SPECIFIC_INIT
+
+config SOC_MCXN947_CPU0
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_SAU
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select ARM_TRUSTZONE_M
+ select HAS_MCUX_CACHE
+
+config SOC_MCXN236
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_SAU
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select ARM_TRUSTZONE_M
+ select HAS_MCUX_CACHE
+
+if SOC_SERIES_MCXN
+
+if SOC_MCXN947
+config SECOND_CORE_MCUX
+ bool "MCXN94X's second core"
+ depends on HAS_MCUX
+ help
+ Indicates the second core will be enabled, and the part will run
+ in dual core mode.
+
+config FLASH_DISABLE_CACHE64
+ bool "Disable the CACHE64 cache for FlexSPI flash accesses"
+ help
+ Disable cache64 cache.
+
+config MCUX_CORE_SUFFIX
+ default "_cm33_core0" if SOC_MCXN947_CPU0
+ default "_cm33_core1" if SOC_MCXN947_CPU1
+endif
+
+rsource "../../common/Kconfig.flexspi_xip"
+
+endif # SOC_SERIES_MCXN
diff --git a/soc/nxp/mcx/mcxn/Kconfig.defconfig b/soc/nxp/mcx/mcxn/Kconfig.defconfig
new file mode 100644
index 0000000..ada924c
--- /dev/null
+++ b/soc/nxp/mcx/mcxn/Kconfig.defconfig
@@ -0,0 +1,30 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_MCXN
+
+config MFD
+ default y if DT_HAS_NXP_LP_FLEXCOMM_ENABLED
+
+config NUM_IRQS
+ default 155
+
+config ROM_START_OFFSET
+ default 0x400 if BOOTLOADER_MCUBOOT
+
+config ZTEST_NO_YIELD
+ default y if (PM && ZTEST)
+
+config MCUX_LPTMR_TIMER
+ default n if (DT_HAS_NXP_OS_TIMER_ENABLED || DT_HAS_ARM_ARMV8M_SYSTICK_ENABLED)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default 1000000 if MCUX_OS_TIMER
+ default 16000 if MCUX_LPTMR_TIMER
+ default 150000000 if CORTEX_M_SYSTICK
+
+# Set to the minimal size of data which can be written.
+config FLASH_FILL_BUFFER_SIZE
+ default 128
+
+endif # SOC_SERIES_MCXN
diff --git a/soc/nxp/mcx/mcxn/Kconfig.soc b/soc/nxp/mcx/mcxn/Kconfig.soc
new file mode 100644
index 0000000..b852dc5
--- /dev/null
+++ b/soc/nxp/mcx/mcxn/Kconfig.soc
@@ -0,0 +1,47 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXN
+ bool
+ select SOC_FAMILY_NXP_MCX
+
+config SOC_SERIES
+ default "mcxn" if SOC_SERIES_MCXN
+
+config SOC_MCXN947
+ bool
+ select SOC_SERIES_MCXN
+
+config SOC_MCXN947_CPU0
+ bool
+ select SOC_MCXN947
+
+config SOC_MCXN947_CPU1
+ bool
+ select SOC_MCXN947
+
+config SOC_MCXN236
+ bool
+ select SOC_SERIES_MCXN
+
+config SOC
+ default "mcxn947" if SOC_MCXN947
+ default "mcxn236" if SOC_MCXN236
+
+config SOC_PART_NUMBER_MCXN947VDF
+ bool
+
+config SOC_PART_NUMBER_MCXN947VNL
+ bool
+
+config SOC_PART_NUMBER_MCXN236VDF
+ bool
+
+config SOC_PART_NUMBER_MCXN236VNL
+ bool
+
+config SOC_PART_NUMBER
+ default "MCXN947VDF" if SOC_PART_NUMBER_MCXN947VDF
+ default "MCXN947VNL" if SOC_PART_NUMBER_MCXN947VNL
+ default "MCXN236VDF" if SOC_PART_NUMBER_MCXN236VDF
+ default "MCXN236VNL" if SOC_PART_NUMBER_MCXN236VNL
diff --git a/soc/nxp/mcx/mcxnx4x/flash_clock_setup.c b/soc/nxp/mcx/mcxn/flash_clock_setup.c
similarity index 100%
rename from soc/nxp/mcx/mcxnx4x/flash_clock_setup.c
rename to soc/nxp/mcx/mcxn/flash_clock_setup.c
diff --git a/soc/nxp/mcx/mcxnx4x/pinctrl_soc.h b/soc/nxp/mcx/mcxn/pinctrl_soc.h
similarity index 100%
rename from soc/nxp/mcx/mcxnx4x/pinctrl_soc.h
rename to soc/nxp/mcx/mcxn/pinctrl_soc.h
diff --git a/soc/nxp/mcx/mcxnx4x/soc.c b/soc/nxp/mcx/mcxn/soc.c
similarity index 100%
rename from soc/nxp/mcx/mcxnx4x/soc.c
rename to soc/nxp/mcx/mcxn/soc.c
diff --git a/soc/nxp/mcx/mcxnx4x/soc.h b/soc/nxp/mcx/mcxn/soc.h
similarity index 100%
rename from soc/nxp/mcx/mcxnx4x/soc.h
rename to soc/nxp/mcx/mcxn/soc.h
diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig b/soc/nxp/mcx/mcxnx4x/Kconfig
deleted file mode 100644
index b301060..0000000
--- a/soc/nxp/mcx/mcxnx4x/Kconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MCXNX4X
- select HAS_MCUX
- select HAS_MCUX_FLEXCOMM
- select CPU_CORTEX_M_HAS_SYSTICK
- select CPU_CORTEX_M_HAS_DWT
- select PLATFORM_SPECIFIC_INIT
-
-config SOC_MCXN947_CPU0
- select CPU_CORTEX_M33
- select CPU_HAS_ARM_SAU
- select CPU_HAS_ARM_MPU
- select CPU_HAS_FPU
- select ARMV8_M_DSP
- select ARM_TRUSTZONE_M
- select HAS_MCUX_CACHE
-
-if SOC_SERIES_MCXNX4X
-
-config SECOND_CORE_MCUX
- bool "MCXN94X's second core"
- depends on HAS_MCUX
- help
- Indicates the second core will be enabled, and the part will run
- in dual core mode.
-
-config FLASH_DISABLE_CACHE64
- bool "Disable the CACHE64 cache for FlexSPI flash accesses"
- help
- Disable cache64 cache.
-
-config MCUX_CORE_SUFFIX
- default "_cm33_core0" if SOC_MCXN947_CPU0
- default "_cm33_core1" if SOC_MCXN947_CPU1
-
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
-
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
-
-DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
-DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
-
-config FLASH_BASE_ADDRESS
- default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
- if $(DT_FLASH_PARENT_IS_FLEXSPI)
-
-config FLASH_SIZE
- default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
- if $(DT_FLASH_HAS_SIZE_PROP)
-
-config FLASH_MCUX_FLEXSPI_XIP
- bool
- default $(DT_FLASH_PARENT_IS_FLEXSPI)
- select XIP
- help
- Allows for the soc to safely initialize the clocks for the
- FlexSpi when planning to execute code in FlexSpi Memory.
-
-endif # SOC_SERIES_MCXNX4X
diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig b/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig
deleted file mode 100644
index c108869..0000000
--- a/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_MCXNX4X
-
-config NUM_IRQS
- default 155
-
-config ROM_START_OFFSET
- default 0x400 if BOOTLOADER_MCUBOOT
-
-config ZTEST_NO_YIELD
- default y if (PM && ZTEST)
-
-config MCUX_LPTMR_TIMER
- default n if (DT_HAS_NXP_OS_TIMER_ENABLED || DT_HAS_ARM_ARMV8M_SYSTICK_ENABLED)
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
- default 1000000 if MCUX_OS_TIMER
- default 16000 if MCUX_LPTMR_TIMER
- default 150000000 if CORTEX_M_SYSTICK
-
-# Set to the minimal size of data which can be written.
-config FLASH_FILL_BUFFER_SIZE
- default 128
-
-endif # SOC_SERIES_MCXNX4X
diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig.soc b/soc/nxp/mcx/mcxnx4x/Kconfig.soc
deleted file mode 100644
index 460d363..0000000
--- a/soc/nxp/mcx/mcxnx4x/Kconfig.soc
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MCXNX4X
- bool
- select SOC_FAMILY_NXP_MCX
-
-config SOC_SERIES
- default "mcxnx4x" if SOC_SERIES_MCXNX4X
-
-config SOC_MCXN947
- bool
- select SOC_SERIES_MCXNX4X
-
-config SOC_MCXN947_CPU0
- bool
- select SOC_MCXN947
-
-config SOC_MCXN947_CPU1
- bool
- select SOC_MCXN947
-
-config SOC
- default "mcxn947" if SOC_MCXN947
-
-config SOC_PART_NUMBER_MCXN947VDF
- bool
-
-config SOC_PART_NUMBER_MCXN947VNL
- bool
-
-config SOC_PART_NUMBER
- default "MCXN947VDF" if SOC_PART_NUMBER_MCXN947VDF
- default "MCXN947VNL" if SOC_PART_NUMBER_MCXN947VNL
diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml
index 24cf8c5..7174e4b 100644
--- a/soc/nxp/mcx/soc.yml
+++ b/soc/nxp/mcx/soc.yml
@@ -1,12 +1,13 @@
family:
- name: nxp_mcx
series:
- - name: mcxnx4x
+ - name: mcxn
socs:
- name: mcxn947
cpuclusters:
- name: cpu0
- name: cpu1
+ - name: mcxn236
runners:
run_once:
'--erase':
diff --git a/soc/nxp/rw/Kconfig b/soc/nxp/rw/Kconfig
index a072151..b32ec76 100644
--- a/soc/nxp/rw/Kconfig
+++ b/soc/nxp/rw/Kconfig
@@ -15,15 +15,11 @@
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_MCUX
select HAS_MCUX_FLEXCOMM
- select INIT_SYS_PLL
select HAS_MCUX_CACHE
select HAS_PM
if SOC_SERIES_RW6XX
-config INIT_SYS_PLL
- bool "Initialize SYS PLL"
-
menuconfig NXP_RW6XX_BOOT_HEADER
bool "Create boot header"
default y if !BOOTLOADER_MCUBOOT
@@ -33,14 +29,7 @@
if NXP_RW6XX_BOOT_HEADER
-choice BOOT_DEVICE
- prompt "Boot device selection"
- default BOOT_FLEXSPI_NOR
-
-config BOOT_FLEXSPI_NOR
- bool "FlexSPI serial NOR"
-
-endchoice
+rsource "../common/Kconfig.rom_loader"
config FLASH_CONFIG_OFFSET
hex "Flash config data offset"
@@ -60,34 +49,6 @@
endif # NXP_RW6XX_BOOT_HEADER
-# Used for default value in FLASH_MCUX_FLEXSPI_XIP
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
-# Macros to shorten Kconfig definitions
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
-
-config FLASH_MCUX_FLEXSPI_XIP
- bool "MCUX FlexSPI flash access with xip"
- default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
- select XIP
- help
- Allows for the soc to safely initialize the clocks for the
- FlexSpi when planning to execute code in FlexSpi Memory.
-
-config NXP_RW_ROM_RAMLOADER
- depends on !FLASH_MCUX_FLEXSPI_XIP
- # Required so that debugger will load image to correct offset
- select BUILD_OUTPUT_HEX
- bool "Create output image that RW ROM can load from FlexSPI to ram"
- help
- Builds an output image that the RW BootROM can load from the
- FlexSPI boot device into RAM region. The image will be loaded
- from FLEXSPI into the region specified by `zephyr,flash` node.
-
-config FLASH_MCUX_FLEXSPI_XIP_MEM
- string
- default "RAM"
- depends on MEMC_MCUX_FLEXSPI
+rsource "../common/Kconfig.flexspi_xip"
endif # SOC_SERIES_RW6XX
diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig
index 198b0b1..284c5e7 100644
--- a/soc/nxp/rw/Kconfig.defconfig
+++ b/soc/nxp/rw/Kconfig.defconfig
@@ -9,104 +9,26 @@
config NUM_IRQS
default 129
-if MCUX_OS_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
- default 1000000
-
-endif # MCUX_OS_TIMER
-
-if CORTEX_M_SYSTICK
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
- default 260000000
-
-endif # CORTEX_M_SYSTICK
-
-# The base address is determined from the zephyr,flash node with the following
-# precedence:
-# FlexSPI base address (if flash node is on a FlexSPI bus)
-# node reg property (used for memory regions such as SRAM)
-
-# Workaround for not being able to have commas in macro arguments
-
-DT_CHOSEN_Z_FLASH := zephyr,flash
-DT_COMPAT_FLEXSPI := nxp,imx-flexspi
-
-# Macros to shorten Kconfig definitions
-DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
-DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
-
-config FLASH_BASE_ADDRESS
- default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
- if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
- default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
-
-# The RW6xx has no internal flash. If the flash node has a size property,
-# use that over the reg property. This is used for the external flash
-# present on the board. Otherwise, fallback to the reg property
-config FLASH_SIZE
- default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
- if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
- default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
-
-if NXP_RW_ROM_RAMLOADER
-
-FLASH_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
-FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
-config BUILD_OUTPUT_ADJUST_LMA
- default "$(FLEXSPI_BASE) - $(FLASH_BASE)"
-
-endif # NXP_RW_ROM_RAMLOADER
-
-if FLASH_MCUX_FLEXSPI_XIP
-
-# Avoid RWW hazards by defaulting logging to disabled
-choice FLASH_LOG_LEVEL_CHOICE
- default FLASH_LOG_LEVEL_OFF
-endchoice
-
-choice MEMC_LOG_LEVEL_CHOICE
- default MEMC_LOG_LEVEL_OFF
-endchoice
-
-# Code relocation is needed when MEMC driver is enabled
-config CODE_DATA_RELOCATION_SRAM
- default y if MEMC
-
-endif # FLASH_MCUX_FLEXSPI_XIP
-
-choice USB_MCUX_CONTROLLER_TYPE
- default USB_DC_NXP_EHCI
-endchoice
+ default 1000000 if MCUX_OS_TIMER
+ default 260000000 if CORTEX_M_SYSTICK
if BT
-config FLASH
+config NXP_MONOLITHIC_BT
default y
-config BT_DIS_MANUF
- default "NXP"
-
-config BT_BUF_EVT_DISCARDABLE_SIZE
- default 84
-
-config BT_HCI_ACL_FLOW_CONTROL
- default n
-
config HCI_NXP_ENABLE_AUTO_SLEEP
default y
config HCI_NXP_SET_CAL_DATA
default y
-config HEAP_MEM_POOL_SIZE
- default 256
-
endif # BT
-config NXP_MONOLITHIC_BT
- default y if BT
+config NXP_MONOLITHIC_WIFI
+ default y if WIFI
config NXP_FW_LOADER
default y if (BT || WIFI)
diff --git a/soc/nxp/rw/firmwares.ld b/soc/nxp/rw/firmwares.ld
index 4287132..98953c7 100644
--- a/soc/nxp/rw/firmwares.ld
+++ b/soc/nxp/rw/firmwares.ld
@@ -4,6 +4,17 @@
* SPDX-License-Identifier: Apache-2.0
*/
+/* For RW612, fw_cpu1 is used for wifi firmware.
+ * Place the wifi and ble firmwares in rodata section. If both binaries
+ * are placed next to each other, the firmware loader will detect the
+ * second binary as part of the first one, leading to initialization
+ * issue, so add a padding of one word */
+#if defined(CONFIG_NXP_MONOLITHIC_WIFI)
+. = ALIGN(4);
+KEEP(*(.fw_cpu1))
+. += 4;
+#endif
+
#if defined(CONFIG_NXP_MONOLITHIC_BT)
. = ALIGN(4);
KEEP(*(.fw_cpu2_ble))
diff --git a/soc/nxp/rw/power.c b/soc/nxp/rw/power.c
index 69e9901..2979d48 100644
--- a/soc/nxp/rw/power.c
+++ b/soc/nxp/rw/power.c
@@ -6,6 +6,7 @@
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/init.h>
+#include <zephyr/drivers/pinctrl.h>
#include "fsl_power.h"
@@ -27,11 +28,58 @@
power_sleep_config_t slp_cfg;
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay) || DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
+pinctrl_soc_pin_t pin_cfg;
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
+static void pin0_isr(const struct device *dev)
+{
+ uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin0), wakeup_level)) & 0x1;
+
+ POWER_ConfigWakeupPin(kPOWER_WakeupPin0, level);
+ NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin0)));
+ DisableIRQ(DT_IRQN(DT_NODELABEL(pin0)));
+ POWER_DisableWakeup(DT_IRQN(DT_NODELABEL(pin0)));
+}
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
+static void pin1_isr(const struct device *dev)
+{
+ uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin1), wakeup_level)) & 0x1;
+
+ POWER_ConfigWakeupPin(kPOWER_WakeupPin1, level);
+ NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin1)));
+ DisableIRQ(DT_IRQN(DT_NODELABEL(pin1)));
+ POWER_DisableWakeup(DT_IRQN(DT_NODELABEL(pin1)));
+}
+#endif
+
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
+ pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO);
+ pinctrl_configure_pins(&pin_cfg, 1, 0);
+ POWER_ConfigWakeupPin(kPOWER_WakeupPin0, DT_ENUM_IDX(DT_NODELABEL(pin0), wakeup_level));
+ POWER_ClearWakeupStatus(DT_IRQN(DT_NODELABEL(pin0)));
+ NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin0)));
+ EnableIRQ(DT_IRQN(DT_NODELABEL(pin0)));
+ POWER_EnableWakeup(DT_IRQN(DT_NODELABEL(pin0)));
+#endif
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
+ pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO);
+ pinctrl_configure_pins(&pin_cfg, 1, 0);
+ POWER_ConfigWakeupPin(kPOWER_WakeupPin1, DT_ENUM_IDX(DT_NODELABEL(pin1), wakeup_level));
+ POWER_ClearWakeupStatus(DT_IRQN(DT_NODELABEL(pin1)));
+ NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin1)));
+ EnableIRQ(DT_IRQN(DT_NODELABEL(pin1)));
+ POWER_EnableWakeup(DT_IRQN(DT_NODELABEL(pin1)));
+#endif
+
/* Set PRIMASK */
__disable_irq();
/* Set BASEPRI to 0 */
@@ -71,6 +119,30 @@
slp_cfg.memPdCfg = suspend_sleepconfig[3];
slp_cfg.pm3BuckCfg = suspend_sleepconfig[4];
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
+ /* PIN 0 uses GPIO0_24, confiure the pin as GPIO */
+ pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO);
+ pinctrl_configure_pins(&pin_cfg, 1, 0);
+
+ /* Initialize the settings in the PMU for this wakeup interrupt */
+ pin0_isr(NULL);
+
+ IRQ_CONNECT(DT_IRQN(DT_NODELABEL(pin0)), DT_IRQ(DT_NODELABEL(pin0), priority), pin0_isr,
+ NULL, 0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
+ /* PIN 1 uses GPIO0_25, confiure the pin as GPIO */
+ pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO);
+ pinctrl_configure_pins(&pin_cfg, 1, 0);
+
+ /* Initialize the settings in the PMU for this wakeup interrupt */
+ pin1_isr(NULL);
+
+ IRQ_CONNECT(DT_IRQN(DT_NODELABEL(pin1)), DT_IRQ(DT_NODELABEL(pin1), priority), pin1_isr,
+ NULL, 0);
+#endif
+
return 0;
}
diff --git a/soc/nxp/s32/s32ze/Kconfig b/soc/nxp/s32/s32ze/Kconfig
index 5adac36..eee441d 100644
--- a/soc/nxp/s32/s32ze/Kconfig
+++ b/soc/nxp/s32/s32ze/Kconfig
@@ -16,6 +16,7 @@
select HAS_NXP_S32_HAL
select HAS_MCUX
select HAS_MCUX_PIT
+ select HAS_MCUX_FLEXCAN
if SOC_SERIES_S32ZE
diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h
index 7390202..0df9ec3 100644
--- a/soc/renesas/ra/common_fsp/pinctrl_soc.h
+++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h
@@ -10,7 +10,7 @@
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
-#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
/**
* @brief Type to hold a renesas ra pin's pinctrl configuration.
@@ -39,6 +39,7 @@
.pin_num = RA_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
.cfg = (DT_PROP(node_id, bias_pull_up) << 4) | \
(DT_PROP(node_id, drive_open_drain) << 6) | \
+ (DT_PROP(node_id, renesas_analog_enable) << 15) | \
(DT_ENUM_IDX(node_id, drive_strength) << 10) | \
(RA_GET_MODE(DT_PROP_BY_IDX(node_id, prop, idx)) << 16) | \
(RA_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)) << 24), \
diff --git a/soc/renesas/ra/ra2a1/CMakeLists.txt b/soc/renesas/ra/ra2a1/CMakeLists.txt
new file mode 100644
index 0000000..223a8ef
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
+zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
+zephyr_linker_sources(ROM_START rom_start.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra2a1/Kconfig b/soc/renesas/ra/ra2a1/Kconfig
new file mode 100644
index 0000000..f447a62
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/Kconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA2A1
+ select ARM
+ select CPU_CORTEX_M23
+ select CPU_HAS_ARM_MPU
+ select CPU_CORTEX_M_HAS_VTOR
+ select CPU_CORTEX_M_HAS_SYSTICK
+ select HAS_SWO
+ select XIP
+ select HAS_RENESAS_RA_FSP
diff --git a/soc/renesas/ra/ra2a1/Kconfig.defconfig b/soc/renesas/ra/ra2a1/Kconfig.defconfig
new file mode 100644
index 0000000..33a1eff
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA2A1
+
+config NUM_IRQS
+ default 32
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA2A1
diff --git a/soc/renesas/ra/ra2a1/Kconfig.soc b/soc/renesas/ra/ra2a1/Kconfig.soc
new file mode 100644
index 0000000..23af5c7
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA2A1
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA2A1 series
+
+config SOC_R7FA2A1AB3CFM
+ bool
+ select SOC_SERIES_RA2A1
+ help
+ R7FA2A1AB3CFM
+
+config SOC_SERIES
+ default "ra2a1" if SOC_SERIES_RA2A1
+
+config SOC
+ default "r7fa2a1ab3cfm" if SOC_R7FA2A1AB3CFM
diff --git a/soc/renesas/ra/ra2a1/data_sections.ld b/soc/renesas/ra/ra2a1/data_sections.ld
new file mode 100644
index 0000000..84cb7c0
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/data_sections.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
diff --git a/soc/renesas/ra/ra2a1/ram_sections.ld b/soc/renesas/ra/ra2a1/ram_sections.ld
new file mode 100644
index 0000000..2f1217e
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/ram_sections.ld
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
diff --git a/soc/renesas/ra/ra2a1/rom_start.ld b/soc/renesas/ra/ra2a1/rom_start.ld
new file mode 100644
index 0000000..64eb3c8
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/rom_start.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;
diff --git a/soc/renesas/ra/ra2a1/sections.ld b/soc/renesas/ra/ra2a1/sections.ld
new file mode 100644
index 0000000..e3034ad
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/sections.ld
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+ KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
+
+SECTION_PROLOGUE(.option_setting_ns,,)
+{
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = __OPTION_SETTING_NS_Start + 0x04;
+ KEEP(*(.option_setting_ofs3))
+ . = __OPTION_SETTING_NS_Start + 0x10;
+ KEEP(*(.option_setting_banksel))
+ . = __OPTION_SETTING_NS_Start + 0x40;
+ KEEP(*(.option_setting_bps0))
+ . = __OPTION_SETTING_NS_Start + 0x44;
+ KEEP(*(.option_setting_bps1))
+ . = __OPTION_SETTING_NS_Start + 0x48;
+ KEEP(*(.option_setting_bps2))
+ . = __OPTION_SETTING_NS_Start + 0x4C;
+ KEEP(*(.option_setting_bps3))
+ . = __OPTION_SETTING_NS_Start + 0x60;
+ KEEP(*(.option_setting_pbps0))
+ . = __OPTION_SETTING_NS_Start + 0x64;
+ KEEP(*(.option_setting_pbps1))
+ . = __OPTION_SETTING_NS_Start + 0x68;
+ KEEP(*(.option_setting_pbps2))
+ . = __OPTION_SETTING_NS_Start + 0x6C;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra2a1/soc.c b/soc/renesas/ra/ra2a1/soc.c
new file mode 100644
index 0000000..5b944ea
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/soc.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA2A1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra2a1_init(void)
+{
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+ bsp_clock_init();
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra2a1_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra2a1/soc.h b/soc/renesas/ra/ra2a1/soc.h
new file mode 100644
index 0000000..3dab874
--- /dev/null
+++ b/soc/renesas/ra/ra2a1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA2A1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ */
diff --git a/soc/renesas/ra/ra6e1/CMakeLists.txt b/soc/renesas/ra/ra6e1/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6e1/Kconfig b/soc/renesas/ra/ra6e1/Kconfig
new file mode 100644
index 0000000..e67c9f6
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E1
+ select ARM
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6e1/Kconfig.defconfig b/soc/renesas/ra/ra6e1/Kconfig.defconfig
new file mode 100644
index 0000000..07ec796
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6E1
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6E1
diff --git a/soc/renesas/ra/ra6e1/Kconfig.soc b/soc/renesas/ra/ra6e1/Kconfig.soc
new file mode 100644
index 0000000..979e118
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E1
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6E1 series
+
+config SOC_R7FA6E10F2CFP
+ bool
+ select SOC_SERIES_RA6E1
+ help
+ R7FA6E10F2CFP
+
+config SOC_SERIES
+ default "ra6e1" if SOC_SERIES_RA6E1
+
+config SOC
+ default "r7fa6e10f2cfp" if SOC_R7FA6E10F2CFP
diff --git a/soc/renesas/ra/ra6e1/sections.ld b/soc/renesas/ra/ra6e1/sections.ld
new file mode 100644
index 0000000..cfc81ae
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/sections.ld
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
diff --git a/soc/renesas/ra/ra6e1/soc.c b/soc/renesas/ra/ra6e1/soc.c
new file mode 100644
index 0000000..5ca796f
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/soc.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6E1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6e1_init(void)
+{
+ uint32_t key;
+
+ extern volatile uint16_t g_protect_counters[];
+
+ for (uint32_t i = 0; i < 4; i++) {
+ g_protect_counters[i] = 0;
+ }
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+ /* Disable protection using PRCR register. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+ /* Initialize peripherals to secure mode for flat projects */
+ R_PSCU->PSARB = 0;
+ R_PSCU->PSARC = 0;
+ R_PSCU->PSARD = 0;
+ R_PSCU->PSARE = 0;
+
+ R_CPSCU->ICUSARG = 0;
+ R_CPSCU->ICUSARH = 0;
+ R_CPSCU->ICUSARI = 0;
+
+ /* Enable protection using PRCR register. */
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+ key = irq_lock();
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6e1_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6e1/soc.h b/soc/renesas/ra/ra6e1/soc.h
new file mode 100644
index 0000000..0d3eb2c
--- /dev/null
+++ b/soc/renesas/ra/ra6e1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6E1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ */
diff --git a/soc/renesas/ra/ra6e2/CMakeLists.txt b/soc/renesas/ra/ra6e2/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6e2/Kconfig b/soc/renesas/ra/ra6e2/Kconfig
new file mode 100644
index 0000000..9ac1ba7
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E2
+ select ARM
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6e2/Kconfig.defconfig b/soc/renesas/ra/ra6e2/Kconfig.defconfig
new file mode 100644
index 0000000..e08fb2e
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6E2
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6E2
diff --git a/soc/renesas/ra/ra6e2/Kconfig.soc b/soc/renesas/ra/ra6e2/Kconfig.soc
new file mode 100644
index 0000000..3a0feff
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E2
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6E2 series
+
+config SOC_R7FA6E2BB3CFM
+ bool
+ select SOC_SERIES_RA6E2
+ help
+ R7FA6E2BB3CFM
+
+config SOC_SERIES
+ default "ra6e2" if SOC_SERIES_RA6E2
+
+config SOC
+ default "r7fa6e2bb3cfm" if SOC_R7FA6E2BB3CFM
diff --git a/soc/renesas/ra/ra6e2/sections.ld b/soc/renesas/ra/ra6e2/sections.ld
new file mode 100644
index 0000000..511ad08
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/sections.ld
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+SECTION_PROLOGUE(.id_code,,)
+{
+ KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
diff --git a/soc/renesas/ra/ra6e2/soc.c b/soc/renesas/ra/ra6e2/soc.c
new file mode 100644
index 0000000..2249db6
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/soc.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6E2 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6e2_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ extern volatile uint16_t g_protect_counters[];
+
+ for (uint32_t i = 0; i < 4; i++) {
+ g_protect_counters[i] = 0;
+ }
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+ /* Disable protection using PRCR register. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+ /* Initialize peripherals to secure mode for flat projects */
+ R_PSCU->PSARB = 0;
+ R_PSCU->PSARC = 0;
+ R_PSCU->PSARD = 0;
+ R_PSCU->PSARE = 0;
+
+ R_CPSCU->ICUSARG = 0;
+ R_CPSCU->ICUSARH = 0;
+ R_CPSCU->ICUSARI = 0;
+
+ /* Enable protection using PRCR register. */
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6e2_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6e2/soc.h b/soc/renesas/ra/ra6e2/soc.h
new file mode 100644
index 0000000..a403240
--- /dev/null
+++ b/soc/renesas/ra/ra6e2/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6E2 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_ */
diff --git a/soc/renesas/ra/ra6m1/CMakeLists.txt b/soc/renesas/ra/ra6m1/CMakeLists.txt
new file mode 100644
index 0000000..ccc5f98
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6m1/Kconfig b/soc/renesas/ra/ra6m1/Kconfig
new file mode 100644
index 0000000..e2520fc
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M1
+ select ARM
+ select CPU_CORTEX_M4
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6m1/Kconfig.defconfig b/soc/renesas/ra/ra6m1/Kconfig.defconfig
new file mode 100644
index 0000000..4f61b47
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6M1
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6M1
diff --git a/soc/renesas/ra/ra6m1/Kconfig.soc b/soc/renesas/ra/ra6m1/Kconfig.soc
new file mode 100644
index 0000000..b979a8b
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M1
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6M1 series
+
+config SOC_R7FA6M1AD3CFP
+ bool
+ select SOC_SERIES_RA6M1
+ help
+ R7FA6M1AD3CFP
+
+config SOC_SERIES
+ default "ra6m1" if SOC_SERIES_RA6M1
+
+config SOC
+ default "r7fa6m1ad3cfp" if SOC_R7FA6M1AD3CFP
diff --git a/soc/renesas/ra/ra6m1/opt_set_mem.ld b/soc/renesas/ra/ra6m1/opt_set_mem.ld
new file mode 100644
index 0000000..07aef9e
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/opt_set_mem.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;
diff --git a/soc/renesas/ra/ra6m1/sections.ld b/soc/renesas/ra/ra6m1/sections.ld
new file mode 100644
index 0000000..b850a64
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/sections.ld
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+ KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
diff --git a/soc/renesas/ra/ra6m1/soc.c b/soc/renesas/ra/ra6m1/soc.c
new file mode 100644
index 0000000..d56bde1
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/soc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6M1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6m1_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6m1_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6m1/soc.h b/soc/renesas/ra/ra6m1/soc.h
new file mode 100644
index 0000000..b341280
--- /dev/null
+++ b/soc/renesas/ra/ra6m1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6M1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_ */
diff --git a/soc/renesas/ra/ra6m2/CMakeLists.txt b/soc/renesas/ra/ra6m2/CMakeLists.txt
new file mode 100644
index 0000000..ccc5f98
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6m2/Kconfig b/soc/renesas/ra/ra6m2/Kconfig
new file mode 100644
index 0000000..89c951a
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M2
+ select ARM
+ select CPU_CORTEX_M4
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6m2/Kconfig.defconfig b/soc/renesas/ra/ra6m2/Kconfig.defconfig
new file mode 100644
index 0000000..33ada2c
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6M2
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6M2
diff --git a/soc/renesas/ra/ra6m2/Kconfig.soc b/soc/renesas/ra/ra6m2/Kconfig.soc
new file mode 100644
index 0000000..6c8b47e
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M2
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6M2 series
+
+config SOC_R7FA6M2AF3CFB
+ bool
+ select SOC_SERIES_RA6M2
+ help
+ R7FA6M2AF3CFB
+
+config SOC_SERIES
+ default "ra6m2" if SOC_SERIES_RA6M2
+
+config SOC
+ default "r7fa6m2af3cfb" if SOC_R7FA6M2AF3CFB
diff --git a/soc/renesas/ra/ra6m2/opt_set_mem.ld b/soc/renesas/ra/ra6m2/opt_set_mem.ld
new file mode 100644
index 0000000..07aef9e
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/opt_set_mem.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;
diff --git a/soc/renesas/ra/ra6m2/sections.ld b/soc/renesas/ra/ra6m2/sections.ld
new file mode 100644
index 0000000..b850a64
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/sections.ld
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+ KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
diff --git a/soc/renesas/ra/ra6m2/soc.c b/soc/renesas/ra/ra6m2/soc.c
new file mode 100644
index 0000000..4b10f21
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/soc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6M2 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6m2_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6m2_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6m2/soc.h b/soc/renesas/ra/ra6m2/soc.h
new file mode 100644
index 0000000..8ad75a1
--- /dev/null
+++ b/soc/renesas/ra/ra6m2/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6M2 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ */
diff --git a/soc/renesas/ra/ra6m3/CMakeLists.txt b/soc/renesas/ra/ra6m3/CMakeLists.txt
new file mode 100644
index 0000000..ccc5f98
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6m3/Kconfig b/soc/renesas/ra/ra6m3/Kconfig
new file mode 100644
index 0000000..c91e528
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M3
+ select ARM
+ select CPU_CORTEX_M4
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6m3/Kconfig.defconfig b/soc/renesas/ra/ra6m3/Kconfig.defconfig
new file mode 100644
index 0000000..f1d9a29
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6M3
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6M3
diff --git a/soc/renesas/ra/ra6m3/Kconfig.soc b/soc/renesas/ra/ra6m3/Kconfig.soc
new file mode 100644
index 0000000..af57f34
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M3
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6M3 series
+
+config SOC_R7FA6M3AH3CFC
+ bool
+ select SOC_SERIES_RA6M3
+ help
+ R7FA6M3AH3CFC
+
+config SOC_SERIES
+ default "ra6m3" if SOC_SERIES_RA6M3
+
+config SOC
+ default "r7fa6m3ah3cfc" if SOC_R7FA6M3AH3CFC
diff --git a/soc/renesas/ra/ra6m3/opt_set_mem.ld b/soc/renesas/ra/ra6m3/opt_set_mem.ld
new file mode 100644
index 0000000..07aef9e
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/opt_set_mem.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;
diff --git a/soc/renesas/ra/ra6m3/sections.ld b/soc/renesas/ra/ra6m3/sections.ld
new file mode 100644
index 0000000..b850a64
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/sections.ld
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+ KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
diff --git a/soc/renesas/ra/ra6m3/soc.c b/soc/renesas/ra/ra6m3/soc.c
new file mode 100644
index 0000000..b2d87b5
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/soc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6M3 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6m3_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6m3_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6m3/soc.h b/soc/renesas/ra/ra6m3/soc.h
new file mode 100644
index 0000000..9fa414f
--- /dev/null
+++ b/soc/renesas/ra/ra6m3/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6M3 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_ */
diff --git a/soc/renesas/ra/ra6m4/CMakeLists.txt b/soc/renesas/ra/ra6m4/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6m4/Kconfig b/soc/renesas/ra/ra6m4/Kconfig
new file mode 100644
index 0000000..b74ea68
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M4
+ select ARM
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6m4/Kconfig.defconfig b/soc/renesas/ra/ra6m4/Kconfig.defconfig
new file mode 100644
index 0000000..672c88d
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6M4
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6M4
diff --git a/soc/renesas/ra/ra6m4/Kconfig.soc b/soc/renesas/ra/ra6m4/Kconfig.soc
new file mode 100644
index 0000000..d0e9add
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M4
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6M4 series
+
+config SOC_R7FA6M4AF3CFB
+ bool
+ select SOC_SERIES_RA6M4
+ help
+ R7FA6M4AF3CFB
+
+config SOC_SERIES
+ default "ra6m4" if SOC_SERIES_RA6M4
+
+config SOC
+ default "r7fa6m4af3cfb" if SOC_R7FA6M4AF3CFB
diff --git a/soc/renesas/ra/ra6m4/sections.ld b/soc/renesas/ra/ra6m4/sections.ld
new file mode 100644
index 0000000..cfc81ae
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/sections.ld
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
diff --git a/soc/renesas/ra/ra6m4/soc.c b/soc/renesas/ra/ra6m4/soc.c
new file mode 100644
index 0000000..1d61e5f
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/soc.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6M4 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6m4_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ extern volatile uint16_t g_protect_counters[];
+
+ for (uint32_t i = 0; i < 4; i++) {
+ g_protect_counters[i] = 0;
+ }
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+ /* Disable protection using PRCR register. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+ /* Initialize peripherals to secure mode for flat projects */
+ R_PSCU->PSARB = 0;
+ R_PSCU->PSARC = 0;
+ R_PSCU->PSARD = 0;
+ R_PSCU->PSARE = 0;
+
+ R_CPSCU->ICUSARG = 0;
+ R_CPSCU->ICUSARH = 0;
+ R_CPSCU->ICUSARI = 0;
+
+ /* Enable protection using PRCR register. */
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6m4_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6m4/soc.h b/soc/renesas/ra/ra6m4/soc.h
new file mode 100644
index 0000000..13344b7
--- /dev/null
+++ b/soc/renesas/ra/ra6m4/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6M4 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_ */
diff --git a/soc/renesas/ra/ra6m5/CMakeLists.txt b/soc/renesas/ra/ra6m5/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra6m5/Kconfig b/soc/renesas/ra/ra6m5/Kconfig
new file mode 100644
index 0000000..f7fdc08
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M5
+ select ARM
+ select CPU_CORTEX_M33
+ select CPU_HAS_ARM_MPU
+ select HAS_RENESAS_RA_FSP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select CPU_CORTEX_M_HAS_DWT
+ select CPU_HAS_FPU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
diff --git a/soc/renesas/ra/ra6m5/Kconfig.defconfig b/soc/renesas/ra/ra6m5/Kconfig.defconfig
new file mode 100644
index 0000000..ca09319
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6M5
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA6M5
diff --git a/soc/renesas/ra/ra6m5/Kconfig.soc b/soc/renesas/ra/ra6m5/Kconfig.soc
new file mode 100644
index 0000000..169511e
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6M5
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA6M5 series
+
+config SOC_R7FA6M5BH3CFC
+ bool
+ select SOC_SERIES_RA6M5
+ help
+ R7FA6M5BH3CFC
+
+config SOC_SERIES
+ default "ra6m5" if SOC_SERIES_RA6M5
+
+config SOC
+ default "r7fa6m5bh3cfc" if SOC_R7FA6M5BH3CFC
diff --git a/soc/renesas/ra/ra6m5/sections.ld b/soc/renesas/ra/ra6m5/sections.ld
new file mode 100644
index 0000000..cfc81ae
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/sections.ld
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
diff --git a/soc/renesas/ra/ra6m5/soc.c b/soc/renesas/ra/ra6m5/soc.c
new file mode 100644
index 0000000..fda381f
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/soc.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6M5 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6m5_init(void)
+{
+ uint32_t key;
+
+ key = irq_lock();
+
+ extern volatile uint16_t g_protect_counters[];
+
+ for (uint32_t i = 0; i < 4; i++) {
+ g_protect_counters[i] = 0;
+ }
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+ /* Disable protection using PRCR register. */
+ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+ /* Initialize peripherals to secure mode for flat projects */
+ R_PSCU->PSARB = 0;
+ R_PSCU->PSARC = 0;
+ R_PSCU->PSARD = 0;
+ R_PSCU->PSARE = 0;
+
+ R_CPSCU->ICUSARG = 0;
+ R_CPSCU->ICUSARH = 0;
+ R_CPSCU->ICUSARI = 0;
+
+ /* Enable protection using PRCR register. */
+ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ irq_unlock(key);
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra6m5_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra6m5/soc.h b/soc/renesas/ra/ra6m5/soc.h
new file mode 100644
index 0000000..2774723
--- /dev/null
+++ b/soc/renesas/ra/ra6m5/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6M5 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ */
diff --git a/soc/renesas/ra/ra8d1/CMakeLists.txt b/soc/renesas/ra/ra8d1/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra8d1/Kconfig b/soc/renesas/ra/ra8d1/Kconfig
new file mode 100644
index 0000000..8945d31
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8D1
+ select ARM
+ select CPU_CORTEX_M85
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_FPU
+ select CPU_HAS_ARM_SAU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select HAS_RENESAS_RA_FSP
diff --git a/soc/renesas/ra/ra8d1/Kconfig.defconfig b/soc/renesas/ra/ra8d1/Kconfig.defconfig
new file mode 100644
index 0000000..dedc907
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA8D1
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA8D1
diff --git a/soc/renesas/ra/ra8d1/Kconfig.soc b/soc/renesas/ra/ra8d1/Kconfig.soc
new file mode 100644
index 0000000..979caf5
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/Kconfig.soc
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config SOC_SERIES_RA8D1
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA8D1 series
+
+config SOC_SERIES
+ default "ra8d1" if SOC_SERIES_RA8D1
+
+config SOC_R7FA8D1BHECBD
+ bool
+ select SOC_SERIES_RA8D1
+ help
+ R7FA8D1BHECBD
+
+config SOC
+ default "r7fa8d1bhecbd" if SOC_R7FA8D1BHECBD
diff --git a/soc/renesas/ra/ra8d1/sections.ld b/soc/renesas/ra/ra8d1/sections.ld
new file mode 100644
index 0000000..cfc81ae
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/sections.ld
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
diff --git a/soc/renesas/ra/ra8d1/soc.c b/soc/renesas/ra/ra8d1/soc.c
new file mode 100644
index 0000000..e915ceb
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/soc.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA8D1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra8d1_init(void)
+{
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra8d1_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra8d1/soc.h b/soc/renesas/ra/ra8d1/soc.h
new file mode 100644
index 0000000..5b0ce25
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA8D1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_ */
diff --git a/soc/renesas/ra/ra8t1/CMakeLists.txt b/soc/renesas/ra/ra8t1/CMakeLists.txt
new file mode 100644
index 0000000..1c74575
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+ soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra8t1/Kconfig b/soc/renesas/ra/ra8t1/Kconfig
new file mode 100644
index 0000000..1c96706
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8T1
+ select ARM
+ select CPU_CORTEX_M85
+ select CPU_HAS_ARM_MPU
+ select CPU_HAS_FPU
+ select CPU_HAS_ARM_SAU
+ select ARMV8_M_DSP
+ select FPU
+ select HAS_SWO
+ select XIP
+ select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+ select HAS_RENESAS_RA_FSP
diff --git a/soc/renesas/ra/ra8t1/Kconfig.defconfig b/soc/renesas/ra/ra8t1/Kconfig.defconfig
new file mode 100644
index 0000000..4fbedc9
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA8T1
+
+config NUM_IRQS
+ default 96
+
+config PINCTRL
+ default y
+
+endif # SOC_SERIES_RA8T1
diff --git a/soc/renesas/ra/ra8t1/Kconfig.soc b/soc/renesas/ra/ra8t1/Kconfig.soc
new file mode 100644
index 0000000..a3a616a
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/Kconfig.soc
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config SOC_SERIES_RA8T1
+ bool
+ select SOC_FAMILY_RENESAS_RA
+ help
+ Renesas RA8T1 series
+
+config SOC_SERIES
+ default "ra8t1" if SOC_SERIES_RA8T1
+
+config SOC_R7FA8T1AHECBD
+ bool
+ select SOC_SERIES_RA8T1
+ help
+ R7FA8T1AHECBD
+
+config SOC
+ default "r7fa8t1ahecbd" if SOC_R7FA8T1AHECBD
diff --git a/soc/renesas/ra/ra8t1/sections.ld b/soc/renesas/ra/ra8t1/sections.ld
new file mode 100644
index 0000000..cfc81ae
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/sections.ld
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+ . = ALIGN(4);
+ __Code_In_RAM_Start = .;
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ *(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = __OPTION_SETTING_OFS_Start + 0x04;
+ KEEP(*(.option_setting_ofs2))
+ . = __OPTION_SETTING_OFS_Start + 0x10;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = __OPTION_SETTING_S_Start + 0x04;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = __OPTION_SETTING_S_Start + 0x10;
+ KEEP(*(.option_setting_banksel_sec))
+ . = __OPTION_SETTING_S_Start + 0x40;
+ KEEP(*(.option_setting_bps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x44;
+ KEEP(*(.option_setting_bps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x48;
+ KEEP(*(.option_setting_bps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x4C;
+ KEEP(*(.option_setting_bps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x60;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = __OPTION_SETTING_S_Start + 0x64;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = __OPTION_SETTING_S_Start + 0x68;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = __OPTION_SETTING_S_Start + 0x6C;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = __OPTION_SETTING_S_Start + 0x80;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = __OPTION_SETTING_S_Start + 0x84;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = __OPTION_SETTING_S_Start + 0x90;
+ KEEP(*(.option_setting_banksel_sel))
+ . = __OPTION_SETTING_S_Start + 0xC0;
+ KEEP(*(.option_setting_bps_sel0))
+ . = __OPTION_SETTING_S_Start + 0xC4;
+ KEEP(*(.option_setting_bps_sel1))
+ . = __OPTION_SETTING_S_Start + 0xC8;
+ KEEP(*(.option_setting_bps_sel2))
+ . = __OPTION_SETTING_S_Start + 0xCC;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
diff --git a/soc/renesas/ra/ra8t1/soc.c b/soc/renesas/ra/ra8t1/soc.c
new file mode 100644
index 0000000..e62a6d2
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/soc.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA8T1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra8t1_init(void)
+{
+ SystemCoreClock = BSP_MOCO_HZ;
+ g_protect_pfswe_counter = 0;
+
+ return 0;
+}
+
+SYS_INIT(renesas_ra8t1_init, PRE_KERNEL_1, 0);
diff --git a/soc/renesas/ra/ra8t1/soc.h b/soc/renesas/ra/ra8t1/soc.h
new file mode 100644
index 0000000..3160d3e
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA8T1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_ */
diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml
index 58bd0d6..cf3c905 100644
--- a/soc/renesas/ra/soc.yml
+++ b/soc/renesas/ra/soc.yml
@@ -1,9 +1,39 @@
family:
- name: renesas_ra
series:
+ - name: ra2a1
+ socs:
+ - name: r7fa2a1ab3cfm
- name: ra4m1
socs:
- name: r7fa4m1ab3cfm
+ - name: ra6m1
+ socs:
+ - name: r7fa6m1ad3cfp
+ - name: ra6m2
+ socs:
+ - name: r7fa6m2af3cfb
+ - name: ra6m3
+ socs:
+ - name: r7fa6m3ah3cfc
+ - name: ra6m4
+ socs:
+ - name: r7fa6m4af3cfb
+ - name: ra6m5
+ socs:
+ - name: r7fa6m5bh3cfc
+ - name: ra6e1
+ socs:
+ - name: r7fa6e10f2cfp
+ - name: ra6e2
+ socs:
+ - name: r7fa6e2bb3cfm
- name: ra8m1
socs:
- name: r7fa8m1ahecbd
+ - name: ra8d1
+ socs:
+ - name: r7fa8d1bhecbd
+ - name: ra8t1
+ socs:
+ - name: r7fa8t1ahecbd
diff --git a/soc/sifive/sifive_freedom/fu500/clock.c b/soc/sifive/sifive_freedom/fu500/clock.c
index 8792989..7e1d4b4 100644
--- a/soc/sifive/sifive_freedom/fu500/clock.c
+++ b/soc/sifive/sifive_freedom/fu500/clock.c
@@ -28,8 +28,9 @@
PLL_RANGE(PLL_RANGE_33MHZ) |
PLL_BYPASS(PLL_BYPASS_DISABLE) |
PLL_FSE(PLL_FSE_INTERNAL);
- while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0)
+ while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0) {
;
+ }
/* Switch clock to COREPLL */
PRCI_REG(PRCI_CORECLKSEL) = CORECLKSEL_CORECLKSEL(CORECLKSEL_CORE_PLL);
diff --git a/soc/sifive/sifive_freedom/fu700/clock.c b/soc/sifive/sifive_freedom/fu700/clock.c
index 5c3fa56..f14b62a 100644
--- a/soc/sifive/sifive_freedom/fu700/clock.c
+++ b/soc/sifive/sifive_freedom/fu700/clock.c
@@ -40,8 +40,9 @@
PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
PLL_BYPASS(PLL_BYPASS_DISABLE) |
PLL_FSE(PLL_FSE_INTERNAL);
- while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0)
+ while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0) {
;
+ }
/* Switch CORE_CLK to CORE_PLL from HFCLK */
PRCI_REG(PRCI_COREPLLSEL) = COREPLLSEL_SEL(COREPLLSEL_COREPLL);
@@ -54,8 +55,9 @@
PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
PLL_BYPASS(PLL_BYPASS_DISABLE) |
PLL_FSE(PLL_FSE_INTERNAL);
- while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0)
+ while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0) {
;
+ }
/* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */
PRCI_REG(PRCI_HFPCLKPLLOUTDIV) = OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
@@ -68,8 +70,9 @@
PLL_RANGE(PLL_RANGE_18MHZ) |
PLL_BYPASS(PLL_BYPASS_DISABLE) |
PLL_FSE(PLL_FSE_INTERNAL);
- while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
+ while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0) {
;
+ }
PRCI_REG(PRCI_DDRPLLOUTDIV) |= OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml
index 50326de..08a8a41 100644
--- a/soc/st/stm32/soc.yml
+++ b/soc/st/stm32/soc.yml
@@ -128,6 +128,10 @@
- name: m4
- name: stm32h750xx
- name: stm32h753xx
+ - name: stm32h755xx
+ cpuclusters:
+ - name: m7
+ - name: m4
- name: stm32l0x
socs:
- name: stm32l010x4
diff --git a/soc/st/stm32/stm32h7x/Kconfig b/soc/st/stm32/stm32h7x/Kconfig
index f72707a..45d7b5f 100644
--- a/soc/st/stm32/stm32h7x/Kconfig
+++ b/soc/st/stm32/stm32h7x/Kconfig
@@ -52,6 +52,12 @@
config SOC_STM32H753XX
select CPU_CORTEX_M7
+config SOC_STM32H755XX_M7
+ select CPU_CORTEX_M7
+
+config SOC_STM32H755XX_M4
+ select CPU_CORTEX_M4
+
config SOC_STM32H7A3XX
select CPU_CORTEX_M7
diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h755xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h755xx
new file mode 100644
index 0000000..fb4515a
--- /dev/null
+++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h755xx
@@ -0,0 +1,14 @@
+# ST STM32H755X MCU configuration options
+
+# Copyright (c) 2024 S&C Electric Company
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
+
+config STM32H7_DUAL_CORE
+ default y
+
+config NUM_IRQS
+ default 150
+
+endif # SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
diff --git a/soc/st/stm32/stm32h7x/Kconfig.soc b/soc/st/stm32/stm32h7x/Kconfig.soc
index 18841c0..e28e09f 100644
--- a/soc/st/stm32/stm32h7x/Kconfig.soc
+++ b/soc/st/stm32/stm32h7x/Kconfig.soc
@@ -60,6 +60,14 @@
bool
select SOC_SERIES_STM32H7X
+config SOC_STM32H755XX_M4
+ bool
+ select SOC_SERIES_STM32H7X
+
+config SOC_STM32H755XX_M7
+ bool
+ select SOC_SERIES_STM32H7X
+
config SOC_STM32H7A3XX
bool
select SOC_SERIES_STM32H7X
@@ -101,3 +109,4 @@
default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4
default "stm32h750xx" if SOC_STM32H750XX
default "stm32h753xx" if SOC_STM32H753XX
+ default "stm32h755xx" if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
diff --git a/soc/st/stm32/stm32h7x/soc_m4.c b/soc/st/stm32/stm32h7x/soc_m4.c
index 9d89817..0af22ec 100644
--- a/soc/st/stm32/stm32h7x/soc_m4.c
+++ b/soc/st/stm32/stm32h7x/soc_m4.c
@@ -51,8 +51,9 @@
* End of system initialization is reached when CM7 takes HSEM.
*/
while ((HSEM->RLR[CFG_HW_ENTRY_STOP_MODE_SEMID] & HSEM_R_LOCK)
- != HSEM_R_LOCK)
+ != HSEM_R_LOCK) {
;
+ }
}
return 0;
diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml
index 2741601..f6e0bd8 100644
--- a/submanifests/optional.yaml
+++ b/submanifests/optional.yaml
@@ -34,7 +34,7 @@
groups:
- optional
- name: sof
- revision: 3f1716b0da7a48358bc265586b90b2252745c14c
+ revision: 0e4c4efcaae858036027607e88406d59bd2a31d8
path: modules/audio/sof
remote: upstream
groups:
diff --git a/subsys/CMakeLists.txt b/subsys/CMakeLists.txt
index 584559f..58f0cf6 100644
--- a/subsys/CMakeLists.txt
+++ b/subsys/CMakeLists.txt
@@ -48,6 +48,7 @@
add_subdirectory_ifdef(CONFIG_LLEXT llext)
add_subdirectory_ifdef(CONFIG_MODEM_MODULES modem)
add_subdirectory_ifdef(CONFIG_NET_BUF net)
+add_subdirectory_ifdef(CONFIG_PROFILING profiling)
add_subdirectory_ifdef(CONFIG_RETENTION retention)
add_subdirectory_ifdef(CONFIG_SENSING sensing)
add_subdirectory_ifdef(CONFIG_SETTINGS settings)
diff --git a/subsys/Kconfig b/subsys/Kconfig
index 2c708e2..59c7fa1 100644
--- a/subsys/Kconfig
+++ b/subsys/Kconfig
@@ -33,6 +33,7 @@
source "subsys/net/Kconfig"
source "subsys/pm/Kconfig"
source "subsys/portability/Kconfig"
+source "subsys/profiling/Kconfig"
source "subsys/random/Kconfig"
source "subsys/retention/Kconfig"
source "subsys/rtio/Kconfig"
diff --git a/subsys/bluetooth/Kconfig.logging b/subsys/bluetooth/Kconfig.logging
index ab28df1..e985878 100644
--- a/subsys/bluetooth/Kconfig.logging
+++ b/subsys/bluetooth/Kconfig.logging
@@ -28,6 +28,7 @@
# COMMON (subsys/bluetooth/common/Kconfig)
+menu "Common"
module = BT_HCI_DRIVER
module-str = "Bluetooth HCI driver"
source "subsys/logging/Kconfig.template.log_config_inherit"
@@ -35,197 +36,26 @@
module = BT_RPA
module-str = "Bluetooth Resolvable Private Address (RPA)"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endmenu # Common
-menu "Audio"
+menu "Libraries"
-# AICS
-
-module = BT_AICS
-module-str = "Audio Input Control Service"
+if BT_EAD
+module = BT_EAD
+module-str = "Bluetooth Encrypted Advertising Data"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_EAD
-module = BT_AICS_CLIENT
-module-str = "Audio Input Control Service client"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# BAP
-
-module = BT_BAP_STREAM
-module-str = "Bluetooth Audio Stream"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_BASE
-module-str = "Bluetooth Basic Audio Profile Broadcast Audio Source Endpoint"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_AUDIO_CODEC
-module-str = "Bluetooth Audio Codec"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_ASCS
-module-str = "Audio Stream Control Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_UNICAST_SERVER
-module-str = "Bluetooth Audio Unicast Server"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_UNICAST_CLIENT
-module-str = "Basic Audio Profile"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_BROADCAST_SOURCE
-module-str = "Bluetooth Audio Broadcast Source"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_BROADCAST_SINK
-module-str = "Bluetooth Audio Broadcast Sink"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_SCAN_DELEGATOR
-module-str = "Broadcast Audio Scan Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_BROADCAST_ASSISTANT
-module-str = "Broadcast Audio Scan Service client debug"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_BAP_ISO
-module-str = "Bluetooth Audio ISO"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# CAP
-
-module = BT_CAP_ACCEPTOR
-module-str = "Common Audio Profile Acceptor"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CAP_INITIATOR
-module-str = "Common Audio Profile Initiator"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CAP_COMMANDER
-module-str = "Common Audio Profile Commander"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CAP_COMMON
-module-str = "Common Audio Profile Common"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CAP_STREAM
-module-str = "Common Audio Profile Stream"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# CSIP
-
-module = BT_CSIP_SET_MEMBER
-module-str = "Coordinated Set Identification Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CSIP_SET_COORDINATOR
-module-str = "Coordinated Set Identification Profile Set Coordinator"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_CSIP_SET_MEMBER_CRYPTO
-module-str = "Coordinated Set Identification Profile crypto functions"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# HAS
-
-module = BT_HAS
-module-str = "Hearing Access Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_HAS_CLIENT
-module-str = "Hearing Access Service Client"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# MCS
-
-module = BT_MCS
-module-str = "Media Control Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_MCC
-module-str = "Media Control Client"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# MCTL
-
-module = MCTL
-module-str = "Media control"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# MICP
-
-module = BT_MICP_MIC_DEV
-module-str = "Microphone Control Profile Microphone Device"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_MICP_MIC_CTLR
-module-str = "Microphone Control Profile Microphone Controller"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# MPL
-
-module = BT_MPL
-module-str = "Media player"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# PACS
-
-module = BT_PACS
-module-str = "Published Audio Capabilities Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# TBS
-
-module = BT_TBS
-module-str = "Telephone Bearer Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_TBS_CLIENT
-module-str = "Telephone Bearer Service client"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# VCP
-
-module = BT_VCP_VOL_REND
-module-str = "Volume Control Profile Voluem Renderer"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_VCP_VOL_CTLR
-module-str = "Volume Control Profile Volume Controller"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# VOCS
-
-module = BT_VOCS
-module-str = "Volume Offset Control Service"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-module = BT_VOCS_CLIENT
-module-str = "Volume Offset Control Service client"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# PBP
-
-module = BT_PBP
-module-str = "Public Broadcast Profile"
-source "${ZEPHYR_BASE}/subsys/logging/Kconfig.template.log_config"
-
-endmenu # Audio
-
-menu "Others"
-
-# CRYPTO (subsys/bluetooth/crypto/Kconfig)
-
+if BT_CRYPTO
module = BT_CRYPTO
module-str = "Bluetooth Cryptographic Toolbox"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CRYPTO
-# GATT
+endmenu # Libraries
+if BT_HCI_HOST
+menu "Host"
module = BT_ATT
module-str = "Bluetooth Attribute Protocol (ATT)"
source "subsys/logging/Kconfig.template.log_config_inherit"
@@ -234,61 +64,308 @@
module-str = "Bluetooth Generic Attribute Profile (GATT)"
source "subsys/logging/Kconfig.template.log_config_inherit"
-# L2CAP
-
module = BT_L2CAP
module-str = "Bluetooth L2CAP"
source "subsys/logging/Kconfig.template.log_config_inherit"
-# LIB (subsys/bluetooth/lib/Kconfig)
-
-module = BT_EAD
-module-str = "Bluetooth Encrypted Advertising Data"
-source "subsys/logging/Kconfig.template.log_config_inherit"
-
-# HOST (subsys/bluetooth/host/Kconfig)
-
+if BT_DF
module = BT_DF
module-str = "Bluetooth Direction Finding"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_DF
+if BT_SETTINGS
module = BT_SETTINGS
module-str = "Bluetooth storage"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_SETTINGS
module = BT_HCI_CORE
module-str = "Bluetooth HCI core"
source "subsys/logging/Kconfig.template.log_config_inherit"
+if BT_CONN
module = BT_CONN
module-str = "Bluetooth connection"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CONN
+if BT_ISO
module = BT_ISO
module-str = "ISO channel"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_ISO
module = BT_KEYS
module-str = "Bluetooth security keys"
source "subsys/logging/Kconfig.template.log_config_inherit"
+if BT_SMP
module = BT_SMP
module-str = "Bluetooth Security Manager Protocol"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_SMP
module = BT_SERVICE
module-str = "Bluetooth Services"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endmenu # LE Host
+endif # BT_HCI_HOST
-# CONTROLLER (subsys/bluetooth/controller/Kconfig)
+if BT_AUDIO
+menu "Audio"
-module = BT_CTLR_ISOAL
-module-str = "Bluetooth Controller ISO-AL"
+if BT_AICS
+module = BT_AICS
+module-str = "Audio Input Control Service"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_AICS
-endmenu # Others
+if BT_AICS_CLIENT
+module = BT_AICS_CLIENT
+module-str = "Audio Input Control Service client"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_AICS_CLIENT
-menu "BR/EDR"
+if BT_BAP_STREAM
+module = BT_BAP_STREAM
+module-str = "Bluetooth Audio Stream"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_STREAM
+
+if BT_BAP_BASE
+module = BT_BAP_BASE
+module-str = "Bluetooth Basic Audio Profile Broadcast Audio Source Endpoint"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_BASE
+
+if BT_BAP_STREAM
+module = BT_AUDIO_CODEC
+module-str = "Bluetooth Audio Codec"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_STREAM
+
+if BT_ASCS
+module = BT_ASCS
+module-str = "Audio Stream Control Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_ASCS
+
+if BT_BAP_UNICAST_SERVER
+module = BT_BAP_UNICAST_SERVER
+module-str = "Bluetooth Audio Unicast Server"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_UNICAST_SERVER
+
+if BT_BAP_UNICAST_CLIENT
+module = BT_BAP_UNICAST_CLIENT
+module-str = "Basic Audio Profile"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_UNICAST_CLIENT
+
+if BT_BAP_BROADCAST_SOURCE
+module = BT_BAP_BROADCAST_SOURCE
+module-str = "Bluetooth Audio Broadcast Source"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_BROADCAST_SOURCE
+
+if BT_BAP_BROADCAST_SINK
+module = BT_BAP_BROADCAST_SINK
+module-str = "Bluetooth Audio Broadcast Sink"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_BROADCAST_SINK
+
+if BT_BAP_SCAN_DELEGATOR
+module = BT_BAP_SCAN_DELEGATOR
+module-str = "Broadcast Audio Scan Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_SCAN_DELEGATOR
+
+if BT_BAP_BROADCAST_ASSISTANT
+module = BT_BAP_BROADCAST_ASSISTANT
+module-str = "Broadcast Audio Scan Service client debug"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_BROADCAST_ASSISTANT
+
+if BT_BAP_STREAM
+module = BT_BAP_ISO
+module-str = "Bluetooth Audio ISO"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_BAP_STREAM
+
+# CAP
+
+if BT_CAP_ACCEPTOR
+module = BT_CAP_ACCEPTOR
+module-str = "Common Audio Profile Acceptor"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CAP_ACCEPTOR
+
+if BT_CAP_INITIATOR
+module = BT_CAP_INITIATOR
+module-str = "Common Audio Profile Initiator"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CAP_INITIATOR
+
+if BT_CAP_COMMANDER
+module = BT_CAP_COMMANDER
+module-str = "Common Audio Profile Commander"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CAP_COMMANDER
+
+if BT_AUDIO
+module = BT_CAP_COMMON
+module-str = "Common Audio Profile Common"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_AUDIO
+
+if BT_CAP
+module = BT_CAP_STREAM
+module-str = "Common Audio Profile Stream"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CAP
+
+# CSIP
+
+if BT_CSIP_SET_MEMBER
+module = BT_CSIP_SET_MEMBER
+module-str = "Coordinated Set Identification Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CSIP_SET_MEMBER
+
+if BT_CSIP_SET_COORDINATOR
+module = BT_CSIP_SET_COORDINATOR
+module-str = "Coordinated Set Identification Profile Set Coordinator"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_CSIP_SET_COORDINATOR
+
+if BT_AUDIO
+module = BT_CSIP_SET_MEMBER_CRYPTO
+module-str = "Coordinated Set Identification Profile crypto functions"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_AUDIO
+
+# HAS
+
+if BT_HAS
+module = BT_HAS
+module-str = "Hearing Access Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_HAS
+
+if BT_HAS_CLIENT
+module = BT_HAS_CLIENT
+module-str = "Hearing Access Service Client"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_HAS_CLIENT
+
+# MCS
+
+if BT_MCS
+module = BT_MCS
+module-str = "Media Control Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_MCS
+
+if BT_MCC
+module = BT_MCC
+module-str = "Media Control Client"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_MCC
+
+# MCTL
+
+if MCTL
+module = MCTL
+module-str = "Media control"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # MCTL
+
+# MICP
+
+if BT_MICP_MIC_DEV
+module = BT_MICP_MIC_DEV
+module-str = "Microphone Control Profile Microphone Device"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_MICP_MIC_DEV
+
+if BT_MICP_MIC_CTLR
+module = BT_MICP_MIC_CTLR
+module-str = "Microphone Control Profile Microphone Controller"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_MICP_MIC_CTLR
+
+# MPL
+
+if BT_MPL
+module = BT_MPL
+module-str = "Media player"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_MPL
+
+# PACS
+
+if BT_PACS
+module = BT_PACS
+module-str = "Published Audio Capabilities Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_PACS
+
+# TBS
+
+if BT_TBS
+module = BT_TBS
+module-str = "Telephone Bearer Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_TBS
+
+if BT_TBS_CLIENT
+module = BT_TBS_CLIENT
+module-str = "Telephone Bearer Service client"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_TBS_CLIENT
+
+# VCP
+
+if BT_VCP_VOL_REND
+module = BT_VCP_VOL_REND
+module-str = "Volume Control Profile Volume Renderer"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_VCP_VOL_REND
+
+if BT_VCP_VOL_CTLR
+module = BT_VCP_VOL_CTLR
+module-str = "Volume Control Profile Volume Controller"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_VCP_VOL_CTLR
+
+# VOCS
+
+if BT_VOCS
+module = BT_VOCS
+module-str = "Volume Offset Control Service"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_VOCS
+
+if BT_VOCS_CLIENT
+module = BT_VOCS_CLIENT
+module-str = "Volume Offset Control Service client"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_VOCS_CLIENT
+
+# PBP
+
+if BT_PBP
+module = BT_PBP
+module-str = "Public Broadcast Profile"
+source "${ZEPHYR_BASE}/subsys/logging/Kconfig.template.log_config"
+endif # BT_PBP
+
+endmenu # Audio
+endif # BT_AUDIO
+
+if BT_CLASSIC
+menu "Bluetooth Classic"
module = BT_RFCOMM
module-str = "Bluetooth RFCOMM"
@@ -314,10 +391,12 @@
module-str = "Bluetooth Service Discovery Protocol (SDP)"
source "subsys/logging/Kconfig.template.log_config_inherit"
-endmenu # BR/EDR
+endmenu # Bluetooth Classic
+endif # BT_CLASSIC
# MESH (subsys/bluetooth/mesh/Kconfig)
+if BT_MESH
menu "Mesh"
module = BT_MESH
@@ -401,46 +480,61 @@
source "subsys/logging/Kconfig.template.log_config_inherit"
endmenu # Mesh
+endif # BT_MESH
menu "Services"
# BAS
+if BT_BAS
module = BT_BAS
module-str = BAS
source "subsys/logging/Kconfig.template.log_config"
+endif # BT_BAS
# HRS
+if BT_HRS
module = BT_HRS
module-str = HRS
source "subsys/logging/Kconfig.template.log_config"
+endif # BT_HRS
# TPS
+if BT_TPS
module = BT_TPS
module-str = TPS
source "subsys/logging/Kconfig.template.log_config"
+endif # BT_TPS
# IAS
+if BT_IAS_CLIENT
module = BT_IAS_CLIENT
module-str = "Immediate Alert Service Client"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_IAS_CLIENT
+if BT_IAS
module = BT_IAS
module-str = IAS
source "${ZEPHYR_BASE}/subsys/logging/Kconfig.template.log_config"
+endif # BT_IAS
# OTS (subsys/bluetooth/services/ots/Kconfig)
+if BT_OTS_CLIENT
module = BT_OTS_CLIENT
module-str = "Object Transfer Service Client"
source "subsys/logging/Kconfig.template.log_config_inherit"
+endif # BT_OTS_CLIENT
+if BT_OTS
module = BT_OTS
module-str = BT_OTS
source "${ZEPHYR_BASE}/subsys/logging/Kconfig.template.log_config"
+endif # BT_OTS
endmenu # Services
diff --git a/subsys/bluetooth/audio/bap_endpoint.h b/subsys/bluetooth/audio/bap_endpoint.h
index 4f52351..cd6165b 100644
--- a/subsys/bluetooth/audio/bap_endpoint.h
+++ b/subsys/bluetooth/audio/bap_endpoint.h
@@ -64,11 +64,27 @@
struct bt_bap_broadcast_sink *broadcast_sink;
};
+struct bt_bap_unicast_group_cig_param {
+ uint32_t c_to_p_interval;
+ uint32_t p_to_c_interval;
+ uint16_t c_to_p_latency;
+ uint16_t p_to_c_latency;
+ uint8_t framing;
+ uint8_t packing;
+#if defined(CONFIG_BT_ISO_TEST_PARAMS)
+ uint8_t c_to_p_ft;
+ uint8_t p_to_c_ft;
+ uint16_t iso_interval;
+#endif /* CONFIG_BT_ISO_TEST_PARAMS */
+};
+
struct bt_bap_unicast_group {
+ /* Group-wide QoS used to create the CIG */
+ struct bt_bap_unicast_group_cig_param cig_param;
+
+ /* Unicast group fields */
uint8_t index;
bool allocated;
- /* QoS used to create the CIG */
- const struct bt_audio_codec_qos *qos;
struct bt_iso_cig *cig;
/* The ISO API for CIG creation requires an array of pointers to ISO channels */
struct bt_iso_chan *cis[UNICAST_GROUP_STREAM_CNT];
diff --git a/subsys/bluetooth/audio/bap_unicast_client.c b/subsys/bluetooth/audio/bap_unicast_client.c
index 862a8a1..51a34d9 100644
--- a/subsys/bluetooth/audio/bap_unicast_client.c
+++ b/subsys/bluetooth/audio/bap_unicast_client.c
@@ -2136,40 +2136,48 @@
}
static void bt_audio_codec_qos_to_cig_param(struct bt_iso_cig_param *cig_param,
- const struct bt_audio_codec_qos *qos,
- const struct bt_bap_unicast_group_param *group_param)
+ const struct bt_bap_unicast_group *group)
{
- cig_param->framing = qos->framing;
- cig_param->packing = BT_ISO_PACKING_SEQUENTIAL; /* TODO: Add to QoS struct */
- cig_param->c_to_p_interval = qos->interval;
- cig_param->p_to_c_interval = qos->interval;
- cig_param->c_to_p_latency = qos->latency;
- cig_param->p_to_c_latency = qos->latency;
+ cig_param->framing = group->cig_param.framing;
+ cig_param->c_to_p_interval = group->cig_param.c_to_p_interval;
+ cig_param->p_to_c_interval = group->cig_param.p_to_c_interval;
+ cig_param->c_to_p_latency = group->cig_param.c_to_p_latency;
+ cig_param->p_to_c_latency = group->cig_param.p_to_c_latency;
+ cig_param->packing = group->cig_param.packing;
cig_param->sca = BT_GAP_SCA_UNKNOWN;
- if (group_param != NULL) {
- cig_param->packing = group_param->packing;
-#if defined(CONFIG_BT_ISO_TEST_PARAMS)
- cig_param->c_to_p_ft = group_param->c_to_p_ft;
- cig_param->p_to_c_ft = group_param->p_to_c_ft;
- cig_param->iso_interval = group_param->iso_interval;
-#endif /* CONFIG_BT_ISO_TEST_PARAMS */
+ IF_ENABLED(CONFIG_BT_ISO_TEST_PARAMS, ({
+ cig_param->c_to_p_ft = group->cig_param.c_to_p_ft;
+ cig_param->p_to_c_ft = group->cig_param.p_to_c_ft;
+ cig_param->iso_interval = group->cig_param.iso_interval;
+ }));
+
+ /* In the case that we only setup a single direction, we still need
+ * (as per section 7.8.97 LE Set CIG Parameters command) to set the interval and latency on
+ * both sides. The value shall be ignored, but the value may not always be ignored correctly
+ * by all controllers, so we always set it here.
+ * If it is at this point unset, then we set the opposing direction to the same value.
+ */
+ if (cig_param->c_to_p_interval == 0U) {
+ cig_param->c_to_p_interval = cig_param->p_to_c_interval;
+ } else if (cig_param->p_to_c_interval == 0U) {
+ cig_param->p_to_c_interval = cig_param->c_to_p_interval;
+ }
+
+ if (cig_param->c_to_p_latency == 0U) {
+ cig_param->c_to_p_latency = cig_param->p_to_c_latency;
+ } else if (cig_param->p_to_c_latency == 0U) {
+ cig_param->p_to_c_latency = cig_param->c_to_p_latency;
}
}
-/* FIXME: Remove `qos` parameter. Some of the QoS related CIG can be different
- * between CIS'es. The implementation shall take the CIG parameters from
- * unicast_group instead.
- */
-static int bt_audio_cig_create(struct bt_bap_unicast_group *group,
- const struct bt_audio_codec_qos *qos,
- const struct bt_bap_unicast_group_param *group_param)
+static int bt_audio_cig_create(struct bt_bap_unicast_group *group)
{
- struct bt_iso_cig_param param;
+ struct bt_iso_cig_param param = {0};
uint8_t cis_count;
int err;
- LOG_DBG("group %p qos %p", group, qos);
+ LOG_DBG("group %p", group);
cis_count = 0U;
for (size_t i = 0U; i < ARRAY_SIZE(group->cis); i++) {
@@ -2183,7 +2191,7 @@
param.num_cis = cis_count;
param.cis_channels = group->cis;
- bt_audio_codec_qos_to_cig_param(¶m, qos, group_param);
+ bt_audio_codec_qos_to_cig_param(¶m, group);
err = bt_iso_cig_create(¶m, &group->cig);
if (err != 0) {
@@ -2191,19 +2199,16 @@
return err;
}
- group->qos = qos;
-
return 0;
}
-static int bt_audio_cig_reconfigure(struct bt_bap_unicast_group *group,
- const struct bt_audio_codec_qos *qos)
+static int bt_audio_cig_reconfigure(struct bt_bap_unicast_group *group)
{
struct bt_iso_cig_param param;
uint8_t cis_count;
int err;
- LOG_DBG("group %p qos %p", group, qos);
+ LOG_DBG("group %p ", group);
cis_count = 0U;
for (size_t i = 0U; i < ARRAY_SIZE(group->cis); i++) {
@@ -2217,7 +2222,7 @@
param.num_cis = cis_count;
param.cis_channels = group->cis;
- bt_audio_codec_qos_to_cig_param(¶m, qos, NULL);
+ bt_audio_codec_qos_to_cig_param(¶m, group);
err = bt_iso_cig_reconfigure(group->cig, ¶m);
if (err != 0) {
@@ -2225,8 +2230,6 @@
return err;
}
- group->qos = qos;
-
return 0;
}
@@ -2369,9 +2372,21 @@
bt_bap_iso_bind_ep(iso, stream->ep);
}
- /* Store the Codec QoS in the bap_iso */
+ /* Store the stream Codec QoS in the bap_iso */
unicast_client_codec_qos_to_iso_qos(iso, qos, dir);
+ /* Store the group Codec QoS in the group - This assume thats the parameters have been
+ * verified first
+ */
+ group->cig_param.framing = qos->framing;
+ if (dir == BT_AUDIO_DIR_SOURCE) {
+ group->cig_param.p_to_c_interval = qos->interval;
+ group->cig_param.p_to_c_latency = qos->latency;
+ } else {
+ group->cig_param.c_to_p_interval = qos->interval;
+ group->cig_param.c_to_p_latency = qos->latency;
+ }
+
sys_slist_append(&group->streams, &stream->_node);
}
@@ -2558,25 +2573,135 @@
return 0;
}
-static int group_qos_common_set(const struct bt_audio_codec_qos **group_qos,
- const struct bt_bap_unicast_group_stream_pair_param *param)
+/** Validates that the stream parameter does not contain invalid values */
+static bool valid_unicast_group_stream_param(const struct bt_bap_unicast_group_stream_param *param,
+ struct bt_bap_unicast_group_cig_param *cig_param,
+ enum bt_audio_dir dir)
{
- if (param->rx_param != NULL && *group_qos == NULL) {
- *group_qos = param->rx_param->qos;
+ const struct bt_audio_codec_qos *qos;
+
+ CHECKIF(param->stream == NULL) {
+ LOG_DBG("param->stream is NULL");
+ return -EINVAL;
}
- if (param->tx_param != NULL && *group_qos == NULL) {
- *group_qos = param->tx_param->qos;
+ CHECKIF(param->qos == NULL) {
+ LOG_DBG("param->qos is NULL");
+ return -EINVAL;
}
- return 0;
+ if (param->stream != NULL && param->stream->group != NULL) {
+ LOG_DBG("stream %p already part of group %p", param->stream, param->stream->group);
+ return -EALREADY;
+ }
+
+ CHECKIF(bt_audio_verify_qos(param->qos) != BT_BAP_ASCS_REASON_NONE) {
+ LOG_DBG("Invalid QoS");
+ return -EINVAL;
+ }
+
+ qos = param->qos;
+
+ /* If unset we set the interval else we verify that all streams use the same interval and
+ * latency in the same direction, as that is required when creating a CIG
+ */
+ if (dir == BT_AUDIO_DIR_SINK) {
+ if (cig_param->c_to_p_interval == 0) {
+ cig_param->c_to_p_interval = qos->interval;
+ } else if (cig_param->c_to_p_interval != qos->interval) {
+ return false;
+ }
+
+ if (cig_param->c_to_p_latency == 0) {
+ cig_param->c_to_p_latency = qos->latency;
+ } else if (cig_param->c_to_p_latency != qos->latency) {
+ return false;
+ }
+ } else {
+ if (cig_param->p_to_c_interval == 0) {
+ cig_param->p_to_c_interval = qos->interval;
+ } else if (cig_param->p_to_c_interval != qos->interval) {
+ return false;
+ }
+
+ if (cig_param->p_to_c_latency == 0) {
+ cig_param->p_to_c_latency = qos->latency;
+ } else if (cig_param->p_to_c_latency != qos->latency) {
+ return false;
+ }
+ }
+
+ if (cig_param->framing == 0) {
+ if (qos->framing == BT_AUDIO_CODEC_QOS_FRAMING_UNFRAMED) {
+ cig_param->framing = BT_ISO_FRAMING_UNFRAMED;
+ } else if (qos->framing == BT_AUDIO_CODEC_QOS_FRAMING_FRAMED) {
+ cig_param->framing = BT_ISO_FRAMING_FRAMED;
+ }
+ } else if ((qos->framing == BT_AUDIO_CODEC_QOS_FRAMING_UNFRAMED &&
+ cig_param->framing != BT_ISO_FRAMING_UNFRAMED) ||
+ (qos->framing == BT_AUDIO_CODEC_QOS_FRAMING_FRAMED &&
+ cig_param->framing != BT_ISO_FRAMING_FRAMED)) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool
+valid_group_stream_pair_param(const struct bt_bap_unicast_group *unicast_group,
+ const struct bt_bap_unicast_group_stream_pair_param *pair_param)
+{
+ struct bt_bap_unicast_group_cig_param cig_param = {0};
+
+ CHECKIF(pair_param == NULL) {
+ LOG_DBG("pair_param is NULL");
+ return false;
+ }
+
+ if (pair_param->rx_param != NULL) {
+ if (!valid_unicast_group_stream_param(pair_param->rx_param, &cig_param,
+ BT_AUDIO_DIR_SOURCE)) {
+ return false;
+ }
+ }
+
+ if (pair_param->tx_param != NULL) {
+ if (!valid_unicast_group_stream_param(pair_param->tx_param, &cig_param,
+ BT_AUDIO_DIR_SINK)) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static bool valid_unicast_group_param(const struct bt_bap_unicast_group *unicast_group,
+ const struct bt_bap_unicast_group_param *param)
+{
+ CHECKIF(param == NULL) {
+ LOG_DBG("streams is NULL");
+ return false;
+ }
+
+ CHECKIF(param->params_count > UNICAST_GROUP_STREAM_CNT) {
+ LOG_DBG("Too many streams provided: %u/%u", param->params_count,
+ UNICAST_GROUP_STREAM_CNT);
+ return false;
+ }
+
+ for (size_t i = 0U; i < param->params_count; i++) {
+ if (!valid_group_stream_pair_param(unicast_group, ¶m->params[i])) {
+ return false;
+ }
+ }
+
+ return true;
}
int bt_bap_unicast_group_create(struct bt_bap_unicast_group_param *param,
struct bt_bap_unicast_group **out_unicast_group)
{
struct bt_bap_unicast_group *unicast_group;
- const struct bt_audio_codec_qos *group_qos = NULL;
int err;
CHECKIF(out_unicast_group == NULL)
@@ -2587,39 +2712,29 @@
/* Set out_unicast_group to NULL until the source has actually been created */
*out_unicast_group = NULL;
- CHECKIF(param == NULL)
- {
- LOG_DBG("streams is NULL");
- return -EINVAL;
- }
-
- CHECKIF(param->params_count > UNICAST_GROUP_STREAM_CNT)
- {
- LOG_DBG("Too many streams provided: %u/%u", param->params_count,
- UNICAST_GROUP_STREAM_CNT);
- return -EINVAL;
- }
-
unicast_group = unicast_group_alloc();
if (unicast_group == NULL) {
LOG_DBG("Could not allocate any more unicast groups");
return -ENOMEM;
}
+ if (!valid_unicast_group_param(unicast_group, param)) {
+ unicast_group_free(unicast_group);
+
+ return -EINVAL;
+ }
+
for (size_t i = 0U; i < param->params_count; i++) {
struct bt_bap_unicast_group_stream_pair_param *stream_param;
stream_param = ¶m->params[i];
- err = stream_pair_param_check(stream_param);
- if (err < 0) {
- return err;
- }
-
- err = group_qos_common_set(&group_qos, stream_param);
- if (err < 0) {
- return err;
- }
+ unicast_group->cig_param.packing = param->packing;
+ IF_ENABLED(CONFIG_BT_ISO_TEST_PARAMS, ({
+ unicast_group->cig_param.c_to_p_ft = param->c_to_p_ft;
+ unicast_group->cig_param.p_to_c_ft = param->p_to_c_ft;
+ unicast_group->cig_param.iso_interval = param->iso_interval;
+ }));
err = unicast_group_add_stream_pair(unicast_group, stream_param);
if (err < 0) {
@@ -2630,7 +2745,7 @@
}
}
- err = bt_audio_cig_create(unicast_group, group_qos, param);
+ err = bt_audio_cig_create(unicast_group);
if (err != 0) {
LOG_DBG("bt_audio_cig_create failed: %d", err);
unicast_group_free(unicast_group);
@@ -2647,7 +2762,6 @@
struct bt_bap_unicast_group_stream_pair_param params[],
size_t num_param)
{
- const struct bt_audio_codec_qos *group_qos = unicast_group->qos;
struct bt_bap_stream *tmp_stream;
size_t total_stream_cnt;
struct bt_iso_cig *cig;
@@ -2683,6 +2797,12 @@
return -EINVAL;
}
+ for (size_t i = 0U; i < num_param; i++) {
+ if (!valid_group_stream_pair_param(unicast_group, ¶ms[i])) {
+ return -EINVAL;
+ }
+ }
+
/* We can just check the CIG state to see if any streams have started as
* that would start the ISO connection procedure
*/
@@ -2702,11 +2822,6 @@
return err;
}
- err = group_qos_common_set(&group_qos, stream_param);
- if (err < 0) {
- return err;
- }
-
err = unicast_group_add_stream_pair(unicast_group, stream_param);
if (err < 0) {
LOG_DBG("unicast_group_add_stream failed: %d", err);
@@ -2714,7 +2829,7 @@
}
}
- err = bt_audio_cig_reconfigure(unicast_group, group_qos);
+ err = bt_audio_cig_reconfigure(unicast_group);
if (err != 0) {
LOG_DBG("bt_audio_cig_reconfigure failed: %d", err);
goto fail;
diff --git a/subsys/bluetooth/audio/shell/vcp_vol_rend.c b/subsys/bluetooth/audio/shell/vcp_vol_rend.c
index 83acc6a..c677351 100644
--- a/subsys/bluetooth/audio/shell/vcp_vol_rend.c
+++ b/subsys/bluetooth/audio/shell/vcp_vol_rend.c
@@ -28,7 +28,7 @@
static struct bt_vcp_included vcp_included;
-static void vcp_vol_rend_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcp_vol_rend_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
if (err) {
shell_error(ctx_shell, "VCP state get failed (%d)", err);
@@ -37,7 +37,7 @@
}
}
-static void vcp_vol_rend_flags_cb(int err, uint8_t flags)
+static void vcp_vol_rend_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
if (err) {
shell_error(ctx_shell, "VCP flags get failed (%d)", err);
diff --git a/subsys/bluetooth/audio/vcp_vol_rend.c b/subsys/bluetooth/audio/vcp_vol_rend.c
index 7dd4a31..afa6cf0 100644
--- a/subsys/bluetooth/audio/vcp_vol_rend.c
+++ b/subsys/bluetooth/audio/vcp_vol_rend.c
@@ -269,8 +269,7 @@
value_changed(&vol_rend, NOTIFY_STATE);
if (vol_rend.cb && vol_rend.cb->state) {
- vol_rend.cb->state(0, vol_rend.state.volume,
- vol_rend.state.mute);
+ vol_rend.cb->state(conn, 0, vol_rend.state.volume, vol_rend.state.mute);
}
}
@@ -282,7 +281,7 @@
}
if (vol_rend.cb && vol_rend.cb->flags) {
- vol_rend.cb->flags(0, vol_rend.flags);
+ vol_rend.cb->flags(conn, 0, vol_rend.flags);
}
}
return len;
@@ -524,8 +523,7 @@
int bt_vcp_vol_rend_get_state(void)
{
if (vol_rend.cb && vol_rend.cb->state) {
- vol_rend.cb->state(0, vol_rend.state.volume,
- vol_rend.state.mute);
+ vol_rend.cb->state(NULL, 0, vol_rend.state.volume, vol_rend.state.mute);
}
return 0;
@@ -534,7 +532,7 @@
int bt_vcp_vol_rend_get_flags(void)
{
if (vol_rend.cb && vol_rend.cb->flags) {
- vol_rend.cb->flags(0, vol_rend.flags);
+ vol_rend.cb->flags(NULL, 0, vol_rend.flags);
}
return 0;
diff --git a/subsys/bluetooth/common/Kconfig b/subsys/bluetooth/common/Kconfig
index 1cf7853..a34dbae 100644
--- a/subsys/bluetooth/common/Kconfig
+++ b/subsys/bluetooth/common/Kconfig
@@ -208,7 +208,7 @@
config BT_HCI_VS_EXT_DETECT
bool "Use heuristics to guess HCI vendor extensions support in advance"
depends on BT_HCI_VS && !BT_CTLR
- default y if BOARD_QEMU_X86 || BOARD_QEMU_CORTEX_M3 || BOARD_NATIVE_POSIX
+ default y if BOARD_QEMU_X86 || BOARD_QEMU_CORTEX_M3 || BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM
help
Use some heuristics to try to guess in advance whether the controller
supports the HCI vendor extensions in advance, in order to prevent
diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig
index 92e3daa..7623d91 100644
--- a/subsys/bluetooth/controller/Kconfig
+++ b/subsys/bluetooth/controller/Kconfig
@@ -568,6 +568,7 @@
bool "LE Path Loss Monitoring Feature"
depends on BT_CTLR_LE_PATH_LOSS_MONITORING_SUPPORT
default y if BT_PATH_LOSS_MONITORING
+ select BT_CTLR_LE_POWER_CONTROL
help
Enable support for LE Path Loss Monitoring feature that is defined in the
Bluetooth Core specification, Version 5.4 | Vol 6, Part B, Section 4.6.32.
diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split
index 1b62bdd..21a6df3 100644
--- a/subsys/bluetooth/controller/Kconfig.ll_sw_split
+++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split
@@ -219,6 +219,10 @@
endif # BT_CTLR_ADV_EXT
+module = BT_CTLR_ISOAL
+module-str = "Bluetooth Controller ISO-AL"
+source "subsys/logging/Kconfig.template.log_config_inherit"
+
config BT_CTLR_ISOAL_LOG_DBG_VERBOSE
bool "ISO-AL verbose debug logging"
depends on BT_CTLR_ISOAL_LOG_LEVEL = 4
@@ -607,7 +611,7 @@
permit use of SoC's peripheral for custom use when Bluetooth is not
enabled.
-choice
+choice BT_CTLR_OPTIMIZE
prompt "Optimization options"
depends on !LTO
default BT_CTLR_OPTIMIZE_FOR_SPEED
@@ -1256,6 +1260,16 @@
endmenu
+# Workaround to be able to have default for "choice" in hidden "menu" above
+choice BT_CTLR_OPTIMIZE
+ prompt "Optimization options"
+ depends on !LTO
+
+config BT_CTLR_OPTIMIZE_FOR_SPEED
+ bool "Optimize for Speed"
+
+endchoice
+
source "subsys/bluetooth/controller/coex/Kconfig"
comment "BLE Controller debug configuration"
diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c
index 69c8d44..9217a08 100644
--- a/subsys/bluetooth/controller/hci/hci.c
+++ b/subsys/bluetooth/controller/hci/hci.c
@@ -8603,11 +8603,13 @@
#if defined(CONFIG_BT_CTLR_PROFILE_ISR)
case NODE_RX_TYPE_PROFILE:
- LOG_INF("l: %u, %u, %u; t: %u, %u, %u; cpu: %u, %u, %u, %u.",
+ LOG_INF("l: %u, %u, %u; t: %u, %u, %u; cpu: %u (%u), %u (%u), %u (%u), %u (%u).",
pdu_data->profile.lcur, pdu_data->profile.lmin, pdu_data->profile.lmax,
pdu_data->profile.cur, pdu_data->profile.min, pdu_data->profile.max,
- pdu_data->profile.radio, pdu_data->profile.lll, pdu_data->profile.ull_high,
- pdu_data->profile.ull_low);
+ pdu_data->profile.radio, pdu_data->profile.radio_ticks,
+ pdu_data->profile.lll, pdu_data->profile.lll_ticks,
+ pdu_data->profile.ull_high, pdu_data->profile.ull_high_ticks,
+ pdu_data->profile.ull_low, pdu_data->profile.ull_low_ticks);
return;
#endif /* CONFIG_BT_CTLR_PROFILE_ISR */
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c
index b7061d9..c63883b 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c
@@ -596,6 +596,7 @@
* EVENT_* registers are not reset to save code and CPU time.
*/
nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_READY);
+ nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_ADDRESS);
nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_END);
#if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST)
/* Clear it only for SoCs supporting DF extension */
@@ -616,6 +617,11 @@
return (NRF_RADIO->EVENTS_READY != 0);
}
+uint32_t radio_is_address(void)
+{
+ return (NRF_RADIO->EVENTS_ADDRESS != 0);
+}
+
#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
static uint32_t last_pdu_end_us;
@@ -664,7 +670,19 @@
return (NRF_RADIO->CRCSTATUS != 0);
}
-static uint8_t MALIGN(4) _pkt_empty[PDU_EM_LL_SIZE_MAX];
+/* Note: Only 3 bytes (PDU_EM_LL_SIZE_MAX) is required for empty PDU
+ * transmission, but in case of Radio ISR latency if rx packet pointer
+ * is not setup then Radio DMA will use previously assigned buffer which
+ * can be this empty PDU buffer. Radio DMA will overrun this buffer and
+ * cause memory corruption. Any detection of ISR latency will not happen
+ * if the ISR function pointer in RAM is corrupted by this overrun.
+ * Increasing ISR latencies in OS and CPU usage in the ULL_HIGH priority
+ * if it is same as LLL priority in Controller implementation then it is
+ * making it tight to execute Controller code in the tIFS between Tx-Rx
+ * PDU's Radio ISRs.
+ */
+static uint8_t MALIGN(4) _pkt_empty[MAX(HAL_RADIO_PDU_LEN_MAX,
+ PDU_EM_LL_SIZE_MAX)];
static uint8_t MALIGN(4) _pkt_scratch[MAX((HAL_RADIO_PDU_LEN_MAX + 3),
PDU_AC_LL_SIZE_MAX)];
@@ -1849,10 +1867,8 @@
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
-#endif /* !CONFIG_SOC_SERIES_NRF51X */
-#if !defined(CONFIG_SOC_SERIES_NRF51X) && \
- !defined(CONFIG_SOC_NRF52832) && \
+#if !defined(CONFIG_SOC_NRF52832) && \
(!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
(CONFIG_BT_CTLR_DATA_LENGTH_MAX < ((HAL_RADIO_PDU_LEN_MAX) - 4U)))
uint8_t max_len = (NRF_RADIO->PCNF1 & RADIO_PCNF1_MAXLEN_Msk) >>
@@ -1877,6 +1893,11 @@
}
#endif /* CONFIG_HAS_HW_NRF_CCM_HEADERMASK */
+#else /* CONFIG_SOC_SERIES_NRF51X */
+ hal_trigger_crypt_ppi_config();
+ hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
+#endif /* CONFIG_SOC_SERIES_NRF51X */
+
NRF_CCM->MODE = mode;
NRF_CCM->CNFPTR = (uint32_t)cnf;
NRF_CCM->INPTR = (uint32_t)_pkt_scratch;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h
index fbc79906..f2a99cf 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h
@@ -84,6 +84,7 @@
void radio_status_reset(void);
uint32_t radio_is_ready(void);
+uint32_t radio_is_address(void);
uint32_t radio_is_done(void);
uint32_t radio_has_disabled(void);
uint32_t radio_is_idle(void);
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c
index da684ff..c28776f 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c
@@ -1289,6 +1289,11 @@
}
}
+ if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
+ lll_prof_cputime_capture();
+ lll_prof_send();
+ }
+
isr_rx_do_close:
radio_isr_set(isr_done, param);
radio_disable();
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c
index d944a52..de7179b 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c
@@ -607,6 +607,11 @@
}
}
+ if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
+ lll_prof_cputime_capture();
+ lll_prof_send();
+ }
+
isr_rx_do_close:
radio_isr_set(isr_done, param);
radio_disable();
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_pdu.h b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_pdu.h
index 14ce6a2..5d36fd0 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_pdu.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_pdu.h
@@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
+/* The Aux Offset shall be at least the length of the packet plus T_MAFS */
+#define PDU_ADV_AUX_OFFSET_MIN_US 300
+
#if defined(CONFIG_BT_CTLR_ADV_PDU_LINK)
#define PDU_ADV_MEM_SIZE MROUND(PDU_AC_LL_HEADER_SIZE + \
PDU_AC_PAYLOAD_SIZE_MAX + \
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c
index 5580ae7..131fcde 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c
@@ -396,7 +396,12 @@
#endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
/* assert if radio packet ptr is not set and radio started tx */
- LL_ASSERT(!radio_is_ready());
+ if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
+ LL_ASSERT_MSG(!radio_is_address(), "%s: Radio ISR latency: %u", __func__,
+ lll_prof_latency_get());
+ } else {
+ LL_ASSERT(!radio_is_address());
+ }
lll_conn_isr_rx_exit:
/* Save the AA captured for the first Rx in connection event */
@@ -497,6 +502,10 @@
struct lll_conn *lll;
uint32_t hcto;
+ if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
+ lll_prof_latency_capture();
+ }
+
/* Clear radio tx status and events */
lll_isr_tx_status_reset();
@@ -566,7 +575,12 @@
lll_conn_rx_pkt_set(lll);
/* assert if radio packet ptr is not set and radio started rx */
- LL_ASSERT(!radio_is_ready());
+ if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
+ LL_ASSERT_MSG(!radio_is_address(), "%s: Radio ISR latency: %u", __func__,
+ lll_prof_latency_get());
+ } else {
+ LL_ASSERT(!radio_is_address());
+ }
#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX)
pdu_tx = get_last_tx_pdu(lll);
@@ -637,6 +651,7 @@
void lll_conn_rx_pkt_set(struct lll_conn *lll)
{
+ struct pdu_data *pdu_data_rx;
struct node_rx_pdu *node_rx;
uint16_t max_rx_octets;
uint8_t phy;
@@ -644,6 +659,15 @@
node_rx = ull_pdu_rx_alloc_peek(1);
LL_ASSERT(node_rx);
+ /* In case of ISR latencies, if packet pointer has not been set on time
+ * then we do not want to check uninitialized length in rx buffer that
+ * did not get used by Radio DMA. This would help us in detecting radio
+ * ready event being set? We can not detect radio ready if it happens
+ * twice before Radio ISR executes after latency.
+ */
+ pdu_data_rx = (void *)node_rx->pdu;
+ pdu_data_rx->len = 0U;
+
#if defined(CONFIG_BT_CTLR_DATA_LENGTH)
max_rx_octets = lll->dle.eff.max_rx_octets;
#else /* !CONFIG_BT_CTLR_DATA_LENGTH */
@@ -680,7 +704,7 @@
#error "Undefined HAL_RADIO_PDU_LEN_MAX."
#else
radio_pkt_rx_set(radio_ccm_rx_pkt_set(&lll->ccm_rx, phy,
- node_rx->pdu));
+ pdu_data_rx));
#endif
#endif /* CONFIG_BT_CTLR_LE_ENC */
} else {
@@ -688,7 +712,7 @@
RADIO_PKT_CONF_FLAGS(RADIO_PKT_CONF_PDU_TYPE_DC, phy,
RADIO_PKT_CONF_CTE_DISABLED));
- radio_pkt_rx_set(node_rx->pdu);
+ radio_pkt_rx_set(pdu_data_rx);
}
}
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof.c
index aee16fb..48323156 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof.c
@@ -15,6 +15,8 @@
#include "util/memq.h"
+#include "ticker/ticker.h"
+
#include "pdu_df.h"
#include "pdu_vendor.h"
#include "pdu.h"
@@ -22,63 +24,83 @@
#include "lll.h"
static int send(struct node_rx_pdu *rx);
+static uint16_t latency_get(void);
static inline void sample(uint32_t *timestamp);
-static inline void delta(uint32_t timestamp, uint8_t *cputime);
+static inline void sample_ticks(uint32_t *timestamp_ticks);
+static inline void delta(uint32_t timestamp, uint16_t *cputime);
+static inline void delta_ticks(uint32_t timestamp_ticks, uint8_t *cputime_ticks);
static uint32_t timestamp_radio;
static uint32_t timestamp_lll;
static uint32_t timestamp_ull_high;
static uint32_t timestamp_ull_low;
-static uint8_t cputime_radio;
-static uint8_t cputime_lll;
-static uint8_t cputime_ull_high;
-static uint8_t cputime_ull_low;
-static uint8_t latency_min = (uint8_t) -1;
-static uint8_t latency_max;
-static uint8_t latency_prev;
-static uint8_t cputime_min = (uint8_t) -1;
-static uint8_t cputime_max;
-static uint8_t cputime_prev;
+static uint16_t cputime_radio;
+static uint16_t cputime_lll;
+static uint16_t cputime_ull_high;
+static uint16_t cputime_ull_low;
+static uint16_t latency_min = UINT16_MAX;
+static uint16_t latency_max;
+static uint16_t latency_prev;
+static uint16_t cputime_min = UINT16_MAX;
+static uint16_t cputime_max;
+static uint16_t cputime_prev;
static uint32_t timestamp_latency;
+static uint32_t timestamp_ticks_radio;
+static uint32_t timestamp_ticks_lll;
+static uint32_t timestamp_ticks_ull_high;
+static uint32_t timestamp_ticks_ull_low;
+static uint8_t cputime_ticks_radio;
+static uint8_t cputime_ticks_lll;
+static uint8_t cputime_ticks_ull_high;
+static uint8_t cputime_ticks_ull_low;
+
void lll_prof_enter_radio(void)
{
sample(×tamp_radio);
+ sample_ticks(×tamp_ticks_radio);
}
void lll_prof_exit_radio(void)
{
delta(timestamp_radio, &cputime_radio);
+ delta_ticks(timestamp_ticks_radio, &cputime_ticks_radio);
}
void lll_prof_enter_lll(void)
{
sample(×tamp_lll);
+ sample_ticks(×tamp_ticks_lll);
}
void lll_prof_exit_lll(void)
{
delta(timestamp_lll, &cputime_lll);
+ delta_ticks(timestamp_ticks_lll, &cputime_ticks_lll);
}
void lll_prof_enter_ull_high(void)
{
sample(×tamp_ull_high);
+ sample_ticks(×tamp_ticks_ull_high);
}
void lll_prof_exit_ull_high(void)
{
delta(timestamp_ull_high, &cputime_ull_high);
+ delta_ticks(timestamp_ticks_ull_high, &cputime_ticks_ull_high);
}
void lll_prof_enter_ull_low(void)
{
sample(×tamp_ull_low);
+ sample_ticks(×tamp_ticks_ull_low);
}
void lll_prof_exit_ull_low(void)
{
delta(timestamp_ull_low, &cputime_ull_low);
+ delta_ticks(timestamp_ticks_ull_low, &cputime_ticks_ull_low);
}
void lll_prof_latency_capture(void)
@@ -87,6 +109,29 @@
* and generate the profiling event at the end of the ISR.
*/
radio_tmr_sample();
+
+ /* Initialize so that if we call lll_prof_latency_get before it is
+ * set, we can set it.
+ */
+ timestamp_latency = UINT16_MAX;
+}
+
+uint16_t lll_prof_latency_get(void)
+{
+ uint16_t latency;
+
+ /* We are here before lll_prof_cputime_capture was called */
+ if (timestamp_latency == UINT16_MAX) {
+ /* get the ISR latency sample */
+ timestamp_latency = radio_tmr_sample_get();
+ }
+
+ /* Get the elapsed time in us since on-air radio packet end to ISR
+ * entry.
+ */
+ latency = latency_get();
+
+ return latency;
}
#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
@@ -155,19 +200,15 @@
static int send(struct node_rx_pdu *rx)
{
- uint8_t latency, cputime, prev;
+ uint16_t latency, cputime, prev;
struct pdu_data *pdu;
struct profile *p;
uint8_t chg = 0U;
- /* calculate the elapsed time in us since on-air radio packet end
- * to ISR entry
+ /* Get the elapsed time in us since on-air radio packet end to ISR
+ * entry.
*/
-#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
- latency = timestamp_latency - timestamp_radio_end;
-#else /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
- latency = timestamp_latency - radio_tmr_end_get();
-#endif /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
+ latency = latency_get();
/* check changes in min, avg and max of latency */
if (latency > latency_max) {
@@ -236,25 +277,64 @@
p->lll = cputime_lll;
p->ull_high = cputime_ull_high;
p->ull_low = cputime_ull_low;
+ p->radio_ticks = cputime_ticks_radio;
+ p->lll_ticks = cputime_ticks_lll;
+ p->ull_high_ticks = cputime_ticks_ull_high;
+ p->ull_low_ticks = cputime_ticks_ull_low;
ull_rx_put_sched(rx->hdr.link, rx);
return 0;
}
+static uint16_t latency_get(void)
+{
+ uint16_t latency;
+
+ /* calculate the elapsed time in us since on-air radio packet end
+ * to ISR entry
+ */
+ if (!IS_ENABLED(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)) {
+#if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
+ latency = timestamp_latency - timestamp_radio_end;
+#else /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
+ latency = timestamp_latency - radio_tmr_end_get();
+#endif /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
+ } else {
+ latency = timestamp_latency;
+ }
+
+ return latency;
+}
+
static inline void sample(uint32_t *timestamp)
{
radio_tmr_sample();
*timestamp = radio_tmr_sample_get();
}
-static inline void delta(uint32_t timestamp, uint8_t *cputime)
+static inline void sample_ticks(uint32_t *timestamp_ticks)
+{
+ *timestamp_ticks = ticker_ticks_now_get();
+}
+
+static inline void delta(uint32_t timestamp, uint16_t *cputime)
{
uint32_t delta;
radio_tmr_sample();
delta = radio_tmr_sample_get() - timestamp;
- if (delta < UINT8_MAX && delta > *cputime) {
+ if (delta < UINT16_MAX && delta > *cputime) {
*cputime = delta;
}
}
+
+static inline void delta_ticks(uint32_t timestamp_ticks, uint8_t *cputime_ticks)
+{
+ uint32_t delta;
+
+ delta = ticker_ticks_now_get() - timestamp_ticks;
+ if (delta < UINT8_MAX && delta > *cputime_ticks) {
+ *cputime_ticks = delta;
+ }
+}
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof_internal.h b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof_internal.h
index 603f3cf..d5b3ba5 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof_internal.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_prof_internal.h
@@ -25,6 +25,7 @@
#endif
void lll_prof_latency_capture(void);
+uint16_t lll_prof_latency_get(void);
void lll_prof_radio_end_backup(void);
void lll_prof_cputime_capture(void);
void lll_prof_send(void);
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c
index b1e95bb..eb97ab7 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c
@@ -129,6 +129,7 @@
uint32_t aux_offset_us;
uint32_t overhead_us;
uint8_t *pri_dptr;
+ uint32_t pdu_us;
uint8_t phy;
LL_ASSERT(pdu->type == PDU_ADV_TYPE_EXT_IND);
@@ -183,6 +184,12 @@
/* Calculate the aux offset from start of the scan window */
aux_offset_us = (uint32_t)PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) * window_size_us;
+ /* Skip reception if invalid aux offset */
+ pdu_us = PDU_AC_US(pdu->len, pdu_phy, pdu_phy_flags_rx);
+ if (aux_offset_us < pdu_us) {
+ return 0U;
+ }
+
/* Calculate the window widening that needs to be deducted */
if (aux_ptr->ca) {
window_widening_us = SCA_DRIFT_50_PPM_US(aux_offset_us);
@@ -233,7 +240,7 @@
ftr->radio_end_us = radio_tmr_end_get() -
radio_rx_chain_delay_get(pdu_phy,
pdu_phy_flags_rx) -
- PDU_AC_US(pdu->len, pdu_phy, pdu_phy_flags_rx);
+ pdu_us;
radio_isr_set(setup_cb, node_rx);
radio_disable();
@@ -338,6 +345,7 @@
aux_start_us -= EVENT_JITTER_US;
start_us = radio_tmr_start_us(0, aux_start_us);
+ LL_ASSERT(start_us == (aux_start_us + 1U));
/* Setup header complete timeout */
hcto = start_us;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync.c
index d0285ac..63b6e9a 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync.c
@@ -738,6 +738,7 @@
aux_start_us -= EVENT_JITTER_US;
start_us = radio_tmr_start_us(0, aux_start_us);
+ LL_ASSERT(start_us == (aux_start_us + 1U));
/* Setup header complete timeout */
hcto = start_us;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
index cb6023b..2f4db61 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
@@ -1046,10 +1046,7 @@
start_us = hcto;
hcto = radio_tmr_start_us(0U, start_us);
- /* FIXME: Assertion check disabled until investigation as to
- * why there is high ISR latency causing assertion here.
- */
- /* LL_ASSERT(hcto == (start_us + 1U)); */
+ LL_ASSERT(hcto == (start_us + 1U));
/* Add 8 us * subevents so far, as radio was setup to listen
* 4 us early and subevents could have a 4 us drift each until
diff --git a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_adv_pdu.h b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_adv_pdu.h
index 21f0bed..ddae0e6 100644
--- a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_adv_pdu.h
+++ b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_adv_pdu.h
@@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
+/* The Aux Offset shall be at least the length of the packet plus T_MAFS */
+#define PDU_ADV_AUX_OFFSET_MIN_US 300
+
int lll_adv_data_init(struct lll_adv_pdu *pdu);
int lll_adv_data_reset(struct lll_adv_pdu *pdu);
int lll_adv_data_release(struct lll_adv_pdu *pdu);
diff --git a/subsys/bluetooth/controller/ll_sw/pdu.h b/subsys/bluetooth/controller/ll_sw/pdu.h
index 9f8f363..18ae111 100644
--- a/subsys/bluetooth/controller/ll_sw/pdu.h
+++ b/subsys/bluetooth/controller/ll_sw/pdu.h
@@ -187,8 +187,10 @@
#define EVENT_IFS_US 150
/* Standard allows 2 us timing uncertainty inside the event */
#define EVENT_IFS_MAX_US (EVENT_IFS_US + EVENT_CLOCK_JITTER_US)
-/* Controller will layout extended adv with minimum separation */
+/* Specification defined Minimum AUX Frame Space (MAFS) */
#define EVENT_MAFS_US 300
+/* Controller dependent MAFS minimum used to populate aux_offset */
+#define EVENT_MAFS_MIN_US MAX(EVENT_MAFS_US, PDU_ADV_AUX_OFFSET_MIN_US)
/* Standard allows 2 us timing uncertainty inside the event */
#define EVENT_MAFS_MAX_US (EVENT_MAFS_US + EVENT_CLOCK_JITTER_US)
/* Controller defined back to back transmit MAFS for extended advertising */
@@ -931,16 +933,20 @@
#if defined(CONFIG_BT_CTLR_PROFILE_ISR)
struct profile {
- uint8_t lcur;
- uint8_t lmin;
- uint8_t lmax;
- uint8_t cur;
- uint8_t min;
- uint8_t max;
- uint8_t radio;
- uint8_t lll;
- uint8_t ull_high;
- uint8_t ull_low;
+ uint16_t lcur;
+ uint16_t lmin;
+ uint16_t lmax;
+ uint16_t cur;
+ uint16_t min;
+ uint16_t max;
+ uint16_t radio;
+ uint16_t lll;
+ uint16_t ull_high;
+ uint16_t ull_low;
+ uint8_t radio_ticks;
+ uint8_t lll_ticks;
+ uint8_t ull_high_ticks;
+ uint8_t ull_low_ticks;
} __packed;
#endif /* CONFIG_BT_CTLR_PROFILE_ISR */
diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c b/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
index d2c673b..482239a 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
@@ -3120,14 +3120,18 @@
chan_counter = lll_aux->data_chan_counter;
- /* The offset has to be at least T_MAFS microseconds from the end of packet
+ /* The offset has to be at least T_MAFS microseconds from the end of packet.
+ *
+ * BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 6, Part B, Section 2.3.4.5 AuxPtr field,
+ * The Aux Offset shall be at least the length of the packet plus T_MAFS
+ *
* In addition, the offset recorded in the aux ptr has the same requirement and this
* offset is in steps of 30 microseconds; So use the quantized value in check
*/
pdu_us = PDU_AC_US(pdu->len, adv->phy_p, adv->phy_flags);
offset_us = HAL_TICKER_TICKS_TO_US(lll_aux->ticks_pri_pdu_offset) +
lll_aux->us_pri_pdu_offset;
- if ((offset_us/OFFS_UNIT_30_US)*OFFS_UNIT_30_US < EVENT_MAFS_US + pdu_us) {
+ if (((offset_us / OFFS_UNIT_30_US) * OFFS_UNIT_30_US) < (EVENT_MAFS_MIN_US + pdu_us)) {
uint32_t interval_us;
/* Offset too small, point to next aux packet instead */
@@ -3165,10 +3169,13 @@
uint32_t ticks_current;
uint32_t ticks_elapsed;
struct ll_adv_set *adv;
+ uint16_t chan_counter;
struct pdu_adv *pdu;
uint32_t ticks_now;
uint32_t remainder;
+ uint32_t offset_us;
uint8_t ticker_id;
+ uint16_t pdu_us;
uint8_t retry;
uint8_t id;
@@ -3226,13 +3233,6 @@
*/
lll_aux->ticks_pri_pdu_offset = ticks_to_expire;
- /* NOTE: as first primary channel PDU does not use remainder, the packet
- * timer is started one tick in advance to start the radio with
- * microsecond precision, hence compensate for the higher start_us value
- * captured at radio start of the first primary channel PDU.
- */
- lll_aux->ticks_pri_pdu_offset += 1U;
-
/* Store the microsecond remainder offset for population in other
* advertising primary channel PDUs.
*/
@@ -3241,8 +3241,43 @@
/* Fill the aux offset in the first Primary channel PDU */
/* FIXME: we are in ULL_LOW context, fill offset in LLL context? */
pdu = lll_adv_data_latest_peek(&adv->lll);
- aux_ptr = ull_adv_aux_lll_offset_fill(pdu, ticks_to_expire, remainder,
- 0U);
+
+ /* data channel counter that will be used for auxiliary PDU channel */
+ chan_counter = lll_aux->data_chan_counter;
+
+ /* The offset has to be at least T_MAFS microseconds from the end of packet.
+ *
+ * BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 6, Part B, Section 2.3.4.5 AuxPtr field,
+ * The Aux Offset shall be at least the length of the packet plus T_MAFS
+ *
+ * In addition, the offset recorded in the aux ptr has the same requirement and this
+ * offset is in steps of 30 microseconds; So use the quantized value in check
+ */
+ pdu_us = PDU_AC_US(pdu->len, adv->lll.phy_p, adv->lll.phy_flags);
+ offset_us = HAL_TICKER_TICKS_TO_US(lll_aux->ticks_pri_pdu_offset) +
+ lll_aux->us_pri_pdu_offset;
+ if (((offset_us / OFFS_UNIT_30_US) * OFFS_UNIT_30_US) < (EVENT_MAFS_MIN_US + pdu_us)) {
+ uint32_t interval_us;
+
+ /* Offset too small, point to next aux packet instead */
+ interval_us = aux->interval * PERIODIC_INT_UNIT_US;
+ offset_us = offset_us + interval_us;
+ lll_aux->ticks_pri_pdu_offset = HAL_TICKER_US_TO_TICKS(offset_us);
+ lll_aux->us_pri_pdu_offset = offset_us -
+ HAL_TICKER_TICKS_TO_US(lll_aux->ticks_pri_pdu_offset);
+ chan_counter++;
+ }
+
+ /* Fill the aux offset */
+ aux_ptr = ull_adv_aux_lll_offset_fill(pdu, lll_aux->ticks_pri_pdu_offset,
+ lll_aux->us_pri_pdu_offset, 0U);
+
+ /* NOTE: as first primary channel PDU does not use remainder, the packet
+ * timer is started one tick in advance to start the radio with
+ * microsecond precision, hence compensate for the higher start_us value
+ * captured at radio start of the first primary channel PDU.
+ */
+ lll_aux->ticks_pri_pdu_offset += 1U;
/* Process channel map update, if any */
if (aux->chm_first != aux->chm_last) {
@@ -3253,10 +3288,11 @@
/* Calculate the radio channel to use */
data_chan_map = aux->chm[aux->chm_first].data_chan_map;
data_chan_count = aux->chm[aux->chm_first].data_chan_count;
- aux_ptr->chan_idx = lll_chan_sel_2(lll_aux->data_chan_counter,
+ aux_ptr->chan_idx = lll_chan_sel_2(chan_counter,
aux->data_chan_id,
data_chan_map, data_chan_count);
+ /* Assertion check for delayed aux_offset calculations */
ticks_now = ticker_ticks_now_get();
ticks_elapsed = ticker_ticks_diff_get(ticks_now, ticks_current);
ticks_to_start = MAX(adv->ull.ticks_active_to_start,
diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
index 3e90448..0e4bbf0 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
@@ -126,6 +126,7 @@
uint8_t acad_len;
uint8_t data_len;
uint8_t hdr_len;
+ uint32_t pdu_us;
uint8_t *ptr;
uint8_t phy;
@@ -705,6 +706,12 @@
aux_offset_us = (uint32_t)PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) * lll_aux->window_size_us;
+ /* Skip reception if invalid aux offset */
+ pdu_us = PDU_AC_US(pdu->len, phy, ftr->phy_flags);
+ if (aux_offset_us < pdu_us) {
+ goto ull_scan_aux_rx_flush;
+ }
+
/* CA field contains the clock accuracy of the advertiser;
* 0 - 51 ppm to 500 ppm
* 1 - 0 ppm to 50 ppm
@@ -723,7 +730,7 @@
/* Calculate the aux offset from start of the scan window */
aux_offset_us += ftr->radio_end_us;
- aux_offset_us -= PDU_AC_US(pdu->len, phy, ftr->phy_flags);
+ aux_offset_us -= pdu_us;
aux_offset_us -= EVENT_TICKER_RES_MARGIN_US;
aux_offset_us -= EVENT_JITTER_US;
aux_offset_us -= ready_delay_us;
diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig
index c8ffedc..b8d7f62 100644
--- a/subsys/bluetooth/host/Kconfig
+++ b/subsys/bluetooth/host/Kconfig
@@ -280,8 +280,8 @@
default 32 if 64BIT
default 16
help
- Necessary user_data size for allowing packet fragmentation when
- sending over HCI. See `struct tx_meta` in conn.c.
+ Necessary user_data size for stack usage. Mostly used for passing
+ callbacks around. See `struct closure` in conn_internal.h.
config BT_CONN_FRAG_COUNT
int
diff --git a/subsys/bluetooth/host/att.c b/subsys/bluetooth/host/att.c
index a225792..4489de0 100644
--- a/subsys/bluetooth/host/att.c
+++ b/subsys/bluetooth/host/att.c
@@ -448,27 +448,27 @@
k_fifo_init(&skipped);
- while ((buf = net_buf_get(fifo, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(fifo, K_NO_WAIT))) {
meta = bt_att_get_tx_meta_data(buf);
if (!ret &&
att_chan_matches_chan_opt(chan, meta->chan_opt)) {
ret = buf;
} else {
- net_buf_put(&skipped, buf);
+ k_fifo_put(&skipped, buf);
}
}
__ASSERT_NO_MSG(k_fifo_is_empty(fifo));
- while ((buf = net_buf_get(&skipped, K_NO_WAIT))) {
- net_buf_put(fifo, buf);
+ while ((buf = k_fifo_get(&skipped, K_NO_WAIT))) {
+ k_fifo_put(fifo, buf);
}
__ASSERT_NO_MSG(k_fifo_is_empty(&skipped));
return ret;
} else {
- return net_buf_get(fifo, K_NO_WAIT);
+ return k_fifo_get(fifo, K_NO_WAIT);
}
}
@@ -779,7 +779,7 @@
err = chan_send(chan, buf);
if (err) {
/* Responses need to be sent back using the same channel */
- net_buf_put(&chan->tx_queue, buf);
+ k_fifo_put(&chan->tx_queue, buf);
}
}
@@ -3063,7 +3063,7 @@
(void)k_work_cancel_delayable_sync(&att->eatt.connection_work, &sync);
#endif /* CONFIG_BT_EATT */
- while ((buf = net_buf_get(&att->tx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&att->tx_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
@@ -3098,7 +3098,7 @@
sys_slist_find_and_remove(&chan->att->chans, &chan->node);
/* Release pending buffers */
- while ((buf = net_buf_get(&chan->tx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&chan->tx_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
@@ -3832,6 +3832,27 @@
return mtu;
}
+uint16_t bt_att_get_uatt_mtu(struct bt_conn *conn)
+{
+ struct bt_att_chan *chan, *tmp;
+ struct bt_att *att;
+
+ att = att_get(conn);
+ if (!att) {
+ return 0;
+ }
+
+ SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&att->chans, chan, tmp, node) {
+ if (!bt_att_is_enhanced(chan)) {
+ return bt_att_mtu(chan);
+ }
+ }
+
+ LOG_WRN("No UATT channel found in %p", conn);
+
+ return 0;
+}
+
static void att_chan_mtu_updated(struct bt_att_chan *updated_chan)
{
struct bt_att *att = updated_chan->att;
@@ -3906,7 +3927,7 @@
return -ENOTCONN;
}
- net_buf_put(&att->tx_queue, buf);
+ k_fifo_put(&att->tx_queue, buf);
att_send_process(att);
return 0;
diff --git a/subsys/bluetooth/host/att_internal.h b/subsys/bluetooth/host/att_internal.h
index a2b9895..7898dce 100644
--- a/subsys/bluetooth/host/att_internal.h
+++ b/subsys/bluetooth/host/att_internal.h
@@ -293,6 +293,7 @@
void bt_att_init(void);
uint16_t bt_att_get_mtu(struct bt_conn *conn);
+uint16_t bt_att_get_uatt_mtu(struct bt_conn *conn);
struct net_buf *bt_att_create_pdu(struct bt_conn *conn, uint8_t op,
size_t len);
diff --git a/subsys/bluetooth/host/classic/l2cap_br.c b/subsys/bluetooth/host/classic/l2cap_br.c
index 59fea22..523cce4 100644
--- a/subsys/bluetooth/host/classic/l2cap_br.c
+++ b/subsys/bluetooth/host/classic/l2cap_br.c
@@ -300,7 +300,7 @@
LOG_DBG("push PDU: cb %p userdata %p", cb, user_data);
make_closure(buf->user_data, cb, user_data);
- net_buf_put(&br_chan->_pdu_tx_queue, buf);
+ k_fifo_put(&br_chan->_pdu_tx_queue, buf);
raise_data_ready(br_chan);
return 0;
@@ -910,7 +910,7 @@
/* Remove buffers on the PDU TX queue. */
while (chan_has_data(br_chan)) {
- struct net_buf *buf = net_buf_get(&br_chan->_pdu_tx_queue, K_NO_WAIT);
+ struct net_buf *buf = k_fifo_get(&br_chan->_pdu_tx_queue, K_NO_WAIT);
net_buf_unref(buf);
}
diff --git a/subsys/bluetooth/host/classic/rfcomm.c b/subsys/bluetooth/host/classic/rfcomm.c
index f7a0c25..21ccba2 100644
--- a/subsys/bluetooth/host/classic/rfcomm.c
+++ b/subsys/bluetooth/host/classic/rfcomm.c
@@ -261,8 +261,7 @@
/* Queue a dummy buffer to wake up and stop the
* tx thread for states where it was running.
*/
- net_buf_put(&dlc->tx_queue,
- net_buf_alloc(&dummy_pool, K_NO_WAIT));
+ k_fifo_put(&dlc->tx_queue, net_buf_alloc(&dummy_pool, K_NO_WAIT));
/* There could be a writer waiting for credits so return a
* dummy credit to wake it up.
@@ -583,7 +582,7 @@
dlc->state == BT_RFCOMM_STATE_USER_DISCONNECT) {
/* Get next packet for dlc */
LOG_DBG("Wait for buf %p", dlc);
- buf = net_buf_get(&dlc->tx_queue, timeout);
+ buf = k_fifo_get(&dlc->tx_queue, timeout);
/* If its dummy buffer or non user disconnect then break */
if ((dlc->state != BT_RFCOMM_STATE_CONNECTED &&
dlc->state != BT_RFCOMM_STATE_USER_DISCONNECT) ||
@@ -618,7 +617,7 @@
LOG_DBG("dlc %p disconnected - cleaning up", dlc);
/* Give back any allocated buffers */
- while ((buf = net_buf_get(&dlc->tx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&dlc->tx_queue, K_NO_WAIT))) {
bt_rfcomm_tx_destroy(dlc, buf);
net_buf_unref(buf);
}
@@ -871,7 +870,7 @@
/* Queue a dummy buffer to wake up and stop the
* tx thread.
*/
- net_buf_put(&dlc->tx_queue,
+ k_fifo_put(&dlc->tx_queue,
net_buf_alloc(&dummy_pool, K_NO_WAIT));
/* There could be a writer waiting for credits so return a
@@ -1489,7 +1488,7 @@
fcs = rfcomm_calc_fcs(BT_RFCOMM_FCS_LEN_UIH, buf->data);
net_buf_add_u8(buf, fcs);
- net_buf_put(&dlc->tx_queue, buf);
+ k_fifo_put(&dlc->tx_queue, buf);
return buf->len;
}
@@ -1748,7 +1747,7 @@
* and stop the tx thread.
*/
dlc->state = BT_RFCOMM_STATE_USER_DISCONNECT;
- net_buf_put(&dlc->tx_queue,
+ k_fifo_put(&dlc->tx_queue,
net_buf_alloc(&dummy_pool, K_NO_WAIT));
k_work_reschedule(&dlc->rtx_work, RFCOMM_DISC_TIMEOUT);
diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c
index 0478314..e11375b 100644
--- a/subsys/bluetooth/host/conn.c
+++ b/subsys/bluetooth/host/conn.c
@@ -35,6 +35,7 @@
#include "hci_core.h"
#include "id.h"
#include "adv.h"
+#include "scan.h"
#include "conn_internal.h"
#include "l2cap_internal.h"
#include "keys.h"
@@ -934,12 +935,7 @@
__maybe_unused sys_snode_t *s = sys_slist_get(&bt_dev.le.conn_ready);
__ASSERT_NO_MSG(s == node);
-
(void)atomic_set(&conn->_conn_ready_lock, 0);
- /* Note: we can't assert `old` is non-NULL here, as the
- * connection might have been marked ready by an l2cap channel
- * that cancelled its request to send.
- */
/* Append connection to list if it still has data */
if (conn->has_data(conn)) {
@@ -1117,6 +1113,7 @@
node = sys_slist_get(&conn->tx_pending);
if (!node) {
+ bt_tx_irq_raise();
return;
}
@@ -1269,10 +1266,18 @@
* the application through bt_conn_disconnect or by
* timeout set by bt_conn_le_create_param.timeout.
*/
- if (conn->err) {
- notify_connected(conn);
- }
+ if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
+ int err = bt_le_scan_user_remove(BT_LE_SCAN_USER_CONN);
+ if (err) {
+ LOG_WRN("Error while removing conn user from scanner (%d)",
+ err);
+ }
+
+ if (conn->err) {
+ notify_connected(conn);
+ }
+ }
bt_conn_unref(conn);
break;
case BT_CONN_ADV_DIR_CONNECTABLE:
@@ -1697,7 +1702,7 @@
conn->err = reason;
bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
- bt_le_scan_update(false);
+ return bt_le_scan_user_add(BT_LE_SCAN_USER_CONN);
}
return 0;
case BT_CONN_INITIATING:
@@ -3002,7 +3007,7 @@
{
struct bt_conn_cb *callback;
- SYS_SLIST_FOR_EACH_CONTAINER(&callback_list, callback, _node) {
+ SYS_SLIST_FOR_EACH_CONTAINER(&conn_cbs, callback, _node) {
if (callback->path_loss_threshold_report) {
callback->path_loss_threshold_report(conn, &report);
}
@@ -3364,27 +3369,32 @@
{
if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
+ LOG_DBG("Conn check failed: BT dev not ready.");
return -EAGAIN;
}
if (!bt_le_conn_params_valid(conn_param)) {
+ LOG_DBG("Conn check failed: invalid parameters.");
return -EINVAL;
}
- if (!BT_LE_STATES_SCAN_INIT(bt_dev.le.states) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
+ if (!BT_LE_STATES_SCAN_INIT(bt_dev.le.states) && bt_le_explicit_scanner_running()) {
+ LOG_DBG("Conn check failed: scanner was explicitly requested.");
return -EAGAIN;
}
if (atomic_test_bit(bt_dev.flags, BT_DEV_INITIATING)) {
+ LOG_DBG("Conn check failed: device is already initiating.");
return -EALREADY;
}
if (!bt_id_scan_random_addr_check()) {
+ LOG_DBG("Conn check failed: invalid random address.");
return -EINVAL;
}
if (bt_conn_exists_le(BT_ID_DEFAULT, peer)) {
+ LOG_DBG("Conn check failed: ACL connection already exists.");
return -EINVAL;
}
@@ -3437,8 +3447,9 @@
/* Use host-based identity resolving. */
bt_conn_set_state(conn, BT_CONN_SCAN_BEFORE_INITIATING);
- err = bt_le_scan_update(true);
+ err = bt_le_scan_user_add(BT_LE_SCAN_USER_CONN);
if (err) {
+ bt_le_scan_user_remove(BT_LE_SCAN_USER_CONN);
bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
bt_conn_unref(conn);
@@ -3458,7 +3469,12 @@
bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
bt_conn_unref(conn);
- bt_le_scan_update(false);
+ /* Best-effort attempt to inform the scanner that the initiator stopped. */
+ int scan_check_err = bt_le_scan_user_add(BT_LE_SCAN_USER_NONE);
+
+ if (scan_check_err) {
+ LOG_WRN("Error while updating the scanner (%d)", scan_check_err);
+ }
return err;
}
@@ -3560,17 +3576,18 @@
}
}
+ int err = 0;
if (conn->state == BT_CONN_DISCONNECTED &&
atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
if (param) {
bt_conn_set_state(conn, BT_CONN_SCAN_BEFORE_INITIATING);
+ err = bt_le_scan_user_add(BT_LE_SCAN_USER_CONN);
}
- bt_le_scan_update(false);
}
bt_conn_unref(conn);
- return 0;
+ return err;
}
#endif /* !defined(CONFIG_BT_FILTER_ACCEPT_LIST) */
#endif /* CONFIG_BT_CENTRAL */
diff --git a/subsys/bluetooth/host/gatt.c b/subsys/bluetooth/host/gatt.c
index 03d476c..d5b11d5 100644
--- a/subsys/bluetooth/host/gatt.c
+++ b/subsys/bluetooth/host/gatt.c
@@ -3164,6 +3164,11 @@
return bt_att_get_mtu(conn);
}
+uint16_t bt_gatt_get_uatt_mtu(struct bt_conn *conn)
+{
+ return bt_att_get_uatt_mtu(conn);
+}
+
uint8_t bt_gatt_check_perm(struct bt_conn *conn, const struct bt_gatt_attr *attr,
uint16_t mask)
{
diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c
index 943f9f6..427e0c1 100644
--- a/subsys/bluetooth/host/hci_core.c
+++ b/subsys/bluetooth/host/hci_core.c
@@ -356,7 +356,7 @@
return err;
}
- net_buf_put(&bt_dev.cmd_tx_queue, buf);
+ k_fifo_put(&bt_dev.cmd_tx_queue, buf);
bt_tx_irq_raise();
return 0;
@@ -392,7 +392,7 @@
k_sem_init(&sync_sem, 0, 1);
cmd(buf)->sync = &sync_sem;
- net_buf_put(&bt_dev.cmd_tx_queue, net_buf_ref(buf));
+ k_fifo_put(&bt_dev.cmd_tx_queue, net_buf_ref(buf));
bt_tx_irq_raise();
/* TODO: disallow sending sync commands from syswq altogether */
@@ -1010,7 +1010,12 @@
#if defined(CONFIG_BT_CENTRAL) && !defined(CONFIG_BT_FILTER_ACCEPT_LIST)
if (atomic_test_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
bt_conn_set_state(conn, BT_CONN_SCAN_BEFORE_INITIATING);
- bt_le_scan_update(false);
+ /* Just a best-effort check if the scanner should be started. */
+ int err = bt_le_scan_user_remove(BT_LE_SCAN_USER_NONE);
+
+ if (err) {
+ LOG_WRN("Error while updating the scanner (%d)", err);
+ }
}
#endif /* defined(CONFIG_BT_CENTRAL) && !defined(CONFIG_BT_FILTER_ACCEPT_LIST) */
@@ -1561,9 +1566,14 @@
bt_conn_unref(conn);
- if (IS_ENABLED(CONFIG_BT_CENTRAL) &&
- conn->role == BT_HCI_ROLE_CENTRAL) {
- bt_le_scan_update(false);
+ if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->role == BT_HCI_ROLE_CENTRAL) {
+ int err;
+
+ /* Just a best-effort check if the scanner should be started. */
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_NONE);
+ if (err) {
+ LOG_WRN("Error while updating the scanner (%d)", err);
+ }
}
}
@@ -1661,7 +1671,11 @@
if (IS_ENABLED(CONFIG_BT_CENTRAL) && status == BT_HCI_ERR_UNKNOWN_CONN_ID) {
le_conn_complete_cancel(status);
- bt_le_scan_update(false);
+ int err = bt_le_scan_user_remove(BT_LE_SCAN_USER_NONE);
+
+ if (err) {
+ LOG_WRN("Error while updating the scanner (%d)", err);
+ }
return;
}
@@ -3042,7 +3056,7 @@
/* Get next command */
LOG_DBG("fetch cmd");
- buf = net_buf_get(&bt_dev.cmd_tx_queue, K_NO_WAIT);
+ buf = k_fifo_get(&bt_dev.cmd_tx_queue, K_NO_WAIT);
BT_ASSERT(buf);
/* Clear out any existing sent command */
@@ -4200,7 +4214,7 @@
atomic_set_bit(bt_dev.flags, BT_DEV_READY);
if (IS_ENABLED(CONFIG_BT_OBSERVER)) {
- bt_le_scan_update(false);
+ bt_scan_reset();
}
bt_dev_show_info();
@@ -4310,7 +4324,14 @@
/* We now TX everything from the syswq */
return &k_sys_work_q.thread;
}
-#endif
+
+#if defined(CONFIG_BT_ISO)
+void bt_testing_set_iso_mtu(uint16_t mtu)
+{
+ bt_dev.le.iso_mtu = mtu;
+}
+#endif /* CONFIG_BT_ISO */
+#endif /* CONFIG_BT_TESTING */
int bt_enable(bt_ready_cb_t cb)
{
diff --git a/subsys/bluetooth/host/hci_core.h b/subsys/bluetooth/host/hci_core.h
index 827d7a4..4f632dd 100644
--- a/subsys/bluetooth/host/hci_core.h
+++ b/subsys/bluetooth/host/hci_core.h
@@ -38,16 +38,11 @@
BT_DEV_HAS_PUB_KEY,
BT_DEV_PUB_KEY_BUSY,
- /** The application explicitly instructed the stack to scan for advertisers
- * using the API @ref bt_le_scan_start().
- */
- BT_DEV_EXPLICIT_SCAN,
-
/** The application either explicitly or implicitly instructed the stack to scan
* for advertisers.
*
* Examples of such cases
- * - Explicit scanning, @ref BT_DEV_EXPLICIT_SCAN.
+ * - Explicit scanning, @ref BT_LE_SCAN_USER_EXPLICIT_SCAN.
* - The application instructed the stack to automatically connect if a given device
* is detected.
* - The application wants to connect to a peer device using private addresses, but
@@ -63,13 +58,9 @@
*/
BT_DEV_SCANNING,
- /* Cached parameters used when initially enabling the scanner.
- * These are needed to ensure the same parameters are used when restarting
- * the scanner after refreshing an RPA.
+ /**
+ * Scanner is configured with a timeout.
*/
- BT_DEV_ACTIVE_SCAN,
- BT_DEV_SCAN_FILTER_DUP,
- BT_DEV_SCAN_FILTERED,
BT_DEV_SCAN_LIMITED,
BT_DEV_INITIATING,
@@ -489,30 +480,6 @@
*/
int bt_get_df_cte_type(uint8_t hci_cte_type);
-/** Start or restart scanner if needed
- *
- * Examples of cases where it may be required to start/restart a scanner:
- * - When the auto-connection establishement feature is used:
- * - When the host sets a connection context for auto-connection establishment.
- * - When a connection was established.
- * The host may now be able to retry to automatically set up a connection.
- * - When a connection was disconnected/lost.
- * The host may now be able to retry to automatically set up a connection.
- * - When the application stops explicit scanning.
- * The host may now be able to retry to automatically set up a connection.
- * - The application tries to connect to another device, but fails.
- * The host may now be able to retry to automatically set up a connection.
- * - When the application wants to connect to a device, but we need
- * to fallback to host privacy.
- * - When the application wants to establish a periodic sync to a device
- * and the application has not already started scanning.
- *
- * @param fast_scan Use fast scan parameters or slow scan parameters
- *
- * @return 0 in case of success, or a negative error code on failure.
- */
-int bt_le_scan_update(bool fast_scan);
-
int bt_le_create_conn(const struct bt_conn *conn);
int bt_le_create_conn_cancel(void);
int bt_le_create_conn_synced(const struct bt_conn *conn, const struct bt_le_ext_adv *adv,
diff --git a/subsys/bluetooth/host/hci_raw.c b/subsys/bluetooth/host/hci_raw.c
index 64340c2..984c860 100644
--- a/subsys/bluetooth/host/hci_raw.c
+++ b/subsys/bluetooth/host/hci_raw.c
@@ -225,7 +225,7 @@
}
/* Queue to RAW rx queue */
- net_buf_put(raw_rx, buf);
+ k_fifo_put(raw_rx, buf);
return 0;
}
diff --git a/subsys/bluetooth/host/id.c b/subsys/bluetooth/host/id.c
index e4d48ce..871e016 100644
--- a/subsys/bluetooth/host/id.c
+++ b/subsys/bluetooth/host/id.c
@@ -689,11 +689,11 @@
le_rpa_invalidate();
/* IF no roles using the RPA is running we can stop the RPA timer */
- if (!(adv_enabled ||
- atomic_test_bit(bt_dev.flags, BT_DEV_INITIATING) ||
- (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_ACTIVE_SCAN)))) {
- return;
+ if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
+ if (!(adv_enabled || atomic_test_bit(bt_dev.flags, BT_DEV_INITIATING) ||
+ bt_le_scan_active_scanner_running())) {
+ return;
+ }
}
le_update_private_addr();
diff --git a/subsys/bluetooth/host/iso.c b/subsys/bluetooth/host/iso.c
index 5ee3033..7d04fed 100644
--- a/subsys/bluetooth/host/iso.c
+++ b/subsys/bluetooth/host/iso.c
@@ -431,6 +431,7 @@
__ASSERT(chan->iso != NULL, "NULL conn for iso chan %p", chan);
bt_iso_chan_set_state(chan, BT_ISO_STATE_DISCONNECTED);
+ bt_conn_set_state(chan->iso, BT_CONN_DISCONNECT_COMPLETE);
/* The peripheral does not have the concept of a CIG, so once a CIS
* disconnects it is completely freed by unref'ing it
@@ -778,6 +779,8 @@
LOG_DBG("channel has been disconnected");
__ASSERT_NO_MSG(b == frag);
+ net_buf_unref(b);
+
/* Service other connections */
bt_tx_irq_raise();
@@ -840,7 +843,7 @@
return -EINVAL;
}
- net_buf_put(&conn->iso.txq, buf);
+ k_fifo_put(&conn->iso.txq, buf);
BT_ISO_DATA_DBG("%p put on list", buf);
/* only one ISO channel per conn-object */
diff --git a/subsys/bluetooth/host/l2cap.c b/subsys/bluetooth/host/l2cap.c
index 626df10..1b25f83 100644
--- a/subsys/bluetooth/host/l2cap.c
+++ b/subsys/bluetooth/host/l2cap.c
@@ -261,7 +261,7 @@
* `l2cap_chan_destroy()` as it is not called for fixed channels.
*/
while (chan_has_data(le_chan)) {
- struct net_buf *buf = net_buf_get(&le_chan->tx_queue, K_NO_WAIT);
+ struct net_buf *buf = k_fifo_get(&le_chan->tx_queue, K_NO_WAIT);
net_buf_unref(buf);
}
@@ -312,7 +312,7 @@
struct bt_l2cap_le_chan *ch = CHAN_RX(work);
struct net_buf *buf;
- while ((buf = net_buf_get(&ch->rx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&ch->rx_queue, K_NO_WAIT))) {
LOG_DBG("ch %p buf %p", ch, buf);
l2cap_chan_le_recv(ch, buf);
net_buf_unref(buf);
@@ -331,6 +331,23 @@
LOG_DBG("conn %p chan %p", conn, chan);
}
+static void init_le_chan_private(struct bt_l2cap_le_chan *le_chan)
+{
+ /* Initialize private members of the struct. We can't "just memset" as
+ * some members are used as application parameters.
+ */
+#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
+ le_chan->_sdu = NULL;
+ le_chan->_sdu_len = 0;
+#if defined(CONFIG_BT_L2CAP_SEG_RECV)
+ le_chan->_sdu_len_done = 0;
+#endif /* CONFIG_BT_L2CAP_SEG_RECV */
+#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */
+ memset(&le_chan->_pdu_ready, 0, sizeof(le_chan->_pdu_ready));
+ le_chan->_pdu_ready_lock = 0;
+ le_chan->_pdu_remaining = 0;
+}
+
static bool l2cap_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan,
bt_l2cap_chan_destroy_t destroy)
{
@@ -348,6 +365,7 @@
}
atomic_clear(chan->status);
+ init_le_chan_private(le_chan);
bt_l2cap_chan_add(conn, chan, destroy);
@@ -720,7 +738,7 @@
make_closure(pdu->user_data, cb, user_data);
LOG_DBG("push: pdu %p len %d cb %p userdata %p", pdu, pdu->len, cb, user_data);
- net_buf_put(&le_chan->tx_queue, pdu);
+ k_fifo_put(&le_chan->tx_queue, pdu);
raise_data_ready(le_chan); /* tis just a flag */
@@ -885,11 +903,15 @@
*/
struct net_buf *pdu = k_fifo_peek_head(&lechan->tx_queue);
+ /* We don't have anything to send for the current channel. We could
+ * however have something to send on another channel that is attached to
+ * the same ACL connection. Re-trigger the TX processor: it will call us
+ * again and this time we will select another channel to pull data from.
+ */
if (!pdu) {
bt_tx_irq_raise();
return NULL;
}
- /* __ASSERT(pdu, "signaled ready but no PDUs in the TX queue"); */
if (bt_buf_has_view(pdu)) {
LOG_ERR("already have view on %p", pdu);
@@ -1281,7 +1303,7 @@
}
/* Remove buffers on the SDU RX queue */
- while ((buf = net_buf_get(&le_chan->rx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&le_chan->rx_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
@@ -2241,12 +2263,12 @@
}
/* Remove buffers on the TX queue */
- while ((buf = net_buf_get(&le_chan->tx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&le_chan->tx_queue, K_NO_WAIT))) {
l2cap_tx_buf_destroy(chan->conn, buf, -ESHUTDOWN);
}
/* Remove buffers on the RX queue */
- while ((buf = net_buf_get(&le_chan->rx_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&le_chan->rx_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
@@ -2651,7 +2673,7 @@
return;
}
- net_buf_put(&chan->rx_queue, buf);
+ k_fifo_put(&chan->rx_queue, buf);
k_work_submit(&chan->rx_work);
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */
@@ -3117,9 +3139,9 @@
return -EINVAL;
}
- CHECKIF(user_data_not_empty(buf)) {
- LOG_DBG("Please clear user_data first");
- return -EINVAL;
+ if (user_data_not_empty(buf)) {
+ /* There may be issues if user_data is not empty. */
+ LOG_WRN("user_data is not empty");
}
/* Prepend SDU length.
@@ -3144,7 +3166,7 @@
net_buf_push_le16(buf, sdu_len);
/* Put buffer on TX queue */
- net_buf_put(&le_chan->tx_queue, buf);
+ k_fifo_put(&le_chan->tx_queue, buf);
/* Always process the queue in the same context */
raise_data_ready(le_chan);
diff --git a/subsys/bluetooth/host/scan.c b/subsys/bluetooth/host/scan.c
index 35f0997..ad469a5 100644
--- a/subsys/bluetooth/host/scan.c
+++ b/subsys/bluetooth/host/scan.c
@@ -5,8 +5,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/types.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
#include <zephyr/sys/atomic.h>
+#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/check.h>
@@ -25,14 +29,32 @@
#include "id.h"
#include "common/bt_str.h"
+#include "scan.h"
#define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_scan);
+struct scanner_state {
+ ATOMIC_DEFINE(scan_flags, BT_LE_SCAN_USER_NUM_FLAGS);
+ struct bt_le_scan_param explicit_scan_param;
+ struct bt_le_scan_param used_scan_param;
+ struct k_mutex scan_update_mutex;
+ struct k_mutex scan_explicit_params_mutex;
+};
+
+enum scan_action {
+ SCAN_ACTION_NONE,
+ SCAN_ACTION_START,
+ SCAN_ACTION_STOP,
+ SCAN_ACTION_UPDATE,
+};
+
static bt_le_scan_cb_t *scan_dev_found_cb;
static sys_slist_t scan_cbs = SYS_SLIST_STATIC_INIT(&scan_cbs);
+static struct scanner_state scan_state;
+
#if defined(CONFIG_BT_EXT_ADV)
/* A buffer used to reassemble advertisement data from the controller. */
NET_BUF_SIMPLE_DEFINE(ext_scan_buf, CONFIG_BT_EXT_SCAN_BUF_SIZE);
@@ -77,7 +99,7 @@
#endif /* defined(CONFIG_BT_PER_ADV_SYNC) */
#endif /* defined(CONFIG_BT_EXT_ADV) */
-void bt_scan_reset(void)
+void bt_scan_softreset(void)
{
scan_dev_found_cb = NULL;
#if defined(CONFIG_BT_EXT_ADV)
@@ -85,7 +107,15 @@
#endif
}
-static int set_le_ext_scan_enable(uint8_t enable, uint16_t duration)
+void bt_scan_reset(void)
+{
+ memset(&scan_state, 0x0, sizeof(scan_state));
+ k_mutex_init(&scan_state.scan_update_mutex);
+ k_mutex_init(&scan_state.scan_explicit_params_mutex);
+ bt_scan_softreset();
+}
+
+static int cmd_le_set_ext_scan_enable(bool enable, bool filter_duplicates, uint16_t duration)
{
struct bt_hci_cp_le_set_ext_scan_enable *cp;
struct bt_hci_cmd_state_set state;
@@ -99,13 +129,7 @@
cp = net_buf_add(buf, sizeof(*cp));
- if (enable == BT_HCI_LE_SCAN_ENABLE) {
- cp->filter_dup = atomic_test_bit(bt_dev.flags,
- BT_DEV_SCAN_FILTER_DUP);
- } else {
- cp->filter_dup = BT_HCI_LE_SCAN_FILTER_DUP_DISABLE;
- }
-
+ cp->filter_dup = filter_duplicates;
cp->enable = enable;
cp->duration = sys_cpu_to_le16(duration);
cp->period = 0;
@@ -121,7 +145,7 @@
return 0;
}
-static int bt_le_scan_set_enable_legacy(uint8_t enable)
+static int cmd_le_set_scan_enable_legacy(bool enable, bool filter_duplicates)
{
struct bt_hci_cp_le_set_scan_enable *cp;
struct bt_hci_cmd_state_set state;
@@ -135,13 +159,7 @@
cp = net_buf_add(buf, sizeof(*cp));
- if (enable == BT_HCI_LE_SCAN_ENABLE) {
- cp->filter_dup = atomic_test_bit(bt_dev.flags,
- BT_DEV_SCAN_FILTER_DUP);
- } else {
- cp->filter_dup = BT_HCI_LE_SCAN_FILTER_DUP_DISABLE;
- }
-
+ cp->filter_dup = filter_duplicates;
cp->enable = enable;
bt_hci_cmd_state_set_init(buf, &state, bt_dev.flags, BT_DEV_SCANNING,
@@ -155,20 +173,49 @@
return 0;
}
-int bt_le_scan_set_enable(uint8_t enable)
+static int cmd_le_set_scan_enable(bool enable, bool filter_duplicates)
{
- if (IS_ENABLED(CONFIG_BT_EXT_ADV) &&
- BT_DEV_FEAT_LE_EXT_ADV(bt_dev.le.features)) {
- return set_le_ext_scan_enable(enable, 0);
+ if (IS_ENABLED(CONFIG_BT_EXT_ADV) && BT_DEV_FEAT_LE_EXT_ADV(bt_dev.le.features)) {
+ return cmd_le_set_ext_scan_enable(enable, filter_duplicates, 0);
}
- return bt_le_scan_set_enable_legacy(enable);
+ return cmd_le_set_scan_enable_legacy(enable, filter_duplicates);
}
-static int start_le_scan_ext(struct bt_hci_ext_scan_phy *phy_1m,
- struct bt_hci_ext_scan_phy *phy_coded,
- uint16_t duration)
+int bt_le_scan_set_enable(uint8_t enable)
{
+ return cmd_le_set_scan_enable(enable, scan_state.used_scan_param.options &
+ BT_LE_SCAN_OPT_FILTER_DUPLICATE);
+}
+
+static int start_le_scan_ext(struct bt_le_scan_param *scan_param)
+{
+ struct bt_hci_ext_scan_phy param_1m;
+ struct bt_hci_ext_scan_phy param_coded;
+
+ struct bt_hci_ext_scan_phy *phy_1m = NULL;
+ struct bt_hci_ext_scan_phy *phy_coded = NULL;
+
+ if (!(scan_param->options & BT_LE_SCAN_OPT_NO_1M)) {
+ param_1m.type = scan_param->type;
+ param_1m.interval = sys_cpu_to_le16(scan_param->interval);
+ param_1m.window = sys_cpu_to_le16(scan_param->window);
+
+ phy_1m = ¶m_1m;
+ }
+
+ if (scan_param->options & BT_LE_SCAN_OPT_CODED) {
+ uint16_t interval = scan_param->interval_coded ? scan_param->interval_coded
+ : scan_param->interval;
+ uint16_t window =
+ scan_param->window_coded ? scan_param->window_coded : scan_param->window;
+
+ param_coded.type = scan_param->type;
+ param_coded.interval = sys_cpu_to_le16(interval);
+ param_coded.window = sys_cpu_to_le16(window);
+ phy_coded = ¶m_coded;
+ }
+
struct bt_hci_cp_le_set_ext_scan_param *set_param;
struct net_buf *buf;
uint8_t own_addr_type;
@@ -178,7 +225,7 @@
active_scan = (phy_1m && phy_1m->type == BT_HCI_LE_SCAN_ACTIVE) ||
(phy_coded && phy_coded->type == BT_HCI_LE_SCAN_ACTIVE);
- if (duration > 0) {
+ if (scan_param->timeout > 0) {
atomic_set_bit(bt_dev.flags, BT_DEV_SCAN_LIMITED);
/* Allow bt_le_oob_get_local to be called directly before
@@ -205,13 +252,9 @@
set_param = net_buf_add(buf, sizeof(*set_param));
set_param->own_addr_type = own_addr_type;
set_param->phys = 0;
-
- if (IS_ENABLED(CONFIG_BT_FILTER_ACCEPT_LIST) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_SCAN_FILTERED)) {
- set_param->filter_policy = BT_HCI_LE_SCAN_FP_BASIC_FILTER;
- } else {
- set_param->filter_policy = BT_HCI_LE_SCAN_FP_BASIC_NO_FILTER;
- }
+ set_param->filter_policy = scan_param->options & BT_LE_SCAN_OPT_FILTER_ACCEPT_LIST
+ ? BT_HCI_LE_SCAN_FP_BASIC_FILTER
+ : BT_HCI_LE_SCAN_FP_BASIC_NO_FILTER;
if (phy_1m) {
set_param->phys |= BT_HCI_LE_EXT_SCAN_PHY_1M;
@@ -228,17 +271,17 @@
return err;
}
- err = set_le_ext_scan_enable(BT_HCI_LE_SCAN_ENABLE, duration);
+ err = cmd_le_set_ext_scan_enable(BT_HCI_LE_SCAN_ENABLE,
+ scan_param->options & BT_LE_SCAN_OPT_FILTER_DUPLICATE,
+ scan_param->timeout);
if (err) {
return err;
}
- atomic_set_bit_to(bt_dev.flags, BT_DEV_ACTIVE_SCAN, active_scan);
-
return 0;
}
-static int start_le_scan_legacy(uint8_t scan_type, uint16_t interval, uint16_t window)
+static int start_le_scan_legacy(struct bt_le_scan_param *param)
{
struct bt_hci_cp_le_set_scan_param set_param;
struct net_buf *buf;
@@ -247,22 +290,22 @@
(void)memset(&set_param, 0, sizeof(set_param));
- set_param.scan_type = scan_type;
+ set_param.scan_type = param->type;
/* for the rest parameters apply default values according to
* spec 4.2, vol2, part E, 7.8.10
*/
- set_param.interval = sys_cpu_to_le16(interval);
- set_param.window = sys_cpu_to_le16(window);
+ set_param.interval = sys_cpu_to_le16(param->interval);
+ set_param.window = sys_cpu_to_le16(param->window);
if (IS_ENABLED(CONFIG_BT_FILTER_ACCEPT_LIST) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_SCAN_FILTERED)) {
+ param->options & BT_LE_SCAN_OPT_FILTER_ACCEPT_LIST) {
set_param.filter_policy = BT_HCI_LE_SCAN_FP_BASIC_FILTER;
} else {
set_param.filter_policy = BT_HCI_LE_SCAN_FP_BASIC_NO_FILTER;
}
- active_scan = scan_type == BT_HCI_LE_SCAN_ACTIVE;
+ active_scan = param->type == BT_HCI_LE_SCAN_ACTIVE;
err = bt_id_set_scan_own_addr(active_scan, &set_param.addr_type);
if (err) {
return err;
@@ -280,99 +323,205 @@
return err;
}
- err = bt_le_scan_set_enable(BT_HCI_LE_SCAN_ENABLE);
+ err = cmd_le_set_scan_enable(BT_HCI_LE_SCAN_ENABLE,
+ param->options & BT_LE_SCAN_OPT_FILTER_DUPLICATE);
if (err) {
return err;
}
- atomic_set_bit_to(bt_dev.flags, BT_DEV_ACTIVE_SCAN, active_scan);
+ return 0;
+}
+
+bool bt_le_scan_active_scanner_running(void)
+{
+ return atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING) &&
+ scan_state.used_scan_param.type == BT_LE_SCAN_TYPE_ACTIVE;
+}
+
+static void select_scan_params(struct bt_le_scan_param *scan_param)
+{
+ /* From high priority to low priority: select parameters */
+ /* 1. Priority: explicitly chosen parameters */
+ if (atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN)) {
+ memcpy(scan_param, &scan_state.explicit_scan_param, sizeof(*scan_param));
+ }
+ /* Below this, the scanner module chooses the parameters. */
+ /* 2. Priority: reuse parameters from initiator */
+ else if (atomic_test_bit(bt_dev.flags, BT_DEV_INITIATING)) {
+ *scan_param = (struct bt_le_scan_param){
+ .type = BT_LE_SCAN_TYPE_PASSIVE,
+ .options = BT_LE_SCAN_OPT_FILTER_DUPLICATE,
+ .interval = bt_dev.create_param.interval,
+ .window = bt_dev.create_param.window,
+ .timeout = 0,
+ .interval_coded = bt_dev.create_param.interval_coded,
+ .window_coded = bt_dev.create_param.window_coded,
+ };
+ }
+ /* 3. Priority: choose custom parameters */
+ else {
+ *scan_param = (struct bt_le_scan_param){
+ .type = BT_LE_SCAN_TYPE_PASSIVE,
+ .options = BT_LE_SCAN_OPT_FILTER_DUPLICATE,
+ .interval = CONFIG_BT_BACKGROUND_SCAN_INTERVAL,
+ .window = CONFIG_BT_BACKGROUND_SCAN_WINDOW,
+ .timeout = 0,
+ .interval_coded = 0,
+ .window_coded = 0,
+ };
+
+ if (BT_FEAT_LE_PHY_CODED(bt_dev.le.features)) {
+ scan_param->options |= BT_LE_SCAN_OPT_CODED;
+ }
+
+ if (atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_PER_SYNC) ||
+ atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_CONN)) {
+ scan_param->window = BT_GAP_SCAN_FAST_WINDOW;
+ scan_param->interval = BT_GAP_SCAN_FAST_INTERVAL;
+ }
+ }
+}
+
+static int start_scan(struct bt_le_scan_param *scan_param)
+{
+ if (IS_ENABLED(CONFIG_BT_EXT_ADV) && BT_DEV_FEAT_LE_EXT_ADV(bt_dev.le.features)) {
+ return start_le_scan_ext(scan_param);
+ }
+
+ return start_le_scan_legacy(scan_param);
+}
+
+static bool is_already_using_same_params(struct bt_le_scan_param *scan_param)
+{
+ return !memcmp(scan_param, &scan_state.used_scan_param, sizeof(*scan_param));
+}
+
+static enum scan_action get_scan_action(struct bt_le_scan_param *scan_param)
+{
+ bool is_scanning = atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING);
+
+ /* Check if there is reason to have the scanner running */
+ if (atomic_get(scan_state.scan_flags) != 0) {
+ if (is_scanning) {
+ if (is_already_using_same_params(scan_param)) {
+ /* Already scanning with the desired parameters */
+ return SCAN_ACTION_NONE;
+ } else {
+ return SCAN_ACTION_UPDATE;
+ }
+ } else {
+ return SCAN_ACTION_START;
+ }
+ } else {
+ /* Scanner should not run */
+ if (is_scanning) {
+ return SCAN_ACTION_STOP;
+ } else {
+ return SCAN_ACTION_NONE;
+ }
+ }
+}
+
+static int scan_update(void)
+{
+ int32_t err;
+
+ struct bt_le_scan_param scan_param;
+
+ /* Prevent partial updates of the scanner state. */
+ err = k_mutex_lock(&scan_state.scan_update_mutex, K_NO_WAIT);
+
+ if (err) {
+ return err;
+ }
+
+ select_scan_params(&scan_param);
+
+ enum scan_action action = get_scan_action(&scan_param);
+
+ /* start/stop/update if required and allowed */
+ switch (action) {
+ case SCAN_ACTION_NONE:
+ break;
+ case SCAN_ACTION_STOP:
+ err = cmd_le_set_scan_enable(BT_HCI_LE_SCAN_DISABLE,
+ BT_HCI_LE_SCAN_FILTER_DUP_DISABLE);
+ if (err) {
+ LOG_DBG("Could not stop scanner: %d", err);
+ break;
+ }
+ memset(&scan_state.used_scan_param, 0x0,
+ sizeof(scan_state.used_scan_param));
+ break;
+ case SCAN_ACTION_UPDATE:
+ err = cmd_le_set_scan_enable(BT_HCI_LE_SCAN_DISABLE,
+ BT_HCI_LE_SCAN_FILTER_DUP_DISABLE);
+ if (err) {
+ LOG_DBG("Could not stop scanner to update: %d", err);
+ break;
+ }
+ __fallthrough;
+ case SCAN_ACTION_START:
+ err = start_scan(&scan_param);
+ if (err) {
+ LOG_DBG("Could not start scanner: %d", err);
+ break;
+ }
+ memcpy(&scan_state.used_scan_param, &scan_param, sizeof(scan_param));
+ break;
+ }
+
+ k_mutex_unlock(&scan_state.scan_update_mutex);
+
+ return err;
+}
+
+static uint32_t scan_check_if_state_allowed(enum bt_le_scan_user flag)
+{
+ /* check if state is already set */
+ if (atomic_test_bit(scan_state.scan_flags, flag)) {
+ return -EALREADY;
+ }
+
+ if (flag == BT_LE_SCAN_USER_EXPLICIT_SCAN && !BT_LE_STATES_SCAN_INIT(bt_dev.le.states) &&
+ atomic_test_bit(bt_dev.flags, BT_DEV_INITIATING)) {
+ return -EPERM;
+ }
return 0;
}
-static int start_host_initiated_scan(bool fast_scan)
+int bt_le_scan_user_add(enum bt_le_scan_user flag)
{
- uint16_t interval, window;
+ uint32_t err;
- if (fast_scan) {
- interval = BT_GAP_SCAN_FAST_INTERVAL;
- window = BT_GAP_SCAN_FAST_WINDOW;
- } else {
- interval = CONFIG_BT_BACKGROUND_SCAN_INTERVAL;
- window = CONFIG_BT_BACKGROUND_SCAN_WINDOW;
- }
-
- if (IS_ENABLED(CONFIG_BT_EXT_ADV) &&
- BT_DEV_FEAT_LE_EXT_ADV(bt_dev.le.features)) {
- struct bt_hci_ext_scan_phy scan_phy_params;
-
- scan_phy_params.type = BT_HCI_LE_SCAN_PASSIVE;
- scan_phy_params.interval = sys_cpu_to_le16(interval);
- scan_phy_params.window = sys_cpu_to_le16(window);
-
- /* Scan on 1M + Coded if the controller supports it*/
- if (BT_FEAT_LE_PHY_CODED(bt_dev.le.features)) {
- return start_le_scan_ext(&scan_phy_params, &scan_phy_params, 0);
- } else {
- return start_le_scan_ext(&scan_phy_params, NULL, 0);
- }
-
- }
-
- return start_le_scan_legacy(BT_HCI_LE_SCAN_PASSIVE, interval, window);
-}
-
-int bt_le_scan_update(bool fast_scan)
-{
- if (atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
- /* The application has already explicitly started scanning.
- * We should keep the scanner running to avoid changing scan parameters.
+ if (flag == BT_LE_SCAN_USER_NONE) {
+ /* Only check if the scanner parameters should be updated / the scanner should be
+ * started. This is mainly triggered once connections are established.
*/
- return 0;
- }
-
- if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
- int err;
-
- err = bt_le_scan_set_enable(BT_HCI_LE_SCAN_DISABLE);
+ } else {
+ /* Check if it can be enabled */
+ err = scan_check_if_state_allowed(flag);
if (err) {
return err;
}
+ atomic_set_bit(scan_state.scan_flags, flag);
}
- if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
- struct bt_conn *conn;
+ return scan_update();
+}
- if (!BT_LE_STATES_SCAN_INIT(bt_dev.le.states)) {
- /* don't restart scan if we have pending connection */
- conn = bt_conn_lookup_state_le(BT_ID_DEFAULT, NULL,
- BT_CONN_INITIATING);
- if (conn) {
- bt_conn_unref(conn);
- return 0;
- }
- }
-
- conn = bt_conn_lookup_state_le(BT_ID_DEFAULT, NULL,
- BT_CONN_SCAN_BEFORE_INITIATING);
- if (conn) {
- atomic_set_bit(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP);
-
- bt_conn_unref(conn);
-
- /* Start/Restart the scanner */
- return start_host_initiated_scan(fast_scan);
- }
+int bt_le_scan_user_remove(enum bt_le_scan_user flag)
+{
+ if (flag == BT_LE_SCAN_USER_NONE) {
+ /* Only check if the scanner parameters should be updated / the scanner should be
+ * started. This is mainly triggered once connections are established.
+ */
+ } else {
+ atomic_clear_bit(scan_state.scan_flags, flag);
}
-#if defined(CONFIG_BT_PER_ADV_SYNC)
- if (get_pending_per_adv_sync()) {
- /* Start/Restart the scanner. */
- return start_host_initiated_scan(fast_scan);
- }
-#endif
-
- return 0;
+ return scan_update();
}
#if defined(CONFIG_BT_CENTRAL)
@@ -380,12 +529,13 @@
const bt_addr_le_t *addr, uint8_t adv_props)
{
struct bt_conn *conn;
+ int err;
/* No connections are allowed during explicit scanning
* when the controller does not support concurrent scanning and initiating.
*/
if (!BT_LE_STATES_SCAN_INIT(bt_dev.le.states) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
+ atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN)) {
return;
}
@@ -400,11 +550,13 @@
return;
}
- if (!BT_LE_STATES_SCAN_INIT(bt_dev.le.states)) {
- if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING) &&
- bt_le_scan_set_enable(BT_HCI_LE_SCAN_DISABLE)) {
- goto failed;
- }
+ /* Stop the scanner if there is no other reason to have it running.
+ * Ignore possible failures here, since the user is guaranteed to be removed
+ * and the scanner state is updated once the initiator starts / stops.
+ */
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_CONN);
+ if (err) {
+ LOG_DBG("Error while removing conn user from scanner (%d)", err);
}
bt_addr_le_copy(&conn->le.resp_addr, addr);
@@ -420,7 +572,12 @@
conn->err = BT_HCI_ERR_UNSPECIFIED;
bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
bt_conn_unref(conn);
- bt_le_scan_update(false);
+ /* Just a best-effort check if the scanner should be started. */
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_NONE);
+
+ if (err) {
+ LOG_WRN("Error while updating the scanner (%d)", err);
+ }
}
#endif /* CONFIG_BT_CENTRAL */
@@ -465,9 +622,8 @@
LOG_DBG("%s event %u, len %u, rssi %d dBm", bt_addr_le_str(addr), info->adv_type, len,
info->rssi);
- if (!IS_ENABLED(CONFIG_BT_PRIVACY) &&
- !IS_ENABLED(CONFIG_BT_SCAN_WITH_IDENTITY) &&
- atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN) &&
+ if (!IS_ENABLED(CONFIG_BT_PRIVACY) && !IS_ENABLED(CONFIG_BT_SCAN_WITH_IDENTITY) &&
+ atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN) &&
(info->adv_props & BT_HCI_LE_ADV_PROP_DIRECT)) {
LOG_DBG("Dropped direct adv report");
return;
@@ -517,8 +673,16 @@
{
struct bt_le_scan_cb *listener, *next;
- atomic_clear_bit(bt_dev.flags, BT_DEV_SCANNING);
- atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
+ int err = bt_le_scan_user_remove(BT_LE_SCAN_USER_EXPLICIT_SCAN);
+
+ if (err) {
+ k_yield();
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_EXPLICIT_SCAN);
+ }
+
+ if (err) {
+ LOG_WRN("Could not stop the explicit scanner (%d)", err);
+ }
atomic_clear_bit(bt_dev.flags, BT_DEV_SCAN_LIMITED);
atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);
@@ -610,7 +774,7 @@
bool more_to_come;
bool is_new_advertiser;
- if (!atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
+ if (!atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN)) {
/* The application has not requested explicit scan, so it is not expecting
* advertising reports. Discard, and reset the reassembler if not inactive
* This is done in the loop as this flag can change between each iteration,
@@ -1014,9 +1178,8 @@
pending_per_adv_sync = get_pending_per_adv_sync();
if (pending_per_adv_sync) {
- atomic_clear_bit(pending_per_adv_sync->flags,
- BT_PER_ADV_SYNC_SYNCING);
- err = bt_le_scan_update(false);
+ atomic_clear_bit(pending_per_adv_sync->flags, BT_PER_ADV_SYNC_SYNCING);
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_PER_SYNC);
if (err) {
LOG_ERR("Could not update scan (%d)", err);
@@ -1474,7 +1637,7 @@
while (num_reports--) {
struct bt_le_scan_recv_info adv_info;
- if (!atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
+ if (!atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN)) {
/* The application has not requested explicit scan, so it is not expecting
* advertising reports. Discard.
* This is done in the loop as this flag can change between each iteration,
@@ -1577,91 +1740,37 @@
return -EINVAL;
}
- /* Return if active scan is already enabled */
- if (atomic_test_and_set_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
- return -EALREADY;
- }
-
- if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
- err = bt_le_scan_set_enable(BT_HCI_LE_SCAN_DISABLE);
- if (err) {
- atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
- return err;
- }
- }
-
- atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP,
- param->options & BT_LE_SCAN_OPT_FILTER_DUPLICATE);
-
-#if defined(CONFIG_BT_FILTER_ACCEPT_LIST)
- atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_FILTERED,
- param->options & BT_LE_SCAN_OPT_FILTER_ACCEPT_LIST);
-#endif /* defined(CONFIG_BT_FILTER_ACCEPT_LIST) */
-
- if (IS_ENABLED(CONFIG_BT_EXT_ADV) &&
- BT_DEV_FEAT_LE_EXT_ADV(bt_dev.le.features)) {
- if (IS_ENABLED(CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL) && param->timeout) {
- atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
- return -ENOTSUP;
- }
-
- struct bt_hci_ext_scan_phy param_1m;
- struct bt_hci_ext_scan_phy param_coded;
-
- struct bt_hci_ext_scan_phy *phy_1m = NULL;
- struct bt_hci_ext_scan_phy *phy_coded = NULL;
-
- if (!(param->options & BT_LE_SCAN_OPT_NO_1M)) {
- param_1m.type = param->type;
- param_1m.interval = sys_cpu_to_le16(param->interval);
- param_1m.window = sys_cpu_to_le16(param->window);
-
- phy_1m = ¶m_1m;
- }
-
- if (param->options & BT_LE_SCAN_OPT_CODED) {
- uint16_t interval = param->interval_coded ?
- param->interval_coded :
- param->interval;
- uint16_t window = param->window_coded ?
- param->window_coded :
- param->window;
-
- param_coded.type = param->type;
- param_coded.interval = sys_cpu_to_le16(interval);
- param_coded.window = sys_cpu_to_le16(window);
- phy_coded = ¶m_coded;
- }
-
- err = start_le_scan_ext(phy_1m, phy_coded, param->timeout);
- } else {
- if (param->timeout) {
- atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
- return -ENOTSUP;
- }
-
- err = start_le_scan_legacy(param->type, param->interval,
- param->window);
- }
+ /* Prevent multiple threads to try to enable explicit scanning at the same time.
+ * That could lead to unwanted overwriting of scan_state.explicit_scan_param.
+ */
+ err = k_mutex_lock(&scan_state.scan_explicit_params_mutex, K_NO_WAIT);
if (err) {
- atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
return err;
}
- scan_dev_found_cb = cb;
+ err = scan_check_if_state_allowed(BT_LE_SCAN_USER_EXPLICIT_SCAN);
- return 0;
+ if (err) {
+ k_mutex_unlock(&scan_state.scan_explicit_params_mutex);
+ return err;
+ }
+
+ /* store the parameters that were used to start the scanner */
+ memcpy(&scan_state.explicit_scan_param, param,
+ sizeof(scan_state.explicit_scan_param));
+
+ scan_dev_found_cb = cb;
+ err = bt_le_scan_user_add(BT_LE_SCAN_USER_EXPLICIT_SCAN);
+ k_mutex_unlock(&scan_state.scan_explicit_params_mutex);
+
+ return err;
}
int bt_le_scan_stop(void)
{
- /* Return if active scanning is already disabled */
- if (!atomic_test_and_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
- return -EALREADY;
- }
-
- bt_scan_reset();
+ bt_scan_softreset();
+ scan_dev_found_cb = NULL;
if (IS_ENABLED(CONFIG_BT_EXT_ADV) &&
atomic_test_and_clear_bit(bt_dev.flags, BT_DEV_SCAN_LIMITED)) {
@@ -1672,7 +1781,7 @@
#endif
}
- return bt_le_scan_update(false);
+ return bt_le_scan_user_remove(BT_LE_SCAN_USER_EXPLICIT_SCAN);
}
int bt_le_scan_cb_register(struct bt_le_scan_cb *cb)
@@ -1844,13 +1953,16 @@
* established. We don't need to use any callbacks since we rely on
* the advertiser address in the sync params.
*/
- if (!atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
- err = bt_le_scan_update(true);
+ err = bt_le_scan_user_add(BT_LE_SCAN_USER_PER_SYNC);
+ if (err) {
+ int per_sync_remove_err = bt_le_scan_user_remove(BT_LE_SCAN_USER_PER_SYNC);
- if (err) {
- bt_le_per_adv_sync_delete(per_adv_sync);
- return err;
+ if (per_sync_remove_err) {
+ LOG_WRN("Error while updating the scanner (%d)", per_sync_remove_err);
}
+
+ bt_le_per_adv_sync_delete(per_adv_sync);
+ return err;
}
*out_sync = per_adv_sync;
@@ -1870,6 +1982,12 @@
return -EINVAL;
}
+ err = bt_le_scan_user_remove(BT_LE_SCAN_USER_PER_SYNC);
+
+ if (err) {
+ return err;
+ }
+
buf = bt_hci_cmd_create(BT_HCI_OP_LE_PER_ADV_CREATE_SYNC_CANCEL, 0);
if (!buf) {
return -ENOBUFS;
@@ -2285,3 +2403,8 @@
return 0;
}
#endif /* defined(CONFIG_BT_PER_ADV_SYNC) */
+
+bool bt_le_explicit_scanner_running(void)
+{
+ return atomic_test_bit(scan_state.scan_flags, BT_LE_SCAN_USER_EXPLICIT_SCAN);
+}
diff --git a/subsys/bluetooth/host/scan.h b/subsys/bluetooth/host/scan.h
index d369359..b30adfc 100644
--- a/subsys/bluetooth/host/scan.h
+++ b/subsys/bluetooth/host/scan.h
@@ -5,10 +5,120 @@
* SPDX-License-Identifier: Apache-2.0
*/
+#ifndef SUBSYS_BLUETOOTH_HOST_SCAN_H_
+#define SUBSYS_BLUETOOTH_HOST_SCAN_H_
+
+#include <stdint.h>
+
+#include <zephyr/sys/atomic.h>
+#include <zephyr/bluetooth/bluetooth.h>
+
+/**
+ * Reasons why a scanner can be running.
+ * Used as input to @ref bt_le_scan_user_add
+ * and @ref bt_le_scan_user_remove.
+ */
+enum bt_le_scan_user {
+ /** The application explicitly instructed the stack to scan for advertisers
+ * using the API @ref bt_le_scan_start.
+ * Users of the scanner module may not use this flag as input to @ref bt_le_scan_user_add
+ * and @ref bt_le_scan_user_remove. Use ®ref bt_le_scan_start and @ref bt_le_scan_stop
+ * instead.
+ */
+ BT_LE_SCAN_USER_EXPLICIT_SCAN,
+
+ /**
+ * Periodic sync syncing to a periodic advertiser.
+ */
+ BT_LE_SCAN_USER_PER_SYNC,
+
+ /**
+ * Scanning to find devices to connect to.
+ */
+ BT_LE_SCAN_USER_CONN,
+
+ /**
+ * Special state for a NOP for @ref bt_le_scan_user_add and @ref bt_le_scan_user_remove to
+ * not add/remove any user.
+ */
+ BT_LE_SCAN_USER_NONE,
+ BT_LE_SCAN_USER_NUM_FLAGS,
+};
+
void bt_scan_reset(void);
bool bt_id_scan_random_addr_check(void);
+bool bt_le_scan_active_scanner_running(void);
int bt_le_scan_set_enable(uint8_t enable);
void bt_periodic_sync_disable(void);
+
+/**
+ * Start / update the scanner.
+ *
+ * This API updates the users of the scanner.
+ * Multiple users can be enabled at the same time.
+ * Depending on all the users, scan parameters are selected
+ * and the scanner is started or updated, if needed.
+ * This API may update the scan parameters, for example if the scanner is already running
+ * when another user that demands higher duty-cycle is being added.
+ * It is not allowed to add a user that was already added.
+ *
+ * Every SW module that informs the scanner that it should run, needs to eventually remove
+ * the flag again using @ref bt_le_scan_user_remove once it does not require
+ * the scanner to run, anymore.
+ *
+ * If flag is set to @ref BT_LE_SCAN_USER_NONE, no user is being added. Instead, the
+ * existing users are checked and the scanner is started, stopped or updated.
+ * For platforms where scanning and initiating at the same time is not supported,
+ * this allows the background scanner to be started or stopped once the device starts to
+ * initiate a connection.
+ *
+ * @param flag user requesting the scanner
+ *
+ * @retval 0 in case of success
+ * @retval -EALREADY if the user is already enabled
+ * @retval -EPERM if the explicit scanner is being enabled while the initiator is running
+ * and the device does not support this configuration.
+ * @retval -ENOBUFS if no hci command buffer could be allocated
+ * @retval -EBUSY if the scanner is updated in a different thread. The user was added but
+ * the scanner was not started/stopped/updated.
+ * @returns negative error codes for errors in @ref bt_hci_cmd_send_sync
+ */
+int bt_le_scan_user_add(enum bt_le_scan_user flag);
+
+/**
+ * Stop / update the scanner.
+ *
+ * This API updates the users of the scanner.
+ * Depending on all enabled users, scan parameters are selected
+ * and the scanner is stopped or updated, if needed.
+ * This API may update the scan parameters, for example if the scanner is already running
+ * when a user that demands higher duty-cycle is being removed.
+ * Removing a user that was not added does not result in an error.
+ *
+ * This API allows removing the user why the scanner is running.
+ * If all users for the scanner to run are removed, this API will stop the scanner.
+ *
+ * If flag is set to @ref BT_LE_SCAN_USER_NONE, no user is being added. Instead, the
+ * existing users are checked and the scanner is started, stopped or updated.
+ * For platforms where scanning and initiating at the same time is not supported,
+ * this allows the background scanner to be started or stopped once the device starts to
+ * initiate a connection.
+ *
+ * @param flag user releasing the scanner
+ *
+ * @retval 0 in case of success
+ * @retval -ENOBUFS if no hci command buffer could be allocated
+ * @retval -EBUSY if the scanner is updated in a different thread. The user was removed but
+ * the scanner was not started/stopped/updated.
+ * @returns negative error codes for errors in @ref bt_hci_cmd_send_sync
+ */
+int bt_le_scan_user_remove(enum bt_le_scan_user flag);
+
+/**
+ * Check if the explicit scanner was enabled.
+ */
+bool bt_le_explicit_scanner_running(void);
+#endif /* defined SUBSYS_BLUETOOTH_HOST_SCAN_H_ */
diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig
index 2b5dd5f..fb0d8ec 100644
--- a/subsys/bluetooth/mesh/Kconfig
+++ b/subsys/bluetooth/mesh/Kconfig
@@ -895,6 +895,18 @@
help
The timer value that Pull BLOB Transfer Server uses to report missed chunks.
+config BT_MESH_RX_BLOB_CHUNK_SIZE
+ depends on !BT_MESH_ALIGN_CHUNK_SIZE_TO_MAX_SEGMENT
+ int "BLOB Server chunk size"
+ default 8
+ range 8 377
+ help
+ Set the chunk size for the BLOB Server.
+ The actual maximum chunk size depends on how many segments are
+ possible and will be clamped to the max possible if set above.
+ see also: BT_MESH_RX_SEG_MAX,
+ and the maximum SDU a node can receive.
+
endif # BT_MESH_BLOB_SRV
menuconfig BT_MESH_BLOB_CLI
@@ -911,11 +923,27 @@
Controls the number of times the client will attempt to resend missing
chunks to the BLOB receivers for every block.
-endif
+config BT_MESH_TX_BLOB_CHUNK_SIZE
+ depends on !BT_MESH_ALIGN_CHUNK_SIZE_TO_MAX_SEGMENT
+ int "BLOB Client chunk size"
+ default 8
+ range 1 377
+ help
+ Set the chunk size for the BLOB Client.
+ The actual maximum chunk size depends on how many segments are
+ possible and will be clamped to the max possible if set above.
+ see also: BT_MESH_TX_SEG_MAX,
+ and the maximum SDU a node can receive.
+
+endif # BT_MESH_BLOB_CLI
menu "BLOB models common configuration"
visible if BT_MESH_BLOB_SRV || BT_MESH_BLOB_CLI
+config BT_MESH_ALIGN_CHUNK_SIZE_TO_MAX_SEGMENT
+ bool "Align chunk size to max segmented message size"
+ default y
+
config BT_MESH_BLOB_CHUNK_COUNT_MAX
int "Maximum chunk count per block"
default 256
diff --git a/subsys/bluetooth/mesh/blob.h b/subsys/bluetooth/mesh/blob.h
index 2898dcd..1627254 100644
--- a/subsys/bluetooth/mesh/blob.h
+++ b/subsys/bluetooth/mesh/blob.h
@@ -27,6 +27,20 @@
#define BLOB_CHUNK_SIZE_MAX(sdu_max) ((sdu_max) - BLOB_CHUNK_SDU_OVERHEAD)
#define BLOB_CHUNK_SDU_LEN(chunk_size) (BLOB_CHUNK_SDU_OVERHEAD + (chunk_size))
+#if CONFIG_BT_MESH_ALIGN_CHUNK_SIZE_TO_MAX_SEGMENT || \
+ CONFIG_BT_MESH_RX_BLOB_CHUNK_SIZE > BLOB_CHUNK_SIZE_MAX(BT_MESH_RX_SDU_MAX)
+#define BLOB_RX_CHUNK_SIZE BLOB_CHUNK_SIZE_MAX(BT_MESH_RX_SDU_MAX)
+#else
+#define BLOB_RX_CHUNK_SIZE CONFIG_BT_MESH_RX_BLOB_CHUNK_SIZE
+#endif
+
+#if CONFIG_BT_MESH_ALIGN_CHUNK_SIZE_TO_MAX_SEGMENT || \
+ CONFIG_BT_MESH_TX_BLOB_CHUNK_SIZE > BLOB_CHUNK_SIZE_MAX(BT_MESH_TX_SDU_MAX)
+#define BLOB_TX_CHUNK_SIZE BLOB_CHUNK_SIZE_MAX(BT_MESH_TX_SDU_MAX)
+#else
+#define BLOB_TX_CHUNK_SIZE CONFIG_BT_MESH_TX_BLOB_CHUNK_SIZE
+#endif
+
/* Utility macros for calculating log2 of a number at compile time.
* Used to determine the log2 representation of the block size, which
* is configured as a raw number, but encoded as log2.
diff --git a/subsys/bluetooth/mesh/blob_cli.c b/subsys/bluetooth/mesh/blob_cli.c
index ab32d55..85502f3 100644
--- a/subsys/bluetooth/mesh/blob_cli.c
+++ b/subsys/bluetooth/mesh/blob_cli.c
@@ -19,8 +19,6 @@
SYS_SLIST_FOR_EACH_CONTAINER((sys_slist_t *)&(cli)->inputs->targets, \
target, n)
-#define CHUNK_SIZE_MAX BLOB_CHUNK_SIZE_MAX(BT_MESH_TX_SDU_MAX)
-
/* The Maximum BLOB Poll Interval - T_MBPI */
#define BLOB_POLL_TIME_MAX_SECS 30
@@ -1496,7 +1494,7 @@
cli->caps.min_block_size_log = 0x06;
cli->caps.max_block_size_log = 0x20;
cli->caps.max_chunks = CONFIG_BT_MESH_BLOB_CHUNK_COUNT_MAX;
- cli->caps.max_chunk_size = CHUNK_SIZE_MAX;
+ cli->caps.max_chunk_size = BLOB_TX_CHUNK_SIZE;
cli->caps.max_size = 0xffffffff;
cli->caps.mtu_size = 0xffff;
cli->caps.modes = BT_MESH_BLOB_XFER_MODE_ALL;
@@ -1521,9 +1519,9 @@
return -EBUSY;
}
- if (!(xfer->mode & BT_MESH_BLOB_XFER_MODE_ALL) ||
- xfer->block_size_log < 0x06 || xfer->block_size_log > 0x20 ||
- xfer->chunk_size < 8 || xfer->chunk_size > CHUNK_SIZE_MAX) {
+ if (!(xfer->mode & BT_MESH_BLOB_XFER_MODE_ALL) || xfer->block_size_log < 0x06 ||
+ xfer->block_size_log > 0x20 || xfer->chunk_size < 8 ||
+ xfer->chunk_size > BLOB_TX_CHUNK_SIZE) {
LOG_ERR("Incompatible transfer parameters");
return -EINVAL;
}
diff --git a/subsys/bluetooth/mesh/blob_io_flash.c b/subsys/bluetooth/mesh/blob_io_flash.c
index 31abd11..eb0b334 100644
--- a/subsys/bluetooth/mesh/blob_io_flash.c
+++ b/subsys/bluetooth/mesh/blob_io_flash.c
@@ -117,8 +117,7 @@
chunk->data, chunk->size);
}
- uint8_t buf[ROUND_UP(BLOB_CHUNK_SIZE_MAX(BT_MESH_RX_SDU_MAX),
- WRITE_BLOCK_SIZE)];
+ uint8_t buf[ROUND_UP(BLOB_RX_CHUNK_SIZE, WRITE_BLOCK_SIZE)];
off_t area_offset = flash->offset + block->offset + chunk->offset;
int i = 0;
diff --git a/subsys/bluetooth/mesh/blob_srv.c b/subsys/bluetooth/mesh/blob_srv.c
index 3773a17..2d4ec56 100644
--- a/subsys/bluetooth/mesh/blob_srv.c
+++ b/subsys/bluetooth/mesh/blob_srv.c
@@ -16,7 +16,6 @@
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_mesh_blob_srv);
-#define CHUNK_SIZE_MAX BLOB_CHUNK_SIZE_MAX(BT_MESH_RX_SDU_MAX)
#define MTU_SIZE_MAX (BT_MESH_RX_SDU_MAX - BT_MESH_MIC_SHORT)
/* The Receive BLOB Timeout Timer */
@@ -53,9 +52,8 @@
static inline uint32_t max_chunk_size(const struct bt_mesh_blob_srv *srv)
{
- return MIN((srv->state.mtu_size - 2 -
- BT_MESH_MODEL_OP_LEN(BT_MESH_BLOB_OP_CHUNK)),
- CHUNK_SIZE_MAX);
+ return MIN((srv->state.mtu_size - 2 - BT_MESH_MODEL_OP_LEN(BT_MESH_BLOB_OP_CHUNK)),
+ BLOB_RX_CHUNK_SIZE);
}
static inline uint32_t max_chunk_count(const struct bt_mesh_blob_srv *srv)
@@ -221,6 +219,7 @@
srv->state.xfer.mode = BT_MESH_BLOB_XFER_MODE_NONE;
srv->state.ttl = BT_MESH_TTL_DEFAULT;
srv->block.number = 0xffff;
+ memset(srv->block.missing, 0, sizeof(srv->block.missing));
srv->state.xfer.chunk_size = 0xffff;
k_work_cancel_delayable(&srv->rx_timeout);
k_work_cancel_delayable(&srv->pull.report);
@@ -822,7 +821,7 @@
net_buf_simple_add_u8(&rsp, BLOB_BLOCK_SIZE_LOG_MIN);
net_buf_simple_add_u8(&rsp, BLOB_BLOCK_SIZE_LOG_MAX);
net_buf_simple_add_le16(&rsp, CONFIG_BT_MESH_BLOB_CHUNK_COUNT_MAX);
- net_buf_simple_add_le16(&rsp, CHUNK_SIZE_MAX);
+ net_buf_simple_add_le16(&rsp, BLOB_RX_CHUNK_SIZE);
net_buf_simple_add_le32(&rsp, CONFIG_BT_MESH_BLOB_SIZE_MAX);
net_buf_simple_add_le16(&rsp, MTU_SIZE_MAX);
net_buf_simple_add_u8(&rsp, BT_MESH_BLOB_XFER_MODE_ALL);
diff --git a/subsys/bluetooth/mesh/proxy_srv.c b/subsys/bluetooth/mesh/proxy_srv.c
index ca5e8bb..f17e98f 100644
--- a/subsys/bluetooth/mesh/proxy_srv.c
+++ b/subsys/bluetooth/mesh/proxy_srv.c
@@ -783,7 +783,7 @@
{
int err;
- int32_t max_adv_duration;
+ int32_t max_adv_duration = 0;
int cnt;
struct bt_mesh_subnet *sub;
struct proxy_adv_request request;
diff --git a/subsys/bluetooth/services/CMakeLists.txt b/subsys/bluetooth/services/CMakeLists.txt
index 0955f20..c02eb79 100644
--- a/subsys/bluetooth/services/CMakeLists.txt
+++ b/subsys/bluetooth/services/CMakeLists.txt
@@ -3,12 +3,14 @@
zephyr_sources_ifdef(CONFIG_BT_DIS dis.c)
-zephyr_sources_ifdef(CONFIG_BT_BAS bas.c)
-
zephyr_sources_ifdef(CONFIG_BT_HRS hrs.c)
zephyr_sources_ifdef(CONFIG_BT_TPS tps.c)
+if(CONFIG_BT_BAS)
+ add_subdirectory(bas)
+endif()
+
if(CONFIG_BT_OTS OR CONFIG_BT_OTS_CLIENT)
add_subdirectory(ots)
endif()
diff --git a/subsys/bluetooth/services/Kconfig b/subsys/bluetooth/services/Kconfig
index f4a42ac..0377c06 100644
--- a/subsys/bluetooth/services/Kconfig
+++ b/subsys/bluetooth/services/Kconfig
@@ -8,8 +8,6 @@
rsource "Kconfig.dis"
-rsource "Kconfig.bas"
-
rsource "Kconfig.hrs"
rsource "Kconfig.tps"
@@ -20,4 +18,6 @@
rsource "ots/Kconfig"
+rsource "bas/Kconfig.bas"
+
endmenu
diff --git a/subsys/bluetooth/services/Kconfig.bas b/subsys/bluetooth/services/Kconfig.bas
deleted file mode 100644
index 2dbff5f..0000000
--- a/subsys/bluetooth/services/Kconfig.bas
+++ /dev/null
@@ -1,7 +0,0 @@
-# Bluetooth GATT Battery service
-
-# Copyright (c) 2018 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config BT_BAS
- bool "GATT Battery service"
diff --git a/subsys/bluetooth/services/bas.c b/subsys/bluetooth/services/bas.c
deleted file mode 100644
index 1896136..0000000
--- a/subsys/bluetooth/services/bas.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/** @file
- * @brief GATT Battery Service
- */
-
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2016 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <errno.h>
-#include <zephyr/init.h>
-#include <zephyr/sys/__assert.h>
-#include <stdbool.h>
-#include <zephyr/types.h>
-
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/gatt.h>
-#include <zephyr/bluetooth/uuid.h>
-#include <zephyr/bluetooth/services/bas.h>
-
-#define LOG_LEVEL CONFIG_BT_BAS_LOG_LEVEL
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(bas);
-
-static uint8_t battery_level = 100U;
-
-static void blvl_ccc_cfg_changed(const struct bt_gatt_attr *attr,
- uint16_t value)
-{
- ARG_UNUSED(attr);
-
- bool notif_enabled = (value == BT_GATT_CCC_NOTIFY);
-
- LOG_INF("BAS Notifications %s", notif_enabled ? "enabled" : "disabled");
-}
-
-static ssize_t read_blvl(struct bt_conn *conn,
- const struct bt_gatt_attr *attr, void *buf,
- uint16_t len, uint16_t offset)
-{
- uint8_t lvl8 = battery_level;
-
- return bt_gatt_attr_read(conn, attr, buf, len, offset, &lvl8,
- sizeof(lvl8));
-}
-
-/* Constant values from the Assigned Numbers specification:
- * https://www.bluetooth.com/wp-content/uploads/Files/Specification/Assigned_Numbers.pdf?id=89
- */
-static const struct bt_gatt_cpf level_cpf = {
- .format = 0x04, /* uint8 */
- .exponent = 0x0,
- .unit = 0x27AD, /* Percentage */
- .name_space = 0x01, /* Bluetooth SIG */
- .description = 0x0106, /* "main" */
-};
-
-BT_GATT_SERVICE_DEFINE(bas,
- BT_GATT_PRIMARY_SERVICE(BT_UUID_BAS),
- BT_GATT_CHARACTERISTIC(BT_UUID_BAS_BATTERY_LEVEL,
- BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY,
- BT_GATT_PERM_READ, read_blvl, NULL,
- &battery_level),
- BT_GATT_CCC(blvl_ccc_cfg_changed,
- BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),
- BT_GATT_CPF(&level_cpf),
-);
-
-static int bas_init(void)
-{
-
- return 0;
-}
-
-uint8_t bt_bas_get_battery_level(void)
-{
- return battery_level;
-}
-
-int bt_bas_set_battery_level(uint8_t level)
-{
- int rc;
-
- if (level > 100U) {
- return -EINVAL;
- }
-
- battery_level = level;
-
- rc = bt_gatt_notify(NULL, &bas.attrs[1], &level, sizeof(level));
-
- return rc == -ENOTCONN ? 0 : rc;
-}
-
-SYS_INIT(bas_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/subsys/bluetooth/services/bas/CMakeLists.txt b/subsys/bluetooth/services/bas/CMakeLists.txt
new file mode 100644
index 0000000..ff8bdaa
--- /dev/null
+++ b/subsys/bluetooth/services/bas/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_sources_ifdef(CONFIG_BT_BAS bas.c)
+zephyr_sources_ifdef(CONFIG_BT_BAS_BLS bas_bls.c)
diff --git a/subsys/bluetooth/services/bas/Kconfig.bas b/subsys/bluetooth/services/bas/Kconfig.bas
new file mode 100644
index 0000000..5eec755
--- /dev/null
+++ b/subsys/bluetooth/services/bas/Kconfig.bas
@@ -0,0 +1,30 @@
+# Bluetooth GATT Battery service
+
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BT_BAS
+ bool "GATT Battery service"
+
+config BT_BAS_BLS
+ bool "Battery Level Status"
+ help
+ Enable this option to include Battery Level Status Characteristic.
+
+if BT_BAS_BLS
+
+config BT_BAS_BLS_IDENTIFIER_PRESENT
+ bool "Battery Level Identifier Present"
+ help
+ Enable this option if the Battery Level Identifier is present.
+
+config BT_BAS_BLS_BATTERY_LEVEL_PRESENT
+ bool "Battery Level Present"
+ help
+ Enable this option if the Battery Level is present.
+
+config BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT
+ bool "Additional Battery Status Present"
+ help
+ Enable this option if Additional Battery Status information is present.
+endif
diff --git a/subsys/bluetooth/services/bas/bas.c b/subsys/bluetooth/services/bas/bas.c
new file mode 100644
index 0000000..6960107
--- /dev/null
+++ b/subsys/bluetooth/services/bas/bas.c
@@ -0,0 +1,134 @@
+/** @file
+ * @brief GATT Battery Service
+ */
+
+/*
+ * Copyright (c) 2024 Demant A/S
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/__assert.h>
+#include <stdbool.h>
+#include <zephyr/types.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/services/bas.h>
+#include "bas_internal.h"
+
+#define LOG_LEVEL CONFIG_BT_BAS_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bas, CONFIG_BT_BAS_LOG_LEVEL);
+
+static uint8_t battery_level = 100U;
+
+static void blvl_ccc_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
+{
+ ARG_UNUSED(attr);
+
+ bool notif_enabled = (value == BT_GATT_CCC_NOTIFY);
+
+ LOG_INF("BAS Notifications %s", notif_enabled ? "enabled" : "disabled");
+}
+
+#if defined(CONFIG_BT_BAS_BLS)
+static void blvl_status_ccc_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
+{
+ ARG_UNUSED(attr);
+
+ bool notif_enabled = (value == BT_GATT_CCC_NOTIFY);
+ bool ind_enabled = (value == BT_GATT_CCC_INDICATE);
+
+ LOG_INF("BAS Notifications %s", notif_enabled ? "enabled" : "disabled");
+ LOG_INF("BAS Indications %s", ind_enabled ? "enabled" : "disabled");
+}
+#endif
+
+static ssize_t read_blvl(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf,
+ uint16_t len, uint16_t offset)
+{
+ uint8_t lvl8 = battery_level;
+
+ return bt_gatt_attr_read(conn, attr, buf, len, offset, &lvl8, sizeof(lvl8));
+}
+
+/* Constant values from the Assigned Numbers specification:
+ * https://www.bluetooth.com/wp-content/uploads/Files/Specification/Assigned_Numbers.pdf?id=89
+ */
+static const struct bt_gatt_cpf level_cpf = {
+ .format = 0x04, /* uint8 */
+ .exponent = 0x0,
+ .unit = 0x27AD, /* Percentage */
+ .name_space = 0x01, /* Bluetooth SIG */
+ .description = 0x0106, /* "main" */
+};
+
+BT_GATT_SERVICE_DEFINE(
+ bas, BT_GATT_PRIMARY_SERVICE(BT_UUID_BAS),
+ BT_GATT_CHARACTERISTIC(BT_UUID_BAS_BATTERY_LEVEL, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY,
+ BT_GATT_PERM_READ, read_blvl, NULL, NULL),
+ BT_GATT_CCC(blvl_ccc_cfg_changed, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),
+ BT_GATT_CPF(&level_cpf),
+#if defined(CONFIG_BT_BAS_BLS)
+ BT_GATT_CHARACTERISTIC(BT_UUID_BAS_BATTERY_LEVEL_STATUS,
+ BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_INDICATE,
+ BT_GATT_PERM_READ, bt_bas_bls_read_blvl_status, NULL, NULL),
+ BT_GATT_CCC(blvl_status_ccc_cfg_changed, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),
+#endif
+);
+
+static int bas_init(void)
+{
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS)) {
+ /* Initialize the Battery Level Status Module */
+ bt_bas_bls_init();
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)) {
+ /* Set the identifier only if BT_BAS_BLS_IDENTIFIER_PRESENT is defined */
+ bt_bas_bls_set_identifier(level_cpf.description);
+ }
+ }
+ return 0;
+}
+
+uint8_t bt_bas_get_battery_level(void)
+{
+ return battery_level;
+}
+
+int bt_bas_set_battery_level(uint8_t level)
+{
+ int rc;
+
+ if (level > 100U) {
+ return -EINVAL;
+ }
+
+ battery_level = level;
+
+ rc = bt_gatt_notify(NULL, &bas.attrs[1], &level, sizeof(level));
+
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)) {
+ bt_bas_bls_set_battery_level(level);
+ }
+
+ return rc == -ENOTCONN ? 0 : rc;
+}
+
+const struct bt_gatt_attr *bt_bas_get_bas_attr(uint16_t index)
+{
+ if (index < bas.attr_count) {
+ return &bas.attrs[index];
+ }
+ return NULL;
+}
+
+SYS_INIT(bas_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/subsys/bluetooth/services/bas/bas_bls.c b/subsys/bluetooth/services/bas/bas_bls.c
new file mode 100644
index 0000000..bcb2fea
--- /dev/null
+++ b/subsys/bluetooth/services/bas/bas_bls.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2024 Demant A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/bluetooth/services/bas.h>
+#include <zephyr/bluetooth/gatt.h>
+#include "bas_internal.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(bas, CONFIG_BT_BAS_LOG_LEVEL);
+
+/* The battery level status of a battery. */
+static struct bt_bas_bls bls;
+
+#define BT_BAS_IDX_BATT_LVL_STATUS_CHAR_VAL 6
+
+/* Notify/Indicate all connections */
+static struct bt_gatt_indicate_params ind_params;
+
+/*
+ * Bitfield structure: Power State
+ *
+ * - Bits 0: Battery Present
+ * - Bits 1–2: Wired External Power Source Connected
+ * - Bits 3–4: Wireless External Power Source Connected
+ * - Bits 5–6: Battery Charge State
+ * - Bits 7–8: Battery Charge Level
+ * - Bits 9–11: Charging Type
+ * - Bits 12–14: Charging Fault Reason
+ * - Bit 15: RFU
+ *
+ * For detailed specification, refer to:
+ * https://bitbucket.org/bluetooth-SIG/public/src/main/gss/
+ * org.bluetooth.characteristic.battery_level_status.yaml
+ */
+
+#define BATTERY_SHIFT 0
+#define WIRED_POWER_SHIFT 1
+#define WIRELESS_POWER_SHIFT 3
+#define BATTERY_CHARGE_STATE_SHIFT 5
+#define BATTERY_CHARGE_LEVEL_SHIFT 7
+#define BATTERY_CHARGE_TYPE_SHIFT 9
+#define CHARGING_FAULT_SHIFT 12
+
+#define BATTERY_MASK (BIT_MASK(1) << BATTERY_SHIFT)
+#define WIRED_POWER_MASK (BIT_MASK(2) << WIRED_POWER_SHIFT)
+#define WIRELESS_POWER_MASK (BIT_MASK(2) << WIRELESS_POWER_SHIFT)
+#define BATTERY_CHARGE_STATE_MASK (BIT_MASK(2) << BATTERY_CHARGE_STATE_SHIFT)
+#define BATTERY_CHARGE_LEVEL_MASK (BIT_MASK(2) << BATTERY_CHARGE_LEVEL_SHIFT)
+#define BATTERY_CHARGE_TYPE_MASK (BIT_MASK(3) << BATTERY_CHARGE_TYPE_SHIFT)
+#define CHARGING_FAULT_MASK (BIT_MASK(3) << CHARGING_FAULT_SHIFT)
+
+/*
+ * Bitfield structure: Additional Status
+ *
+ * - Bits 0–1: Service Required
+ * - Bit 2: Battery Fault
+ * - Bits 3–7: Reserved
+ */
+#define SERVICE_REQUIRED_SHIFT 0
+#define BATTERY_FAULT_SHIFT 2
+
+#define SERVICE_REQUIRED_MASK (BIT_MASK(2) << SERVICE_REQUIRED_SHIFT)
+#define BATTERY_FAULT_MASK (BIT_MASK(1) << BATTERY_FAULT_SHIFT)
+
+void bt_bas_bls_init(void)
+{
+ LOG_DBG("Initialise BAS Battery Level Status Module");
+
+ bls.flags = 0;
+ bls.power_state = 0;
+
+#if defined(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)
+ /* Set identifier flag */
+ bls.flags |= BT_BAS_BLS_FLAG_IDENTIFIER_PRESENT;
+ bls.identifier = 0;
+#endif /* CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)
+ /* Set battery level flag */
+ bls.flags |= BT_BAS_BLS_FLAG_BATTERY_LEVEL_PRESENT;
+ bls.battery_level = bt_bas_get_battery_level();
+#endif /* CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)
+ /* Set additional status flag */
+ bls.flags |= BT_BAS_BLS_FLAG_ADDITIONAL_STATUS_PRESENT;
+ bls.additional_status = 0;
+#endif /* CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT */
+}
+
+static void indicate_cb(struct bt_conn *conn, struct bt_gatt_indicate_params *params, uint8_t err)
+{
+ if (err != 0) {
+ LOG_DBG("Indication failed with error %d\n", err);
+ } else {
+ LOG_DBG("Indication sent successfully\n");
+ }
+}
+
+static void bt_bas_bls_update_battery_level_status(void)
+{
+ int err;
+ const struct bt_gatt_attr *attr = bt_bas_get_bas_attr(BT_BAS_IDX_BATT_LVL_STATUS_CHAR_VAL);
+
+ if (attr) {
+ const struct bt_bas_bls le_battery_level_status = {
+ .flags = bls.flags,
+ .power_state = sys_cpu_to_le16(bls.power_state),
+#if defined(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)
+ .identifier = sys_cpu_to_le16(bls.identifier),
+#endif
+#if defined(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)
+ .battery_level = bls.battery_level,
+#endif
+#if defined(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)
+ .additional_status = bls.additional_status,
+#endif
+ };
+
+ /* Notify/Indicate all connections */
+ ind_params.attr = attr;
+ ind_params.data = &le_battery_level_status;
+ ind_params.len = sizeof(le_battery_level_status);
+ ind_params.func = indicate_cb;
+ err = bt_gatt_indicate(NULL, &ind_params);
+ if (err) {
+ LOG_DBG("Failed to send ntf/ind to all connections (err %d)\n", err);
+ }
+ }
+}
+
+ssize_t bt_bas_bls_read_blvl_status(struct bt_conn *conn, const struct bt_gatt_attr *attr,
+ void *buf, uint16_t len, uint16_t offset)
+{
+ const struct bt_bas_bls le_battery_level_status = {
+ .flags = bls.flags,
+ .power_state = sys_cpu_to_le16(bls.power_state),
+#if defined(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)
+ .identifier = sys_cpu_to_le16(bls.identifier),
+#endif
+#if defined(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)
+ .battery_level = bls.battery_level,
+#endif
+#if defined(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)
+ .additional_status = bls.additional_status,
+#endif
+ };
+
+ return bt_gatt_attr_read(conn, attr, buf, len, offset, &le_battery_level_status,
+ sizeof(le_battery_level_status));
+}
+
+void bt_bas_bls_set_battery_present(enum bt_bas_bls_battery_present present)
+{
+ bls.power_state &= ~BATTERY_MASK;
+ bls.power_state |= (present << BATTERY_SHIFT) & BATTERY_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_wired_external_power_source(enum bt_bas_bls_wired_power_source source)
+{
+ bls.power_state &= ~WIRED_POWER_MASK;
+ bls.power_state |= (source << WIRED_POWER_SHIFT) & WIRED_POWER_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_wireless_external_power_source(enum bt_bas_bls_wireless_power_source source)
+{
+ bls.power_state &= ~WIRELESS_POWER_MASK;
+ bls.power_state |= (source << WIRELESS_POWER_SHIFT) & WIRELESS_POWER_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_battery_charge_state(enum bt_bas_bls_battery_charge_state state)
+{
+ bls.power_state &= ~BATTERY_CHARGE_STATE_MASK;
+ bls.power_state |= (state << BATTERY_CHARGE_STATE_SHIFT) & BATTERY_CHARGE_STATE_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_battery_charge_level(enum bt_bas_bls_battery_charge_level level)
+{
+ bls.power_state &= ~BATTERY_CHARGE_LEVEL_MASK;
+ bls.power_state |= (level << BATTERY_CHARGE_LEVEL_SHIFT) & BATTERY_CHARGE_LEVEL_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_battery_charge_type(enum bt_bas_bls_battery_charge_type type)
+{
+ bls.power_state &= ~BATTERY_CHARGE_TYPE_MASK;
+ bls.power_state |= (type << BATTERY_CHARGE_TYPE_SHIFT) & BATTERY_CHARGE_TYPE_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_charging_fault_reason(enum bt_bas_bls_charging_fault_reason reason)
+{
+ bls.power_state &= ~CHARGING_FAULT_MASK;
+ bls.power_state |= (reason << CHARGING_FAULT_SHIFT) & CHARGING_FAULT_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+#if defined(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)
+void bt_bas_bls_set_battery_level(uint8_t level)
+{
+ bls.battery_level = level;
+ bt_bas_bls_update_battery_level_status();
+}
+#endif /* CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)
+void bt_bas_bls_set_identifier(uint16_t identifier)
+{
+ bls.identifier = sys_cpu_to_le16(identifier);
+ bt_bas_bls_update_battery_level_status();
+}
+#endif /* CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)
+void bt_bas_bls_set_service_required(enum bt_bas_bls_service_required value)
+{
+ bls.additional_status &= ~SERVICE_REQUIRED_MASK;
+ bls.additional_status |= (value << SERVICE_REQUIRED_SHIFT) & SERVICE_REQUIRED_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+
+void bt_bas_bls_set_battery_fault(enum bt_bas_bls_battery_fault value)
+{
+ bls.additional_status &= ~BATTERY_FAULT_MASK;
+ bls.additional_status |= (value << BATTERY_FAULT_SHIFT) & BATTERY_FAULT_MASK;
+ bt_bas_bls_update_battery_level_status();
+}
+#endif /* CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT */
diff --git a/subsys/bluetooth/services/bas/bas_internal.h b/subsys/bluetooth/services/bas/bas_internal.h
new file mode 100644
index 0000000..0dfd33a
--- /dev/null
+++ b/subsys/bluetooth/services/bas/bas_internal.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2024 Demant A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef BT_BAS_INTERNAL_H_
+#define BT_BAS_INTERNAL_H_
+
+#include <sys/types.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/types.h>
+
+/**
+ * @brief Battery level status structure definition.
+ */
+struct bt_bas_bls {
+
+ /** @brief Flags Field
+ *
+ * The values of this field are defined below.
+ *
+ * - bit 0: Identifier Present
+ * - Indicates whether the identifier field is present.
+ * - bit 1: Battery Level Present
+ * - Indicates whether the battery level field is present.
+ * - bit 2: Additional Status Present
+ * - Indicates whether the additional status field is present.
+ * - bit 3–7: RFU (Reserved for Future Use)
+ * - Reserved bits for future use; should be set to zero.
+ */
+ uint8_t flags;
+
+ /** @brief Power State
+ *
+ * The values of this field are defined below.
+ *
+ * - bit 0: Battery Present
+ * - 0 = No
+ * - 1 = Yes
+ * - bit 1–2: Wired External Power Source Connected
+ * - 0 = No
+ * - 1 = Yes
+ * - 2 = Unknown
+ * - 3 = RFU
+ * - bit 3–4: Wireless External Power Source Connected
+ * - 0 = No
+ * - 1 = Yes
+ * - 2 = Unknown
+ * - 3 = RFU
+ * - bit 5–6: Battery Charge State
+ * - 0 = Unknown
+ * - 1 = Charging
+ * - 2 = Discharging: Active
+ * - 3 = Discharging: Inactive
+ * - bit 7–8: Battery Charge Level
+ * - 0 = Unknown
+ * - 1 = Good
+ * - 2 = Low
+ * - 3 = Critical
+ * - bit 9–11: Charging Type
+ * - 0 = Unknown or Not Charging
+ * - 1 = Constant Current
+ * - 2 = Constant Voltage
+ * - 3 = Trickle
+ * - 4 = Float
+ * - 5–7 = RFU
+ * - bit 12–14: Charging Fault Reason
+ * - Bit 12: Battery
+ * - Bit 13: External Power source
+ * - Bit 14: Other
+ * - bit 15: RFU
+ */
+ uint16_t power_state;
+
+#if defined(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)
+ /** Identifier for the battery, range 0x0000 to 0xFFFF.*/
+ uint16_t identifier;
+#endif /* CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)
+ /** Current battery level */
+ uint8_t battery_level;
+#endif /* CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT */
+
+#if defined(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)
+
+ /** @brief Additional Status
+ *
+ * The values of this field are defined below.
+ *
+ * - bit 0–1: Service Required
+ * - 0 = False
+ * - 1 = True
+ * - 2 = Unknown
+ * - 3 = RFU
+ * - bit 2: Battery Fault
+ * - 0 = False or Unknown
+ * - 1 = Yes
+ * - bit 3–7: RFU
+ */
+ uint8_t additional_status;
+
+#endif /* CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT */
+
+} __packed;
+
+/**
+ * @brief Initialize the Battery Level Status Module.
+ *
+ */
+void bt_bas_bls_init(void);
+
+/**
+ * @brief Set the battery level characteristic value.
+ *
+ * @param battery_level The new battery level value in percent (0-100).
+ */
+void bt_bas_bls_set_battery_level(uint8_t battery_level);
+
+/**
+ * @brief Read the Battery Level Status characteristic.
+ *
+ * @param conn Pointer to the Bluetooth connection object representing the client requesting
+ * the characteristic.
+ * @param attr Pointer to the GATT attribute representing the Battery Level Status characteristic.
+ * @param buf Buffer to store the read value.
+ * @param len Length of the buffer.
+ * @param offset Offset within the characteristic value to start reading.
+ *
+ * @return The number of bytes read and sent to the client, or a negative error code on failure.
+ */
+ssize_t bt_bas_bls_read_blvl_status(struct bt_conn *conn, const struct bt_gatt_attr *attr,
+ void *buf, uint16_t len, uint16_t offset);
+
+/**
+ * @brief Retrieve the Bluetooth GATT attribute for the BAS service by index.
+ *
+ * @param index The index of the attribute within the BAS service.
+ *
+ * @return Pointer to the Bluetooth GATT attribute if the index is valid,
+ * otherwise NULL if the index is out of bounds.
+ */
+const struct bt_gatt_attr *bt_bas_get_bas_attr(uint16_t index);
+
+#endif /* BT_BAS_INTERNAL_H_ */
diff --git a/subsys/bluetooth/services/ots/ots_l2cap.c b/subsys/bluetooth/services/ots/ots_l2cap.c
index aa54036..7f0bc02 100644
--- a/subsys/bluetooth/services/ots/ots_l2cap.c
+++ b/subsys/bluetooth/services/ots/ots_l2cap.c
@@ -25,7 +25,7 @@
#if defined(CONFIG_BT_OTS)
LOG_MODULE_DECLARE(bt_ots, CONFIG_BT_OTS_LOG_LEVEL);
#elif defined(CONFIG_BT_OTS_CLIENT)
-LOG_MODULE_REGISTER(bt_ots, CONFIG_BT_OTS_LOG_LEVEL);
+LOG_MODULE_REGISTER(bt_ots, CONFIG_BT_OTS_CLIENT_LOG_LEVEL);
#endif
/* According to BLE specification Assigned Numbers that are used in the
diff --git a/subsys/bluetooth/shell/l2cap.c b/subsys/bluetooth/shell/l2cap.c
index a29329a..a122753 100644
--- a/subsys/bluetooth/shell/l2cap.c
+++ b/subsys/bluetooth/shell/l2cap.c
@@ -88,7 +88,7 @@
struct l2ch *c = L2CH_WORK(work);
struct net_buf *buf;
- while ((buf = net_buf_get(&l2cap_recv_fifo, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&l2cap_recv_fifo, K_NO_WAIT))) {
shell_print(ctx_shell, "Confirming reception");
bt_l2cap_chan_recv_complete(&c->ch.chan, buf);
}
@@ -116,7 +116,7 @@
l2cap_recv_delay_ms);
}
- net_buf_put(&l2cap_recv_fifo, buf);
+ k_fifo_put(&l2cap_recv_fifo, buf);
k_work_schedule(&l2ch->recv_work, K_MSEC(l2cap_recv_delay_ms));
return -EINPROGRESS;
diff --git a/subsys/canbus/isotp/isotp.c b/subsys/canbus/isotp/isotp.c
index dcb3438..289d5a8 100644
--- a/subsys/canbus/isotp/isotp.c
+++ b/subsys/canbus/isotp/isotp.c
@@ -278,7 +278,7 @@
ud_rem_len = net_buf_user_data(rctx->buf);
*ud_rem_len = 0;
LOG_DBG("SM process SF of length %d", rctx->length);
- net_buf_put(&rctx->fifo, rctx->buf);
+ k_fifo_put(&rctx->fifo, rctx->buf);
rctx->state = ISOTP_RX_STATE_RECYCLE;
receive_state_machine(rctx);
break;
@@ -300,7 +300,7 @@
rctx->bs = rctx->opts.bs;
ud_rem_len = net_buf_user_data(rctx->buf);
*ud_rem_len = rctx->length;
- net_buf_put(&rctx->fifo, rctx->buf);
+ k_fifo_put(&rctx->fifo, rctx->buf);
}
rctx->wft = ISOTP_WFT_FIRST;
@@ -538,7 +538,7 @@
if (rctx->length == 0) {
rctx->state = ISOTP_RX_STATE_RECYCLE;
*ud_rem_len = 0;
- net_buf_put(&rctx->fifo, rctx->buf);
+ k_fifo_put(&rctx->fifo, rctx->buf);
return;
}
@@ -546,7 +546,7 @@
LOG_DBG("Block is complete. Allocate new buffer");
rctx->bs = rctx->opts.bs;
*ud_rem_len = rctx->length;
- net_buf_put(&rctx->fifo, rctx->buf);
+ k_fifo_put(&rctx->fifo, rctx->buf);
rctx->state = ISOTP_RX_STATE_TRY_ALLOC;
}
}
@@ -684,7 +684,7 @@
rctx->state = ISOTP_RX_STATE_UNBOUND;
- while ((buf = net_buf_get(&rctx->fifo, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&rctx->fifo, K_NO_WAIT))) {
net_buf_unref(buf);
}
@@ -702,7 +702,7 @@
struct net_buf *buf;
int ret;
- buf = net_buf_get(&rctx->fifo, timeout);
+ buf = k_fifo_get(&rctx->fifo, timeout);
if (!buf) {
ret = rctx->error_nr ? rctx->error_nr : ISOTP_RECV_TIMEOUT;
rctx->error_nr = 0;
@@ -721,7 +721,7 @@
int err;
if (!rctx->recv_buf) {
- rctx->recv_buf = net_buf_get(&rctx->fifo, timeout);
+ rctx->recv_buf = k_fifo_get(&rctx->fifo, timeout);
if (!rctx->recv_buf) {
err = rctx->error_nr ? rctx->error_nr : ISOTP_RECV_TIMEOUT;
rctx->error_nr = 0;
diff --git a/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c b/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
index 2a8525d..06f1e5a 100644
--- a/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
+++ b/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
@@ -57,8 +57,9 @@
/* skip the overflow data. Don't wrap around to keep the most important data
* such as registers and call stack in the beginning of mem window.
*/
- if (mem_wptr >= ADSP_DW_SLOT_SIZE - 4)
+ if (mem_wptr >= ADSP_DW_SLOT_SIZE - 4) {
return;
+ }
if (buf) {
for (data_left = buflen; data_left > 0; data_left--) {
diff --git a/subsys/debug/thread_analyzer.c b/subsys/debug/thread_analyzer.c
index f61f44d..9b161cb 100644
--- a/subsys/debug/thread_analyzer.c
+++ b/subsys/debug/thread_analyzer.c
@@ -164,8 +164,9 @@
{
unsigned int num_cpus = arch_num_cpus();
- for (int i = 0; i < num_cpus; i++)
+ for (int i = 0; i < num_cpus; i++) {
isr_stack(i);
+ }
}
void thread_analyzer_run(thread_analyzer_cb cb, unsigned int cpu)
@@ -173,22 +174,25 @@
struct ta_cb_user_data ud = { .cb = cb, .cpu = cpu };
if (IS_ENABLED(CONFIG_THREAD_ANALYZER_RUN_UNLOCKED)) {
- if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES))
+ if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES)) {
k_thread_foreach_unlocked_filter_by_cpu(cpu, thread_analyze_cb, &ud);
- else
+ } else {
k_thread_foreach_unlocked(thread_analyze_cb, &ud);
+ }
} else {
- if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES))
+ if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES)) {
k_thread_foreach_filter_by_cpu(cpu, thread_analyze_cb, &ud);
- else
+ } else {
k_thread_foreach(thread_analyze_cb, &ud);
+ }
}
if (IS_ENABLED(CONFIG_THREAD_ANALYZER_ISR_STACK_USAGE)) {
- if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES))
+ if (IS_ENABLED(CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES)) {
isr_stack(cpu);
- else
+ } else {
isr_stacks();
+ }
}
}
diff --git a/subsys/fs/fat_fs.c b/subsys/fs/fat_fs.c
index 2a0b7b7..20367a8 100644
--- a/subsys/fs/fat_fs.c
+++ b/subsys/fs/fat_fs.c
@@ -176,10 +176,11 @@
/* Check if 'to' path exists; remove it if it does */
res = f_stat(translate_path(to), &fno);
- if (FR_OK == res) {
+ if (res == FR_OK) {
res = f_unlink(translate_path(to));
- if (FR_OK != res)
+ if (res != FR_OK) {
return translate_error(res);
+ }
}
res = f_rename(translate_path(from), translate_path(to));
diff --git a/subsys/input/CMakeLists.txt b/subsys/input/CMakeLists.txt
index f536787..9c8be14 100644
--- a/subsys/input/CMakeLists.txt
+++ b/subsys/input/CMakeLists.txt
@@ -8,3 +8,4 @@
zephyr_library_sources_ifdef(CONFIG_INPUT_KEYMAP input_keymap.c)
zephyr_library_sources_ifdef(CONFIG_INPUT_LONGPRESS input_longpress.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_DOUBLE_TAP input_double_tap.c)
diff --git a/subsys/input/Kconfig b/subsys/input/Kconfig
index 3678f6d..c9789c36 100644
--- a/subsys/input/Kconfig
+++ b/subsys/input/Kconfig
@@ -95,4 +95,11 @@
help
Enable the input keymap driver.
+config INPUT_DOUBLE_TAP
+ bool "Input double tap"
+ default y
+ depends on DT_HAS_ZEPHYR_INPUT_DOUBLE_TAP_ENABLED
+ help
+ Enable the input double tap driver.
+
endif # INPUT
diff --git a/subsys/input/input_double_tap.c b/subsys/input/input_double_tap.c
new file mode 100644
index 0000000..1928393
--- /dev/null
+++ b/subsys/input/input_double_tap.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2024 Kelly Helmut Lord
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT zephyr_input_double_tap
+
+#include <zephyr/device.h>
+#include <zephyr/input/input.h>
+#include <zephyr/kernel.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(input_double_tap, CONFIG_INPUT_LOG_LEVEL);
+
+struct double_tap_config {
+ const struct device *input_dev;
+ struct double_tap_data_entry *entries;
+ const uint16_t *input_codes;
+ const uint16_t *double_tap_codes;
+ uint32_t double_tap_delay_ms;
+ uint8_t num_codes;
+};
+
+struct double_tap_data_entry {
+ const struct device *dev;
+ struct k_work_delayable work;
+ uint8_t index;
+ bool first_tap;
+};
+
+static void double_tap_deferred(struct k_work *work)
+{
+ struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+ struct double_tap_data_entry *entry =
+ CONTAINER_OF(dwork, struct double_tap_data_entry, work);
+
+ entry->first_tap = false;
+}
+
+static void double_tap_cb(struct input_event *evt, void *user_data)
+{
+ const struct device *dev = user_data;
+ const struct double_tap_config *cfg = dev->config;
+ struct double_tap_data_entry *entry;
+ int i;
+
+ if (evt->type != INPUT_EV_KEY) {
+ return;
+ }
+
+ for (i = 0; i < cfg->num_codes; i++) {
+ if (evt->code == cfg->input_codes[i]) {
+ break;
+ }
+ }
+ if (i == cfg->num_codes) {
+ LOG_DBG("ignored code %d", evt->code);
+ return;
+ }
+
+ entry = &cfg->entries[i];
+
+ if (evt->value) {
+ if (entry->first_tap) {
+ k_work_cancel_delayable(&entry->work);
+ input_report_key(dev, cfg->double_tap_codes[i], 1, true, K_FOREVER);
+ input_report_key(dev, cfg->double_tap_codes[i], 0, true, K_FOREVER);
+ entry->first_tap = false;
+ } else {
+ entry->first_tap = true;
+ k_work_schedule(&entry->work, K_MSEC(cfg->double_tap_delay_ms));
+ }
+ }
+}
+
+static int double_tap_init(const struct device *dev)
+{
+ const struct double_tap_config *cfg = dev->config;
+
+ if (cfg->input_dev && !device_is_ready(cfg->input_dev)) {
+ LOG_ERR("input device not ready");
+ return -ENODEV;
+ }
+
+ for (int i = 0; i < cfg->num_codes; i++) {
+ struct double_tap_data_entry *entry = &cfg->entries[i];
+
+ entry->dev = dev;
+ entry->index = i;
+ entry->first_tap = false;
+ k_work_init_delayable(&entry->work, double_tap_deferred);
+ }
+
+ return 0;
+}
+
+#define INPUT_DOUBLE_TAP_DEFINE(inst) \
+ BUILD_ASSERT(DT_INST_PROP_LEN(inst, input_codes) == \
+ DT_INST_PROP_LEN(inst, double_tap_codes)); \
+ \
+ INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(inst, input)), \
+ double_tap_cb, (void *)DEVICE_DT_INST_GET(inst), \
+ double_tap_cb_##inst); \
+ \
+ static const uint16_t double_tap_input_codes_##inst[] = DT_INST_PROP(inst, input_codes); \
+ \
+ static const uint16_t double_tap_codes_##inst[] = DT_INST_PROP(inst, double_tap_codes); \
+ \
+ static struct double_tap_data_entry \
+ double_tap_data_entries_##inst[DT_INST_PROP_LEN(inst, input_codes)]; \
+ \
+ static const struct double_tap_config double_tap_config_##inst = { \
+ .input_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(inst, input)), \
+ .entries = double_tap_data_entries_##inst, \
+ .input_codes = double_tap_input_codes_##inst, \
+ .double_tap_codes = double_tap_codes_##inst, \
+ .num_codes = DT_INST_PROP_LEN(inst, input_codes), \
+ .double_tap_delay_ms = DT_INST_PROP(inst, double_tap_delay_ms), \
+ }; \
+ \
+ DEVICE_DT_INST_DEFINE(inst, double_tap_init, NULL, NULL, &double_tap_config_##inst, \
+ POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(INPUT_DOUBLE_TAP_DEFINE)
diff --git a/subsys/ipc/ipc_service/lib/ipc_static_vrings.c b/subsys/ipc/ipc_service/lib/ipc_static_vrings.c
index e23c5de..4daac52 100644
--- a/subsys/ipc/ipc_service/lib/ipc_static_vrings.c
+++ b/subsys/ipc/ipc_service/lib/ipc_static_vrings.c
@@ -166,8 +166,9 @@
return -EINVAL;
}
- if (!vr->shm_device.name)
+ if (!vr->shm_device.name) {
vr->shm_device.name = SHM_DEVICE_DEFAULT_NAME;
+ }
vr->shm_device.num_regions = 1;
vr->shm_physmap[0] = vr->shm_addr;
diff --git a/subsys/llext/llext_link.c b/subsys/llext/llext_link.c
index dcbd441..4ee19f5 100644
--- a/subsys/llext/llext_link.c
+++ b/subsys/llext/llext_link.c
@@ -144,8 +144,9 @@
link_addr = llext_find_sym(NULL,
SYM_NAME_OR_SLID(name, sym_tbl.st_value));
- if (!link_addr)
+ if (!link_addr) {
link_addr = llext_find_sym(&ext->sym_tab, name);
+ }
if (!link_addr) {
LOG_WRN("PLT: cannot find idx %u name %s", j, name);
diff --git a/subsys/logging/Kconfig.formatting b/subsys/logging/Kconfig.formatting
index 0723b76..7c1e297 100644
--- a/subsys/logging/Kconfig.formatting
+++ b/subsys/logging/Kconfig.formatting
@@ -145,6 +145,9 @@
config LOG_INFO_COLOR_GREEN
bool "Use green color for info level logs"
+config LOG_DBG_COLOR_BLUE
+ bool "Use blue color for debug level logs"
+
endif # LOG_BACKEND_SHOW_COLOR
config LOG_TAG_MAX_LEN
diff --git a/subsys/logging/backends/log_backend_adsp_mtrace.c b/subsys/logging/backends/log_backend_adsp_mtrace.c
index 1eaeb20..d18ae6e 100644
--- a/subsys/logging/backends/log_backend_adsp_mtrace.c
+++ b/subsys/logging/backends/log_backend_adsp_mtrace.c
@@ -133,8 +133,9 @@
if (mtrace_active && mtrace_hook) {
/* if we are in panic mode, need to flush out asap */
- if (unlikely(mtrace_panic_mode))
+ if (unlikely(mtrace_panic_mode)) {
space_left = 0;
+ }
mtrace_hook(out, space_left);
}
diff --git a/subsys/logging/log_mgmt.c b/subsys/logging/log_mgmt.c
index dbde3d2..85d5e57 100644
--- a/subsys/logging/log_mgmt.c
+++ b/subsys/logging/log_mgmt.c
@@ -243,6 +243,9 @@
const char *log_source_name_get(uint32_t domain_id, uint32_t source_id)
{
if (z_log_is_local_domain(domain_id)) {
+ if (IS_ENABLED(CONFIG_LOG_FMT_SECTION_STRIP)) {
+ return "unknown";
+ }
if (source_id < log_src_cnt_get(domain_id)) {
return TYPE_SECTION_START(log_const)[source_id].name;
} else {
@@ -362,6 +365,10 @@
int log_source_id_get(const char *name)
{
+ if (IS_ENABLED(CONFIG_LOG_FMT_SECTION_STRIP)) {
+ return -1;
+ }
+
for (int i = 0; i < log_src_cnt_get(Z_LOG_LOCAL_DOMAIN_ID); i++) {
const char *sname = log_source_name_get(Z_LOG_LOCAL_DOMAIN_ID, i);
diff --git a/subsys/logging/log_output.c b/subsys/logging/log_output.c
index cd8e898..3add383 100644
--- a/subsys/logging/log_output.c
+++ b/subsys/logging/log_output.c
@@ -19,6 +19,7 @@
#define LOG_COLOR_CODE_RED "\x1B[1;31m"
#define LOG_COLOR_CODE_GREEN "\x1B[1;32m"
#define LOG_COLOR_CODE_YELLOW "\x1B[1;33m"
+#define LOG_COLOR_CODE_BLUE "\x1B[1;34m"
#define HEXDUMP_BYTES_IN_LINE 16
@@ -41,7 +42,7 @@
LOG_COLOR_CODE_RED, /* err */
LOG_COLOR_CODE_YELLOW, /* warn */
IS_ENABLED(CONFIG_LOG_INFO_COLOR_GREEN) ? LOG_COLOR_CODE_GREEN : NULL, /* info */
- NULL /* dbg */
+ IS_ENABLED(CONFIG_LOG_DBG_COLOR_BLUE) ? LOG_COLOR_CODE_BLUE : NULL, /* dbg */
};
static uint32_t freq;
diff --git a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_espi.c b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_espi.c
index 09224ff..b64bd40 100644
--- a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_espi.c
+++ b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_espi.c
@@ -131,8 +131,9 @@
int ret;
/* Ignore in-progress on eSPI since interface is synchronous anyway */
- if (result == EC_HOST_CMD_IN_PROGRESS)
+ if (result == EC_HOST_CMD_IN_PROGRESS) {
return 0;
+ }
hc_espi->state = ESPI_STATE_SENDING;
diff --git a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c
index a5bb9ad..e30de12 100644
--- a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c
+++ b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c
@@ -875,11 +875,6 @@
return ret;
}
- /* If booter doesn't set the host interface type */
- if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
- npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
- }
-
/*
* SHICFG1 (SHI Configuration 1) setting
* [7] - IWRAP = 1: Wrap input buffer to the first address
diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/Kconfig b/subsys/mgmt/mcumgr/grp/img_mgmt/Kconfig
index 80e524f..56030a1 100644
--- a/subsys/mgmt/mcumgr/grp/img_mgmt/Kconfig
+++ b/subsys/mgmt/mcumgr/grp/img_mgmt/Kconfig
@@ -185,6 +185,22 @@
endchoice
+config MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_HOOK
+ bool "Image slot state hook"
+ depends on MCUMGR_MGMT_NOTIFICATION_HOOKS
+ help
+ Allows applications to add additional fields to responses for the image slot state
+ command.
+
+config MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_STATES
+ int
+ prompt "Predicted maximum number of entries per group" if MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_HOOK
+ default 15
+ help
+ This is used for defining CBOR map holding group data.
+ The value does not affect memory allocation, it is used by zcbor
+ to figure out how to encode map depending on its predicted size.
+
module = MCUMGR_GRP_IMG
module-str = mcumgr_grp_img
source "subsys/logging/Kconfig.template.log_config"
diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
index 79f5932..a580d7a 100644
--- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
+++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
@@ -28,16 +28,11 @@
#include <zephyr/mgmt/mcumgr/mgmt/callbacks.h>
#endif
-LOG_MODULE_DECLARE(mcumgr_img_grp, CONFIG_MCUMGR_GRP_IMG_LOG_LEVEL);
+#ifdef CONFIG_MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_HOOK
+#include <mgmt/mcumgr/transport/smp_internal.h>
+#endif
-/* The value here sets how many "characteristics" that describe image is
- * encoded into a map per each image (like bootable flags, and so on).
- * This value is only used for zcbor to predict map size and map encoding
- * and does not affect memory allocation.
- * In case when more "characteristics" are added to image map then
- * zcbor_map_end_encode may fail it this value does not get updated.
- */
-#define MAX_IMG_CHARACTERISTICS 15
+LOG_MODULE_DECLARE(mcumgr_img_grp, CONFIG_MCUMGR_GRP_IMG_LOG_LEVEL);
#ifndef CONFIG_MCUMGR_GRP_IMG_FRUGAL_LIST
#define ZCBOR_ENCODE_FLAG(zse, label, value) \
@@ -414,8 +409,9 @@
}
/* Return zcbor encoding result */
-static bool img_mgmt_state_encode_slot(zcbor_state_t *zse, uint32_t slot, int state_flags)
+static bool img_mgmt_state_encode_slot(struct smp_streamer *ctxt, uint32_t slot, int state_flags)
{
+ zcbor_state_t *zse = ctxt->writer->zs;
uint32_t flags;
char vers_str[IMG_MGMT_VER_MAX_STR_LEN];
uint8_t hash[IMAGE_HASH_LEN]; /* SHA256 hash */
@@ -424,17 +420,30 @@
bool ok;
int rc = img_mgmt_read_info(slot, &ver, hash, &flags);
+#if defined(CONFIG_MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_HOOK)
+ int32_t err_rc;
+ uint16_t err_group;
+ struct img_mgmt_state_slot_encode slot_encode_data = {
+ .ok = &ok,
+ .zse = zse,
+ .slot = slot,
+ .version = vers_str,
+ .hash = hash,
+ .flags = flags,
+ };
+#endif
+
if (rc != 0) {
/* zcbor encoding did not fail */
return true;
}
- ok = zcbor_map_start_encode(zse, MAX_IMG_CHARACTERISTICS) &&
+ ok = zcbor_map_start_encode(zse, CONFIG_MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_STATES) &&
(CONFIG_MCUMGR_GRP_IMG_UPDATABLE_IMAGE_NUMBER == 1 ||
- (zcbor_tstr_put_lit(zse, "image") &&
- zcbor_uint32_put(zse, slot >> 1))) &&
- zcbor_tstr_put_lit(zse, "slot") &&
- zcbor_uint32_put(zse, slot % 2) &&
+ (zcbor_tstr_put_lit(zse, "image") &&
+ zcbor_uint32_put(zse, slot >> 1))) &&
+ zcbor_tstr_put_lit(zse, "slot") &&
+ zcbor_uint32_put(zse, slot % 2) &&
zcbor_tstr_put_lit(zse, "version");
if (ok) {
@@ -446,15 +455,27 @@
}
}
- ok = ok && zcbor_tstr_put_lit(zse, "hash") &&
+ ok = ok && zcbor_tstr_put_lit(zse, "hash") &&
zcbor_bstr_encode(zse, &zhash) &&
ZCBOR_ENCODE_FLAG(zse, "bootable", !(flags & IMAGE_F_NON_BOOTABLE)) &&
ZCBOR_ENCODE_FLAG(zse, "pending", state_flags & REPORT_SLOT_PENDING) &&
ZCBOR_ENCODE_FLAG(zse, "confirmed", state_flags & REPORT_SLOT_CONFIRMED) &&
ZCBOR_ENCODE_FLAG(zse, "active", state_flags & REPORT_SLOT_ACTIVE) &&
- ZCBOR_ENCODE_FLAG(zse, "permanent", state_flags & REPORT_SLOT_PERMANENT) &&
- zcbor_map_end_encode(zse, MAX_IMG_CHARACTERISTICS);
+ ZCBOR_ENCODE_FLAG(zse, "permanent", state_flags & REPORT_SLOT_PERMANENT);
+ if (!ok) {
+ goto failed;
+ }
+
+#if defined(CONFIG_MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_HOOK)
+ /* Send notification to application to optionally append more fields */
+ (void)mgmt_callback_notify(MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE, &slot_encode_data,
+ sizeof(slot_encode_data), &err_rc, &err_group);
+#endif
+
+ ok &= zcbor_map_end_encode(zse, CONFIG_MCUMGR_GRP_IMG_IMAGE_SLOT_STATE_STATES);
+
+failed:
return ok;
}
@@ -498,11 +519,11 @@
/* Need to report slots in proper order */
if (slot_a < slot_o) {
- ok = img_mgmt_state_encode_slot(zse, slot_a, flags_a) &&
- img_mgmt_state_encode_slot(zse, slot_o, flags_o);
+ ok = img_mgmt_state_encode_slot(ctxt, slot_a, flags_a) &&
+ img_mgmt_state_encode_slot(ctxt, slot_o, flags_o);
} else {
- ok = img_mgmt_state_encode_slot(zse, slot_o, flags_o) &&
- img_mgmt_state_encode_slot(zse, slot_a, flags_a);
+ ok = img_mgmt_state_encode_slot(ctxt, slot_o, flags_o) &&
+ img_mgmt_state_encode_slot(ctxt, slot_a, flags_a);
}
}
diff --git a/subsys/mgmt/mcumgr/smp_client/src/client.c b/subsys/mgmt/mcumgr/smp_client/src/client.c
index cca1738..84449ea 100644
--- a/subsys/mgmt/mcumgr/smp_client/src/client.c
+++ b/subsys/mgmt/mcumgr/smp_client/src/client.c
@@ -58,7 +58,7 @@
smp_client = (void *)work;
smpt = smp_client->smpt;
- while ((nb = net_buf_get(&smp_client->tx_fifo, K_NO_WAIT)) != NULL) {
+ while ((nb = k_fifo_get(&smp_client->tx_fifo, K_NO_WAIT)) != NULL) {
smpt->functions.output(nb);
}
}
@@ -111,7 +111,7 @@
entry->nb = net_buf_ref(entry->nb);
entry->retry_cnt--;
entry->timestamp = time_stamp_ref + CONFIG_SMP_CMD_RETRY_TIME;
- net_buf_put(&entry->smp_client->tx_fifo, entry->nb);
+ k_fifo_put(&entry->smp_client->tx_fifo, entry->nb);
smp_tx_req(&entry->smp_client->work);
continue;
}
@@ -319,7 +319,7 @@
/* Increment reference for re-transmission and read smp header */
nb = net_buf_ref(nb);
smp_cmd_add_to_list(cmd_req);
- net_buf_put(&smp_client->tx_fifo, nb);
+ k_fifo_put(&smp_client->tx_fifo, nb);
smp_tx_req(&smp_client->work);
return MGMT_ERR_EOK;
}
diff --git a/subsys/mgmt/mcumgr/transport/src/smp.c b/subsys/mgmt/mcumgr/transport/src/smp.c
index 0f23bd4..f2dc825 100644
--- a/subsys/mgmt/mcumgr/transport/src/smp.c
+++ b/subsys/mgmt/mcumgr/transport/src/smp.c
@@ -136,7 +136,7 @@
smpt = (void *)work;
/* Read and handle received messages */
- while ((nb = net_buf_get(&smpt->fifo, K_NO_WAIT)) != NULL) {
+ while ((nb = k_fifo_get(&smpt->fifo, K_NO_WAIT)) != NULL) {
smp_process_packet(smpt, nb);
}
}
@@ -199,7 +199,7 @@
WEAK void
smp_rx_req(struct smp_transport *smpt, struct net_buf *nb)
{
- net_buf_put(&smpt->fifo, nb);
+ k_fifo_put(&smpt->fifo, nb);
k_work_submit_to_queue(&smp_work_queue, &smpt->work);
}
@@ -230,17 +230,17 @@
*/
k_fifo_init(&temp_fifo);
- while ((nb = net_buf_get(&zst->fifo, K_NO_WAIT)) != NULL) {
+ while ((nb = k_fifo_get(&zst->fifo, K_NO_WAIT)) != NULL) {
if (!zst->functions.query_valid_check(nb, arg)) {
smp_free_buf(nb, zst);
} else {
- net_buf_put(&temp_fifo, nb);
+ k_fifo_put(&temp_fifo, nb);
}
}
/* Re-insert the remaining queued operations into the original FIFO */
- while ((nb = net_buf_get(&temp_fifo, K_NO_WAIT)) != NULL) {
- net_buf_put(&zst->fifo, nb);
+ while ((nb = k_fifo_get(&temp_fifo, K_NO_WAIT)) != NULL) {
+ k_fifo_put(&zst->fifo, nb);
}
/* If at least one entry remains, queue the workqueue for running */
@@ -259,7 +259,7 @@
}
/* Drain the FIFO of all entries without re-adding any */
- while ((nb = net_buf_get(&zst->fifo, K_NO_WAIT)) != NULL) {
+ while ((nb = k_fifo_get(&zst->fifo, K_NO_WAIT)) != NULL) {
smp_free_buf(nb, zst);
}
}
diff --git a/subsys/mgmt/mcumgr/transport/src/smp_shell.c b/subsys/mgmt/mcumgr/transport/src/smp_shell.c
index 669f463..d58f5cb 100644
--- a/subsys/mgmt/mcumgr/transport/src/smp_shell.c
+++ b/subsys/mgmt/mcumgr/transport/src/smp_shell.c
@@ -162,7 +162,7 @@
if (mcumgr_state == SMP_SHELL_MCUMGR_STATE_PAYLOAD &&
byte == '\n') {
if (data->buf) {
- net_buf_put(&data->buf_ready, data->buf);
+ k_fifo_put(&data->buf_ready, data->buf);
data->buf = NULL;
}
atomic_clear_bit(&data->esc_state, ESC_MCUMGR_PKT_1);
@@ -187,7 +187,7 @@
struct net_buf *nb;
while (true) {
- buf = net_buf_get(&data->buf_ready, K_NO_WAIT);
+ buf = k_fifo_get(&data->buf_ready, K_NO_WAIT);
if (!buf) {
break;
}
diff --git a/subsys/net/buf.c b/subsys/net/buf.c
index 8267943..6f0ee42 100644
--- a/subsys/net/buf.c
+++ b/subsys/net/buf.c
@@ -338,6 +338,7 @@
buf->flags = 0U;
buf->frags = NULL;
buf->size = size;
+ memset(buf->user_data, 0, buf->user_data_size);
net_buf_reset(buf);
#if defined(CONFIG_NET_BUF_POOL_USAGE)
diff --git a/subsys/net/conn_mgr/conn_mgr_monitor.c b/subsys/net/conn_mgr/conn_mgr_monitor.c
index 09097f4..765d51f 100644
--- a/subsys/net/conn_mgr/conn_mgr_monitor.c
+++ b/subsys/net/conn_mgr/conn_mgr_monitor.c
@@ -221,7 +221,7 @@
*/
static void conn_mgr_mon_initial_state(struct net_if *iface)
{
- int idx = net_if_get_by_iface(iface) - 1;
+ int idx = conn_mgr_get_index_for_if(iface);
k_mutex_lock(&conn_mgr_mon_lock, K_FOREVER);
@@ -415,4 +415,18 @@
return 0;
}
+uint16_t conn_mgr_if_state(struct net_if *iface)
+{
+ int idx = conn_mgr_get_index_for_if(iface);
+ uint16_t state = CONN_MGR_IF_STATE_INVALID;
+
+ if (idx < CONN_MGR_IFACE_MAX) {
+ k_mutex_lock(&conn_mgr_mon_lock, K_FOREVER);
+ state = iface_states[idx];
+ k_mutex_unlock(&conn_mgr_mon_lock);
+ }
+
+ return state;
+}
+
SYS_INIT(conn_mgr_mon_init, APPLICATION, CONFIG_NET_CONNECTION_MANAGER_MONITOR_PRIORITY);
diff --git a/subsys/net/conn_mgr/conn_mgr_private.h b/subsys/net/conn_mgr/conn_mgr_private.h
index 5aa08ed..364eb26 100644
--- a/subsys/net/conn_mgr/conn_mgr_private.h
+++ b/subsys/net/conn_mgr/conn_mgr_private.h
@@ -32,6 +32,9 @@
#define CONN_MGR_IF_READY_IPV4 BIT(14)
#define CONN_MGR_IF_READY_IPV6 BIT(15)
+/* Special value indicating invalid state. */
+#define CONN_MGR_IF_STATE_INVALID 0xFFFF
+
/* NET_MGMT event masks */
#define CONN_MGR_IFACE_EVENTS_MASK (NET_EVENT_IF_DOWN | \
NET_EVENT_IF_UP)
@@ -60,4 +63,7 @@
/* Cause conn_mgr_connectivity to Initialize all connectivity implementation bindings */
void conn_mgr_conn_init(void);
+/* Internal helper function to allow the shell net cm command to safely read conn_mgr state. */
+uint16_t conn_mgr_if_state(struct net_if *iface);
+
#endif /* __CONN_MGR_PRV_H__ */
diff --git a/subsys/net/ip/net_core.c b/subsys/net/ip/net_core.c
index f2e564c..8ab2fb9 100644
--- a/subsys/net/ip/net_core.c
+++ b/subsys/net/ip/net_core.c
@@ -16,6 +16,7 @@
#include <zephyr/init.h>
#include <zephyr/kernel.h>
+#include <zephyr/tracing/tracing.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <string.h>
@@ -379,13 +380,18 @@
int net_send_data(struct net_pkt *pkt)
{
int status;
+ int ret;
+
+ SYS_PORT_TRACING_FUNC_ENTER(net, send_data, pkt);
if (!pkt || !pkt->frags) {
- return -ENODATA;
+ ret = -ENODATA;
+ goto err;
}
if (!net_pkt_iface(pkt)) {
- return -EINVAL;
+ ret = -EINVAL;
+ goto err;
}
net_pkt_trim_buffer(pkt);
@@ -399,7 +405,8 @@
* we just silently drop the packet by returning 0.
*/
if (status == -ENOMSG) {
- return 0;
+ ret = 0;
+ goto err;
}
return status;
@@ -409,11 +416,13 @@
*/
NET_DBG("Loopback pkt %p back to us", pkt);
processing_data(pkt, true);
- return 0;
+ ret = 0;
+ goto err;
}
if (net_if_send_data(net_pkt_iface(pkt), pkt) == NET_DROP) {
- return -EIO;
+ ret = -EIO;
+ goto err;
}
if (IS_ENABLED(CONFIG_NET_STATISTICS)) {
@@ -427,7 +436,12 @@
}
}
- return 0;
+ ret = 0;
+
+err:
+ SYS_PORT_TRACING_FUNC_EXIT(net, send_data, pkt, ret);
+
+ return ret;
}
static void net_rx(struct net_if *iface, struct net_pkt *pkt)
@@ -489,16 +503,23 @@
/* Called by driver when a packet has been received */
int net_recv_data(struct net_if *iface, struct net_pkt *pkt)
{
+ int ret;
+
+ SYS_PORT_TRACING_FUNC_ENTER(net, recv_data, iface, pkt);
+
if (!pkt || !iface) {
- return -EINVAL;
+ ret = -EINVAL;
+ goto err;
}
if (net_pkt_is_empty(pkt)) {
- return -ENODATA;
+ ret = -ENODATA;
+ goto err;
}
if (!net_if_flag_is_set(iface, NET_IF_UP)) {
- return -ENETDOWN;
+ ret = -ENETDOWN;
+ goto err;
}
net_pkt_set_overwrite(pkt, true);
@@ -520,7 +541,12 @@
net_queue_rx(iface, pkt);
}
- return 0;
+ ret = 0;
+
+err:
+ SYS_PORT_TRACING_FUNC_EXIT(net, recv_data, iface, pkt, ret);
+
+ return ret;
}
static inline void l3_init(void)
diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c
index 98d7131..52bee86 100644
--- a/subsys/net/ip/net_if.c
+++ b/subsys/net/ip/net_if.c
@@ -247,7 +247,8 @@
context = net_pkt_context(pkt);
if (net_if_flag_is_set(iface, NET_IF_LOWER_UP)) {
- if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS)) {
+ if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
pkt_priority = net_pkt_priority(pkt);
if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS_DETAIL)) {
@@ -262,7 +263,8 @@
status = net_if_l2(iface)->send(iface, pkt);
net_if_tx_unlock(iface);
- if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS)) {
+ if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
uint32_t end_tick = k_cycle_get_32();
net_pkt_set_tx_stats_tick(pkt, end_tick);
@@ -272,6 +274,8 @@
create_time,
end_tick);
+ SYS_PORT_TRACING_FUNC(net, tx_time, pkt, end_tick);
+
if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS_DETAIL)) {
update_txtime_stats_detail(
pkt,
diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c
index d0ee064..9faf830 100644
--- a/subsys/net/ip/net_pkt.c
+++ b/subsys/net/ip/net_pkt.c
@@ -1274,7 +1274,8 @@
}
if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) ||
- IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS)) {
+ IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
create_time = k_cycle_get_32();
} else {
ARG_UNUSED(create_time);
@@ -1313,7 +1314,8 @@
}
if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) ||
- IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS)) {
+ IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
net_pkt_set_create_time(pkt, create_time);
}
@@ -1833,8 +1835,9 @@
{
int32_t ll_addr_offset;
- if (!lladdr->addr)
+ if (!lladdr->addr) {
return;
+ }
ll_addr_offset = net_pkt_find_offset(pkt, lladdr->addr);
diff --git a/subsys/net/l2/ethernet/Kconfig b/subsys/net/l2/ethernet/Kconfig
index 1b61c25..3df528e 100644
--- a/subsys/net/l2/ethernet/Kconfig
+++ b/subsys/net/l2/ethernet/Kconfig
@@ -115,7 +115,7 @@
config NET_ETHERNET_BRIDGE_SHELL
bool "Ethernet Bridging management shell"
depends on NET_ETHERNET_BRIDGE
- select SHELL
+ select NET_SHELL
help
Enables shell utility to manage bridge configuration interactively.
diff --git a/subsys/net/l2/ethernet/bridge_shell.c b/subsys/net/l2/ethernet/bridge_shell.c
index b2ed720..7ac0bd6 100644
--- a/subsys/net/l2/ethernet/bridge_shell.c
+++ b/subsys/net/l2/ethernet/bridge_shell.c
@@ -221,7 +221,9 @@
SHELL_SUBCMD_SET_END
);
-SHELL_CMD_REGISTER(bridge, &bridge_commands, "Ethernet Bridge commands", NULL);
+SHELL_SUBCMD_ADD((net), bridge, &bridge_commands,
+ "Ethernet bridge commands.",
+ cmd_bridge_show, 1, 1);
#if defined(CONFIG_NET_ETHERNET_BRIDGE_DEFAULT)
static ETH_BRIDGE_INIT(shell_default_bridge);
diff --git a/subsys/net/l2/openthread/openthread_utils.c b/subsys/net/l2/openthread/openthread_utils.c
index f3eba81..2e78da6 100644
--- a/subsys/net/l2/openthread/openthread_utils.c
+++ b/subsys/net/l2/openthread/openthread_utils.c
@@ -32,7 +32,7 @@
const otMeshLocalPrefix *ml_prefix =
otThreadGetMeshLocalPrefix(context->instance);
- return (memcmp(address, ml_prefix->m8, sizeof(ml_prefix)) == 0);
+ return (memcmp(address, ml_prefix->m8, sizeof(ml_prefix->m8)) == 0);
}
int pkt_list_add(struct openthread_context *context, struct net_pkt *pkt)
@@ -156,9 +156,8 @@
context, address->mAddress.mFields.m8);
/* Mark address as deprecated if it is not preferred. */
- if (!address->mPreferred) {
- if_addr->addr_state = NET_ADDR_DEPRECATED;
- }
+ if_addr->addr_state =
+ address->mPreferred ? NET_ADDR_PREFERRED : NET_ADDR_DEPRECATED;
}
}
diff --git a/subsys/net/l2/ppp/fsm.c b/subsys/net/l2/ppp/fsm.c
index 1f64de1..3dd2802 100644
--- a/subsys/net/l2/ppp/fsm.c
+++ b/subsys/net/l2/ppp/fsm.c
@@ -226,10 +226,10 @@
case PPP_OPENED:
case PPP_REQUEST_SENT:
if (reason) {
- int len = strlen(reason);
+ int limit_len = sizeof(fsm->terminate_reason) - 1;
- len = MIN(sizeof(fsm->terminate_reason) - 1, len);
- strncpy(fsm->terminate_reason, reason, len);
+ strncpy(fsm->terminate_reason, reason, limit_len);
+ fsm->terminate_reason[limit_len] = '\0';
}
terminate(fsm, PPP_CLOSING);
diff --git a/subsys/net/l2/wifi/CMakeLists.txt b/subsys/net/l2/wifi/CMakeLists.txt
index c834c5b..6548e81 100644
--- a/subsys/net/l2/wifi/CMakeLists.txt
+++ b/subsys/net/l2/wifi/CMakeLists.txt
@@ -8,6 +8,9 @@
zephyr_library_compile_definitions_ifdef(
CONFIG_NEWLIB_LIBC __LINUX_ERRNO_EXTENSIONS__
)
+zephyr_library_include_directories_ifdef(
+ CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE test_certs
+ )
zephyr_library_sources_ifdef(CONFIG_NET_L2_WIFI_MGMT wifi_mgmt.c)
zephyr_library_sources_ifdef(CONFIG_NET_L2_WIFI_SHELL wifi_shell.c)
@@ -19,3 +22,28 @@
if (CONFIG_WIFI_NM)
zephyr_iterable_section(NAME wifi_nm_instance GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN)
endif()
+
+# Wi-Fi Enterprise test certificates handling
+set(gen_inc_dir ${ZEPHYR_BINARY_DIR}/misc/generated)
+set(gen_dir ${gen_inc_dir}/wifi_enterprise_test_certs)
+
+# convert .pem files to array data at build time
+zephyr_include_directories(${gen_inc_dir})
+
+generate_inc_file_for_target(
+ app
+ ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client.pem
+ ${gen_dir}/client.pem.inc
+ )
+
+generate_inc_file_for_target(
+ app
+ ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client-key.pem
+ ${gen_dir}/client-key.pem.inc
+ )
+
+generate_inc_file_for_target(
+ app
+ ${ZEPHYR_BASE}/samples/net/wifi/test_certs/ca.pem
+ ${gen_dir}/ca.pem.inc
+ )
diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c
index 5c995fb..9ba9a3b 100644
--- a/subsys/net/l2/wifi/wifi_mgmt.c
+++ b/subsys/net/l2/wifi/wifi_mgmt.c
@@ -31,11 +31,15 @@
return "WPA2-PSK";
case WIFI_SECURITY_TYPE_PSK_SHA256:
return "WPA2-PSK-SHA256";
- case WIFI_SECURITY_TYPE_SAE:
- return "WPA3-SAE";
+ case WIFI_SECURITY_TYPE_SAE_HNP:
+ return "WPA3-SAE-HNP";
+ case WIFI_SECURITY_TYPE_SAE_H2E:
+ return "WPA3-SAE-H2E";
+ case WIFI_SECURITY_TYPE_SAE_AUTO:
+ return "WPA3-SAE-AUTO";
case WIFI_SECURITY_TYPE_WAPI:
return "WAPI";
- case WIFI_SECURITY_TYPE_EAP:
+ case WIFI_SECURITY_TYPE_EAP_TLS:
return "EAP";
case WIFI_SECURITY_TYPE_UNKNOWN:
default:
@@ -280,7 +284,9 @@
params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) &&
((params->psk_length < 8) || (params->psk_length > 64) ||
(params->psk_length == 0U) || !params->psk)) ||
- ((params->security == WIFI_SECURITY_TYPE_SAE) &&
+ ((params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
+ params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
+ params->security == WIFI_SECURITY_TYPE_SAE_AUTO) &&
((params->psk_length == 0U) || !params->psk) &&
((params->sae_password_length == 0U) || !params->sae_password)) ||
((params->channel != WIFI_CHANNEL_ANY) &&
@@ -769,6 +775,44 @@
NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_VERSION, wifi_get_version);
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+static int wifi_btm_query(uint32_t mgmt_request, struct net_if *iface, void *data, size_t len)
+{
+ const struct device *dev = net_if_get_device(iface);
+ const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_api(iface);
+ uint8_t query_reason = *((uint8_t *)data);
+
+ if (wifi_mgmt_api == NULL || wifi_mgmt_api->btm_query == NULL) {
+ return -ENOTSUP;
+ }
+
+ if (query_reason >= WIFI_BTM_QUERY_REASON_UNSPECIFIED &&
+ query_reason <= WIFI_BTM_QUERY_REASON_LEAVING_ESS) {
+ return wifi_mgmt_api->btm_query(dev, query_reason);
+ }
+
+ return -EINVAL;
+}
+
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_BTM_QUERY, wifi_btm_query);
+#endif
+
+static int wifi_get_connection_params(uint32_t mgmt_request, struct net_if *iface,
+ void *data, size_t len)
+{
+ const struct device *dev = net_if_get_device(iface);
+ const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_api(iface);
+ struct wifi_connect_req_params *conn_params = data;
+
+ if (wifi_mgmt_api == NULL || wifi_mgmt_api->get_conn_params == NULL) {
+ return -ENOTSUP;
+ }
+
+ return wifi_mgmt_api->get_conn_params(dev, conn_params);
+}
+
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_CONN_PARAMS, wifi_get_connection_params);
+
static int wifi_set_rts_threshold(uint32_t mgmt_request, struct net_if *iface,
void *data, size_t len)
{
@@ -805,6 +849,39 @@
NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_DPP, wifi_dpp);
+static int wifi_pmksa_flush(uint32_t mgmt_request, struct net_if *iface,
+ void *data, size_t len)
+{
+ const struct device *dev = net_if_get_device(iface);
+ const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_api(iface);
+
+ if (wifi_mgmt_api == NULL || wifi_mgmt_api->pmksa_flush == NULL) {
+ return -ENOTSUP;
+ }
+
+ return wifi_mgmt_api->pmksa_flush(dev);
+}
+
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_PMKSA_FLUSH, wifi_pmksa_flush);
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+static int wifi_set_enterprise_creds(uint32_t mgmt_request, struct net_if *iface,
+ void *data, size_t len)
+{
+ const struct device *dev = net_if_get_device(iface);
+ const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_api(iface);
+ struct wifi_enterprise_creds_params *params = data;
+
+ if (wifi_mgmt_api == NULL || wifi_mgmt_api->enterprise_creds == NULL) {
+ return -ENOTSUP;
+ }
+
+ return wifi_mgmt_api->enterprise_creds(dev, params);
+}
+
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_ENTERPRISE_CREDS, wifi_set_enterprise_creds);
+#endif
+
#ifdef CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS
void wifi_mgmt_raise_raw_scan_result_event(struct net_if *iface,
struct wifi_raw_scan_result *raw_scan_result)
diff --git a/subsys/net/l2/wifi/wifi_nm.c b/subsys/net/l2/wifi/wifi_nm.c
index 842127a..a5fce02 100644
--- a/subsys/net/l2/wifi/wifi_nm.c
+++ b/subsys/net/l2/wifi/wifi_nm.c
@@ -66,12 +66,12 @@
bool wifi_nm_iface_is_sta(struct net_if *iface)
{
- return wifi_nm_get_type_iface(iface) & (1 << WIFI_TYPE_STA);
+ return wifi_nm_get_type_iface(iface) & BIT(WIFI_TYPE_STA);
}
bool wifi_nm_iface_is_sap(struct net_if *iface)
{
- return wifi_nm_get_type_iface(iface) & (1 << WIFI_TYPE_SAP);
+ return wifi_nm_get_type_iface(iface) & BIT(WIFI_TYPE_SAP);
}
int wifi_nm_register_mgd_iface(struct wifi_nm_instance *nm, struct net_if *iface)
@@ -117,7 +117,7 @@
for (int i = 0; i < CONFIG_WIFI_NM_MAX_MANAGED_INTERFACES; i++) {
if (!nm->mgd_ifaces[i].iface) {
nm->mgd_ifaces[i].iface = iface;
- nm->mgd_ifaces[i].type = (1 << type);
+ nm->mgd_ifaces[i].type = BIT(type);
k_mutex_unlock(&wifi_nm_lock);
return 0;
}
diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c
index 5fc0d1b..ac6e2c3 100644
--- a/subsys/net/l2/wifi/wifi_shell.c
+++ b/subsys/net/l2/wifi/wifi_shell.c
@@ -29,6 +29,19 @@
#include <zephyr/sys/slist.h>
#include "net_shell_private.h"
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+static const char ca_cert_test[] = {
+ #include <wifi_enterprise_test_certs/ca.pem.inc>
+};
+
+static const char client_cert_test[] = {
+ #include <wifi_enterprise_test_certs/client.pem.inc>
+};
+
+static const char client_key_test[] = {
+ #include <wifi_enterprise_test_certs/client-key.pem.inc>
+};
+#endif
#define WIFI_SHELL_MODULE "wifi"
@@ -75,6 +88,28 @@
};
static struct wifi_ap_sta_node sta_list[CONFIG_WIFI_SHELL_MAX_AP_STA];
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+static int cmd_wifi_set_enterprise_creds(const struct shell *sh, struct net_if *iface)
+{
+ struct wifi_enterprise_creds_params params = {0};
+
+ params.ca_cert = (uint8_t *)ca_cert_test;
+ params.ca_cert_len = ARRAY_SIZE(ca_cert_test);
+ params.client_cert = (uint8_t *)client_cert_test;
+ params.client_cert_len = ARRAY_SIZE(client_cert_test);
+ params.client_key = (uint8_t *)client_key_test;
+ params.client_key_len = ARRAY_SIZE(client_key_test);
+
+ if (net_mgmt(NET_REQUEST_WIFI_ENTERPRISE_CREDS, iface, ¶ms, sizeof(params))) {
+ PR_WARNING("Set enterprise credentials failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif
+
static bool parse_number(const struct shell *sh, long *param, char *str,
char *pname, long min, long max)
{
@@ -464,6 +499,8 @@
{"band", required_argument, 0, 'b'},
{"channel", required_argument, 0, 'c'},
{"timeout", required_argument, 0, 't'},
+ {"anon-id", required_argument, 0, 'a'},
+ {"key-passwd", required_argument, 0, 'K'},
{"help", no_argument, 0, 'h'},
{0, 0, 0, 0}};
char *endptr;
@@ -486,7 +523,7 @@
params->security = WIFI_SECURITY_TYPE_NONE;
params->mfp = WIFI_MFP_OPTIONAL;
- while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:m:t:h",
+ while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:m:t:a:K:h",
long_options, &opt_index)) != -1) {
state = getopt_state_get();
switch (opt) {
@@ -583,6 +620,24 @@
}
}
break;
+ case 'a':
+ params->anon_id = optarg;
+ params->aid_length = strlen(params->anon_id);
+ if (params->aid_length > WIFI_ENT_IDENTITY_MAX_LEN) {
+ PR_WARNING("anon_id too long (max %d characters)\n",
+ WIFI_ENT_IDENTITY_MAX_LEN);
+ return -EINVAL;
+ }
+ break;
+ case 'K':
+ params->key_passwd = optarg;
+ params->key_passwd_length = strlen(params->key_passwd);
+ if (params->key_passwd_length > WIFI_ENT_PSWD_MAX_LEN) {
+ PR_WARNING("key_passwd too long (max %d characters)\n",
+ WIFI_ENT_PSWD_MAX_LEN);
+ return -EINVAL;
+ }
+ break;
case 'h':
return -ENOEXEC;
default:
@@ -619,6 +674,13 @@
return -ENOEXEC;
}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+ /* Load the enterprise credentials if needed */
+ if (cnx_params.security == WIFI_SECURITY_TYPE_EAP_TLS) {
+ cmd_wifi_set_enterprise_creds(sh, iface);
+ }
+#endif
+
context.connecting = true;
ret = net_mgmt(NET_REQUEST_WIFI_CONNECT, iface,
&cnx_params, sizeof(struct wifi_connect_req_params));
@@ -1570,6 +1632,30 @@
return 0;
}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+static int cmd_wifi_btm_query(const struct shell *sh, size_t argc, char *argv[])
+{
+ struct net_if *iface = net_if_get_first_wifi();
+ uint8_t query_reason = 0;
+
+ context.sh = sh;
+
+ if (!parse_number(sh, (long *)&query_reason, argv[1], NULL,
+ WIFI_BTM_QUERY_REASON_UNSPECIFIED, WIFI_BTM_QUERY_REASON_LEAVING_ESS)) {
+ return -EINVAL;
+ }
+
+ if (net_mgmt(NET_REQUEST_WIFI_BTM_QUERY, iface, &query_reason, sizeof(query_reason))) {
+ PR_WARNING("Setting BTM query Reason failed..Reason :%d\n", query_reason);
+ return -ENOEXEC;
+ }
+
+ PR("Query reason %d\n", query_reason);
+
+ return 0;
+}
+#endif
+
static int cmd_wifi_ps_wakeup_mode(const struct shell *sh, size_t argc, char *argv[])
{
struct net_if *iface = net_if_get_first_wifi();
@@ -2373,6 +2459,20 @@
return 0;
}
+static int cmd_wifi_pmksa_flush(const struct shell *sh, size_t argc, char *argv[])
+{
+ struct net_if *iface = net_if_get_wifi_sta();
+
+ context.sh = sh;
+
+ if (net_mgmt(NET_REQUEST_WIFI_PMKSA_FLUSH, iface, NULL, 0)) {
+ PR_WARNING("Flush PMKSA cache entries failed\n");
+ return -ENOEXEC;
+ }
+
+ return 0;
+}
+
SHELL_STATIC_SUBCMD_SET_CREATE(wifi_cmd_ap,
SHELL_CMD_ARG(disable, NULL,
"Disable Access Point mode.\n",
@@ -2383,7 +2483,8 @@
"-c --channel=<channel number>\n"
"-p --passphrase=<PSK> (valid only for secure SSIDs)\n"
"-k --key-mgmt=<Security type> (valid only for secure SSIDs)\n"
- "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n"
+ "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP-TLS, 6:WEP\n"
+ "7: WPA-PSK\n"
"-w --ieee-80211w=<MFP> (optional: needs security type to be specified)\n"
"0:Disable, 1:Optional, 2:Required\n"
"-b --band=<band> (2 -2.6GHz, 5 - 5Ghz, 6 - 6GHz)\n"
@@ -2500,12 +2601,14 @@
"[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n"
"[-p, --psk]: Passphrase (valid only for secure SSIDs)\n"
"[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n"
- "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP,"
- " 7: WPA-PSK, 8: WPA-Auto-Personal\n"
+ "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE-HNP, 4:SAE-H2E, 5:SAE-AUTO, 6:WAPI,"
+ " 7:EAP-TLS, 8:WEP, 9: WPA-PSK, 10: WPA-Auto-Personal\n"
"[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n"
": 0:Disable, 1:Optional, 2:Required.\n"
"[-m, --bssid]: MAC address of the AP (BSSID).\n"
"[-t, --timeout]: Timeout for the connection attempt (in seconds).\n"
+ "[-a, --anon-id]: Anonymous identity for enterprise mode.\n"
+ "[-K, --key-passwd]: Private key passwd for enterprise mode.\n"
"[-h, --help]: Print out the help for the connect command.\n",
cmd_wifi_connect,
2, 7),
@@ -2594,6 +2697,13 @@
"wifi -i1 -c5.\n",
cmd_wifi_channel,
2, 4),
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+ SHELL_CMD_ARG(11v_btm_query,
+ NULL,
+ "<query_reason: The reason code for a BSS transition management query>.\n",
+ cmd_wifi_btm_query,
+ 2, 0),
+#endif
SHELL_CMD_ARG(ps_timeout,
NULL,
"<val> - PS inactivity timer(in ms).\n",
@@ -2615,6 +2725,9 @@
cmd_wifi_set_rts_threshold,
2, 0),
SHELL_CMD(dpp, &wifi_cmd_dpp, "DPP actions\n", NULL),
+ SHELL_CMD_ARG(pmksa_flush, NULL,
+ "Flush PMKSA cache entries.\n",
+ cmd_wifi_pmksa_flush, 1, 0),
SHELL_SUBCMD_SET_END
);
diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c
index 092916f..5ac55f8 100644
--- a/subsys/net/lib/capture/capture.c
+++ b/subsys/net/lib/capture/capture.c
@@ -23,6 +23,7 @@
#include "ipv4.h"
#include "ipv6.h"
#include "udp_internal.h"
+#include "net_stats.h"
#define PKT_ALLOC_TIME K_MSEC(50)
#define DEFAULT_PORT 4242
@@ -554,7 +555,7 @@
if (captured == NULL) {
NET_DBG("Captured pkt %s", "dropped");
- /* TODO: update capture data statistics */
+ net_stats_update_processing_error(ctx->tunnel_iface);
ret = -ENOMEM;
goto out;
}
diff --git a/subsys/net/lib/config/init_clock_sntp.c b/subsys/net/lib/config/init_clock_sntp.c
index 49f1ad8..9dbf519 100644
--- a/subsys/net/lib/config/init_clock_sntp.c
+++ b/subsys/net/lib/config/init_clock_sntp.c
@@ -8,6 +8,7 @@
LOG_MODULE_DECLARE(net_config, CONFIG_NET_CONFIG_LOG_LEVEL);
#include <errno.h>
+#include <zephyr/net/net_if.h>
#include <zephyr/net/sntp.h>
#include <zephyr/posix/time.h>
diff --git a/subsys/net/lib/dhcpv4/Kconfig b/subsys/net/lib/dhcpv4/Kconfig
index 80252a2..c457a2b 100644
--- a/subsys/net/lib/dhcpv4/Kconfig
+++ b/subsys/net/lib/dhcpv4/Kconfig
@@ -162,4 +162,15 @@
will send a NAK, informing the client it should proceed with a full
procedure.
+config NET_DHCPV4_SERVER_OPTION_DNS_ADDRESS
+ string "DNS Server address"
+ default DNS_SERVER1 if DNS_SERVER_IP_ADDRESSES
+ default ""
+ help
+ This configuration option specifies the DNS server address that the DHCPv4
+ server should provide to clients when they request an IP address. The
+ DHCPv4 server adds this DNS server address in the DHCP offer and
+ acknowledgment messages sent to the clients, allowing them to use the
+ specified DNS server for name resolution.
+
endif # NET_DHCPV4_SERVER
diff --git a/subsys/net/lib/dhcpv4/dhcpv4_server.c b/subsys/net/lib/dhcpv4/dhcpv4_server.c
index 9124d64..58b0253 100644
--- a/subsys/net/lib/dhcpv4/dhcpv4_server.c
+++ b/subsys/net/lib/dhcpv4/dhcpv4_server.c
@@ -30,6 +30,7 @@
#define DHCPV4_OPTIONS_SERVER_ID_SIZE 6
#define DHCPV4_OPTIONS_SUBNET_MASK_SIZE 6
#define DHCPV4_OPTIONS_ROUTER_SIZE 6
+#define DHCPV4_OPTIONS_DNS_SERVER_SIZE 6
#define DHCPV4_OPTIONS_CLIENT_ID_MIN_SIZE 2
#define ADDRESS_RESERVED_TIMEOUT K_SECONDS(30)
@@ -398,6 +399,29 @@
return buf + DHCPV4_OPTIONS_ROUTER_SIZE;
}
+static uint8_t *dhcpv4_encode_dns_server_option(uint8_t *buf, size_t *buflen)
+{
+ struct in_addr dns_address;
+
+ if (buf == NULL || *buflen < DHCPV4_OPTIONS_DNS_SERVER_SIZE) {
+ return NULL;
+ }
+
+ if (net_addr_pton(AF_INET, CONFIG_NET_DHCPV4_SERVER_OPTION_DNS_ADDRESS, &dns_address)) {
+ LOG_ERR("Invalid DNS server address: %s",
+ CONFIG_NET_DHCPV4_SERVER_OPTION_DNS_ADDRESS);
+ return NULL;
+ }
+
+ buf[0] = DHCPV4_OPTIONS_DNS_SERVER;
+ buf[1] = sizeof(struct in_addr);
+ memcpy(&buf[2], dns_address.s4_addr, sizeof(struct in_addr));
+
+ *buflen -= DHCPV4_OPTIONS_DNS_SERVER_SIZE;
+
+ return buf + DHCPV4_OPTIONS_DNS_SERVER_SIZE;
+}
+
static uint8_t *dhcpv4_encode_end_option(uint8_t *buf, size_t *buflen)
{
if (buf == NULL || *buflen < 1) {
@@ -498,6 +522,13 @@
goto out;
}
break;
+
+ case DHCPV4_OPTIONS_DNS_SERVER:
+ buf = dhcpv4_encode_dns_server_option(buf, buflen);
+ if (buf == NULL) {
+ goto out;
+ }
+ break;
/* Others - just ignore. */
default:
break;
diff --git a/subsys/net/lib/lwm2m/Kconfig b/subsys/net/lib/lwm2m/Kconfig
index 7bbdfda..32fdae4 100644
--- a/subsys/net/lib/lwm2m/Kconfig
+++ b/subsys/net/lib/lwm2m/Kconfig
@@ -18,7 +18,7 @@
menu "Protocol versions"
-choice
+choice LWM2M_VERSION
prompt "LwM2M protocol version"
default LWM2M_VERSION_1_0
help
@@ -716,12 +716,4 @@
source "subsys/net/lib/lwm2m/Kconfig.ucifi"
-menu "Deprecated flags"
-config LWM2M_RD_CLIENT_SUPPORT
- bool "DEPRECATED: client bootstrap/registration state machine"
- select DEPRECATED
- help
- Deprecated flag. RD state machine is always part of engine. It cannot be disabled.
-endmenu # "Deprecated flags"
-
endif # LWM2M
diff --git a/subsys/net/lib/lwm2m/lwm2m_message_handling.c b/subsys/net/lib/lwm2m/lwm2m_message_handling.c
index 83a8142..77a007f 100644
--- a/subsys/net/lib/lwm2m/lwm2m_message_handling.c
+++ b/subsys/net/lib/lwm2m/lwm2m_message_handling.c
@@ -3379,7 +3379,7 @@
}
}
-#if defined(CONFIG_LWM2M_SERVER_OBJECT_VERSION_1_1)
+#if defined(CONFIG_LWM2M_VERSION_1_1)
static int do_send_reply_cb(const struct coap_packet *response, struct coap_reply *reply,
const struct sockaddr *from)
{
@@ -3455,7 +3455,7 @@
int lwm2m_send_cb(struct lwm2m_ctx *ctx, const struct lwm2m_obj_path path_list[],
uint8_t path_list_size, lwm2m_send_cb_t reply_cb)
{
-#if defined(CONFIG_LWM2M_SERVER_OBJECT_VERSION_1_1)
+#if defined(CONFIG_LWM2M_VERSION_1_1)
struct lwm2m_message *msg;
int ret;
uint16_t content_format;
@@ -3594,7 +3594,7 @@
lwm2m_reset_message(msg, true);
return ret;
#else
- LOG_WRN("LwM2M send is only supported for CONFIG_LWM2M_SERVER_OBJECT_VERSION_1_1");
+ LOG_WRN("LwM2M send is only supported for CONFIG_LWM2M_VERSION_1_1");
return -ENOTSUP;
#endif
}
diff --git a/subsys/net/lib/lwm2m/lwm2m_registry.c b/subsys/net/lib/lwm2m/lwm2m_registry.c
index ce59e48..1c22d11 100644
--- a/subsys/net/lib/lwm2m/lwm2m_registry.c
+++ b/subsys/net/lib/lwm2m/lwm2m_registry.c
@@ -754,11 +754,6 @@
return lwm2m_engine_set(path, &value, 4);
}
-int lwm2m_set_u64(const struct lwm2m_obj_path *path, uint64_t value)
-{
- return lwm2m_engine_set(path, &value, 8);
-}
-
int lwm2m_set_s8(const struct lwm2m_obj_path *path, int8_t value)
{
return lwm2m_engine_set(path, &value, 1);
@@ -1030,11 +1025,6 @@
return lwm2m_engine_get(path, value, 4);
}
-int lwm2m_get_u64(const struct lwm2m_obj_path *path, uint64_t *value)
-{
- return lwm2m_engine_get(path, value, 8);
-}
-
int lwm2m_get_s8(const struct lwm2m_obj_path *path, int8_t *value)
{
return lwm2m_engine_get(path, value, 1);
diff --git a/subsys/net/lib/shell/CMakeLists.txt b/subsys/net/lib/shell/CMakeLists.txt
index ea310b5..7505d70 100644
--- a/subsys/net/lib/shell/CMakeLists.txt
+++ b/subsys/net/lib/shell/CMakeLists.txt
@@ -16,6 +16,7 @@
zephyr_library_sources(gptp.c)
zephyr_library_sources(http.c)
zephyr_library_sources(iface.c)
+zephyr_library_sources(cm.c)
zephyr_library_sources(ipv4.c)
zephyr_library_sources(ipv6.c)
zephyr_library_sources(mem.c)
diff --git a/subsys/net/lib/shell/cm.c b/subsys/net/lib/shell/cm.c
new file mode 100644
index 0000000..9c2225f
--- /dev/null
+++ b/subsys/net/lib/shell/cm.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(net_shell);
+
+#include <zephyr/net/net_if.h>
+#include <strings.h>
+#include <ctype.h>
+
+#include "net_shell_private.h"
+
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+
+#include "conn_mgr_private.h"
+#include <zephyr/net/conn_mgr_connectivity.h>
+#include <zephyr/net/conn_mgr_monitor.h>
+
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+
+
+#define CM_IF_NAME_NONE "unnamed"
+
+#if defined(CONFIG_NET_INTERFACE_NAME)
+#define CM_MAX_IF_NAME MAX(sizeof(CM_IF_NAME_NONE), CONFIG_NET_INTERFACE_NAME_LEN)
+#else
+#define CM_MAX_IF_NAME sizeof(CM_IF_NAME_NONE)
+#endif
+
+#define CM_MAX_IF_INFO (CM_MAX_IF_NAME + 40)
+
+
+/* Parsing and printing helpers. None of these are used unless CONFIG_NET_CONNECTION_MANAGER
+ * is enabled.
+ */
+
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+
+enum cm_type {
+ CM_TARG_IFACE,
+ CM_TARG_NONE,
+ CM_TARG_ALL,
+ CM_TARG_INVALID,
+};
+struct cm_target {
+ enum cm_type type;
+ struct net_if *iface;
+};
+enum cm_gs_type {
+ CM_GS_GET,
+ CM_GS_SET
+};
+struct cm_flag_string {
+ const char *const name;
+ enum conn_mgr_if_flag flag;
+};
+static const struct cm_flag_string flag_strings[] = {
+ {"PERSISTENT", CONN_MGR_IF_PERSISTENT},
+ {"NO_AUTO_CONNECT", CONN_MGR_IF_NO_AUTO_CONNECT},
+ {"NO_AUTO_DOWN", CONN_MGR_IF_NO_AUTO_DOWN},
+};
+
+static const char *flag_name(enum conn_mgr_if_flag flag)
+{
+ /* Scan over predefined flag strings, and return the name
+ * of the first one of matching flag.
+ */
+ for (int i = 0; i < ARRAY_SIZE(flag_strings); i++) {
+ if (flag_strings[i].flag == flag) {
+ return flag_strings[i].name;
+ }
+ }
+
+ /* No matches found, it's invalid. */
+ return "INVALID";
+}
+
+static void cm_print_flags(const struct shell *sh)
+{
+ PR("Valid flag keywords are:\n");
+ for (int i = 0; i < ARRAY_SIZE(flag_strings); i++) {
+ PR("\t%s,\n", flag_strings[i].name);
+ }
+}
+
+/* Verify that a provided string consists only of the characters 0-9*/
+static bool check_numeric(char *str)
+{
+ int i;
+ int len = strlen(str);
+
+ for (i = 0; i < len; i++) {
+ if (!isdigit((int)str[i])) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static void cm_target_help(const struct shell *sh)
+{
+ PR("Valid target specifiers are 'ifi [index]', 'if [name]', or '[index]'.\n");
+}
+
+/* These parsers treat argv as a tokenstream, and increment *argidx by the number of
+ * tokens parsed.
+ */
+static int parse_ifi_target(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ struct cm_target *target)
+{
+ char *arg;
+ int err = 0;
+ unsigned long iface_index;
+
+ /* At least one remaining argument is required to specify a target index */
+ if (*argidx >= argc) {
+ PR_ERROR("Please specify the target iface index.\n");
+ goto error;
+ }
+
+ arg = argv[*argidx];
+
+ iface_index = shell_strtoul(arg, 10, &err);
+
+ if (err) {
+ PR_ERROR("\"%s\" is not a valid iface index.\n", arg);
+ goto error;
+ }
+
+ target->iface = net_if_get_by_index(iface_index);
+
+ if (target->iface == NULL) {
+ PR_ERROR("iface with index \"%s\" does not exist.\n", arg);
+ goto error;
+ }
+
+ *argidx += 1;
+ target->type = CM_TARG_IFACE;
+ return 0;
+
+error:
+ target->type = CM_TARG_INVALID;
+ return -EINVAL;
+}
+
+static int parse_if_target(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ struct cm_target *target)
+{
+#if defined(CONFIG_NET_INTERFACE_NAME)
+ char *arg;
+ /* At least one remaining argument is required to specify a target name */
+ if (*argidx >= argc) {
+ PR_ERROR("Please specify the target iface name.\n");
+ goto error;
+ }
+
+ arg = argv[*argidx];
+
+ target->iface = net_if_get_by_index(net_if_get_by_name(arg));
+
+ if (target->iface == NULL) {
+ PR_ERROR("iface with name \"%s\" does not exist.\n", arg);
+ goto error;
+ }
+
+ *argidx += 1;
+ target->type = CM_TARG_IFACE;
+ return 0;
+#else
+ PR_ERROR("iface name lookup requires CONFIG_NET_INTERFACE_NAME.\n");
+ goto error;
+#endif
+
+error:
+ target->type = CM_TARG_INVALID;
+ return -EINVAL;
+}
+
+/* parse `if [iface name]`, `ifi [iface index]`, `[iface index]`, or `all` */
+static int parse_target(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ struct cm_target *target)
+{
+ char *arg;
+
+ /* At least one argument is required to specify a target */
+ if (*argidx >= argc) {
+ target->type = CM_TARG_NONE;
+ return 0;
+ }
+
+ arg = argv[*argidx];
+
+ /* At least one argument provided. Is it "all" or "none"? */
+ if (strcasecmp(arg, "all") == 0) {
+ *argidx += 1;
+ target->type = CM_TARG_ALL;
+ return 0;
+ }
+
+ if (strcasecmp(arg, "none") == 0) {
+ *argidx += 1;
+ target->type = CM_TARG_NONE;
+ return 0;
+ }
+
+ /* If not, interpret as an iface index if it is also numeric */
+ if (check_numeric(arg)) {
+ return parse_ifi_target(sh, argc, argv, argidx, target);
+ }
+
+ /* Otherwise, arg must be a target type specifier */
+ if (strcasecmp(arg, "if") == 0) {
+ *argidx += 1;
+ return parse_if_target(sh, argc, argv, argidx, target);
+ }
+
+ if (strcasecmp(arg, "ifi") == 0) {
+ *argidx += 1;
+ return parse_ifi_target(sh, argc, argv, argidx, target);
+ }
+
+ PR_ERROR("%s is not a valid target type or target specifier.\n", arg);
+ cm_target_help(sh);
+ target->type = CM_TARG_INVALID;
+
+ return -EINVAL;
+}
+
+static int parse_getset(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ enum cm_gs_type *result)
+{
+ char *arg;
+
+ /* At least one argument is required to specify get or set */
+ if (*argidx >= argc) {
+ goto error;
+ }
+
+ arg = argv[*argidx];
+
+ if (strcasecmp(arg, "get") == 0) {
+ *argidx += 1;
+ *result = CM_GS_GET;
+ return 0;
+ }
+
+ if (strcasecmp(arg, "set") == 0) {
+ *argidx += 1;
+ *result = CM_GS_SET;
+ return 0;
+ }
+
+error:
+ PR_ERROR("Please specify get or set\n");
+ return -EINVAL;
+}
+
+static int parse_flag(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ enum conn_mgr_if_flag *result)
+{
+ char *arg;
+
+ /* At least one argument is required to specify get or set */
+ if (*argidx >= argc) {
+ PR_ERROR("Please specify a flag.\n");
+ cm_print_flags(sh);
+
+ return -EINVAL;
+ }
+
+ arg = argv[*argidx];
+
+ for (int i = 0; i < ARRAY_SIZE(flag_strings); i++) {
+ if (strcasecmp(arg, flag_strings[i].name) == 0) {
+ *argidx += 1;
+ *result = flag_strings[i].flag;
+ return 0;
+ }
+ }
+
+ PR_ERROR("%s is not a valid flag.\n", arg);
+ return -EINVAL;
+}
+
+static int parse_bool(const struct shell *sh, size_t argc, char *argv[], int *argidx, bool *result)
+{
+ char *arg;
+
+ /* At least one argument is required to specify a boolean */
+ if (*argidx >= argc) {
+ goto error;
+ }
+
+ arg = argv[*argidx];
+
+ if (strcasecmp(arg, "yes") == 0 ||
+ strcasecmp(arg, "y") == 0 ||
+ strcasecmp(arg, "1") == 0 ||
+ strcasecmp(arg, "true") == 0) {
+ *argidx += 1;
+ *result = true;
+ return 0;
+ }
+
+ if (strcasecmp(arg, "no") == 0 ||
+ strcasecmp(arg, "n") == 0 ||
+ strcasecmp(arg, "0") == 0 ||
+ strcasecmp(arg, "false") == 0) {
+ *argidx += 1;
+ *result = false;
+ return 0;
+ }
+
+error:
+ PR_ERROR("Please specify true or false.\n");
+ return -EINVAL;
+}
+
+static int parse_timeout(const struct shell *sh, size_t argc, char *argv[], int *argidx,
+ int *result)
+{
+ char *arg;
+ int err = 0;
+ unsigned long value;
+
+ /* At least one argument is required to specify a timeout */
+ if (*argidx >= argc) {
+ PR_ERROR("Please specify a timeout (in seconds).\n");
+ return -EINVAL;
+ }
+
+ arg = argv[*argidx];
+
+ /* Check for special keyword "none" */
+ if (strcasecmp(arg, "none") == 0) {
+ *argidx += 1;
+ *result = CONN_MGR_IF_NO_TIMEOUT;
+ return 0;
+ }
+
+ /* Otherwise, try to parse integer timeout (seconds). */
+ if (!check_numeric(arg)) {
+ PR_ERROR("%s is not a valid timeout.\n", arg);
+ return -EINVAL;
+ }
+
+ value = shell_strtoul(arg, 10, &err);
+ if (err) {
+ PR_ERROR("%s is not a valid timeout.\n", arg);
+ return -EINVAL;
+ }
+
+ *argidx += 1;
+ *result = value;
+ return 0;
+}
+
+static void cm_get_iface_info(struct net_if *iface, char *buf, size_t len)
+{
+#if defined(CONFIG_NET_INTERFACE_NAME)
+ char name[CM_MAX_IF_NAME];
+
+ if (net_if_get_name(iface, name, sizeof(name))) {
+ strcpy(name, CM_IF_NAME_NONE);
+ }
+
+ snprintf(buf, len, "%d (%p - %s - %s)", net_if_get_by_iface(iface), iface, name,
+ iface2str(iface, NULL));
+#else
+ snprintf(buf, len, "%d (%p - %s)", net_if_get_by_iface(iface), iface,
+ iface2str(iface, NULL));
+#endif
+}
+
+/* bulk iface actions */
+static void cm_iface_status(struct net_if *iface, void *user_data)
+{
+ const struct shell *sh = user_data;
+ uint16_t state = conn_mgr_if_state(iface);
+ bool ignored;
+ bool bound;
+ bool admin_up;
+ bool oper_up;
+ bool has_ipv4;
+ bool has_ipv6;
+ bool connected;
+ char iface_info[CM_MAX_IF_INFO];
+ char *ip_state;
+
+ cm_get_iface_info(iface, iface_info, sizeof(iface_info));
+
+ if (state == CONN_MGR_IF_STATE_INVALID) {
+ PR("iface %s not tracked.\n", iface_info);
+ } else {
+ ignored = state & CONN_MGR_IF_IGNORED;
+ bound = conn_mgr_if_is_bound(iface);
+ admin_up = net_if_is_admin_up(iface);
+ oper_up = state & CONN_MGR_IF_UP;
+ has_ipv4 = state & CONN_MGR_IF_IPV4_SET;
+ has_ipv6 = state & CONN_MGR_IF_IPV6_SET;
+ connected = state & CONN_MGR_IF_READY;
+
+ if (has_ipv4 && has_ipv6) {
+ ip_state = "IPv4 + IPv6";
+ } else if (has_ipv4) {
+ ip_state = "IPv4";
+ } else if (has_ipv6) {
+ ip_state = "IPv6";
+ } else {
+ ip_state = "no IP";
+ }
+
+ PR("iface %s status: %s, %s, %s, %s, %s, %s.\n", iface_info,
+ ignored ? "ignored" : "watched",
+ bound ? "bound" : "not bound",
+ admin_up ? "admin-up" : "admin-down",
+ oper_up ? "oper-up" : "oper-down",
+ ip_state,
+ connected ? "connected" : "not connected");
+ }
+}
+
+static void cm_iface_ignore(struct net_if *iface, void *user_data)
+{
+ const struct shell *sh = user_data;
+ char iface_info[CM_MAX_IF_INFO];
+
+ cm_get_iface_info(iface, iface_info, sizeof(iface_info));
+
+ conn_mgr_ignore_iface(iface);
+ PR("iface %s now ignored.\n", iface_info);
+}
+
+static void cm_iface_watch(struct net_if *iface, void *user_data)
+{
+ const struct shell *sh = user_data;
+ char iface_info[CM_MAX_IF_INFO];
+
+ cm_get_iface_info(iface, iface_info, sizeof(iface_info));
+
+ conn_mgr_watch_iface(iface);
+ PR("iface %s now watched.\n", iface_info);
+}
+
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+
+static void not_available(const struct shell *sh)
+{
+ PR_INFO("This command is not available unless CONFIG_NET_CONNECTION_MANAGER is enabled.\n");
+}
+
+#endif /* !defined(CONFIG_NET_CONNECTION_MANAGER) */
+
+
+/* Commands */
+
+static int cmd_net_cm_status(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE || target.type == CM_TARG_ALL) {
+ net_if_foreach(cm_iface_status, (void *)sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_iface_status(target.iface, (void *)sh);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ PR_INFO("conn_mgr is not enabled. Enable by setting CONFIG_NET_CONNECTION_MANAGER=y.\n");
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_ignore(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Ignoring all ifaces.\n");
+ net_if_foreach(cm_iface_ignore, (void *)sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_iface_ignore(target.iface, (void *)sh);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_watch(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Watching all ifaces.\n");
+ net_if_foreach(cm_iface_watch, (void *)sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_iface_watch(target.iface, (void *)sh);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_connect(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Instructing all non-ignored ifaces to connect.\n");
+ conn_mgr_all_if_connect(true);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+
+ if (!conn_mgr_if_is_bound(target.iface)) {
+ PR_ERROR("iface %s is not bound to a connectivity implementation, cannot "
+ "connect.\n", iface_info);
+ return 0;
+ }
+
+ PR("Instructing iface %s to connect.\n", iface_info);
+ conn_mgr_if_connect(target.iface);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_disconnect(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Instructing all non-ignored ifaces to disconnect.\n");
+ conn_mgr_all_if_disconnect(true);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+
+ if (!conn_mgr_if_is_bound(target.iface)) {
+ PR_ERROR("iface %s is not bound to a connectivity implementation, cannot "
+ "disconnect.\n", iface_info);
+ return 0;
+ }
+
+ PR("Instructing iface %s to disonnect.\n", iface_info);
+ conn_mgr_if_disconnect(target.iface);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_up(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Taking all non-ignored ifaces admin-up.\n");
+ conn_mgr_all_if_up(true);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+ PR("Taking iface %s admin-up.\n", iface_info);
+ PR_WARNING("This command duplicates 'net iface up' if [target] != all.\n");
+
+ net_if_up(target.iface);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_down(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ /* no need to print anything, parse_target already explained the issue */
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR("Taking all non-ignored ifaces admin-down.\n");
+ conn_mgr_all_if_down(true);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_IFACE) {
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+ PR("Taking iface %s admin-down.\n", iface_info);
+ PR_WARNING("This command duplicates 'net iface down' if [target] != all.\n");
+
+ net_if_down(target.iface);
+ return 0;
+ }
+
+ PR_ERROR("Invalid target selected.\n");
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_flag(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ enum cm_gs_type getset = CM_GS_GET;
+ enum conn_mgr_if_flag flag = CONN_MGR_IF_PERSISTENT;
+ bool value = false;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR_ERROR("Cannot get/set flags for all ifaces.\n");
+ return 0;
+ }
+
+ if (target.type != CM_TARG_IFACE) {
+ PR_ERROR("Invalid target selected.\n");
+ return 0;
+ }
+
+ if (parse_getset(sh, argc, argv, &argidx, &getset)) {
+ return 0;
+ }
+
+ if (parse_flag(sh, argc, argv, &argidx, &flag)) {
+ return 0;
+ }
+
+ /* If we are in set mode, expect the value to be provided. */
+ if (getset == CM_GS_SET && parse_bool(sh, argc, argv, &argidx, &value)) {
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+
+ if (!conn_mgr_if_is_bound(target.iface)) {
+ PR_ERROR("iface %s is not bound to a connectivity implementation, cannot "
+ "get/set connectivity flag.\n", iface_info);
+ return 0;
+ }
+
+ if (getset == CM_GS_SET) {
+ (void)conn_mgr_if_set_flag(target.iface, flag, value);
+ PR("Set the connectivity %s flag to %s on iface %s.\n", flag_name(flag),
+ value?"y":"n", iface_info);
+ } else {
+ value = conn_mgr_if_get_flag(target.iface, flag);
+ PR("The current value of the %s connectivity flag on iface %s is %s.\n",
+ flag_name(flag), iface_info, value?"y":"n");
+ }
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+static int cmd_net_cm_timeout(const struct shell *sh, size_t argc, char *argv[])
+{
+#if defined(CONFIG_NET_CONNECTION_MANAGER)
+ int argidx = 1;
+ enum cm_gs_type getset = CM_GS_GET;
+ int value = CONN_MGR_IF_NO_TIMEOUT;
+ struct cm_target target = {
+ .type = CM_TARG_INVALID
+ };
+ char iface_info[CM_MAX_IF_INFO];
+
+ if (parse_target(sh, argc, argv, &argidx, &target)) {
+ return 0;
+ }
+
+ if (target.type == CM_TARG_NONE) {
+ PR_ERROR("Please specify a target.\n");
+ cm_target_help(sh);
+ return 0;
+ }
+
+ if (target.type == CM_TARG_ALL) {
+ PR_ERROR("Cannot get/set timeout for all ifaces.\n");
+ return 0;
+ }
+
+ if (target.type != CM_TARG_IFACE) {
+ PR_ERROR("Invalid target selected.\n");
+ return 0;
+ }
+
+ if (parse_getset(sh, argc, argv, &argidx, &getset)) {
+ return 0;
+ }
+
+ /* If we are in set mode, expect the value to be provided. */
+ if (getset == CM_GS_SET && parse_timeout(sh, argc, argv, &argidx, &value)) {
+ return 0;
+ }
+
+ if (argidx != argc) {
+ PR_ERROR("Too many args.\n");
+ return 0;
+ }
+
+ cm_get_iface_info(target.iface, iface_info, sizeof(iface_info));
+
+ if (!conn_mgr_if_is_bound(target.iface)) {
+ PR_ERROR("iface %s is not bound to a connectivity implementation, cannot "
+ "get/set connectivity timeout.\n", iface_info);
+ return 0;
+ }
+
+ if (getset == CM_GS_SET) {
+ (void)conn_mgr_if_set_timeout(target.iface, value);
+ PR("Set the connectivity timeout for iface %s to %d%s.\n", iface_info, value,
+ value == 0 ? " (no timeout)":" seconds");
+ } else {
+ value = conn_mgr_if_get_timeout(target.iface);
+ PR("The connectivity timeout for iface %s is %d%s.\n", iface_info, value,
+ value == 0 ? " (no timeout)":" seconds");
+ }
+#else /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ not_available(sh);
+#endif /* defined(CONFIG_NET_CONNECTION_MANAGER) */
+ return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(net_cmd_cm,
+ SHELL_CMD_ARG(status, NULL,
+ "'net cm status [target]' shows the connectivity status of the specified "
+ "iface(s).",
+ cmd_net_cm_status, 1, 2),
+ SHELL_CMD_ARG(ignore, NULL,
+ "'net cm ignore [target]' ignores the specified iface(s).",
+ cmd_net_cm_ignore, 1, 2),
+ SHELL_CMD_ARG(watch, NULL,
+ "'net cm watch [target]' watches the specified iface(s).",
+ cmd_net_cm_watch, 1, 2),
+ SHELL_CMD_ARG(connect, NULL,
+ "'net cm connect [target]' connects the specified iface(s).",
+ cmd_net_cm_connect, 1, 2),
+ SHELL_CMD_ARG(disconnect, NULL,
+ "'net cm disconnect [target]' disconnects the specified iface(s).",
+ cmd_net_cm_disconnect, 1, 2),
+ SHELL_CMD_ARG(up, NULL,
+ "'net cm up [target]' takes the specified iface(s) admin-up.",
+ cmd_net_cm_up, 1, 2),
+ SHELL_CMD_ARG(down, NULL,
+ "'net cm down [target]' takes the specified iface(s) admin-down.",
+ cmd_net_cm_down, 1, 2),
+ SHELL_CMD_ARG(flag, NULL,
+ "'net cm flag [target] [get/set] [flag] [value]' gets or sets a flag "
+ "for the specified iface.",
+ cmd_net_cm_flag, 1, 5),
+ SHELL_CMD_ARG(timeout, NULL,
+ "'net cm timeout [target] [get/set] [value]' gets or sets the timeout "
+ "for the specified iface.",
+ cmd_net_cm_timeout, 1, 4),
+ SHELL_SUBCMD_SET_END
+);
+
+SHELL_SUBCMD_ADD((net), cm, &net_cmd_cm, "Control conn_mgr.", NULL, 1, 0);
diff --git a/subsys/net/lib/sockets/sockets.c b/subsys/net/lib/sockets/sockets.c
index 2532893..dc74a22 100644
--- a/subsys/net/lib/sockets/sockets.c
+++ b/subsys/net/lib/sockets/sockets.c
@@ -1265,6 +1265,8 @@
net_pkt_create_time(pkt),
end_tick);
+ SYS_PORT_TRACING_FUNC(net, rx_time, pkt, end_tick);
+
if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS_DETAIL)) {
uint32_t val, prev = net_pkt_create_time(pkt);
int i;
@@ -1596,7 +1598,8 @@
}
}
- if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) &&
+ if ((IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) &&
!(flags & ZSOCK_MSG_PEEK)) {
net_socket_update_tc_rx_time(pkt, k_cycle_get_32());
}
@@ -1669,7 +1672,8 @@
sock_set_eof(ctx);
}
- if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS)) {
+ if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
net_socket_update_tc_rx_time(pkt, k_cycle_get_32());
}
diff --git a/subsys/net/lib/sockets/sockets_packet.c b/subsys/net/lib/sockets/sockets_packet.c
index 6a793fc..3fe9258 100644
--- a/subsys/net/lib/sockets/sockets_packet.c
+++ b/subsys/net/lib/sockets/sockets_packet.c
@@ -345,7 +345,8 @@
zpacket_set_source_addr(ctx, pkt, src_addr, addrlen);
}
- if (IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) &&
+ if ((IS_ENABLED(CONFIG_NET_PKT_RXTIME_STATS) ||
+ IS_ENABLED(CONFIG_TRACING_NET_CORE)) &&
!(flags & ZSOCK_MSG_PEEK)) {
net_socket_update_tc_rx_time(pkt, k_cycle_get_32());
}
diff --git a/subsys/net/lib/websocket/websocket.c b/subsys/net/lib/websocket/websocket.c
index 1a7eb90..c2dcba9 100644
--- a/subsys/net/lib/websocket/websocket.c
+++ b/subsys/net/lib/websocket/websocket.c
@@ -645,7 +645,8 @@
k_timepoint_t req_end_timepoint = sys_timepoint_calc(req_timeout);
return sendmsg_all(ctx->real_sock, &msg,
- K_TIMEOUT_EQ(tout, K_NO_WAIT) ? MSG_DONTWAIT : 0, req_end_timepoint);
+ K_TIMEOUT_EQ(tout, K_NO_WAIT) ? ZSOCK_MSG_DONTWAIT : 0,
+ req_end_timepoint);
#endif /* CONFIG_NET_TEST */
}
@@ -995,7 +996,7 @@
ret = wait_rx(ctx->real_sock, timeout_to_ms(&tout));
if (ret == 0) {
ret = zsock_recv(ctx->real_sock, ctx->recv_buf.buf,
- ctx->recv_buf.size, MSG_DONTWAIT);
+ ctx->recv_buf.size, ZSOCK_MSG_DONTWAIT);
if (ret < 0) {
ret = -errno;
}
diff --git a/subsys/net/lib/zperf/zperf_udp_receiver.c b/subsys/net/lib/zperf/zperf_udp_receiver.c
index 9991cf5..0f7e1e4 100644
--- a/subsys/net/lib/zperf/zperf_udp_receiver.c
+++ b/subsys/net/lib/zperf/zperf_udp_receiver.c
@@ -236,8 +236,9 @@
if (if_name[0]) {
iface = net_if_get_by_index(net_if_get_by_name(if_name));
- if (iface == NULL)
+ if (iface == NULL) {
iface = net_if_get_default();
+ }
} else {
iface = net_if_get_default();
}
@@ -253,8 +254,9 @@
if (if_name[0]) {
iface = net_if_get_by_index(net_if_get_by_name(if_name));
- if (iface == NULL)
+ if (iface == NULL) {
iface = net_if_get_default();
+ }
} else {
iface = net_if_get_default();
}
@@ -275,15 +277,17 @@
if (IS_ENABLED(CONFIG_NET_IPV4) && addr.sa_family == AF_INET) {
struct sockaddr_in *addr4 = (struct sockaddr_in *)&addr;
- if (net_ipv4_is_addr_mcast(&addr4->sin_addr))
+ if (net_ipv4_is_addr_mcast(&addr4->sin_addr)) {
net_ipv4_igmp_leave(iface, &addr4->sin_addr);
+ }
}
if (IS_ENABLED(CONFIG_NET_IPV6) && addr.sa_family == AF_INET6) {
struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)&addr;
- if (net_ipv6_is_addr_mcast(&addr6->sin6_addr))
+ if (net_ipv6_is_addr_mcast(&addr6->sin6_addr)) {
net_ipv6_mld_leave(iface, &addr6->sin6_addr);
+ }
}
}
diff --git a/subsys/profiling/CMakeLists.txt b/subsys/profiling/CMakeLists.txt
new file mode 100644
index 0000000..223d049
--- /dev/null
+++ b/subsys/profiling/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_PROFILING_PERF perf)
diff --git a/subsys/profiling/Kconfig b/subsys/profiling/Kconfig
new file mode 100644
index 0000000..6239b97
--- /dev/null
+++ b/subsys/profiling/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig PROFILING
+ bool "Profiling tools"
+ help
+ Enable profiling tools, such as perf
+
+if PROFILING
+
+source "subsys/profiling/perf/Kconfig"
+
+endif
diff --git a/subsys/profiling/perf/CMakeLists.txt b/subsys/profiling/perf/CMakeLists.txt
new file mode 100644
index 0000000..f8b261a
--- /dev/null
+++ b/subsys/profiling/perf/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(backends)
+
+zephyr_library()
+
+zephyr_library_sources(
+ perf.c
+)
diff --git a/subsys/profiling/perf/Kconfig b/subsys/profiling/perf/Kconfig
new file mode 100644
index 0000000..31ddf7d
--- /dev/null
+++ b/subsys/profiling/perf/Kconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2023 KNS Group LLC (YADRO)
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config PROFILING_PERF
+ bool "Perf support"
+ depends on !SMP
+ depends on SHELL
+ depends on PROFILING_PERF_HAS_BACKEND
+ help
+ Enable perf shell command.
+
+if PROFILING_PERF
+
+config PROFILING_PERF_BUFFER_SIZE
+ int "Perf buffer size"
+ default 2048
+ help
+ Size of buffer used by perf to save stack trace samples.
+
+endif
+
+rsource "backends/Kconfig"
diff --git a/subsys/profiling/perf/backends/CMakeLists.txt b/subsys/profiling/perf/backends/CMakeLists.txt
new file mode 100644
index 0000000..a335273
--- /dev/null
+++ b/subsys/profiling/perf/backends/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Meta Platforms
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_PROFILING_PERF_BACKEND_RISCV
+ perf_riscv.c
+)
+
+zephyr_sources_ifdef(CONFIG_PROFILING_PERF_BACKEND_X86
+ perf_x86.c
+)
+
+zephyr_sources_ifdef(CONFIG_PROFILING_PERF_BACKEND_X86_64
+ perf_x86_64.c
+)
diff --git a/subsys/profiling/perf/backends/Kconfig b/subsys/profiling/perf/backends/Kconfig
new file mode 100644
index 0000000..6ea7018
--- /dev/null
+++ b/subsys/profiling/perf/backends/Kconfig
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 Meta Platforms
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config PROFILING_PERF_HAS_BACKEND
+ bool
+ help
+ Selected when there's an implementation for
+ `arch_perf_current_stack_trace()`
+
+config PROFILING_PERF_BACKEND_RISCV
+ bool
+ default y
+ depends on RISCV
+ depends on THREAD_STACK_INFO
+ depends on FRAME_POINTER
+ select PROFILING_PERF_HAS_BACKEND
+
+config PROFILING_PERF_BACKEND_X86
+ bool
+ default y
+ depends on X86 && !X86_64
+ depends on THREAD_STACK_INFO
+ depends on FRAME_POINTER
+ select PROFILING_PERF_HAS_BACKEND
+
+config PROFILING_PERF_BACKEND_X86_64
+ bool
+ default y
+ depends on X86_64
+ depends on THREAD_STACK_INFO
+ depends on FRAME_POINTER
+ select PROFILING_PERF_HAS_BACKEND
diff --git a/subsys/profiling/perf/backends/perf_riscv.c b/subsys/profiling/perf/backends/perf_riscv.c
new file mode 100644
index 0000000..3ef0994
--- /dev/null
+++ b/subsys/profiling/perf/backends/perf_riscv.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2023 KNS Group LLC (YADRO)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+static bool valid_stack(uintptr_t addr, k_tid_t current)
+{
+ return current->stack_info.start <= addr &&
+ addr < current->stack_info.start + current->stack_info.size;
+}
+
+static inline bool in_text_region(uintptr_t addr)
+{
+ extern uintptr_t __text_region_start, __text_region_end;
+
+ return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+}
+
+/*
+ * This function use frame pointers to unwind stack and get trace of return addresses.
+ * Return addresses are translated in corresponding function's names using .elf file.
+ * So we get function call trace
+ */
+size_t arch_perf_current_stack_trace(uintptr_t *buf, size_t size)
+{
+ if (size < 2U)
+ return 0;
+
+ size_t idx = 0;
+
+ /*
+ * In riscv (arch/riscv/core/isr.S) ra, ip($mepc) and fp($s0) are saved
+ * at the beginning of _isr_wrapper in order, specified by z_arch_esf_t.
+ * Then, before calling interruption handler, core switch $sp to
+ * _current_cpu->irq_stack and save $sp with offset -16 on irq stack
+ *
+ * The following lines lines do the reverse things to get ra, ip anf fp
+ * from thread stack
+ */
+ const struct arch_esf * const esf =
+ *((struct arch_esf **)(((uintptr_t)_current_cpu->irq_stack) - 16));
+
+ /*
+ * $s0 is used as frame pointer.
+ *
+ * stack frame in memory (commonly):
+ * (addresses growth up)
+ * ....
+ * [-] <- $fp($s0) (curr)
+ * $ra
+ * $fp($s0) (next)
+ * ....
+ *
+ * If function do not call any other function, compiller may not save $ra,
+ * then stack frame will be:
+ * ....
+ * [-] <- $fp($s0) (curr)
+ * $fp($s0) (next)
+ * ....
+ *
+ */
+ void **fp = (void **)esf->s0;
+ void **new_fp = (void **)fp[-1];
+
+ buf[idx++] = (uintptr_t)esf->mepc;
+
+ /*
+ * During function prologue and epilogue fp is equal to fp of
+ * previous function stack frame, it looks like second function
+ * from top is missed.
+ * So saving $ra will help in case when irq occurred in
+ * function prologue or epilogue.
+ */
+ buf[idx++] = (uintptr_t)esf->ra;
+ if (valid_stack((uintptr_t)new_fp, _current)) {
+ fp = new_fp;
+ }
+ while (valid_stack((uintptr_t)fp, _current)) {
+ if (idx >= size)
+ return 0;
+
+ if (!in_text_region((uintptr_t)fp[-1])) {
+ break;
+ }
+
+ buf[idx++] = (uintptr_t)fp[-1];
+ new_fp = (void **)fp[-2];
+
+ /*
+ * anti-infinity-loop if
+ * new_fp can't be smaller than fp, cause the stack is growing down
+ * and trace moves deeper into the stack
+ */
+ if (new_fp <= fp) {
+ break;
+ }
+ fp = new_fp;
+ }
+
+ return idx;
+}
diff --git a/subsys/profiling/perf/backends/perf_x86.c b/subsys/profiling/perf/backends/perf_x86.c
new file mode 100644
index 0000000..05f4207
--- /dev/null
+++ b/subsys/profiling/perf/backends/perf_x86.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 KNS Group LLC (YADRO)
+ * Copyright (c) 2020 Yonatan Goldschmidt <yon.goldschmidt@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+static bool valid_stack(uintptr_t addr, k_tid_t current)
+{
+ return current->stack_info.start <= addr &&
+ addr < current->stack_info.start + current->stack_info.size;
+}
+
+static inline bool in_text_region(uintptr_t addr)
+{
+ extern uintptr_t __text_region_start, __text_region_end;
+
+ return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+}
+
+/* interruption stack frame */
+struct isf {
+ uint32_t ebp;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t eax;
+ uint32_t eip;
+};
+
+/*
+ * This function use frame pointers to unwind stack and get trace of return addresses.
+ * Return addresses are translated in corresponding function's names using .elf file.
+ * So we get function call trace
+ */
+size_t arch_perf_current_stack_trace(uintptr_t *buf, size_t size)
+{
+ if (size < 1U)
+ return 0;
+
+ size_t idx = 0;
+
+ const struct isf * const isf =
+ *((struct isf **)(((void **)_current_cpu->irq_stack)-1));
+ /*
+ * In x86 (arch/x86/core/ia32/intstub.S) %eip and %ebp
+ * are saved at the beginning of _interrupt_enter in order, that described
+ * in struct esf. Core switch %esp to
+ * _current_cpu->irq_stack and push %esp on irq stack
+ *
+ * The following lines lines do the reverse things to get %eip and %ebp
+ * from thread stack
+ */
+ void **fp = (void **)isf->ebp;
+
+ /*
+ * %ebp is frame pointer.
+ *
+ * stack frame in memory:
+ * (addresses growth up)
+ * ....
+ * ra
+ * %ebp (next) <- %ebp (curr)
+ * ....
+ */
+
+ buf[idx++] = (uintptr_t)isf->eip;
+ while (valid_stack((uintptr_t)fp, _current)) {
+ if (idx >= size)
+ return 0;
+
+ if (!in_text_region((uintptr_t)fp[1])) {
+ break;
+ }
+
+ buf[idx++] = (uintptr_t)fp[1];
+ void **new_fp = (void **)fp[0];
+
+ /*
+ * anti-infinity-loop if
+ * new_fp can't be smaller than fp, cause the stack is growing down
+ * and trace moves deeper into the stack
+ */
+ if (new_fp <= fp) {
+ break;
+ }
+ fp = new_fp;
+ }
+
+ return idx;
+}
diff --git a/subsys/profiling/perf/backends/perf_x86_64.c b/subsys/profiling/perf/backends/perf_x86_64.c
new file mode 100644
index 0000000..d0386a0
--- /dev/null
+++ b/subsys/profiling/perf/backends/perf_x86_64.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 KNS Group LLC (YADRO)
+ * Copyright (c) 2020 Yonatan Goldschmidt <yon.goldschmidt@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+static bool valid_stack(uintptr_t addr, k_tid_t current)
+{
+ return current->stack_info.start <= addr &&
+ addr < current->stack_info.start + current->stack_info.size;
+}
+
+static inline bool in_text_region(uintptr_t addr)
+{
+ extern uintptr_t __text_region_start, __text_region_end;
+
+ return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+}
+
+/*
+ * This function use frame pointers to unwind stack and get trace of return addresses.
+ * Return addresses are translated in corresponding function's names using .elf file.
+ * So we get function call trace
+ */
+size_t arch_perf_current_stack_trace(uintptr_t *buf, size_t size)
+{
+ if (size < 1U)
+ return 0;
+
+ size_t idx = 0;
+
+ /*
+ * In x86_64 (arch/x86/core/intel64/locore.S) %rip and %rbp
+ * are always saved in _current->callee_saved before calling
+ * handler function if interrupt is not nested
+ *
+ * %rip points the location where interrupt was occurred
+ */
+ buf[idx++] = (uintptr_t)_current->callee_saved.rip;
+ void **fp = (void **)_current->callee_saved.rbp;
+
+ /*
+ * %rbp is frame pointer.
+ *
+ * stack frame in memory:
+ * (addresses growth up)
+ * ....
+ * ra
+ * %rbp (next) <- %rbp (curr)
+ * ....
+ */
+ while (valid_stack((uintptr_t)fp, _current)) {
+ if (idx >= size)
+ return 0;
+
+ if (!in_text_region((uintptr_t)fp[1])) {
+ break;
+ }
+
+ buf[idx++] = (uintptr_t)fp[1];
+ void **new_fp = (void **)fp[0];
+
+ /*
+ * anti-infinity-loop if
+ * new_fp can't be smaller than fp, cause the stack is growing down
+ * and trace moves deeper into the stack
+ */
+ if (new_fp <= fp) {
+ break;
+ }
+ fp = new_fp;
+ }
+
+ return idx;
+}
diff --git a/subsys/profiling/perf/perf.c b/subsys/profiling/perf/perf.c
new file mode 100644
index 0000000..db6a7bf
--- /dev/null
+++ b/subsys/profiling/perf/perf.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2023 KNS Group LLC (YADRO)
+ * Copyright (c) 2020 Yonatan Goldschmidt <yon.goldschmidt@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_uart.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+size_t arch_perf_current_stack_trace(uintptr_t *buf, size_t size);
+
+struct perf_data_t {
+ struct k_timer timer;
+
+ const struct shell *sh;
+
+ struct k_work_delayable dwork;
+
+ size_t idx;
+ uintptr_t buf[CONFIG_PROFILING_PERF_BUFFER_SIZE];
+ bool buf_full;
+};
+
+static void perf_tracer(struct k_timer *timer);
+static void perf_dwork_handler(struct k_work *work);
+static struct perf_data_t perf_data = {
+ .timer = Z_TIMER_INITIALIZER(perf_data.timer, perf_tracer, NULL),
+ .dwork = Z_WORK_DELAYABLE_INITIALIZER(perf_dwork_handler),
+};
+
+static void perf_tracer(struct k_timer *timer)
+{
+ struct perf_data_t *perf_data_ptr =
+ (struct perf_data_t *)k_timer_user_data_get(timer);
+
+ size_t trace_length = 0;
+
+ if (++perf_data_ptr->idx < CONFIG_PROFILING_PERF_BUFFER_SIZE) {
+ trace_length = arch_perf_current_stack_trace(
+ perf_data_ptr->buf + perf_data_ptr->idx,
+ CONFIG_PROFILING_PERF_BUFFER_SIZE - perf_data_ptr->idx);
+ }
+
+ if (trace_length != 0) {
+ perf_data_ptr->buf[perf_data_ptr->idx - 1] = trace_length;
+ perf_data_ptr->idx += trace_length;
+ } else {
+ --perf_data_ptr->idx;
+ perf_data_ptr->buf_full = true;
+ k_work_reschedule(&perf_data_ptr->dwork, K_NO_WAIT);
+ }
+}
+
+static void perf_dwork_handler(struct k_work *work)
+{
+ struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+ struct perf_data_t *perf_data_ptr = CONTAINER_OF(dwork, struct perf_data_t, dwork);
+
+ k_timer_stop(&perf_data_ptr->timer);
+ if (perf_data_ptr->buf_full) {
+ shell_error(perf_data_ptr->sh, "Perf buf overflow!");
+ } else {
+ shell_print(perf_data_ptr->sh, "Perf done!");
+ }
+}
+
+static int cmd_perf_record(const struct shell *sh, size_t argc, char **argv)
+{
+ if (k_work_delayable_is_pending(&perf_data.dwork)) {
+ shell_warn(sh, "Perf is running");
+ return -EINPROGRESS;
+ }
+
+ if (perf_data.buf_full) {
+ shell_warn(sh, "Perf buffer is full");
+ return -ENOBUFS;
+ }
+
+ k_timeout_t duration = K_MSEC(strtoll(argv[1], NULL, 10));
+ k_timeout_t period = K_NSEC(1000000000 / strtoll(argv[2], NULL, 10));
+
+ perf_data.sh = sh;
+
+ k_timer_user_data_set(&perf_data.timer, &perf_data);
+ k_timer_start(&perf_data.timer, K_NO_WAIT, period);
+
+ k_work_schedule(&perf_data.dwork, duration);
+
+ shell_print(sh, "Enabled perf");
+
+ return 0;
+}
+
+static int cmd_perf_clear(const struct shell *sh, size_t argc, char **argv)
+{
+ if (sh != NULL) {
+ if (k_work_delayable_is_pending(&perf_data.dwork)) {
+ shell_warn(sh, "Perf is running");
+ return -EINPROGRESS;
+ }
+ shell_print(sh, "Perf buffer cleared");
+ }
+
+ perf_data.idx = 0;
+ perf_data.buf_full = false;
+
+ return 0;
+}
+
+static int cmd_perf_info(const struct shell *sh, size_t argc, char **argv)
+{
+ if (k_work_delayable_is_pending(&perf_data.dwork)) {
+ shell_print(sh, "Perf is running");
+ }
+
+ shell_print(sh, "Perf buf: %zu/%d %s", perf_data.idx, CONFIG_PROFILING_PERF_BUFFER_SIZE,
+ perf_data.buf_full ? "(full)" : "");
+
+ return 0;
+}
+
+static int cmd_perf_print(const struct shell *sh, size_t argc, char **argv)
+{
+ if (k_work_delayable_is_pending(&perf_data.dwork)) {
+ shell_warn(sh, "Perf is running");
+ return -EINPROGRESS;
+ }
+
+ shell_print(sh, "Perf buf length %zu", perf_data.idx);
+ for (size_t i = 0; i < perf_data.idx; i++) {
+ shell_print(sh, "%016lx", perf_data.buf[i]);
+ }
+
+ cmd_perf_clear(NULL, 0, NULL);
+
+ return 0;
+}
+
+#define CMD_HELP_RECORD \
+ "Start recording for <duration> ms on <frequency> Hz\n" \
+ "Usage: record <duration> <frequency>"
+
+SHELL_STATIC_SUBCMD_SET_CREATE(m_sub_perf,
+ SHELL_CMD_ARG(record, NULL, CMD_HELP_RECORD, cmd_perf_record, 3, 0),
+ SHELL_CMD_ARG(printbuf, NULL, "Print the perf buffer", cmd_perf_print, 0, 0),
+ SHELL_CMD_ARG(clear, NULL, "Clear the perf buffer", cmd_perf_clear, 0, 0),
+ SHELL_CMD_ARG(info, NULL, "Print the perf info", cmd_perf_info, 0, 0),
+ SHELL_SUBCMD_SET_END
+);
+SHELL_CMD_ARG_REGISTER(perf, &m_sub_perf, "Lightweight profiler", NULL, 0, 0);
diff --git a/subsys/rtio/rtio_executor.c b/subsys/rtio/rtio_executor.c
index 651ab64..49347b3 100644
--- a/subsys/rtio/rtio_executor.c
+++ b/subsys/rtio/rtio_executor.c
@@ -19,7 +19,7 @@
switch (sqe->op) {
case RTIO_OP_CALLBACK:
- sqe->callback(iodev_sqe->r, sqe, sqe->arg0);
+ sqe->callback.callback(iodev_sqe->r, sqe, sqe->callback.arg0);
rtio_iodev_sqe_ok(iodev_sqe, 0);
break;
default:
@@ -124,13 +124,13 @@
if (curr->sqe.op == RTIO_OP_RX && FIELD_GET(RTIO_SQE_MEMPOOL_BUFFER, curr->sqe.flags)) {
if (is_canceled) {
/* Free the memory first since no CQE will be generated */
- LOG_DBG("Releasing memory @%p size=%u", (void *)curr->sqe.buf,
- curr->sqe.buf_len);
- rtio_release_buffer(r, curr->sqe.buf, curr->sqe.buf_len);
+ LOG_DBG("Releasing memory @%p size=%u", (void *)curr->sqe.rx.buf,
+ curr->sqe.rx.buf_len);
+ rtio_release_buffer(r, curr->sqe.rx.buf, curr->sqe.rx.buf_len);
}
/* Reset the buffer info so the next request can get a new one */
- curr->sqe.buf = NULL;
- curr->sqe.buf_len = 0;
+ curr->sqe.rx.buf = NULL;
+ curr->sqe.rx.buf_len = 0;
}
if (!is_canceled) {
/* Request was not canceled, put the SQE back in the queue */
diff --git a/subsys/rtio/rtio_handlers.c b/subsys/rtio/rtio_handlers.c
index d3f3824..a82de16 100644
--- a/subsys/rtio/rtio_handlers.c
+++ b/subsys/rtio/rtio_handlers.c
@@ -29,18 +29,18 @@
case RTIO_OP_NOP:
break;
case RTIO_OP_TX:
- valid_sqe &= K_SYSCALL_MEMORY(sqe->buf, sqe->buf_len, false);
+ valid_sqe &= K_SYSCALL_MEMORY(sqe->tx.buf, sqe->tx.buf_len, false);
break;
case RTIO_OP_RX:
if ((sqe->flags & RTIO_SQE_MEMPOOL_BUFFER) == 0) {
- valid_sqe &= K_SYSCALL_MEMORY(sqe->buf, sqe->buf_len, true);
+ valid_sqe &= K_SYSCALL_MEMORY(sqe->rx.buf, sqe->rx.buf_len, true);
}
break;
case RTIO_OP_TINY_TX:
break;
case RTIO_OP_TXRX:
- valid_sqe &= K_SYSCALL_MEMORY(sqe->tx_buf, sqe->txrx_buf_len, true);
- valid_sqe &= K_SYSCALL_MEMORY(sqe->rx_buf, sqe->txrx_buf_len, true);
+ valid_sqe &= K_SYSCALL_MEMORY(sqe->txrx.tx_buf, sqe->txrx.buf_len, true);
+ valid_sqe &= K_SYSCALL_MEMORY(sqe->txrx.rx_buf, sqe->txrx.buf_len, true);
break;
default:
/* RTIO OP must be known and allowable from user mode
diff --git a/subsys/sd/sd.c b/subsys/sd/sd.c
index f075203..9387cbe 100644
--- a/subsys/sd/sd.c
+++ b/subsys/sd/sd.c
@@ -56,7 +56,7 @@
resp = cmd.response[0];
}
if ((resp & 0xFF) != SD_IF_COND_CHECK) {
- LOG_INF("Legacy card detected, no CMD8 support");
+ LOG_DBG("Legacy card detected, no CMD8 support");
/* Retry probe */
return SD_RETRY;
}
diff --git a/subsys/sd/sd_ops.c b/subsys/sd/sd_ops.c
index 5815f3f..7e0f534 100644
--- a/subsys/sd/sd_ops.c
+++ b/subsys/sd/sd_ops.c
@@ -795,6 +795,16 @@
*/
ret = sdmmc_wait_ready(card);
break;
+ case DISK_IOCTL_CTRL_DEINIT:
+ /* Ensure card is not busy with data write */
+ ret = sdmmc_wait_ready(card);
+ if (ret < 0) {
+ LOG_WRN("Card busy when powering off");
+ }
+ /* Power down the card */
+ card->bus_io.power_mode = SDHC_POWER_OFF;
+ ret = sdhc_set_io(card->sdhc, &card->bus_io);
+ break;
default:
ret = -ENOTSUP;
}
diff --git a/subsys/shell/backends/Kconfig.backends b/subsys/shell/backends/Kconfig.backends
index 372ba10..4524d03 100644
--- a/subsys/shell/backends/Kconfig.backends
+++ b/subsys/shell/backends/Kconfig.backends
@@ -75,6 +75,11 @@
endchoice
+config SHELL_BACKEND_SERIAL_FORCE_TX_BLOCKING_MODE
+ bool "Force blocking mode for TX"
+ help
+ Force blocking mode for TX.
+
config SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE
int "Set TX ring buffer size"
default 8
diff --git a/subsys/shell/backends/shell_uart.c b/subsys/shell/backends/shell_uart.c
index a452323..7cf4bbf 100644
--- a/subsys/shell/backends/shell_uart.c
+++ b/subsys/shell/backends/shell_uart.c
@@ -346,7 +346,8 @@
{
struct shell_uart_common *sh_uart = (struct shell_uart_common *)transport->ctx;
- sh_uart->blocking_tx = blocking_tx;
+ sh_uart->blocking_tx =
+ blocking_tx || IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_FORCE_TX_BLOCKING_MODE);
if (IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_API_INTERRUPT_DRIVEN) && blocking_tx) {
uart_irq_tx_disable(sh_uart->dev);
diff --git a/subsys/testsuite/arch/unit_testing/Kconfig b/subsys/testsuite/arch/unit_testing/Kconfig
index fcb56a1..3d214d8 100644
--- a/subsys/testsuite/arch/unit_testing/Kconfig
+++ b/subsys/testsuite/arch/unit_testing/Kconfig
@@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0
# Current the use of X86 is for consistency with old testsuite/ztest which
-# defined CONFIG_X86 manually. To consider, is NATIVE_POSIX a better choice?
+# defined CONFIG_X86 manually. To consider, is ARCH_POSIX a better choice?
config X86
bool
default y
diff --git a/subsys/testsuite/coverage/coverage.c b/subsys/testsuite/coverage/coverage.c
index 8e723dd..084aaec 100644
--- a/subsys/testsuite/coverage/coverage.c
+++ b/subsys/testsuite/coverage/coverage.c
@@ -263,7 +263,9 @@
{
struct gcov_info *gcov_list = NULL;
+#ifdef CONFIG_MULTITHREADING
k_sched_lock();
+#endif
gcov_list = gcov_get_list_head();
@@ -272,7 +274,9 @@
gcov_list = gcov_list->next;
}
+#ifdef CONFIG_MULTITHREADING
k_sched_unlock();
+#endif
}
void dump_on_console_start(const char *filename)
@@ -305,7 +309,9 @@
struct gcov_info *gcov_list = gcov_info_head;
if (!k_is_in_isr()) {
+#ifdef CONFIG_MULTITHREADING
k_sched_lock();
+#endif
}
printk("\nGCOV_COVERAGE_DUMP_START");
while (gcov_list) {
@@ -336,7 +342,9 @@
coverage_dump_end:
printk("\nGCOV_COVERAGE_DUMP_END\n");
if (!k_is_in_isr()) {
+#ifdef CONFIG_MULTITHREADING
k_sched_unlock();
+#endif
}
return;
}
diff --git a/subsys/testsuite/coverage/coverage_ram.ld b/subsys/testsuite/coverage/coverage_ram.ld
index df348cb..5c44f15 100644
--- a/subsys/testsuite/coverage/coverage_ram.ld
+++ b/subsys/testsuite/coverage/coverage_ram.ld
@@ -6,7 +6,7 @@
/* Copied from linker.ld */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
SECTION_DATA_PROLOGUE(_GCOV_BSS_SECTION_NAME,(NOLOAD),)
{
#ifdef CONFIG_USERSPACE
diff --git a/subsys/testsuite/ztest/CMakeLists.txt b/subsys/testsuite/ztest/CMakeLists.txt
index 2a5104e..35bbe09 100644
--- a/subsys/testsuite/ztest/CMakeLists.txt
+++ b/subsys/testsuite/ztest/CMakeLists.txt
@@ -18,7 +18,7 @@
zephyr_library()
# For strtok_r() and strdup()
-zephyr_library_compile_options(-D_POSIX_C_SOURCE=200809L)
+zephyr_library_compile_options(-U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L)
zephyr_library_sources(
src/ztest.c
diff --git a/subsys/testsuite/ztest/src/ztest.c b/subsys/testsuite/ztest/src/ztest.c
index 68de18d..84d5aba 100644
--- a/subsys/testsuite/ztest/src/ztest.c
+++ b/subsys/testsuite/ztest/src/ztest.c
@@ -948,7 +948,7 @@
struct ztest_unit_test *test = NULL;
unsigned int suite_duration_worst_ms = 0;
- /** summary of disctinct run */
+ /** summary of distinct run */
while (((test = z_ztest_get_next_test(suite->name, test)) != NULL)) {
distinct_total++;
suite_duration_worst_ms += test->stats->duration_worst_ms;
@@ -1022,7 +1022,7 @@
}
if (flush_frequency % 3 == 0) {
- /** Reduce the flush frequencey a bit to speed up the output */
+ /** Reduce the flush frequency a bit to speed up the output */
flush_log();
}
flush_frequency++;
@@ -1285,8 +1285,7 @@
case 's':
val = atoi(state->optarg);
if (val < 1) {
- shell_fprintf(sh, SHELL_ERROR,
- "Invalid number of suite interations\n");
+ shell_error(sh, "Invalid number of suite iterations");
return -ENOEXEC;
}
suite_iter = val;
@@ -1295,16 +1294,15 @@
case 'c':
val = atoi(state->optarg);
if (val < 1) {
- shell_fprintf(sh, SHELL_ERROR,
- "Invalid number of case interations\n");
+ shell_error(sh, "Invalid number of case iterations");
return -ENOEXEC;
}
case_iter = val;
opt_num++;
break;
default:
- shell_fprintf(sh, SHELL_ERROR, "Invalid option or option usage: %s\n",
- argv[opt_index + 1]);
+ shell_error(sh, "Invalid option or option usage: %s",
+ argv[opt_index + 1]);
return -ENOEXEC;
}
}
diff --git a/subsys/tracing/Kconfig b/subsys/tracing/Kconfig
index 31017e6..4e9abb0 100644
--- a/subsys/tracing/Kconfig
+++ b/subsys/tracing/Kconfig
@@ -329,11 +329,26 @@
Enable tracing Power Management.
config TRACING_NETWORKING
- bool "Tracing Network Sockets"
+ bool "Tracing Network Objects"
default y if NETWORKING
help
+ Enable tracing network objects.
+
+config TRACING_NET_SOCKETS
+ bool "Tracing Network Sockets"
+ depends on TRACING_NETWORKING
+ default y if NET_SOCKETS
+ help
Enable tracing network sockets.
+config TRACING_NET_CORE
+ bool "Tracing Network Core IP stack"
+ depends on TRACING_NETWORKING
+ default y if NET_IP
+ help
+ Enable tracing core network IP stack, like packet reception
+ and sending.
+
endmenu # Tracing Configuration
endif
diff --git a/subsys/tracing/ctf/ctf_top.c b/subsys/tracing/ctf/ctf_top.c
index b8d1def..12ab437 100644
--- a/subsys/tracing/ctf/ctf_top.c
+++ b/subsys/tracing/ctf/ctf_top.c
@@ -8,8 +8,11 @@
#include <zephyr/kernel_structs.h>
#include <kernel_internal.h>
#include <ctf_top.h>
+#include <zephyr/net/net_core.h>
#include <zephyr/net/net_ip.h>
#include <zephyr/net/socket_poll.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/net_pkt.h>
static void _get_thread_name(struct k_thread *thread,
ctf_bounded_string_t *name)
@@ -635,3 +638,111 @@
{
ctf_top_socket_socketpair_exit(sock_A, sock_B, ret);
}
+
+void sys_trace_net_recv_data_enter(struct net_if *iface, struct net_pkt *pkt)
+{
+ ctf_top_net_recv_data_enter((int32_t)net_if_get_by_iface(iface),
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (uint32_t)net_pkt_get_len(pkt));
+}
+
+void sys_trace_net_recv_data_exit(struct net_if *iface, struct net_pkt *pkt, int ret)
+{
+ ctf_top_net_recv_data_exit((int32_t)net_if_get_by_iface(iface),
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (int32_t)ret);
+}
+
+void sys_trace_net_send_data_enter(struct net_pkt *pkt)
+{
+ struct net_if *iface;
+ int ifindex;
+
+ iface = net_pkt_iface(pkt);
+ if (iface == NULL) {
+ ifindex = -1;
+ } else {
+ ifindex = net_if_get_by_iface(iface);
+ }
+
+ ctf_top_net_send_data_enter((int32_t)ifindex,
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (uint32_t)net_pkt_get_len(pkt));
+}
+
+void sys_trace_net_send_data_exit(struct net_pkt *pkt, int ret)
+{
+ struct net_if *iface;
+ int ifindex;
+
+ iface = net_pkt_iface(pkt);
+ if (iface == NULL) {
+ ifindex = -1;
+ } else {
+ ifindex = net_if_get_by_iface(iface);
+ }
+
+ ctf_top_net_send_data_exit((int32_t)ifindex,
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (int32_t)ret);
+}
+
+void sys_trace_net_rx_time(struct net_pkt *pkt, uint32_t end_time)
+{
+ struct net_if *iface;
+ int ifindex;
+ uint32_t diff;
+ int tc;
+ uint32_t duration_us;
+
+ iface = net_pkt_iface(pkt);
+ if (iface == NULL) {
+ ifindex = -1;
+ tc = 0;
+ duration_us = 0;
+ } else {
+ ifindex = net_if_get_by_iface(iface);
+ diff = end_time - net_pkt_create_time(pkt);
+ tc = net_rx_priority2tc(net_pkt_priority(pkt));
+ duration_us = k_cyc_to_ns_floor64(diff) / 1000U;
+ }
+
+ ctf_top_net_rx_time((int32_t)ifindex,
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (uint32_t)net_pkt_priority(pkt),
+ (uint32_t)tc,
+ (uint32_t)duration_us);
+}
+
+void sys_trace_net_tx_time(struct net_pkt *pkt, uint32_t end_time)
+{
+ struct net_if *iface;
+ int ifindex;
+ uint32_t diff;
+ int tc;
+ uint32_t duration_us;
+
+ iface = net_pkt_iface(pkt);
+ if (iface == NULL) {
+ ifindex = -1;
+ tc = 0;
+ duration_us = 0;
+ } else {
+ ifindex = net_if_get_by_iface(iface);
+ diff = end_time - net_pkt_create_time(pkt);
+ tc = net_rx_priority2tc(net_pkt_priority(pkt));
+ duration_us = k_cyc_to_ns_floor64(diff) / 1000U;
+ }
+
+ ctf_top_net_tx_time((int32_t)ifindex,
+ (uint32_t)(uintptr_t)iface,
+ (uint32_t)(uintptr_t)pkt,
+ (uint32_t)net_pkt_priority(pkt),
+ (uint32_t)tc,
+ (uint32_t)duration_us);
+}
diff --git a/subsys/tracing/ctf/ctf_top.h b/subsys/tracing/ctf/ctf_top.h
index 38ce467..4929107 100644
--- a/subsys/tracing/ctf/ctf_top.h
+++ b/subsys/tracing/ctf/ctf_top.h
@@ -151,6 +151,12 @@
CTF_EVENT_SOCKET_GETSOCKNAME_EXIT = 0x59,
CTF_EVENT_SOCKET_SOCKETPAIR_ENTER = 0x5A,
CTF_EVENT_SOCKET_SOCKETPAIR_EXIT = 0x5B,
+ CTF_EVENT_NET_RECV_DATA_ENTER = 0x5C,
+ CTF_EVENT_NET_RECV_DATA_EXIT = 0x5D,
+ CTF_EVENT_NET_SEND_DATA_ENTER = 0x5E,
+ CTF_EVENT_NET_SEND_DATA_EXIT = 0x5F,
+ CTF_EVENT_NET_RX_TIME = 0x60,
+ CTF_EVENT_NET_TX_TIME = 0x61,
} ctf_event_t;
@@ -609,4 +615,47 @@
CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_SOCKET_SOCKETPAIR_EXIT), sock_A, sock_B, ret);
}
+
+static inline void ctf_top_net_recv_data_enter(int32_t if_index, uint32_t iface, uint32_t pkt,
+ uint32_t len)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_RECV_DATA_ENTER),
+ if_index, iface, pkt, len);
+}
+
+static inline void ctf_top_net_recv_data_exit(int32_t if_index, uint32_t iface, uint32_t pkt,
+ int32_t ret)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_RECV_DATA_EXIT),
+ if_index, iface, pkt, ret);
+}
+
+static inline void ctf_top_net_send_data_enter(int32_t if_index, uint32_t iface, uint32_t pkt,
+ uint32_t len)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_SEND_DATA_ENTER),
+ if_index, iface, pkt, len);
+}
+
+static inline void ctf_top_net_send_data_exit(int32_t if_index, uint32_t iface, uint32_t pkt,
+ int32_t ret)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_SEND_DATA_EXIT),
+ if_index, iface, pkt, ret);
+}
+
+static inline void ctf_top_net_rx_time(int32_t if_index, uint32_t iface, uint32_t pkt,
+ uint32_t priority, uint32_t tc, uint32_t duration)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_RX_TIME),
+ if_index, iface, pkt, priority, tc, duration);
+}
+
+static inline void ctf_top_net_tx_time(int32_t if_index, uint32_t iface, uint32_t pkt,
+ uint32_t priority, uint32_t tc, uint32_t duration)
+{
+ CTF_EVENT(CTF_LITERAL(uint8_t, CTF_EVENT_NET_TX_TIME),
+ if_index, iface, pkt, priority, tc, duration);
+}
+
#endif /* SUBSYS_DEBUG_TRACING_CTF_TOP_H */
diff --git a/subsys/tracing/ctf/tracing_ctf.h b/subsys/tracing/ctf/tracing_ctf.h
index 2756e6e..ab87411 100644
--- a/subsys/tracing/ctf/tracing_ctf.h
+++ b/subsys/tracing/ctf/tracing_ctf.h
@@ -569,6 +569,29 @@
void sys_trace_socket_socketpair_enter(int family, int type, int proto, int *sv);
void sys_trace_socket_socketpair_exit(int sock_A, int sock_B, int ret);
+#define sys_port_trace_net_recv_data_enter(iface, pkt) \
+ sys_trace_net_recv_data_enter(iface, pkt)
+#define sys_port_trace_net_recv_data_exit(iface, pkt, ret) \
+ sys_trace_net_recv_data_exit(iface, pkt, ret)
+#define sys_port_trace_net_send_data_enter(pkt) \
+ sys_trace_net_send_data_enter(pkt)
+#define sys_port_trace_net_send_data_exit(pkt, ret) \
+ sys_trace_net_send_data_exit(pkt, ret)
+#define sys_port_trace_net_rx_time(pkt, end_time) \
+ sys_trace_net_rx_time(pkt, end_time)
+#define sys_port_trace_net_tx_time(pkt, end_time) \
+ sys_trace_net_tx_time(pkt, end_time)
+
+struct net_if;
+struct net_pkt;
+
+void sys_trace_net_recv_data_enter(struct net_if *iface, struct net_pkt *pkt);
+void sys_trace_net_recv_data_exit(struct net_if *iface, struct net_pkt *pkt, int ret);
+void sys_trace_net_send_data_enter(struct net_pkt *pkt);
+void sys_trace_net_send_data_exit(struct net_pkt *pkt, int ret);
+void sys_trace_net_rx_time(struct net_pkt *pkt, uint32_t end_time);
+void sys_trace_net_tx_time(struct net_pkt *pkt, uint32_t end_time);
+
#ifdef __cplusplus
}
#endif
diff --git a/subsys/tracing/ctf/tsdl/metadata b/subsys/tracing/ctf/tsdl/metadata
index dd57334..efaa2ad 100644
--- a/subsys/tracing/ctf/tsdl/metadata
+++ b/subsys/tracing/ctf/tsdl/metadata
@@ -707,3 +707,73 @@
int32_t result;
};
};
+
+event {
+ name = net_recv_data_enter;
+ id = 0x5C;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ uint32_t pkt_len;
+ };
+};
+
+event {
+ name = net_recv_data_exit;
+ id = 0x5D;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ int32_t result;
+ };
+};
+
+event {
+ name = net_send_data_enter;
+ id = 0x5E;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ uint32_t pkt_len;
+ };
+};
+
+event {
+ name = net_send_data_exit;
+ id = 0x5F;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ int32_t result;
+ };
+};
+
+event {
+ name = net_rx_time;
+ id = 0x60;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ uint32_t priority;
+ uint32_t traffic_class;
+ uint32_t duration_us;
+ };
+};
+
+event {
+ name = net_tx_time;
+ id = 0x61;
+ fields := struct {
+ int32_t if_index;
+ uint32_t iface;
+ uint32_t pkt;
+ uint32_t priority;
+ uint32_t traffic_class;
+ uint32_t duration_us;
+ };
+};
diff --git a/subsys/tracing/test/tracing_test.h b/subsys/tracing/test/tracing_test.h
index 6ad7bcd..3afbb79 100644
--- a/subsys/tracing/test/tracing_test.h
+++ b/subsys/tracing/test/tracing_test.h
@@ -732,6 +732,13 @@
#define sys_port_trace_socket_socketpair_enter(family, type, proto, sv)
#define sys_port_trace_socket_socketpair_exit(sockA, sockB, ret)
+#define sys_port_trace_net_recv_data_enter(iface, pkt)
+#define sys_port_trace_net_recv_data_exit(iface, pkt, ret)
+#define sys_port_trace_net_send_data_enter(pkt)
+#define sys_port_trace_net_send_data_exit(pkt, ret)
+#define sys_port_trace_net_rx_time(pkt, end_time)
+#define sys_port_trace_net_tx_time(pkt, end_time)
+
#define sys_trace_sys_init_enter(...)
#define sys_trace_sys_init_exit(...)
diff --git a/subsys/tracing/tracing_backend_adsp_memory_window.c b/subsys/tracing/tracing_backend_adsp_memory_window.c
index 2efcb64..43f8229 100644
--- a/subsys/tracing/tracing_backend_adsp_memory_window.c
+++ b/subsys/tracing/tracing_backend_adsp_memory_window.c
@@ -41,8 +41,9 @@
if (length) {
memcpy((void *)mem_window->data, data + to_copy, length);
mem_window->head_offset = length;
- } else
+ } else {
mem_window->head_offset += to_copy;
+ }
}
static void tracing_backend_adsp_memory_window_init(void)
diff --git a/subsys/tracing/user/tracing_user.h b/subsys/tracing/user/tracing_user.h
index f513405..8d66308 100644
--- a/subsys/tracing/user/tracing_user.h
+++ b/subsys/tracing/user/tracing_user.h
@@ -383,6 +383,13 @@
#define sys_port_trace_socket_socketpair_enter(family, type, proto, sv)
#define sys_port_trace_socket_socketpair_exit(sockA, sockB, ret)
+#define sys_port_trace_net_recv_data_enter(iface, pkt)
+#define sys_port_trace_net_recv_data_exit(iface, pkt, ret)
+#define sys_port_trace_net_send_data_enter(pkt)
+#define sys_port_trace_net_send_data_exit(pkt, ret)
+#define sys_port_trace_net_rx_time(pkt, end_time)
+#define sys_port_trace_net_tx_time(pkt, end_time)
+
#ifdef __cplusplus
}
#endif
diff --git a/subsys/usb/device/class/bluetooth.c b/subsys/usb/device/class/bluetooth.c
index 63b8523..59e5f31 100644
--- a/subsys/usb/device/class/bluetooth.c
+++ b/subsys/usb/device/class/bluetooth.c
@@ -133,7 +133,7 @@
while (true) {
struct net_buf *buf;
- buf = net_buf_get(&tx_queue, K_FOREVER);
+ buf = k_fifo_get(&tx_queue, K_FOREVER);
if (IS_ENABLED(CONFIG_USB_DEVICE_BLUETOOTH_VS_H4) &&
bt_hci_raw_get_mode() == BT_HCI_RAW_MODE_H4) {
@@ -188,7 +188,7 @@
struct net_buf *buf;
int err;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
err = bt_send(buf);
if (err) {
@@ -296,7 +296,7 @@
}
if (buf != NULL && pkt_len == buf->len) {
- net_buf_put(&rx_queue, buf);
+ k_fifo_put(&rx_queue, buf);
LOG_DBG("put");
buf = NULL;
pkt_len = 0;
@@ -373,7 +373,7 @@
net_buf_add_u8(rsp, BT_HCI_VS_USB_H2_MODE);
net_buf_add_u8(rsp, BT_HCI_VS_USB_H4_MODE);
- net_buf_put(&tx_queue, rsp);
+ k_fifo_put(&tx_queue, rsp);
return BT_HCI_ERR_EXT_HANDLED;
}
@@ -430,7 +430,7 @@
return -ENOMEM;
}
- net_buf_put(&rx_queue, buf);
+ k_fifo_put(&rx_queue, buf);
return 0;
}
diff --git a/subsys/usb/device/class/bt_h4.c b/subsys/usb/device/class/bt_h4.c
index d4004a8..83a94a0 100644
--- a/subsys/usb/device/class/bt_h4.c
+++ b/subsys/usb/device/class/bt_h4.c
@@ -105,7 +105,7 @@
return;
}
- net_buf_put(&rx_queue, buf);
+ k_fifo_put(&rx_queue, buf);
}
/* Start a new read transfer */
@@ -124,7 +124,7 @@
while (true) {
struct net_buf *buf;
- buf = net_buf_get(&tx_queue, K_FOREVER);
+ buf = k_fifo_get(&tx_queue, K_FOREVER);
usb_transfer_sync(bt_h4_ep_data[BT_H4_IN_EP_IDX].ep_addr,
buf->data, buf->len, USB_TRANS_WRITE);
@@ -142,7 +142,7 @@
while (true) {
struct net_buf *buf;
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
if (bt_send(buf)) {
LOG_ERR("Error sending to driver");
net_buf_unref(buf);
diff --git a/subsys/usb/device/class/netusb/function_rndis.c b/subsys/usb/device/class/netusb/function_rndis.c
index bbdfa75..1491b6e 100644
--- a/subsys/usb/device/class/netusb/function_rndis.c
+++ b/subsys/usb/device/class/netusb/function_rndis.c
@@ -409,7 +409,7 @@
LOG_DBG("Queued response pkt %p", rsp);
- net_buf_put(&rndis_tx_queue, rsp);
+ k_fifo_put(&rndis_tx_queue, rsp);
}
/* Notify host about available data */
@@ -776,7 +776,7 @@
memcpy(net_buf_add(buf, len), data, len);
- net_buf_put(&rndis_cmd_queue, buf);
+ k_fifo_put(&rndis_cmd_queue, buf);
LOG_DBG("queued buf %p", buf);
@@ -827,7 +827,7 @@
LOG_DBG("");
- buf = net_buf_get(&rndis_tx_queue, K_NO_WAIT);
+ buf = k_fifo_get(&rndis_tx_queue, K_NO_WAIT);
if (!buf) {
LOG_ERR("Error getting response buffer");
*len = 0U;
@@ -894,7 +894,7 @@
while (true) {
struct net_buf *buf;
- buf = net_buf_get(&rndis_cmd_queue, K_FOREVER);
+ buf = k_fifo_get(&rndis_cmd_queue, K_FOREVER);
LOG_DBG("got buf %p", buf);
diff --git a/subsys/usb/device/usb_descriptor.c b/subsys/usb/device/usb_descriptor.c
index 1fcbefa..3b6b29d 100644
--- a/subsys/usb/device/usb_descriptor.c
+++ b/subsys/usb/device/usb_descriptor.c
@@ -266,7 +266,7 @@
ep_cfg.ep_type = (ep_descr->bmAttributes &
USB_EP_TRANSFER_TYPE_MASK);
- ep_cfg.ep_mps = ep_descr->wMaxPacketSize;
+ ep_cfg.ep_mps = sys_le16_to_cpu(ep_descr->wMaxPacketSize);
ep_cfg.ep_addr = ep_descr->bEndpointAddress;
if (ep_cfg.ep_addr & USB_EP_DIR_IN) {
if ((*requested_ep & (1U << (idx + 16U)))) {
diff --git a/subsys/usb/device_next/class/bt_hci.c b/subsys/usb/device_next/class/bt_hci.c
index 273a910..debefa1 100644
--- a/subsys/usb/device_next/class/bt_hci.c
+++ b/subsys/usb/device_next/class/bt_hci.c
@@ -204,7 +204,7 @@
struct net_buf *bt_buf;
uint8_t ep;
- bt_buf = net_buf_get(&bt_hci_tx_queue, K_FOREVER);
+ bt_buf = k_fifo_get(&bt_hci_tx_queue, K_FOREVER);
switch (bt_buf_get_type(bt_buf)) {
case BT_BUF_EVT:
@@ -231,7 +231,7 @@
int err;
/* FIXME: Do we need a separate thread for bt_send()? */
- buf = net_buf_get(&bt_hci_rx_queue, K_FOREVER);
+ buf = k_fifo_get(&bt_hci_rx_queue, K_FOREVER);
err = bt_send(buf);
if (err) {
@@ -354,7 +354,7 @@
}
if (hci_data->acl_buf != NULL && hci_data->acl_len == hci_data->acl_buf->len) {
- net_buf_put(&bt_hci_rx_queue, hci_data->acl_buf);
+ k_fifo_put(&bt_hci_rx_queue, hci_data->acl_buf);
hci_data->acl_buf = NULL;
hci_data->acl_len = 0;
}
@@ -440,7 +440,7 @@
return -ENOMEM;
}
- net_buf_put(&bt_hci_rx_queue, cmd_buf);
+ k_fifo_put(&bt_hci_rx_queue, cmd_buf);
return 0;
}
@@ -564,7 +564,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = BT_HCI_EP_VOICE_IN, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = 0, \
+ .wMaxPacketSize = sys_cpu_to_le16(0), \
.bInterval = BT_HCI_EP_INTERVAL_VOICE, \
}, \
\
@@ -573,7 +573,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = BT_HCI_EP_VOICE_OUT, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = 0, \
+ .wMaxPacketSize = sys_cpu_to_le16(0), \
.bInterval = BT_HCI_EP_INTERVAL_VOICE, \
}, \
\
@@ -594,7 +594,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = BT_HCI_EP_VOICE_IN, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = BT_HCI_EP_MPS_VOICE, \
+ .wMaxPacketSize = sys_cpu_to_le16(BT_HCI_EP_MPS_VOICE), \
.bInterval = BT_HCI_EP_INTERVAL_VOICE, \
}, \
\
@@ -603,7 +603,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = BT_HCI_EP_VOICE_OUT, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = BT_HCI_EP_MPS_VOICE, \
+ .wMaxPacketSize = sys_cpu_to_le16(BT_HCI_EP_MPS_VOICE), \
.bInterval = BT_HCI_EP_INTERVAL_VOICE, \
}, \
\
diff --git a/subsys/usb/device_next/class/loopback.c b/subsys/usb/device_next/class/loopback.c
index 8a9688d..2237cab 100644
--- a/subsys/usb/device_next/class/loopback.c
+++ b/subsys/usb/device_next/class/loopback.c
@@ -270,7 +270,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = 0x83, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = 0, \
+ .wMaxPacketSize = sys_cpu_to_le16(0), \
.bInterval = LB_ISO_EP_INTERVAL, \
}, \
\
@@ -279,7 +279,7 @@
.bDescriptorType = USB_DESC_ENDPOINT, \
.bEndpointAddress = 0x03, \
.bmAttributes = USB_EP_TYPE_ISO, \
- .wMaxPacketSize = 0, \
+ .wMaxPacketSize = sys_cpu_to_le16(0), \
.bInterval = LB_ISO_EP_INTERVAL, \
}, \
\
diff --git a/subsys/usb/device_next/class/usbd_hid.c b/subsys/usb/device_next/class/usbd_hid.c
index e11c7f1..fe67f7e 100644
--- a/subsys/usb/device_next/class/usbd_hid.c
+++ b/subsys/usb/device_next/class/usbd_hid.c
@@ -742,6 +742,8 @@
(USBD_HID_INTERFACE_ALTERNATE_DEFINE(n)))
#define USBD_HID_INSTANCE_DEFINE(n) \
+ HID_VERIFY_REPORT_SIZES(n); \
+ \
NET_BUF_POOL_DEFINE(hid_buf_pool_in_##n, \
CONFIG_USBD_HID_IN_BUF_COUNT, 0, \
sizeof(struct udc_buf_info), NULL); \
diff --git a/subsys/usb/device_next/class/usbd_hid_macros.h b/subsys/usb/device_next/class/usbd_hid_macros.h
index ba12113..ac9dbde 100644
--- a/subsys/usb/device_next/class/usbd_hid_macros.h
+++ b/subsys/usb/device_next/class/usbd_hid_macros.h
@@ -84,966 +84,6 @@
#define HID_MPS_LESS_65_62 1
#define HID_MPS_LESS_65_63 1
#define HID_MPS_LESS_65_64 1
-#define HID_MPS_LESS_65_65 0
-#define HID_MPS_LESS_65_66 0
-#define HID_MPS_LESS_65_67 0
-#define HID_MPS_LESS_65_68 0
-#define HID_MPS_LESS_65_69 0
-#define HID_MPS_LESS_65_70 0
-#define HID_MPS_LESS_65_71 0
-#define HID_MPS_LESS_65_72 0
-#define HID_MPS_LESS_65_73 0
-#define HID_MPS_LESS_65_74 0
-#define HID_MPS_LESS_65_75 0
-#define HID_MPS_LESS_65_76 0
-#define HID_MPS_LESS_65_77 0
-#define HID_MPS_LESS_65_78 0
-#define HID_MPS_LESS_65_79 0
-#define HID_MPS_LESS_65_80 0
-#define HID_MPS_LESS_65_81 0
-#define HID_MPS_LESS_65_82 0
-#define HID_MPS_LESS_65_83 0
-#define HID_MPS_LESS_65_84 0
-#define HID_MPS_LESS_65_85 0
-#define HID_MPS_LESS_65_86 0
-#define HID_MPS_LESS_65_87 0
-#define HID_MPS_LESS_65_88 0
-#define HID_MPS_LESS_65_89 0
-#define HID_MPS_LESS_65_90 0
-#define HID_MPS_LESS_65_91 0
-#define HID_MPS_LESS_65_92 0
-#define HID_MPS_LESS_65_93 0
-#define HID_MPS_LESS_65_94 0
-#define HID_MPS_LESS_65_95 0
-#define HID_MPS_LESS_65_96 0
-#define HID_MPS_LESS_65_97 0
-#define HID_MPS_LESS_65_98 0
-#define HID_MPS_LESS_65_99 0
-#define HID_MPS_LESS_65_100 0
-#define HID_MPS_LESS_65_101 0
-#define HID_MPS_LESS_65_102 0
-#define HID_MPS_LESS_65_103 0
-#define HID_MPS_LESS_65_104 0
-#define HID_MPS_LESS_65_105 0
-#define HID_MPS_LESS_65_106 0
-#define HID_MPS_LESS_65_107 0
-#define HID_MPS_LESS_65_108 0
-#define HID_MPS_LESS_65_109 0
-#define HID_MPS_LESS_65_110 0
-#define HID_MPS_LESS_65_111 0
-#define HID_MPS_LESS_65_112 0
-#define HID_MPS_LESS_65_113 0
-#define HID_MPS_LESS_65_114 0
-#define HID_MPS_LESS_65_115 0
-#define HID_MPS_LESS_65_116 0
-#define HID_MPS_LESS_65_117 0
-#define HID_MPS_LESS_65_118 0
-#define HID_MPS_LESS_65_119 0
-#define HID_MPS_LESS_65_120 0
-#define HID_MPS_LESS_65_121 0
-#define HID_MPS_LESS_65_122 0
-#define HID_MPS_LESS_65_123 0
-#define HID_MPS_LESS_65_124 0
-#define HID_MPS_LESS_65_125 0
-#define HID_MPS_LESS_65_126 0
-#define HID_MPS_LESS_65_127 0
-#define HID_MPS_LESS_65_128 0
-#define HID_MPS_LESS_65_129 0
-#define HID_MPS_LESS_65_130 0
-#define HID_MPS_LESS_65_131 0
-#define HID_MPS_LESS_65_132 0
-#define HID_MPS_LESS_65_133 0
-#define HID_MPS_LESS_65_134 0
-#define HID_MPS_LESS_65_135 0
-#define HID_MPS_LESS_65_136 0
-#define HID_MPS_LESS_65_137 0
-#define HID_MPS_LESS_65_138 0
-#define HID_MPS_LESS_65_139 0
-#define HID_MPS_LESS_65_140 0
-#define HID_MPS_LESS_65_141 0
-#define HID_MPS_LESS_65_142 0
-#define HID_MPS_LESS_65_143 0
-#define HID_MPS_LESS_65_144 0
-#define HID_MPS_LESS_65_145 0
-#define HID_MPS_LESS_65_146 0
-#define HID_MPS_LESS_65_147 0
-#define HID_MPS_LESS_65_148 0
-#define HID_MPS_LESS_65_149 0
-#define HID_MPS_LESS_65_150 0
-#define HID_MPS_LESS_65_151 0
-#define HID_MPS_LESS_65_152 0
-#define HID_MPS_LESS_65_153 0
-#define HID_MPS_LESS_65_154 0
-#define HID_MPS_LESS_65_155 0
-#define HID_MPS_LESS_65_156 0
-#define HID_MPS_LESS_65_157 0
-#define HID_MPS_LESS_65_158 0
-#define HID_MPS_LESS_65_159 0
-#define HID_MPS_LESS_65_160 0
-#define HID_MPS_LESS_65_161 0
-#define HID_MPS_LESS_65_162 0
-#define HID_MPS_LESS_65_163 0
-#define HID_MPS_LESS_65_164 0
-#define HID_MPS_LESS_65_165 0
-#define HID_MPS_LESS_65_166 0
-#define HID_MPS_LESS_65_167 0
-#define HID_MPS_LESS_65_168 0
-#define HID_MPS_LESS_65_169 0
-#define HID_MPS_LESS_65_170 0
-#define HID_MPS_LESS_65_171 0
-#define HID_MPS_LESS_65_172 0
-#define HID_MPS_LESS_65_173 0
-#define HID_MPS_LESS_65_174 0
-#define HID_MPS_LESS_65_175 0
-#define HID_MPS_LESS_65_176 0
-#define HID_MPS_LESS_65_177 0
-#define HID_MPS_LESS_65_178 0
-#define HID_MPS_LESS_65_179 0
-#define HID_MPS_LESS_65_180 0
-#define HID_MPS_LESS_65_181 0
-#define HID_MPS_LESS_65_182 0
-#define HID_MPS_LESS_65_183 0
-#define HID_MPS_LESS_65_184 0
-#define HID_MPS_LESS_65_185 0
-#define HID_MPS_LESS_65_186 0
-#define HID_MPS_LESS_65_187 0
-#define HID_MPS_LESS_65_188 0
-#define HID_MPS_LESS_65_189 0
-#define HID_MPS_LESS_65_190 0
-#define HID_MPS_LESS_65_191 0
-#define HID_MPS_LESS_65_192 0
-#define HID_MPS_LESS_65_193 0
-#define HID_MPS_LESS_65_194 0
-#define HID_MPS_LESS_65_195 0
-#define HID_MPS_LESS_65_196 0
-#define HID_MPS_LESS_65_197 0
-#define HID_MPS_LESS_65_198 0
-#define HID_MPS_LESS_65_199 0
-#define HID_MPS_LESS_65_200 0
-#define HID_MPS_LESS_65_201 0
-#define HID_MPS_LESS_65_202 0
-#define HID_MPS_LESS_65_203 0
-#define HID_MPS_LESS_65_204 0
-#define HID_MPS_LESS_65_205 0
-#define HID_MPS_LESS_65_206 0
-#define HID_MPS_LESS_65_207 0
-#define HID_MPS_LESS_65_208 0
-#define HID_MPS_LESS_65_209 0
-#define HID_MPS_LESS_65_210 0
-#define HID_MPS_LESS_65_211 0
-#define HID_MPS_LESS_65_212 0
-#define HID_MPS_LESS_65_213 0
-#define HID_MPS_LESS_65_214 0
-#define HID_MPS_LESS_65_215 0
-#define HID_MPS_LESS_65_216 0
-#define HID_MPS_LESS_65_217 0
-#define HID_MPS_LESS_65_218 0
-#define HID_MPS_LESS_65_219 0
-#define HID_MPS_LESS_65_220 0
-#define HID_MPS_LESS_65_221 0
-#define HID_MPS_LESS_65_222 0
-#define HID_MPS_LESS_65_223 0
-#define HID_MPS_LESS_65_224 0
-#define HID_MPS_LESS_65_225 0
-#define HID_MPS_LESS_65_226 0
-#define HID_MPS_LESS_65_227 0
-#define HID_MPS_LESS_65_228 0
-#define HID_MPS_LESS_65_229 0
-#define HID_MPS_LESS_65_230 0
-#define HID_MPS_LESS_65_231 0
-#define HID_MPS_LESS_65_232 0
-#define HID_MPS_LESS_65_233 0
-#define HID_MPS_LESS_65_234 0
-#define HID_MPS_LESS_65_235 0
-#define HID_MPS_LESS_65_236 0
-#define HID_MPS_LESS_65_237 0
-#define HID_MPS_LESS_65_238 0
-#define HID_MPS_LESS_65_239 0
-#define HID_MPS_LESS_65_240 0
-#define HID_MPS_LESS_65_241 0
-#define HID_MPS_LESS_65_242 0
-#define HID_MPS_LESS_65_243 0
-#define HID_MPS_LESS_65_244 0
-#define HID_MPS_LESS_65_245 0
-#define HID_MPS_LESS_65_246 0
-#define HID_MPS_LESS_65_247 0
-#define HID_MPS_LESS_65_248 0
-#define HID_MPS_LESS_65_249 0
-#define HID_MPS_LESS_65_250 0
-#define HID_MPS_LESS_65_251 0
-#define HID_MPS_LESS_65_252 0
-#define HID_MPS_LESS_65_253 0
-#define HID_MPS_LESS_65_254 0
-#define HID_MPS_LESS_65_255 0
-#define HID_MPS_LESS_65_256 0
-#define HID_MPS_LESS_65_257 0
-#define HID_MPS_LESS_65_258 0
-#define HID_MPS_LESS_65_259 0
-#define HID_MPS_LESS_65_260 0
-#define HID_MPS_LESS_65_261 0
-#define HID_MPS_LESS_65_262 0
-#define HID_MPS_LESS_65_263 0
-#define HID_MPS_LESS_65_264 0
-#define HID_MPS_LESS_65_265 0
-#define HID_MPS_LESS_65_266 0
-#define HID_MPS_LESS_65_267 0
-#define HID_MPS_LESS_65_268 0
-#define HID_MPS_LESS_65_269 0
-#define HID_MPS_LESS_65_270 0
-#define HID_MPS_LESS_65_271 0
-#define HID_MPS_LESS_65_272 0
-#define HID_MPS_LESS_65_273 0
-#define HID_MPS_LESS_65_274 0
-#define HID_MPS_LESS_65_275 0
-#define HID_MPS_LESS_65_276 0
-#define HID_MPS_LESS_65_277 0
-#define HID_MPS_LESS_65_278 0
-#define HID_MPS_LESS_65_279 0
-#define HID_MPS_LESS_65_280 0
-#define HID_MPS_LESS_65_281 0
-#define HID_MPS_LESS_65_282 0
-#define HID_MPS_LESS_65_283 0
-#define HID_MPS_LESS_65_284 0
-#define HID_MPS_LESS_65_285 0
-#define HID_MPS_LESS_65_286 0
-#define HID_MPS_LESS_65_287 0
-#define HID_MPS_LESS_65_288 0
-#define HID_MPS_LESS_65_289 0
-#define HID_MPS_LESS_65_290 0
-#define HID_MPS_LESS_65_291 0
-#define HID_MPS_LESS_65_292 0
-#define HID_MPS_LESS_65_293 0
-#define HID_MPS_LESS_65_294 0
-#define HID_MPS_LESS_65_295 0
-#define HID_MPS_LESS_65_296 0
-#define HID_MPS_LESS_65_297 0
-#define HID_MPS_LESS_65_298 0
-#define HID_MPS_LESS_65_299 0
-#define HID_MPS_LESS_65_300 0
-#define HID_MPS_LESS_65_301 0
-#define HID_MPS_LESS_65_302 0
-#define HID_MPS_LESS_65_303 0
-#define HID_MPS_LESS_65_304 0
-#define HID_MPS_LESS_65_305 0
-#define HID_MPS_LESS_65_306 0
-#define HID_MPS_LESS_65_307 0
-#define HID_MPS_LESS_65_308 0
-#define HID_MPS_LESS_65_309 0
-#define HID_MPS_LESS_65_310 0
-#define HID_MPS_LESS_65_311 0
-#define HID_MPS_LESS_65_312 0
-#define HID_MPS_LESS_65_313 0
-#define HID_MPS_LESS_65_314 0
-#define HID_MPS_LESS_65_315 0
-#define HID_MPS_LESS_65_316 0
-#define HID_MPS_LESS_65_317 0
-#define HID_MPS_LESS_65_318 0
-#define HID_MPS_LESS_65_319 0
-#define HID_MPS_LESS_65_320 0
-#define HID_MPS_LESS_65_321 0
-#define HID_MPS_LESS_65_322 0
-#define HID_MPS_LESS_65_323 0
-#define HID_MPS_LESS_65_324 0
-#define HID_MPS_LESS_65_325 0
-#define HID_MPS_LESS_65_326 0
-#define HID_MPS_LESS_65_327 0
-#define HID_MPS_LESS_65_328 0
-#define HID_MPS_LESS_65_329 0
-#define HID_MPS_LESS_65_330 0
-#define HID_MPS_LESS_65_331 0
-#define HID_MPS_LESS_65_332 0
-#define HID_MPS_LESS_65_333 0
-#define HID_MPS_LESS_65_334 0
-#define HID_MPS_LESS_65_335 0
-#define HID_MPS_LESS_65_336 0
-#define HID_MPS_LESS_65_337 0
-#define HID_MPS_LESS_65_338 0
-#define HID_MPS_LESS_65_339 0
-#define HID_MPS_LESS_65_340 0
-#define HID_MPS_LESS_65_341 0
-#define HID_MPS_LESS_65_342 0
-#define HID_MPS_LESS_65_343 0
-#define HID_MPS_LESS_65_344 0
-#define HID_MPS_LESS_65_345 0
-#define HID_MPS_LESS_65_346 0
-#define HID_MPS_LESS_65_347 0
-#define HID_MPS_LESS_65_348 0
-#define HID_MPS_LESS_65_349 0
-#define HID_MPS_LESS_65_350 0
-#define HID_MPS_LESS_65_351 0
-#define HID_MPS_LESS_65_352 0
-#define HID_MPS_LESS_65_353 0
-#define HID_MPS_LESS_65_354 0
-#define HID_MPS_LESS_65_355 0
-#define HID_MPS_LESS_65_356 0
-#define HID_MPS_LESS_65_357 0
-#define HID_MPS_LESS_65_358 0
-#define HID_MPS_LESS_65_359 0
-#define HID_MPS_LESS_65_360 0
-#define HID_MPS_LESS_65_361 0
-#define HID_MPS_LESS_65_362 0
-#define HID_MPS_LESS_65_363 0
-#define HID_MPS_LESS_65_364 0
-#define HID_MPS_LESS_65_365 0
-#define HID_MPS_LESS_65_366 0
-#define HID_MPS_LESS_65_367 0
-#define HID_MPS_LESS_65_368 0
-#define HID_MPS_LESS_65_369 0
-#define HID_MPS_LESS_65_370 0
-#define HID_MPS_LESS_65_371 0
-#define HID_MPS_LESS_65_372 0
-#define HID_MPS_LESS_65_373 0
-#define HID_MPS_LESS_65_374 0
-#define HID_MPS_LESS_65_375 0
-#define HID_MPS_LESS_65_376 0
-#define HID_MPS_LESS_65_377 0
-#define HID_MPS_LESS_65_378 0
-#define HID_MPS_LESS_65_379 0
-#define HID_MPS_LESS_65_380 0
-#define HID_MPS_LESS_65_381 0
-#define HID_MPS_LESS_65_382 0
-#define HID_MPS_LESS_65_383 0
-#define HID_MPS_LESS_65_384 0
-#define HID_MPS_LESS_65_385 0
-#define HID_MPS_LESS_65_386 0
-#define HID_MPS_LESS_65_387 0
-#define HID_MPS_LESS_65_388 0
-#define HID_MPS_LESS_65_389 0
-#define HID_MPS_LESS_65_390 0
-#define HID_MPS_LESS_65_391 0
-#define HID_MPS_LESS_65_392 0
-#define HID_MPS_LESS_65_393 0
-#define HID_MPS_LESS_65_394 0
-#define HID_MPS_LESS_65_395 0
-#define HID_MPS_LESS_65_396 0
-#define HID_MPS_LESS_65_397 0
-#define HID_MPS_LESS_65_398 0
-#define HID_MPS_LESS_65_399 0
-#define HID_MPS_LESS_65_400 0
-#define HID_MPS_LESS_65_401 0
-#define HID_MPS_LESS_65_402 0
-#define HID_MPS_LESS_65_403 0
-#define HID_MPS_LESS_65_404 0
-#define HID_MPS_LESS_65_405 0
-#define HID_MPS_LESS_65_406 0
-#define HID_MPS_LESS_65_407 0
-#define HID_MPS_LESS_65_408 0
-#define HID_MPS_LESS_65_409 0
-#define HID_MPS_LESS_65_410 0
-#define HID_MPS_LESS_65_411 0
-#define HID_MPS_LESS_65_412 0
-#define HID_MPS_LESS_65_413 0
-#define HID_MPS_LESS_65_414 0
-#define HID_MPS_LESS_65_415 0
-#define HID_MPS_LESS_65_416 0
-#define HID_MPS_LESS_65_417 0
-#define HID_MPS_LESS_65_418 0
-#define HID_MPS_LESS_65_419 0
-#define HID_MPS_LESS_65_420 0
-#define HID_MPS_LESS_65_421 0
-#define HID_MPS_LESS_65_422 0
-#define HID_MPS_LESS_65_423 0
-#define HID_MPS_LESS_65_424 0
-#define HID_MPS_LESS_65_425 0
-#define HID_MPS_LESS_65_426 0
-#define HID_MPS_LESS_65_427 0
-#define HID_MPS_LESS_65_428 0
-#define HID_MPS_LESS_65_429 0
-#define HID_MPS_LESS_65_430 0
-#define HID_MPS_LESS_65_431 0
-#define HID_MPS_LESS_65_432 0
-#define HID_MPS_LESS_65_433 0
-#define HID_MPS_LESS_65_434 0
-#define HID_MPS_LESS_65_435 0
-#define HID_MPS_LESS_65_436 0
-#define HID_MPS_LESS_65_437 0
-#define HID_MPS_LESS_65_438 0
-#define HID_MPS_LESS_65_439 0
-#define HID_MPS_LESS_65_440 0
-#define HID_MPS_LESS_65_441 0
-#define HID_MPS_LESS_65_442 0
-#define HID_MPS_LESS_65_443 0
-#define HID_MPS_LESS_65_444 0
-#define HID_MPS_LESS_65_445 0
-#define HID_MPS_LESS_65_446 0
-#define HID_MPS_LESS_65_447 0
-#define HID_MPS_LESS_65_448 0
-#define HID_MPS_LESS_65_449 0
-#define HID_MPS_LESS_65_450 0
-#define HID_MPS_LESS_65_451 0
-#define HID_MPS_LESS_65_452 0
-#define HID_MPS_LESS_65_453 0
-#define HID_MPS_LESS_65_454 0
-#define HID_MPS_LESS_65_455 0
-#define HID_MPS_LESS_65_456 0
-#define HID_MPS_LESS_65_457 0
-#define HID_MPS_LESS_65_458 0
-#define HID_MPS_LESS_65_459 0
-#define HID_MPS_LESS_65_460 0
-#define HID_MPS_LESS_65_461 0
-#define HID_MPS_LESS_65_462 0
-#define HID_MPS_LESS_65_463 0
-#define HID_MPS_LESS_65_464 0
-#define HID_MPS_LESS_65_465 0
-#define HID_MPS_LESS_65_466 0
-#define HID_MPS_LESS_65_467 0
-#define HID_MPS_LESS_65_468 0
-#define HID_MPS_LESS_65_469 0
-#define HID_MPS_LESS_65_470 0
-#define HID_MPS_LESS_65_471 0
-#define HID_MPS_LESS_65_472 0
-#define HID_MPS_LESS_65_473 0
-#define HID_MPS_LESS_65_474 0
-#define HID_MPS_LESS_65_475 0
-#define HID_MPS_LESS_65_476 0
-#define HID_MPS_LESS_65_477 0
-#define HID_MPS_LESS_65_478 0
-#define HID_MPS_LESS_65_479 0
-#define HID_MPS_LESS_65_480 0
-#define HID_MPS_LESS_65_481 0
-#define HID_MPS_LESS_65_482 0
-#define HID_MPS_LESS_65_483 0
-#define HID_MPS_LESS_65_484 0
-#define HID_MPS_LESS_65_485 0
-#define HID_MPS_LESS_65_486 0
-#define HID_MPS_LESS_65_487 0
-#define HID_MPS_LESS_65_488 0
-#define HID_MPS_LESS_65_489 0
-#define HID_MPS_LESS_65_490 0
-#define HID_MPS_LESS_65_491 0
-#define HID_MPS_LESS_65_492 0
-#define HID_MPS_LESS_65_493 0
-#define HID_MPS_LESS_65_494 0
-#define HID_MPS_LESS_65_495 0
-#define HID_MPS_LESS_65_496 0
-#define HID_MPS_LESS_65_497 0
-#define HID_MPS_LESS_65_498 0
-#define HID_MPS_LESS_65_499 0
-#define HID_MPS_LESS_65_500 0
-#define HID_MPS_LESS_65_501 0
-#define HID_MPS_LESS_65_502 0
-#define HID_MPS_LESS_65_503 0
-#define HID_MPS_LESS_65_504 0
-#define HID_MPS_LESS_65_505 0
-#define HID_MPS_LESS_65_506 0
-#define HID_MPS_LESS_65_507 0
-#define HID_MPS_LESS_65_508 0
-#define HID_MPS_LESS_65_509 0
-#define HID_MPS_LESS_65_510 0
-#define HID_MPS_LESS_65_511 0
-#define HID_MPS_LESS_65_512 0
-#define HID_MPS_LESS_65_513 0
-#define HID_MPS_LESS_65_514 0
-#define HID_MPS_LESS_65_515 0
-#define HID_MPS_LESS_65_516 0
-#define HID_MPS_LESS_65_517 0
-#define HID_MPS_LESS_65_518 0
-#define HID_MPS_LESS_65_519 0
-#define HID_MPS_LESS_65_520 0
-#define HID_MPS_LESS_65_521 0
-#define HID_MPS_LESS_65_522 0
-#define HID_MPS_LESS_65_523 0
-#define HID_MPS_LESS_65_524 0
-#define HID_MPS_LESS_65_525 0
-#define HID_MPS_LESS_65_526 0
-#define HID_MPS_LESS_65_527 0
-#define HID_MPS_LESS_65_528 0
-#define HID_MPS_LESS_65_529 0
-#define HID_MPS_LESS_65_530 0
-#define HID_MPS_LESS_65_531 0
-#define HID_MPS_LESS_65_532 0
-#define HID_MPS_LESS_65_533 0
-#define HID_MPS_LESS_65_534 0
-#define HID_MPS_LESS_65_535 0
-#define HID_MPS_LESS_65_536 0
-#define HID_MPS_LESS_65_537 0
-#define HID_MPS_LESS_65_538 0
-#define HID_MPS_LESS_65_539 0
-#define HID_MPS_LESS_65_540 0
-#define HID_MPS_LESS_65_541 0
-#define HID_MPS_LESS_65_542 0
-#define HID_MPS_LESS_65_543 0
-#define HID_MPS_LESS_65_544 0
-#define HID_MPS_LESS_65_545 0
-#define HID_MPS_LESS_65_546 0
-#define HID_MPS_LESS_65_547 0
-#define HID_MPS_LESS_65_548 0
-#define HID_MPS_LESS_65_549 0
-#define HID_MPS_LESS_65_550 0
-#define HID_MPS_LESS_65_551 0
-#define HID_MPS_LESS_65_552 0
-#define HID_MPS_LESS_65_553 0
-#define HID_MPS_LESS_65_554 0
-#define HID_MPS_LESS_65_555 0
-#define HID_MPS_LESS_65_556 0
-#define HID_MPS_LESS_65_557 0
-#define HID_MPS_LESS_65_558 0
-#define HID_MPS_LESS_65_559 0
-#define HID_MPS_LESS_65_560 0
-#define HID_MPS_LESS_65_561 0
-#define HID_MPS_LESS_65_562 0
-#define HID_MPS_LESS_65_563 0
-#define HID_MPS_LESS_65_564 0
-#define HID_MPS_LESS_65_565 0
-#define HID_MPS_LESS_65_566 0
-#define HID_MPS_LESS_65_567 0
-#define HID_MPS_LESS_65_568 0
-#define HID_MPS_LESS_65_569 0
-#define HID_MPS_LESS_65_570 0
-#define HID_MPS_LESS_65_571 0
-#define HID_MPS_LESS_65_572 0
-#define HID_MPS_LESS_65_573 0
-#define HID_MPS_LESS_65_574 0
-#define HID_MPS_LESS_65_575 0
-#define HID_MPS_LESS_65_576 0
-#define HID_MPS_LESS_65_577 0
-#define HID_MPS_LESS_65_578 0
-#define HID_MPS_LESS_65_579 0
-#define HID_MPS_LESS_65_580 0
-#define HID_MPS_LESS_65_581 0
-#define HID_MPS_LESS_65_582 0
-#define HID_MPS_LESS_65_583 0
-#define HID_MPS_LESS_65_584 0
-#define HID_MPS_LESS_65_585 0
-#define HID_MPS_LESS_65_586 0
-#define HID_MPS_LESS_65_587 0
-#define HID_MPS_LESS_65_588 0
-#define HID_MPS_LESS_65_589 0
-#define HID_MPS_LESS_65_590 0
-#define HID_MPS_LESS_65_591 0
-#define HID_MPS_LESS_65_592 0
-#define HID_MPS_LESS_65_593 0
-#define HID_MPS_LESS_65_594 0
-#define HID_MPS_LESS_65_595 0
-#define HID_MPS_LESS_65_596 0
-#define HID_MPS_LESS_65_597 0
-#define HID_MPS_LESS_65_598 0
-#define HID_MPS_LESS_65_599 0
-#define HID_MPS_LESS_65_600 0
-#define HID_MPS_LESS_65_601 0
-#define HID_MPS_LESS_65_602 0
-#define HID_MPS_LESS_65_603 0
-#define HID_MPS_LESS_65_604 0
-#define HID_MPS_LESS_65_605 0
-#define HID_MPS_LESS_65_606 0
-#define HID_MPS_LESS_65_607 0
-#define HID_MPS_LESS_65_608 0
-#define HID_MPS_LESS_65_609 0
-#define HID_MPS_LESS_65_610 0
-#define HID_MPS_LESS_65_611 0
-#define HID_MPS_LESS_65_612 0
-#define HID_MPS_LESS_65_613 0
-#define HID_MPS_LESS_65_614 0
-#define HID_MPS_LESS_65_615 0
-#define HID_MPS_LESS_65_616 0
-#define HID_MPS_LESS_65_617 0
-#define HID_MPS_LESS_65_618 0
-#define HID_MPS_LESS_65_619 0
-#define HID_MPS_LESS_65_620 0
-#define HID_MPS_LESS_65_621 0
-#define HID_MPS_LESS_65_622 0
-#define HID_MPS_LESS_65_623 0
-#define HID_MPS_LESS_65_624 0
-#define HID_MPS_LESS_65_625 0
-#define HID_MPS_LESS_65_626 0
-#define HID_MPS_LESS_65_627 0
-#define HID_MPS_LESS_65_628 0
-#define HID_MPS_LESS_65_629 0
-#define HID_MPS_LESS_65_630 0
-#define HID_MPS_LESS_65_631 0
-#define HID_MPS_LESS_65_632 0
-#define HID_MPS_LESS_65_633 0
-#define HID_MPS_LESS_65_634 0
-#define HID_MPS_LESS_65_635 0
-#define HID_MPS_LESS_65_636 0
-#define HID_MPS_LESS_65_637 0
-#define HID_MPS_LESS_65_638 0
-#define HID_MPS_LESS_65_639 0
-#define HID_MPS_LESS_65_640 0
-#define HID_MPS_LESS_65_641 0
-#define HID_MPS_LESS_65_642 0
-#define HID_MPS_LESS_65_643 0
-#define HID_MPS_LESS_65_644 0
-#define HID_MPS_LESS_65_645 0
-#define HID_MPS_LESS_65_646 0
-#define HID_MPS_LESS_65_647 0
-#define HID_MPS_LESS_65_648 0
-#define HID_MPS_LESS_65_649 0
-#define HID_MPS_LESS_65_650 0
-#define HID_MPS_LESS_65_651 0
-#define HID_MPS_LESS_65_652 0
-#define HID_MPS_LESS_65_653 0
-#define HID_MPS_LESS_65_654 0
-#define HID_MPS_LESS_65_655 0
-#define HID_MPS_LESS_65_656 0
-#define HID_MPS_LESS_65_657 0
-#define HID_MPS_LESS_65_658 0
-#define HID_MPS_LESS_65_659 0
-#define HID_MPS_LESS_65_660 0
-#define HID_MPS_LESS_65_661 0
-#define HID_MPS_LESS_65_662 0
-#define HID_MPS_LESS_65_663 0
-#define HID_MPS_LESS_65_664 0
-#define HID_MPS_LESS_65_665 0
-#define HID_MPS_LESS_65_666 0
-#define HID_MPS_LESS_65_667 0
-#define HID_MPS_LESS_65_668 0
-#define HID_MPS_LESS_65_669 0
-#define HID_MPS_LESS_65_670 0
-#define HID_MPS_LESS_65_671 0
-#define HID_MPS_LESS_65_672 0
-#define HID_MPS_LESS_65_673 0
-#define HID_MPS_LESS_65_674 0
-#define HID_MPS_LESS_65_675 0
-#define HID_MPS_LESS_65_676 0
-#define HID_MPS_LESS_65_677 0
-#define HID_MPS_LESS_65_678 0
-#define HID_MPS_LESS_65_679 0
-#define HID_MPS_LESS_65_680 0
-#define HID_MPS_LESS_65_681 0
-#define HID_MPS_LESS_65_682 0
-#define HID_MPS_LESS_65_683 0
-#define HID_MPS_LESS_65_684 0
-#define HID_MPS_LESS_65_685 0
-#define HID_MPS_LESS_65_686 0
-#define HID_MPS_LESS_65_687 0
-#define HID_MPS_LESS_65_688 0
-#define HID_MPS_LESS_65_689 0
-#define HID_MPS_LESS_65_690 0
-#define HID_MPS_LESS_65_691 0
-#define HID_MPS_LESS_65_692 0
-#define HID_MPS_LESS_65_693 0
-#define HID_MPS_LESS_65_694 0
-#define HID_MPS_LESS_65_695 0
-#define HID_MPS_LESS_65_696 0
-#define HID_MPS_LESS_65_697 0
-#define HID_MPS_LESS_65_698 0
-#define HID_MPS_LESS_65_699 0
-#define HID_MPS_LESS_65_700 0
-#define HID_MPS_LESS_65_701 0
-#define HID_MPS_LESS_65_702 0
-#define HID_MPS_LESS_65_703 0
-#define HID_MPS_LESS_65_704 0
-#define HID_MPS_LESS_65_705 0
-#define HID_MPS_LESS_65_706 0
-#define HID_MPS_LESS_65_707 0
-#define HID_MPS_LESS_65_708 0
-#define HID_MPS_LESS_65_709 0
-#define HID_MPS_LESS_65_710 0
-#define HID_MPS_LESS_65_711 0
-#define HID_MPS_LESS_65_712 0
-#define HID_MPS_LESS_65_713 0
-#define HID_MPS_LESS_65_714 0
-#define HID_MPS_LESS_65_715 0
-#define HID_MPS_LESS_65_716 0
-#define HID_MPS_LESS_65_717 0
-#define HID_MPS_LESS_65_718 0
-#define HID_MPS_LESS_65_719 0
-#define HID_MPS_LESS_65_720 0
-#define HID_MPS_LESS_65_721 0
-#define HID_MPS_LESS_65_722 0
-#define HID_MPS_LESS_65_723 0
-#define HID_MPS_LESS_65_724 0
-#define HID_MPS_LESS_65_725 0
-#define HID_MPS_LESS_65_726 0
-#define HID_MPS_LESS_65_727 0
-#define HID_MPS_LESS_65_728 0
-#define HID_MPS_LESS_65_729 0
-#define HID_MPS_LESS_65_730 0
-#define HID_MPS_LESS_65_731 0
-#define HID_MPS_LESS_65_732 0
-#define HID_MPS_LESS_65_733 0
-#define HID_MPS_LESS_65_734 0
-#define HID_MPS_LESS_65_735 0
-#define HID_MPS_LESS_65_736 0
-#define HID_MPS_LESS_65_737 0
-#define HID_MPS_LESS_65_738 0
-#define HID_MPS_LESS_65_739 0
-#define HID_MPS_LESS_65_740 0
-#define HID_MPS_LESS_65_741 0
-#define HID_MPS_LESS_65_742 0
-#define HID_MPS_LESS_65_743 0
-#define HID_MPS_LESS_65_744 0
-#define HID_MPS_LESS_65_745 0
-#define HID_MPS_LESS_65_746 0
-#define HID_MPS_LESS_65_747 0
-#define HID_MPS_LESS_65_748 0
-#define HID_MPS_LESS_65_749 0
-#define HID_MPS_LESS_65_750 0
-#define HID_MPS_LESS_65_751 0
-#define HID_MPS_LESS_65_752 0
-#define HID_MPS_LESS_65_753 0
-#define HID_MPS_LESS_65_754 0
-#define HID_MPS_LESS_65_755 0
-#define HID_MPS_LESS_65_756 0
-#define HID_MPS_LESS_65_757 0
-#define HID_MPS_LESS_65_758 0
-#define HID_MPS_LESS_65_759 0
-#define HID_MPS_LESS_65_760 0
-#define HID_MPS_LESS_65_761 0
-#define HID_MPS_LESS_65_762 0
-#define HID_MPS_LESS_65_763 0
-#define HID_MPS_LESS_65_764 0
-#define HID_MPS_LESS_65_765 0
-#define HID_MPS_LESS_65_766 0
-#define HID_MPS_LESS_65_767 0
-#define HID_MPS_LESS_65_768 0
-#define HID_MPS_LESS_65_769 0
-#define HID_MPS_LESS_65_770 0
-#define HID_MPS_LESS_65_771 0
-#define HID_MPS_LESS_65_772 0
-#define HID_MPS_LESS_65_773 0
-#define HID_MPS_LESS_65_774 0
-#define HID_MPS_LESS_65_775 0
-#define HID_MPS_LESS_65_776 0
-#define HID_MPS_LESS_65_777 0
-#define HID_MPS_LESS_65_778 0
-#define HID_MPS_LESS_65_779 0
-#define HID_MPS_LESS_65_780 0
-#define HID_MPS_LESS_65_781 0
-#define HID_MPS_LESS_65_782 0
-#define HID_MPS_LESS_65_783 0
-#define HID_MPS_LESS_65_784 0
-#define HID_MPS_LESS_65_785 0
-#define HID_MPS_LESS_65_786 0
-#define HID_MPS_LESS_65_787 0
-#define HID_MPS_LESS_65_788 0
-#define HID_MPS_LESS_65_789 0
-#define HID_MPS_LESS_65_790 0
-#define HID_MPS_LESS_65_791 0
-#define HID_MPS_LESS_65_792 0
-#define HID_MPS_LESS_65_793 0
-#define HID_MPS_LESS_65_794 0
-#define HID_MPS_LESS_65_795 0
-#define HID_MPS_LESS_65_796 0
-#define HID_MPS_LESS_65_797 0
-#define HID_MPS_LESS_65_798 0
-#define HID_MPS_LESS_65_799 0
-#define HID_MPS_LESS_65_800 0
-#define HID_MPS_LESS_65_801 0
-#define HID_MPS_LESS_65_802 0
-#define HID_MPS_LESS_65_803 0
-#define HID_MPS_LESS_65_804 0
-#define HID_MPS_LESS_65_805 0
-#define HID_MPS_LESS_65_806 0
-#define HID_MPS_LESS_65_807 0
-#define HID_MPS_LESS_65_808 0
-#define HID_MPS_LESS_65_809 0
-#define HID_MPS_LESS_65_810 0
-#define HID_MPS_LESS_65_811 0
-#define HID_MPS_LESS_65_812 0
-#define HID_MPS_LESS_65_813 0
-#define HID_MPS_LESS_65_814 0
-#define HID_MPS_LESS_65_815 0
-#define HID_MPS_LESS_65_816 0
-#define HID_MPS_LESS_65_817 0
-#define HID_MPS_LESS_65_818 0
-#define HID_MPS_LESS_65_819 0
-#define HID_MPS_LESS_65_820 0
-#define HID_MPS_LESS_65_821 0
-#define HID_MPS_LESS_65_822 0
-#define HID_MPS_LESS_65_823 0
-#define HID_MPS_LESS_65_824 0
-#define HID_MPS_LESS_65_825 0
-#define HID_MPS_LESS_65_826 0
-#define HID_MPS_LESS_65_827 0
-#define HID_MPS_LESS_65_828 0
-#define HID_MPS_LESS_65_829 0
-#define HID_MPS_LESS_65_830 0
-#define HID_MPS_LESS_65_831 0
-#define HID_MPS_LESS_65_832 0
-#define HID_MPS_LESS_65_833 0
-#define HID_MPS_LESS_65_834 0
-#define HID_MPS_LESS_65_835 0
-#define HID_MPS_LESS_65_836 0
-#define HID_MPS_LESS_65_837 0
-#define HID_MPS_LESS_65_838 0
-#define HID_MPS_LESS_65_839 0
-#define HID_MPS_LESS_65_840 0
-#define HID_MPS_LESS_65_841 0
-#define HID_MPS_LESS_65_842 0
-#define HID_MPS_LESS_65_843 0
-#define HID_MPS_LESS_65_844 0
-#define HID_MPS_LESS_65_845 0
-#define HID_MPS_LESS_65_846 0
-#define HID_MPS_LESS_65_847 0
-#define HID_MPS_LESS_65_848 0
-#define HID_MPS_LESS_65_849 0
-#define HID_MPS_LESS_65_850 0
-#define HID_MPS_LESS_65_851 0
-#define HID_MPS_LESS_65_852 0
-#define HID_MPS_LESS_65_853 0
-#define HID_MPS_LESS_65_854 0
-#define HID_MPS_LESS_65_855 0
-#define HID_MPS_LESS_65_856 0
-#define HID_MPS_LESS_65_857 0
-#define HID_MPS_LESS_65_858 0
-#define HID_MPS_LESS_65_859 0
-#define HID_MPS_LESS_65_860 0
-#define HID_MPS_LESS_65_861 0
-#define HID_MPS_LESS_65_862 0
-#define HID_MPS_LESS_65_863 0
-#define HID_MPS_LESS_65_864 0
-#define HID_MPS_LESS_65_865 0
-#define HID_MPS_LESS_65_866 0
-#define HID_MPS_LESS_65_867 0
-#define HID_MPS_LESS_65_868 0
-#define HID_MPS_LESS_65_869 0
-#define HID_MPS_LESS_65_870 0
-#define HID_MPS_LESS_65_871 0
-#define HID_MPS_LESS_65_872 0
-#define HID_MPS_LESS_65_873 0
-#define HID_MPS_LESS_65_874 0
-#define HID_MPS_LESS_65_875 0
-#define HID_MPS_LESS_65_876 0
-#define HID_MPS_LESS_65_877 0
-#define HID_MPS_LESS_65_878 0
-#define HID_MPS_LESS_65_879 0
-#define HID_MPS_LESS_65_880 0
-#define HID_MPS_LESS_65_881 0
-#define HID_MPS_LESS_65_882 0
-#define HID_MPS_LESS_65_883 0
-#define HID_MPS_LESS_65_884 0
-#define HID_MPS_LESS_65_885 0
-#define HID_MPS_LESS_65_886 0
-#define HID_MPS_LESS_65_887 0
-#define HID_MPS_LESS_65_888 0
-#define HID_MPS_LESS_65_889 0
-#define HID_MPS_LESS_65_890 0
-#define HID_MPS_LESS_65_891 0
-#define HID_MPS_LESS_65_892 0
-#define HID_MPS_LESS_65_893 0
-#define HID_MPS_LESS_65_894 0
-#define HID_MPS_LESS_65_895 0
-#define HID_MPS_LESS_65_896 0
-#define HID_MPS_LESS_65_897 0
-#define HID_MPS_LESS_65_898 0
-#define HID_MPS_LESS_65_899 0
-#define HID_MPS_LESS_65_900 0
-#define HID_MPS_LESS_65_901 0
-#define HID_MPS_LESS_65_902 0
-#define HID_MPS_LESS_65_903 0
-#define HID_MPS_LESS_65_904 0
-#define HID_MPS_LESS_65_905 0
-#define HID_MPS_LESS_65_906 0
-#define HID_MPS_LESS_65_907 0
-#define HID_MPS_LESS_65_908 0
-#define HID_MPS_LESS_65_909 0
-#define HID_MPS_LESS_65_910 0
-#define HID_MPS_LESS_65_911 0
-#define HID_MPS_LESS_65_912 0
-#define HID_MPS_LESS_65_913 0
-#define HID_MPS_LESS_65_914 0
-#define HID_MPS_LESS_65_915 0
-#define HID_MPS_LESS_65_916 0
-#define HID_MPS_LESS_65_917 0
-#define HID_MPS_LESS_65_918 0
-#define HID_MPS_LESS_65_919 0
-#define HID_MPS_LESS_65_920 0
-#define HID_MPS_LESS_65_921 0
-#define HID_MPS_LESS_65_922 0
-#define HID_MPS_LESS_65_923 0
-#define HID_MPS_LESS_65_924 0
-#define HID_MPS_LESS_65_925 0
-#define HID_MPS_LESS_65_926 0
-#define HID_MPS_LESS_65_927 0
-#define HID_MPS_LESS_65_928 0
-#define HID_MPS_LESS_65_929 0
-#define HID_MPS_LESS_65_930 0
-#define HID_MPS_LESS_65_931 0
-#define HID_MPS_LESS_65_932 0
-#define HID_MPS_LESS_65_933 0
-#define HID_MPS_LESS_65_934 0
-#define HID_MPS_LESS_65_935 0
-#define HID_MPS_LESS_65_936 0
-#define HID_MPS_LESS_65_937 0
-#define HID_MPS_LESS_65_938 0
-#define HID_MPS_LESS_65_939 0
-#define HID_MPS_LESS_65_940 0
-#define HID_MPS_LESS_65_941 0
-#define HID_MPS_LESS_65_942 0
-#define HID_MPS_LESS_65_943 0
-#define HID_MPS_LESS_65_944 0
-#define HID_MPS_LESS_65_945 0
-#define HID_MPS_LESS_65_946 0
-#define HID_MPS_LESS_65_947 0
-#define HID_MPS_LESS_65_948 0
-#define HID_MPS_LESS_65_949 0
-#define HID_MPS_LESS_65_950 0
-#define HID_MPS_LESS_65_951 0
-#define HID_MPS_LESS_65_952 0
-#define HID_MPS_LESS_65_953 0
-#define HID_MPS_LESS_65_954 0
-#define HID_MPS_LESS_65_955 0
-#define HID_MPS_LESS_65_956 0
-#define HID_MPS_LESS_65_957 0
-#define HID_MPS_LESS_65_958 0
-#define HID_MPS_LESS_65_959 0
-#define HID_MPS_LESS_65_960 0
-#define HID_MPS_LESS_65_961 0
-#define HID_MPS_LESS_65_962 0
-#define HID_MPS_LESS_65_963 0
-#define HID_MPS_LESS_65_964 0
-#define HID_MPS_LESS_65_965 0
-#define HID_MPS_LESS_65_966 0
-#define HID_MPS_LESS_65_967 0
-#define HID_MPS_LESS_65_968 0
-#define HID_MPS_LESS_65_969 0
-#define HID_MPS_LESS_65_970 0
-#define HID_MPS_LESS_65_971 0
-#define HID_MPS_LESS_65_972 0
-#define HID_MPS_LESS_65_973 0
-#define HID_MPS_LESS_65_974 0
-#define HID_MPS_LESS_65_975 0
-#define HID_MPS_LESS_65_976 0
-#define HID_MPS_LESS_65_977 0
-#define HID_MPS_LESS_65_978 0
-#define HID_MPS_LESS_65_979 0
-#define HID_MPS_LESS_65_980 0
-#define HID_MPS_LESS_65_981 0
-#define HID_MPS_LESS_65_982 0
-#define HID_MPS_LESS_65_983 0
-#define HID_MPS_LESS_65_984 0
-#define HID_MPS_LESS_65_985 0
-#define HID_MPS_LESS_65_986 0
-#define HID_MPS_LESS_65_987 0
-#define HID_MPS_LESS_65_988 0
-#define HID_MPS_LESS_65_989 0
-#define HID_MPS_LESS_65_990 0
-#define HID_MPS_LESS_65_991 0
-#define HID_MPS_LESS_65_992 0
-#define HID_MPS_LESS_65_993 0
-#define HID_MPS_LESS_65_994 0
-#define HID_MPS_LESS_65_995 0
-#define HID_MPS_LESS_65_996 0
-#define HID_MPS_LESS_65_997 0
-#define HID_MPS_LESS_65_998 0
-#define HID_MPS_LESS_65_999 0
-#define HID_MPS_LESS_65_1000 0
-#define HID_MPS_LESS_65_1001 0
-#define HID_MPS_LESS_65_1002 0
-#define HID_MPS_LESS_65_1003 0
-#define HID_MPS_LESS_65_1004 0
-#define HID_MPS_LESS_65_1005 0
-#define HID_MPS_LESS_65_1006 0
-#define HID_MPS_LESS_65_1007 0
-#define HID_MPS_LESS_65_1008 0
-#define HID_MPS_LESS_65_1009 0
-#define HID_MPS_LESS_65_1010 0
-#define HID_MPS_LESS_65_1011 0
-#define HID_MPS_LESS_65_1012 0
-#define HID_MPS_LESS_65_1013 0
-#define HID_MPS_LESS_65_1014 0
-#define HID_MPS_LESS_65_1015 0
-#define HID_MPS_LESS_65_1016 0
-#define HID_MPS_LESS_65_1017 0
-#define HID_MPS_LESS_65_1018 0
-#define HID_MPS_LESS_65_1019 0
-#define HID_MPS_LESS_65_1020 0
-#define HID_MPS_LESS_65_1021 0
-#define HID_MPS_LESS_65_1022 0
-#define HID_MPS_LESS_65_1023 0
-#define HID_MPS_LESS_65_1024 0
#define HID_MPS_LESS_65(x) UTIL_PRIMITIVE_CAT(HID_MPS_LESS_65_, x)
@@ -1052,8 +92,8 @@
* configure an alternate interface.
*/
#define HID_ALL_MPS_LESS_65(n) \
- UTIL_AND(HID_MPS_LESS_65(DT_INST_PROP(n, out_report_size)), \
- HID_MPS_LESS_65(DT_INST_PROP(n, in_report_size)))
+ COND_CODE_1(HID_MPS_LESS_65(DT_INST_PROP_OR(n, out_report_size, 0)), \
+ (HID_MPS_LESS_65(DT_INST_PROP(n, in_report_size))), (0))
/* Get IN endpoint polling rate based on the desired speed. */
#define HID_IN_EP_INTERVAL(n, hs) \
@@ -1113,7 +153,7 @@
*/
#define HID_OUT_EP_MPS(n, alt) \
COND_CODE_1(alt, \
- (sys_cpu_to_le16(DT_INST_PROP(n, out_report_size))), \
+ (sys_cpu_to_le16(USB_TPL_TO_MPS(DT_INST_PROP(n, out_report_size)))), \
(sys_cpu_to_le16(MIN(DT_INST_PROP(n, out_report_size), 64U))))
/*
@@ -1122,7 +162,7 @@
*/
#define HID_IN_EP_MPS(n, alt) \
COND_CODE_1(alt, \
- (sys_cpu_to_le16(DT_INST_PROP(n, in_report_size))), \
+ (sys_cpu_to_le16(USB_TPL_TO_MPS(DT_INST_PROP(n, in_report_size)))), \
(sys_cpu_to_le16(MIN(DT_INST_PROP(n, in_report_size), 64U))))
#define HID_OUT_EP_DEFINE(n, hs, alt) \
@@ -1166,4 +206,10 @@
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, out_report_size), \
(&hid_buf_pool_out_##n), (NULL))
+#define HID_VERIFY_REPORT_SIZES(n) \
+ BUILD_ASSERT(USB_TPL_IS_VALID(DT_INST_PROP_OR(n, out_report_size, 0)), \
+ "out-report-size must be valid Total Packet Length"); \
+ BUILD_ASSERT(USB_TPL_IS_VALID(DT_INST_PROP_OR(n, in_report_size, 0)), \
+ "in-report-size must be valid Total Packet Length");
+
#endif /* ZEPHYR_USB_DEVICE_CLASS_HID_MACROS_H_ */
diff --git a/subsys/usb/device_next/class/usbd_uac2_macros.h b/subsys/usb/device_next/class/usbd_uac2_macros.h
index 5871621..7182e8e 100644
--- a/subsys/usb/device_next/class/usbd_uac2_macros.h
+++ b/subsys/usb/device_next/class/usbd_uac2_macros.h
@@ -464,7 +464,7 @@
USB_DESC_ENDPOINT, /* bDescriptorType */ \
FIRST_IN_EP_ADDR, /* bEndpointAddress */ \
USB_EP_TYPE_INTERRUPT, /* bmAttributes */ \
- 0x06, /* wMaxPacketSize */ \
+ U16_LE(0x06), /* wMaxPacketSize */ \
0x01, /* bInterval */ \
#define AC_ENDPOINT_DESCRIPTOR_ARRAY(node) \
diff --git a/subsys/usb/device_next/usbd_ch9.c b/subsys/usb/device_next/usbd_ch9.c
index d3eebca..45775e8 100644
--- a/subsys/usb/device_next/usbd_ch9.c
+++ b/subsys/usb/device_next/usbd_ch9.c
@@ -19,6 +19,7 @@
#include "usbd_class.h"
#include "usbd_class_api.h"
#include "usbd_interface.h"
+#include "usbd_msg.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(usbd_ch9, CONFIG_USBD_LOG_LEVEL);
@@ -171,6 +172,10 @@
uds_ctx->ch9_data.state = USBD_STATE_CONFIGURED;
}
+ if (ret == 0) {
+ usbd_msg_pub_simple(uds_ctx, USBD_MSG_CONFIGURATION, setup->wValue);
+ }
+
return ret;
}
diff --git a/subsys/usb/device_next/usbd_endpoint.c b/subsys/usb/device_next/usbd_endpoint.c
index 5d49e0d..1d41f4c 100644
--- a/subsys/usb/device_next/usbd_endpoint.c
+++ b/subsys/usb/device_next/usbd_endpoint.c
@@ -24,7 +24,7 @@
int ret;
ret = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize), ed->bInterval);
if (ret == 0) {
usbd_ep_bm_set(ep_bm, ed->bEndpointAddress);
}
diff --git a/subsys/usb/device_next/usbd_init.c b/subsys/usb/device_next/usbd_init.c
index 69de723..551dc32 100644
--- a/subsys/usb/device_next/usbd_init.c
+++ b/subsys/usb/device_next/usbd_init.c
@@ -28,7 +28,7 @@
int ret = -ENODEV;
for (unsigned int idx = 1; idx < 16U; idx++) {
- uint16_t mps = ed->wMaxPacketSize;
+ uint16_t mps = sys_le16_to_cpu(ed->wMaxPacketSize);
uint8_t ep;
if (USB_EP_DIR_IS_IN(ed->bEndpointAddress)) {
@@ -50,7 +50,7 @@
if (ret == 0) {
LOG_DBG("ep 0x%02x -> 0x%02x", ed->bEndpointAddress, ep);
ed->bEndpointAddress = ep;
- ed->wMaxPacketSize = mps;
+ ed->wMaxPacketSize = sys_cpu_to_le16(mps);
usbd_ep_bm_set(class_ep_bm, ed->bEndpointAddress);
usbd_ep_bm_set(config_ep_bm, ed->bEndpointAddress);
@@ -166,8 +166,10 @@
return ret;
}
- LOG_INF("\tep 0x%02x mps %u interface ep-bm 0x%08x",
- ed->bEndpointAddress, ed->wMaxPacketSize, class_ep_bm);
+ LOG_INF("\tep 0x%02x mps 0x%04x interface ep-bm 0x%08x",
+ ed->bEndpointAddress,
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ class_ep_bm);
}
dhp++;
diff --git a/subsys/zbus/zbus.c b/subsys/zbus/zbus.c
index 174d6ad..149c22e 100644
--- a/subsys/zbus/zbus.c
+++ b/subsys/zbus/zbus.c
@@ -101,7 +101,7 @@
return -ENOMEM;
}
- net_buf_put(obs->message_fifo, cloned_buf);
+ k_fifo_put(obs->message_fifo, cloned_buf);
break;
}
@@ -464,7 +464,7 @@
_ZBUS_ASSERT(chan != NULL, "chan is required");
_ZBUS_ASSERT(msg != NULL, "msg is required");
- struct net_buf *buf = net_buf_get(sub->message_fifo, timeout);
+ struct net_buf *buf = k_fifo_get(sub->message_fifo, timeout);
if (buf == NULL) {
return -ENOMSG;
diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
index c8da699..fe99dbd 100644
--- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
+++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
@@ -27,8 +27,8 @@
#elif defined(CONFIG_SOC_SERIES_NRF54LX)
/* For nRF54L Series, use SWI00-02 interrupt lines. */
#define _ISR_OFFSET SWI00_IRQn
-#elif defined(CONFIG_SOC_SERIES_NRF54HX)
-/* For nRF54H Series, use BELLBOARD_0-2 interrupt lines. */
+#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X)
+/* For nRF54H and nRF92 Series, use BELLBOARD_0-2 interrupt lines. */
#define _ISR_OFFSET BELLBOARD_0_IRQn
#else
/* For other nRF targets, use TIMER0-2 interrupt lines. */
@@ -144,7 +144,7 @@
void nrfx_power_clock_irq_handler(void);
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
#define POWER_CLOCK_IRQ_NUM POWER_CLOCK_IRQn
-#elif defined(CONFIG_SOC_SERIES_NRF54HX)
+#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X)
#define POWER_CLOCK_IRQ_NUM -1 /* not needed */
#else
#define POWER_CLOCK_IRQ_NUM CLOCK_POWER_IRQn
@@ -154,7 +154,8 @@
void timer0_nrf_isr(void);
#define TIMER_IRQ_HANDLER timer0_nrf_isr
#define TIMER_IRQ_NUM TIMER0_IRQn
-#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX)
+#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) || \
+ defined(CONFIG_SOC_SERIES_NRF92X)
void nrfx_grtc_irq_handler(void);
#define TIMER_IRQ_HANDLER nrfx_grtc_irq_handler
#define TIMER_IRQ_NUM GRTC_0_IRQn
diff --git a/tests/bluetooth/audio/bap_base/Kconfig b/tests/bluetooth/audio/bap_base/Kconfig
new file mode 100644
index 0000000..04d45e7
--- /dev/null
+++ b/tests/bluetooth/audio/bap_base/Kconfig
@@ -0,0 +1,14 @@
+# Temporary override
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BT_BAP_BASE
+ # Override until someone fixes the UT build system
+ bool
+ default y
+
+# Include Zephyr's Kconfig.
+source "Kconfig.zephyr"
diff --git a/tests/bluetooth/audio/cap_commander/Kconfig b/tests/bluetooth/audio/cap_commander/Kconfig
new file mode 100644
index 0000000..1493bd1
--- /dev/null
+++ b/tests/bluetooth/audio/cap_commander/Kconfig
@@ -0,0 +1,14 @@
+# Temporary override
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BT_BAP_STREAM
+ # Override until someone fixes the UT build system
+ bool
+ default y
+
+# Include Zephyr's Kconfig.
+source "Kconfig.zephyr"
diff --git a/tests/bluetooth/controller/common/src/helper_util.c b/tests/bluetooth/controller/common/src/helper_util.c
index d89126c7..6d05630 100644
--- a/tests/bluetooth/controller/common/src/helper_util.c
+++ b/tests/bluetooth/controller/common/src/helper_util.c
@@ -389,8 +389,9 @@
* return the current event counter value (i.e. -1);
* otherwise return the next event counter value
*/
- if (*evt_active)
+ if (*evt_active) {
event_counter--;
+ }
return event_counter;
}
diff --git a/tests/bluetooth/hci_uart_async/src/test_hci_uart_async.c b/tests/bluetooth/hci_uart_async/src/test_hci_uart_async.c
index 69b35ff..8ee60a6 100644
--- a/tests/bluetooth/hci_uart_async/src/test_hci_uart_async.c
+++ b/tests/bluetooth/hci_uart_async/src/test_hci_uart_async.c
@@ -106,7 +106,7 @@
LOG_HEXDUMP_DBG(buf->data, buf->len, "buf");
__ASSERT_NO_MSG(buf);
- net_buf_put(&drv_send_fifo, buf);
+ k_fifo_put(&drv_send_fifo, buf);
return 0;
}
@@ -213,7 +213,7 @@
for (uint16_t i = 0; i < HCI_NORMAL_CMD_BUF_COUNT; i++) {
/* The mock controller processes a command. */
{
- struct net_buf *buf = net_buf_get(&drv_send_fifo, TIMEOUT_PRESUME_STUCK);
+ struct net_buf *buf = k_fifo_get(&drv_send_fifo, TIMEOUT_PRESUME_STUCK);
zassert_not_null(buf);
zassert_equal(buf->len, sizeof(h4_msg_cmd_dummy1) - 1, "Wrong length");
@@ -241,7 +241,7 @@
for (uint16_t i = 0; i < TEST_PARAM_HOST_COMPLETE_COUNT; i++) {
/* The mock controller processes a 'HCI Host Number of Completed Packets'. */
{
- struct net_buf *buf = net_buf_get(&drv_send_fifo, TIMEOUT_PRESUME_STUCK);
+ struct net_buf *buf = k_fifo_get(&drv_send_fifo, TIMEOUT_PRESUME_STUCK);
zassert_not_null(buf);
zassert_equal(buf->len, sizeof(h4_msg_cmd_host_num_complete) - 1,
diff --git a/tests/bluetooth/host/id/mocks/scan.c b/tests/bluetooth/host/id/mocks/scan.c
index bc91e86..d9921e6 100644
--- a/tests/bluetooth/host/id/mocks/scan.c
+++ b/tests/bluetooth/host/id/mocks/scan.c
@@ -9,3 +9,4 @@
#include <mocks/scan.h>
DEFINE_FAKE_VALUE_FUNC(int, bt_le_scan_set_enable, uint8_t);
+DEFINE_FAKE_VALUE_FUNC(bool, bt_le_scan_active_scanner_running);
diff --git a/tests/bluetooth/host/id/mocks/scan.h b/tests/bluetooth/host/id/mocks/scan.h
index 04fae90..a54d43b 100644
--- a/tests/bluetooth/host/id/mocks/scan.h
+++ b/tests/bluetooth/host/id/mocks/scan.h
@@ -11,3 +11,4 @@
#define SCAN_FFF_FAKES_LIST(FAKE) FAKE(bt_le_scan_set_enable)
DECLARE_FAKE_VALUE_FUNC(int, bt_le_scan_set_enable, uint8_t);
+DECLARE_FAKE_VALUE_FUNC(bool, bt_le_scan_active_scanner_running);
diff --git a/tests/bluetooth/qualification/.editorconfig b/tests/bluetooth/qualification/.editorconfig
new file mode 100644
index 0000000..40957fa
--- /dev/null
+++ b/tests/bluetooth/qualification/.editorconfig
@@ -0,0 +1,2 @@
+[*.{pts}]
+end_of_line = crlf
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833.pts
index c9256dc..79a5216 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833.pts
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833.pts
@@ -1,1079 +1,1079 @@
-<?xml version="1.0" encoding="utf-8"?>
-<project>
- <qdid>187777</qdid>
- <name>Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833</name>
- <pics>
- <profile>
- <name>SUM ICS</name>
- <item>
- <table>21</table>
- <row>21</row>
- </item>
- <item>
- <table>51</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>PROD</name>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>LL</name>
- <item>
- <table>9</table>
- <row>43</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>3a</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>10</row>
- </item>
- <item>
- <table>3</table>
- <row>11</row>
- </item>
- <item>
- <table>3</table>
- <row>13</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>4a</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>6a</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>10a</row>
- </item>
- <item>
- <table>6</table>
- <row>10b</row>
- </item>
- <item>
- <table>6</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>23</row>
- </item>
- <item>
- <table>6</table>
- <row>23a</row>
- </item>
- <item>
- <table>6</table>
- <row>24</row>
- </item>
- <item>
- <table>6</table>
- <row>25</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>4a</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>10</row>
- </item>
- <item>
- <table>7</table>
- <row>10a</row>
- </item>
- <item>
- <table>7</table>
- <row>10b</row>
- </item>
- <item>
- <table>7</table>
- <row>11</row>
- </item>
- <item>
- <table>7</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>13</row>
- </item>
- <item>
- <table>7</table>
- <row>14</row>
- </item>
- <item>
- <table>7</table>
- <row>15</row>
- </item>
- <item>
- <table>7</table>
- <row>16</row>
- </item>
- <item>
- <table>7</table>
- <row>19</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>20</row>
- </item>
- <item>
- <table>7</table>
- <row>21</row>
- </item>
- <item>
- <table>7</table>
- <row>22</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>23a</row>
- </item>
- <item>
- <table>7</table>
- <row>24</row>
- </item>
- <item>
- <table>7</table>
- <row>25</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>4a</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>10</row>
- </item>
- <item>
- <table>9</table>
- <row>12</row>
- </item>
- <item>
- <table>9</table>
- <row>13</row>
- </item>
- <item>
- <table>9</table>
- <row>14</row>
- </item>
- <item>
- <table>9</table>
- <row>15</row>
- </item>
- <item>
- <table>9</table>
- <row>16</row>
- </item>
- <item>
- <table>9</table>
- <row>17</row>
- </item>
- <item>
- <table>9</table>
- <row>18</row>
- </item>
- <item>
- <table>9</table>
- <row>19</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>9</table>
- <row>20</row>
- </item>
- <item>
- <table>9</table>
- <row>21</row>
- </item>
- <item>
- <table>9</table>
- <row>22</row>
- </item>
- <item>
- <table>9</table>
- <row>23</row>
- </item>
- <item>
- <table>9</table>
- <row>24</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>6a</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>41</row>
- </item>
- <item>
- <table>9</table>
- <row>42</row>
- </item>
- <item>
- <table>3</table>
- <row>12a</row>
- </item>
- <item>
- <table>3</table>
- <row>1a</row>
- </item>
- <item>
- <table>3</table>
- <row>4b</row>
- </item>
- <item>
- <table>3</table>
- <row>5a</row>
- </item>
- </profile>
- <profile>
- <name>4.0HCI</name>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>12</row>
- </item>
- <item>
- <table>10</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>14</row>
- </item>
- <item>
- <table>10</table>
- <row>15</row>
- </item>
- <item>
- <table>10</table>
- <row>16</row>
- </item>
- <item>
- <table>10</table>
- <row>18</row>
- </item>
- <item>
- <table>10</table>
- <row>19</row>
- </item>
- <item>
- <table>10</table>
- <row>20</row>
- </item>
- <item>
- <table>10</table>
- <row>21</row>
- </item>
- <item>
- <table>10</table>
- <row>22</row>
- </item>
- <item>
- <table>10</table>
- <row>23</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>13</table>
- <row>12</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>17</row>
- </item>
- <item>
- <table>14</table>
- <row>18</row>
- </item>
- <item>
- <table>14</table>
- <row>19</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>20</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>32</row>
- </item>
- <item>
- <table>16</table>
- <row>33</row>
- </item>
- <item>
- <table>16</table>
- <row>34</row>
- </item>
- <item>
- <table>16</table>
- <row>35</row>
- </item>
- <item>
- <table>16</table>
- <row>36</row>
- </item>
- <item>
- <table>16</table>
- <row>39</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>12</row>
- </item>
- <item>
- <table>17</table>
- <row>13</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>1a</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>13</row>
- </item>
- <item>
- <table>5</table>
- <row>14</row>
- </item>
- <item>
- <table>5</table>
- <row>15</row>
- </item>
- <item>
- <table>5</table>
- <row>16</row>
- </item>
- <item>
- <table>5</table>
- <row>17</row>
- </item>
- <item>
- <table>5</table>
- <row>27</row>
- </item>
- <item>
- <table>5</table>
- <row>28</row>
- </item>
- <item>
- <table>5</table>
- <row>29</row>
- </item>
- <item>
- <table>5</table>
- <row>30</row>
- </item>
- <item>
- <table>5</table>
- <row>31</row>
- </item>
- <item>
- <table>5</table>
- <row>32</row>
- </item>
- <item>
- <table>5</table>
- <row>33</row>
- </item>
- <item>
- <table>5</table>
- <row>34</row>
- </item>
- <item>
- <table>5</table>
- <row>35</row>
- </item>
- <item>
- <table>5</table>
- <row>36</row>
- </item>
- <item>
- <table>5</table>
- <row>37</row>
- </item>
- <item>
- <table>5</table>
- <row>38</row>
- </item>
- <item>
- <table>5</table>
- <row>39</row>
- </item>
- <item>
- <table>5</table>
- <row>40</row>
- </item>
- <item>
- <table>5</table>
- <row>41</row>
- </item>
- <item>
- <table>5</table>
- <row>42</row>
- </item>
- <item>
- <table>5</table>
- <row>43</row>
- </item>
- <item>
- <table>5</table>
- <row>44</row>
- </item>
- <item>
- <table>5</table>
- <row>47</row>
- </item>
- <item>
- <table>5</table>
- <row>48</row>
- </item>
- <item>
- <table>5</table>
- <row>49</row>
- </item>
- <item>
- <table>5</table>
- <row>50</row>
- </item>
- <item>
- <table>5</table>
- <row>51</row>
- </item>
- <item>
- <table>5</table>
- <row>52</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>17</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>26</row>
- </item>
- <item>
- <table>6</table>
- <row>27</row>
- </item>
- <item>
- <table>6</table>
- <row>28</row>
- </item>
- <item>
- <table>6</table>
- <row>29</row>
- </item>
- <item>
- <table>6</table>
- <row>30</row>
- </item>
- <item>
- <table>6</table>
- <row>31</row>
- </item>
- <item>
- <table>6</table>
- <row>32</row>
- </item>
- <item>
- <table>6</table>
- <row>33</row>
- </item>
- <item>
- <table>6</table>
- <row>34</row>
- </item>
- <item>
- <table>6</table>
- <row>35</row>
- </item>
- <item>
- <table>6</table>
- <row>36</row>
- </item>
- <item>
- <table>6</table>
- <row>37</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>24</row>
- </item>
- <item>
- <table>7</table>
- <row>25</row>
- </item>
- <item>
- <table>7</table>
- <row>26</row>
- </item>
- <item>
- <table>7</table>
- <row>27</row>
- </item>
- <item>
- <table>7</table>
- <row>28</row>
- </item>
- <item>
- <table>7</table>
- <row>35</row>
- </item>
- <item>
- <table>7</table>
- <row>36</row>
- </item>
- <item>
- <table>7</table>
- <row>37</row>
- </item>
- <item>
- <table>7</table>
- <row>38</row>
- </item>
- <item>
- <table>7</table>
- <row>39</row>
- </item>
- <item>
- <table>7</table>
- <row>40</row>
- </item>
- <item>
- <table>7</table>
- <row>41</row>
- </item>
- <item>
- <table>7</table>
- <row>42</row>
- </item>
- <item>
- <table>7</table>
- <row>43</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>9</row>
- </item>
- <item>
- <table>15</table>
- <row>2c</row>
- </item>
- <item>
- <table>15</table>
- <row>4c</row>
- </item>
- <item>
- <table>16</table>
- <row>37b</row>
- </item>
- <item>
- <table>16</table>
- <row>38b</row>
- </item>
- <item>
- <table>16</table>
- <row>46b</row>
- </item>
- <item>
- <table>16</table>
- <row>47b</row>
- </item>
- <item>
- <table>16</table>
- <row>48b</row>
- </item>
- <item>
- <table>17</table>
- <row>18</row>
- </item>
- <item>
- <table>8</table>
- <row>5b</row>
- </item>
- <item>
- <table>8</table>
- <row>8b</row>
- </item>
- </profile>
- </pics>
-</project>
\ No newline at end of file
+<?xml version="1.0" encoding="utf-8"?>
+<project>
+ <qdid>187777</qdid>
+ <name>Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833</name>
+ <pics>
+ <profile>
+ <name>SUM ICS</name>
+ <item>
+ <table>21</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>PROD</name>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>LL</name>
+ <item>
+ <table>9</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3a</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6a</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6a</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4b</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5a</row>
+ </item>
+ </profile>
+ <profile>
+ <name>4.0HCI</name>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>44</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>47</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>48</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>49</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>50</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>51</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>52</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2c</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4c</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>37b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>38b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>46b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>47b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>48b</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>5b</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8b</row>
+ </item>
+ </profile>
+ </pics>
+</project>
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840.pts
index 5cc3753..8126a31 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840.pts
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840.pts
@@ -1,967 +1,967 @@
-<?xml version="1.0" encoding="utf-8"?>
-<project>
- <qdid>183721</qdid>
- <name>Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840</name>
- <pics>
- <profile>
- <name>SUM ICS</name>
- <item>
- <table>21</table>
- <row>21</row>
- </item>
- <item>
- <table>51</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>PROD</name>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>LL</name>
- <item>
- <table>9</table>
- <row>43</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>3a</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>10</row>
- </item>
- <item>
- <table>3</table>
- <row>11</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>4a</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>6a</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>10a</row>
- </item>
- <item>
- <table>6</table>
- <row>10b</row>
- </item>
- <item>
- <table>6</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>23</row>
- </item>
- <item>
- <table>6</table>
- <row>23a</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>4a</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>10</row>
- </item>
- <item>
- <table>7</table>
- <row>10a</row>
- </item>
- <item>
- <table>7</table>
- <row>10b</row>
- </item>
- <item>
- <table>7</table>
- <row>11</row>
- </item>
- <item>
- <table>7</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>13</row>
- </item>
- <item>
- <table>7</table>
- <row>14</row>
- </item>
- <item>
- <table>7</table>
- <row>15</row>
- </item>
- <item>
- <table>7</table>
- <row>16</row>
- </item>
- <item>
- <table>7</table>
- <row>19</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>20</row>
- </item>
- <item>
- <table>7</table>
- <row>21</row>
- </item>
- <item>
- <table>7</table>
- <row>22</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>23a</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>4a</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>10</row>
- </item>
- <item>
- <table>9</table>
- <row>12</row>
- </item>
- <item>
- <table>9</table>
- <row>13</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>6a</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>41</row>
- </item>
- <item>
- <table>9</table>
- <row>42</row>
- </item>
- <item>
- <table>3</table>
- <row>12a</row>
- </item>
- <item>
- <table>3</table>
- <row>1a</row>
- </item>
- <item>
- <table>3</table>
- <row>4b</row>
- </item>
- <item>
- <table>3</table>
- <row>5a</row>
- </item>
- </profile>
- <profile>
- <name>4.0HCI</name>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>12</row>
- </item>
- <item>
- <table>10</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>14</row>
- </item>
- <item>
- <table>10</table>
- <row>15</row>
- </item>
- <item>
- <table>10</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>13</table>
- <row>12</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>17</row>
- </item>
- <item>
- <table>14</table>
- <row>18</row>
- </item>
- <item>
- <table>14</table>
- <row>19</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>20</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>32</row>
- </item>
- <item>
- <table>16</table>
- <row>33</row>
- </item>
- <item>
- <table>16</table>
- <row>34</row>
- </item>
- <item>
- <table>16</table>
- <row>35</row>
- </item>
- <item>
- <table>16</table>
- <row>36</row>
- </item>
- <item>
- <table>16</table>
- <row>39</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>12</row>
- </item>
- <item>
- <table>17</table>
- <row>13</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>1a</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>13</row>
- </item>
- <item>
- <table>5</table>
- <row>14</row>
- </item>
- <item>
- <table>5</table>
- <row>15</row>
- </item>
- <item>
- <table>5</table>
- <row>16</row>
- </item>
- <item>
- <table>5</table>
- <row>17</row>
- </item>
- <item>
- <table>5</table>
- <row>27</row>
- </item>
- <item>
- <table>5</table>
- <row>28</row>
- </item>
- <item>
- <table>5</table>
- <row>29</row>
- </item>
- <item>
- <table>5</table>
- <row>30</row>
- </item>
- <item>
- <table>5</table>
- <row>31</row>
- </item>
- <item>
- <table>5</table>
- <row>32</row>
- </item>
- <item>
- <table>5</table>
- <row>33</row>
- </item>
- <item>
- <table>5</table>
- <row>34</row>
- </item>
- <item>
- <table>5</table>
- <row>35</row>
- </item>
- <item>
- <table>5</table>
- <row>36</row>
- </item>
- <item>
- <table>5</table>
- <row>37</row>
- </item>
- <item>
- <table>5</table>
- <row>38</row>
- </item>
- <item>
- <table>5</table>
- <row>39</row>
- </item>
- <item>
- <table>5</table>
- <row>40</row>
- </item>
- <item>
- <table>5</table>
- <row>41</row>
- </item>
- <item>
- <table>5</table>
- <row>42</row>
- </item>
- <item>
- <table>5</table>
- <row>43</row>
- </item>
- <item>
- <table>5</table>
- <row>44</row>
- </item>
- <item>
- <table>5</table>
- <row>47</row>
- </item>
- <item>
- <table>5</table>
- <row>48</row>
- </item>
- <item>
- <table>5</table>
- <row>49</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>17</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>26</row>
- </item>
- <item>
- <table>6</table>
- <row>27</row>
- </item>
- <item>
- <table>6</table>
- <row>28</row>
- </item>
- <item>
- <table>6</table>
- <row>29</row>
- </item>
- <item>
- <table>6</table>
- <row>30</row>
- </item>
- <item>
- <table>6</table>
- <row>31</row>
- </item>
- <item>
- <table>6</table>
- <row>32</row>
- </item>
- <item>
- <table>6</table>
- <row>33</row>
- </item>
- <item>
- <table>6</table>
- <row>34</row>
- </item>
- <item>
- <table>6</table>
- <row>35</row>
- </item>
- <item>
- <table>6</table>
- <row>36</row>
- </item>
- <item>
- <table>6</table>
- <row>37</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>24</row>
- </item>
- <item>
- <table>7</table>
- <row>25</row>
- </item>
- <item>
- <table>7</table>
- <row>26</row>
- </item>
- <item>
- <table>7</table>
- <row>27</row>
- </item>
- <item>
- <table>7</table>
- <row>28</row>
- </item>
- <item>
- <table>7</table>
- <row>35</row>
- </item>
- <item>
- <table>7</table>
- <row>36</row>
- </item>
- <item>
- <table>7</table>
- <row>37</row>
- </item>
- <item>
- <table>7</table>
- <row>38</row>
- </item>
- <item>
- <table>7</table>
- <row>39</row>
- </item>
- <item>
- <table>7</table>
- <row>40</row>
- </item>
- <item>
- <table>7</table>
- <row>41</row>
- </item>
- <item>
- <table>7</table>
- <row>42</row>
- </item>
- <item>
- <table>7</table>
- <row>43</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>7</row>
- </item>
- <item>
- <table>15</table>
- <row>2c</row>
- </item>
- <item>
- <table>15</table>
- <row>4c</row>
- </item>
- <item>
- <table>16</table>
- <row>37b</row>
- </item>
- <item>
- <table>16</table>
- <row>38b</row>
- </item>
- <item>
- <table>16</table>
- <row>46b</row>
- </item>
- <item>
- <table>16</table>
- <row>47b</row>
- </item>
- <item>
- <table>16</table>
- <row>48b</row>
- </item>
- <item>
- <table>17</table>
- <row>18</row>
- </item>
- <item>
- <table>8</table>
- <row>5b</row>
- </item>
- <item>
- <table>8</table>
- <row>8b</row>
- </item>
- </profile>
- </pics>
-</project>
\ No newline at end of file
+<?xml version="1.0" encoding="utf-8"?>
+<project>
+ <qdid>183721</qdid>
+ <name>Zephyr_Bluetooth_Controller_nrf52840dk_nrf52840</name>
+ <pics>
+ <profile>
+ <name>SUM ICS</name>
+ <item>
+ <table>21</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>PROD</name>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>LL</name>
+ <item>
+ <table>9</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3a</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6a</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6a</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4b</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5a</row>
+ </item>
+ </profile>
+ <profile>
+ <name>4.0HCI</name>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>44</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>47</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>48</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>49</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2c</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4c</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>37b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>38b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>46b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>47b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>48b</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>5b</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8b</row>
+ </item>
+ </profile>
+ </pics>
+</project>
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.pts
index c4c7080..fba3f8d 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.pts
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.pts
@@ -1,779 +1,779 @@
-<?xml version="1.0" encoding="utf-8"?>
-<project>
- <qdid>184832</qdid>
- <name>Zephyr_Bluetooth_Controller_nrf52dk_nrf52832</name>
- <pics>
- <profile>
- <name>SUM ICS</name>
- <item>
- <table>21</table>
- <row>21</row>
- </item>
- <item>
- <table>51</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>PROD</name>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>LL</name>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>4a</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>10a</row>
- </item>
- <item>
- <table>6</table>
- <row>10b</row>
- </item>
- <item>
- <table>6</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>23</row>
- </item>
- <item>
- <table>6</table>
- <row>23a</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>4a</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>10</row>
- </item>
- <item>
- <table>7</table>
- <row>10a</row>
- </item>
- <item>
- <table>7</table>
- <row>10b</row>
- </item>
- <item>
- <table>7</table>
- <row>11</row>
- </item>
- <item>
- <table>7</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>13</row>
- </item>
- <item>
- <table>7</table>
- <row>14</row>
- </item>
- <item>
- <table>7</table>
- <row>15</row>
- </item>
- <item>
- <table>7</table>
- <row>16</row>
- </item>
- <item>
- <table>7</table>
- <row>19</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>20</row>
- </item>
- <item>
- <table>7</table>
- <row>21</row>
- </item>
- <item>
- <table>7</table>
- <row>22</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>23a</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>4a</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>10</row>
- </item>
- <item>
- <table>9</table>
- <row>12</row>
- </item>
- <item>
- <table>9</table>
- <row>13</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>6a</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- </profile>
- <profile>
- <name>4.0HCI</name>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>12</row>
- </item>
- <item>
- <table>10</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>14</row>
- </item>
- <item>
- <table>10</table>
- <row>15</row>
- </item>
- <item>
- <table>10</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>13</table>
- <row>12</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>32</row>
- </item>
- <item>
- <table>16</table>
- <row>33</row>
- </item>
- <item>
- <table>16</table>
- <row>34</row>
- </item>
- <item>
- <table>16</table>
- <row>35</row>
- </item>
- <item>
- <table>16</table>
- <row>36</row>
- </item>
- <item>
- <table>16</table>
- <row>39</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>12</row>
- </item>
- <item>
- <table>17</table>
- <row>13</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>1a</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>13</row>
- </item>
- <item>
- <table>5</table>
- <row>14</row>
- </item>
- <item>
- <table>5</table>
- <row>15</row>
- </item>
- <item>
- <table>5</table>
- <row>16</row>
- </item>
- <item>
- <table>5</table>
- <row>17</row>
- </item>
- <item>
- <table>5</table>
- <row>27</row>
- </item>
- <item>
- <table>5</table>
- <row>28</row>
- </item>
- <item>
- <table>5</table>
- <row>29</row>
- </item>
- <item>
- <table>5</table>
- <row>30</row>
- </item>
- <item>
- <table>5</table>
- <row>31</row>
- </item>
- <item>
- <table>5</table>
- <row>32</row>
- </item>
- <item>
- <table>5</table>
- <row>44</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>17</row>
- </item>
- <item>
- <table>6</table>
- <row>18</row>
- </item>
- <item>
- <table>6</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>20</row>
- </item>
- <item>
- <table>6</table>
- <row>21</row>
- </item>
- <item>
- <table>6</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>26</row>
- </item>
- <item>
- <table>7</table>
- <row>23</row>
- </item>
- <item>
- <table>7</table>
- <row>24</row>
- </item>
- <item>
- <table>7</table>
- <row>25</row>
- </item>
- <item>
- <table>7</table>
- <row>26</row>
- </item>
- <item>
- <table>7</table>
- <row>27</row>
- </item>
- <item>
- <table>7</table>
- <row>28</row>
- </item>
- <item>
- <table>7</table>
- <row>35</row>
- </item>
- <item>
- <table>7</table>
- <row>36</row>
- </item>
- <item>
- <table>7</table>
- <row>37</row>
- </item>
- <item>
- <table>7</table>
- <row>38</row>
- </item>
- <item>
- <table>7</table>
- <row>39</row>
- </item>
- <item>
- <table>7</table>
- <row>40</row>
- </item>
- <item>
- <table>7</table>
- <row>42</row>
- </item>
- <item>
- <table>7</table>
- <row>43</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>7</row>
- </item>
- <item>
- <table>15</table>
- <row>2c</row>
- </item>
- <item>
- <table>15</table>
- <row>4c</row>
- </item>
- <item>
- <table>16</table>
- <row>37b</row>
- </item>
- <item>
- <table>16</table>
- <row>38b</row>
- </item>
- <item>
- <table>16</table>
- <row>46b</row>
- </item>
- <item>
- <table>16</table>
- <row>47b</row>
- </item>
- <item>
- <table>16</table>
- <row>48b</row>
- </item>
- <item>
- <table>17</table>
- <row>18</row>
- </item>
- <item>
- <table>8</table>
- <row>5b</row>
- </item>
- <item>
- <table>8</table>
- <row>8b</row>
- </item>
- </profile>
- </pics>
-</project>
\ No newline at end of file
+<?xml version="1.0" encoding="utf-8"?>
+<project>
+ <qdid>184832</qdid>
+ <name>Zephyr_Bluetooth_Controller_nrf52dk_nrf52832</name>
+ <pics>
+ <profile>
+ <name>SUM ICS</name>
+ <item>
+ <table>21</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>PROD</name>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>LL</name>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10b</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4a</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6a</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ </profile>
+ <profile>
+ <name>4.0HCI</name>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>44</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2c</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4c</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>37b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>38b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>46b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>47b</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>48b</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>5b</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8b</row>
+ </item>
+ </profile>
+ </pics>
+</project>
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
index c2f8f7d..7e90c87 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
@@ -1,11503 +1,11503 @@
-<?xml version="1.0" encoding="utf-8"?>
-<project>
- <qdid>300252</qdid>
- <name>Zephyr_Bluetooth_Host</name>
- <pics>
- <profile>
- <name>GAP</name>
- <item>
- <table>27c</table>
- <row>1</row>
- </item>
- <item>
- <table>17b</table>
- <row>2</row>
- </item>
- <item>
- <table>35</table>
- <row>14</row>
- </item>
- <item>
- <table>11b</table>
- <row>3</row>
- </item>
- <item>
- <table>35</table>
- <row>11</row>
- </item>
- <item>
- <table>14a</table>
- <row>7</row>
- </item>
- <item>
- <table>27b</table>
- <row>7</row>
- </item>
- <item>
- <table>37c</table>
- <row>2</row>
- </item>
- <item>
- <table>30a</table>
- <row>5</row>
- </item>
- <item>
- <table>30a</table>
- <row>3</row>
- </item>
- <item>
- <table>8a</table>
- <row>14a</row>
- </item>
- <item>
- <table>14a</table>
- <row>16</row>
- </item>
- <item>
- <table>37c</table>
- <row>3</row>
- </item>
- <item>
- <table>30a</table>
- <row>10</row>
- </item>
- <item>
- <table>30a</table>
- <row>17</row>
- </item>
- <item>
- <table>27b</table>
- <row>5</row>
- </item>
- <item>
- <table>8a</table>
- <row>18</row>
- </item>
- <item>
- <table>35</table>
- <row>15</row>
- </item>
- <item>
- <table>30a</table>
- <row>8</row>
- </item>
- <item>
- <table>27b</table>
- <row>2</row>
- </item>
- <item>
- <table>14a</table>
- <row>18</row>
- </item>
- <item>
- <table>14a</table>
- <row>17</row>
- </item>
- <item>
- <table>14a</table>
- <row>5</row>
- </item>
- <item>
- <table>14a</table>
- <row>19</row>
- </item>
- <item>
- <table>25</table>
- <row>12</row>
- </item>
- <item>
- <table>17b</table>
- <row>3</row>
- </item>
- <item>
- <table>30a</table>
- <row>19</row>
- </item>
- <item>
- <table>30a</table>
- <row>18</row>
- </item>
- <item>
- <table>37b</table>
- <row>6</row>
- </item>
- <item>
- <table>20A</table>
- <row>14a</row>
- </item>
- <item>
- <table>11</table>
- <row>4</row>
- </item>
- <item>
- <table>27b</table>
- <row>9</row>
- </item>
- <item>
- <table>37b</table>
- <row>1</row>
- </item>
- <item>
- <table>27b</table>
- <row>1</row>
- </item>
- <item>
- <table>30a</table>
- <row>4</row>
- </item>
- <item>
- <table>37b</table>
- <row>9</row>
- </item>
- <item>
- <table>37b</table>
- <row>2</row>
- </item>
- <item>
- <table>30a</table>
- <row>12</row>
- </item>
- <item>
- <table>30a</table>
- <row>14</row>
- </item>
- <item>
- <table>30a</table>
- <row>13</row>
- </item>
- <item>
- <table>37c</table>
- <row>1</row>
- </item>
- <item>
- <table>25</table>
- <row>13</row>
- </item>
- <item>
- <table>14a</table>
- <row>2</row>
- </item>
- <item>
- <table>11b</table>
- <row>4</row>
- </item>
- <item>
- <table>20A</table>
- <row>18</row>
- </item>
- <item>
- <table>37b</table>
- <row>3</row>
- </item>
- <item>
- <table>30a</table>
- <row>15</row>
- </item>
- <item>
- <table>11b</table>
- <row>2</row>
- </item>
- <item>
- <table>30a</table>
- <row>6</row>
- </item>
- <item>
- <table>14a</table>
- <row>4</row>
- </item>
- <item>
- <table>27c</table>
- <row>2</row>
- </item>
- <item>
- <table>14a</table>
- <row>6</row>
- </item>
- <item>
- <table>14a</table>
- <row>15</row>
- </item>
- <item>
- <table>35</table>
- <row>13</row>
- </item>
- <item>
- <table>14a</table>
- <row>11</row>
- </item>
- <item>
- <table>20A</table>
- <row>19</row>
- </item>
- <item>
- <table>14a</table>
- <row>14</row>
- </item>
- <item>
- <table>37b</table>
- <row>8</row>
- </item>
- <item>
- <table>30a</table>
- <row>16</row>
- </item>
- <item>
- <table>30a</table>
- <row>1</row>
- </item>
- <item>
- <table>35</table>
- <row>12</row>
- </item>
- <item>
- <table>30a</table>
- <row>11</row>
- </item>
- <item>
- <table>14a</table>
- <row>9</row>
- </item>
- <item>
- <table>30a</table>
- <row>9</row>
- </item>
- <item>
- <table>14a</table>
- <row>1</row>
- </item>
- <item>
- <table>14a</table>
- <row>14a</row>
- </item>
- <item>
- <table>30a</table>
- <row>14a</row>
- </item>
- <item>
- <table>14a</table>
- <row>10</row>
- </item>
- <item>
- <table>27b</table>
- <row>8</row>
- </item>
- <item>
- <table>27b</table>
- <row>3</row>
- </item>
- <item>
- <table>25</table>
- <row>14</row>
- </item>
- <item>
- <table>37b</table>
- <row>5</row>
- </item>
- <item>
- <table>27b</table>
- <row>6</row>
- </item>
- <item>
- <table>14a</table>
- <row>13</row>
- </item>
- <item>
- <table>30a</table>
- <row>7</row>
- </item>
- <item>
- <table>25</table>
- <row>11</row>
- </item>
- <item>
- <table>8a</table>
- <row>19</row>
- </item>
- <item>
- <table>14a</table>
- <row>3</row>
- </item>
- <item>
- <table>37b</table>
- <row>7</row>
- </item>
- <item>
- <table>14a</table>
- <row>8</row>
- </item>
- <item>
- <table>14a</table>
- <row>12</row>
- </item>
- <item>
- <table>30a</table>
- <row>2</row>
- </item>
- <item>
- <table>27c</table>
- <row>3</row>
- </item>
- <item>
- <table>0</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>11a</table>
- <row>1</row>
- </item>
- <item>
- <table>11a</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>17</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>4</row>
- </item>
- <item>
- <table>17a</table>
- <row>1</row>
- </item>
- <item>
- <table>17a</table>
- <row>2</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>19</table>
- <row>2</row>
- </item>
- <item>
- <table>19</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>7</row>
- </item>
- <item>
- <table>20A</table>
- <row>1</row>
- </item>
- <item>
- <table>20A</table>
- <row>10</row>
- </item>
- <item>
- <table>20A</table>
- <row>11</row>
- </item>
- <item>
- <table>20A</table>
- <row>12</row>
- </item>
- <item>
- <table>20A</table>
- <row>13</row>
- </item>
- <item>
- <table>20A</table>
- <row>14</row>
- </item>
- <item>
- <table>20A</table>
- <row>15</row>
- </item>
- <item>
- <table>20A</table>
- <row>16</row>
- </item>
- <item>
- <table>20A</table>
- <row>17</row>
- </item>
- <item>
- <table>20A</table>
- <row>2</row>
- </item>
- <item>
- <table>20A</table>
- <row>3</row>
- </item>
- <item>
- <table>20A</table>
- <row>4</row>
- </item>
- <item>
- <table>20A</table>
- <row>5</row>
- </item>
- <item>
- <table>20A</table>
- <row>7</row>
- </item>
- <item>
- <table>20A</table>
- <row>8</row>
- </item>
- <item>
- <table>20A</table>
- <row>9</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>10</row>
- </item>
- <item>
- <table>21</table>
- <row>11</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>21</table>
- <row>3</row>
- </item>
- <item>
- <table>21</table>
- <row>4</row>
- </item>
- <item>
- <table>21</table>
- <row>5</row>
- </item>
- <item>
- <table>21</table>
- <row>6</row>
- </item>
- <item>
- <table>21</table>
- <row>7</row>
- </item>
- <item>
- <table>21</table>
- <row>8</row>
- </item>
- <item>
- <table>21</table>
- <row>9</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>1</row>
- </item>
- <item>
- <table>23</table>
- <row>2</row>
- </item>
- <item>
- <table>23</table>
- <row>3</row>
- </item>
- <item>
- <table>23</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>5</row>
- </item>
- <item>
- <table>24</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>2</row>
- </item>
- <item>
- <table>24</table>
- <row>3</row>
- </item>
- <item>
- <table>24</table>
- <row>4</row>
- </item>
- <item>
- <table>25</table>
- <row>1</row>
- </item>
- <item>
- <table>25</table>
- <row>10</row>
- </item>
- <item>
- <table>25</table>
- <row>2</row>
- </item>
- <item>
- <table>25</table>
- <row>3</row>
- </item>
- <item>
- <table>25</table>
- <row>4</row>
- </item>
- <item>
- <table>25</table>
- <row>5</row>
- </item>
- <item>
- <table>25</table>
- <row>6</row>
- </item>
- <item>
- <table>25</table>
- <row>7</row>
- </item>
- <item>
- <table>25</table>
- <row>8</row>
- </item>
- <item>
- <table>25</table>
- <row>9</row>
- </item>
- <item>
- <table>26</table>
- <row>1</row>
- </item>
- <item>
- <table>26</table>
- <row>2</row>
- </item>
- <item>
- <table>26</table>
- <row>3</row>
- </item>
- <item>
- <table>26</table>
- <row>4</row>
- </item>
- <item>
- <table>27</table>
- <row>1</row>
- </item>
- <item>
- <table>27</table>
- <row>2</row>
- </item>
- <item>
- <table>27</table>
- <row>5</row>
- </item>
- <item>
- <table>27</table>
- <row>6</row>
- </item>
- <item>
- <table>27</table>
- <row>9</row>
- </item>
- <item>
- <table>28</table>
- <row>1</row>
- </item>
- <item>
- <table>28</table>
- <row>2</row>
- </item>
- <item>
- <table>29</table>
- <row>1</row>
- </item>
- <item>
- <table>29</table>
- <row>2</row>
- </item>
- <item>
- <table>29</table>
- <row>3</row>
- </item>
- <item>
- <table>29</table>
- <row>4</row>
- </item>
- <item>
- <table>30</table>
- <row>1</row>
- </item>
- <item>
- <table>30</table>
- <row>2</row>
- </item>
- <item>
- <table>31</table>
- <row>1</row>
- </item>
- <item>
- <table>31</table>
- <row>10</row>
- </item>
- <item>
- <table>31</table>
- <row>11</row>
- </item>
- <item>
- <table>31</table>
- <row>2</row>
- </item>
- <item>
- <table>31</table>
- <row>3</row>
- </item>
- <item>
- <table>31</table>
- <row>4</row>
- </item>
- <item>
- <table>31</table>
- <row>5</row>
- </item>
- <item>
- <table>31</table>
- <row>6</row>
- </item>
- <item>
- <table>31</table>
- <row>8</row>
- </item>
- <item>
- <table>31</table>
- <row>9</row>
- </item>
- <item>
- <table>32</table>
- <row>1</row>
- </item>
- <item>
- <table>32</table>
- <row>2</row>
- </item>
- <item>
- <table>32</table>
- <row>3</row>
- </item>
- <item>
- <table>33</table>
- <row>1</row>
- </item>
- <item>
- <table>33</table>
- <row>2</row>
- </item>
- <item>
- <table>33</table>
- <row>4</row>
- </item>
- <item>
- <table>33</table>
- <row>5</row>
- </item>
- <item>
- <table>33</table>
- <row>6</row>
- </item>
- <item>
- <table>34</table>
- <row>1</row>
- </item>
- <item>
- <table>34</table>
- <row>2</row>
- </item>
- <item>
- <table>34</table>
- <row>3</row>
- </item>
- <item>
- <table>35</table>
- <row>1</row>
- </item>
- <item>
- <table>35</table>
- <row>10</row>
- </item>
- <item>
- <table>35</table>
- <row>2</row>
- </item>
- <item>
- <table>35</table>
- <row>3</row>
- </item>
- <item>
- <table>35</table>
- <row>4</row>
- </item>
- <item>
- <table>35</table>
- <row>5</row>
- </item>
- <item>
- <table>35</table>
- <row>6</row>
- </item>
- <item>
- <table>35</table>
- <row>7</row>
- </item>
- <item>
- <table>35</table>
- <row>8</row>
- </item>
- <item>
- <table>35</table>
- <row>9</row>
- </item>
- <item>
- <table>36</table>
- <row>1</row>
- </item>
- <item>
- <table>36</table>
- <row>2</row>
- </item>
- <item>
- <table>36</table>
- <row>3</row>
- </item>
- <item>
- <table>36</table>
- <row>5</row>
- </item>
- <item>
- <table>37</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>2</row>
- </item>
- <item>
- <table>37</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>8</table>
- <row>4</row>
- </item>
- <item>
- <table>8a</table>
- <row>1</row>
- </item>
- <item>
- <table>8a</table>
- <row>10</row>
- </item>
- <item>
- <table>8a</table>
- <row>11</row>
- </item>
- <item>
- <table>8a</table>
- <row>12</row>
- </item>
- <item>
- <table>8a</table>
- <row>13</row>
- </item>
- <item>
- <table>8a</table>
- <row>14</row>
- </item>
- <item>
- <table>8a</table>
- <row>15</row>
- </item>
- <item>
- <table>8a</table>
- <row>16</row>
- </item>
- <item>
- <table>8a</table>
- <row>17</row>
- </item>
- <item>
- <table>8a</table>
- <row>2</row>
- </item>
- <item>
- <table>8a</table>
- <row>3</row>
- </item>
- <item>
- <table>8a</table>
- <row>4</row>
- </item>
- <item>
- <table>8a</table>
- <row>5</row>
- </item>
- <item>
- <table>8a</table>
- <row>6</row>
- </item>
- <item>
- <table>8a</table>
- <row>7</row>
- </item>
- <item>
- <table>8a</table>
- <row>8</row>
- </item>
- <item>
- <table>8a</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>4</row>
- </item>
- <item>
- <table>10</table>
- <row>5</row>
- </item>
- <item>
- <table>11b</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>17b</table>
- <row>1</row>
- </item>
- <item>
- <table>23</table>
- <row>6</row>
- </item>
- <item>
- <table>33</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- </profile>
- <profile>
- <name>L2CAP</name>
- <item>
- <table>2</table>
- <row>48b</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>49</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>40</row>
- </item>
- <item>
- <table>2</table>
- <row>41</row>
- </item>
- <item>
- <table>2</table>
- <row>42</row>
- </item>
- <item>
- <table>2</table>
- <row>43</row>
- </item>
- <item>
- <table>2</table>
- <row>45a</row>
- </item>
- <item>
- <table>2</table>
- <row>46</row>
- </item>
- <item>
- <table>2</table>
- <row>47</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>12</row>
- </item>
- <item>
- <table>3</table>
- <row>16</row>
- </item>
- <item>
- <table>0</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>1</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>48</row>
- </item>
- </profile>
- <profile>
- <name>IOP</name>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>GATT</name>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>11</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3a</row>
- </item>
- <item>
- <table>9</table>
- <row>10</row>
- </item>
- <item>
- <table>10</table>
- <row>6</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>15</row>
- </item>
- <item>
- <table>10</table>
- <row>7</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>10</row>
- </item>
- <item>
- <table>3a</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>8</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>9</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>12</row>
- </item>
- <item>
- <table>10</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>3a</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- <item>
- <table>7</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>10</table>
- <row>9</row>
- </item>
- <item>
- <table>4a</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>11</row>
- </item>
- <item>
- <table>9</table>
- <row>14</row>
- </item>
- <item>
- <table>9</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>4a</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>10</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>12</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>1a</table>
- <row>1</row>
- </item>
- <item>
- <table>1a</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>29</row>
- </item>
- <item>
- <table>3</table>
- <row>30</row>
- </item>
- <item>
- <table>4</table>
- <row>30</row>
- </item>
- <item>
- <table>4</table>
- <row>31</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>10</row>
- </item>
- <item>
- <table>3</table>
- <row>11</row>
- </item>
- <item>
- <table>3</table>
- <row>12</row>
- </item>
- <item>
- <table>3</table>
- <row>13</row>
- </item>
- <item>
- <table>3</table>
- <row>14</row>
- </item>
- <item>
- <table>3</table>
- <row>15</row>
- </item>
- <item>
- <table>3</table>
- <row>17</row>
- </item>
- <item>
- <table>3</table>
- <row>18</row>
- </item>
- <item>
- <table>3</table>
- <row>19</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>20</row>
- </item>
- <item>
- <table>3</table>
- <row>21</row>
- </item>
- <item>
- <table>3</table>
- <row>22</row>
- </item>
- <item>
- <table>3</table>
- <row>23</row>
- </item>
- <item>
- <table>3</table>
- <row>25</row>
- </item>
- <item>
- <table>3</table>
- <row>26</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>10</row>
- </item>
- <item>
- <table>4</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>13</row>
- </item>
- <item>
- <table>4</table>
- <row>14</row>
- </item>
- <item>
- <table>4</table>
- <row>15</row>
- </item>
- <item>
- <table>4</table>
- <row>16</row>
- </item>
- <item>
- <table>4</table>
- <row>17</row>
- </item>
- <item>
- <table>4</table>
- <row>18</row>
- </item>
- <item>
- <table>4</table>
- <row>19</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>20</row>
- </item>
- <item>
- <table>4</table>
- <row>21</row>
- </item>
- <item>
- <table>4</table>
- <row>22</row>
- </item>
- <item>
- <table>4</table>
- <row>23</row>
- </item>
- <item>
- <table>4</table>
- <row>25</row>
- </item>
- <item>
- <table>4</table>
- <row>26</row>
- </item>
- <item>
- <table>4</table>
- <row>27</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- </profile>
- <profile>
- <name>SM</name>
- <item>
- <table>7a</table>
- <row>1</row>
- </item>
- <item>
- <table>7a</table>
- <row>2</row>
- </item>
- <item>
- <table>7b</table>
- <row>1</row>
- </item>
- <item>
- <table>7b</table>
- <row>2</row>
- </item>
- <item>
- <table>7b</table>
- <row>3</row>
- </item>
- <item>
- <table>7a</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>ATT</name>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>3a</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>30</row>
- </item>
- <item>
- <table>3</table>
- <row>31</row>
- </item>
- <item>
- <table>3</table>
- <row>32</row>
- </item>
- <item>
- <table>4</table>
- <row>31</row>
- </item>
- <item>
- <table>4</table>
- <row>32</row>
- </item>
- <item>
- <table>4</table>
- <row>33</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>10</row>
- </item>
- <item>
- <table>3</table>
- <row>11</row>
- </item>
- <item>
- <table>3</table>
- <row>12</row>
- </item>
- <item>
- <table>3</table>
- <row>13</row>
- </item>
- <item>
- <table>3</table>
- <row>14</row>
- </item>
- <item>
- <table>3</table>
- <row>15</row>
- </item>
- <item>
- <table>3</table>
- <row>16</row>
- </item>
- <item>
- <table>3</table>
- <row>17</row>
- </item>
- <item>
- <table>3</table>
- <row>18</row>
- </item>
- <item>
- <table>3</table>
- <row>19</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>20</row>
- </item>
- <item>
- <table>3</table>
- <row>21</row>
- </item>
- <item>
- <table>3</table>
- <row>22</row>
- </item>
- <item>
- <table>3</table>
- <row>23</row>
- </item>
- <item>
- <table>3</table>
- <row>24</row>
- </item>
- <item>
- <table>3</table>
- <row>25</row>
- </item>
- <item>
- <table>3</table>
- <row>26</row>
- </item>
- <item>
- <table>3</table>
- <row>27</row>
- </item>
- <item>
- <table>3</table>
- <row>28</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>10</row>
- </item>
- <item>
- <table>4</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>13</row>
- </item>
- <item>
- <table>4</table>
- <row>14</row>
- </item>
- <item>
- <table>4</table>
- <row>15</row>
- </item>
- <item>
- <table>4</table>
- <row>16</row>
- </item>
- <item>
- <table>4</table>
- <row>17</row>
- </item>
- <item>
- <table>4</table>
- <row>18</row>
- </item>
- <item>
- <table>4</table>
- <row>19</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>20</row>
- </item>
- <item>
- <table>4</table>
- <row>21</row>
- </item>
- <item>
- <table>4</table>
- <row>22</row>
- </item>
- <item>
- <table>4</table>
- <row>23</row>
- </item>
- <item>
- <table>4</table>
- <row>24</row>
- </item>
- <item>
- <table>4</table>
- <row>25</row>
- </item>
- <item>
- <table>4</table>
- <row>26</row>
- </item>
- <item>
- <table>4</table>
- <row>27</row>
- </item>
- <item>
- <table>4</table>
- <row>28</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>30</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- </profile>
- <profile>
- <name>DIS</name>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>0</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>11</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- </profile>
- <profile>
- <name>IAS</name>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>HRS</name>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>BAS</name>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>0</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- </profile>
- <profile>
- <name>OTS</name>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>8</row>
- </item>
- <item>
- <table>8</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>4</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>13</row>
- </item>
- <item>
- <table>4</table>
- <row>15</row>
- </item>
- <item>
- <table>4</table>
- <row>16</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>20</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>5</row>
- </item>
- <item>
- <table>5</table>
- <row>6</row>
- </item>
- <item>
- <table>5</table>
- <row>9</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>OTP</name>
- <item>
- <table>9</table>
- <row>11</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>15</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>12</row>
- </item>
- <item>
- <table>9</table>
- <row>10</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>14</row>
- </item>
- <item>
- <table>9</table>
- <row>13</row>
- </item>
- <item>
- <table>9</table>
- <row>16</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>18</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>6</table>
- <row>9</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>15</row>
- </item>
- <item>
- <table>7</table>
- <row>16</row>
- </item>
- <item>
- <table>7</table>
- <row>17</row>
- </item>
- <item>
- <table>7</table>
- <row>18</row>
- </item>
- <item>
- <table>7</table>
- <row>19</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>20</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>17</row>
- </item>
- <item>
- <table>8</table>
- <row>18</row>
- </item>
- <item>
- <table>8</table>
- <row>19</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>30</row>
- </item>
- </profile>
- <profile>
- <name>MESH</name>
- <item>
- <table>11</table>
- <row>11</row>
- </item>
- <item>
- <table>11</table>
- <row>20</row>
- </item>
- <item>
- <table>4</table>
- <row>14</row>
- </item>
- <item>
- <table>11</table>
- <row>12</row>
- </item>
- <item>
- <table>11</table>
- <row>23</row>
- </item>
- <item>
- <table>11</table>
- <row>24</row>
- </item>
- <item>
- <table>4</table>
- <row>15</row>
- </item>
- <item>
- <table>12</table>
- <row>12</row>
- </item>
- <item>
- <table>12</table>
- <row>8</row>
- </item>
- <item>
- <table>10</table>
- <row>5</row>
- </item>
- <item>
- <table>18</table>
- <row>12</row>
- </item>
- <item>
- <table>1a</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>18</row>
- </item>
- <item>
- <table>11</table>
- <row>14</row>
- </item>
- <item>
- <table>11</table>
- <row>16</row>
- </item>
- <item>
- <table>4</table>
- <row>13</row>
- </item>
- <item>
- <table>0</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>6</row>
- </item>
- <item>
- <table>11</table>
- <row>19</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>13</row>
- </item>
- <item>
- <table>11</table>
- <row>15</row>
- </item>
- <item>
- <table>11</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>7</row>
- </item>
- <item>
- <table>11</table>
- <row>17</row>
- </item>
- <item>
- <table>4</table>
- <row>16</row>
- </item>
- <item>
- <table>11</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>22</row>
- </item>
- <item>
- <table>11</table>
- <row>21</row>
- </item>
- <item>
- <table>12</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>17</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>4</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>11</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>12</table>
- <row>6</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>3</row>
- </item>
- <item>
- <table>15</table>
- <row>4</row>
- </item>
- <item>
- <table>15</table>
- <row>5</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>10</row>
- </item>
- <item>
- <table>4</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>10</row>
- </item>
- <item>
- <table>18</table>
- <row>11</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>18</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>4</row>
- </item>
- <item>
- <table>18</table>
- <row>5</row>
- </item>
- <item>
- <table>18</table>
- <row>6</row>
- </item>
- <item>
- <table>18</table>
- <row>7</row>
- </item>
- <item>
- <table>18</table>
- <row>8</row>
- </item>
- <item>
- <table>18</table>
- <row>9</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>5</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>21</table>
- <row>3</row>
- </item>
- <item>
- <table>21</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>AICS</name>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>2</table>
- <row>8</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>VOCS</name>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>VCS</name>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>VCP</name>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>5</row>
- </item>
- <item>
- <table>18</table>
- <row>15</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>14</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>16</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>12</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>15</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>10</row>
- </item>
- <item>
- <table>18</table>
- <row>7</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>9</row>
- </item>
- <item>
- <table>16</table>
- <row>13</row>
- </item>
- <item>
- <table>16</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>11</row>
- </item>
- <item>
- <table>18</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>10</row>
- </item>
- <item>
- <table>17</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>18</table>
- <row>12</row>
- </item>
- <item>
- <table>16</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>11</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>17</table>
- <row>3</row>
- </item>
- <item>
- <table>15</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>12</row>
- </item>
- <item>
- <table>18</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>8</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>12</table>
- <row>6</row>
- </item>
- <item>
- <table>15</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>5</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>6</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>17</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- </profile>
- <profile>
- <name>MICS</name>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>MICP</name>
- <item>
- <table>15</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>15</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>10</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>7</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>15</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>11</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>15</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>7</row>
- </item>
- <item>
- <table>15</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>14</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>15</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>15</table>
- <row>10</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>MCS</name>
- <item>
- <table>23</table>
- <row>7</row>
- </item>
- <item>
- <table>23</table>
- <row>11</row>
- </item>
- <item>
- <table>22</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>7</row>
- </item>
- <item>
- <table>23</table>
- <row>17</row>
- </item>
- <item>
- <table>23</table>
- <row>19</row>
- </item>
- <item>
- <table>22</table>
- <row>6</row>
- </item>
- <item>
- <table>25</table>
- <row>6</row>
- </item>
- <item>
- <table>22</table>
- <row>15</row>
- </item>
- <item>
- <table>23</table>
- <row>21</row>
- </item>
- <item>
- <table>22</table>
- <row>12</row>
- </item>
- <item>
- <table>22</table>
- <row>24</row>
- </item>
- <item>
- <table>22</table>
- <row>26</row>
- </item>
- <item>
- <table>22</table>
- <row>11</row>
- </item>
- <item>
- <table>23</table>
- <row>20</row>
- </item>
- <item>
- <table>23</table>
- <row>15</row>
- </item>
- <item>
- <table>22</table>
- <row>19</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>10</row>
- </item>
- <item>
- <table>23</table>
- <row>1</row>
- </item>
- <item>
- <table>23</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>8</row>
- </item>
- <item>
- <table>22</table>
- <row>23</row>
- </item>
- <item>
- <table>25</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>17</row>
- </item>
- <item>
- <table>23</table>
- <row>12</row>
- </item>
- <item>
- <table>23</table>
- <row>9</row>
- </item>
- <item>
- <table>22</table>
- <row>5</row>
- </item>
- <item>
- <table>23</table>
- <row>13</row>
- </item>
- <item>
- <table>22</table>
- <row>18</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>21</row>
- </item>
- <item>
- <table>23</table>
- <row>6</row>
- </item>
- <item>
- <table>24</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>10</row>
- </item>
- <item>
- <table>25</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>20</row>
- </item>
- <item>
- <table>22</table>
- <row>13</row>
- </item>
- <item>
- <table>22</table>
- <row>9</row>
- </item>
- <item>
- <table>23</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>22</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>8</row>
- </item>
- <item>
- <table>23</table>
- <row>5</row>
- </item>
- <item>
- <table>23</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>14</row>
- </item>
- <item>
- <table>23</table>
- <row>16</row>
- </item>
- <item>
- <table>22</table>
- <row>16</row>
- </item>
- <item>
- <table>22</table>
- <row>2</row>
- </item>
- <item>
- <table>25</table>
- <row>1</row>
- </item>
- <item>
- <table>0b</table>
- <row>2</row>
- </item>
- <item>
- <table>25</table>
- <row>2</row>
- </item>
- <item>
- <table>23</table>
- <row>14</row>
- </item>
- <item>
- <table>22</table>
- <row>25</row>
- </item>
- <item>
- <table>23</table>
- <row>18</row>
- </item>
- </profile>
- <profile>
- <name>MCP</name>
- <item>
- <table>17</table>
- <row>13</row>
- </item>
- <item>
- <table>17</table>
- <row>19</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>19</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>21</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>5</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>22</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>12</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>17</table>
- <row>17</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>18</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>12</row>
- </item>
- <item>
- <table>17</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>17</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>18</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>16</table>
- <row>8</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>5</row>
- </item>
- <item>
- <table>18</table>
- <row>15</row>
- </item>
- <item>
- <table>16</table>
- <row>14</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>21</row>
- </item>
- <item>
- <table>16</table>
- <row>7</row>
- </item>
- <item>
- <table>18</table>
- <row>14</row>
- </item>
- <item>
- <table>17</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>17</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>9</row>
- </item>
- <item>
- <table>16</table>
- <row>13</row>
- </item>
- <item>
- <table>17</table>
- <row>14</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>16</table>
- <row>20</row>
- </item>
- <item>
- <table>16</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>16</table>
- <row>16</row>
- </item>
- <item>
- <table>17</table>
- <row>20</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>15</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>8</row>
- </item>
- <item>
- <table>17</table>
- <row>16</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>16</table>
- <row>18</row>
- </item>
- <item>
- <table>16</table>
- <row>15</row>
- </item>
- </profile>
- <profile>
- <name>TBS</name>
- <item>
- <table>23</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>13</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>24</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>15</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>17</row>
- </item>
- <item>
- <table>2</table>
- <row>7</row>
- </item>
- <item>
- <table>24</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>22</row>
- </item>
- <item>
- <table>2</table>
- <row>23</row>
- </item>
- <item>
- <table>2</table>
- <row>21</row>
- </item>
- <item>
- <table>22</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>23</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>16</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>18</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>23</table>
- <row>6</row>
- </item>
- <item>
- <table>23</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>14</row>
- </item>
- <item>
- <table>22</table>
- <row>19</row>
- </item>
- <item>
- <table>0b</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>22</table>
- <row>13</row>
- </item>
- <item>
- <table>2</table>
- <row>19</row>
- </item>
- <item>
- <table>23</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>14</row>
- </item>
- <item>
- <table>2</table>
- <row>25</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>24</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>21</row>
- </item>
- <item>
- <table>2</table>
- <row>9</row>
- </item>
- <item>
- <table>2</table>
- <row>17</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>11</row>
- </item>
- <item>
- <table>24</table>
- <row>7</row>
- </item>
- <item>
- <table>23</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>20</row>
- </item>
- <item>
- <table>2</table>
- <row>24</row>
- </item>
- <item>
- <table>2</table>
- <row>10</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>22</table>
- <row>11</row>
- </item>
- <item>
- <table>24</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>22</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>0b</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>8</row>
- </item>
- <item>
- <table>22</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>20</row>
- </item>
- <item>
- <table>24</table>
- <row>5</row>
- </item>
- </profile>
- <profile>
- <name>CCP</name>
- <item>
- <table>12</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>14</row>
- </item>
- <item>
- <table>12</table>
- <row>13</row>
- </item>
- <item>
- <table>11</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>20</row>
- </item>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>13</table>
- <row>15</row>
- </item>
- <item>
- <table>12</table>
- <row>6</row>
- </item>
- <item>
- <table>13</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>21</row>
- </item>
- <item>
- <table>12</table>
- <row>17</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>11</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>15</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>18</row>
- </item>
- <item>
- <table>12</table>
- <row>9</row>
- </item>
- <item>
- <table>15</table>
- <row>15</row>
- </item>
- <item>
- <table>11</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>18</row>
- </item>
- <item>
- <table>15</table>
- <row>6</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>19</row>
- </item>
- <item>
- <table>12</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>11</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>5</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>22</row>
- </item>
- <item>
- <table>11</table>
- <row>5</row>
- </item>
- <item>
- <table>12</table>
- <row>8</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>22</row>
- </item>
- <item>
- <table>11</table>
- <row>15</row>
- </item>
- <item>
- <table>14</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>12</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>6</row>
- </item>
- <item>
- <table>11</table>
- <row>14</row>
- </item>
- <item>
- <table>12</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>13</row>
- </item>
- <item>
- <table>15</table>
- <row>14</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>15</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>17</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>11</row>
- </item>
- <item>
- <table>15</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>20</row>
- </item>
- <item>
- <table>12</table>
- <row>10</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>11</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>6</row>
- </item>
- <item>
- <table>11</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>7</row>
- </item>
- <item>
- <table>6</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>12</row>
- </item>
- <item>
- <table>11</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>15</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>19</row>
- </item>
- <item>
- <table>15</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>21</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>11</table>
- <row>16</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>13</row>
- </item>
- </profile>
- <profile>
- <name>CSIS</name>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>4</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>2</table>
- <row>5</row>
- </item>
- <item>
- <table>0a</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- </profile>
- <profile>
- <name>CSIP</name>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>6</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>15</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>9</row>
- </item>
- <item>
- <table>13</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>15</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>5</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>16</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>7</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>PACS</name>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>4</table>
- <row>11</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>12</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>15</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>16</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>4</table>
- <row>10</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>13</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>14</row>
- </item>
- </profile>
- <profile>
- <name>ASCS</name>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>9</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>6</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>BASS</name>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>8</row>
- </item>
- <item>
- <table>5</table>
- <row>5</row>
- </item>
- <item>
- <table>5</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>BAP</name>
- <item>
- <table>66</table>
- <row>2</row>
- </item>
- <item>
- <table>44</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>89</table>
- <row>2</row>
- </item>
- <item>
- <table>70</table>
- <row>11</row>
- </item>
- <item>
- <table>14</table>
- <row>11</row>
- </item>
- <item>
- <table>54</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>8</row>
- </item>
- <item>
- <table>38</table>
- <row>5</row>
- </item>
- <item>
- <table>36</table>
- <row>7</row>
- </item>
- <item>
- <table>44</table>
- <row>9</row>
- </item>
- <item>
- <table>89</table>
- <row>13</row>
- </item>
- <item>
- <table>53</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>15</row>
- </item>
- <item>
- <table>60</table>
- <row>4</row>
- </item>
- <item>
- <table>54</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>8</row>
- </item>
- <item>
- <table>89</table>
- <row>5</row>
- </item>
- <item>
- <table>23</table>
- <row>18</row>
- </item>
- <item>
- <table>38</table>
- <row>9</row>
- </item>
- <item>
- <table>38</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>13</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>46</table>
- <row>2</row>
- </item>
- <item>
- <table>69</table>
- <row>5</row>
- </item>
- <item>
- <table>68</table>
- <row>11</row>
- </item>
- <item>
- <table>69</table>
- <row>11</row>
- </item>
- <item>
- <table>55</table>
- <row>6</row>
- </item>
- <item>
- <table>33a</table>
- <row>7</row>
- </item>
- <item>
- <table>9a</table>
- <row>6</row>
- </item>
- <item>
- <table>84</table>
- <row>1</row>
- </item>
- <item>
- <table>38</table>
- <row>11</row>
- </item>
- <item>
- <table>22</table>
- <row>8</row>
- </item>
- <item>
- <table>68</table>
- <row>6</row>
- </item>
- <item>
- <table>90</table>
- <row>6</row>
- </item>
- <item>
- <table>80</table>
- <row>21</row>
- </item>
- <item>
- <table>39</table>
- <row>4</row>
- </item>
- <item>
- <table>21</table>
- <row>9</row>
- </item>
- <item>
- <table>39</table>
- <row>12</row>
- </item>
- <item>
- <table>32</table>
- <row>5</row>
- </item>
- <item>
- <table>55</table>
- <row>11</row>
- </item>
- <item>
- <table>90</table>
- <row>1</row>
- </item>
- <item>
- <table>90</table>
- <row>21</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>90</table>
- <row>4</row>
- </item>
- <item>
- <table>88</table>
- <row>3</row>
- </item>
- <item>
- <table>23</table>
- <row>10</row>
- </item>
- <item>
- <table>56</table>
- <row>14</row>
- </item>
- <item>
- <table>54</table>
- <row>11</row>
- </item>
- <item>
- <table>10</table>
- <row>5</row>
- </item>
- <item>
- <table>32</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>8</row>
- </item>
- <item>
- <table>15</table>
- <row>15</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>69</table>
- <row>16</row>
- </item>
- <item>
- <table>69</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>15</row>
- </item>
- <item>
- <table>14</table>
- <row>10</row>
- </item>
- <item>
- <table>54</table>
- <row>17</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>8</row>
- </item>
- <item>
- <table>82</table>
- <row>1</row>
- </item>
- <item>
- <table>56</table>
- <row>10</row>
- </item>
- <item>
- <table>69</table>
- <row>8</row>
- </item>
- <item>
- <table>39</table>
- <row>10</row>
- </item>
- <item>
- <table>12</table>
- <row>7</row>
- </item>
- <item>
- <table>40</table>
- <row>5</row>
- </item>
- <item>
- <table>37</table>
- <row>1</row>
- </item>
- <item>
- <table>43</table>
- <row>1</row>
- </item>
- <item>
- <table>51</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>65</table>
- <row>5</row>
- </item>
- <item>
- <table>17</table>
- <row>12</row>
- </item>
- <item>
- <table>55</table>
- <row>5</row>
- </item>
- <item>
- <table>59</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>46</table>
- <row>6</row>
- </item>
- <item>
- <table>21</table>
- <row>12</row>
- </item>
- <item>
- <table>20</table>
- <row>9</row>
- </item>
- <item>
- <table>40</table>
- <row>2</row>
- </item>
- <item>
- <table>73</table>
- <row>9</row>
- </item>
- <item>
- <table>36</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>8</row>
- </item>
- <item>
- <table>21</table>
- <row>8</row>
- </item>
- <item>
- <table>25</table>
- <row>2</row>
- </item>
- <item>
- <table>39</table>
- <row>9</row>
- </item>
- <item>
- <table>40</table>
- <row>9</row>
- </item>
- <item>
- <table>7</table>
- <row>10</row>
- </item>
- <item>
- <table>74</table>
- <row>4</row>
- </item>
- <item>
- <table>45</table>
- <row>6</row>
- </item>
- <item>
- <table>90</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>13</row>
- </item>
- <item>
- <table>45</table>
- <row>2</row>
- </item>
- <item>
- <table>46</table>
- <row>9</row>
- </item>
- <item>
- <table>12</table>
- <row>16</row>
- </item>
- <item>
- <table>15</table>
- <row>13</row>
- </item>
- <item>
- <table>73</table>
- <row>2</row>
- </item>
- <item>
- <table>54</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>3</row>
- </item>
- <item>
- <table>39</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>5</row>
- </item>
- <item>
- <table>87</table>
- <row>2</row>
- </item>
- <item>
- <table>52</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>2</row>
- </item>
- <item>
- <table>55</table>
- <row>10</row>
- </item>
- <item>
- <table>16</table>
- <row>15</row>
- </item>
- <item>
- <table>29</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>11</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>30</table>
- <row>3</row>
- </item>
- <item>
- <table>36</table>
- <row>6</row>
- </item>
- <item>
- <table>60</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>39</table>
- <row>16</row>
- </item>
- <item>
- <table>36</table>
- <row>12</row>
- </item>
- <item>
- <table>69</table>
- <row>10</row>
- </item>
- <item>
- <table>17</table>
- <row>6</row>
- </item>
- <item>
- <table>39</table>
- <row>7</row>
- </item>
- <item>
- <table>56</table>
- <row>5</row>
- </item>
- <item>
- <table>25</table>
- <row>3</row>
- </item>
- <item>
- <table>36</table>
- <row>17</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>16</table>
- <row>14</row>
- </item>
- <item>
- <table>51</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>13</row>
- </item>
- <item>
- <table>23</table>
- <row>7</row>
- </item>
- <item>
- <table>56</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>7</row>
- </item>
- <item>
- <table>77</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>16</row>
- </item>
- <item>
- <table>44</table>
- <row>8</row>
- </item>
- <item>
- <table>13</table>
- <row>16</row>
- </item>
- <item>
- <table>36</table>
- <row>5</row>
- </item>
- <item>
- <table>22</table>
- <row>4</row>
- </item>
- <item>
- <table>32</table>
- <row>7</row>
- </item>
- <item>
- <table>69</table>
- <row>13</row>
- </item>
- <item>
- <table>21</table>
- <row>7</row>
- </item>
- <item>
- <table>89</table>
- <row>9</row>
- </item>
- <item>
- <table>76</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>9</row>
- </item>
- <item>
- <table>61</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>9</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>31</table>
- <row>5</row>
- </item>
- <item>
- <table>58</table>
- <row>3</row>
- </item>
- <item>
- <table>69</table>
- <row>12</row>
- </item>
- <item>
- <table>41</table>
- <row>4</row>
- </item>
- <item>
- <table>15</table>
- <row>8</row>
- </item>
- <item>
- <table>72</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>3</row>
- </item>
- <item>
- <table>32</table>
- <row>10</row>
- </item>
- <item>
- <table>33</table>
- <row>6</row>
- </item>
- <item>
- <table>74</table>
- <row>22</row>
- </item>
- <item>
- <table>30</table>
- <row>1</row>
- </item>
- <item>
- <table>80</table>
- <row>1</row>
- </item>
- <item>
- <table>74</table>
- <row>2</row>
- </item>
- <item>
- <table>38</table>
- <row>6</row>
- </item>
- <item>
- <table>59</table>
- <row>12</row>
- </item>
- <item>
- <table>38</table>
- <row>13</row>
- </item>
- <item>
- <table>40</table>
- <row>15</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>5</row>
- </item>
- <item>
- <table>52</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>15</table>
- <row>12</row>
- </item>
- <item>
- <table>87</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>9</row>
- </item>
- <item>
- <table>88</table>
- <row>7</row>
- </item>
- <item>
- <table>21</table>
- <row>4</row>
- </item>
- <item>
- <table>92</table>
- <row>7</row>
- </item>
- <item>
- <table>56</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>12</table>
- <row>11</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>44</table>
- <row>1</row>
- </item>
- <item>
- <table>34</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>7</row>
- </item>
- <item>
- <table>56</table>
- <row>16</row>
- </item>
- <item>
- <table>70</table>
- <row>12</row>
- </item>
- <item>
- <table>61</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>36</table>
- <row>11</row>
- </item>
- <item>
- <table>36</table>
- <row>8</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>9</table>
- <row>4</row>
- </item>
- <item>
- <table>33a</table>
- <row>8</row>
- </item>
- <item>
- <table>73</table>
- <row>12</row>
- </item>
- <item>
- <table>33</table>
- <row>4</row>
- </item>
- <item>
- <table>55</table>
- <row>8</row>
- </item>
- <item>
- <table>73</table>
- <row>6</row>
- </item>
- <item>
- <table>33a</table>
- <row>4</row>
- </item>
- <item>
- <table>45</table>
- <row>11</row>
- </item>
- <item>
- <table>62</table>
- <row>1</row>
- </item>
- <item>
- <table>32</table>
- <row>3</row>
- </item>
- <item>
- <table>38</table>
- <row>8</row>
- </item>
- <item>
- <table>68</table>
- <row>8</row>
- </item>
- <item>
- <table>45</table>
- <row>9</row>
- </item>
- <item>
- <table>74</table>
- <row>6</row>
- </item>
- <item>
- <table>56</table>
- <row>9</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>55</table>
- <row>1</row>
- </item>
- <item>
- <table>36</table>
- <row>10</row>
- </item>
- <item>
- <table>45</table>
- <row>4</row>
- </item>
- <item>
- <table>52</table>
- <row>5</row>
- </item>
- <item>
- <table>15</table>
- <row>14</row>
- </item>
- <item>
- <table>40</table>
- <row>4</row>
- </item>
- <item>
- <table>82</table>
- <row>2</row>
- </item>
- <item>
- <table>68</table>
- <row>7</row>
- </item>
- <item>
- <table>44</table>
- <row>4</row>
- </item>
- <item>
- <table>54</table>
- <row>13</row>
- </item>
- <item>
- <table>37</table>
- <row>9</row>
- </item>
- <item>
- <table>56</table>
- <row>11</row>
- </item>
- <item>
- <table>16</table>
- <row>16</row>
- </item>
- <item>
- <table>74</table>
- <row>9</row>
- </item>
- <item>
- <table>44</table>
- <row>10</row>
- </item>
- <item>
- <table>33</table>
- <row>1</row>
- </item>
- <item>
- <table>70</table>
- <row>5</row>
- </item>
- <item>
- <table>45</table>
- <row>8</row>
- </item>
- <item>
- <table>55</table>
- <row>15</row>
- </item>
- <item>
- <table>36</table>
- <row>2</row>
- </item>
- <item>
- <table>65</table>
- <row>3</row>
- </item>
- <item>
- <table>55</table>
- <row>4</row>
- </item>
- <item>
- <table>69</table>
- <row>15</row>
- </item>
- <item>
- <table>9</table>
- <row>6</row>
- </item>
- <item>
- <table>70</table>
- <row>8</row>
- </item>
- <item>
- <table>54</table>
- <row>14</row>
- </item>
- <item>
- <table>74</table>
- <row>8</row>
- </item>
- <item>
- <table>22</table>
- <row>9</row>
- </item>
- <item>
- <table>68</table>
- <row>5</row>
- </item>
- <item>
- <table>76</table>
- <row>4</row>
- </item>
- <item>
- <table>39</table>
- <row>13</row>
- </item>
- <item>
- <table>37</table>
- <row>17</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>56</table>
- <row>2</row>
- </item>
- <item>
- <table>74</table>
- <row>15</row>
- </item>
- <item>
- <table>33</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>12</row>
- </item>
- <item>
- <table>36</table>
- <row>13</row>
- </item>
- <item>
- <table>16</table>
- <row>7</row>
- </item>
- <item>
- <table>37</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>15</row>
- </item>
- <item>
- <table>22</table>
- <row>3</row>
- </item>
- <item>
- <table>37</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>1</row>
- </item>
- <item>
- <table>89</table>
- <row>1</row>
- </item>
- <item>
- <table>32</table>
- <row>9</row>
- </item>
- <item>
- <table>48</table>
- <row>1</row>
- </item>
- <item>
- <table>92</table>
- <row>3</row>
- </item>
- <item>
- <table>27</table>
- <row>4</row>
- </item>
- <item>
- <table>54</table>
- <row>3</row>
- </item>
- <item>
- <table>54</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>14</row>
- </item>
- <item>
- <table>55</table>
- <row>12</row>
- </item>
- <item>
- <table>80</table>
- <row>5</row>
- </item>
- <item>
- <table>59</table>
- <row>10</row>
- </item>
- <item>
- <table>39</table>
- <row>6</row>
- </item>
- <item>
- <table>9</table>
- <row>8</row>
- </item>
- <item>
- <table>73</table>
- <row>3</row>
- </item>
- <item>
- <table>50</table>
- <row>1</row>
- </item>
- <item>
- <table>70</table>
- <row>6</row>
- </item>
- <item>
- <table>40</table>
- <row>8</row>
- </item>
- <item>
- <table>22</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>17</row>
- </item>
- <item>
- <table>86</table>
- <row>1</row>
- </item>
- <item>
- <table>44</table>
- <row>5</row>
- </item>
- <item>
- <table>80</table>
- <row>10</row>
- </item>
- <item>
- <table>38</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>13</row>
- </item>
- <item>
- <table>39</table>
- <row>14</row>
- </item>
- <item>
- <table>40</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>6</row>
- </item>
- <item>
- <table>34</table>
- <row>5</row>
- </item>
- <item>
- <table>45</table>
- <row>3</row>
- </item>
- <item>
- <table>60</table>
- <row>2</row>
- </item>
- <item>
- <table>37</table>
- <row>11</row>
- </item>
- <item>
- <table>41</table>
- <row>14</row>
- </item>
- <item>
- <table>86</table>
- <row>4</row>
- </item>
- <item>
- <table>67</table>
- <row>3</row>
- </item>
- <item>
- <table>9a</table>
- <row>4</row>
- </item>
- <item>
- <table>33a</table>
- <row>5</row>
- </item>
- <item>
- <table>53</table>
- <row>2</row>
- </item>
- <item>
- <table>89</table>
- <row>11</row>
- </item>
- <item>
- <table>1</table>
- <row>6</row>
- </item>
- <item>
- <table>59</table>
- <row>8</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>39</table>
- <row>5</row>
- </item>
- <item>
- <table>74</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>88</table>
- <row>4</row>
- </item>
- <item>
- <table>55</table>
- <row>16</row>
- </item>
- <item>
- <table>46</table>
- <row>4</row>
- </item>
- <item>
- <table>69</table>
- <row>4</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>28</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>10</row>
- </item>
- <item>
- <table>16</table>
- <row>9</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>78</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>14</row>
- </item>
- <item>
- <table>20</table>
- <row>5</row>
- </item>
- <item>
- <table>86</table>
- <row>3</row>
- </item>
- <item>
- <table>69</table>
- <row>14</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>4</row>
- </item>
- <item>
- <table>56</table>
- <row>8</row>
- </item>
- <item>
- <table>38</table>
- <row>14</row>
- </item>
- <item>
- <table>20</table>
- <row>11</row>
- </item>
- <item>
- <table>68</table>
- <row>17</row>
- </item>
- <item>
- <table>37</table>
- <row>16</row>
- </item>
- <item>
- <table>45</table>
- <row>13</row>
- </item>
- <item>
- <table>26</table>
- <row>1</row>
- </item>
- <item>
- <table>32</table>
- <row>6</row>
- </item>
- <item>
- <table>15</table>
- <row>11</row>
- </item>
- <item>
- <table>61</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>12</row>
- </item>
- <item>
- <table>90</table>
- <row>20</row>
- </item>
- <item>
- <table>37</table>
- <row>10</row>
- </item>
- <item>
- <table>39</table>
- <row>11</row>
- </item>
- <item>
- <table>74</table>
- <row>23</row>
- </item>
- <item>
- <table>14</table>
- <row>16</row>
- </item>
- <item>
- <table>89</table>
- <row>3</row>
- </item>
- <item>
- <table>41</table>
- <row>9</row>
- </item>
- <item>
- <table>37</table>
- <row>6</row>
- </item>
- <item>
- <table>80</table>
- <row>6</row>
- </item>
- <item>
- <table>80</table>
- <row>2</row>
- </item>
- <item>
- <table>9a</table>
- <row>1</row>
- </item>
- <item>
- <table>59</table>
- <row>3</row>
- </item>
- <item>
- <table>17</table>
- <row>10</row>
- </item>
- <item>
- <table>54</table>
- <row>16</row>
- </item>
- <item>
- <table>74</table>
- <row>11</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>9a</table>
- <row>2</row>
- </item>
- <item>
- <table>48</table>
- <row>2</row>
- </item>
- <item>
- <table>44</table>
- <row>7</row>
- </item>
- <item>
- <table>41</table>
- <row>1</row>
- </item>
- <item>
- <table>33</table>
- <row>8</row>
- </item>
- <item>
- <table>20</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>10</row>
- </item>
- <item>
- <table>44</table>
- <row>14</row>
- </item>
- <item>
- <table>89</table>
- <row>10</row>
- </item>
- <item>
- <table>22</table>
- <row>12</row>
- </item>
- <item>
- <table>73</table>
- <row>4</row>
- </item>
- <item>
- <table>51</table>
- <row>2</row>
- </item>
- <item>
- <table>87</table>
- <row>3</row>
- </item>
- <item>
- <table>41</table>
- <row>11</row>
- </item>
- <item>
- <table>15</table>
- <row>16</row>
- </item>
- <item>
- <table>54</table>
- <row>9</row>
- </item>
- <item>
- <table>31</table>
- <row>6</row>
- </item>
- <item>
- <table>33a</table>
- <row>3</row>
- </item>
- <item>
- <table>72</table>
- <row>1</row>
- </item>
- <item>
- <table>66</table>
- <row>1</row>
- </item>
- <item>
- <table>45</table>
- <row>10</row>
- </item>
- <item>
- <table>58</table>
- <row>2</row>
- </item>
- <item>
- <table>23</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>73</table>
- <row>5</row>
- </item>
- <item>
- <table>28</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>15</row>
- </item>
- <item>
- <table>38</table>
- <row>16</row>
- </item>
- <item>
- <table>36</table>
- <row>4</row>
- </item>
- <item>
- <table>68</table>
- <row>14</row>
- </item>
- <item>
- <table>34</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>76</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>12</row>
- </item>
- <item>
- <table>59</table>
- <row>9</row>
- </item>
- <item>
- <table>33a</table>
- <row>6</row>
- </item>
- <item>
- <table>34</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>5</row>
- </item>
- <item>
- <table>71</table>
- <row>1</row>
- </item>
- <item>
- <table>54</table>
- <row>15</row>
- </item>
- <item>
- <table>16</table>
- <row>12</row>
- </item>
- <item>
- <table>34</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- <item>
- <table>65</table>
- <row>4</row>
- </item>
- <item>
- <table>51</table>
- <row>5</row>
- </item>
- <item>
- <table>46</table>
- <row>14</row>
- </item>
- <item>
- <table>68</table>
- <row>2</row>
- </item>
- <item>
- <table>31</table>
- <row>3</row>
- </item>
- <item>
- <table>70</table>
- <row>9</row>
- </item>
- <item>
- <table>21</table>
- <row>10</row>
- </item>
- <item>
- <table>31</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>55</table>
- <row>2</row>
- </item>
- <item>
- <table>90</table>
- <row>3</row>
- </item>
- <item>
- <table>65</table>
- <row>2</row>
- </item>
- <item>
- <table>46</table>
- <row>5</row>
- </item>
- <item>
- <table>76</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>3</row>
- </item>
- <item>
- <table>21</table>
- <row>6</row>
- </item>
- <item>
- <table>88</table>
- <row>6</row>
- </item>
- <item>
- <table>54</table>
- <row>2</row>
- </item>
- <item>
- <table>89</table>
- <row>8</row>
- </item>
- <item>
- <table>13</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>10</row>
- </item>
- <item>
- <table>89</table>
- <row>12</row>
- </item>
- <item>
- <table>22</table>
- <row>11</row>
- </item>
- <item>
- <table>68</table>
- <row>13</row>
- </item>
- <item>
- <table>45</table>
- <row>12</row>
- </item>
- <item>
- <table>73</table>
- <row>7</row>
- </item>
- <item>
- <table>46</table>
- <row>3</row>
- </item>
- <item>
- <table>90</table>
- <row>5</row>
- </item>
- <item>
- <table>92</table>
- <row>1</row>
- </item>
- <item>
- <table>25</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>23</table>
- <row>19</row>
- </item>
- <item>
- <table>70</table>
- <row>16</row>
- </item>
- <item>
- <table>39</table>
- <row>2</row>
- </item>
- <item>
- <table>73</table>
- <row>8</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>52</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>33a</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>15</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>64</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>13</row>
- </item>
- <item>
- <table>70</table>
- <row>15</row>
- </item>
- <item>
- <table>31</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>7</row>
- </item>
- <item>
- <table>85</table>
- <row>4</row>
- </item>
- <item>
- <table>9a</table>
- <row>3</row>
- </item>
- <item>
- <table>33a</table>
- <row>2</row>
- </item>
- <item>
- <table>36</table>
- <row>15</row>
- </item>
- <item>
- <table>32</table>
- <row>2</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>36</table>
- <row>14</row>
- </item>
- <item>
- <table>15</table>
- <row>5</row>
- </item>
- <item>
- <table>22</table>
- <row>10</row>
- </item>
- <item>
- <table>83</table>
- <row>1</row>
- </item>
- <item>
- <table>56</table>
- <row>13</row>
- </item>
- <item>
- <table>12</table>
- <row>8</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>33</table>
- <row>2</row>
- </item>
- <item>
- <table>48</table>
- <row>3</row>
- </item>
- <item>
- <table>59</table>
- <row>5</row>
- </item>
- <item>
- <table>69</table>
- <row>7</row>
- </item>
- <item>
- <table>13</table>
- <row>13</row>
- </item>
- <item>
- <table>74</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>13</row>
- </item>
- <item>
- <table>89</table>
- <row>7</row>
- </item>
- <item>
- <table>20</table>
- <row>8</row>
- </item>
- <item>
- <table>69</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>11</row>
- </item>
- <item>
- <table>33</table>
- <row>5</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>70</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>23</table>
- <row>5</row>
- </item>
- <item>
- <table>57</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>16</row>
- </item>
- <item>
- <table>44</table>
- <row>15</row>
- </item>
- <item>
- <table>20</table>
- <row>6</row>
- </item>
- <item>
- <table>15</table>
- <row>10</row>
- </item>
- <item>
- <table>15</table>
- <row>3</row>
- </item>
- <item>
- <table>72</table>
- <row>2</row>
- </item>
- <item>
- <table>35</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>14</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>33</table>
- <row>7</row>
- </item>
- <item>
- <table>13</table>
- <row>12</row>
- </item>
- <item>
- <table>65</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>3</row>
- </item>
- <item>
- <table>85</table>
- <row>2</row>
- </item>
- <item>
- <table>90</table>
- <row>11</row>
- </item>
- <item>
- <table>41</table>
- <row>12</row>
- </item>
- <item>
- <table>59</table>
- <row>4</row>
- </item>
- <item>
- <table>68</table>
- <row>1</row>
- </item>
- <item>
- <table>56</table>
- <row>12</row>
- </item>
- <item>
- <table>73</table>
- <row>11</row>
- </item>
- <item>
- <table>37</table>
- <row>3</row>
- </item>
- <item>
- <table>54</table>
- <row>6</row>
- </item>
- <item>
- <table>92</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>11</row>
- </item>
- <item>
- <table>10</table>
- <row>3</row>
- </item>
- <item>
- <table>60</table>
- <row>3</row>
- </item>
- <item>
- <table>45</table>
- <row>7</row>
- </item>
- <item>
- <table>27</table>
- <row>2</row>
- </item>
- <item>
- <table>69</table>
- <row>3</row>
- </item>
- <item>
- <table>44</table>
- <row>11</row>
- </item>
- <item>
- <table>45</table>
- <row>14</row>
- </item>
- <item>
- <table>73</table>
- <row>10</row>
- </item>
- <item>
- <table>87</table>
- <row>4</row>
- </item>
- <item>
- <table>74</table>
- <row>10</row>
- </item>
- <item>
- <table>44</table>
- <row>16</row>
- </item>
- <item>
- <table>80</table>
- <row>22</row>
- </item>
- <item>
- <table>70</table>
- <row>1</row>
- </item>
- <item>
- <table>74</table>
- <row>7</row>
- </item>
- <item>
- <table>54</table>
- <row>8</row>
- </item>
- <item>
- <table>40</table>
- <row>11</row>
- </item>
- <item>
- <table>68</table>
- <row>3</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>21</table>
- <row>3</row>
- </item>
- <item>
- <table>38</table>
- <row>3</row>
- </item>
- <item>
- <table>80</table>
- <row>3</row>
- </item>
- <item>
- <table>51</table>
- <row>3</row>
- </item>
- <item>
- <table>70</table>
- <row>3</row>
- </item>
- <item>
- <table>54</table>
- <row>5</row>
- </item>
- <item>
- <table>61</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>17</row>
- </item>
- <item>
- <table>40</table>
- <row>13</row>
- </item>
- <item>
- <table>38</table>
- <row>2</row>
- </item>
- <item>
- <table>61</table>
- <row>6</row>
- </item>
- <item>
- <table>61</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>11</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>80</table>
- <row>7</row>
- </item>
- <item>
- <table>86</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>6</row>
- </item>
- <item>
- <table>15</table>
- <row>4</row>
- </item>
- <item>
- <table>68</table>
- <row>16</row>
- </item>
- <item>
- <table>31</table>
- <row>7</row>
- </item>
- <item>
- <table>41</table>
- <row>10</row>
- </item>
- <item>
- <table>63</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>88</table>
- <row>1</row>
- </item>
- <item>
- <table>56</table>
- <row>3</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>6</row>
- </item>
- <item>
- <table>88</table>
- <row>2</row>
- </item>
- <item>
- <table>15</table>
- <row>9</row>
- </item>
- <item>
- <table>45</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>11</row>
- </item>
- <item>
- <table>70</table>
- <row>7</row>
- </item>
- <item>
- <table>17</table>
- <row>3</row>
- </item>
- <item>
- <table>32</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>16</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>9</row>
- </item>
- <item>
- <table>15</table>
- <row>7</row>
- </item>
- <item>
- <table>56</table>
- <row>15</row>
- </item>
- <item>
- <table>9a</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>14</row>
- </item>
- <item>
- <table>36</table>
- <row>9</row>
- </item>
- <item>
- <table>37</table>
- <row>8</row>
- </item>
- <item>
- <table>35</table>
- <row>1</row>
- </item>
- <item>
- <table>68</table>
- <row>10</row>
- </item>
- <item>
- <table>41</table>
- <row>5</row>
- </item>
- <item>
- <table>68</table>
- <row>12</row>
- </item>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>69</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>7</row>
- </item>
- <item>
- <table>69</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>36</table>
- <row>16</row>
- </item>
- <item>
- <table>68</table>
- <row>9</row>
- </item>
- <item>
- <table>40</table>
- <row>10</row>
- </item>
- <item>
- <table>22</table>
- <row>6</row>
- </item>
- <item>
- <table>44</table>
- <row>3</row>
- </item>
- <item>
- <table>54</table>
- <row>10</row>
- </item>
- <item>
- <table>56</table>
- <row>4</row>
- </item>
- <item>
- <table>49</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>14</row>
- </item>
- <item>
- <table>23</table>
- <row>2</row>
- </item>
- <item>
- <table>44</table>
- <row>12</row>
- </item>
- <item>
- <table>45</table>
- <row>5</row>
- </item>
- <item>
- <table>68</table>
- <row>4</row>
- </item>
- <item>
- <table>67</table>
- <row>1</row>
- </item>
- <item>
- <table>38</table>
- <row>10</row>
- </item>
- <item>
- <table>10</table>
- <row>4</row>
- </item>
- <item>
- <table>38</table>
- <row>12</row>
- </item>
- <item>
- <table>68</table>
- <row>15</row>
- </item>
- <item>
- <table>70</table>
- <row>14</row>
- </item>
- <item>
- <table>55</table>
- <row>14</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>9a</table>
- <row>7</row>
- </item>
- <item>
- <table>38</table>
- <row>1</row>
- </item>
- <item>
- <table>9a</table>
- <row>8</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>70</table>
- <row>13</row>
- </item>
- <item>
- <table>39</table>
- <row>8</row>
- </item>
- <item>
- <table>20</table>
- <row>10</row>
- </item>
- <item>
- <table>70</table>
- <row>4</row>
- </item>
- <item>
- <table>58</table>
- <row>1</row>
- </item>
- <item>
- <table>67</table>
- <row>2</row>
- </item>
- <item>
- <table>41</table>
- <row>15</row>
- </item>
- <item>
- <table>55</table>
- <row>13</row>
- </item>
- <item>
- <table>73</table>
- <row>1</row>
- </item>
- <item>
- <table>82</table>
- <row>3</row>
- </item>
- <item>
- <table>52</table>
- <row>4</row>
- </item>
- <item>
- <table>32</table>
- <row>8</row>
- </item>
- <item>
- <table>44</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>46</table>
- <row>1</row>
- </item>
- <item>
- <table>55</table>
- <row>7</row>
- </item>
- <item>
- <table>40</table>
- <row>7</row>
- </item>
- <item>
- <table>90</table>
- <row>8</row>
- </item>
- <item>
- <table>44</table>
- <row>6</row>
- </item>
- <item>
- <table>42</table>
- <row>1</row>
- </item>
- <item>
- <table>9</table>
- <row>7</row>
- </item>
- <item>
- <table>36</table>
- <row>3</row>
- </item>
- <item>
- <table>55</table>
- <row>3</row>
- </item>
- <item>
- <table>30</table>
- <row>2</row>
- </item>
- <item>
- <table>89</table>
- <row>6</row>
- </item>
- <item>
- <table>59</table>
- <row>2</row>
- </item>
- <item>
- <table>9</table>
- <row>5</row>
- </item>
- <item>
- <table>39</table>
- <row>15</row>
- </item>
- <item>
- <table>39</table>
- <row>1</row>
- </item>
- <item>
- <table>55</table>
- <row>9</row>
- </item>
- <item>
- <table>46</table>
- <row>15</row>
- </item>
- <item>
- <table>31</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>14</row>
- </item>
- <item>
- <table>90</table>
- <row>7</row>
- </item>
- <item>
- <table>70</table>
- <row>10</row>
- </item>
- <item>
- <table>51</table>
- <row>6</row>
- </item>
- <item>
- <table>38</table>
- <row>15</row>
- </item>
- <item>
- <table>79</table>
- <row>2</row>
- </item>
- <item>
- <table>17</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>41</table>
- <row>2</row>
- </item>
- <item>
- <table>89</table>
- <row>4</row>
- </item>
- <item>
- <table>41</table>
- <row>7</row>
- </item>
- <item>
- <table>29</table>
- <row>2</row>
- </item>
- <item>
- <table>56</table>
- <row>7</row>
- </item>
- </profile>
- <profile>
- <name>CAS</name>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>CAP</name>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>11</row>
- </item>
- <item>
- <table>26</table>
- <row>5</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>26</table>
- <row>6</row>
- </item>
- <item>
- <table>31</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>19</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>6</row>
- </item>
- <item>
- <table>22</table>
- <row>8</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>6a</table>
- <row>2</row>
- </item>
- <item>
- <table>26</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>5</row>
- </item>
- <item>
- <table>23</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>9</row>
- </item>
- <item>
- <table>28</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>7</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>33</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>2</row>
- </item>
- <item>
- <table>28</table>
- <row>9</row>
- </item>
- <item>
- <table>32</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>8</row>
- </item>
- <item>
- <table>11</table>
- <row>5</row>
- </item>
- <item>
- <table>22</table>
- <row>7</row>
- </item>
- <item>
- <table>26</table>
- <row>7</row>
- </item>
- <item>
- <table>21</table>
- <row>3</row>
- </item>
- <item>
- <table>22</table>
- <row>4</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>31</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>10</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>31</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>12</row>
- </item>
- <item>
- <table>22</table>
- <row>11</row>
- </item>
- <item>
- <table>33</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>8</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>9</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>26</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>3</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>23</table>
- <row>1</row>
- </item>
- <item>
- <table>29</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>28</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>11</table>
- <row>6</row>
- </item>
- <item>
- <table>6a</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>7</row>
- </item>
- <item>
- <table>22</table>
- <row>10</row>
- </item>
- <item>
- <table>8</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>9</row>
- </item>
- <item>
- <table>22</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>6</row>
- </item>
- <item>
- <table>7</table>
- <row>5</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>27</table>
- <row>5</row>
- </item>
- <item>
- <table>11</table>
- <row>9</row>
- </item>
- <item>
- <table>27</table>
- <row>4</row>
- </item>
- <item>
- <table>11</table>
- <row>12</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>19</table>
- <row>4</row>
- </item>
- <item>
- <table>11</table>
- <row>4</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>HAS</name>
- <item>
- <table>5</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>10</row>
- </item>
- <item>
- <table>4</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>4</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>12</row>
- </item>
- <item>
- <table>4</table>
- <row>7</row>
- </item>
- <item>
- <table>3</table>
- <row>14</row>
- </item>
- <item>
- <table>3</table>
- <row>11</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>5</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>4</row>
- </item>
- <item>
- <table>5</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>4</table>
- <row>4</row>
- </item>
- <item>
- <table>4</table>
- <row>5</row>
- </item>
- <item>
- <table>5</table>
- <row>5</row>
- </item>
- <item>
- <table>3</table>
- <row>6</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>9</row>
- </item>
- <item>
- <table>3</table>
- <row>10</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>13</row>
- </item>
- <item>
- <table>3</table>
- <row>8</row>
- </item>
- <item>
- <table>4</table>
- <row>9</row>
- </item>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>1a</row>
- </item>
- <item>
- <table>4</table>
- <row>6</row>
- </item>
- </profile>
- <profile>
- <name>HAP</name>
- <item>
- <table>12</table>
- <row>5</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>92</table>
- <row>1</row>
- </item>
- <item>
- <table>50</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>51</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>43</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>7</row>
- </item>
- <item>
- <table>90</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>2</row>
- </item>
- <item>
- <table>50</table>
- <row>2</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>24</table>
- <row>3</row>
- </item>
- <item>
- <table>13</table>
- <row>6</row>
- </item>
- <item>
- <table>26</table>
- <row>1</row>
- </item>
- <item>
- <table>43</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>46</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>43</table>
- <row>4</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>24</table>
- <row>4</row>
- </item>
- <item>
- <table>24</table>
- <row>6</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>19</table>
- <row>2</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>5</row>
- </item>
- <item>
- <table>43</table>
- <row>1</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>46</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>4</row>
- </item>
- </profile>
- <profile>
- <name>TMAP</name>
- <item>
- <table>95</table>
- <row>5</row>
- </item>
- <item>
- <table>114</table>
- <row>4</row>
- </item>
- <item>
- <table>52</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>7</row>
- </item>
- <item>
- <table>57</table>
- <row>3</row>
- </item>
- <item>
- <table>56</table>
- <row>12</row>
- </item>
- <item>
- <table>56</table>
- <row>14</row>
- </item>
- <item>
- <table>79</table>
- <row>1</row>
- </item>
- <item>
- <table>79</table>
- <row>2</row>
- </item>
- <item>
- <table>153</table>
- <row>6</row>
- </item>
- <item>
- <table>57</table>
- <row>2</row>
- </item>
- <item>
- <table>95</table>
- <row>7</row>
- </item>
- <item>
- <table>76</table>
- <row>3</row>
- </item>
- <item>
- <table>116</table>
- <row>12</row>
- </item>
- <item>
- <table>95</table>
- <row>3</row>
- </item>
- <item>
- <table>115</table>
- <row>3</row>
- </item>
- <item>
- <table>96</table>
- <row>15</row>
- </item>
- <item>
- <table>56</table>
- <row>1</row>
- </item>
- <item>
- <table>116</table>
- <row>4</row>
- </item>
- <item>
- <table>116</table>
- <row>5</row>
- </item>
- <item>
- <table>56</table>
- <row>5</row>
- </item>
- <item>
- <table>78</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>8</row>
- </item>
- <item>
- <table>116</table>
- <row>11</row>
- </item>
- <item>
- <table>70</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>16</row>
- </item>
- <item>
- <table>118</table>
- <row>2</row>
- </item>
- <item>
- <table>76</table>
- <row>5</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>93</table>
- <row>1</row>
- </item>
- <item>
- <table>55</table>
- <row>3</row>
- </item>
- <item>
- <table>95</table>
- <row>8</row>
- </item>
- <item>
- <table>113</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>12</row>
- </item>
- <item>
- <table>99</table>
- <row>2</row>
- </item>
- <item>
- <table>96</table>
- <row>7</row>
- </item>
- <item>
- <table>94</table>
- <row>1</row>
- </item>
- <item>
- <table>151</table>
- <row>3</row>
- </item>
- <item>
- <table>98</table>
- <row>3</row>
- </item>
- <item>
- <table>116</table>
- <row>9</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>150</table>
- <row>1</row>
- </item>
- <item>
- <table>153</table>
- <row>4</row>
- </item>
- <item>
- <table>116</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>2</row>
- </item>
- <item>
- <table>116</table>
- <row>13</row>
- </item>
- <item>
- <table>75</table>
- <row>3</row>
- </item>
- <item>
- <table>115</table>
- <row>5</row>
- </item>
- <item>
- <table>55</table>
- <row>5</row>
- </item>
- <item>
- <table>116</table>
- <row>6</row>
- </item>
- <item>
- <table>153</table>
- <row>5</row>
- </item>
- <item>
- <table>57</table>
- <row>1</row>
- </item>
- <item>
- <table>112</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>97</table>
- <row>1</row>
- </item>
- <item>
- <table>116</table>
- <row>7</row>
- </item>
- <item>
- <table>96</table>
- <row>13</row>
- </item>
- <item>
- <table>56</table>
- <row>9</row>
- </item>
- <item>
- <table>115</table>
- <row>1</row>
- </item>
- <item>
- <table>151</table>
- <row>6</row>
- </item>
- <item>
- <table>56</table>
- <row>6</row>
- </item>
- <item>
- <table>55</table>
- <row>4</row>
- </item>
- <item>
- <table>78</table>
- <row>3</row>
- </item>
- <item>
- <table>76</table>
- <row>6</row>
- </item>
- <item>
- <table>100</table>
- <row>2</row>
- </item>
- <item>
- <table>110</table>
- <row>1</row>
- </item>
- <item>
- <table>98</table>
- <row>2</row>
- </item>
- <item>
- <table>56</table>
- <row>4</row>
- </item>
- <item>
- <table>76</table>
- <row>4</row>
- </item>
- <item>
- <table>95</table>
- <row>4</row>
- </item>
- <item>
- <table>118</table>
- <row>3</row>
- </item>
- <item>
- <table>116</table>
- <row>2</row>
- </item>
- <item>
- <table>116</table>
- <row>15</row>
- </item>
- <item>
- <table>75</table>
- <row>1</row>
- </item>
- <item>
- <table>114</table>
- <row>1</row>
- </item>
- <item>
- <table>55</table>
- <row>8</row>
- </item>
- <item>
- <table>56</table>
- <row>3</row>
- </item>
- <item>
- <table>75</table>
- <row>4</row>
- </item>
- <item>
- <table>74</table>
- <row>3</row>
- </item>
- <item>
- <table>94</table>
- <row>4</row>
- </item>
- <item>
- <table>151</table>
- <row>1</row>
- </item>
- <item>
- <table>119</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>6</row>
- </item>
- <item>
- <table>116</table>
- <row>16</row>
- </item>
- <item>
- <table>95</table>
- <row>2</row>
- </item>
- <item>
- <table>56</table>
- <row>7</row>
- </item>
- <item>
- <table>77</table>
- <row>1</row>
- </item>
- <item>
- <table>54</table>
- <row>3</row>
- </item>
- <item>
- <table>97</table>
- <row>2</row>
- </item>
- <item>
- <table>54</table>
- <row>1</row>
- </item>
- <item>
- <table>115</table>
- <row>4</row>
- </item>
- <item>
- <table>53</table>
- <row>1</row>
- </item>
- <item>
- <table>117</table>
- <row>1</row>
- </item>
- <item>
- <table>76</table>
- <row>2</row>
- </item>
- <item>
- <table>78</table>
- <row>2</row>
- </item>
- <item>
- <table>96</table>
- <row>6</row>
- </item>
- <item>
- <table>131</table>
- <row>1</row>
- </item>
- <item>
- <table>156</table>
- <row>1</row>
- </item>
- <item>
- <table>120</table>
- <row>1</row>
- </item>
- <item>
- <table>152</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>74</table>
- <row>5</row>
- </item>
- <item>
- <table>115</table>
- <row>2</row>
- </item>
- <item>
- <table>96</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>3</row>
- </item>
- <item>
- <table>75</table>
- <row>2</row>
- </item>
- <item>
- <table>115</table>
- <row>6</row>
- </item>
- <item>
- <table>154</table>
- <row>1</row>
- </item>
- <item>
- <table>114</table>
- <row>3</row>
- </item>
- <item>
- <table>118</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>4</row>
- </item>
- <item>
- <table>56</table>
- <row>10</row>
- </item>
- <item>
- <table>55</table>
- <row>6</row>
- </item>
- <item>
- <table>52</table>
- <row>1</row>
- </item>
- <item>
- <table>75</table>
- <row>5</row>
- </item>
- <item>
- <table>56</table>
- <row>11</row>
- </item>
- <item>
- <table>96</table>
- <row>10</row>
- </item>
- <item>
- <table>94</table>
- <row>3</row>
- </item>
- <item>
- <table>56</table>
- <row>16</row>
- </item>
- <item>
- <table>72</table>
- <row>2</row>
- </item>
- <item>
- <table>117</table>
- <row>2</row>
- </item>
- <item>
- <table>72</table>
- <row>1</row>
- </item>
- <item>
- <table>116</table>
- <row>3</row>
- </item>
- <item>
- <table>116</table>
- <row>14</row>
- </item>
- <item>
- <table>116</table>
- <row>8</row>
- </item>
- <item>
- <table>116</table>
- <row>10</row>
- </item>
- <item>
- <table>96</table>
- <row>14</row>
- </item>
- <item>
- <table>56</table>
- <row>13</row>
- </item>
- <item>
- <table>56</table>
- <row>15</row>
- </item>
- <item>
- <table>75</table>
- <row>6</row>
- </item>
- <item>
- <table>121</table>
- <row>2</row>
- </item>
- <item>
- <table>77</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>8</row>
- </item>
- <item>
- <table>98</table>
- <row>1</row>
- </item>
- <item>
- <table>115</table>
- <row>8</row>
- </item>
- <item>
- <table>96</table>
- <row>9</row>
- </item>
- <item>
- <table>95</table>
- <row>1</row>
- </item>
- <item>
- <table>115</table>
- <row>7</row>
- </item>
- <item>
- <table>92</table>
- <row>2</row>
- </item>
- <item>
- <table>96</table>
- <row>11</row>
- </item>
- <item>
- <table>100</table>
- <row>1</row>
- </item>
- <item>
- <table>121</table>
- <row>1</row>
- </item>
- <item>
- <table>76</table>
- <row>1</row>
- </item>
- <item>
- <table>99</table>
- <row>1</row>
- </item>
- <item>
- <table>55</table>
- <row>2</row>
- </item>
- <item>
- <table>153</table>
- <row>2</row>
- </item>
- <item>
- <table>74</table>
- <row>4</row>
- </item>
- <item>
- <table>119</table>
- <row>2</row>
- </item>
- <item>
- <table>90</table>
- <row>1</row>
- </item>
- <item>
- <table>112</table>
- <row>2</row>
- </item>
- <item>
- <table>56</table>
- <row>8</row>
- </item>
- <item>
- <table>56</table>
- <row>2</row>
- </item>
- <item>
- <table>50</table>
- <row>1</row>
- </item>
- <item>
- <table>74</table>
- <row>1</row>
- </item>
- <item>
- <table>96</table>
- <row>5</row>
- </item>
- <item>
- <table>55</table>
- <row>7</row>
- </item>
- <item>
- <table>151</table>
- <row>5</row>
- </item>
- <item>
- <table>92</table>
- <row>1</row>
- </item>
- <item>
- <table>151</table>
- <row>4</row>
- </item>
- <item>
- <table>151</table>
- <row>2</row>
- </item>
- <item>
- <table>94</table>
- <row>5</row>
- </item>
- <item>
- <table>55</table>
- <row>1</row>
- </item>
- <item>
- <table>95</table>
- <row>6</row>
- </item>
- <item>
- <table>74</table>
- <row>6</row>
- </item>
- </profile>
- <profile>
- <name>PBP</name>
- <item>
- <table>13</table>
- <row>4</row>
- </item>
- <item>
- <table>6</table>
- <row>8</row>
- </item>
- <item>
- <table>8</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>4</row>
- </item>
- <item>
- <table>7</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>4</row>
- </item>
- <item>
- <table>8</table>
- <row>10</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>13</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>9</row>
- </item>
- <item>
- <table>14</table>
- <row>10</row>
- </item>
- <item>
- <table>7</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>13</table>
- <row>3</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>8</table>
- <row>11</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>8</table>
- <row>8</row>
- </item>
- <item>
- <table>6</table>
- <row>7</row>
- </item>
- <item>
- <table>7</table>
- <row>1</row>
- </item>
- <item>
- <table>5</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>8</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>6</table>
- <row>5</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>3</row>
- </item>
- <item>
- <table>5</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>7</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>8</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>11</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>8</table>
- <row>3</row>
- </item>
- <item>
- <table>9</table>
- <row>1</row>
- </item>
- <item>
- <table>6</table>
- <row>6</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>MBTM</name>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>10</table>
- <row>2</row>
- </item>
- </profile>
- <profile>
- <name>DFUM</name>
- <item>
- <table>3</table>
- <row>3</row>
- </item>
- <item>
- <table>3</table>
- <row>2</row>
- </item>
- <item>
- <table>22</table>
- <row>3</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>30</table>
- <row>1</row>
- </item>
- <item>
- <table>0</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>3</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>21</table>
- <row>2</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- </profile>
- <profile>
- <name>GMAP</name>
- <item>
- <table>79</table>
- <row>2</row>
- </item>
- <item>
- <table>32</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>92</row>
- </item>
- <item>
- <table>14</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>33</row>
- </item>
- <item>
- <table>20</table>
- <row>63</row>
- </item>
- <item>
- <table>20</table>
- <row>85</row>
- </item>
- <item>
- <table>20</table>
- <row>29</row>
- </item>
- <item>
- <table>102</table>
- <row>1</row>
- </item>
- <item>
- <table>107</table>
- <row>2</row>
- </item>
- <item>
- <table>79</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>82</row>
- </item>
- <item>
- <table>20</table>
- <row>80</row>
- </item>
- <item>
- <table>40</table>
- <row>58</row>
- </item>
- <item>
- <table>77</table>
- <row>1</row>
- </item>
- <item>
- <table>57</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>59</row>
- </item>
- <item>
- <table>36</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>32</row>
- </item>
- <item>
- <table>20</table>
- <row>19</row>
- </item>
- <item>
- <table>40</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>43</row>
- </item>
- <item>
- <table>20</table>
- <row>24</row>
- </item>
- <item>
- <table>20</table>
- <row>43</row>
- </item>
- <item>
- <table>16</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>95</row>
- </item>
- <item>
- <table>38</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>62</row>
- </item>
- <item>
- <table>20</table>
- <row>12</row>
- </item>
- <item>
- <table>58</table>
- <row>2</row>
- </item>
- <item>
- <table>32</table>
- <row>2</row>
- </item>
- <item>
- <table>104</table>
- <row>2</row>
- </item>
- <item>
- <table>16</table>
- <row>5</row>
- </item>
- <item>
- <table>34</table>
- <row>5</row>
- </item>
- <item>
- <table>90</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>9</row>
- </item>
- <item>
- <table>40</table>
- <row>71</row>
- </item>
- <item>
- <table>36</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>42</row>
- </item>
- <item>
- <table>20</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>46</row>
- </item>
- <item>
- <table>40</table>
- <row>55</row>
- </item>
- <item>
- <table>20</table>
- <row>67</row>
- </item>
- <item>
- <table>34</table>
- <row>3</row>
- </item>
- <item>
- <table>32</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>11</row>
- </item>
- <item>
- <table>40</table>
- <row>70</row>
- </item>
- <item>
- <table>40</table>
- <row>21</row>
- </item>
- <item>
- <table>14</table>
- <row>3</row>
- </item>
- <item>
- <table>92</table>
- <row>1</row>
- </item>
- <item>
- <table>93</table>
- <row>7</row>
- </item>
- <item>
- <table>20</table>
- <row>90</row>
- </item>
- <item>
- <table>32</table>
- <row>5</row>
- </item>
- <item>
- <table>105</table>
- <row>1</row>
- </item>
- <item>
- <table>106</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>71</row>
- </item>
- <item>
- <table>20</table>
- <row>41</row>
- </item>
- <item>
- <table>105</table>
- <row>3</row>
- </item>
- <item>
- <table>92</table>
- <row>5</row>
- </item>
- <item>
- <table>103</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>56</row>
- </item>
- <item>
- <table>56</table>
- <row>2</row>
- </item>
- <item>
- <table>100</table>
- <row>1</row>
- </item>
- <item>
- <table>104</table>
- <row>1</row>
- </item>
- <item>
- <table>35</table>
- <row>12</row>
- </item>
- <item>
- <table>20</table>
- <row>13</row>
- </item>
- <item>
- <table>10</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>23</row>
- </item>
- <item>
- <table>76</table>
- <row>2</row>
- </item>
- <item>
- <table>42</table>
- <row>1</row>
- </item>
- <item>
- <table>41</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>14</table>
- <row>12</row>
- </item>
- <item>
- <table>20</table>
- <row>11</row>
- </item>
- <item>
- <table>20</table>
- <row>5</row>
- </item>
- <item>
- <table>93</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>17</row>
- </item>
- <item>
- <table>20</table>
- <row>44</row>
- </item>
- <item>
- <table>40</table>
- <row>22</row>
- </item>
- <item>
- <table>34</table>
- <row>2</row>
- </item>
- <item>
- <table>38</table>
- <row>4</row>
- </item>
- <item>
- <table>1</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>9</row>
- </item>
- <item>
- <table>77</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>75</row>
- </item>
- <item>
- <table>102</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>10</row>
- </item>
- <item>
- <table>37</table>
- <row>1</row>
- </item>
- <item>
- <table>70</table>
- <row>1</row>
- </item>
- <item>
- <table>18</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>62</row>
- </item>
- <item>
- <table>40</table>
- <row>44</row>
- </item>
- <item>
- <table>20</table>
- <row>48</row>
- </item>
- <item>
- <table>40</table>
- <row>12</row>
- </item>
- <item>
- <table>20</table>
- <row>28</row>
- </item>
- <item>
- <table>1</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>38</row>
- </item>
- <item>
- <table>20</table>
- <row>34</row>
- </item>
- <item>
- <table>40</table>
- <row>68</row>
- </item>
- <item>
- <table>40</table>
- <row>51</row>
- </item>
- <item>
- <table>56</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>55</row>
- </item>
- <item>
- <table>40</table>
- <row>27</row>
- </item>
- <item>
- <table>62</table>
- <row>1</row>
- </item>
- <item>
- <table>105</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>54</row>
- </item>
- <item>
- <table>20</table>
- <row>2</row>
- </item>
- <item>
- <table>40</table>
- <row>17</row>
- </item>
- <item>
- <table>20</table>
- <row>47</row>
- </item>
- <item>
- <table>40</table>
- <row>36</row>
- </item>
- <item>
- <table>32</table>
- <row>7</row>
- </item>
- <item>
- <table>38</table>
- <row>2</row>
- </item>
- <item>
- <table>1</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>18</row>
- </item>
- <item>
- <table>20</table>
- <row>42</row>
- </item>
- <item>
- <table>102</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>106</row>
- </item>
- <item>
- <table>54</table>
- <row>4</row>
- </item>
- <item>
- <table>35</table>
- <row>3</row>
- </item>
- <item>
- <table>59</table>
- <row>2</row>
- </item>
- <item>
- <table>74</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>15</row>
- </item>
- <item>
- <table>79</table>
- <row>14</row>
- </item>
- <item>
- <table>20</table>
- <row>110</row>
- </item>
- <item>
- <table>20</table>
- <row>112</row>
- </item>
- <item>
- <table>53</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>25</row>
- </item>
- <item>
- <table>20</table>
- <row>113</row>
- </item>
- <item>
- <table>40</table>
- <row>1</row>
- </item>
- <item>
- <table>79</table>
- <row>5</row>
- </item>
- <item>
- <table>77</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>12</row>
- </item>
- <item>
- <table>14</table>
- <row>7</row>
- </item>
- <item>
- <table>40</table>
- <row>14</row>
- </item>
- <item>
- <table>52</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>89</row>
- </item>
- <item>
- <table>20</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>2</row>
- </item>
- <item>
- <table>102</table>
- <row>3</row>
- </item>
- <item>
- <table>1</table>
- <row>6</row>
- </item>
- <item>
- <table>76</table>
- <row>1</row>
- </item>
- <item>
- <table>79</table>
- <row>16</row>
- </item>
- <item>
- <table>40</table>
- <row>47</row>
- </item>
- <item>
- <table>40</table>
- <row>38</row>
- </item>
- <item>
- <table>20</table>
- <row>6</row>
- </item>
- <item>
- <table>37</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>40</row>
- </item>
- <item>
- <table>40</table>
- <row>65</row>
- </item>
- <item>
- <table>78</table>
- <row>3</row>
- </item>
- <item>
- <table>36</table>
- <row>2</row>
- </item>
- <item>
- <table>30</table>
- <row>1</row>
- </item>
- <item>
- <table>75</table>
- <row>1</row>
- </item>
- <item>
- <table>32</table>
- <row>4</row>
- </item>
- <item>
- <table>22</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>108</row>
- </item>
- <item>
- <table>59</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>109</row>
- </item>
- <item>
- <table>18</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>26</row>
- </item>
- <item>
- <table>20</table>
- <row>97</row>
- </item>
- <item>
- <table>1</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>24</row>
- </item>
- <item>
- <table>57</table>
- <row>1</row>
- </item>
- <item>
- <table>35</table>
- <row>9</row>
- </item>
- <item>
- <table>40</table>
- <row>20</row>
- </item>
- <item>
- <table>40</table>
- <row>50</row>
- </item>
- <item>
- <table>79</table>
- <row>13</row>
- </item>
- <item>
- <table>59</table>
- <row>8</row>
- </item>
- <item>
- <table>40</table>
- <row>35</row>
- </item>
- <item>
- <table>40</table>
- <row>67</row>
- </item>
- <item>
- <table>20</table>
- <row>27</row>
- </item>
- <item>
- <table>40</table>
- <row>7</row>
- </item>
- <item>
- <table>14</table>
- <row>10</row>
- </item>
- <item>
- <table>20</table>
- <row>52</row>
- </item>
- <item>
- <table>40</table>
- <row>49</row>
- </item>
- <item>
- <table>40</table>
- <row>69</row>
- </item>
- <item>
- <table>35</table>
- <row>4</row>
- </item>
- <item>
- <table>39</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>100</row>
- </item>
- <item>
- <table>18</table>
- <row>5</row>
- </item>
- <item>
- <table>50</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>13</row>
- </item>
- <item>
- <table>40</table>
- <row>41</row>
- </item>
- <item>
- <table>20</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>59</row>
- </item>
- <item>
- <table>20</table>
- <row>73</row>
- </item>
- <item>
- <table>20</table>
- <row>105</row>
- </item>
- <item>
- <table>20</table>
- <row>20</row>
- </item>
- <item>
- <table>79</table>
- <row>3</row>
- </item>
- <item>
- <table>81</table>
- <row>1</row>
- </item>
- <item>
- <table>37</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>7</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>23</row>
- </item>
- <item>
- <table>20</table>
- <row>58</row>
- </item>
- <item>
- <table>40</table>
- <row>32</row>
- </item>
- <item>
- <table>40</table>
- <row>4</row>
- </item>
- <item>
- <table>18</table>
- <row>6</row>
- </item>
- <item>
- <table>17</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>61</row>
- </item>
- <item>
- <table>17</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>50</row>
- </item>
- <item>
- <table>54</table>
- <row>1</row>
- </item>
- <item>
- <table>1</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>114</row>
- </item>
- <item>
- <table>17</table>
- <row>3</row>
- </item>
- <item>
- <table>82</table>
- <row>1</row>
- </item>
- <item>
- <table>93</table>
- <row>4</row>
- </item>
- <item>
- <table>16</table>
- <row>3</row>
- </item>
- <item>
- <table>54</table>
- <row>2</row>
- </item>
- <item>
- <table>40</table>
- <row>34</row>
- </item>
- <item>
- <table>72</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>51</row>
- </item>
- <item>
- <table>103</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>33</row>
- </item>
- <item>
- <table>20</table>
- <row>60</row>
- </item>
- <item>
- <table>14</table>
- <row>5</row>
- </item>
- <item>
- <table>102</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>19</row>
- </item>
- <item>
- <table>40</table>
- <row>16</row>
- </item>
- <item>
- <table>79</table>
- <row>12</row>
- </item>
- <item>
- <table>40</table>
- <row>39</row>
- </item>
- <item>
- <table>40</table>
- <row>54</row>
- </item>
- <item>
- <table>15</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>84</row>
- </item>
- <item>
- <table>93</table>
- <row>2</row>
- </item>
- <item>
- <table>40</table>
- <row>63</row>
- </item>
- <item>
- <table>40</table>
- <row>66</row>
- </item>
- <item>
- <table>60</table>
- <row>1</row>
- </item>
- <item>
- <table>14</table>
- <row>8</row>
- </item>
- <item>
- <table>57</table>
- <row>2</row>
- </item>
- <item>
- <table>79</table>
- <row>15</row>
- </item>
- <item>
- <table>37</table>
- <row>6</row>
- </item>
- <item>
- <table>38</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>9</row>
- </item>
- <item>
- <table>33</table>
- <row>1</row>
- </item>
- <item>
- <table>73</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>39</row>
- </item>
- <item>
- <table>40</table>
- <row>52</row>
- </item>
- <item>
- <table>35</table>
- <row>6</row>
- </item>
- <item>
- <table>40</table>
- <row>31</row>
- </item>
- <item>
- <table>20</table>
- <row>14</row>
- </item>
- <item>
- <table>20</table>
- <row>18</row>
- </item>
- <item>
- <table>20</table>
- <row>87</row>
- </item>
- <item>
- <table>36</table>
- <row>6</row>
- </item>
- <item>
- <table>16</table>
- <row>1</row>
- </item>
- <item>
- <table>56</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>98</row>
- </item>
- <item>
- <table>79</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>53</row>
- </item>
- <item>
- <table>40</table>
- <row>40</row>
- </item>
- <item>
- <table>16</table>
- <row>6</row>
- </item>
- <item>
- <table>92</table>
- <row>2</row>
- </item>
- <item>
- <table>79</table>
- <row>7</row>
- </item>
- <item>
- <table>19</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>35</row>
- </item>
- <item>
- <table>105</table>
- <row>5</row>
- </item>
- <item>
- <table>40</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>15</row>
- </item>
- <item>
- <table>93</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>49</row>
- </item>
- <item>
- <table>35</table>
- <row>11</row>
- </item>
- <item>
- <table>59</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>76</row>
- </item>
- <item>
- <table>32</table>
- <row>6</row>
- </item>
- <item>
- <table>20</table>
- <row>88</row>
- </item>
- <item>
- <table>20</table>
- <row>101</row>
- </item>
- <item>
- <table>72</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>65</row>
- </item>
- <item>
- <table>18</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>91</row>
- </item>
- <item>
- <table>35</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>74</row>
- </item>
- <item>
- <table>75</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>22</row>
- </item>
- <item>
- <table>20</table>
- <row>96</row>
- </item>
- <item>
- <table>76</table>
- <row>4</row>
- </item>
- <item>
- <table>110</table>
- <row>1</row>
- </item>
- <item>
- <table>59</table>
- <row>11</row>
- </item>
- <item>
- <table>20</table>
- <row>16</row>
- </item>
- <item>
- <table>20</table>
- <row>78</row>
- </item>
- <item>
- <table>103</table>
- <row>1</row>
- </item>
- <item>
- <table>38</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>61</row>
- </item>
- <item>
- <table>35</table>
- <row>2</row>
- </item>
- <item>
- <table>34</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>64</row>
- </item>
- <item>
- <table>94</table>
- <row>1</row>
- </item>
- <item>
- <table>79</table>
- <row>11</row>
- </item>
- <item>
- <table>17</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>46</row>
- </item>
- <item>
- <table>58</table>
- <row>1</row>
- </item>
- <item>
- <table>12</table>
- <row>2</row>
- </item>
- <item>
- <table>79</table>
- <row>9</row>
- </item>
- <item>
- <table>20</table>
- <row>36</row>
- </item>
- <item>
- <table>20</table>
- <row>45</row>
- </item>
- <item>
- <table>40</table>
- <row>45</row>
- </item>
- <item>
- <table>20</table>
- <row>66</row>
- </item>
- <item>
- <table>34</table>
- <row>4</row>
- </item>
- <item>
- <table>40</table>
- <row>25</row>
- </item>
- <item>
- <table>105</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>99</row>
- </item>
- <item>
- <table>40</table>
- <row>57</row>
- </item>
- <item>
- <table>93</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>64</row>
- </item>
- <item>
- <table>15</table>
- <row>1</row>
- </item>
- <item>
- <table>92</table>
- <row>4</row>
- </item>
- <item>
- <table>77</table>
- <row>4</row>
- </item>
- <item>
- <table>35</table>
- <row>10</row>
- </item>
- <item>
- <table>20</table>
- <row>57</row>
- </item>
- <item>
- <table>40</table>
- <row>60</row>
- </item>
- <item>
- <table>54</table>
- <row>3</row>
- </item>
- <item>
- <table>76</table>
- <row>3</row>
- </item>
- <item>
- <table>57</table>
- <row>4</row>
- </item>
- <item>
- <table>59</table>
- <row>10</row>
- </item>
- <item>
- <table>20</table>
- <row>70</row>
- </item>
- <item>
- <table>40</table>
- <row>72</row>
- </item>
- <item>
- <table>108</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>30</row>
- </item>
- <item>
- <table>40</table>
- <row>30</row>
- </item>
- <item>
- <table>36</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>21</row>
- </item>
- <item>
- <table>20</table>
- <row>111</row>
- </item>
- <item>
- <table>40</table>
- <row>2</row>
- </item>
- <item>
- <table>107</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>10</row>
- </item>
- <item>
- <table>13</table>
- <row>1</row>
- </item>
- <item>
- <table>59</table>
- <row>5</row>
- </item>
- <item>
- <table>105</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>53</row>
- </item>
- <item>
- <table>103</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>81</row>
- </item>
- <item>
- <table>20</table>
- <row>68</row>
- </item>
- <item>
- <table>55</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>86</row>
- </item>
- <item>
- <table>38</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>2</row>
- </item>
- <item>
- <table>20</table>
- <row>26</row>
- </item>
- <item>
- <table>40</table>
- <row>5</row>
- </item>
- <item>
- <table>20</table>
- <row>102</row>
- </item>
- <item>
- <table>19</table>
- <row>3</row>
- </item>
- <item>
- <table>105</table>
- <row>7</row>
- </item>
- <item>
- <table>20</table>
- <row>31</row>
- </item>
- <item>
- <table>20</table>
- <row>104</row>
- </item>
- <item>
- <table>21</table>
- <row>1</row>
- </item>
- <item>
- <table>17</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>4</row>
- </item>
- <item>
- <table>20</table>
- <row>107</row>
- </item>
- <item>
- <table>20</table>
- <row>94</row>
- </item>
- <item>
- <table>20</table>
- <row>8</row>
- </item>
- <item>
- <table>37</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>37</row>
- </item>
- <item>
- <table>40</table>
- <row>29</row>
- </item>
- <item>
- <table>74</table>
- <row>3</row>
- </item>
- <item>
- <table>93</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>56</row>
- </item>
- <item>
- <table>19</table>
- <row>2</row>
- </item>
- <item>
- <table>35</table>
- <row>7</row>
- </item>
- <item>
- <table>20</table>
- <row>103</row>
- </item>
- <item>
- <table>20</table>
- <row>77</row>
- </item>
- <item>
- <table>14</table>
- <row>1</row>
- </item>
- <item>
- <table>40</table>
- <row>11</row>
- </item>
- <item>
- <table>59</table>
- <row>9</row>
- </item>
- <item>
- <table>36</table>
- <row>3</row>
- </item>
- <item>
- <table>40</table>
- <row>8</row>
- </item>
- <item>
- <table>20</table>
- <row>93</row>
- </item>
- <item>
- <table>79</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>69</row>
- </item>
- <item>
- <table>40</table>
- <row>48</row>
- </item>
- <item>
- <table>74</table>
- <row>2</row>
- </item>
- <item>
- <table>59</table>
- <row>3</row>
- </item>
- <item>
- <table>14</table>
- <row>6</row>
- </item>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>20</table>
- <row>37</row>
- </item>
- <item>
- <table>40</table>
- <row>28</row>
- </item>
- <item>
- <table>35</table>
- <row>8</row>
- </item>
- <item>
- <table>74</table>
- <row>4</row>
- </item>
- <item>
- <table>104</table>
- <row>3</row>
- </item>
- <item>
- <table>18</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>83</row>
- </item>
- <item>
- <table>17</table>
- <row>5</row>
- </item>
- <item>
- <table>92</table>
- <row>3</row>
- </item>
- <item>
- <table>35</table>
- <row>1</row>
- </item>
- <item>
- <table>79</table>
- <row>8</row>
- </item>
- <item>
- <table>20</table>
- <row>72</row>
- </item>
- <item>
- <table>20</table>
- <row>79</row>
- </item>
- <item>
- <table>79</table>
- <row>10</row>
- </item>
- </profile>
- <profile>
- <name>CORE</name>
- <item>
- <table>12</table>
- <row>3</row>
- </item>
- <item>
- <table>2a</table>
- <row>53</row>
- </item>
- <item>
- <table>40</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>6</row>
- </item>
- <item>
- <table>2</table>
- <row>54</row>
- </item>
- <item>
- <table>20a</table>
- <row>1</row>
- </item>
- <item>
- <table>11</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>1</row>
- </item>
- <item>
- <table>2a</table>
- <row>54</row>
- </item>
- <item>
- <table>2a</table>
- <row>51</row>
- </item>
- <item>
- <table>31</table>
- <row>2</row>
- </item>
- <item>
- <table>41</table>
- <row>2</row>
- </item>
- <item>
- <table>11</table>
- <row>5</row>
- </item>
- <item>
- <table>2</table>
- <row>1</row>
- </item>
- <item>
- <table>20</table>
- <row>4</row>
- </item>
- <item>
- <table>2a</table>
- <row>50</row>
- </item>
- <item>
- <table>12</table>
- <row>1</row>
- </item>
- <item>
- <table>2a</table>
- <row>52</row>
- </item>
- <item>
- <table>2b</table>
- <row>54</row>
- </item>
- <item>
- <table>11</table>
- <row>3</row>
- </item>
- </profile>
- <profile>
- <name>UHCI</name>
- <item>
- <table>0</table>
- <row>54</row>
- </item>
- </profile>
- </pics>
-</project>
+<?xml version="1.0" encoding="utf-8"?>
+<project>
+ <qdid>300252</qdid>
+ <name>Zephyr_Bluetooth_Host</name>
+ <pics>
+ <profile>
+ <name>GAP</name>
+ <item>
+ <table>27c</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>11b</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>37c</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>14a</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>37c</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>17b</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>14a</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>37c</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11b</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>11b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>27c</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>14a</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>14a</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>27b</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>37b</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>14a</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>30a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>27c</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>11a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>20A</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>8a</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ </profile>
+ <profile>
+ <name>L2CAP</name>
+ <item>
+ <table>2</table>
+ <row>48b</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>49</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>45a</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>46</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>47</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>48</row>
+ </item>
+ </profile>
+ <profile>
+ <name>IOP</name>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>GATT</name>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3a</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ </profile>
+ <profile>
+ <name>SM</name>
+ <item>
+ <table>7a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7b</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>ATT</name>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3a</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ </profile>
+ <profile>
+ <name>DIS</name>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ </profile>
+ <profile>
+ <name>IAS</name>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>HRS</name>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>BAS</name>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ </profile>
+ <profile>
+ <name>OTS</name>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>OTP</name>
+ <item>
+ <table>9</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>30</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MESH</name>
+ <item>
+ <table>11</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>1a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>AICS</name>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>VOCS</name>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>VCS</name>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>VCP</name>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MICS</name>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MICP</name>
+ <item>
+ <table>15</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MCS</name>
+ <item>
+ <table>23</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>0b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>18</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MCP</name>
+ <item>
+ <table>17</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>15</row>
+ </item>
+ </profile>
+ <profile>
+ <name>TBS</name>
+ <item>
+ <table>23</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>0b</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>0b</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>5</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CCP</name>
+ <item>
+ <table>12</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>13</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CSIS</name>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>0a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CSIP</name>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>PACS</name>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>14</row>
+ </item>
+ </profile>
+ <profile>
+ <name>ASCS</name>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>BASS</name>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>BAP</name>
+ <item>
+ <table>66</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>53</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>60</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>84</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>82</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>43</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>65</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>87</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>60</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>58</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>87</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>62</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>82</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>65</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>48</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>50</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>86</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>60</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>86</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>67</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>53</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>78</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>86</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>48</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>87</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>66</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>58</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>71</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>65</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>65</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>25</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>64</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>85</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>33a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>83</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>48</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>65</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>85</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>60</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>87</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>61</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>80</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>86</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>63</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>88</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>69</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>49</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>45</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>67</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>68</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9a</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>58</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>67</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>82</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>44</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>42</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>89</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>7</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CAS</name>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CAP</name>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6a</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>23</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>29</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>28</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>6a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>27</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>HAS</name>
+ <item>
+ <table>5</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1a</row>
+ </item>
+ <item>
+ <table>4</table>
+ <row>6</row>
+ </item>
+ </profile>
+ <profile>
+ <name>HAP</name>
+ <item>
+ <table>12</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>50</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>51</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>43</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>50</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>26</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>43</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>43</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>24</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>43</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>46</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>4</row>
+ </item>
+ </profile>
+ <profile>
+ <name>TMAP</name>
+ <item>
+ <table>95</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>114</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>153</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>78</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>118</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>113</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>99</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>94</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>98</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>150</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>153</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>153</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>112</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>97</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>78</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>100</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>110</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>98</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>118</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>114</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>94</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>119</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>97</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>53</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>117</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>78</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>131</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>156</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>120</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>152</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>154</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>114</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>118</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>94</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>117</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>116</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>121</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>98</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>115</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>100</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>121</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>99</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>153</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>119</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>112</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>50</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>96</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>151</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>94</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>95</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>6</row>
+ </item>
+ </profile>
+ <profile>
+ <name>PBP</name>
+ <item>
+ <table>13</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>5</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>7</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>8</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>9</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>6</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>MBTM</name>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>2</row>
+ </item>
+ </profile>
+ <profile>
+ <name>DFUM</name>
+ <item>
+ <table>3</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>0</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>3</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ </profile>
+ <profile>
+ <name>GMAP</name>
+ <item>
+ <table>79</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>92</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>63</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>85</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>102</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>107</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>82</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>80</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>58</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>59</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>43</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>95</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>62</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>58</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>104</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>90</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>71</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>46</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>55</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>67</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>70</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>90</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>106</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>71</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>103</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>56</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>100</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>104</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>10</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>42</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>44</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>75</row>
+ </item>
+ <item>
+ <table>102</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>70</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>62</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>44</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>48</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>68</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>51</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>55</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>62</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>54</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>17</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>47</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>42</row>
+ </item>
+ <item>
+ <table>102</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>106</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>110</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>112</row>
+ </item>
+ <item>
+ <table>53</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>113</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>52</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>89</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>102</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>47</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>38</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>65</row>
+ </item>
+ <item>
+ <table>78</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>30</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>22</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>108</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>109</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>97</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>24</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>50</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>67</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>27</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>52</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>49</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>69</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>39</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>100</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>50</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>13</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>41</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>59</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>73</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>105</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>20</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>81</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>23</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>58</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>32</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>61</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>50</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>1</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>114</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>82</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>34</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>51</row>
+ </item>
+ <item>
+ <table>103</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>33</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>60</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>102</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>19</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>12</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>54</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>84</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>63</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>66</row>
+ </item>
+ <item>
+ <table>60</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>33</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>73</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>39</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>52</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>14</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>18</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>87</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>56</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>98</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>53</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>40</row>
+ </item>
+ <item>
+ <table>16</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>35</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>15</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>49</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>76</row>
+ </item>
+ <item>
+ <table>32</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>88</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>101</row>
+ </item>
+ <item>
+ <table>72</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>65</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>91</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>74</row>
+ </item>
+ <item>
+ <table>75</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>22</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>96</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>110</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>16</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>78</row>
+ </item>
+ <item>
+ <table>103</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>61</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>64</row>
+ </item>
+ <item>
+ <table>94</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>46</row>
+ </item>
+ <item>
+ <table>58</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>36</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>45</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>45</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>66</row>
+ </item>
+ <item>
+ <table>34</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>25</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>99</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>57</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>64</row>
+ </item>
+ <item>
+ <table>15</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>77</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>57</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>60</row>
+ </item>
+ <item>
+ <table>54</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>76</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>57</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>70</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>72</row>
+ </item>
+ <item>
+ <table>108</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>30</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>21</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>111</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>107</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>10</row>
+ </item>
+ <item>
+ <table>13</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>53</row>
+ </item>
+ <item>
+ <table>103</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>81</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>68</row>
+ </item>
+ <item>
+ <table>55</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>86</row>
+ </item>
+ <item>
+ <table>38</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>26</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>102</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>105</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>31</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>104</row>
+ </item>
+ <item>
+ <table>21</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>107</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>94</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>37</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>29</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>93</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>56</row>
+ </item>
+ <item>
+ <table>19</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>7</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>103</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>77</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>11</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>9</row>
+ </item>
+ <item>
+ <table>36</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>93</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>69</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>48</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>59</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>14</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>37</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>28</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>74</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>104</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>18</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>83</row>
+ </item>
+ <item>
+ <table>17</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>92</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>35</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>8</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>72</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>79</row>
+ </item>
+ <item>
+ <table>79</table>
+ <row>10</row>
+ </item>
+ </profile>
+ <profile>
+ <name>CORE</name>
+ <item>
+ <table>12</table>
+ <row>3</row>
+ </item>
+ <item>
+ <table>2a</table>
+ <row>53</row>
+ </item>
+ <item>
+ <table>40</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>6</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>54</row>
+ </item>
+ <item>
+ <table>20a</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2a</table>
+ <row>54</row>
+ </item>
+ <item>
+ <table>2a</table>
+ <row>51</row>
+ </item>
+ <item>
+ <table>31</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>41</table>
+ <row>2</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>5</row>
+ </item>
+ <item>
+ <table>2</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>20</table>
+ <row>4</row>
+ </item>
+ <item>
+ <table>2a</table>
+ <row>50</row>
+ </item>
+ <item>
+ <table>12</table>
+ <row>1</row>
+ </item>
+ <item>
+ <table>2a</table>
+ <row>52</row>
+ </item>
+ <item>
+ <table>2b</table>
+ <row>54</row>
+ </item>
+ <item>
+ <table>11</table>
+ <row>3</row>
+ </item>
+ </profile>
+ <profile>
+ <name>UHCI</name>
+ <item>
+ <table>0</table>
+ <row>54</row>
+ </item>
+ </profile>
+ </pics>
+</project>
diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml
index 6ac40bc..4a3bca9 100644
--- a/tests/bluetooth/shell/testcase.yaml
+++ b/tests/bluetooth/shell/testcase.yaml
@@ -27,6 +27,13 @@
- CONFIG_BT_TRANSMIT_POWER_CONTROL=y
- CONFIG_BT_CTLR=n
platform_allow:
+ - native_sim
+ build_only: true
+ bluetooth.shell.path_loss_monitoring:
+ extra_configs:
+ - CONFIG_BT_PATH_LOSS_MONITORING=y
+ - CONFIG_BT_CTLR=n
+ platform_allow:
- native_posix
build_only: true
bluetooth.shell.subrating:
@@ -34,7 +41,7 @@
- CONFIG_BT_SUBRATING=y
- CONFIG_BT_CTLR=n
platform_allow:
- - native_posix
+ - native_sim
build_only: true
bluetooth.shell.cdc_acm:
extra_args:
@@ -362,19 +369,19 @@
bluetooth.audio_shell.no_gmap:
extra_args: CONF_FILE="audio.conf"
build_only: true
- platform_allow: native_posix
+ platform_allow: native_sim
extra_configs:
- CONFIG_BT_GMAP=n
bluetooth.audio_shell.no_cap_commander:
extra_args: CONF_FILE="audio.conf"
build_only: true
- platform_allow: native_posix
+ platform_allow: native_sim
extra_configs:
- CONFIG_BT_CAP_COMMANDER=n
bluetooth.audio_shell.only_cap_commander:
extra_args: CONF_FILE="audio.conf"
build_only: true
- platform_allow: native_posix
+ platform_allow: native_sim
extra_configs:
- CONFIG_BT_BAP_UNICAST_CLIENT=n
- CONFIG_BT_CAP_ACCEPTOR=n
diff --git a/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.conf b/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.conf
new file mode 100644
index 0000000..2913939
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.conf
@@ -0,0 +1,23 @@
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+# Enable the option below to measure stack usage
+#CONFIG_INIT_STACKS=y
+CONFIG_THREAD_NAME=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_RTT_CONSOLE=y
+CONFIG_LOG_BACKEND_RTT=y
+CONFIG_LOG_BACKEND_RTT_MODE_DROP=y
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
+CONFIG_LOG_BACKEND_SHOW_COLOR=n
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 0000000..e6d4f67
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/ {
+ chosen {
+ zephyr,uart-pipe = &uart136;
+ };
+};
+
+&uart136 {
+ compatible = "nordic,nrf-uarte";
+ current-speed = <115200>;
+ status = "okay";
+ hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/src/audio/btp_bap_audio_stream.c b/tests/bluetooth/tester/src/audio/btp_bap_audio_stream.c
index 4cbc088..e294cac 100644
--- a/tests/bluetooth/tester/src/audio/btp_bap_audio_stream.c
+++ b/tests/bluetooth/tester/src/audio/btp_bap_audio_stream.c
@@ -23,7 +23,8 @@
NET_BUF_POOL_FIXED_DEFINE(tx_pool, MAX(CONFIG_BT_ASCS_ASE_SRC_COUNT,
CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT),
- BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU), 8, NULL);
+ BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU),
+ CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
RING_BUF_DECLARE(audio_ring_buf, CONFIG_BT_ISO_TX_MTU);
diff --git a/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c b/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
index 836d748..df3b2f3 100644
--- a/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
+++ b/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
@@ -1208,14 +1208,7 @@
return BTP_STATUS_FAILED;
}
- if (cp->requested_bis_sync == BT_BAP_BIS_SYNC_NO_PREF) {
- broadcaster->requested_bis_sync = sys_le32_to_cpu(cp->requested_bis_sync);
- } else {
- /* For semantic purposes Zephyr API uses BIS Index bitfield
- * where BIT(1) means BIS Index 1
- */
- broadcaster->requested_bis_sync = sys_le32_to_cpu(cp->requested_bis_sync) << 1;
- }
+ broadcaster->requested_bis_sync = sys_le32_to_cpu(cp->requested_bis_sync);
err = bt_bap_broadcast_sink_sync(broadcaster->sink, broadcaster->requested_bis_sync,
broadcaster->sink_streams,
diff --git a/tests/bluetooth/tester/src/audio/btp_vcp.c b/tests/bluetooth/tester/src/audio/btp_vcp.c
index 1f3bd1b..d456106 100644
--- a/tests/bluetooth/tester/src/audio/btp_vcp.c
+++ b/tests/bluetooth/tester/src/audio/btp_vcp.c
@@ -144,12 +144,12 @@
return BTP_STATUS_SUCCESS;
}
-static void vcs_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcs_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
LOG_DBG("VCP state cb err (%d)", err);
}
-static void vcs_flags_cb(int err, uint8_t flags)
+static void vcs_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
LOG_DBG("VCP flags cb err (%d)", err);
}
diff --git a/tests/bluetooth/tester/src/btp_l2cap.c b/tests/bluetooth/tester/src/btp_l2cap.c
index ff78fa9..69c438f 100644
--- a/tests/bluetooth/tester/src/btp_l2cap.c
+++ b/tests/bluetooth/tester/src/btp_l2cap.c
@@ -25,7 +25,8 @@
#define CHANNELS 2
#define SERVERS 1
-NET_BUF_POOL_FIXED_DEFINE(data_pool, CHANNELS, DATA_BUF_SIZE, 8, NULL);
+NET_BUF_POOL_FIXED_DEFINE(data_pool, CHANNELS, DATA_BUF_SIZE, CONFIG_BT_CONN_TX_USER_DATA_SIZE,
+ NULL);
static bool authorize_flag;
static uint8_t req_keysize;
diff --git a/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c b/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c
index f539b20..92ff136 100644
--- a/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c
+++ b/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c
@@ -15,7 +15,8 @@
#define DT_CPU_COMPAT espressif_xtensa_lx6
#elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3)
#define DT_CPU_COMPAT espressif_xtensa_lx7
-#elif defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \
+ defined(CONFIG_SOC_SERIES_ESP32C6)
#define DT_CPU_COMPAT espressif_riscv
#endif
@@ -74,8 +75,13 @@
uint32_t rtc_pll_src_freq_mhz[] = {
ESP32_CLK_CPU_PLL_80M,
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+ ESP32_CLK_CPU_PLL_120M,
+#else
ESP32_CLK_CPU_PLL_160M,
-#if !defined(CONFIG_SOC_SERIES_ESP32C3) && !defined(CONFIG_SOC_SERIES_ESP32C6)
+#endif
+#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) && \
+ !defined(CONFIG_SOC_SERIES_ESP32C6)
ESP32_CLK_CPU_PLL_240M,
#endif
};
diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
index 317e14b..87de852 100644
--- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
@@ -653,28 +653,6 @@
return 0;
}
-static uint16_t interval_to_sync_timeout(uint16_t pa_interval)
-{
- uint16_t pa_timeout;
-
- if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) {
- /* Use maximum value to maximize chance of success */
- pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT;
- } else {
- uint32_t interval_ms;
- uint32_t timeout;
-
- /* Add retries and convert to unit in 10's of ms */
- interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval);
- timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
-
- /* Enforce restraints */
- pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
- }
-
- return pa_timeout;
-}
-
static int pa_sync_create(void)
{
struct bt_le_per_adv_sync_param create_params = {0};
diff --git a/tests/bsim/bluetooth/audio/src/bap_scan_delegator_test.c b/tests/bsim/bluetooth/audio/src/bap_scan_delegator_test.c
index 0e68993..53ef463 100644
--- a/tests/bsim/bluetooth/audio/src/bap_scan_delegator_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_scan_delegator_test.c
@@ -108,28 +108,6 @@
return NULL;
}
-static uint16_t interval_to_sync_timeout(uint16_t pa_interval)
-{
- uint16_t pa_timeout;
-
- if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) {
- /* Use maximum value to maximize chance of success */
- pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT;
- } else {
- uint32_t interval_ms;
- uint32_t timeout;
-
- /* Add retries and convert to unit in 10's of ms */
- interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval);
- timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
-
- /* Enforce restraints */
- pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
- }
-
- return pa_timeout;
-}
-
static void pa_timer_handler(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
@@ -654,12 +632,17 @@
static int sync_broadcast(struct sync_state *state)
{
int err;
+ uint32_t bis_sync[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS];
UNSET_FLAG(flag_recv_state_updated);
+ for (size_t i = 0U; i < CONFIG_BT_BAP_BASS_MAX_SUBGROUPS; i++) {
+ bis_sync[i] = BT_ISO_BIS_INDEX_BIT(i + 1);
+ }
+
/* We don't actually need to sync to the BIG/BISes */
- err = bt_bap_scan_delegator_set_bis_sync_state(state->src_id,
- (uint32_t[]){BT_ISO_BIS_INDEX_BIT(1)});
+ err = bt_bap_scan_delegator_set_bis_sync_state(state->src_id, bis_sync);
+
if (err) {
return err;
}
diff --git a/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c b/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c
index d7b4b7a..a92fd61 100644
--- a/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c
@@ -52,7 +52,7 @@
static struct bt_bap_unicast_group_stream_pair_param pair_params[ARRAY_SIZE(test_streams)];
static struct bt_bap_unicast_group_stream_param stream_params[ARRAY_SIZE(test_streams)];
-/* Mandatory support preset by both client and server */
+/*Mandatory support preset by both client and server */
static struct bt_bap_lc3_preset preset_16_2_1 = BT_BAP_LC3_UNICAST_PRESET_16_2_1(
BT_AUDIO_LOCATION_FRONT_LEFT, BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED);
@@ -627,7 +627,8 @@
WAIT_FOR_FLAG(flag_source_discovered);
}
-static int codec_configure_stream(struct bt_bap_stream *stream, struct bt_bap_ep *ep)
+static int codec_configure_stream(struct bt_bap_stream *stream, struct bt_bap_ep *ep,
+ struct bt_audio_codec_cfg *codec_cfg)
{
int err;
@@ -636,7 +637,7 @@
do {
- err = bt_bap_stream_config(default_conn, stream, ep, &preset_16_2_1.codec_cfg);
+ err = bt_bap_stream_config(default_conn, stream, ep, codec_cfg);
if (err == -EBUSY) {
k_sleep(BAP_STREAM_RETRY_WAIT);
} else if (err != 0) {
@@ -656,7 +657,8 @@
for (size_t i = 0U; i < ARRAY_SIZE(pair_params); i++) {
if (pair_params[i].rx_param != NULL && g_sources[i] != NULL) {
struct bt_bap_stream *stream = pair_params[i].rx_param->stream;
- const int err = codec_configure_stream(stream, g_sources[i]);
+ const int err = codec_configure_stream(stream, g_sources[i],
+ &preset_16_2_1.codec_cfg);
if (err != 0) {
FAIL("Unable to configure source stream[%zu]: %d", i, err);
@@ -666,7 +668,8 @@
if (pair_params[i].tx_param != NULL && g_sinks[i] != NULL) {
struct bt_bap_stream *stream = pair_params[i].tx_param->stream;
- const int err = codec_configure_stream(stream, g_sinks[i]);
+ const int err = codec_configure_stream(stream, g_sinks[i],
+ &preset_16_2_1.codec_cfg);
if (err != 0) {
FAIL("Unable to configure sink stream[%zu]: %d", i, err);
@@ -1191,6 +1194,45 @@
PASS("Unicast client ACL disconnect passed\n");
}
+static void test_main_async_group(void)
+{
+ struct bt_bap_stream rx_stream = {0};
+ struct bt_bap_stream tx_stream = {0};
+ struct bt_audio_codec_qos rx_qos = BT_AUDIO_CODEC_QOS_UNFRAMED(7500U, 30U, 2U, 75U, 40000U);
+ struct bt_audio_codec_qos tx_qos =
+ BT_AUDIO_CODEC_QOS_UNFRAMED(10000U, 40U, 2U, 100U, 40000U);
+ struct bt_bap_unicast_group_stream_param rx_param = {
+ .qos = &rx_qos,
+ .stream = &rx_stream,
+ };
+ struct bt_bap_unicast_group_stream_param tx_param = {
+ .qos = &tx_qos,
+ .stream = &tx_stream,
+ };
+ struct bt_bap_unicast_group_stream_pair_param pair_param = {
+ .rx_param = &rx_param,
+ .tx_param = &tx_param,
+ };
+ struct bt_bap_unicast_group_param param = {
+ .params = &pair_param,
+ .params_count = 1U,
+ .packing = BT_ISO_PACKING_SEQUENTIAL,
+ };
+ struct bt_bap_unicast_group *unicast_group;
+ int err;
+
+ init();
+
+ err = bt_bap_unicast_group_create(¶m, &unicast_group);
+ if (err != 0) {
+ FAIL("Unable to create unicast group: %d", err);
+
+ return;
+ }
+
+ PASS("Unicast client async group parameters passed\n");
+}
+
static const struct bst_test_instance test_unicast_client[] = {
{
.test_id = "unicast_client",
@@ -1204,6 +1246,15 @@
.test_tick_f = test_tick,
.test_main_f = test_main_acl_disconnect,
},
+ {
+ .test_id = "unicast_client_async_group",
+ .test_pre_init_f = test_init,
+ .test_tick_f = test_tick,
+ .test_main_f = test_main_async_group,
+ .test_descr = "Tests that a unicast group (CIG) can be created with different "
+ "values in each direction, such as 10000us SDU interval in C to P "
+ "and 7500us for P to C",
+ },
BSTEST_END_MARKER,
};
diff --git a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
index 4e7485b..6ef9ec7 100644
--- a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
@@ -55,6 +55,7 @@
CREATE_FLAG(flag_pa_request);
CREATE_FLAG(flag_bis_sync_requested);
CREATE_FLAG(flag_base_metadata_updated);
+CREATE_FLAG(flag_unicast_stream_configured);
static struct bt_bap_broadcast_sink *g_broadcast_sink;
static struct bt_le_scan_recv_info broadcaster_info;
@@ -62,14 +63,6 @@
static struct bt_le_per_adv_sync *pa_sync;
static uint32_t broadcaster_broadcast_id;
static struct audio_test_stream broadcast_sink_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
-static struct bt_le_ext_adv *ext_adv;
-static uint32_t requested_bis_sync;
-static const struct bt_bap_scan_delegator_recv_state *req_recv_state;
-
-static const struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP_LC3(
- BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY,
- BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2,
- (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA));
static const struct bt_audio_codec_qos_pref unicast_qos_pref =
BT_AUDIO_CODEC_QOS_PREF(true, BT_GAP_LE_PHY_2M, 0u, 60u, 20000u, 40000u, 20000u, 40000u);
@@ -79,11 +72,6 @@
static K_SEM_DEFINE(sem_broadcast_started, 0U, ARRAY_SIZE(broadcast_sink_streams));
static K_SEM_DEFINE(sem_broadcast_stopped, 0U, ARRAY_SIZE(broadcast_sink_streams));
-/* Create a mask for the maximum BIS we can sync to using the number of
- * broadcast_sink_streams we have. We add an additional 1 since the bis indexes
- * start from 1 and not 0.
- */
-static const uint32_t bis_index_mask = BIT_MASK(ARRAY_SIZE(broadcast_sink_streams) + 1U);
static uint32_t bis_index_bitfield;
#define UNICAST_CHANNEL_COUNT_1 BIT(0)
@@ -91,8 +79,6 @@
static struct bt_cap_stream unicast_streams[CONFIG_BT_ASCS_ASE_SNK_COUNT +
CONFIG_BT_ASCS_ASE_SRC_COUNT];
-CREATE_FLAG(flag_unicast_stream_configured);
-
static bool subgroup_data_func_cb(struct bt_data *data, void *user_data)
{
bool *stream_context_found = (bool *)user_data;
@@ -153,6 +139,11 @@
static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap_base *base,
size_t base_size)
{
+ /* Create a mask for the maximum BIS we can sync to using the number of
+ * broadcast_sink_streams we have. We add an additional 1 since the bis indexes
+ * start from 1 and not 0.
+ */
+ const uint32_t bis_index_mask = BIT_MASK(ARRAY_SIZE(broadcast_sink_streams) + 1U);
uint32_t base_bis_index_bitfield = 0U;
int ret;
@@ -384,10 +375,9 @@
}
printk("Sync request\n");
- req_recv_state = recv_state;
- bt_addr_le_copy(&broadcaster_addr, &req_recv_state->addr);
- broadcaster_info.sid = req_recv_state->adv_sid;
+ bt_addr_le_copy(&broadcaster_addr, &recv_state->addr);
+ broadcaster_info.sid = recv_state->adv_sid;
broadcaster_info.interval = pa_interval;
SET_FLAG(flag_pa_request);
@@ -402,8 +392,6 @@
return -EALREADY;
}
- req_recv_state = recv_state;
-
UNSET_FLAG(flag_pa_request);
return 0;
@@ -414,7 +402,6 @@
const uint32_t bis_sync_req[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS])
{
/* We only care about a single subgroup in this test */
- requested_bis_sync = bis_sync_req[0];
broadcaster_broadcast_id = recv_state->broadcast_id;
if (bis_sync_req[0] != 0) {
SET_FLAG(flag_bis_sync_requested);
@@ -431,8 +418,6 @@
{
printk("Broadcast code received for %p\n", recv_state);
- req_recv_state = recv_state;
-
SET_FLAG(flag_broadcast_code);
}
@@ -645,6 +630,7 @@
void test_start_adv(void)
{
int err;
+ struct bt_le_ext_adv *ext_adv;
/* Create a connectable non-scannable advertising set */
err = bt_le_ext_adv_create(BT_LE_ADV_CONN_ONE_TIME, NULL, &ext_adv);
@@ -700,7 +686,10 @@
.sirk = { 0xcd, 0xcc, 0x72, 0xdd, 0x86, 0x8c, 0xcd, 0xce,
0x22, 0xfd, 0xa1, 0x21, 0x09, 0x7d, 0x7d, 0x45 },
};
-
+ static const struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP_LC3(
+ BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY,
+ BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2,
+ (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA));
int err;
err = bt_enable(NULL);
@@ -891,31 +880,10 @@
PASS("CAP acceptor unicast passed\n");
}
-static uint16_t interval_to_sync_timeout(uint16_t pa_interval)
-{
- uint16_t pa_timeout;
-
- if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) {
- /* Use maximum value to maximize chance of success */
- pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT;
- } else {
- uint32_t interval_ms;
- uint32_t timeout;
-
- /* Add retries and convert to unit in 10's of ms */
- interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval);
- timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
-
- /* Enforce restraints */
- pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
- }
-
- return pa_timeout;
-}
-
-static int pa_sync_create(void)
+static void pa_sync_create(void)
{
struct bt_le_per_adv_sync_param create_params = {0};
+ int err;
bt_addr_le_copy(&create_params.addr, &broadcaster_addr);
create_params.options = BT_LE_PER_ADV_SYNC_OPT_FILTER_DUPLICATE;
@@ -923,17 +891,20 @@
create_params.skip = PA_SYNC_SKIP;
create_params.timeout = interval_to_sync_timeout(broadcaster_info.interval);
- return bt_le_per_adv_sync_create(&create_params, &pa_sync);
+ err = bt_le_per_adv_sync_create(&create_params, &pa_sync);
+ if (err != 0) {
+ FAIL("Could not create Broadcast PA sync: %d\n", err);
+ return;
+ }
+
+ printk("Broadcast source found, waiting for PA sync\n");
+ WAIT_FOR_FLAG(flag_pa_synced);
}
-static void test_cap_acceptor_broadcast(void)
+static void pa_sync_to_broadcaster(void)
{
- static struct bt_bap_stream *bap_streams[ARRAY_SIZE(broadcast_sink_streams)];
- size_t stream_count;
int err;
- init();
-
printk("Scanning for broadcast sources\n");
err = bt_le_scan_start(BT_LE_SCAN_ACTIVE, NULL);
if (err != 0) {
@@ -952,14 +923,13 @@
printk("Scan stopped, attempting to PA sync to the broadcaster with id 0x%06X\n",
broadcaster_broadcast_id);
- err = pa_sync_create();
- if (err != 0) {
- FAIL("Could not create Broadcast PA sync: %d\n", err);
- return;
- }
- printk("Broadcast source found, waiting for PA sync\n");
- WAIT_FOR_FLAG(flag_pa_synced);
+ pa_sync_create();
+}
+
+static void create_and_sync_sink(struct bt_bap_stream *bap_streams[], size_t *stream_count)
+{
+ int err;
printk("Creating the broadcast sink\n");
err = bt_bap_broadcast_sink_create(pa_sync, broadcaster_broadcast_id, &g_broadcast_sink);
@@ -980,10 +950,10 @@
}
printk("Syncing the sink\n");
- stream_count = 0;
+ *stream_count = 0;
for (int i = 1; i < BT_ISO_MAX_GROUP_ISO_COUNT; i++) {
if ((bis_index_bitfield & BIT(i)) != 0) {
- stream_count++;
+ *stream_count += 1;
}
}
@@ -994,15 +964,28 @@
}
/* Wait for all to be started */
- printk("Waiting for %zu streams to be started\n", stream_count);
- for (size_t i = 0U; i < stream_count; i++) {
+ printk("Waiting for %zu streams to be started\n", *stream_count);
+ for (size_t i = 0U; i < *stream_count; i++) {
k_sem_take(&sem_broadcast_started, K_FOREVER);
}
+}
+static void sink_wait_for_data(void)
+{
printk("Waiting for data\n");
WAIT_FOR_FLAG(flag_received);
backchannel_sync_send_all(); /* let other devices know we have received what we wanted */
+}
+static void base_wait_for_metadata_update(void)
+{
+ printk("Waiting for meta update\n");
+ WAIT_FOR_FLAG(flag_base_metadata_updated);
+ backchannel_sync_send_all(); /* let others know we have received a metadata update */
+}
+
+static void wait_for_streams_stop(int stream_count)
+{
/* The order of PA sync lost and BIG Sync lost is irrelevant
* and depend on timeout parameters. We just wait for PA first, but
* either way will work.
@@ -1014,6 +997,22 @@
for (size_t i = 0U; i < stream_count; i++) {
k_sem_take(&sem_broadcast_stopped, K_FOREVER);
}
+}
+
+static void test_cap_acceptor_broadcast(void)
+{
+ static struct bt_bap_stream *bap_streams[ARRAY_SIZE(broadcast_sink_streams)];
+ size_t stream_count;
+
+ init();
+
+ pa_sync_to_broadcaster();
+
+ create_and_sync_sink(bap_streams, &stream_count);
+
+ sink_wait_for_data();
+
+ wait_for_streams_stop(stream_count);
PASS("CAP acceptor broadcast passed\n");
}
@@ -1022,85 +1021,26 @@
{
static struct bt_bap_stream *bap_streams[ARRAY_SIZE(broadcast_sink_streams)];
size_t stream_count;
- int err;
init();
WAIT_FOR_FLAG(flag_pa_request);
- err = pa_sync_create();
- if (err != 0) {
- FAIL("Could not create Broadcast PA sync: %d\n", err);
- return;
- }
+ pa_sync_create();
- printk("Waiting for PA sync\n");
- WAIT_FOR_FLAG(flag_pa_synced);
+ create_and_sync_sink(bap_streams, &stream_count);
- err = bt_bap_broadcast_sink_create(pa_sync, broadcaster_broadcast_id, &g_broadcast_sink);
- if (err != 0) {
- FAIL("Unable to create the sink: %d\n", err);
- return;
- }
+ sink_wait_for_data();
- if (req_recv_state->num_subgroups == 0) {
- FAIL("Number of subgroups is 0");
- return;
- }
-
- printk("Broadcast source PA synced, waiting for BASE\n");
- WAIT_FOR_FLAG(flag_base_received);
- printk("BASE received\n");
-
- WAIT_FOR_FLAG(flag_syncable);
-
- for (size_t i = 0U; i < ARRAY_SIZE(broadcast_sink_streams); i++) {
- bap_streams[i] = bap_stream_from_audio_test_stream(&broadcast_sink_streams[i]);
- }
-
- printk("Syncing the sink\n");
- stream_count = 0;
- for (int i = 1; i < BT_ISO_MAX_GROUP_ISO_COUNT; i++) {
- if ((bis_index_bitfield & BIT(i)) != 0) {
- stream_count++;
- }
- }
-
- err = bt_bap_broadcast_sink_sync(g_broadcast_sink, bis_index_bitfield, bap_streams, NULL);
- if (err != 0) {
- FAIL("Unable to sync the sink: %d\n", err);
- return;
- }
-
- /* Wait for all to be started */
- printk("Waiting for %zu streams to be started\n", stream_count);
- for (size_t i = 0U; i < stream_count; i++) {
- k_sem_take(&sem_broadcast_started, K_FOREVER);
- }
-
- printk("Waiting for data\n");
- WAIT_FOR_FLAG(flag_received);
-
- backchannel_sync_send_all(); /* let others know we have received some data */
-
- printk("Waiting for meta update\n");
- WAIT_FOR_FLAG(flag_base_metadata_updated);
-
- backchannel_sync_send_all(); /* let others know we have received a metadata update */
+ /* Since we are re-using the BAP broadcast source test
+ * we get a metadata udate, and we need to send an extra
+ * backchannel sync
+ */
+ base_wait_for_metadata_update();
backchannel_sync_send_all(); /* let broadcaster know we can stop the source */
- /* The order of PA sync lost and BIG Sync lost is irrelevant
- * and depend on timeout parameters. We just wait for PA first, but
- * either way will work.
- */
- printk("Waiting for PA disconnected\n");
- WAIT_FOR_FLAG(flag_pa_sync_lost);
-
- printk("Waiting for %zu streams to be stopped\n", stream_count);
- for (size_t i = 0U; i < stream_count; i++) {
- k_sem_take(&sem_broadcast_stopped, K_FOREVER);
- }
+ wait_for_streams_stop(stream_count);
PASS("CAP acceptor broadcast reception passed\n");
}
diff --git a/tests/bsim/bluetooth/audio/src/cap_commander_test.c b/tests/bsim/bluetooth/audio/src/cap_commander_test.c
index 0d69b6b..ed86bbc 100644
--- a/tests/bsim/bluetooth/audio/src/cap_commander_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_commander_test.c
@@ -243,28 +243,6 @@
k_sem_give(&sem_disconnected);
}
-static uint16_t interval_to_sync_timeout(uint16_t pa_interval)
-{
- uint16_t pa_timeout;
-
- if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) {
- /* Use maximum value to maximize chance of success */
- pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT;
- } else {
- uint32_t interval_ms;
- uint32_t timeout;
-
- /* Add retries and convert to unit in 10's of ms */
- interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval);
- timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
-
- /* Enforce restraints */
- pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
- }
-
- return pa_timeout;
-}
-
static int pa_sync_create(void)
{
struct bt_le_per_adv_sync_param create_params = {0};
diff --git a/tests/bsim/bluetooth/audio/src/common.c b/tests/bsim/bluetooth/audio/src/common.c
index 3d00f97..30a4ab0 100644
--- a/tests/bsim/bluetooth/audio/src/common.c
+++ b/tests/bsim/bluetooth/audio/src/common.c
@@ -213,6 +213,38 @@
}
/**
+ * @brief Calculate the sync timeout based on the PA interval
+ *
+ * Calculates the sync timeout, based on the PA interval and a pre-defined ratio.
+ * The return value is in N*10ms, conform the parameter for bt_le_per_adv_sync_create
+ *
+ * @param pa_interval PA interval
+ *
+ * @return uint16_t synchronization timeout (N * 10 ms)
+ */
+uint16_t interval_to_sync_timeout(uint16_t pa_interval)
+{
+ uint16_t pa_timeout;
+
+ if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) {
+ /* Use maximum value to maximize chance of success */
+ pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT;
+ } else {
+ uint32_t interval_ms;
+ uint32_t timeout;
+
+ /* Add retries and convert to unit in 10's of ms */
+ interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval);
+ timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
+
+ /* Enforce restraints */
+ pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
+ }
+
+ return pa_timeout;
+}
+
+/**
* @brief Set up the backchannels between each pair of device
*
* Each pair of devices will get a unique channel
diff --git a/tests/bsim/bluetooth/audio/src/common.h b/tests/bsim/bluetooth/audio/src/common.h
index 8c10939..b257529 100644
--- a/tests/bsim/bluetooth/audio/src/common.h
+++ b/tests/bsim/bluetooth/audio/src/common.h
@@ -121,6 +121,7 @@
void test_tick(bs_time_t HW_device_time);
void test_init(void);
uint16_t get_dev_cnt(void);
+uint16_t interval_to_sync_timeout(uint16_t pa_interval);
void backchannel_sync_send(uint dev);
void backchannel_sync_send_all(void);
void backchannel_sync_wait(uint dev);
diff --git a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
index 578afa0..b12e9ff 100644
--- a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
+++ b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
@@ -114,21 +114,6 @@
printk("Receiving ISO packets\n");
}
-static uint16_t interval_to_sync_timeout(uint16_t interval)
-{
- uint32_t interval_ms;
- uint32_t timeout;
-
- /* Add retries and convert to unit in 10's of ms */
- interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(interval);
- timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10;
-
- /* Enforce restraints */
- timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT);
-
- return (uint16_t)timeout;
-}
-
static bool pa_decode_base(struct bt_data *data, void *user_data)
{
const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(data);
diff --git a/tests/bsim/bluetooth/audio/src/vcp_vol_rend_test.c b/tests/bsim/bluetooth/audio/src/vcp_vol_rend_test.c
index 8b7b687..f6d2ae4 100644
--- a/tests/bsim/bluetooth/audio/src/vcp_vol_rend_test.c
+++ b/tests/bsim/bluetooth/audio/src/vcp_vol_rend_test.c
@@ -54,7 +54,7 @@
static char g_aics_desc[AICS_DESC_SIZE];
static volatile bool g_cb;
-static void vcs_state_cb(int err, uint8_t volume, uint8_t mute)
+static void vcs_state_cb(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute)
{
if (err != 0) {
FAIL("VCP state cb err (%d)", err);
@@ -66,7 +66,7 @@
g_cb = true;
}
-static void vcs_flags_cb(int err, uint8_t flags)
+static void vcs_flags_cb(struct bt_conn *conn, int err, uint8_t flags)
{
if (err != 0) {
FAIL("VCP flags cb err (%d)", err);
diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_encrypted.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_encrypted.sh
index b780602..c42b1cf 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_encrypted.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_encrypted.sh
@@ -16,11 +16,13 @@
SIMULATION_ID="broadcaster_encrypted"
Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
- -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=broadcast_source_encrypted -rs=23 -D=2
+ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=broadcast_source_encrypted \
+ -RealEncryption=1 -rs=23 -D=2
Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
- -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=broadcast_sink_encrypted -rs=27 -D=2
+ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=broadcast_sink_encrypted \
+ -RealEncryption=1 -rs=27 -D=2
# Simulation time should be larger than the WAIT_TIME in common.h
Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_client_async_group.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_client_async_group.sh
new file mode 100755
index 0000000..ae9ae83
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_client_async_group.sh
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021-2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SIMULATION_ID="bap_unicast_client_async_group"
+VERBOSITY_LEVEL=2
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+printf "\n\n======== BAP Unicast Client Aync Group parameters test =========\n\n"
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
+ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=unicast_client_async_group -rs=23 -D=1
+
+# Simulation time should be larger than the WAIT_TIME in common.h
+Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
+ -D=1 -sim_length=60e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/adv/compile.sh b/tests/bsim/bluetooth/host/adv/compile.sh
index fda294c..845f86d 100755
--- a/tests/bsim/bluetooth/host/adv/compile.sh
+++ b/tests/bsim/bluetooth/host/adv/compile.sh
@@ -16,8 +16,8 @@
app=tests/bsim/bluetooth/host/adv/periodic compile
app=tests/bsim/bluetooth/host/adv/periodic conf_file=prj_long_data.conf compile
app=tests/bsim/bluetooth/host/adv/periodic conf_file=prj_coded.conf compile
-app=tests/bsim/bluetooth/host/adv/encrypted/css_sample_data compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/compile.sh
app=tests/bsim/bluetooth/host/adv/encrypted/ead_sample compile
-app=tests/bsim/bluetooth/host/adv/long_ad compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/adv/long_ad/compile.sh
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/compile.sh
diff --git a/tests/bsim/bluetooth/host/adv/long_ad/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/long_ad/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/adv/long_ad/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/adv/long_ad/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/compile.sh b/tests/bsim/bluetooth/host/att/compile.sh
index 59d232b..46fddfa 100755
--- a/tests/bsim/bluetooth/host/att/compile.sh
+++ b/tests/bsim/bluetooth/host/att/compile.sh
@@ -15,18 +15,12 @@
app=tests/bsim/bluetooth/host/att/eatt conf_file=prj_multiple_conn.conf compile
app=tests/bsim/bluetooth/host/att/eatt conf_file=prj_autoconnect.conf compile
app=tests/bsim/bluetooth/host/att/eatt_notif conf_file=prj.conf compile
-app=tests/bsim/bluetooth/host/att/mtu_update compile
-app=tests/bsim/bluetooth/host/att/read_fill_buf/client compile
-app=tests/bsim/bluetooth/host/att/read_fill_buf/server compile
-app=tests/bsim/bluetooth/host/att/retry_on_sec_err/client compile
-app=tests/bsim/bluetooth/host/att/retry_on_sec_err/server compile
-app=tests/bsim/bluetooth/host/att/sequential/dut compile
-app=tests/bsim/bluetooth/host/att/sequential/tester compile
-app=tests/bsim/bluetooth/host/att/pipeline/dut compile
-app=tests/bsim/bluetooth/host/att/pipeline/dut \
- conf_file='prj.conf;rx_tx_prio_invert.extra.conf' compile
-app=tests/bsim/bluetooth/host/att/pipeline/tester compile
-app=tests/bsim/bluetooth/host/att/long_read compile
-app=tests/bsim/bluetooth/host/att/open_close compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/mtu_update/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/read_fill_buf/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/retry_on_sec_err/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/sequential/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/pipeline/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/long_read/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/att/open_close/compile.sh
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/long_read/compile.sh
similarity index 100%
copy from tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh
copy to tests/bsim/bluetooth/host/att/long_read/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh
deleted file mode 100755
index 718910a..0000000
--- a/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-# Copyright 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-set -eu
-: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}"
-
-INCR_BUILD=1
-
-source ${ZEPHYR_BASE}/tests/bsim/compile.source
-
-app="$(guess_test_relpath)" compile
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/CMakeLists.txt b/tests/bsim/bluetooth/host/att/mtu_update/CMakeLists.txt
index 575b041..737bd9b 100644
--- a/tests/bsim/bluetooth/host/att/mtu_update/CMakeLists.txt
+++ b/tests/bsim/bluetooth/host/att/mtu_update/CMakeLists.txt
@@ -5,12 +5,18 @@
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(bsim_test_mtu_update)
-target_sources(app PRIVATE
- src/main.c
- ${ZEPHYR_BASE}/samples/bluetooth/mtu_update/central/src/central_mtu_update.c
+target_include_directories(app PRIVATE src)
+
+target_sources_ifdef(CONFIG_BT_PERIPHERAL app PRIVATE
+ src/main_peripheral.c
${ZEPHYR_BASE}/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
)
+target_sources_ifdef(CONFIG_BT_CENTRAL app PRIVATE
+ src/main_central.c
+ ${ZEPHYR_BASE}/samples/bluetooth/mtu_update/central/src/central_mtu_update.c
+)
+
zephyr_include_directories(
${BSIM_COMPONENTS_PATH}/libUtilv1/src/
${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/compile.sh b/tests/bsim/bluetooth/host/att/mtu_update/compile.sh
new file mode 100755
index 0000000..6c611c5
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/compile.sh
@@ -0,0 +1,14 @@
+#!/usr/bin/env bash
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+set -eu
+: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}"
+
+INCR_BUILD=1
+source ${ZEPHYR_BASE}/tests/bsim/compile.source
+
+app="$(guess_test_relpath)" conf_file=prj_central.conf compile
+app="$(guess_test_relpath)" conf_file=prj_peripheral.conf compile
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/prj.conf b/tests/bsim/bluetooth/host/att/mtu_update/prj.conf
deleted file mode 100644
index 9550168..0000000
--- a/tests/bsim/bluetooth/host/att/mtu_update/prj.conf
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BT=y
-CONFIG_BT_CENTRAL=y
-CONFIG_BT_PERIPHERAL=y
-CONFIG_BT_DEVICE_NAME="MTU Update Test"
-
-CONFIG_BT_GATT_CLIENT=y
-
-# HCI ACL buffers size
-# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE
-CONFIG_BT_BUF_ACL_RX_SIZE=251
-
-# L2CAP SDU/PDU TX MTU
-CONFIG_BT_L2CAP_TX_MTU=247
-
-CONFIG_LOG=y
-CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/prj_central.conf b/tests/bsim/bluetooth/host/att/mtu_update/prj_central.conf
new file mode 100644
index 0000000..3112e95
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/prj_central.conf
@@ -0,0 +1,15 @@
+CONFIG_BT=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_DEVICE_NAME="MTU Update Test"
+
+CONFIG_BT_GATT_CLIENT=y
+
+# HCI ACL buffers size
+# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE
+CONFIG_BT_BUF_ACL_RX_SIZE=251
+
+# L2CAP SDU/PDU TX MTU
+CONFIG_BT_L2CAP_TX_MTU=247
+
+CONFIG_LOG=y
+CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/prj_peripheral.conf b/tests/bsim/bluetooth/host/att/mtu_update/prj_peripheral.conf
new file mode 100644
index 0000000..79a6f73
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/prj_peripheral.conf
@@ -0,0 +1,13 @@
+CONFIG_BT=y
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_DEVICE_NAME="MTU Update Test"
+
+# HCI ACL buffers size
+# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE
+CONFIG_BT_BUF_ACL_RX_SIZE=251
+
+# L2CAP SDU/PDU TX MTU
+CONFIG_BT_L2CAP_TX_MTU=247
+
+CONFIG_LOG=y
+CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/src/common.h b/tests/bsim/bluetooth/host/att/mtu_update/src/common.h
new file mode 100644
index 0000000..426bef3
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/src/common.h
@@ -0,0 +1,37 @@
+/*
+ * Common functions and helpers for MTU Update test
+ *
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+
+#include "bs_types.h"
+#include "bs_tracing.h"
+#include "bstests.h"
+
+#define FAIL(...) \
+ do { \
+ bst_result = Failed; \
+ bs_trace_error_time_line(__VA_ARGS__); \
+ } while (0)
+
+#define PASS(...) \
+ do { \
+ bst_result = Passed; \
+ bs_trace_info_time(1, __VA_ARGS__); \
+ } while (0)
+
+extern enum bst_result_t bst_result;
+
+#define CREATE_FLAG(flag) static atomic_t flag = (atomic_t)false
+#define SET_FLAG(flag) (void)atomic_set(&flag, (atomic_t)true)
+#define WAIT_FOR_FLAG(flag) \
+ while (!(bool)atomic_get(&flag)) { \
+ (void)k_sleep(K_MSEC(1)); \
+ }
+
+#define WAIT_TIME (20e6) /* 20 seconds */
+#define PERIPHERAL_NOTIFY_TIME ((WAIT_TIME - 10e6) / 1e6)
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/src/main.c b/tests/bsim/bluetooth/host/att/mtu_update/src/main.c
deleted file mode 100644
index 47b62d8..0000000
--- a/tests/bsim/bluetooth/host/att/mtu_update/src/main.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <zephyr/kernel.h>
-
-#include <zephyr/sys/printk.h>
-
-#include <zephyr/bluetooth/gatt.h>
-
-#include "bs_types.h"
-#include "bs_tracing.h"
-#include "time_machine.h"
-#include "bstests.h"
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(bt_bsim_mtu_update, LOG_LEVEL_DBG);
-
-extern void run_central_sample(void *cb);
-extern void run_peripheral_sample(uint8_t *notify_data, size_t notify_data_size, uint16_t seconds);
-
-#define FAIL(...) \
- do { \
- bst_result = Failed; \
- bs_trace_error_time_line(__VA_ARGS__); \
- } while (0)
-
-#define PASS(...) \
- do { \
- bst_result = Passed; \
- bs_trace_info_time(1, __VA_ARGS__); \
- } while (0)
-
-extern enum bst_result_t bst_result;
-
-#define CREATE_FLAG(flag) static atomic_t flag = (atomic_t)false
-#define SET_FLAG(flag) (void)atomic_set(&flag, (atomic_t)true)
-#define WAIT_FOR_FLAG(flag) \
- while (!(bool)atomic_get(&flag)) { \
- (void)k_sleep(K_MSEC(1)); \
- }
-
-#define WAIT_TIME (20e6) /* 20 seconds */
-#define PERIPHERAL_NOTIFY_TIME ((WAIT_TIME - 10e6) / 1e6)
-
-CREATE_FLAG(flag_notification_received);
-uint8_t notify_data[100] = {};
-uint8_t is_data_equal;
-
-static uint8_t notify_cb(struct bt_conn *conn, struct bt_gatt_subscribe_params *params,
- const void *data, uint16_t length)
-{
- printk("BSIM NOTIFY_CALLBACK\n");
-
- is_data_equal = (length == sizeof(notify_data) && !memcmp(notify_data, data, length));
-
- LOG_HEXDUMP_DBG(data, length, "notification data");
- LOG_HEXDUMP_DBG(notify_data, sizeof(notify_data), "expected data");
-
- SET_FLAG(flag_notification_received);
-
- return 0;
-}
-
-static void test_central_main(void)
-{
- notify_data[13] = 0x7f;
- notify_data[99] = 0x55;
-
- run_central_sample(notify_cb);
-
- WAIT_FOR_FLAG(flag_notification_received);
-
- if (is_data_equal) {
- PASS("MTU Update test passed\n");
- } else {
- FAIL("MTU Update test failed\n");
- }
-}
-
-static void test_peripheral_main(void)
-{
- notify_data[13] = 0x7f;
- notify_data[99] = 0x55;
-
- run_peripheral_sample(notify_data, sizeof(notify_data), PERIPHERAL_NOTIFY_TIME);
-
- PASS("MTU Update test passed\n");
-}
-
-void test_tick(bs_time_t HW_device_time)
-{
- if (bst_result != Passed) {
- FAIL("Test failed (not passed after %i seconds)\n", WAIT_TIME);
- }
-}
-
-static void test_mtu_update_init(void)
-{
- bst_ticker_set_next_tick_absolute(WAIT_TIME);
- bst_result = In_progress;
-}
-
-static const struct bst_test_instance test_def[] = {
- {
- .test_id = "central",
- .test_descr = "Central GATT MTU Update",
- .test_pre_init_f = test_mtu_update_init,
- .test_tick_f = test_tick,
- .test_main_f = test_central_main
- },
- {
- .test_id = "peripheral",
- .test_descr = "Peripheral GATT MTU Update",
- .test_pre_init_f = test_mtu_update_init,
- .test_tick_f = test_tick,
- .test_main_f = test_peripheral_main
- },
- BSTEST_END_MARKER
-};
-
-struct bst_test_list *test_mtu_update_install(struct bst_test_list *tests)
-{
- return bst_add_tests(tests, test_def);
-}
-
-bst_test_install_t test_installers[] = {
- test_mtu_update_install,
- NULL
-};
-
-int main(void)
-{
- bst_main();
- return 0;
-}
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/src/main_central.c b/tests/bsim/bluetooth/host/att/mtu_update/src/main_central.c
new file mode 100644
index 0000000..d41cf84
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/src/main_central.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/kernel.h>
+
+#include <zephyr/sys/printk.h>
+
+#include <zephyr/bluetooth/gatt.h>
+
+#include "common.h"
+#include "time_machine.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bt_bsim_mtu_update, LOG_LEVEL_DBG);
+
+extern void run_central_sample(void *cb);
+
+CREATE_FLAG(flag_notification_received);
+uint8_t notify_data[100] = {};
+uint8_t is_data_equal;
+
+static uint8_t notify_cb(struct bt_conn *conn, struct bt_gatt_subscribe_params *params,
+ const void *data, uint16_t length)
+{
+ printk("BSIM NOTIFY_CALLBACK\n");
+
+ is_data_equal = (length == sizeof(notify_data) && !memcmp(notify_data, data, length));
+
+ LOG_HEXDUMP_DBG(data, length, "notification data");
+ LOG_HEXDUMP_DBG(notify_data, sizeof(notify_data), "expected data");
+
+ SET_FLAG(flag_notification_received);
+
+ return 0;
+}
+
+static void test_central_main(void)
+{
+ notify_data[13] = 0x7f;
+ notify_data[99] = 0x55;
+
+ run_central_sample(notify_cb);
+
+ WAIT_FOR_FLAG(flag_notification_received);
+
+ if (is_data_equal) {
+ PASS("MTU Update test passed\n");
+ } else {
+ FAIL("MTU Update test failed\n");
+ }
+}
+
+void test_tick(bs_time_t HW_device_time)
+{
+ if (bst_result != Passed) {
+ FAIL("Test failed (not passed after %i seconds)\n", WAIT_TIME);
+ }
+}
+
+static void test_mtu_update_init(void)
+{
+ bst_ticker_set_next_tick_absolute(WAIT_TIME);
+ bst_result = In_progress;
+}
+
+static const struct bst_test_instance test_def[] = {
+ {
+ .test_id = "central",
+ .test_descr = "Central GATT MTU Update",
+ .test_pre_init_f = test_mtu_update_init,
+ .test_tick_f = test_tick,
+ .test_main_f = test_central_main
+ },
+ BSTEST_END_MARKER
+};
+
+struct bst_test_list *test_mtu_update_install(struct bst_test_list *tests)
+{
+ return bst_add_tests(tests, test_def);
+}
+
+bst_test_install_t test_installers[] = {
+ test_mtu_update_install,
+ NULL
+};
+
+int main(void)
+{
+ bst_main();
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/src/main_peripheral.c b/tests/bsim/bluetooth/host/att/mtu_update/src/main_peripheral.c
new file mode 100644
index 0000000..9124965
--- /dev/null
+++ b/tests/bsim/bluetooth/host/att/mtu_update/src/main_peripheral.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/kernel.h>
+
+#include <zephyr/sys/printk.h>
+
+#include "common.h"
+#include "time_machine.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bt_bsim_mtu_update, LOG_LEVEL_DBG);
+
+extern void run_peripheral_sample(uint8_t *notify_data, size_t notify_data_size, uint16_t seconds);
+
+uint8_t notify_data[100] = {};
+
+static void test_peripheral_main(void)
+{
+ notify_data[13] = 0x7f;
+ notify_data[99] = 0x55;
+
+ run_peripheral_sample(notify_data, sizeof(notify_data), PERIPHERAL_NOTIFY_TIME);
+
+ PASS("MTU Update test passed\n");
+}
+
+void test_tick(bs_time_t HW_device_time)
+{
+ if (bst_result != Passed) {
+ FAIL("Test failed (not passed after %i seconds)\n", WAIT_TIME);
+ }
+}
+
+static void test_mtu_update_init(void)
+{
+ bst_ticker_set_next_tick_absolute(WAIT_TIME);
+ bst_result = In_progress;
+}
+
+static const struct bst_test_instance test_def[] = {
+ {
+ .test_id = "peripheral",
+ .test_descr = "Peripheral GATT MTU Update",
+ .test_pre_init_f = test_mtu_update_init,
+ .test_tick_f = test_tick,
+ .test_main_f = test_peripheral_main
+ },
+ BSTEST_END_MARKER
+};
+
+struct bst_test_list *test_mtu_update_install(struct bst_test_list *tests)
+{
+ return bst_add_tests(tests, test_def);
+}
+
+bst_test_install_t test_installers[] = {
+ test_mtu_update_install,
+ NULL
+};
+
+int main(void)
+{
+ bst_main();
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh
deleted file mode 100755
index 42740d4..0000000
--- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/usr/bin/env bash
-# Copyright 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-set -eu
-: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}"
-
-INCR_BUILD=1
-source ${ZEPHYR_BASE}/tests/bsim/compile.source
-
-app="$(guess_test_relpath)" compile
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh
index 37901c3..f2947d6 100755
--- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh
+++ b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh
@@ -5,13 +5,14 @@
set -eu
source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
-simulation_id="$(guess_test_long_name)"
+simulation_id="mtu_update"
verbosity_level=2
-central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf"
-peripheral_exe="${central_exe}"
cd ${BSIM_OUT_PATH}/bin
+central_exe="./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_mtu_update_prj_central_conf"
+peripheral_exe="./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_mtu_update_prj_peripheral_conf"
+
Execute "$central_exe" \
-v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -RealEncryption=1
diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/open_close/compile.sh
similarity index 100%
copy from tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh
copy to tests/bsim/bluetooth/host/att/open_close/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh
deleted file mode 100755
index de926e8..0000000
--- a/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/usr/bin/env bash
-# Copyright 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-set -eu
-
-: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}"
-
-INCR_BUILD=1
-
-source ${ZEPHYR_BASE}/tests/bsim/compile.source
-
-app="$(guess_test_relpath)" compile
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/pipeline/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/att/pipeline/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c b/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
index 90fdd6f..803917c 100644
--- a/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
@@ -387,7 +387,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/att/read_fill_buf/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/att/retry_on_sec_err/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/sequential/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/att/sequential/compile.sh
diff --git a/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c b/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
index cecbd8c..57fbc42 100644
--- a/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
@@ -363,7 +363,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/compile.sh b/tests/bsim/bluetooth/host/compile.sh
index c7c2975..b735ab2 100755
--- a/tests/bsim/bluetooth/host/compile.sh
+++ b/tests/bsim/bluetooth/host/compile.sh
@@ -21,25 +21,24 @@
app=tests/bsim/bluetooth/host/iso/cis compile
app=tests/bsim/bluetooth/host/iso/bis compile
app=tests/bsim/bluetooth/host/iso/frag compile
+app=tests/bsim/bluetooth/host/iso/frag_2 compile
app=tests/bsim/bluetooth/host/misc/disable compile
-app=tests/bsim/bluetooth/host/misc/disconnect/dut compile
-app=tests/bsim/bluetooth/host/misc/disconnect/tester compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/misc/disconnect/compile.sh
app=tests/bsim/bluetooth/host/misc/conn_stress/central compile
app=tests/bsim/bluetooth/host/misc/conn_stress/peripheral compile
-app=tests/bsim/bluetooth/host/misc/hfc compile
-app=tests/bsim/bluetooth/host/misc/hfc_multilink/dut compile
-app=tests/bsim/bluetooth/host/misc/hfc_multilink/tester compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/misc/hfc/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/misc/hfc_multilink/compile.sh
app=tests/bsim/bluetooth/host/misc/unregister_conn_cb compile
-app=tests/bsim/bluetooth/host/misc/sample_test compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/misc/sample_test/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/misc/acl_tx_frag/compile.sh
-app=tests/bsim/bluetooth/host/privacy/central compile
-app=tests/bsim/bluetooth/host/privacy/peripheral compile
-app=tests/bsim/bluetooth/host/privacy/peripheral conf_file=prj_rpa_expired.conf compile
-app=tests/bsim/bluetooth/host/privacy/peripheral conf_file=prj_rpa_sharing.conf compile
-app=tests/bsim/bluetooth/host/privacy/device compile
-app=tests/bsim/bluetooth/host/privacy/legacy compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/privacy/central/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/privacy/peripheral/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/privacy/device/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/privacy/legacy/compile.sh
-app=tests/bsim/bluetooth/host/id/settings compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/id/settings/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/scan/start_stop/compile.sh
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/gatt/ccc_store/compile.sh
diff --git a/tests/bsim/bluetooth/host/gatt/compile.sh b/tests/bsim/bluetooth/host/gatt/compile.sh
index 67ebb09..d26e400 100755
--- a/tests/bsim/bluetooth/host/gatt/compile.sh
+++ b/tests/bsim/bluetooth/host/gatt/compile.sh
@@ -16,10 +16,8 @@
app=tests/bsim/bluetooth/host/gatt/general compile
app=tests/bsim/bluetooth/host/gatt/notify compile
app=tests/bsim/bluetooth/host/gatt/notify_multiple compile
-app=tests/bsim/bluetooth/host/gatt/settings compile
-app=tests/bsim/bluetooth/host/gatt/settings conf_file=prj_2.conf compile
-app=tests/bsim/bluetooth/host/gatt/ccc_store compile
-app=tests/bsim/bluetooth/host/gatt/ccc_store conf_file=prj_2.conf compile
-app=tests/bsim/bluetooth/host/gatt/sc_indicate compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/gatt/settings/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/gatt/ccc_store/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/gatt/sc_indicate/compile.sh
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/sc_indicate/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/gatt/sc_indicate/compile.sh
diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/settings/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/gatt/settings/compile.sh
diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/id/settings/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/id/settings/compile.sh
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/CMakeLists.txt b/tests/bsim/bluetooth/host/iso/frag_2/CMakeLists.txt
new file mode 100644
index 0000000..9fa69bf
--- /dev/null
+++ b/tests/bsim/bluetooth/host/iso/frag_2/CMakeLists.txt
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(bsim_test_iso_frag_2)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+target_sources(app PRIVATE
+ src/broadcaster.c
+ src/main.c
+)
+
+zephyr_include_directories(
+ ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+ ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+)
+
+target_link_options(app PUBLIC -Wl,--wrap=bt_send)
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/prj.conf b/tests/bsim/bluetooth/host/iso/frag_2/prj.conf
new file mode 100644
index 0000000..4ae6391
--- /dev/null
+++ b/tests/bsim/bluetooth/host/iso/frag_2/prj.conf
@@ -0,0 +1,33 @@
+CONFIG_LOG=y
+CONFIG_BT_ISO_LOG_LEVEL_DBG=y
+# CONFIG_BT_CONN_LOG_LEVEL_DBG=y
+
+CONFIG_ASSERT=y
+CONFIG_BT_TESTING=y
+CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y
+
+CONFIG_BT=y
+CONFIG_BT_DEVICE_NAME="ISO frag test 2"
+
+CONFIG_BT_EXT_ADV=y
+CONFIG_BT_PER_ADV=y
+CONFIG_BT_PER_ADV_SYNC=y
+
+CONFIG_BT_ISO_BROADCASTER=y
+CONFIG_BT_ISO_TX_BUF_COUNT=2
+CONFIG_BT_ISO_MAX_CHAN=2
+CONFIG_BT_ISO_TX_MTU=100
+CONFIG_BT_ISO_RX_MTU=100
+
+# Controller ISO configs
+CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_BUFFERS=10
+
+# Controller Extended Advertising configs
+CONFIG_BT_CTLR_ADV_EXT=y
+CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
+
+# ISO Broadcaster Controller
+CONFIG_BT_CTLR_ADV_PERIODIC=y
+CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=247
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c b/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c
new file mode 100644
index 0000000..6b70c3f
--- /dev/null
+++ b/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+#include "babblekit/flags.h"
+#include "babblekit/testcase.h"
+
+LOG_MODULE_REGISTER(broadcaster, LOG_LEVEL_INF);
+
+static struct bt_iso_chan iso_chans[CONFIG_BT_ISO_MAX_CHAN];
+static struct bt_iso_chan *default_chan = &iso_chans[0];
+
+NET_BUF_POOL_FIXED_DEFINE(tx_pool, CONFIG_BT_ISO_TX_BUF_COUNT,
+ BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU),
+ CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
+
+static DEFINE_FLAG(iso_connected);
+static DEFINE_FLAG(first_frag);
+static DEFINE_FLAG(sdu_sent);
+
+extern void bt_conn_suspend_tx(bool suspend);
+extern void bt_testing_set_iso_mtu(uint16_t mtu);
+
+static int send_data(struct bt_iso_chan *chan)
+{
+ static uint16_t seq;
+ struct net_buf *buf;
+ int err;
+
+ if (!IS_FLAG_SET(iso_connected)) {
+ /* TX has been aborted */
+ return -ENOTCONN;
+ }
+
+ buf = net_buf_alloc(&tx_pool, K_NO_WAIT);
+ TEST_ASSERT(buf != NULL, "Failed to allocate buffer");
+
+ net_buf_reserve(buf, BT_ISO_CHAN_SEND_RESERVE);
+
+ net_buf_add(buf, 40);
+
+ LOG_INF("Sending SDU (headroom %d)", net_buf_headroom(buf));
+ LOG_HEXDUMP_INF(buf->data, buf->len, "SDU payload");
+
+ err = bt_iso_chan_send(default_chan, buf, seq++);
+
+ return err;
+}
+
+static void iso_connected_cb(struct bt_iso_chan *chan)
+{
+ LOG_INF("ISO Channel %p connected", chan);
+
+ SET_FLAG(iso_connected);
+}
+
+static void iso_disconnected_cb(struct bt_iso_chan *chan, uint8_t reason)
+{
+ LOG_INF("ISO Channel %p disconnected (reason 0x%02x)", chan, reason);
+
+ UNSET_FLAG(iso_connected);
+}
+
+static void sdu_sent_cb(struct bt_iso_chan *chan)
+{
+ SET_FLAG(sdu_sent);
+}
+
+static void create_ext_adv(struct bt_le_ext_adv **adv)
+{
+ int err;
+
+ LOG_INF("Creating extended advertising set with periodic advertising");
+
+ /* Create a non-connectable advertising set */
+ err = bt_le_ext_adv_create(BT_LE_EXT_ADV_NCONN, NULL, adv);
+ TEST_ASSERT(err == 0, "Unable to create extended advertising set: %d", err);
+
+ /* Set periodic advertising parameters */
+ err = bt_le_per_adv_set_param(*adv, BT_LE_PER_ADV_PARAM(BT_GAP_PER_ADV_FAST_INT_MIN_2,
+ BT_GAP_PER_ADV_FAST_INT_MAX_2,
+ BT_LE_PER_ADV_OPT_NONE));
+ TEST_ASSERT(err == 0, "Failed to set periodic advertising parameters: %d", err);
+}
+
+static void start_ext_adv(struct bt_le_ext_adv *adv)
+{
+ int err;
+
+ LOG_INF("Starting extended and periodic advertising");
+
+ /* Start extended advertising */
+ err = bt_le_ext_adv_start(adv, BT_LE_EXT_ADV_START_DEFAULT);
+ TEST_ASSERT(err == 0, "Failed to start extended advertising: %d", err);
+
+ /* FIXME: Temporary workaround to get around an assert in the controller
+ * Open issue: https://github.com/zephyrproject-rtos/zephyr/issues/72852
+ */
+ k_sleep(K_MSEC(100));
+
+ /* Enable Periodic Advertising */
+ err = bt_le_per_adv_start(adv);
+ TEST_ASSERT(err == 0, "Failed to enable periodic advertising: %d", err);
+}
+
+static void create_big(struct bt_le_ext_adv *adv, size_t cnt, struct bt_iso_big **out_big)
+{
+ const uint16_t latency_ms = 10U;
+ const uint16_t sdu_interval_us = 10U * USEC_PER_MSEC;
+
+ struct bt_iso_chan *channels[ARRAY_SIZE(iso_chans)];
+ struct bt_iso_big_create_param param = {
+ .packing = BT_ISO_PACKING_SEQUENTIAL,
+ .framing = BT_ISO_FRAMING_UNFRAMED,
+ .interval = sdu_interval_us,
+ .bis_channels = channels,
+ .latency = latency_ms,
+ .encryption = false,
+ .num_bis = cnt,
+ };
+ int err;
+
+ for (size_t i = 0U; i < cnt; i++) {
+ channels[i] = &iso_chans[i];
+ }
+
+ LOG_INF("Creating BIG");
+
+ err = bt_iso_big_create(adv, ¶m, out_big);
+ TEST_ASSERT(err == 0, "Failed to create BIG: %d", err);
+
+ WAIT_FOR_FLAG(iso_connected);
+}
+
+struct bt_le_ext_adv *adv;
+struct bt_iso_big *big;
+
+static struct bt_iso_chan_ops iso_ops = {
+ .disconnected = iso_disconnected_cb,
+ .connected = iso_connected_cb,
+ .sent = sdu_sent_cb,
+};
+static struct bt_iso_chan_io_qos iso_tx = {
+ .sdu = CONFIG_BT_ISO_TX_MTU,
+ .phy = BT_GAP_LE_PHY_2M,
+ .rtn = 1,
+ .path = NULL,
+};
+static struct bt_iso_chan_qos iso_qos = {
+ .tx = &iso_tx,
+ .rx = NULL,
+};
+
+static void init(void)
+{
+ int err;
+
+ err = bt_enable(NULL);
+ TEST_ASSERT(err == 0, "Bluetooth enable failed: %d", err);
+}
+
+static void connect_iso(void)
+{
+ bt_testing_set_iso_mtu(10);
+
+ for (size_t i = 0U; i < ARRAY_SIZE(iso_chans); i++) {
+ iso_chans[i].ops = &iso_ops;
+ iso_chans[i].qos = &iso_qos;
+ }
+
+ create_ext_adv(&adv);
+ create_big(adv, 1U, &big);
+ start_ext_adv(adv);
+}
+
+static void disconnect_iso(void)
+{
+ int err;
+
+ err = bt_iso_big_terminate(big);
+ TEST_ASSERT(err == 0, "bt_iso_big_terminate failed (%d)", err);
+ err = bt_le_per_adv_stop(adv);
+ TEST_ASSERT(err == 0, "bt_le_per_adv_stop failed (%d)", err);
+ k_msleep(100);
+ err = bt_le_ext_adv_stop(adv);
+ TEST_ASSERT(err == 0, "bt_le_ext_adv_stop failed (%d)", err);
+ k_msleep(100);
+ err = bt_le_ext_adv_delete(adv);
+ TEST_ASSERT(err == 0, "bt_le_ext_adv_delete failed (%d)", err);
+
+ big = NULL;
+ adv = NULL;
+}
+
+void entrypoint_broadcaster(void)
+{
+ /* Test purpose:
+ *
+ * Verifies that we are not leaking buffers when getting disconnected
+ * while sending fragmented ISO SDU.
+ *
+ * One device:
+ * - `broadcaster`: sends fragmented ISO SDUs
+ *
+ * Procedure:
+ * - initialize Bluetooth and a BIS
+ * - send a fragmented SDU
+ * - disconnect when the first fragment is sent
+ * - repeat TEST_ITERATIONS time
+ *
+ * [verdict]
+ * - no buffer is leaked and repeating the operation success
+ */
+ int err;
+ uint8_t TEST_ITERATIONS = 4;
+
+ LOG_INF("Starting ISO HCI fragmentation test 2");
+
+ init();
+
+ for (size_t i = 0; i < TEST_ITERATIONS; i++) {
+ connect_iso();
+
+ /* Send an SDU */
+ err = send_data(default_chan);
+ TEST_ASSERT(!err, "Failed to send data w/o TS (err %d)", err);
+
+ /* Wait until we have sent the first SDU fragment. */
+ WAIT_FOR_FLAG(first_frag);
+
+ disconnect_iso();
+ bt_conn_suspend_tx(false);
+
+ k_msleep(1000);
+ }
+
+ TEST_PASS_AND_EXIT("Test passed");
+}
+
+void validate_no_iso_frag(struct net_buf *buf)
+{
+ struct bt_hci_iso_hdr *hci_hdr = (void *)buf->data;
+
+ uint16_t handle = sys_le16_to_cpu(hci_hdr->handle);
+ uint8_t flags = bt_iso_flags(handle);
+ uint8_t pb_flag = bt_iso_flags_pb(flags);
+
+ TEST_ASSERT(pb_flag == BT_ISO_SINGLE, "Packet was fragmented");
+}
+
+int __real_bt_send(struct net_buf *buf);
+
+int __wrap_bt_send(struct net_buf *buf)
+{
+ struct bt_hci_iso_hdr *hci_hdr = (void *)buf->data;
+
+ if (bt_buf_get_type(buf) == BT_BUF_ISO_OUT) {
+ uint16_t handle = sys_le16_to_cpu(hci_hdr->handle);
+ uint8_t flags = bt_iso_flags(handle);
+ uint8_t pb_flag = bt_iso_flags_pb(flags);
+
+ if (pb_flag == BT_ISO_START) {
+ SET_FLAG(first_frag);
+ bt_conn_suspend_tx(true);
+ }
+ }
+
+ return __real_bt_send(buf);
+}
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/src/main.c b/tests/bsim/bluetooth/host/iso/frag_2/src/main.c
new file mode 100644
index 0000000..e87fbbb
--- /dev/null
+++ b/tests/bsim/bluetooth/host/iso/frag_2/src/main.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include "bs_tracing.h"
+#include "bstests.h"
+#include "babblekit/testcase.h"
+
+extern void entrypoint_broadcaster(void);
+extern enum bst_result_t bst_result;
+
+
+static void test_end_cb(void)
+{
+ if (bst_result != Passed) {
+ TEST_PRINT("Test has not passed.");
+ }
+}
+
+static const struct bst_test_instance entrypoints[] = {
+ {
+ .test_id = "broadcaster",
+ .test_delete_f = test_end_cb,
+ .test_main_f = entrypoint_broadcaster,
+ },
+ BSTEST_END_MARKER,
+};
+
+static struct bst_test_list *install(struct bst_test_list *tests)
+{
+ return bst_add_tests(tests, entrypoints);
+};
+
+bst_test_install_t test_installers[] = {install, NULL};
+
+int main(void)
+{
+ bst_main();
+
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/host/l2cap/multilink_peripheral/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/iso/frag_2/tests_scripts/_compile.sh
similarity index 100%
copy from tests/bsim/bluetooth/host/l2cap/multilink_peripheral/test_scripts/_compile.sh
copy to tests/bsim/bluetooth/host/iso/frag_2/tests_scripts/_compile.sh
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/tests_scripts/bis.sh b/tests/bsim/bluetooth/host/iso/frag_2/tests_scripts/bis.sh
new file mode 100755
index 0000000..c6307d3
--- /dev/null
+++ b/tests/bsim/bluetooth/host/iso/frag_2/tests_scripts/bis.sh
@@ -0,0 +1,18 @@
+#!/usr/bin/env bash
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+simulation_id="iso_frag_2"
+verbosity_level=2
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+ -D=1 -sim_length=30e6 $@
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_iso_frag_2_prj_conf \
+ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=broadcaster
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/l2cap/compile.sh b/tests/bsim/bluetooth/host/l2cap/compile.sh
index 9485c53..71d41a7 100755
--- a/tests/bsim/bluetooth/host/l2cap/compile.sh
+++ b/tests/bsim/bluetooth/host/l2cap/compile.sh
@@ -11,19 +11,15 @@
source ${ZEPHYR_BASE}/tests/bsim/compile.source
app=tests/bsim/bluetooth/host/l2cap/many_conns compile
-app=tests/bsim/bluetooth/host/l2cap/multilink_peripheral compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/l2cap/multilink_peripheral/compile.sh
app=tests/bsim/bluetooth/host/l2cap/general compile
app=tests/bsim/bluetooth/host/l2cap/userdata compile
-app=tests/bsim/bluetooth/host/l2cap/userdata conf_file=prj_no_checks.conf compile
app=tests/bsim/bluetooth/host/l2cap/stress compile
app=tests/bsim/bluetooth/host/l2cap/stress conf_file=prj_nofrag.conf compile
app=tests/bsim/bluetooth/host/l2cap/stress conf_file=prj_syswq.conf compile
-app=tests/bsim/bluetooth/host/l2cap/split/dut compile
-app=tests/bsim/bluetooth/host/l2cap/split/tester compile
-app=tests/bsim/bluetooth/host/l2cap/reassembly/dut compile
-app=tests/bsim/bluetooth/host/l2cap/reassembly/peer compile
-app=tests/bsim/bluetooth/host/l2cap/ecred/dut compile
-app=tests/bsim/bluetooth/host/l2cap/ecred/peer compile
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/l2cap/split/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/l2cap/reassembly/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/l2cap/ecred/compile.sh
app=tests/bsim/bluetooth/host/l2cap/credits compile
app=tests/bsim/bluetooth/host/l2cap/credits conf_file=prj_ecred.conf compile
app=tests/bsim/bluetooth/host/l2cap/credits_seg_recv compile
diff --git a/tests/bsim/bluetooth/host/l2cap/ecred/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/ecred/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/l2cap/ecred/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/l2cap/ecred/compile.sh
diff --git a/tests/bsim/bluetooth/host/l2cap/multilink_peripheral/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/multilink_peripheral/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/l2cap/multilink_peripheral/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/l2cap/multilink_peripheral/compile.sh
diff --git a/tests/bsim/bluetooth/host/l2cap/reassembly/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/reassembly/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/l2cap/reassembly/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/l2cap/reassembly/compile.sh
diff --git a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
index 2d55513..dce8ffb 100644
--- a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
+++ b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
@@ -328,7 +328,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/split/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/l2cap/split/compile.sh
diff --git a/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c b/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
index f762ee8..7339c91 100644
--- a/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
@@ -343,7 +343,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/l2cap/userdata/prj_no_checks.conf b/tests/bsim/bluetooth/host/l2cap/userdata/prj_no_checks.conf
deleted file mode 100644
index 40f4599..0000000
--- a/tests/bsim/bluetooth/host/l2cap/userdata/prj_no_checks.conf
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BT=y
-CONFIG_BT_CENTRAL=y
-CONFIG_BT_PERIPHERAL=y
-CONFIG_BT_SMP=y
-CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y
-CONFIG_BT_L2CAP_ECRED=y
-
-CONFIG_ASSERT=y
-CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y
-
-CONFIG_LOG=y
-CONFIG_LOG_THREAD_ID_PREFIX=y
-CONFIG_THREAD_NAME=y
-# CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y
-
-CONFIG_NO_RUNTIME_CHECKS=y
diff --git a/tests/bsim/bluetooth/host/l2cap/userdata/src/main_l2cap_userdata.c b/tests/bsim/bluetooth/host/l2cap/userdata/src/main_l2cap_userdata.c
index d11e56c..d7f42d0 100644
--- a/tests/bsim/bluetooth/host/l2cap/userdata/src/main_l2cap_userdata.c
+++ b/tests/bsim/bluetooth/host/l2cap/userdata/src/main_l2cap_userdata.c
@@ -258,20 +258,7 @@
*/
err = bt_l2cap_chan_send(&channel.chan, buf);
- if (has_checks) {
- /* The stack is supposed to reject `buf` if it has non-null
- * user_data.
- */
- if (err == -EINVAL) {
- PASS("(Enabled-checks) Test passed\n");
- return;
- }
-
- FAIL("Expected EINVAL (%d) got %d\n", -EINVAL, err);
- }
-
- /* We have bypassed runtime checks of user_data. L2CAP will take our
- * `buf` with non-null user_data. We verify that:
+ /* L2CAP will take our `buf` with non-null user_data. We verify that:
* - it is cleared
* - we don't segfault later (e.g. in `tx_notify`)
*/
diff --git a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/_compile.sh
index 7ed5e43..80030a8 100755
--- a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/_compile.sh
+++ b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/_compile.sh
@@ -8,6 +8,5 @@
source ${ZEPHYR_BASE}/tests/bsim/compile.source
app="$(guess_test_relpath)" compile
-app="$(guess_test_relpath)" conf_file=prj_no_checks.conf compile
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh
index 1374442..e5bcdd0 100755
--- a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh
+++ b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh
@@ -20,14 +20,3 @@
-D=2 -sim_length=5e6 $@
wait_for_background_jobs
-
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_userdata_prj_no_checks_conf \
- -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central
-
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_userdata_prj_no_checks_conf \
- -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral
-
-Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
- -D=2 -sim_length=5e6 $@
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/CMakeLists.txt b/tests/bsim/bluetooth/host/misc/acl_tx_frag/CMakeLists.txt
new file mode 100644
index 0000000..cab9cac
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/CMakeLists.txt
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(acl_tx_frag)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib)
+target_link_libraries(app PRIVATE testlib)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+zephyr_include_directories(
+ ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+ ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+)
+
+target_sources(app PRIVATE
+ src/main.c
+ src/dut.c
+ src/peer.c
+)
diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/acl_tx_frag/compile.sh
similarity index 100%
copy from tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh
copy to tests/bsim/bluetooth/host/misc/acl_tx_frag/compile.sh
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/prj.conf b/tests/bsim/bluetooth/host/misc/acl_tx_frag/prj.conf
new file mode 100644
index 0000000..6bd02c8
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/prj.conf
@@ -0,0 +1,50 @@
+CONFIG_BT=y
+CONFIG_BT_DEVICE_NAME="acl_tx_frag"
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_CENTRAL=y
+
+# Dependency of testlib/adv and testlib/scan.
+CONFIG_BT_EXT_ADV=y
+
+CONFIG_BT_GATT_CLIENT=y
+CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y
+
+CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION=n
+
+CONFIG_ASSERT=y
+CONFIG_LOG=y
+CONFIG_LOG_RUNTIME_FILTERING=y
+CONFIG_THREAD_NAME=y
+CONFIG_LOG_THREAD_ID_PREFIX=y
+CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y
+
+# Disable auto-initiated procedures so they don't
+# mess with the test's execution.
+CONFIG_BT_AUTO_PHY_UPDATE=n
+CONFIG_BT_AUTO_DATA_LEN_UPDATE=n
+CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n
+
+CONFIG_BT_MAX_CONN=1
+
+# We don't want to be constrained on the number of TX
+# contexts, rather on the number of LL TX buffers.
+CONFIG_BT_CONN_TX_MAX=10
+
+# Outgoing ATT buffers
+CONFIG_BT_ATT_TX_COUNT=1
+
+# Allow big ATT MTU
+CONFIG_BT_BUF_ACL_RX_SIZE=100
+CONFIG_BT_L2CAP_TX_MTU=100
+
+# Controller buffers
+CONFIG_BT_BUF_ACL_TX_COUNT=1
+CONFIG_BT_BUF_ACL_TX_SIZE=27
+
+# If we don't define this, it will inherit
+# CONFIG_BT_BUF_ACL_TX_COUNT and fail a build assert that
+# expects >= 3.
+CONFIG_BT_L2CAP_TX_BUF_COUNT=3
+
+# For indication param structs. It's fine, we run on native.
+CONFIG_HEAP_MEM_POOL_SIZE=1024
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/data.h b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/data.h
new file mode 100644
index 0000000..59912b2
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/data.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_ACL_TX_FRAG_SRC_DATA_H_
+#define ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_ACL_TX_FRAG_SRC_DATA_H_
+
+#include <zephyr/bluetooth/uuid.h>
+
+#define TEST_ITERATIONS 3
+
+/* overhead: opcode + ATT handle + L2CAP PDU header */
+#define GATT_PAYLOAD_SIZE (CONFIG_BT_L2CAP_TX_MTU - 1 - 2 - 4)
+
+#define test_service_uuid \
+ BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf0debc9a, 0x7856, 0x3412, 0x7856, 0x341278563412))
+#define test_characteristic_uuid \
+ BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf2debc9a, 0x7856, 0x3412, 0x7856, 0x341278563412))
+
+#endif /* ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_ACL_TX_FRAG_SRC_DATA_H_ */
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/dut.c b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/dut.c
new file mode 100644
index 0000000..6fe1123
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/dut.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/logging/log.h>
+
+#include "testlib/conn.h"
+#include "testlib/scan.h"
+#include "testlib/log_utils.h"
+
+#include "babblekit/flags.h"
+#include "babblekit/testcase.h"
+
+/* For the radio shenanigans */
+#include "hw_testcheat_if.h"
+
+/* local includes */
+#include "data.h"
+
+LOG_MODULE_REGISTER(dut, LOG_LEVEL_DBG);
+
+static DEFINE_FLAG(is_subscribed);
+static DEFINE_FLAG(mtu_has_been_exchanged);
+static DEFINE_FLAG(conn_recycled);
+static DEFINE_FLAG(conn_param_updated);
+static DEFINE_FLAG(indicated);
+
+extern unsigned long runtime_log_level;
+
+static void recycled(void)
+{
+ LOG_DBG("");
+ SET_FLAG(conn_recycled);
+}
+
+static void params_updated(struct bt_conn *conn, uint16_t interval, uint16_t latency,
+ uint16_t timeout)
+{
+ LOG_DBG("");
+ SET_FLAG(conn_param_updated);
+}
+
+static struct bt_conn_cb conn_cbs = {
+ .recycled = recycled,
+ .le_param_updated = params_updated,
+};
+
+static void ccc_changed(const struct bt_gatt_attr *attr, uint16_t value)
+{
+ /* assume we only get it for the `test_gatt_service` */
+ if (value != 0) {
+ SET_FLAG(is_subscribed);
+ } else {
+ UNSET_FLAG(is_subscribed);
+ }
+}
+
+BT_GATT_SERVICE_DEFINE(test_gatt_service, BT_GATT_PRIMARY_SERVICE(test_service_uuid),
+ BT_GATT_CHARACTERISTIC(test_characteristic_uuid,
+ (BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE |
+ BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_INDICATE),
+ BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, NULL, NULL,
+ NULL),
+ BT_GATT_CCC(ccc_changed, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE));
+
+static void _mtu_exchanged(struct bt_conn *conn, uint8_t err,
+ struct bt_gatt_exchange_params *params)
+{
+ LOG_DBG("MTU exchanged");
+ SET_FLAG(mtu_has_been_exchanged);
+}
+
+static void exchange_mtu(struct bt_conn *conn)
+{
+ int err;
+ struct bt_gatt_exchange_params params = {
+ .func = _mtu_exchanged,
+ };
+
+ UNSET_FLAG(mtu_has_been_exchanged);
+
+ err = bt_gatt_exchange_mtu(conn, ¶ms);
+ TEST_ASSERT(!err, "Failed MTU exchange (err %d)", err);
+
+ WAIT_FOR_FLAG(mtu_has_been_exchanged);
+}
+
+#define UPDATE_PARAM_INTERVAL_MIN 500
+#define UPDATE_PARAM_INTERVAL_MAX 500
+#define UPDATE_PARAM_LATENCY 1
+#define UPDATE_PARAM_TIMEOUT 1000
+
+static struct bt_le_conn_param update_params = {
+ .interval_min = UPDATE_PARAM_INTERVAL_MIN,
+ .interval_max = UPDATE_PARAM_INTERVAL_MAX,
+ .latency = UPDATE_PARAM_LATENCY,
+ .timeout = UPDATE_PARAM_TIMEOUT,
+};
+
+void slow_down_conn(struct bt_conn *conn)
+{
+ int err;
+
+ UNSET_FLAG(conn_param_updated);
+ err = bt_conn_le_param_update(conn, &update_params);
+ TEST_ASSERT(!err, "Parameter update failed (err %d)", err);
+ WAIT_FOR_FLAG(conn_param_updated);
+}
+
+static void make_peer_go_out_of_range(void)
+{
+ hw_radio_testcheat_set_tx_power_gain(-300);
+ hw_radio_testcheat_set_rx_power_gain(-300);
+}
+
+static void make_peer_go_back_in_range(void)
+{
+ hw_radio_testcheat_set_tx_power_gain(+300);
+ hw_radio_testcheat_set_rx_power_gain(+300);
+}
+
+void indicated_cb(struct bt_conn *conn, struct bt_gatt_indicate_params *params, uint8_t err)
+{
+ SET_FLAG(indicated);
+}
+
+static void params_struct_freed_cb(struct bt_gatt_indicate_params *params)
+{
+ k_free(params);
+}
+
+static int send_indication(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *data,
+ uint16_t len)
+{
+ struct bt_gatt_indicate_params *params = k_malloc(sizeof(struct bt_gatt_indicate_params));
+
+ params->attr = attr;
+ params->func = indicated_cb;
+ params->destroy = params_struct_freed_cb;
+ params->data = data;
+ params->len = len;
+
+ return bt_gatt_indicate(conn, params);
+}
+
+static const uint8_t notification_data[GATT_PAYLOAD_SIZE];
+
+static void test_iteration(bt_addr_le_t *peer)
+{
+ int err;
+ struct bt_conn *conn = NULL;
+ const struct bt_gatt_attr *attr;
+
+ /* Create a connection using that address */
+ err = bt_testlib_connect(peer, &conn);
+ TEST_ASSERT(!err, "Failed to initiate connection (err %d)", err);
+
+ LOG_DBG("Connected");
+
+ LOG_INF("Wait until peer subscribes");
+ UNSET_FLAG(is_subscribed);
+ WAIT_FOR_FLAG(is_subscribed);
+
+ /* Prepare data for notifications
+ * attrs[0] is our service declaration
+ * attrs[1] is our characteristic declaration
+ * attrs[2] is our characteristic value
+ *
+ * We store a pointer for the characteristic value as that is the
+ * value we want to notify later.
+ *
+ * We could alternatively use `bt_gatt_notify_uuid()`.
+ */
+ attr = &test_gatt_service.attrs[2];
+
+ exchange_mtu(conn);
+
+ slow_down_conn(conn);
+ LOG_DBG("Updated params");
+
+ LOG_INF("Send indication #1");
+ UNSET_FLAG(indicated);
+ err = send_indication(conn, attr, notification_data, sizeof(notification_data));
+ TEST_ASSERT(!err, "Failed to send notification: err %d", err);
+ LOG_DBG("Wait until peer confirms our first indication");
+ WAIT_FOR_FLAG(indicated);
+
+ LOG_INF("Send indication #2");
+ UNSET_FLAG(indicated);
+ err = send_indication(conn, attr, notification_data, sizeof(notification_data));
+ TEST_ASSERT(!err, "Failed to send notification: err %d", err);
+
+ LOG_DBG("Simulate RF connection loss");
+ UNSET_FLAG(conn_recycled);
+ make_peer_go_out_of_range();
+
+ /* We will not access conn after this: give back our initial ref. */
+ bt_testlib_conn_unref(&conn);
+ WAIT_FOR_FLAG(conn_recycled);
+
+ LOG_DBG("Connection object has been destroyed as expected");
+ make_peer_go_back_in_range();
+}
+
+void entrypoint_dut(void)
+{
+ /* Test purpose:
+ *
+ * Verifies that we don't leak resources or mess up host state when a
+ * disconnection happens whilst the host is transmitting ACL fragments.
+ *
+ * To achieve that, we use the BabbleSim magic modem (see run.sh) to cut
+ * the RF link before we have sent all the ACL fragments the peer. We do
+ * want to send multiple fragments to the controller though, the
+ * important part is that the peer does not acknowledge them, so that
+ * the disconnection happens while the controller has its TX buffers
+ * full.
+ *
+ * Two devices:
+ * - `dut`: the device whose host we are testing
+ * - `peer`: anime side-character. not important.
+ *
+ * Procedure (for n iterations):
+ * - [dut] establish connection to `peer`
+ * - [peer] discover GATT and subscribe to the test characteristic
+ * - [dut] send long indication
+ * - [peer] wait for confirmation of indication
+ * - [dut] send another long indication
+ * - [dut] disconnect
+ *
+ * [verdict]
+ * - All test cycles complete
+ */
+ int err;
+ bt_addr_le_t peer = {};
+
+ /* Mark test as in progress. */
+ TEST_START("dut");
+
+ /* Set the log level given by the `log_level` CLI argument */
+ bt_testlib_log_level_set("dut", runtime_log_level);
+
+ /* Initialize Bluetooth */
+ bt_conn_cb_register(&conn_cbs);
+ err = bt_enable(NULL);
+ TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err);
+
+ LOG_DBG("Bluetooth initialized");
+
+ /* Find the address of the peer. In our case, both devices are actually
+ * the same executable (with the same config) but executed with
+ * different arguments. We can then just use CONFIG_BT_DEVICE_NAME which
+ * contains our device name in string form.
+ */
+ err = bt_testlib_scan_find_name(&peer, CONFIG_BT_DEVICE_NAME);
+ TEST_ASSERT(!err, "Failed to start scan (err %d)", err);
+
+ for (int i = 0; i < TEST_ITERATIONS; i++) {
+ LOG_INF("## Iteration %d", i);
+ test_iteration(&peer);
+ }
+
+ TEST_PASS("dut");
+}
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/main.c b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/main.c
new file mode 100644
index 0000000..9afd99d
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/main.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include "bs_tracing.h"
+#include "bstests.h"
+#include "babblekit/testcase.h"
+#include "testlib/log_utils.h"
+
+extern void entrypoint_dut(void);
+extern void entrypoint_peer(void);
+extern enum bst_result_t bst_result;
+
+unsigned long runtime_log_level = LOG_LEVEL_INF;
+
+static void test_args(int argc, char *argv[])
+{
+ size_t argn = 0;
+ const char *arg = argv[argn];
+
+ if (strcmp(arg, "log_level") == 0) {
+
+ runtime_log_level = strtoul(argv[++argn], NULL, 10);
+
+ if (runtime_log_level >= LOG_LEVEL_NONE && runtime_log_level <= LOG_LEVEL_DBG) {
+ TEST_PRINT("Runtime log level configuration: %d", runtime_log_level);
+ } else {
+ TEST_FAIL("Invalid arguments to set log level: %d", runtime_log_level);
+ }
+ } else {
+ TEST_PRINT("Default runtime log level configuration: INFO");
+ }
+}
+
+static void test_end_cb(void)
+{
+ if (bst_result != Passed) {
+ TEST_FAIL("Test has not passed.");
+ }
+}
+
+static const struct bst_test_instance entrypoints[] = {
+ {
+ .test_id = "dut",
+ .test_delete_f = test_end_cb,
+ .test_main_f = entrypoint_dut,
+ .test_args_f = test_args,
+ },
+ {
+ .test_id = "peer",
+ .test_delete_f = test_end_cb,
+ .test_main_f = entrypoint_peer,
+ .test_args_f = test_args,
+ },
+ BSTEST_END_MARKER,
+};
+
+static struct bst_test_list *install(struct bst_test_list *tests)
+{
+ return bst_add_tests(tests, entrypoints);
+};
+
+bst_test_install_t test_installers[] = {install, NULL};
+
+int main(void)
+{
+ bst_main();
+
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/peer.c b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/peer.c
new file mode 100644
index 0000000..7b40d99
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/src/peer.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/logging/log.h>
+
+#include "testlib/adv.h"
+#include "testlib/att_read.h"
+#include "testlib/att_write.h"
+#include "testlib/conn.h"
+#include "testlib/log_utils.h"
+
+#include "babblekit/flags.h"
+#include "babblekit/testcase.h"
+
+/* local includes */
+#include "data.h"
+
+LOG_MODULE_REGISTER(peer, LOG_LEVEL_DBG);
+
+static DEFINE_FLAG(is_subscribed);
+static DEFINE_FLAG(got_notification_1);
+
+extern unsigned long runtime_log_level;
+
+int find_characteristic(struct bt_conn *conn, const struct bt_uuid *svc, const struct bt_uuid *chrc,
+ uint16_t *chrc_value_handle)
+{
+ uint16_t svc_handle;
+ uint16_t svc_end_handle;
+ uint16_t chrc_end_handle;
+ int err;
+
+ LOG_DBG("");
+
+ err = bt_testlib_gatt_discover_primary(&svc_handle, &svc_end_handle, conn, svc,
+ BT_ATT_FIRST_ATTRIBUTE_HANDLE,
+ BT_ATT_LAST_ATTRIBUTE_HANDLE);
+ if (err != 0) {
+ LOG_ERR("Failed to discover service: %d", err);
+
+ return err;
+ }
+
+ LOG_DBG("svc_handle: %u, svc_end_handle: %u", svc_handle, svc_end_handle);
+
+ err = bt_testlib_gatt_discover_characteristic(chrc_value_handle, &chrc_end_handle, NULL,
+ conn, chrc, (svc_handle + 1), svc_end_handle);
+ if (err != 0) {
+ LOG_ERR("Failed to get value handle: %d", err);
+
+ return err;
+ }
+
+ LOG_DBG("chrc_value_handle: %u, chrc_end_handle: %u", *chrc_value_handle, chrc_end_handle);
+
+ return err;
+}
+
+static uint8_t received_notification(struct bt_conn *conn, struct bt_gatt_subscribe_params *params,
+ const void *data, uint16_t length)
+{
+ if (length) {
+ LOG_INF("RX notification");
+ LOG_HEXDUMP_DBG(data, length, "payload");
+ SET_FLAG(got_notification_1);
+
+ TEST_ASSERT(length == GATT_PAYLOAD_SIZE, "Unexpected length: %d", length);
+ }
+
+ return BT_GATT_ITER_CONTINUE;
+}
+
+static void sub_cb(struct bt_conn *conn, uint8_t err, struct bt_gatt_subscribe_params *params)
+{
+ TEST_ASSERT(!err, "Subscribe failed (err %d)", err);
+
+ TEST_ASSERT(params, "params is NULL");
+ TEST_ASSERT(params->value, "Host shouldn't know we have unsubscribed");
+
+ LOG_DBG("Subscribed to handle 0x%04x", params->value_handle);
+ SET_FLAG(is_subscribed);
+}
+
+/* Subscription parameters have the same lifetime as a subscription.
+ * That is the backing struct should stay valid until a call to
+ * `bt_gatt_unsubscribe()` is made. Hence the `static`.
+ */
+static struct bt_gatt_subscribe_params sub_params;
+
+/* This is "working memory" used by the `CONFIG_BT_GATT_AUTO_DISCOVER_CCC`
+ * feature. It also has to stay valid until the end of the async call.
+ */
+static struct bt_gatt_discover_params ccc_disc_params;
+
+static void subscribe(struct bt_conn *conn, uint16_t handle, bt_gatt_notify_func_t cb)
+{
+ int err;
+
+ /* Subscribe to notifications */
+ sub_params.notify = cb;
+ sub_params.subscribe = sub_cb;
+ sub_params.value = BT_GATT_CCC_INDICATE;
+ sub_params.value_handle = handle;
+
+ /* Set-up auto-discovery of the CCC handle */
+ sub_params.ccc_handle = 0;
+ sub_params.disc_params = &ccc_disc_params;
+ sub_params.end_handle = BT_ATT_LAST_ATTRIBUTE_HANDLE;
+
+ err = bt_gatt_subscribe(conn, &sub_params);
+ TEST_ASSERT(!err, "Subscribe failed (err %d)", err);
+
+ WAIT_FOR_FLAG(is_subscribed);
+}
+
+static uint16_t g_handle;
+
+static void test_iteration(void)
+{
+ struct bt_conn *conn;
+ int err;
+
+ err = bt_testlib_adv_conn(&conn, BT_ID_DEFAULT, bt_get_name());
+ TEST_ASSERT(!err, "Failed to start connectable advertising (err %d)", err);
+
+ if (g_handle) {
+ LOG_DBG("Re-use cached characteristic");
+ } else {
+ LOG_DBG("Discover test characteristic");
+ err = find_characteristic(conn, test_service_uuid, test_characteristic_uuid,
+ &g_handle);
+ TEST_ASSERT(!err, "Failed to find characteristic: %d", err);
+ }
+
+ LOG_DBG("Subscribe to test characteristic: handle 0x%04x", g_handle);
+ subscribe(conn, g_handle, received_notification);
+
+ WAIT_FOR_FLAG(got_notification_1);
+
+ bt_testlib_wait_disconnected(conn);
+ bt_testlib_conn_unref(&conn);
+}
+
+/* Read the comments on `entrypoint_dut()` first. */
+void entrypoint_peer(void)
+{
+ int err;
+
+ /* Mark test as in progress. */
+ TEST_START("peer");
+
+ /* Set the log level given by the `log_level` CLI argument */
+ bt_testlib_log_level_set("peer", runtime_log_level);
+
+ /* Initialize Bluetooth */
+ err = bt_enable(NULL);
+ TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err);
+
+ LOG_DBG("Bluetooth initialized");
+
+ for (int i = 0; i < TEST_ITERATIONS; i++) {
+ LOG_INF("## Iteration %d", i);
+ test_iteration();
+ }
+
+ TEST_PASS_AND_EXIT("peer");
+}
diff --git a/tests/bsim/bluetooth/host/misc/acl_tx_frag/test_scripts/run.sh b/tests/bsim/bluetooth/host/misc/acl_tx_frag/test_scripts/run.sh
new file mode 100755
index 0000000..91eee9a
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/acl_tx_frag/test_scripts/run.sh
@@ -0,0 +1,29 @@
+#!/usr/bin/env bash
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+set -eu
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+test_name="$(guess_test_long_name)"
+simulation_id=${test_name}
+verbosity_level=2
+
+# sixty-second (maximum) sim time.
+# The test will exit simulation as soon as it has passed.
+SIM_LEN_US=$((60 * 1000 * 1000))
+
+test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_${test_name}_prj_conf"
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute "${test_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -rs=420 -testid=dut \
+ -argstest log_level 3
+Execute "${test_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -rs=69 -testid=peer \
+ -argstest log_level 3 >/dev/null
+
+Execute ./bs_2G4_phy_v1 -defmodem=BLE_simple \
+ -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=${SIM_LEN_US} $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/disconnect/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/misc/disconnect/compile.sh
diff --git a/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c b/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
index 4755a55..ebe1224 100644
--- a/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
@@ -341,7 +341,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/hfc/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/misc/hfc/compile.sh
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/hfc_multilink/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/misc/hfc_multilink/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/misc/hfc_multilink/compile.sh
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
index fc915bb..370f6fb 100644
--- a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
@@ -355,7 +355,7 @@
struct net_buf *buf;
/* Wait until a buffer is available */
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
recv(buf);
}
}
diff --git a/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/sample_test/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/misc/sample_test/compile.sh
diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/central/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/privacy/central/compile.sh
diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/device/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/privacy/device/compile.sh
diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/legacy/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/privacy/legacy/compile.sh
diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/peripheral/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/privacy/peripheral/compile.sh
diff --git a/tests/bsim/bluetooth/host/scan/start_stop/CMakeLists.txt b/tests/bsim/bluetooth/host/scan/start_stop/CMakeLists.txt
new file mode 100644
index 0000000..c15553e
--- /dev/null
+++ b/tests/bsim/bluetooth/host/scan/start_stop/CMakeLists.txt
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr HINTS $ENV{ZEPHYR_BASE})
+project(bsim_test_scan_start_stop)
+
+target_sources(app PRIVATE
+ src/main.c
+)
+
+# This contains babblesim-specific helpers, e.g. device synchronization.
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+zephyr_include_directories(
+ $ENV{BSIM_COMPONENTS_PATH}/libUtilv1/src/
+ $ENV{BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+)
diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/scan/start_stop/compile.sh
similarity index 100%
copy from tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh
copy to tests/bsim/bluetooth/host/scan/start_stop/compile.sh
diff --git a/tests/bsim/bluetooth/host/scan/start_stop/prj.conf b/tests/bsim/bluetooth/host/scan/start_stop/prj.conf
new file mode 100644
index 0000000..48b458f
--- /dev/null
+++ b/tests/bsim/bluetooth/host/scan/start_stop/prj.conf
@@ -0,0 +1,13 @@
+CONFIG_BT=y
+CONFIG_BT_BROADCASTER=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_OBSERVER=y
+CONFIG_BT_EXT_ADV=y
+CONFIG_BT_PER_ADV_SYNC=y
+CONFIG_BT_PER_ADV=y
+CONFIG_BT_DEVICE_NAME="Scanner Test"
+CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL=y
+CONFIG_BT_PRIVACY=n
+
+CONFIG_LOG=y
+CONFIG_ASSERT=y
diff --git a/tests/bsim/bluetooth/host/scan/start_stop/src/main.c b/tests/bsim/bluetooth/host/scan/start_stop/src/main.c
new file mode 100644
index 0000000..b266d88
--- /dev/null
+++ b/tests/bsim/bluetooth/host/scan/start_stop/src/main.c
@@ -0,0 +1,268 @@
+/* Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/irq.h>
+#include <string.h>
+
+#include <zephyr/logging/log.h>
+#include <zephyr/settings/settings.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/atomic_builtin.h>
+#include <babblekit/testcase.h>
+#include <babblekit/sync.h>
+#include <babblekit/flags.h>
+
+LOG_MODULE_REGISTER(bt_bsim_scan_start_stop, LOG_LEVEL_DBG);
+
+#define WAIT_TIME_S 60
+#define WAIT_TIME (WAIT_TIME_S * 1e6)
+
+static atomic_t flag_adv_report_received;
+static atomic_t flag_periodic_sync_established;
+static bt_addr_le_t adv_addr;
+
+static void test_tick(bs_time_t HW_device_time)
+{
+ if (bst_result != Passed) {
+ TEST_FAIL("Test failed (not passed after %d seconds)\n", WAIT_TIME_S);
+ }
+}
+
+static void test_init(void)
+{
+ bst_ticker_set_next_tick_absolute(WAIT_TIME);
+}
+
+static void bt_sync_established_cb(struct bt_le_per_adv_sync *sync,
+ struct bt_le_per_adv_sync_synced_info *info)
+{
+ LOG_DBG("Periodic sync established");
+ atomic_set(&flag_periodic_sync_established, true);
+}
+
+static struct bt_le_per_adv_sync_cb sync_callbacks = {
+ .synced = bt_sync_established_cb,
+};
+
+static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type,
+ struct net_buf_simple *ad)
+{
+ char addr_str[BT_ADDR_LE_STR_LEN];
+
+ memcpy(&adv_addr, addr, sizeof(adv_addr));
+
+ bt_addr_le_to_str(&adv_addr, addr_str, sizeof(addr_str));
+ LOG_DBG("Device found: %s (RSSI %d), type %u, AD data len %u",
+ addr_str, rssi, type, ad->len);
+ atomic_set(&flag_adv_report_received, true);
+}
+
+void run_dut(void)
+{
+ /* Test purpose:
+ *
+ * Verifies that the scanner can establish a sync to a device when
+ * it is explicitly enabled and disabled. Disabling the scanner
+ * explicitly should not stop the implicitly started scanner.
+ * Verify that the explicit scanner can be started when the
+ * implicit scanner is already running.
+ *
+ * Two devices:
+ * - `dut`: tries to establish the sync
+ * - `peer`: runs an advertiser / periodic advertiser
+ *
+ * Procedure:
+ * - [dut] start establishing a sync (no peer)
+ * - [peer] starts advertising
+ * - [dut] starts explicit scanning
+ * - [dut] wait for the peer to be found
+ * - [dut] stops explicit scanning
+ * - [dut] stop the periodic sync
+ * - [dut] start establishing a sync to the peer
+ * - [dut] start and stop explicit scanning
+ * - [peer] start periodic advertiser
+ * - [dut] wait until a sync is established
+ *
+ * [verdict]
+ * - dut is able to sync to the peer.
+ */
+
+ LOG_DBG("start");
+ bk_sync_init();
+ int err;
+
+ LOG_DBG("Starting DUT");
+
+ err = bt_enable(NULL);
+ TEST_ASSERT(!err, "Bluetooth init failed (err %d)\n", err);
+
+ LOG_DBG("Bluetooth initialised");
+
+ /* Try to establish a sync to a periodic advertiser.
+ * This will start the scanner.
+ */
+ memset(&adv_addr, 0x00, sizeof(adv_addr));
+ struct bt_le_per_adv_sync_param per_sync_param = {
+ .addr = adv_addr,
+ .options = 0x0,
+ .sid = 0x0,
+ .skip = 0x0,
+ .timeout = BT_GAP_PER_ADV_MAX_TIMEOUT,
+ };
+ struct bt_le_per_adv_sync *p_per_sync;
+
+ bt_le_per_adv_sync_cb_register(&sync_callbacks);
+
+ err = bt_le_per_adv_sync_create(&per_sync_param, &p_per_sync);
+ TEST_ASSERT(!err, "Periodic sync setup failed (err %d)\n", err);
+ LOG_DBG("Periodic sync started");
+
+ /* Start scanner. Check that we can start the scanner while it is already
+ * running due to the periodic sync.
+ */
+ struct bt_le_scan_param scan_params = {
+ .type = BT_LE_SCAN_TYPE_ACTIVE,
+ .options = 0x0,
+ .interval = 123,
+ .window = 12,
+ .interval_coded = 222,
+ .window_coded = 32,
+ };
+
+ err = bt_le_scan_start(&scan_params, device_found);
+ TEST_ASSERT(!err, "Scanner setup failed (err %d)\n", err);
+ LOG_DBG("Explicit scanner started");
+
+ LOG_DBG("Wait for an advertising report");
+ WAIT_FOR_FLAG(flag_adv_report_received);
+
+ /* Stop the scanner. That should not affect the periodic advertising sync. */
+ err = bt_le_scan_stop();
+ TEST_ASSERT(!err, "Scanner stop failed (err %d)\n", err);
+ LOG_DBG("Explicit scanner stopped");
+
+ /* We should be able to stop the periodic advertising sync. */
+ err = bt_le_per_adv_sync_delete(p_per_sync);
+ TEST_ASSERT(!err, "Periodic sync stop failed (err %d)\n", err);
+ LOG_DBG("Periodic sync stopped");
+
+ /* Start the periodic advertising sync. This time, provide the address of the advertiser
+ * which it should connect to.
+ */
+ per_sync_param = (struct bt_le_per_adv_sync_param) {
+ .addr = adv_addr,
+ .options = 0x0,
+ .sid = 0x0,
+ .skip = 0x0,
+ .timeout = BT_GAP_PER_ADV_MAX_TIMEOUT
+ };
+ err = bt_le_per_adv_sync_create(&per_sync_param, &p_per_sync);
+ TEST_ASSERT(!err, "Periodic sync setup failed (err %d)\n", err);
+ LOG_DBG("Periodic sync started");
+
+ /* Start the explicit scanner */
+ err = bt_le_scan_start(&scan_params, device_found);
+ TEST_ASSERT(!err, "Scanner setup failed (err %d)\n", err);
+ LOG_DBG("Explicit scanner started");
+
+ /* Stop the explicit scanner. This should not stop scanner, since we still try to establish
+ * a sync.
+ */
+ err = bt_le_scan_stop();
+ TEST_ASSERT(!err, "Scanner stop failed (err %d)\n", err);
+ LOG_DBG("Explicit scanner stopped");
+
+ /* Signal to the tester to start the periodic adv. */
+ bk_sync_send();
+
+ /* Validate that we can still establish a sync */
+ LOG_DBG("Wait for sync to periodic adv");
+ WAIT_FOR_FLAG(flag_periodic_sync_established);
+
+ /* Signal to the tester to end the test. */
+ bk_sync_send();
+
+ TEST_PASS("Test passed (DUT)\n");
+}
+
+void run_tester(void)
+{
+ LOG_DBG("start");
+ bk_sync_init();
+
+ int err;
+
+ LOG_DBG("Starting DUT");
+
+ err = bt_enable(NULL);
+ TEST_ASSERT(!err, "Bluetooth init failed (err %d)\n", err);
+
+ LOG_DBG("Bluetooth initialised");
+
+ struct bt_le_ext_adv *per_adv;
+
+ struct bt_le_adv_param adv_param = BT_LE_ADV_PARAM_INIT(BT_LE_ADV_OPT_EXT_ADV,
+ BT_GAP_ADV_FAST_INT_MIN_2,
+ BT_GAP_ADV_FAST_INT_MAX_2,
+ NULL);
+
+ err = bt_le_ext_adv_create(&adv_param, NULL, &per_adv);
+ TEST_ASSERT(!err, "Failed to create advertising set: %d", err);
+ LOG_DBG("Created extended advertising set.");
+
+ err = bt_le_ext_adv_start(per_adv, BT_LE_EXT_ADV_START_DEFAULT);
+ TEST_ASSERT(!err, "Failed to start extended advertising: %d", err);
+ LOG_DBG("Started extended advertising.");
+
+ /* Wait for the DUT before starting the periodic advertising */
+ bk_sync_wait();
+ err = bt_le_per_adv_set_param(per_adv, BT_LE_PER_ADV_DEFAULT);
+ TEST_ASSERT(!err, "Failed to set periodic advertising parameters: %d", err);
+ LOG_DBG("Periodic advertising parameters set.");
+
+ err = bt_le_per_adv_start(per_adv);
+ TEST_ASSERT(!err, "Failed to start periodic advertising: %d", err);
+ LOG_DBG("Periodic advertising started.");
+
+ /* Wait for the signal from the DUT before finishing the test */
+ bk_sync_wait();
+
+ bt_le_per_adv_stop(per_adv);
+
+ TEST_PASS("Test passed (Tester)\n");
+}
+
+static const struct bst_test_instance test_def[] = {
+ {
+ .test_id = "scanner",
+ .test_descr = "SCANNER",
+ .test_post_init_f = test_init,
+ .test_tick_f = test_tick,
+ .test_main_f = run_dut,
+ },
+ {
+ .test_id = "periodic_adv",
+ .test_descr = "PER_ADV",
+ .test_post_init_f = test_init,
+ .test_tick_f = test_tick,
+ .test_main_f = run_tester,
+ },
+ BSTEST_END_MARKER
+};
+
+struct bst_test_list *test_scan_start_stop_install(struct bst_test_list *tests)
+{
+ return bst_add_tests(tests, test_def);
+}
+
+bst_test_install_t test_installers[] = {test_scan_start_stop_install, NULL};
+
+int main(void)
+{
+ bst_main();
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/host/scan/start_stop/test_scripts/start_stop.sh b/tests/bsim/bluetooth/host/scan/start_stop/test_scripts/start_stop.sh
new file mode 100755
index 0000000..2e172fd
--- /dev/null
+++ b/tests/bsim/bluetooth/host/scan/start_stop/test_scripts/start_stop.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_scan_start_stop_prj_conf"
+simulation_id="start_stop"
+verbosity_level=2
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute "./${test_exe}" \
+ -v=${verbosity_level} -s="${simulation_id}" -d=0 -testid=scanner
+
+Execute "./${test_exe}" \
+ -v=${verbosity_level} -s="${simulation_id}" -d=1 -testid=periodic_adv
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}" \
+ -D=2 -sim_length=5e6
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/bond_overwrite_allowed/compile.sh
diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/bond_overwrite_denied/compile.sh
diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/bond_per_connection/compile.sh
diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/ccc_update/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/ccc_update/compile.sh
diff --git a/tests/bsim/bluetooth/host/security/compile.sh b/tests/bsim/bluetooth/host/security/compile.sh
index 9296cd8..e837aec 100755
--- a/tests/bsim/bluetooth/host/security/compile.sh
+++ b/tests/bsim/bluetooth/host/security/compile.sh
@@ -10,13 +10,13 @@
source ${ZEPHYR_BASE}/tests/bsim/compile.source
-app=tests/bsim/bluetooth/host/security/bond_overwrite_allowed compile
-app=tests/bsim/bluetooth/host/security/bond_overwrite_denied compile
-app=tests/bsim/bluetooth/host/security/bond_per_connection compile
-app=tests/bsim/bluetooth/host/security/ccc_update compile
-app=tests/bsim/bluetooth/host/security/ccc_update conf_file=prj_2.conf compile
-app=tests/bsim/bluetooth/host/security/id_addr_update/central compile
-app=tests/bsim/bluetooth/host/security/id_addr_update/peripheral compile
-app=tests/bsim/bluetooth/host/security/security_changed_callback compile
+run_in_background \
+ ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/bond_overwrite_denied/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/bond_per_connection/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/ccc_update/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/id_addr_update/compile.sh
+run_in_background \
+ ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/security/security_changed_callback/compile.sh
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/id_addr_update/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/id_addr_update/compile.sh
diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/security_changed_callback/compile.sh
similarity index 100%
rename from tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh
rename to tests/bsim/bluetooth/host/security/security_changed_callback/compile.sh
diff --git a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_1.c b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_1.c
index f742061..d9bbb46 100644
--- a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_1.c
+++ b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_1.c
@@ -127,8 +127,9 @@
*/
void service_b_3_1_value_v6_notify(void)
{
- if (!value_v6_ntf_active)
+ if (!value_v6_ntf_active) {
return;
+ }
bt_gatt_notify(NULL, &service_b_3_1_attrs[1], &value_v6_value,
sizeof(value_v6_value));
diff --git a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_2.c b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_2.c
index 95020b8..1a57ff7 100644
--- a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_2.c
+++ b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_2.c
@@ -131,8 +131,9 @@
*/
void service_b_3_2_value_v6_notify(void)
{
- if (!value_v6_ntf_active)
+ if (!value_v6_ntf_active) {
return;
+ }
bt_gatt_notify(NULL, &service_b_3_2_attrs[1], &value_v6_value,
sizeof(value_v6_value));
@@ -160,8 +161,9 @@
*/
void service_b_3_2_value_v6_indicate(void)
{
- if (!value_v6_ind_active)
+ if (!value_v6_ind_active) {
return;
+ }
/*
* NOTE: Zephyr doesn't automatically bump up the attribute pointer for
* indications as it does for notifications.
diff --git a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_3.c b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_3.c
index 3a8fe5b..534a73b 100644
--- a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_3.c
+++ b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/service_b_3_3.c
@@ -131,8 +131,9 @@
*/
void service_b_3_3_value_v6_notify(void)
{
- if (!value_v6_ntf_active)
+ if (!value_v6_ntf_active) {
return;
+ }
bt_gatt_notify(NULL, &service_b_3_3_attrs[1], &value_v6_value,
sizeof(value_v6_value));
@@ -160,8 +161,9 @@
*/
void service_b_3_3_value_v6_indicate(void)
{
- if (!value_v6_ind_active)
+ if (!value_v6_ind_active) {
return;
+ }
/*
* NOTE: Zephyr doesn't automatically bump up the attribute pointer for
* indications as it does for notifications.
diff --git a/tests/bsim/bluetooth/ll/edtt/hci_test_app/src/main.c b/tests/bsim/bluetooth/ll/edtt/hci_test_app/src/main.c
index 50c4146..84ff767c 100644
--- a/tests/bsim/bluetooth/ll/edtt/hci_test_app/src/main.c
+++ b/tests/bsim/bluetooth/ll/edtt/hci_test_app/src/main.c
@@ -274,7 +274,7 @@
*/
static void discard_event(void)
{
- struct net_buf *buf = net_buf_get(&event_queue, K_FOREVER);
+ struct net_buf *buf = k_fifo_get(&event_queue, K_FOREVER);
net_buf_unref(buf);
m_events--;
@@ -292,7 +292,7 @@
bt_buf_set_type(evt, BT_BUF_EVT);
net_buf_add_le32(evt, sys_cpu_to_le32(k_uptime_get()));
net_buf_add_mem(evt, buf->data, buf->len);
- net_buf_put(&event_queue, evt);
+ k_fifo_put(&event_queue, evt);
m_events++;
}
return evt;
@@ -306,7 +306,7 @@
struct net_buf *buf, *evt;
while (1) {
- buf = net_buf_get(&rx_queue, K_FOREVER);
+ buf = k_fifo_get(&rx_queue, K_FOREVER);
if (bt_buf_get_type(buf) == BT_BUF_EVT) {
evt = queue_event(buf);
@@ -348,7 +348,7 @@
net_buf_add_le32(data,
sys_cpu_to_le32(k_uptime_get()));
net_buf_add_mem(data, buf->data, buf->len);
- net_buf_put(&data_queue, data);
+ k_fifo_put(&data_queue, data);
}
#if defined(CONFIG_BT_ISO)
} else if (bt_buf_get_type(buf) == BT_BUF_ISO_IN) {
@@ -360,7 +360,7 @@
net_buf_add_le32(data,
sys_cpu_to_le32(k_uptime_get()));
net_buf_add_mem(data, buf->data, buf->len);
- net_buf_put(&iso_data_queue, data);
+ k_fifo_put(&iso_data_queue, data);
}
#endif /* CONFIG_BT_ISO */
}
@@ -378,7 +378,7 @@
uint16_t response = sys_cpu_to_le16(CMD_FLUSH_EVENTS_RSP);
struct net_buf *buf;
- while ((buf = net_buf_get(&event_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&event_queue, K_NO_WAIT))) {
net_buf_unref(buf);
m_events--;
}
@@ -401,7 +401,7 @@
size = 0;
edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
- buf = net_buf_get(&event_queue, K_FOREVER);
+ buf = k_fifo_get(&event_queue, K_FOREVER);
if (buf) {
size = sys_cpu_to_le16(buf->len);
edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
@@ -428,7 +428,7 @@
edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
edtt_write((uint8_t *)&count, sizeof(count), EDTTT_BLOCK);
while (count--) {
- buf = net_buf_get(&event_queue, K_FOREVER);
+ buf = k_fifo_get(&event_queue, K_FOREVER);
size = sys_cpu_to_le16(buf->len);
edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
edtt_write((uint8_t *)buf->data, buf->len, EDTTT_BLOCK);
@@ -467,7 +467,7 @@
uint16_t response = sys_cpu_to_le16(CMD_LE_FLUSH_DATA_RSP);
struct net_buf *buf;
- while ((buf = net_buf_get(&data_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&data_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
read_excess_bytes(size);
@@ -514,7 +514,7 @@
size = 0;
edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
- buf = net_buf_get(&data_queue, K_FOREVER);
+ buf = k_fifo_get(&data_queue, K_FOREVER);
if (buf) {
size = sys_cpu_to_le16(buf->len);
edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
@@ -584,7 +584,7 @@
uint16_t response = sys_cpu_to_le16(CMD_LE_FLUSH_ISO_DATA_RSP);
struct net_buf *buf;
- while ((buf = net_buf_get(&iso_data_queue, K_NO_WAIT))) {
+ while ((buf = k_fifo_get(&iso_data_queue, K_NO_WAIT))) {
net_buf_unref(buf);
}
read_excess_bytes(size);
@@ -631,7 +631,7 @@
size = 0;
edtt_write((uint8_t *)&response, sizeof(response), EDTTT_BLOCK);
- buf = net_buf_get(&iso_data_queue, K_FOREVER);
+ buf = k_fifo_get(&iso_data_queue, K_FOREVER);
if (buf) {
size = sys_cpu_to_le16(buf->len);
edtt_write((uint8_t *)&size, sizeof(size), EDTTT_BLOCK);
diff --git a/tests/bsim/bluetooth/samples/battery_service/CMakeLists.txt b/tests/bsim/bluetooth/samples/battery_service/CMakeLists.txt
new file mode 100644
index 0000000..d5eda77
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/CMakeLists.txt
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(battery_service_test)
+
+target_sources(app PRIVATE
+ src/main.c
+ src/central_test.c
+ src/peripheral_test.c
+)
+
+# This contains a variety of helper functions that abstract away common tasks,
+# like scanning, setting up a connection, querying the peer for a given
+# characteristic, etc..
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib)
+target_link_libraries(app PRIVATE testlib)
+
+# This contains babblesim-specific helpers, e.g. device synchronization.
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth)
+
+zephyr_include_directories(
+ ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+ ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+)
diff --git a/tests/bsim/bluetooth/samples/battery_service/prj.conf b/tests/bsim/bluetooth/samples/battery_service/prj.conf
new file mode 100644
index 0000000..e1c9de0
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/prj.conf
@@ -0,0 +1,14 @@
+CONFIG_BT=y
+CONFIG_LOG=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_SMP=y
+CONFIG_BT_BAS=y
+CONFIG_BT_GATT_CLIENT=y
+CONFIG_BT_DEVICE_NAME="bsim_bas"
+CONFIG_BT_ATT_TX_COUNT=5
+
+CONFIG_BT_BAS_BLS=y
+CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT=y
+CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT=y
+CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT=y
diff --git a/tests/bsim/bluetooth/samples/battery_service/src/central_test.c b/tests/bsim/bluetooth/samples/battery_service/src/central_test.c
new file mode 100644
index 0000000..f527a3a
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/src/central_test.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright (c) 2024 Demant A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include "bs_types.h"
+#include "bs_tracing.h"
+#include "time_machine.h"
+#include "bstests.h"
+#include <argparse.h>
+
+#include <zephyr/types.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include <zephyr/bluetooth/services/bas.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/sys/byteorder.h>
+
+#include "testlib/conn.h"
+#include "testlib/scan.h"
+#include "testlib/log_utils.h"
+
+#include "babblekit/flags.h"
+#include "babblekit/sync.h"
+#include "babblekit/testcase.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bt_bsim_bas, CONFIG_BT_BAS_LOG_LEVEL);
+
+static struct bt_conn *default_conn;
+static bt_addr_le_t peer = {};
+
+static struct bt_uuid_16 uuid = BT_UUID_INIT_16(0);
+static struct bt_gatt_discover_params discover_params;
+
+static struct bt_gatt_subscribe_params battery_level_notify_params;
+static struct bt_gatt_subscribe_params battery_level_status_sub_params;
+
+/*
+ * Battery Service test:
+ * We expect to find a connectable peripheral to which we will
+ * connect and discover Battery Service
+ *
+ * Test the Read/Notify/Indicate Characteristics of BAS
+ */
+
+#define WAIT_TIME 10 /*seconds*/
+#define BAS_BLS_IND_RECEIVED_COUNT 20
+#define BAS_BLS_NTF_RECEIVED_COUNT 20
+
+static DEFINE_FLAG(notification_count_reached);
+static DEFINE_FLAG(indication_count_reached);
+
+extern enum bst_result_t bst_result;
+
+static void test_bas_central_init(void)
+{
+ bst_ticker_set_next_tick_absolute(WAIT_TIME * 1e6);
+ bst_result = In_progress;
+}
+
+static void test_bas_central_tick(bs_time_t HW_device_time)
+{
+ /*
+ * If in WAIT_TIME seconds the testcase did not already pass
+ * (and finish) we consider it failed
+ */
+ if (bst_result != Passed) {
+ TEST_FAIL("test_bas_central failed (not passed after %i seconds)\n", WAIT_TIME);
+ }
+}
+
+/* Callback for handling Battery Level Notifications */
+static uint8_t battery_level_notify_cb(struct bt_conn *conn,
+ struct bt_gatt_subscribe_params *params, const void *data,
+ uint16_t length)
+{
+ if (data) {
+ LOG_INF("[NOTIFICATION] BAS Battery Level: %d%%", *(const uint8_t *)data);
+ } else {
+ LOG_INF("Battery Level Notifications disabled");
+ }
+ return BT_GATT_ITER_CONTINUE;
+}
+
+/* Callback for handling Battery Level Read Response */
+static uint8_t battery_level_read_cb(struct bt_conn *conn, uint8_t err,
+ struct bt_gatt_read_params *params, const void *data,
+ uint16_t length)
+{
+ TEST_ASSERT(err == 0, "Failed to read Battery Level (err %d)", err);
+ if (data) {
+ LOG_DBG("[READ] BAS Battery Level: %d%%\n", *(const uint8_t *)data);
+ }
+
+ return BT_GATT_ITER_STOP;
+}
+
+static bool parse_battery_level_status(const uint8_t *data, uint16_t length)
+{
+ /* Check minimum length for parsing flags and power state */
+ if (length < 3) {
+ TEST_FAIL("Invalid data length: %d", length);
+ return false;
+ }
+
+ /* Parse flags (first byte) */
+ uint8_t flags = data[0];
+
+ LOG_INF("Parsed Flags: 0x%02x", flags);
+
+ if (flags & BT_BAS_BLS_FLAG_IDENTIFIER_PRESENT) {
+ LOG_INF(" Identifier Present");
+ } else {
+ LOG_INF(" Identifier Not Present");
+ }
+
+ if (flags & BT_BAS_BLS_FLAG_BATTERY_LEVEL_PRESENT) {
+ LOG_INF(" Battery Level Present");
+ } else {
+ LOG_INF(" Battery Level Not Present");
+ }
+
+ if (flags & BT_BAS_BLS_FLAG_ADDITIONAL_STATUS_PRESENT) {
+ LOG_INF(" Additional Status Present");
+ } else {
+ LOG_INF(" Additional Status Not Present");
+ }
+
+ /* Parse power state (next 2 bytes) */
+ uint16_t power_state = sys_get_le16(&data[1]);
+
+ LOG_INF("Parsed Power State: 0x%04x", power_state);
+ /* Print out each power state value */
+ LOG_INF(" Battery Present: %s", (power_state & BIT(0)) ? "Yes" : "No");
+
+ uint8_t wired_power = (power_state >> 1) & 0x03;
+
+ switch (wired_power) {
+ case 0:
+ LOG_INF(" Wired Power Source: No");
+ break;
+ case 1:
+ LOG_INF(" Wired Power Source: Yes");
+ break;
+ case 2:
+ LOG_INF(" Wired Power Source: Unknown");
+ break;
+ default:
+ LOG_INF(" Wired Power Source: RFU");
+ break;
+ }
+
+ uint8_t wireless_power = (power_state >> 3) & 0x03;
+
+ switch (wireless_power) {
+ case 0:
+ LOG_INF(" Wireless Power Source: No");
+ break;
+ case 1:
+ LOG_INF(" Wireless Power Source: Yes");
+ break;
+ case 2:
+ LOG_INF(" Wireless Power Source: Unknown");
+ break;
+ default:
+ LOG_INF(" Wireless Power Source: RFU");
+ break;
+ }
+
+ uint8_t charge_state = (power_state >> 5) & 0x03;
+
+ switch (charge_state) {
+ case 0:
+ LOG_INF(" Battery Charge State: Unknown");
+ break;
+ case 1:
+ LOG_INF(" Battery Charge State: Charging");
+ break;
+ case 2:
+ LOG_INF(" Battery Charge State: Discharging (Active)");
+ break;
+ case 3:
+ LOG_INF(" Battery Charge State: Discharging (Inactive)");
+ break;
+ }
+
+ uint8_t charge_level = (power_state >> 7) & 0x03;
+
+ switch (charge_level) {
+ case 0:
+ LOG_INF(" Battery Charge Level: Unknown");
+ break;
+ case 1:
+ LOG_INF(" Battery Charge Level: Good");
+ break;
+ case 2:
+ LOG_INF(" Battery Charge Level: Low");
+ break;
+ case 3:
+ LOG_INF(" Battery Charge Level: Critical");
+ break;
+ }
+
+ uint8_t charging_type = (power_state >> 9) & 0x07;
+
+ switch (charging_type) {
+ case 0:
+ LOG_INF(" Charging Type: Unknown or Not Charging");
+ break;
+ case 1:
+ LOG_INF(" Charging Type: Constant Current");
+ break;
+ case 2:
+ LOG_INF(" Charging Type: Constant Voltage");
+ break;
+ case 3:
+ LOG_INF(" Charging Type: Trickle");
+ break;
+ case 4:
+ LOG_INF(" Charging Type: Float");
+ break;
+ default:
+ LOG_INF(" Charging Type: RFU");
+ break;
+ }
+
+ uint8_t charging_fault = (power_state >> 12) & 0x07;
+
+ if (charging_fault) {
+ LOG_INF(" Charging Fault Reason: %s%s%s",
+ (charging_fault & BIT(0)) ? "Battery " : "",
+ (charging_fault & BIT(1)) ? "External Power Source " : "",
+ (charging_fault & BIT(2)) ? "Other " : "");
+ } else {
+ LOG_INF(" Charging Fault Reason: None");
+ }
+
+ /* Optional: Check if identifier is present */
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT)) {
+ /* Check if length is sufficient for identifier */
+ if (length < 5) {
+ TEST_FAIL("Invalid data length for identifier");
+ return false;
+ }
+
+ /* Parse identifier (next 2 bytes) */
+ uint16_t identifier = sys_get_le16(&data[3]);
+
+ LOG_INF("Parsed Identifier: 0x%04x", identifier);
+ }
+
+ /* Optional: Check if battery level is present */
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS_BATTERY_LEVEL_PRESENT)) {
+ /* Check if length is sufficient for battery level */
+ if (length < 6) {
+ TEST_FAIL("Invalid data length for battery level");
+ return false;
+ }
+
+ /* Parse battery level (next byte) */
+ uint8_t battery_level = data[5];
+
+ LOG_INF("Parsed Battery Level: %d%%", battery_level);
+ }
+
+ /* Optional: Check if additional status is present */
+ if (IS_ENABLED(CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT)) {
+ /* Check if length is sufficient for additional status */
+ if (length < 7) {
+ TEST_FAIL("Invalid data length for additional status");
+ return false;
+ }
+
+ /* Parse additional status (next byte) */
+ uint8_t additional_status = data[6];
+
+ LOG_INF("Parsed Additional Status: 0x%02x", additional_status);
+
+ /* Print out additional status values */
+ uint8_t service_required = additional_status & 0x03;
+
+ switch (service_required) {
+ case 0:
+ LOG_INF(" Service Required: False");
+ break;
+ case 1:
+ LOG_INF(" Service Required: True");
+ break;
+ case 2:
+ LOG_INF(" Service Required: Unknown");
+ break;
+ default:
+ LOG_INF(" Service Required: RFU");
+ break;
+ }
+
+ bool battery_fault = (additional_status & BIT(2)) ? true : false;
+
+ LOG_INF(" Battery Fault: %s", battery_fault ? "Yes" : "No");
+ }
+
+ return true;
+}
+
+static unsigned char battery_level_status_indicate_cb(struct bt_conn *conn,
+ struct bt_gatt_subscribe_params *params,
+ const void *data, uint16_t length)
+{
+ if (!data) {
+ LOG_INF("bas level status indication disabled\n");
+ } else {
+ static int ind_received;
+
+ printk("[INDICATION] BAS Battery Level Status: ");
+ for (int i = 0; i < length; i++) {
+ printk("%02x ", ((uint8_t *)data)[i]);
+ }
+ printk("\n");
+
+ if (parse_battery_level_status(data, length)) {
+ LOG_INF("Notification parsed successfully");
+ } else {
+ LOG_ERR("Notification parsing failed");
+ }
+
+ if (ind_received++ > BAS_BLS_IND_RECEIVED_COUNT) {
+ SET_FLAG(indication_count_reached);
+ }
+ }
+ return BT_GATT_ITER_CONTINUE;
+}
+
+static uint8_t battery_level_status_notify_cb(struct bt_conn *conn,
+ struct bt_gatt_subscribe_params *params,
+ const void *data, uint16_t length)
+{
+ if (!data) {
+ LOG_INF("bas level status notification disabled\n");
+ } else {
+ static int notify_count;
+
+ printk("[NOTIFICATION] BAS Battery Level Status: ");
+ for (int i = 0; i < length; i++) {
+ printk("%02x ", ((uint8_t *)data)[i]);
+ }
+ printk("\n");
+
+ if (parse_battery_level_status(data, length)) {
+ LOG_INF("Notification parsed successfully");
+ } else {
+ LOG_ERR("Notification parsing failed");
+ }
+
+ if (notify_count++ > BAS_BLS_NTF_RECEIVED_COUNT) {
+ SET_FLAG(notification_count_reached);
+ }
+ }
+ return BT_GATT_ITER_CONTINUE;
+}
+
+static void read_battery_level(const struct bt_gatt_attr *attr)
+{
+ /* Read the battery level after subscribing */
+ static struct bt_gatt_read_params read_params;
+
+ read_params.func = battery_level_read_cb;
+ read_params.handle_count = 1;
+ read_params.single.handle = bt_gatt_attr_get_handle(attr);
+ read_params.single.offset = 0;
+ bt_gatt_read(default_conn, &read_params);
+}
+
+static void subscribe_battery_level(const struct bt_gatt_attr *attr)
+{
+ int err;
+
+ battery_level_notify_params = (struct bt_gatt_subscribe_params){
+ /* In Zephyr, it is common practice for the CCC handle
+ * to be positioned two handles after the characteristic handle.
+ */
+ .ccc_handle = bt_gatt_attr_get_handle(attr) + 2,
+ .value_handle = bt_gatt_attr_value_handle(attr),
+ .value = BT_GATT_CCC_NOTIFY,
+ .notify = battery_level_notify_cb,
+ };
+
+ err = bt_gatt_subscribe(default_conn, &battery_level_notify_params);
+ if (err && err != -EALREADY) {
+ TEST_FAIL("Subscribe failed (err %d)\n", err);
+ } else {
+ LOG_DBG("Battery level [SUBSCRIBED]\n");
+ }
+ read_battery_level(attr);
+}
+
+static void subscribe_battery_level_status(const struct bt_gatt_attr *attr)
+{
+ int err;
+
+ if (get_device_nbr() == 1) { /* One device for Indication */
+ battery_level_status_sub_params = (struct bt_gatt_subscribe_params){
+ /* In Zephyr, it is common practice for the CCC handle
+ * to be positioned two handles after the characteristic handle.
+ */
+ .ccc_handle = bt_gatt_attr_get_handle(attr) + 2,
+ .value_handle = bt_gatt_attr_value_handle(attr),
+ .value = BT_GATT_CCC_INDICATE,
+ .notify = battery_level_status_indicate_cb,
+ };
+ } else { /* Other device for Notification */
+ battery_level_status_sub_params = (struct bt_gatt_subscribe_params){
+ .ccc_handle = bt_gatt_attr_get_handle(attr) + 2,
+ .value_handle = bt_gatt_attr_value_handle(attr),
+ .value = BT_GATT_CCC_NOTIFY,
+ .notify = battery_level_status_notify_cb,
+ };
+ }
+
+ err = bt_gatt_subscribe(default_conn, &battery_level_status_sub_params);
+ if (err && err != -EALREADY) {
+ TEST_FAIL("Subscribe failed (err %d)\n", err);
+ } else {
+ LOG_DBG("Battery level status [SUBSCRIBED]\n");
+ }
+}
+
+static uint8_t discover_func(struct bt_conn *conn, const struct bt_gatt_attr *attr,
+ struct bt_gatt_discover_params *params)
+{
+ int err;
+
+ if (!attr) {
+ LOG_DBG("Discover complete\n");
+ memset(params, 0, sizeof(*params));
+ return BT_GATT_ITER_STOP;
+ }
+
+ LOG_DBG("[ATTRIBUTE] handle %u\n", attr->handle);
+
+ if (!bt_uuid_cmp(discover_params.uuid, BT_UUID_BAS)) {
+ LOG_DBG("Battery Service\n");
+ memcpy(&uuid, BT_UUID_BAS_BATTERY_LEVEL, sizeof(uuid));
+ discover_params.uuid = &uuid.uuid;
+ discover_params.start_handle = attr->handle + 1;
+ discover_params.type = BT_GATT_DISCOVER_CHARACTERISTIC;
+
+ err = bt_gatt_discover(conn, &discover_params);
+ if (err) {
+ TEST_FAIL("Discover failed (err %d)\n", err);
+ }
+
+ } else if (!bt_uuid_cmp(discover_params.uuid, BT_UUID_BAS_BATTERY_LEVEL)) {
+ LOG_DBG("Subscribe Battery Level Char\n");
+ subscribe_battery_level(attr);
+
+ memcpy(&uuid, BT_UUID_BAS_BATTERY_LEVEL_STATUS, sizeof(uuid));
+ discover_params.uuid = &uuid.uuid;
+ discover_params.start_handle = attr->handle + 1;
+ discover_params.type = BT_GATT_DISCOVER_CHARACTERISTIC;
+
+ err = bt_gatt_discover(conn, &discover_params);
+ if (err) {
+ TEST_FAIL("Discover failed (err %d)\n", err);
+ }
+ } else if (!bt_uuid_cmp(discover_params.uuid, BT_UUID_BAS_BATTERY_LEVEL_STATUS)) {
+ LOG_DBG("Subscribe Batterry Level Status Char\n");
+ subscribe_battery_level_status(attr);
+ }
+ return BT_GATT_ITER_STOP;
+}
+
+static void discover_bas_service(struct bt_conn *conn)
+{
+ int err;
+
+ LOG_DBG("%s\n", __func__);
+
+ memcpy(&uuid, BT_UUID_BAS, sizeof(uuid));
+ discover_params.uuid = &uuid.uuid;
+ discover_params.func = discover_func;
+ discover_params.start_handle = BT_ATT_FIRST_ATTRIBUTE_HANDLE;
+ discover_params.end_handle = BT_ATT_LAST_ATTRIBUTE_HANDLE;
+ discover_params.type = BT_GATT_DISCOVER_PRIMARY;
+ err = bt_gatt_discover(conn, &discover_params);
+ if (err) {
+ TEST_FAIL("Discover failed(err %d)\n", err);
+ return;
+ }
+}
+
+static void test_bas_central_main(void)
+{
+ int err;
+
+ /* Mark test as in progress. */
+ TEST_START("central");
+ /* bk_sync_init only works between two devices in a simulation, with IDs 0 and 1. */
+ if (get_device_nbr() == 1) {
+ /* Initialize device sync library */
+ bk_sync_init();
+ }
+
+ err = bt_enable(NULL);
+ TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err);
+
+ LOG_DBG("Bluetooth initialized\n");
+
+ err = bt_testlib_scan_find_name(&peer, CONFIG_BT_DEVICE_NAME);
+ TEST_ASSERT(!err, "Failed to start scan (err %d)", err);
+
+ /* Create a connection using that address */
+ err = bt_testlib_connect(&peer, &default_conn);
+ TEST_ASSERT(!err, "Failed to initiate connection (err %d)", err);
+
+ LOG_DBG("Connected");
+ discover_bas_service(default_conn);
+
+ if (get_device_nbr() == 1) {
+ WAIT_FOR_FLAG(indication_count_reached);
+ LOG_INF("Indication Count Reached!");
+ } else {
+ WAIT_FOR_FLAG(notification_count_reached);
+ LOG_INF("Notification Count Reached!");
+ }
+
+ /* bk_sync_send only works between two devices in a simulation, with IDs 0 and 1. */
+ if (get_device_nbr() == 1) {
+ bk_sync_send();
+ }
+
+ bst_result = Passed;
+ TEST_PASS("Central Test Passed");
+}
+
+static const struct bst_test_instance test_bas_central[] = {
+ {
+ .test_id = "central",
+ .test_descr =
+ "Battery Service test. It expects that a peripheral device can be found. "
+ "The test will pass if it can receive notifications and indications more "
+ "than the threshold set within 15 sec. ",
+ .test_pre_init_f = test_bas_central_init,
+ .test_tick_f = test_bas_central_tick,
+ .test_main_f = test_bas_central_main,
+ },
+ BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_bas_central_install(struct bst_test_list *tests)
+{
+ tests = bst_add_tests(tests, test_bas_central);
+ return tests;
+}
diff --git a/tests/bsim/bluetooth/samples/battery_service/src/main.c b/tests/bsim/bluetooth/samples/battery_service/src/main.c
new file mode 100644
index 0000000..26af62c
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/src/main.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Demant A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bstests.h"
+
+extern struct bst_test_list *test_bas_central_install(struct bst_test_list *tests);
+extern struct bst_test_list *test_bas_peripheral_install(struct bst_test_list *tests);
+
+bst_test_install_t test_installers[] = {
+ test_bas_central_install,
+ test_bas_peripheral_install,
+ NULL,
+};
+
+int main(void)
+{
+ bst_main();
+ return 0;
+}
diff --git a/tests/bsim/bluetooth/samples/battery_service/src/peripheral_test.c b/tests/bsim/bluetooth/samples/battery_service/src/peripheral_test.c
new file mode 100644
index 0000000..0d7c3a3
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/src/peripheral_test.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2024 Demant A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+
+#include "bs_types.h"
+#include "bs_tracing.h"
+#include "time_machine.h"
+#include "bstests.h"
+
+#include <zephyr/types.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/services/bas.h>
+#include <zephyr/sys/byteorder.h>
+
+#include "testlib/conn.h"
+#include "testlib/scan.h"
+#include "testlib/log_utils.h"
+
+#include "babblekit/flags.h"
+#include "babblekit/sync.h"
+#include "babblekit/testcase.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(bt_bsim_bas, CONFIG_BT_BAS_LOG_LEVEL);
+
+static struct bt_conn *default_conn;
+
+static struct k_work_delayable update_bas_char_work;
+
+/*
+ * Battery Service test:
+ * We expect a central to connect to us.
+ */
+
+#define WAIT_TIME 10 /*seconds*/
+
+extern enum bst_result_t bst_result;
+
+static void test_bas_peripheral_init(void)
+{
+ bst_ticker_set_next_tick_absolute(WAIT_TIME * 1e6);
+ bst_result = In_progress;
+}
+
+static void test_bas_peripheral_tick(bs_time_t HW_device_time)
+{
+ /*
+ * If in WAIT_TIME seconds the testcase did not already pass
+ * (and finish) we consider it failed
+ */
+ if (bst_result != Passed) {
+ TEST_FAIL("test_bas_peripheral failed (not passed after %i seconds)\n", WAIT_TIME);
+ }
+}
+
+static const struct bt_data ad[] = {
+ BT_DATA_BYTES(BT_DATA_FLAGS, (BT_LE_AD_GENERAL | BT_LE_AD_NO_BREDR)),
+ BT_DATA_BYTES(BT_DATA_UUID16_ALL, BT_UUID_16_ENCODE(BT_UUID_BAS_VAL)),
+ BT_DATA(BT_DATA_NAME_COMPLETE, CONFIG_BT_DEVICE_NAME, sizeof(CONFIG_BT_DEVICE_NAME) - 1),
+};
+
+static void connected(struct bt_conn *conn, uint8_t err)
+{
+ if (err) {
+ TEST_FAIL("Connection failed (err 0x%02x)\n", err);
+ } else {
+ default_conn = bt_conn_ref(conn);
+
+ LOG_DBG("Peripheral Connected\n");
+ }
+}
+
+static void disconnected(struct bt_conn *conn, uint8_t reason)
+{
+ LOG_DBG("Peripheral %s (reason 0x%02x)\n", __func__, reason);
+
+ if (default_conn) {
+ bt_conn_unref(default_conn);
+ default_conn = NULL;
+ }
+}
+
+static struct bt_conn_cb conn_callbacks = {
+ .connected = connected,
+ .disconnected = disconnected,
+};
+
+static void bt_ready(void)
+{
+ int err;
+
+ LOG_DBG("Peripheral Bluetooth initialized\n");
+
+ err = bt_le_adv_start(BT_LE_ADV_CONN, ad, ARRAY_SIZE(ad), NULL, 0);
+ if (err) {
+ TEST_FAIL("Advertising failed to start (err %d)\n", err);
+ return;
+ }
+
+ LOG_DBG("Advertising successfully started");
+}
+
+static void update_bas_char(void)
+{
+ LOG_DBG("[PERIPHERAL] setting battery level");
+ bt_bas_set_battery_level(90);
+ LOG_DBG("[PERIPHERAL] setting battery present");
+ bt_bas_bls_set_battery_present(BT_BAS_BLS_BATTERY_PRESENT);
+ LOG_DBG("[PERIPHERAL] setting battery charge level");
+ bt_bas_bls_set_battery_charge_level(BT_BAS_BLS_CHARGE_LEVEL_CRITICAL);
+ LOG_DBG("[PERIPHERAL] setting battery service required true");
+ bt_bas_bls_set_service_required(BT_BAS_BLS_SERVICE_REQUIRED_TRUE);
+ LOG_DBG("[PERIPHERAL] setting battery service charge type ");
+ bt_bas_bls_set_battery_charge_type(BT_BAS_BLS_CHARGE_TYPE_FLOAT);
+}
+
+/* Work handler function */
+void update_bas_char_work_handler(struct k_work *work)
+{
+ update_bas_char();
+ k_work_reschedule(&update_bas_char_work, K_SECONDS(1));
+}
+
+static void test_bas_peripheral_main(void)
+{
+ int err;
+
+ bt_conn_cb_register(&conn_callbacks);
+
+ /* Mark test as in progress. */
+ TEST_START("peripheral");
+
+ /* Initialize device sync library */
+ bk_sync_init();
+
+ /* Initialize Bluetooth */
+ err = bt_enable(NULL);
+ TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err);
+
+ LOG_DBG("Bluetooth initialized");
+
+ bt_ready();
+
+ /* Initialize the update bas char work handler */
+ k_work_init_delayable(&update_bas_char_work, update_bas_char_work_handler);
+
+ /* Schedule the update bas char work for delayed execution */
+ k_work_schedule(&update_bas_char_work, K_SECONDS(1));
+
+ /* Main thread waits for the sync signal from other device */
+ bk_sync_wait();
+
+ bst_result = Passed;
+ TEST_PASS_AND_EXIT("Peripheral Test Passed");
+}
+
+static const struct bst_test_instance test_bas_peripheral[] = {
+ {
+ .test_id = "peripheral",
+ .test_descr = "Battery Service test. It expects that a central device can be found "
+ "The test will pass if ind/ntf can be sent without crash. ",
+ .test_pre_init_f = test_bas_peripheral_init,
+ .test_tick_f = test_bas_peripheral_tick,
+ .test_main_f = test_bas_peripheral_main,
+ },
+ BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_bas_peripheral_install(struct bst_test_list *tests)
+{
+ tests = bst_add_tests(tests, test_bas_peripheral);
+ return tests;
+}
diff --git a/tests/bsim/bluetooth/samples/battery_service/tests_scripts/bas.sh b/tests/bsim/bluetooth/samples/battery_service/tests_scripts/bas.sh
new file mode 100755
index 0000000..7a80f61
--- /dev/null
+++ b/tests/bsim/bluetooth/samples/battery_service/tests_scripts/bas.sh
@@ -0,0 +1,29 @@
+#!/usr/bin/env bash
+# Copyright 2024 Demant A/S
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+# Battery service test: a central connects to a peripheral and expects a
+# indication/notification of BAS chars from peripheral
+simulation_id="battery_service_test"
+verbosity_level=2
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_samples_battery_service_prj_conf \
+ -v=${verbosity_level} -s=${simulation_id} -d=0 \
+ -testid=peripheral -rs=23
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_samples_battery_service_prj_conf\
+ -v=${verbosity_level} -s=${simulation_id} -d=1 \
+ -testid=central -rs=6
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_samples_battery_service_prj_conf\
+ -v=${verbosity_level} -s=${simulation_id} -d=2 \
+ -testid=central -rs=6
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+ -D=3 -sim_length=10e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/samples/compile.sh b/tests/bsim/bluetooth/samples/compile.sh
index 3b61bdf..98a6e9d 100755
--- a/tests/bsim/bluetooth/samples/compile.sh
+++ b/tests/bsim/bluetooth/samples/compile.sh
@@ -37,5 +37,10 @@
extra_conf_file=${ZEPHYR_BASE}/samples/bluetooth/central_hr/prj.conf \
conf_overlay=${ZEPHYR_BASE}/samples/bluetooth/central_hr/overlay-phy_coded.conf \
compile
+if [ ${BOARD} == "nrf52_bsim" ]; then
+ app=tests/bsim/bluetooth/samples/battery_service \
+ conf_file=prj.conf \
+ compile
+fi
wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt b/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
index fec0c4a..749a42d 100644
--- a/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
+++ b/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
@@ -2,5 +2,5 @@
# This file is used in CI to select which tests are run
tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh
tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh
-tests/bsim/bluetooth/samples/
+tests/bsim/bluetooth/samples/central_hr_peripheral_hr/
tests/bsim/bluetooth/audio_samples/
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
new file mode 100644
index 0000000..e3aced0
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ zephyr,user {
+ io-channels = <&adc0 0>;
+ reference_mv = <3300>;
+ };
+};
+
+&adc0{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ channel@0 {
+ reg = <0>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <12>;
+ zephyr,vref-mv = <3300>;
+ };
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/testcase.yaml b/tests/drivers/adc/adc_accuracy_test/testcase.yaml
index 07bf2e5..e33f723 100644
--- a/tests/drivers/adc/adc_accuracy_test/testcase.yaml
+++ b/tests/drivers/adc/adc_accuracy_test/testcase.yaml
@@ -12,8 +12,10 @@
fixture: dac_adc_loopback
platform_allow:
- frdm_k64f
+ - ek_ra8m1
drivers.adc.accuracy.ref_volt:
harness_config:
fixture: adc_ref_volt
platform_allow:
- frdm_kl25z
+ - ek_ra8m1
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf b/tests/drivers/adc/adc_api/boards/apollo3_evb.conf
similarity index 100%
rename from tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf
rename to tests/drivers/adc/adc_api/boards/apollo3_evb.conf
diff --git a/tests/drivers/adc/adc_api/boards/apollo3_evb.overlay b/tests/drivers/adc/adc_api/boards/apollo3_evb.overlay
new file mode 100644
index 0000000..e5a6d84
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/apollo3_evb.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+ zephyr,user {
+ io-channels = <&adc0 4>, <&adc0 7>;
+ };
+};
+
+&adc0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <12>;
+ };
+};
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf b/tests/drivers/adc/adc_api/boards/apollo3p_evb.conf
similarity index 100%
copy from tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf
copy to tests/drivers/adc/adc_api/boards/apollo3p_evb.conf
diff --git a/tests/drivers/adc/adc_api/boards/apollo3p_evb.overlay b/tests/drivers/adc/adc_api/boards/apollo3p_evb.overlay
new file mode 100644
index 0000000..e5a6d84
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/apollo3p_evb.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+ zephyr,user {
+ io-channels = <&adc0 4>, <&adc0 7>;
+ };
+};
+
+&adc0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <14>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,resolution = <12>;
+ };
+};
diff --git a/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay
new file mode 100644
index 0000000..07924ac
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+ zephyr,user {
+ io-channels = <&adc1 0>, <&adc1 2>;
+ };
+};
+
+&pinctrl {
+ adc1_default: adc1_default {
+ group1 {
+ /* input */
+ psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+ renesas,analog-enable;
+ };
+ };
+};
+
+&adc1 {
+ pinctrl-0 = <&adc1_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,resolution = <12>;
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,vref-mv = <3300>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ zephyr,gain = "ADC_GAIN_1";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,resolution = <12>;
+ zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+ zephyr,vref-mv = <3300>;
+ };
+};
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.conf b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index b6c5c80..0000000
--- a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_ADC_ASYNC=n
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.overlay b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index c288312..0000000
--- a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2022 Wolter HV <wolterhv@gmx.de>
- * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- zephyr,user {
- /* adjust channel number according to pinmux in board.dts */
- io-channels = <&adc0 0>, <&adc0 1>;
- };
-};
-
-&adc0 {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- channel@0 {
- reg = <0>;
- zephyr,gain = "ADC_GAIN_1";
- zephyr,reference = "ADC_REF_INTERNAL";
- zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
- zephyr,resolution = <12>;
- };
-
- channel@1 {
- reg = <1>;
- zephyr,gain = "ADC_GAIN_1";
- zephyr,reference = "ADC_REF_INTERNAL";
- zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
- zephyr,resolution = <12>;
- };
-};
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.conf b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index b6c5c80..0000000
--- a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_ADC_ASYNC=n
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index c288312..0000000
--- a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2022 Wolter HV <wolterhv@gmx.de>
- * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- zephyr,user {
- /* adjust channel number according to pinmux in board.dts */
- io-channels = <&adc0 0>, <&adc0 1>;
- };
-};
-
-&adc0 {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- channel@0 {
- reg = <0>;
- zephyr,gain = "ADC_GAIN_1";
- zephyr,reference = "ADC_REF_INTERNAL";
- zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
- zephyr,resolution = <12>;
- };
-
- channel@1 {
- reg = <1>;
- zephyr,gain = "ADC_GAIN_1";
- zephyr,reference = "ADC_REF_INTERNAL";
- zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
- zephyr,resolution = <12>;
- };
-};
diff --git a/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay
new file mode 100644
index 0000000..d9c1f96
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+/ {
+ zephyr,user {
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>;
+ };
+};
+
+&adc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ zephyr,gain = "ADC_GAIN_1_2";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+ zephyr,input-positive = <NRF_SAADC_AIN1>;
+ zephyr,resolution = <10>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ zephyr,gain = "ADC_GAIN_2";
+ zephyr,reference = "ADC_REF_EXTERNAL0";
+ zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+ zephyr,input-positive = <NRF_SAADC_AIN3>;
+ zephyr,resolution = <10>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ zephyr,gain = "ADC_GAIN_1_2";
+ zephyr,reference = "ADC_REF_INTERNAL";
+ zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+ zephyr,input-positive = <NRF_SAADC_AIN2>;
+ zephyr,resolution = <10>;
+ };
+};
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf b/tests/drivers/adc/adc_api/socs/esp32c3.conf
similarity index 100%
copy from tests/drivers/adc/adc_api/boards/esp32c3_devkitm.conf
copy to tests/drivers/adc/adc_api/socs/esp32c3.conf
diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_devkitm.overlay b/tests/drivers/adc/adc_api/socs/esp32c3.overlay
similarity index 100%
rename from tests/drivers/adc/adc_api/boards/esp32c3_devkitm.overlay
rename to tests/drivers/adc/adc_api/socs/esp32c3.overlay
diff --git a/tests/drivers/build_all/haptics/i2c.dtsi b/tests/drivers/build_all/haptics/i2c.dtsi
index 2038347..a4fc6bb 100644
--- a/tests/drivers/build_all/haptics/i2c.dtsi
+++ b/tests/drivers/build_all/haptics/i2c.dtsi
@@ -11,4 +11,6 @@
compatible = "ti,drv2605";
reg = <0x0>;
status = "okay";
+
+ actuator-mode = "LRA";
};
diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay
index a0216c0..06e9114 100644
--- a/tests/drivers/build_all/input/app.overlay
+++ b/tests/drivers/build_all/input/app.overlay
@@ -154,6 +154,14 @@
long-delay-ms = <100>;
};
+ double_tap: doubletap {
+ input = <&double_tap>;
+ compatible = "zephyr,input-double-tap";
+ input-codes = <0>;
+ double-tap-codes = <0>;
+ double-tap-delay-ms = <0>;
+ };
+
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi
index 8fb151e..8bf865c 100644
--- a/tests/drivers/build_all/sensor/i2c.dtsi
+++ b/tests/drivers/build_all/sensor/i2c.dtsi
@@ -1024,51 +1024,69 @@
status = "okay";
};
-test_i2c_iis328dq: iis328dq@8a {
+test_i2c_iis328dq: iis328dq@8b {
compatible = "st,iis328dq";
status = "okay";
- reg = <0x8a>;
+ reg = <0x8b>;
int2-gpios = <&test_gpio 0 0>;
threshold-int-pad = <2>;
};
-test_i2c_nct75: test_i2c_nct75@8b {
+test_i2c_nct75: test_i2c_nct75@8c {
compatible = "onnn,nct75";
- reg = <0x8b>;
+ reg = <0x8c>;
status = "okay";
};
-test_i2c_tmp114: tmp114@8c {
+test_i2c_tmp114: tmp114@8d {
compatible = "ti,tmp114";
- reg = <0x8c>;
+ reg = <0x8d>;
};
-test_i2c_ina226: ina226@8d {
+test_i2c_ina226: ina226@8e {
compatible = "ti,ina226";
- reg = <0x8d>;
+ reg = <0x8e>;
current-lsb-microamps = <5000>;
rshunt-micro-ohms = <500>;
};
-test_i2c_shtc1: shtc1@8e {
+test_i2c_shtc1: shtc1@8f {
compatible = "sensirion,shtc1", "sensirion,shtcx";
- reg = <0x8e>;
+ reg = <0x8f>;
measure-mode = "low-power";
clock-stretching;
};
-test_i2c_lm95234: lm95234@8f {
+test_i2c_lm95234: lm95234@90 {
compatible = "national,lm95234";
- reg = <0x8f>;
+ reg = <0x90>;
status = "okay";
};
-test_i2c_sht21@90 {
+test_i2c_sht21@91 {
compatible = "sensirion,sht21";
- reg = <0x90>;
+ reg = <0x91>;
};
-test_i2c_lsm9ds1: lsm9ds1@91 {
+test_i2c_lsm9ds1: lsm9ds1@92 {
compatible = "st,lsm9ds1";
- reg = <0x8e>;
+ reg = <0x92>;
+};
+
+test_i2c_icm42670: icm42670@92 {
+ compatible = "invensense,icm42670";
+ reg = <0x92>;
+ int-gpios = <&test_gpio 0 0>;
+ accel-hz = <800>;
+ accel-fs = <16>;
+ gyro-hz = <800>;
+ gyro-fs = <2000>;
+};
+
+test_i2c_fxls8974: fxls8974@93 {
+ compatible = "nxp,fxls8974";
+ reg = <0x93>;
+ reset-gpios = <&test_gpio 0 0>;
+ int1-gpios = <&test_gpio 0 0>;
+ int2-gpios = <&test_gpio 0 0>;
};
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf
index f7e44c2..3a36a35 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf
@@ -19,6 +19,7 @@
CONFIG_FDC2X1X_TRIGGER_GLOBAL_THREAD=y
CONFIG_FXAS21002_TRIGGER_GLOBAL_THREAD=y
CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y
+CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD=y
CONFIG_GROW_R502A_TRIGGER_GLOBAL_THREAD=y
CONFIG_HMC5883L_TRIGGER_GLOBAL_THREAD=y
CONFIG_HTS221_TRIGGER_GLOBAL_THREAD=y
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf
index 9032601..805347a 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf
@@ -19,6 +19,7 @@
CONFIG_FDC2X1X_TRIGGER_NONE=y
CONFIG_FXAS21002_TRIGGER_NONE=y
CONFIG_FXOS8700_TRIGGER_NONE=y
+CONFIG_FXLS8974_TRIGGER_NONE=y
CONFIG_GROW_R502A_TRIGGER_NONE=y
CONFIG_HMC5883L_TRIGGER_NONE=y
CONFIG_HTS221_TRIGGER_NONE=y
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf
index 878a4ba..ef31101 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf
@@ -18,6 +18,7 @@
CONFIG_FDC2X1X_TRIGGER_OWN_THREAD=y
CONFIG_FXAS21002_TRIGGER_OWN_THREAD=y
CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXLS8974_TRIGGER_OWN_THREAD=y
CONFIG_GROW_R502A_TRIGGER_OWN_THREAD=y
CONFIG_HMC5883L_TRIGGER_OWN_THREAD=y
CONFIG_HTS221_TRIGGER_OWN_THREAD=y
diff --git a/tests/drivers/build_all/sensor/src/generic_test.c b/tests/drivers/build_all/sensor/src/generic_test.c
index 0da0bb7..b8500b4 100644
--- a/tests/drivers/build_all/sensor/src/generic_test.c
+++ b/tests/drivers/build_all/sensor/src/generic_test.c
@@ -63,8 +63,9 @@
/* Flush the SQ and CQ */
rtio_sqe_drop_all(&sensor_read_rtio_ctx);
- while (rtio_cqe_consume(&sensor_read_rtio_ctx))
+ while (rtio_cqe_consume(&sensor_read_rtio_ctx)) {
;
+ }
}
/**
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
index cadef95..d8584b4 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
@@ -11,11 +11,7 @@
&clk_hse {
status = "disabled";
- /delete-property/ hse-div;
-};
-
-&clk_hsi {
- status = "disabled";
+ /delete-property/ hse-div2;
};
&clk_lse {
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
index bdaf05c..6a36fb4 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
@@ -1,10 +1,10 @@
common:
timeout: 5
- platform_allow: nucleo_wba52cg
+ platform_allow: nucleo_wba52cg nucleo_wba55cg
tests:
- drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_32:
+ drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
- drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_32_ahb5_div:
+ drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_16_ahb5_div:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16_ahb5_div.overlay"
drivers.clock.stm32_clock_configuration.wba.sysclksrc_hse_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_16.overlay"
diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index 241947b..0000000
--- a/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,3 +0,0 @@
-&timer0 {
- status = "okay";
-};
diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index 241947b..0000000
--- a/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,3 +0,0 @@
-&timer0 {
- status = "okay";
-};
diff --git a/tests/drivers/counter/counter_basic_api/socs/esp32c2.overlay b/tests/drivers/counter/counter_basic_api/socs/esp32c2.overlay
new file mode 100644
index 0000000..0fcefc4
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/socs/esp32c2.overlay
@@ -0,0 +1,7 @@
+&timer0 {
+ status = "okay";
+};
+
+&rtc_timer {
+ status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32c3_devkitm.overlay b/tests/drivers/counter/counter_basic_api/socs/esp32c3.overlay
similarity index 100%
rename from tests/drivers/counter/counter_basic_api/boards/esp32c3_devkitm.overlay
rename to tests/drivers/counter/counter_basic_api/socs/esp32c3.overlay
diff --git a/tests/drivers/disk/disk_access/boards/native_posix_no_explicit_erase.overlay b/tests/drivers/disk/disk_access/boards/native_sim_no_explicit_erase.overlay
similarity index 100%
rename from tests/drivers/disk/disk_access/boards/native_posix_no_explicit_erase.overlay
rename to tests/drivers/disk/disk_access/boards/native_sim_no_explicit_erase.overlay
diff --git a/tests/drivers/disk/disk_access/testcase.yaml b/tests/drivers/disk/disk_access/testcase.yaml
index 94f25c0..d4c2b53 100644
--- a/tests/drivers/disk/disk_access/testcase.yaml
+++ b/tests/drivers/disk/disk_access/testcase.yaml
@@ -37,10 +37,10 @@
drivers.disk.stm32_sdhc:
filter: dt_compat_enabled("st,stm32-sdmmc")
drivers.disk.simulator.no_explicit_erase:
- extra_args: DTC_OVERLAY_FILE=boards/native_posix_no_explicit_erase.overlay
+ extra_args: DTC_OVERLAY_FILE=boards/native_sim_no_explicit_erase.overlay
extra_configs:
- CONFIG_DISK_DRIVER_FLASH=y
- CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE=n
platform_allow:
- - native_posix/native/64
- - native_posix
+ - native_sim/native/64
+ - native_sim
diff --git a/tests/drivers/dma/chan_blen_transfer/CMakeLists.txt b/tests/drivers/dma/chan_blen_transfer/CMakeLists.txt
index 7683c4e..bc85cc0 100644
--- a/tests/drivers/dma/chan_blen_transfer/CMakeLists.txt
+++ b/tests/drivers/dma/chan_blen_transfer/CMakeLists.txt
@@ -7,4 +7,6 @@
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})
-zephyr_code_relocate(FILES src/test_dma.c LOCATION ${CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION}_RODATA_BSS)
+if (CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION)
+ zephyr_code_relocate(FILES src/test_buffers.c LOCATION ${CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION})
+endif()
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_devkitm.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_devkitm.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_devkitm.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.conf b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 56bf25e..0000000
--- a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DMA_TRANSFER_CHANNEL_NR_0=5
-CONFIG_DMA_TRANSFER_CHANNEL_NR_1=0
-CONFIG_HEAP_MEM_POOL_SIZE=32768
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 56bf25e..0000000
--- a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_DMA_TRANSFER_CHANNEL_NR_0=5
-CONFIG_DMA_TRANSFER_CHANNEL_NR_1=0
-CONFIG_HEAP_MEM_POOL_SIZE=32768
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.conf
index 8aa1160..433a675 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.conf
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.conf
@@ -1,3 +1,3 @@
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_MEM_ATTR_HEAP=y
-CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM"
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay
index 43b7fc3..82f0bbe 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay
@@ -7,7 +7,7 @@
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-&itcm {
+&dtcm {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf
index 8aa1160..433a675 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf
@@ -1,3 +1,3 @@
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_MEM_ATTR_HEAP=y
-CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM"
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.overlay
index 43b7fc3..82f0bbe 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.overlay
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.overlay
@@ -7,7 +7,7 @@
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-&itcm {
+&dtcm {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.conf
index 8aa1160..433a675 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.conf
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.conf
@@ -1,3 +1,3 @@
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_MEM_ATTR_HEAP=y
-CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM"
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.overlay
index 43b7fc3..82f0bbe 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.overlay
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evkb.overlay
@@ -7,7 +7,7 @@
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-&itcm {
+&dtcm {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.conf
index 8aa1160..433a675 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.conf
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.conf
@@ -1,3 +1,3 @@
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_MEM_ATTR_HEAP=y
-CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM"
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay
index 43b7fc3..82f0bbe 100644
--- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay
@@ -7,7 +7,7 @@
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-&itcm {
+&dtcm {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_devkitm.conf b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.conf
similarity index 100%
rename from tests/drivers/dma/chan_blen_transfer/boards/esp32c3_devkitm.conf
rename to tests/drivers/dma/chan_blen_transfer/socs/esp32c3.conf
diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay
new file mode 100644
index 0000000..6ac9ff0
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma {
+ status = "okay";
+};
+
+tst_dma0: &dma { };
diff --git a/tests/drivers/dma/chan_blen_transfer/src/test_buffers.c b/tests/drivers/dma/chan_blen_transfer/src/test_buffers.c
new file mode 100644
index 0000000..3ec893f
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/src/test_buffers.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include "test_buffers.h"
+
+__aligned(32) char tx_data[TEST_BUF_SIZE] = "It is harder to be kind than to be wise........";
+__aligned(32) char rx_data[TEST_BUF_SIZE] = { 0 };
diff --git a/tests/drivers/dma/chan_blen_transfer/src/test_buffers.h b/tests/drivers/dma/chan_blen_transfer/src/test_buffers.h
new file mode 100644
index 0000000..d69bf91
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/src/test_buffers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#define TEST_BUF_SIZE (48)
+
+extern char tx_data[TEST_BUF_SIZE];
+extern char rx_data[TEST_BUF_SIZE];
diff --git a/tests/drivers/dma/chan_blen_transfer/src/test_dma.c b/tests/drivers/dma/chan_blen_transfer/src/test_dma.c
index 054bb6b..d5b2b7f 100644
--- a/tests/drivers/dma/chan_blen_transfer/src/test_dma.c
+++ b/tests/drivers/dma/chan_blen_transfer/src/test_dma.c
@@ -20,10 +20,7 @@
#include <zephyr/drivers/dma.h>
#include <zephyr/ztest.h>
-#define RX_BUFF_SIZE (48)
-
-static __aligned(32) char tx_data[] = "It is harder to be kind than to be wise........";
-static __aligned(32) char rx_data[RX_BUFF_SIZE] = { 0 };
+#include "test_buffers.h"
static void test_done(const struct device *dma_dev, void *arg,
uint32_t id, int status)
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_devkitm.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c3_devkitm.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/loop_transfer/boards/esp32c3_devkitm.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.conf b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 311bfc8..0000000
--- a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0
-CONFIG_DMA_LOOP_TRANSFER_SIZE=4094
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 311bfc8..0000000
--- a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0
-CONFIG_DMA_LOOP_TRANSFER_SIZE=4094
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index c93ef73..0000000
--- a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&dma {
- status = "okay";
-};
-
-tst_dma0: &dma { };
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_devkitm.conf b/tests/drivers/dma/loop_transfer/socs/esp32c3.conf
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/esp32c3_devkitm.conf
rename to tests/drivers/dma/loop_transfer/socs/esp32c3.conf
diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay b/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay
new file mode 100644
index 0000000..6ac9ff0
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma {
+ status = "okay";
+};
+
+tst_dma0: &dma { };
diff --git a/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.conf b/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.conf
new file mode 100644
index 0000000..c448e14
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.conf
@@ -0,0 +1 @@
+CONFIG_NOCACHE_MEMORY=y
diff --git a/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.overlay b/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.overlay
new file mode 100644
index 0000000..3feef4c
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/intel_socfpga_agilex5_socdk.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ aliases {
+ dma0 = &dma0;
+ };
+};
+
+&dma0 {
+ status = "okay";
+};
diff --git a/tests/drivers/flash/common/boards/esp32c3_luatos_core.conf b/tests/drivers/flash/common/boards/esp32c3_luatos_core.conf
deleted file mode 100644
index 2bcf636..0000000
--- a/tests/drivers/flash/common/boards/esp32c3_luatos_core.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=16384
diff --git a/tests/drivers/flash/common/boards/esp32c3_luatos_core_esp32c3_usb.conf b/tests/drivers/flash/common/boards/esp32c3_luatos_core_esp32c3_usb.conf
deleted file mode 100644
index 2bcf636..0000000
--- a/tests/drivers/flash/common/boards/esp32c3_luatos_core_esp32c3_usb.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_HEAP_MEM_POOL_SIZE=16384
diff --git a/tests/drivers/flash/common/boards/mimxrt1060_evk.conf b/tests/drivers/flash/common/boards/mimxrt1060_evk.conf
index 45b222b..69cc7d8 100644
--- a/tests/drivers/flash/common/boards/mimxrt1060_evk.conf
+++ b/tests/drivers/flash/common/boards/mimxrt1060_evk.conf
@@ -3,4 +3,4 @@
# SPDX-License-Identifier: Apache-2.0
#
-CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM=y
+CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM="RAM"
diff --git a/tests/drivers/flash/common/boards/esp32c3_devkitm.conf b/tests/drivers/flash/common/socs/esp32c3.conf
similarity index 100%
rename from tests/drivers/flash/common/boards/esp32c3_devkitm.conf
rename to tests/drivers/flash/common/socs/esp32c3.conf
diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c
index 048542b..7889e09 100644
--- a/tests/drivers/flash/common/src/main.c
+++ b/tests/drivers/flash/common/src/main.c
@@ -42,6 +42,20 @@
#error "Unsupported configuraiton"
#endif
+#define TEST_FLASH_START (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)))
+#if (DT_PROP(DT_CHOSEN(zephyr_flash), size))
+/* When flash is defined in DTS as:
+ * size = < 0x4000000 >;
+ * reg = < 0x0 >;
+ */
+#define TEST_FLASH_SIZE (DT_PROP(DT_CHOSEN(zephyr_flash), size))
+#else
+/* When flash is defined in DTS as:
+ * reg = < 0xe000000 0x200000 >;
+ */
+#define TEST_FLASH_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)))
+#endif /* #if (DT_PROP(DT_CHOSEN(zephyr_flash), size)) */
+
#define EXPECTED_SIZE 512
#if !defined(CONFIG_FLASH_HAS_EXPLICIT_ERASE) && \
@@ -253,5 +267,273 @@
zassert_equal(i, EXPECTED_SIZE, "Expected device to be filled wth 0xaa");
}
+ZTEST(flash_driver, test_flash_erase)
+{
+ int rc;
+ uint8_t read_buf[EXPECTED_SIZE];
+ bool comparison_result;
+ const struct flash_parameters *fparams = flash_get_parameters(flash_dev);
+
+ erase_value = fparams->erase_value;
+
+ /* Write test data */
+ rc = flash_write(flash_dev, page_info.start_offset, expected, EXPECTED_SIZE);
+ zassert_equal(rc, 0, "Cannot write to flash");
+
+ /* Confirm write operation */
+ rc = flash_read(flash_dev, page_info.start_offset, read_buf, EXPECTED_SIZE);
+ zassert_equal(rc, 0, "Cannot read flash");
+
+ comparison_result = true;
+ for (int i = 0; i < EXPECTED_SIZE; i++) {
+ if (read_buf[i] != expected[i]) {
+ comparison_result = false;
+ TC_PRINT("i=%d:\tread_buf[i]=%d\texpected[i]=%d\n", i, read_buf[i],
+ expected[i]);
+ }
+ }
+ zassert_true(comparison_result, "Write operation failed");
+ /* Cross check - confirm that expected data is pseudo-random */
+ zassert_not_equal(read_buf[0], expected[1], "These values shall be different");
+
+ /* Erase a nb of pages aligned to the EXPECTED_SIZE */
+ rc = flash_erase(
+ flash_dev, page_info.start_offset,
+ (page_info.size * ((EXPECTED_SIZE + page_info.size - 1) / page_info.size)));
+ zassert_equal(rc, 0, "Flash memory not properly erased");
+
+ /* Confirm erase operation */
+ rc = flash_read(flash_dev, page_info.start_offset, read_buf, EXPECTED_SIZE);
+ zassert_equal(rc, 0, "Cannot read flash");
+
+ comparison_result = true;
+ for (int i = 0; i < EXPECTED_SIZE; i++) {
+ if (read_buf[i] != erase_value) {
+ comparison_result = false;
+ TC_PRINT("i=%d:\tread_buf[i]=%d\texpected=%d\n", i, read_buf[i],
+ erase_value);
+ }
+ }
+ zassert_true(comparison_result, "Write operation failed");
+ /* Cross check - confirm that expected data
+ * doesn't contain erase_value
+ */
+ zassert_not_equal(expected[0], erase_value, "These values shall be different");
+}
+
+ZTEST(flash_driver, test_negative_flash_erase)
+{
+ int rc;
+
+#if !defined(TEST_AREA)
+ /* Flash memory boundaries are correctly calculated
+ * only for storage_partition.
+ */
+ ztest_test_skip();
+#endif
+
+ TC_PRINT("TEST_FLASH_START = 0x%lx\n", (unsigned long)TEST_FLASH_START);
+ TC_PRINT("TEST_FLASH_SIZE = 0x%lx\n", (unsigned long)TEST_FLASH_SIZE);
+
+ /* Check error returned when erasing memory at wrong address (too low) */
+ rc = flash_erase(flash_dev, (TEST_FLASH_START - 1), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_erase returned %d", rc);
+
+ /* Check error returned when erasing memory at wrong address (too high) */
+ rc = flash_erase(flash_dev, (TEST_FLASH_START + TEST_FLASH_SIZE), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_erase returned %d", rc);
+
+ /* Check error returned when erasing to large chunk of memory */
+ rc = flash_erase(flash_dev, TEST_AREA_OFFSET, (TEST_FLASH_SIZE - TEST_AREA_OFFSET + 1));
+ zassert_true(rc < 0, "Invalid use of flash_erase returned %d", rc);
+
+ /* Erasing 0 bytes shall succeed */
+ rc = flash_erase(flash_dev, TEST_AREA_OFFSET, 0);
+ zassert_true(rc == 0, "flash_erase 0 bytes returned %d", rc);
+}
+
+ZTEST(flash_driver, test_negative_flash_fill)
+{
+ int rc;
+ uint8_t fill_val = 0xA; /* Dummy value */
+
+#if !defined(TEST_AREA)
+ /* Flash memory boundaries are correctly calculated
+ * only for storage_partition.
+ */
+ ztest_test_skip();
+#endif
+
+ /* Check error returned when filling memory at wrong address (too low) */
+ rc = flash_fill(flash_dev, fill_val, (TEST_FLASH_START - 1), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_fill returned %d", rc);
+
+ /* Check error returned when filling memory at wrong address (too high) */
+ rc = flash_fill(flash_dev, fill_val, (TEST_FLASH_START + TEST_FLASH_SIZE), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_fill returned %d", rc);
+
+ /* Check error returned when filling to large chunk of memory */
+ rc = flash_fill(flash_dev, fill_val, TEST_AREA_OFFSET,
+ (TEST_FLASH_SIZE - TEST_AREA_OFFSET + 1));
+ zassert_true(rc < 0, "Invalid use of flash_fill returned %d", rc);
+
+ /* Filling 0 bytes shall succeed */
+ rc = flash_fill(flash_dev, fill_val, TEST_AREA_OFFSET, 0);
+ zassert_true(rc == 0, "flash_fill 0 bytes returned %d", rc);
+}
+
+ZTEST(flash_driver, test_negative_flash_flatten)
+{
+ int rc;
+
+#if !defined(TEST_AREA)
+ /* Flash memory boundaries are correctly calculated
+ * only for storage_partition.
+ */
+ ztest_test_skip();
+#endif
+
+ /* Check error returned when flatten memory at wrong address (too low) */
+ rc = flash_flatten(flash_dev, (TEST_FLASH_START - 1), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_flatten returned %d", rc);
+
+ /* Check error returned when flatten memory at wrong address (too high) */
+ rc = flash_flatten(flash_dev, (TEST_FLASH_START + TEST_FLASH_SIZE), EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_flatten returned %d", rc);
+
+ /* Check error returned when flatten to large chunk of memory */
+ rc = flash_flatten(flash_dev, TEST_AREA_OFFSET, (TEST_FLASH_SIZE - TEST_AREA_OFFSET + 1));
+ zassert_true(rc < 0, "Invalid use of flash_flatten returned %d", rc);
+
+ /* Flatten 0 bytes shall succeed */
+ rc = flash_flatten(flash_dev, TEST_AREA_OFFSET, 0);
+ zassert_true(rc == 0, "flash_flatten 0 bytes returned %d", rc);
+}
+
+ZTEST(flash_driver, test_negative_flash_read)
+{
+ int rc;
+ uint8_t read_buf[EXPECTED_SIZE];
+
+#if !defined(TEST_AREA)
+ /* Flash memory boundaries are correctly calculated
+ * only for storage_partition.
+ */
+ ztest_test_skip();
+#endif
+
+ /* Check error returned when reading from a wrong address (too low) */
+ rc = flash_read(flash_dev, (TEST_FLASH_START - 1), read_buf, EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_read returned %d", rc);
+
+ /* Check error returned when reading from a wrong address (too high) */
+ rc = flash_read(flash_dev, (TEST_FLASH_START + TEST_FLASH_SIZE), read_buf, EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_read returned %d", rc);
+
+ /* Check error returned when reading too many data */
+ rc = flash_read(flash_dev, TEST_AREA_OFFSET, read_buf,
+ (TEST_FLASH_SIZE - TEST_AREA_OFFSET + 1));
+ zassert_true(rc < 0, "Invalid use of flash_read returned %d", rc);
+
+ /* Reading 0 bytes shall succeed */
+ rc = flash_read(flash_dev, TEST_AREA_OFFSET, read_buf, 0);
+ zassert_true(rc == 0, "flash_read 0 bytes returned %d", rc);
+}
+
+ZTEST(flash_driver, test_negative_flash_write)
+{
+ int rc;
+
+#if !defined(TEST_AREA)
+ /* Flash memory boundaries are correctly calculated
+ * only for storage_partition.
+ */
+ ztest_test_skip();
+#endif
+
+ /* Check error returned when writing to a wrong address (too low) */
+ rc = flash_write(flash_dev, (TEST_FLASH_START - 1), expected, EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_write returned %d", rc);
+
+ /* Check error returned when writing to a wrong address (too high) */
+ rc = flash_write(flash_dev, (TEST_FLASH_START + TEST_FLASH_SIZE), expected, EXPECTED_SIZE);
+ zassert_true(rc < 0, "Invalid use of flash_write returned %d", rc);
+
+ /* Check error returned when writing too many data */
+ rc = flash_write(flash_dev, TEST_AREA_OFFSET, expected,
+ (TEST_FLASH_SIZE - TEST_AREA_OFFSET + 1));
+ zassert_true(rc < 0, "Invalid use of flash_write returned %d", rc);
+
+ /* Writing 0 bytes shall succeed */
+ rc = flash_write(flash_dev, TEST_AREA_OFFSET, expected, 0);
+ zassert_true(rc == 0, "flash_write 0 bytes returned %d", rc);
+}
+
+struct test_cb_data_type {
+ uint32_t page_counter; /* used to count how many pages was iterated */
+ uint32_t exit_page; /* terminate iteration when this page is reached */
+};
+
+static bool flash_callback(const struct flash_pages_info *info, void *data)
+{
+ struct test_cb_data_type *cb_data = (struct test_cb_data_type *)data;
+
+ cb_data->page_counter++;
+
+ if (cb_data->page_counter >= cb_data->exit_page) {
+ return false;
+ }
+
+ return true;
+}
+
+ZTEST(flash_driver, test_flash_page_layout)
+{
+ int rc;
+ struct flash_pages_info page_info_off = {0};
+ struct flash_pages_info page_info_idx = {0};
+ size_t page_count;
+ struct test_cb_data_type test_cb_data = {0};
+
+#if !defined(CONFIG_FLASH_PAGE_LAYOUT)
+ ztest_test_skip();
+#endif
+
+ /* Get page info with flash_get_page_info_by_offs() */
+ rc = flash_get_page_info_by_offs(flash_dev, TEST_AREA_OFFSET, &page_info_off);
+ zassert_true(rc == 0, "flash_get_page_info_by_offs returned %d", rc);
+ TC_PRINT("start_offset=0x%lx\tsize=%d\tindex=%d\n", page_info_off.start_offset,
+ (int)page_info_off.size, page_info_off.index);
+ zassert_true(page_info_off.start_offset >= 0, "start_offset is %d", rc);
+ zassert_true(page_info_off.size > 0, "size is %d", rc);
+ zassert_true(page_info_off.index >= 0, "index is %d", rc);
+
+ /* Get info for the same page with flash_get_page_info_by_idx() */
+ rc = flash_get_page_info_by_idx(flash_dev, page_info_off.index, &page_info_idx);
+ zassert_true(rc == 0, "flash_get_page_info_by_offs returned %d", rc);
+ zassert_equal(page_info_off.start_offset, page_info_idx.start_offset);
+ zassert_equal(page_info_off.size, page_info_idx.size);
+ zassert_equal(page_info_off.index, page_info_idx.index);
+
+ page_count = flash_get_page_count(flash_dev);
+ TC_PRINT("page_count=%d\n", (int)page_count);
+ zassert_true(page_count > 0, "flash_get_page_count returned %d", rc);
+ zassert_true(page_count >= page_info_off.index);
+
+ /* Test that callback is executed for every page */
+ test_cb_data.exit_page = page_count + 1;
+ flash_page_foreach(flash_dev, flash_callback, &test_cb_data);
+ zassert_true(page_count == test_cb_data.page_counter,
+ "page_count = %d not equal to pages counted with cb = %d", page_count,
+ test_cb_data.page_counter);
+
+ /* Test that callback can cancell iteration */
+ test_cb_data.page_counter = 0;
+ test_cb_data.exit_page = page_count >> 1;
+ flash_page_foreach(flash_dev, flash_callback, &test_cb_data);
+ zassert_true(test_cb_data.exit_page == test_cb_data.page_counter,
+ "%d pages were iterated while it shall stop on page %d",
+ test_cb_data.page_counter, test_cb_data.exit_page);
+}
ZTEST_SUITE(flash_driver, NULL, flash_driver_setup, NULL, NULL, NULL);
diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml
index 028383f..487c8cd 100644
--- a/tests/drivers/flash/common/testcase.yaml
+++ b/tests/drivers/flash/common/testcase.yaml
@@ -31,13 +31,15 @@
- nrf52840dk/nrf52840
drivers.flash.common.default:
filter: ((CONFIG_FLASH_HAS_DRIVER_ENABLED and not CONFIG_TRUSTED_EXECUTION_NONSECURE)
- and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions"))
+ and (dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")
+ or dt_label_with_parent_compat_enabled("storage_partition", "nordic,owned-partitions")))
integration_platforms:
- qemu_x86
- mimxrt1060_evk
drivers.flash.common.no_explicit_erase:
platform_allow:
- nrf54l15pdk/nrf54l15/cpuapp
+ - nrf54h20dk/nrf54h20/cpuapp
drivers.flash.common.tfm_ns:
build_only: true
filter: (CONFIG_FLASH_HAS_DRIVER_ENABLED and CONFIG_TRUSTED_EXECUTION_NONSECURE
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/da1469x_dk_pro.overlay b/tests/drivers/gpio/gpio_basic_api/boards/da1469x_dk_pro.overlay
new file mode 100644
index 0000000..c19e22c
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/da1469x_dk_pro.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ resources {
+ compatible = "test-gpio-basic-api";
+ out-gpios = <&gpio0 2 0>;
+ in-gpios = <&gpio0 3 0>;
+ };
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_devkitm.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_devkitm.overlay
deleted file mode 100644
index 6c4f3e2..0000000
--- a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_devkitm.overlay
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- resources {
- compatible = "test-gpio-basic-api";
- out-gpios = <&gpio0 4 0>;
- in-gpios = <&gpio0 5 0>;
- };
-};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index 6c4f3e2..0000000
--- a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- resources {
- compatible = "test-gpio-basic-api";
- out-gpios = <&gpio0 4 0>;
- in-gpios = <&gpio0 5 0>;
- };
-};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index 6c4f3e2..0000000
--- a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
- resources {
- compatible = "test-gpio-basic-api";
- out-gpios = <&gpio0 4 0>;
- in-gpios = <&gpio0 5 0>;
- };
-};
diff --git a/tests/drivers/gpio/gpio_basic_api/socs/esp32c2.overlay b/tests/drivers/gpio/gpio_basic_api/socs/esp32c2.overlay
new file mode 100644
index 0000000..0d16d4a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/socs/esp32c2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ resources {
+ compatible = "test-gpio-basic-api";
+ out-gpios = <&gpio0 2 0>;
+ in-gpios = <&gpio0 3 0>;
+ };
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/socs/esp32c3.overlay b/tests/drivers/gpio/gpio_basic_api/socs/esp32c3.overlay
new file mode 100644
index 0000000..313d947
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/socs/esp32c3.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ resources {
+ compatible = "test-gpio-basic-api";
+ out-gpios = <&gpio0 4 0>;
+ in-gpios = <&gpio0 5 0>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_api/Kconfig b/tests/drivers/i2c/i2c_api/Kconfig
new file mode 100644
index 0000000..f422302
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/Kconfig
@@ -0,0 +1,22 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "I2C API Test"
+
+source "Kconfig.zephyr"
+
+choice
+ prompt "Select GY271 Sensor Type"
+ default SENSOR_GY271_HMC
+
+ config SENSOR_GY271_HMC
+ bool "Use gy271 HMC type sensor"
+ help
+ Use to enable the use of gy271 HMC sensor
+
+ config SENSOR_GY271_QMC
+ bool "Use gy271 QMC type sensor"
+ help
+ Use to enable the use of gy271 QMC sensor
+
+endchoice
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.conf
new file mode 100644
index 0000000..83547b4
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.conf
@@ -0,0 +1 @@
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.overlay
new file mode 100644
index 0000000..63aa341
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1.overlay
@@ -0,0 +1,10 @@
+/ {
+ aliases {
+ i2c-0 = &iic1;
+ gy271 = &iic1;
+ };
+};
+
+&iic1 {
+ status = "okay";
+};
diff --git a/tests/drivers/i2c/i2c_api/src/test_i2c.c b/tests/drivers/i2c/i2c_api/src/test_i2c.c
index e9fa035..9ed4162 100644
--- a/tests/drivers/i2c/i2c_api/src/test_i2c.c
+++ b/tests/drivers/i2c/i2c_api/src/test_i2c.c
@@ -17,17 +17,28 @@
#include <zephyr/ztest.h>
#if DT_NODE_HAS_STATUS(DT_ALIAS(i2c_0), okay)
-#define I2C_DEV_NODE DT_ALIAS(i2c_0)
+#define I2C_DEV_NODE DT_ALIAS(i2c_0)
#elif DT_NODE_HAS_STATUS(DT_ALIAS(i2c_1), okay)
-#define I2C_DEV_NODE DT_ALIAS(i2c_1)
+#define I2C_DEV_NODE DT_ALIAS(i2c_1)
#elif DT_NODE_HAS_STATUS(DT_ALIAS(i2c_2), okay)
-#define I2C_DEV_NODE DT_ALIAS(i2c_2)
+#define I2C_DEV_NODE DT_ALIAS(i2c_2)
#else
#error "Please set the correct I2C device"
#endif
uint32_t i2c_cfg = I2C_SPEED_SET(I2C_SPEED_STANDARD) | I2C_MODE_CONTROLLER;
+#define GY271_HMC_ADDR (0x1E)
+#define GY271_QMC_ADDR (0x0D)
+
+#if defined(CONFIG_SENSOR_GY271_QMC)
+#define GY271_ADDR GY271_QMC_ADDR
+#elif defined(CONFIG_SENSOR_GY271_HMC)
+#define GY271_ADDR GY271_HMC_ADDR
+#else
+#error "No sensor type defined"
+#endif
+
static int test_gy271(void)
{
unsigned char datas[6];
@@ -55,26 +66,42 @@
return TC_FAIL;
}
+#ifdef CONFIG_SENSOR_GY271_QMC
+ datas[0] = 0x09;
+ datas[1] = 0x01;
+
+ if (i2c_write(i2c_dev, datas, 2, GY271_ADDR)) {
+ TC_PRINT("Fail to configure sensor GY271\n");
+ return TC_FAIL;
+ }
+#else /* GY271 HMC */
datas[0] = 0x01;
datas[1] = 0x20;
/* 3. verify i2c_write() */
- if (i2c_write(i2c_dev, datas, 2, 0x1E)) {
+ if (i2c_write(i2c_dev, datas, 2, GY271_ADDR)) {
TC_PRINT("Fail to configure sensor GY271\n");
return TC_FAIL;
}
datas[0] = 0x02;
datas[1] = 0x00;
- if (i2c_write(i2c_dev, datas, 2, 0x1E)) {
+ if (i2c_write(i2c_dev, datas, 2, GY271_ADDR)) {
TC_PRINT("Fail to configure sensor GY271\n");
return TC_FAIL;
}
+#endif
k_sleep(K_MSEC(1));
+#ifdef CONFIG_SENSOR_GY271_QMC
+ /* Sensor data bits start from 0x00 to 0x05 */
+ datas[0] = 0x00;
+#else /* GY271 HMC */
datas[0] = 0x03;
- if (i2c_write(i2c_dev, datas, 1, 0x1E)) {
+#endif
+
+ if (i2c_write(i2c_dev, datas, 1, GY271_ADDR)) {
TC_PRINT("Fail to write to sensor GY271\n");
return TC_FAIL;
}
@@ -82,14 +109,13 @@
(void)memset(datas, 0, sizeof(datas));
/* 4. verify i2c_read() */
- if (i2c_read(i2c_dev, datas, 6, 0x1E)) {
+ if (i2c_read(i2c_dev, datas, 6, GY271_ADDR)) {
TC_PRINT("Fail to fetch sample from sensor GY271\n");
return TC_FAIL;
}
- TC_PRINT("axis raw data: %d %d %d %d %d %d\n",
- datas[0], datas[1], datas[2],
- datas[3], datas[4], datas[5]);
+ TC_PRINT("axis raw data: %d %d %d %d %d %d\n", datas[0], datas[1], datas[2], datas[3],
+ datas[4], datas[5]);
return TC_PASS;
}
@@ -121,13 +147,21 @@
return TC_FAIL;
}
+#ifdef CONFIG_SENSOR_GY271_QMC
+ datas[0] = 0x09;
+ datas[1] = 0x01;
+
+ if (i2c_burst_write(i2c_dev, GY271_ADDR, 0x00, datas, 2)) {
+ TC_PRINT("Fail to configure sensor GY271 QMC\n");
+ }
+#else
datas[0] = 0x01;
datas[1] = 0x20;
datas[2] = 0x02;
datas[3] = 0x00;
/* 3. verify i2c_burst_write() */
- if (i2c_burst_write(i2c_dev, 0x1E, 0x00, datas, 4)) {
+ if (i2c_burst_write(i2c_dev, GY271_ADDR, 0x00, datas, 4)) {
TC_PRINT("Fail to write to sensor GY271\n");
return TC_FAIL;
}
@@ -135,16 +169,22 @@
k_sleep(K_MSEC(1));
(void)memset(datas, 0, sizeof(datas));
+#endif
+#ifdef CONFIG_SENSOR_GY271_QMC
+ /* Sensor data bits start from 0x00 to 0x05 */
+ int start_bit = 0x00;
+#else /* GY271 HMC */
+ int start_bit = 0x03;
+#endif
/* 4. verify i2c_burst_read() */
- if (i2c_burst_read(i2c_dev, 0x1E, 0x03, datas, 6)) {
+ if (i2c_burst_read(i2c_dev, GY271_ADDR, start_bit, datas, 6)) {
TC_PRINT("Fail to fetch sample from sensor GY271\n");
return TC_FAIL;
}
- TC_PRINT("axis raw data: %d %d %d %d %d %d\n",
- datas[0], datas[1], datas[2],
- datas[3], datas[4], datas[5]);
+ TC_PRINT("axis raw data: %d %d %d %d %d %d\n", datas[0], datas[1], datas[2], datas[3],
+ datas[4], datas[5]);
return TC_PASS;
}
diff --git a/tests/drivers/i2c/i2c_emul/CMakeLists.txt b/tests/drivers/i2c/i2c_emul/CMakeLists.txt
new file mode 100644
index 0000000..66030aa
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(i2c_emul)
+
+target_sources(app PRIVATE
+ src/emulated_target.cpp
+ src/test_fowarding_common.cpp
+)
+if(CONFIG_I2C_TARGET_BUFFER_MODE)
+ target_sources(app PRIVATE src/test_forwarding_buf.cpp)
+else()
+ target_sources(app PRIVATE src/test_forwarding_pio.cpp)
+endif()
+target_include_directories(app PRIVATE include)
diff --git a/tests/drivers/i2c/i2c_emul/boards/native_sim.buf.overlay b/tests/drivers/i2c/i2c_emul/boards/native_sim.buf.overlay
new file mode 100644
index 0000000..5133f59
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/boards/native_sim.buf.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2c1 {
+ target-buffered-mode;
+};
diff --git a/tests/drivers/i2c/i2c_emul/boards/native_sim.overlay b/tests/drivers/i2c/i2c_emul/boards/native_sim.overlay
new file mode 100644
index 0000000..e17f418
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/boards/native_sim.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ i2c1: i2c@400 {
+ status = "okay";
+ compatible = "zephyr,i2c-emul-controller";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #forward-cells = <1>;
+ reg = <0x400 4>;
+ };
+
+ i2c2: i2c@500 {
+ status = "okay";
+ compatible = "zephyr,i2c-emul-controller";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #forward-cells = <1>;
+ reg = <0x500 4>;
+ };
+};
+
+&i2c0 {
+ forwards = <&i2c1 0x20>, <&i2c2 0x24>;
+};
diff --git a/tests/drivers/i2c/i2c_emul/include/emulated_target.hpp b/tests/drivers/i2c/i2c_emul/include/emulated_target.hpp
new file mode 100644
index 0000000..f556c17
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/include/emulated_target.hpp
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _TESTS_DRIVERS_I2C_I2C_EMUL_INCLUDE_EMULATED_TARGET_H
+#define _TESTS_DRIVERS_I2C_I2C_EMUL_INCLUDE_EMULATED_TARGET_H
+
+#include <functional>
+
+#define CUSTOM_FFF_FUNCTION_TEMPLATE(RETURN, FUNCNAME, ...) \
+ std::function<RETURN(__VA_ARGS__)> FUNCNAME
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/fff.h>
+
+#define CONTROLLER_LABEL DT_NODELABEL(i2c0)
+#define TARGET_LABEL(n) DT_NODELABEL(DT_CAT(i2c, n))
+#define FORWARD_COUNT DT_PROP_LEN(CONTROLLER_LABEL, forwards)
+
+extern struct i2c_target_callbacks emulated_callbacks[FORWARD_COUNT];
+extern struct i2c_target_config emulated_target_config[FORWARD_COUNT];
+
+/* Declare all the fake functions needed */
+#define DECLARE_FAKE_TARGET_FUNCTIONS(node_id, prop, n) \
+ DECLARE_FAKE_VALUE_FUNC(int, target_read_requested_##n, struct i2c_target_config *, \
+ uint8_t *); \
+ DECLARE_FAKE_VALUE_FUNC(int, target_read_processed_##n, struct i2c_target_config *, \
+ uint8_t *); \
+ DECLARE_FAKE_VALUE_FUNC(int, target_write_requested_##n, struct i2c_target_config *); \
+ DECLARE_FAKE_VALUE_FUNC(int, target_write_received_##n, struct i2c_target_config *, \
+ uint8_t); \
+ DECLARE_FAKE_VALUE_FUNC(int, target_stop_##n, struct i2c_target_config *); \
+ DECLARE_FAKE_VALUE_FUNC(int, target_buf_read_requested_##n, struct i2c_target_config *, \
+ uint8_t **, uint32_t *) \
+ DECLARE_FAKE_VOID_FUNC(target_buf_write_received_##n, struct i2c_target_config *, \
+ uint8_t *, uint32_t)
+
+DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, DECLARE_FAKE_TARGET_FUNCTIONS)
+
+#define FFF_FAKE_ACTION(node_id, prop, n, fn) \
+ do { \
+ fn(target_read_requested_##n); \
+ fn(target_read_processed_##n); \
+ fn(target_write_requested_##n); \
+ fn(target_write_received_##n); \
+ fn(target_stop_##n); \
+ fn(target_buf_read_requested_##n); \
+ fn(target_buf_write_received_##n); \
+ } while (0);
+
+#define FFF_FAKES_LIST_FOREACH(fn) \
+ DT_FOREACH_PROP_ELEM_VARGS(CONTROLLER_LABEL, forwards, FFF_FAKE_ACTION, fn)
+
+#endif /* _TESTS_DRIVERS_I2C_I2C_EMUL_INCLUDE_EMULATED_TARGET_H */
diff --git a/tests/drivers/i2c/i2c_emul/prj.conf b/tests/drivers/i2c/i2c_emul/prj.conf
new file mode 100644
index 0000000..9c8d117
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2024 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ZTEST=y
+CONFIG_I2C=y
+CONFIG_I2C_TARGET=y
+CONFIG_EMUL=y
+
+CONFIG_CPP=y
+CONFIG_STD_CPP17=y
+CONFIG_REQUIRES_FULL_LIBCPP=y
diff --git a/tests/drivers/i2c/i2c_emul/src/emulated_target.cpp b/tests/drivers/i2c/i2c_emul/src/emulated_target.cpp
new file mode 100644
index 0000000..499942c
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/src/emulated_target.cpp
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "emulated_target.hpp"
+
+DEFINE_FFF_GLOBALS;
+
+#define DEFINE_FAKE_TARGET_FUNCTION(node_id, prop, n) \
+ DEFINE_FAKE_VALUE_FUNC(int, target_read_requested_##n, struct i2c_target_config *, \
+ uint8_t *); \
+ DEFINE_FAKE_VALUE_FUNC(int, target_read_processed_##n, struct i2c_target_config *, \
+ uint8_t *); \
+ DEFINE_FAKE_VALUE_FUNC(int, target_write_requested_##n, struct i2c_target_config *); \
+ DEFINE_FAKE_VALUE_FUNC(int, target_write_received_##n, struct i2c_target_config *, \
+ uint8_t); \
+ DEFINE_FAKE_VALUE_FUNC(int, target_stop_##n, struct i2c_target_config *); \
+ DEFINE_FAKE_VALUE_FUNC(int, target_buf_read_requested_##n, struct i2c_target_config *, \
+ uint8_t **, uint32_t *) \
+ DEFINE_FAKE_VOID_FUNC(target_buf_write_received_##n, struct i2c_target_config *, \
+ uint8_t *, uint32_t)
+
+DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, DEFINE_FAKE_TARGET_FUNCTION);
+
+/* clang-format off */
+#define DEFINE_EMULATED_CALLBACK(node_id, prop, n) \
+ [n] = { \
+ .write_requested = target_write_requested_##n, \
+ .read_requested = target_read_requested_##n, \
+ .write_received = target_write_received_##n, \
+ .read_processed = target_read_processed_##n, \
+ COND_CODE_1(CONFIG_I2C_TARGET_BUFFER_MODE, \
+ (.buf_write_received = target_buf_write_received_##n, ), ()) \
+ COND_CODE_1(CONFIG_I2C_TARGET_BUFFER_MODE, \
+ (.buf_read_requested = target_buf_read_requested_##n, ), ()) \
+ .stop = target_stop_##n, \
+ },
+/* clang-format on */
+
+struct i2c_target_callbacks emulated_callbacks[FORWARD_COUNT] = {
+ DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, DEFINE_EMULATED_CALLBACK)};
+
+#define DEFINE_EMULATED_TARGET_CONFIG(node_id, prop, n) \
+ [n] = { \
+ .flags = 0, \
+ .address = DT_PHA_BY_IDX(node_id, prop, n, addr), \
+ .callbacks = &emulated_callbacks[n], \
+ },
+
+struct i2c_target_config emulated_target_config[FORWARD_COUNT] = {
+ DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, DEFINE_EMULATED_TARGET_CONFIG)};
diff --git a/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp b/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp
new file mode 100644
index 0000000..b7201b2
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "emulated_target.hpp"
+#include <cstdint>
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+namespace
+{
+
+#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
+
+/* Get the devicetree constants */
+constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
+constexpr const struct device *targets[FORWARD_COUNT] = {
+ DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
+
+ZTEST(i2c_emul_forwarding, test_write_is_forwarded)
+{
+ uint8_t data[] = {0x00, 0x01, 0x02};
+
+ target_buf_write_received_0_fake.custom_fake = [&data](struct i2c_target_config *,
+ uint8_t *buf, uint32_t len) {
+ zassert_equal(ARRAY_SIZE(data), len);
+ zexpect_mem_equal(data, buf, len);
+ };
+
+ zassert_ok(
+ i2c_write(controller, data, ARRAY_SIZE(data), emulated_target_config[0].address));
+
+ // Expect 0 reads and 1 write/stop to be made
+ zexpect_equal(0, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(1, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(1, target_stop_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_read_is_forwarded)
+{
+ uint8_t expected[] = {0x01, 0x02, 0x03};
+ uint8_t data[ARRAY_SIZE(expected)] = {};
+
+ /* Set the custom fake function to a lambda which captures the expected value as a reference.
+ * This means that when the function is executed, we can access 'expected' as though it were
+ * within the lambda's scope.
+ */
+ target_buf_read_requested_0_fake.custom_fake = [&expected](struct i2c_target_config *,
+ uint8_t **ptr, uint32_t *len) {
+ *ptr = expected;
+ *len = ARRAY_SIZE(expected);
+ return 0;
+ };
+
+ zassert_ok(i2c_read(controller, data, ARRAY_SIZE(expected),
+ emulated_target_config[0].address));
+
+ // Expect 1 read/stop and 0 write to be made
+ zexpect_equal(1, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(1, target_stop_0_fake.call_count);
+ zexpect_mem_equal(expected, data, ARRAY_SIZE(expected));
+}
+
+ZTEST(i2c_emul_forwarding, test_failed_read_request)
+{
+ uint8_t data;
+ target_buf_read_requested_0_fake.return_val = -EINTR;
+
+ zassert_equal(-EINTR, i2c_read(controller, &data, 1, emulated_target_config[0].address));
+ zexpect_equal(1, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(0, target_stop_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_read_request_overflow)
+{
+ uint8_t data;
+
+ /* Set the custom_fake to a local lambda with no capture values. */
+ target_buf_read_requested_0_fake.custom_fake = [](struct i2c_target_config *, uint8_t **_,
+ uint32_t *len) {
+ *len = UINT32_MAX;
+ return 0;
+ };
+
+ zassert_equal(-ENOMEM, i2c_read(controller, &data, 1, emulated_target_config[0].address));
+ zexpect_equal(1, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(0, target_stop_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_transfer_is_forwarded)
+{
+ uint8_t write_data[1] = {};
+ uint8_t read_data[2] = {};
+
+ struct i2c_msg msgs[] = {
+ {
+ .buf = write_data,
+ .len = sizeof(write_data),
+ .flags = I2C_MSG_WRITE,
+ },
+ {
+ .buf = read_data,
+ .len = sizeof(read_data),
+ .flags = I2C_MSG_READ | I2C_MSG_STOP,
+ },
+ };
+
+ int phase = 0;
+ target_buf_write_received_0_fake.custom_fake = [&phase](struct i2c_target_config *,
+ uint8_t *, uint32_t) {
+ zassert_equal(0, phase,
+ "Expected a call to buf_write_received before anything else");
+ phase++;
+ };
+ target_buf_read_requested_0_fake.custom_fake = [&phase](struct i2c_target_config *,
+ uint8_t **ptr, uint32_t *len) {
+ zassert_equal(1, phase, "Expected a call to buf_Read_requested as the second step");
+ phase++;
+
+ // Write a random byte. It doesn't make a difference.
+ *ptr = (uint8_t *)&phase;
+ *len = 1;
+ return 0;
+ };
+ target_stop_0_fake.custom_fake = [&phase](struct i2c_target_config *) -> int {
+ zassert_equal(2, phase, "Expected a call to stop as the 3rd step");
+ phase++;
+ return 0;
+ };
+
+ zassert_ok(i2c_transfer(controller, msgs, ARRAY_SIZE(msgs),
+ emulated_target_config[0].address));
+ zexpect_equal(1, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(1, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(1, target_stop_0_fake.call_count);
+ zexpect_equal(3, phase, "Expected a total of 3 phases, but got %d", phase);
+}
+
+ZTEST(i2c_emul_forwarding, test_call_pio_forwarded_bus_when_buffering_enabled)
+{
+ uint8_t data[2];
+
+ zassert_ok(i2c_read(controller, data, ARRAY_SIZE(data), emulated_target_config[1].address));
+ zexpect_equal(1, target_read_requested_1_fake.call_count);
+ zexpect_equal(1, target_read_processed_1_fake.call_count);
+ zexpect_equal(1, target_stop_1_fake.call_count);
+}
+
+} // namespace
diff --git a/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp b/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp
new file mode 100644
index 0000000..aa40167
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "emulated_target.hpp"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+namespace
+{
+
+#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
+
+/* Get the devicetree constants */
+constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
+constexpr const struct device *targets[FORWARD_COUNT] = {
+ DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
+
+ZTEST(i2c_emul_forwarding, test_write_is_forwarded)
+{
+ // Try writing some values
+ for (uint8_t data = 0; data < 10; ++data) {
+ const int expected_call_count = 1 + data;
+
+ zassert_ok(i2c_write(controller, &data, sizeof(data),
+ emulated_target_config[0].address));
+
+ // Expected no reads to be made
+ zexpect_equal(0, target_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_read_processed_0_fake.call_count);
+
+ // Expected N write requests to be made
+ zexpect_equal(expected_call_count, target_write_requested_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_write_requested_0_fake.call_count);
+ zexpect_equal(expected_call_count, target_write_received_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_write_received_0_fake.call_count);
+
+ // Check that the data written was correct
+ zexpect_equal(data, target_write_received_0_fake.arg1_val,
+ "Expected data value %u. got %u", data,
+ target_write_received_0_fake.arg1_val);
+
+ // Expect 1 stop call per write request
+ zexpect_equal(expected_call_count, target_stop_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_stop_0_fake.call_count);
+ }
+}
+
+ZTEST(i2c_emul_forwarding, test_read_is_forwarded)
+{
+ // Try reading some values
+ for (uint8_t i = 0; i < 10; ++i) {
+ const uint8_t expected_data[2] = {
+ static_cast<uint8_t>(0x1 * i),
+ static_cast<uint8_t>(0x2 * i),
+ };
+ const unsigned int expected_call_count = 1 + i;
+ uint8_t data[2];
+
+ // Setup some lambdas to do the actual reads using 'expected_data'
+ target_read_requested_0_fake.custom_fake =
+ [expected_data](struct i2c_target_config *, uint8_t *out) -> int {
+ *out = expected_data[0];
+ return 0;
+ };
+ target_read_processed_0_fake.custom_fake =
+ [expected_data](struct i2c_target_config *, uint8_t *out) -> int {
+ *out = expected_data[1];
+ return 0;
+ };
+ zassert_ok(i2c_read(controller, data, sizeof(data),
+ emulated_target_config[0].address));
+
+ // Expect the read functions to be called N times
+ zexpect_equal(expected_call_count, target_read_requested_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_read_requested_0_fake.call_count);
+ zexpect_equal(expected_call_count, target_read_processed_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_read_processed_0_fake.call_count);
+
+ // Expect the data read to match
+ zexpect_equal(expected_data[0], data[0], "Expected 0x%02x, got 0x%02x",
+ expected_data[0], data[0]);
+ zexpect_equal(expected_data[1], data[1], "Expected 0x%02x, got 0x%02x",
+ expected_data[1], data[1]);
+
+ // Expect 0 write calls
+ zexpect_equal(0, target_write_requested_0_fake.call_count);
+ zexpect_equal(0, target_write_received_0_fake.call_count);
+
+ // Expect 1 stop call per read
+ zexpect_equal(expected_call_count, target_stop_0_fake.call_count,
+ "Expected to be called %d times, got %d", expected_call_count,
+ target_stop_0_fake.call_count);
+ }
+}
+
+ZTEST(i2c_emul_forwarding, test_recover_failed_write)
+{
+ uint8_t write_data[2];
+
+ // Fail on the write request (should never call the write_received function)
+ target_write_requested_0_fake.return_val = -EINVAL;
+ zassert_equal(-EINVAL, i2c_write(controller, write_data, sizeof(write_data),
+ emulated_target_config[0].address));
+ zexpect_equal(1, target_write_requested_0_fake.call_count, "Was called %d times",
+ target_write_requested_0_fake.call_count);
+ zexpect_equal(0, target_write_received_0_fake.call_count, "Was called %d times",
+ target_write_requested_0_fake.call_count);
+
+ // Next instruction should succeed
+ target_write_requested_0_fake.return_val = 0;
+ zassert_ok(i2c_write(controller, write_data, sizeof(write_data),
+ emulated_target_config[0].address));
+ zexpect_equal(2, target_write_requested_0_fake.call_count, "Was called %d times",
+ target_write_requested_0_fake.call_count);
+ zexpect_equal(2, target_write_received_0_fake.call_count, "Was called %d times",
+ target_write_requested_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_recover_failed_read)
+{
+ uint8_t read_data[2];
+
+ // Fail the read_requested (should never call the read_processed function)
+ target_read_requested_0_fake.return_val = -EINVAL;
+ zassert_equal(-EINVAL, i2c_read(controller, read_data, sizeof(read_data),
+ emulated_target_config[0].address));
+ zexpect_equal(1, target_read_requested_0_fake.call_count, "Was called %d times",
+ target_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_read_processed_0_fake.call_count, "Was called %d times",
+ target_read_processed_0_fake.call_count);
+
+ // Next instruction should pass
+ target_read_requested_0_fake.return_val = 0;
+ zassert_ok(i2c_read(controller, read_data, sizeof(read_data),
+ emulated_target_config[0].address));
+ zexpect_equal(2, target_read_requested_0_fake.call_count, "Was called %d times",
+ target_read_requested_0_fake.call_count);
+ zexpect_equal(1, target_read_processed_0_fake.call_count, "Was called %d times",
+ target_read_processed_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_transfer_is_forwarded)
+{
+ uint8_t write_data[1] = {};
+ uint8_t read_data[2] = {};
+
+ struct i2c_msg msgs[] = {
+ {
+ .buf = write_data,
+ .len = sizeof(write_data),
+ .flags = I2C_MSG_WRITE,
+ },
+ {
+ .buf = read_data,
+ .len = sizeof(read_data),
+ .flags = I2C_MSG_READ | I2C_MSG_STOP,
+ },
+ };
+
+ int phase = 0;
+ target_write_requested_0_fake.custom_fake = [&phase](struct i2c_target_config *) -> int {
+ zassert_equal(0, phase, "Expected a call to write_requested before anything else");
+ phase++;
+ return 0;
+ };
+ target_write_received_0_fake.custom_fake = [&phase](struct i2c_target_config *,
+ uint8_t) -> int {
+ zassert_equal(1, phase, "Expected a call to write_received as the second step");
+ phase++;
+ return 0;
+ };
+ target_read_requested_0_fake.custom_fake = [&phase](struct i2c_target_config *,
+ uint8_t *) -> int {
+ zassert_equal(2, phase, "Expected a call to read_requested as the 3rd step");
+ phase++;
+ return 0;
+ };
+ target_read_processed_0_fake.custom_fake = [&phase](struct i2c_target_config *,
+ uint8_t *) -> int {
+ zassert_equal(3, phase, "Expected a call to read_processed as the 4th step");
+ phase++;
+ return 0;
+ };
+ target_stop_0_fake.custom_fake = [&phase](struct i2c_target_config *) -> int {
+ zassert_equal(4, phase, "Expected a call to stop as the 5th step");
+ phase++;
+ return 0;
+ };
+ zassert_ok(i2c_transfer(controller, msgs, ARRAY_SIZE(msgs),
+ emulated_target_config[0].address));
+ zexpect_equal(1, target_write_requested_0_fake.call_count,
+ "Expected target_write_requested to be called once, but got %d",
+ target_write_requested_0_fake.call_count);
+ zexpect_equal(1, target_write_received_0_fake.call_count,
+ "Expected target_write_received to be called once, but got %d",
+ target_write_received_0_fake.call_count);
+ zexpect_equal(1, target_read_requested_0_fake.call_count,
+ "Expected target_read_requested to be called once, but got %d",
+ target_read_requested_0_fake.call_count);
+ zexpect_equal(1, target_read_processed_0_fake.call_count,
+ "Expected target_read_processed to be called once, but got %d",
+ target_read_processed_0_fake.call_count);
+ zexpect_equal(1, target_stop_0_fake.call_count,
+ "Expected target_stop to be called once, but got %d",
+ target_stop_0_fake.call_count);
+ zexpect_equal(5, phase, "Expected a total of 5 phases, but got %d", phase);
+}
+
+ZTEST(i2c_emul_forwarding, test_forward_two_targets)
+{
+ uint8_t read_data[2];
+
+ // Read the second forward and ensure that we only forwarded to the correct one
+ zassert_ok(i2c_read(controller, read_data, sizeof(read_data),
+ emulated_target_config[1].address));
+
+ // Check that we got the forward
+ zexpect_equal(1, target_read_requested_1_fake.call_count,
+ "Expected to be called 1 time, got %d",
+ target_read_requested_1_fake.call_count);
+ zexpect_equal(1, target_read_processed_1_fake.call_count,
+ "Expected to be called 1 time, got %d",
+ target_read_processed_1_fake.call_count);
+
+ // Check that we didn't forward to the first target
+ zexpect_equal(0, target_read_requested_0_fake.call_count,
+ "Expected to be called 0 times, got %d",
+ target_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_read_processed_0_fake.call_count,
+ "Expected to be called 0 times, got %d",
+ target_read_processed_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_error_in_write_received)
+{
+ uint8_t data;
+
+ target_write_received_0_fake.return_val = -EINTR;
+ zassert_equal(-EINTR, i2c_write(controller, &data, 1, emulated_target_config[0].address));
+ zexpect_equal(1, target_write_requested_0_fake.call_count);
+ zexpect_equal(1, target_write_received_0_fake.call_count);
+ zexpect_equal(0, target_stop_0_fake.call_count);
+}
+
+} // namespace
diff --git a/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp
new file mode 100644
index 0000000..0dc90b3
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2024 Google LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "emulated_target.hpp"
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+namespace
+{
+
+#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
+
+/* Get the devicetree constants */
+constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
+constexpr const struct device *targets[FORWARD_COUNT] = {
+ DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
+
+static void *i2c_emul_forwarding_setup(void)
+{
+ // Register the target
+ for (int i = 0; i < FORWARD_COUNT; ++i) {
+ zassert_ok(i2c_target_register(targets[i], &emulated_target_config[i]));
+ }
+
+ return NULL;
+}
+
+static void i2c_emul_forwarding_before(void *fixture)
+{
+ ARG_UNUSED(fixture);
+
+ // Reset all fakes
+ FFF_FAKES_LIST_FOREACH(RESET_FAKE);
+ FFF_RESET_HISTORY();
+}
+
+static void i2c_emul_forwarding_teardown(void *fixture)
+{
+ ARG_UNUSED(fixture);
+
+ // Unregister the I2C target callbacks
+ for (int i = 0; i < FORWARD_COUNT; ++i) {
+ zassert_ok(i2c_target_unregister(targets[i], &emulated_target_config[i]));
+ }
+}
+
+ZTEST_SUITE(i2c_emul_forwarding, NULL, i2c_emul_forwarding_setup, i2c_emul_forwarding_before, NULL,
+ i2c_emul_forwarding_teardown);
+
+/* Common tests */
+
+ZTEST(i2c_emul_forwarding, test_invalid_address_for_target)
+{
+ uint8_t data;
+ int rc = i2c_write(targets[0], &data, 1, emulated_target_config[0].address + 1);
+ zassert_equal(-EINVAL, rc, "Expected %d (-EINVAL), but got %d", -EINVAL, rc);
+ zexpect_equal(0, target_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_read_processed_0_fake.call_count);
+ zexpect_equal(0, target_write_requested_0_fake.call_count);
+ zexpect_equal(0, target_write_received_0_fake.call_count);
+ zexpect_equal(0, target_buf_write_received_0_fake.call_count);
+ zexpect_equal(0, target_buf_read_requested_0_fake.call_count);
+ zexpect_equal(0, target_stop_0_fake.call_count);
+}
+
+ZTEST(i2c_emul_forwarding, test_error_in_stop)
+{
+ uint8_t data;
+
+ target_stop_0_fake.return_val = -EINTR;
+ zassert_equal(-EINTR, i2c_write(controller, &data, 1, emulated_target_config[0].address));
+ zexpect_equal(1, target_stop_0_fake.call_count);
+}
+
+} // namespace
diff --git a/tests/drivers/i2c/i2c_emul/testcase.yaml b/tests/drivers/i2c/i2c_emul/testcase.yaml
new file mode 100644
index 0000000..3338100
--- /dev/null
+++ b/tests/drivers/i2c/i2c_emul/testcase.yaml
@@ -0,0 +1,17 @@
+# Copyright 2024 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+ drivers.i2c.emul.target_pio:
+ platform_allow:
+ - native_sim
+ extra_configs:
+ - CONFIG_I2C_TARGET_BUFFER_MODE=n
+ drivers.i2c.emul.target_buf:
+ platform_allow:
+ - native_sim
+ extra_configs:
+ - CONFIG_I2C_TARGET_BUFFER_MODE=y
+ extra_dtc_overlay_files:
+ - "boards/native_sim.overlay"
+ - "boards/native_sim.buf.overlay"
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.conf b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.conf
new file mode 100644
index 0000000..70e009f
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay
new file mode 100644
index 0000000..3eede13
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&pinctrl {
+ pinmux_flexcomm3_lpi2c: pinmux_flexcomm3_lpi2c {
+ group0 {
+ pinmux = <FC3_P0_PIO1_0>,
+ <FC3_P1_PIO1_1>;
+ slew-rate = "fast";
+ drive-strength = "low";
+ input-enable;
+ bias-pull-up;
+ drive-open-drain;
+ };
+ };
+};
+
+&flexcomm3 {
+ status = "okay";
+};
+
+/* We cannot enable SPI and I2C on the same flexcomm */
+&flexcomm3_lpspi3 {
+ status = "disabled";
+};
+
+/* To test this sample, connect
+ * LPI2C3 SCL(J2-12, P1_1/FC1_P1) --> LPI2C5 SCL(J2-20, P1_17/FC2_P1)
+ * LPI2C3 SDA(J2-8, P1_0/FC1_P0) --> LPI2C5 SDA(J2-18, P1_16/FC2_P0)
+ */
+&flexcomm3_lpi2c3 {
+ pinctrl-0 = <&pinmux_flexcomm3_lpi2c>;
+ pinctrl-names = "default";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+ status = "okay";
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ size = <1024>;
+ address-width = <16>;
+ };
+};
+
+&flexcomm5_lpi2c5 {
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ size = <1024>;
+ address-width = <16>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32655evkit_max32655_m4.overlay
index 8889210..d780787 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/max32655evkit_max32655_m4.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32655evkit_max32655_m4.overlay
@@ -18,6 +18,9 @@
pinctrl-0 = <&i2c1_scl_p0_16 &i2c1_sda_p0_17>;
pinctrl-names = "default";
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C1_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C1_RX>;
+ dma-names = "tx", "rx";
+
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.conf b/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.conf
new file mode 100644
index 0000000..c25d2c5
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.overlay
new file mode 100644
index 0000000..1f78e3a
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32662evkit.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2c0 {
+ status = "okay";
+ pinctrl-0 = <&i2c0a_scl_p0_12 &i2c0a_sda_p0_13>;
+ pinctrl-names = "default";
+
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ size = <256>;
+ };
+};
+
+&i2c1 {
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C1_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C1_RX>;
+ dma-names = "tx", "rx";
+
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ size = <256>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.conf b/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.conf
new file mode 100644
index 0000000..c25d2c5
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.overlay
new file mode 100644
index 0000000..c1f7c9a
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32666evkit_max32666_cpu0.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2c1 {
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ address-width = <16>;
+ size = <1024>;
+ };
+};
+
+&i2c2 {
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C2_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C2_RX>;
+ dma-names = "tx", "rx";
+
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ address-width = <16>;
+ size = <1024>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32670evkit.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32670evkit.overlay
index 299619f..1ac4176 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/max32670evkit.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32670evkit.overlay
@@ -18,6 +18,9 @@
pinctrl-0 = <&i2c1_scl_p0_12 &i2c1_sda_p0_13>;
pinctrl-names = "default";
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C1_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C1_RX>;
+ dma-names = "tx", "rx";
+
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32672evkit.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32672evkit.overlay
index 829fad6..c1f095f 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/max32672evkit.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32672evkit.overlay
@@ -18,6 +18,9 @@
pinctrl-0 = <&i2c1a_scl_p0_12 &i2c1a_sda_p0_13>;
pinctrl-names = "default";
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C1_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C1_RX>;
+ dma-names = "tx", "rx";
+
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.conf b/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.conf
new file mode 100644
index 0000000..7fc1aae
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.conf
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.overlay
new file mode 100644
index 0000000..59b1258
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32675evkit.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2c0 {
+ status = "okay";
+ pinctrl-0 = <&i2c0a_scl_p0_6 &i2c0a_sda_p0_7>;
+ pinctrl-names = "default";
+
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ address-width = <16>;
+ size = <1024>;
+ };
+};
+
+&i2c2 {
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C2_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C2_RX>;
+ dma-names = "tx", "rx";
+
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ address-width = <16>;
+ size = <1024>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32680evkit_max32680_m4.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32680evkit_max32680_m4.overlay
index 1b3d140..c8f95fd 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/max32680evkit_max32680_m4.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32680evkit_max32680_m4.overlay
@@ -14,6 +14,9 @@
};
&i2c1 {
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C1_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C1_RX>;
+ dma-names = "tx", "rx";
+
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/i2c/i2c_target_api/boards/max32690evkit_max32690_m4.overlay
index 9fc0e25..b62d4b1 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/max32690evkit_max32690_m4.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/max32690evkit_max32690_m4.overlay
@@ -18,6 +18,9 @@
pinctrl-0 = <&i2c2c_scl_p1_8 &i2c2c_sda_p1_7>;
pinctrl-names = "default";
+ dmas = <&dma0 1 MAX32_DMA_SLOT_I2C2_TX>, <&dma0 2 MAX32_DMA_SLOT_I2C2_RX>;
+ dma-names = "tx", "rx";
+
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 0000000..70e009f
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 0000000..f521284
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J41.12 <-> J44.20 and J41.10 <-> J44.18 */
+
+&lpi2c2 {
+ status = "okay";
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ size = <256>;
+ };
+};
+
+&lpi2c3 {
+ status = "okay";
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ size = <256>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 0000000..70e009f
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 0000000..f521284
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J41.12 <-> J44.20 and J41.10 <-> J44.18 */
+
+&lpi2c2 {
+ status = "okay";
+ eeprom0: eeprom@54 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x54>;
+ size = <256>;
+ };
+};
+
+&lpi2c3 {
+ status = "okay";
+ eeprom1: eeprom@56 {
+ compatible = "zephyr,i2c-target-eeprom";
+ reg = <0x56>;
+ size = <256>;
+ };
+};
diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml
index 34a6634..ec36886 100644
--- a/tests/drivers/i2c/i2c_target_api/testcase.yaml
+++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml
@@ -37,6 +37,17 @@
- frdm_mcxn947/mcxn947/cpu0
- mimxrt1170_evk@B/mimxrt1176/cm7
- mimxrt1170_evk/mimxrt1176/cm7
+ - mimxrt1180_evk/mimxrt1189/cm33
+ - mimxrt1180_evk/mimxrt1189/cm7
- mimxrt1040_evk
- mimxrt1060_evk
- frdm_ke17z512
+ - frdm_mcxn236
+ - max32655evkit/max32655/m4
+ - max32662evkit
+ - max32666evkit/max32666/cpu0
+ - max32670evkit
+ - max32672evkit
+ - max32675evkit
+ - max32680evkit/max32680/m4
+ - max32690evkit/max32690/m4
diff --git a/tests/drivers/pwm/pwm_api/boards/esp32c3_devkitm.overlay b/tests/drivers/pwm/pwm_api/boards/esp32c3_devkitm.overlay
deleted file mode 100644
index 409f7dc..0000000
--- a/tests/drivers/pwm/pwm_api/boards/esp32c3_devkitm.overlay
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- */
-
-#include <zephyr/dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- pwm-0 = &ledc0;
- };
-};
-
-&pinctrl {
- ledc0_default: ledc0_default {
- group1 {
- pinmux = <LEDC_CH0_GPIO2>;
- output-enable;
- };
- };
-};
-
-&ledc0 {
- pinctrl-0 = <&ledc0_default>;
- pinctrl-names = "default";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- channel0@0 {
- reg = <0x0>;
- timer = <0>;
- };
-};
diff --git a/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core.overlay b/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index 409f7dc..0000000
--- a/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- */
-
-#include <zephyr/dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- pwm-0 = &ledc0;
- };
-};
-
-&pinctrl {
- ledc0_default: ledc0_default {
- group1 {
- pinmux = <LEDC_CH0_GPIO2>;
- output-enable;
- };
- };
-};
-
-&ledc0 {
- pinctrl-0 = <&ledc0_default>;
- pinctrl-names = "default";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- channel0@0 {
- reg = <0x0>;
- timer = <0>;
- };
-};
diff --git a/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index 409f7dc..0000000
--- a/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- */
-
-#include <zephyr/dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- pwm-0 = &ledc0;
- };
-};
-
-&pinctrl {
- ledc0_default: ledc0_default {
- group1 {
- pinmux = <LEDC_CH0_GPIO2>;
- output-enable;
- };
- };
-};
-
-&ledc0 {
- pinctrl-0 = <&ledc0_default>;
- pinctrl-names = "default";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- channel0@0 {
- reg = <0x0>;
- timer = <0>;
- };
-};
diff --git a/tests/drivers/pwm/pwm_api/socs/esp32c3.overlay b/tests/drivers/pwm/pwm_api/socs/esp32c3.overlay
new file mode 100644
index 0000000..173073c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/socs/esp32c3.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases {
+ pwm-0 = &ledc0;
+ };
+};
+
+&pinctrl {
+ ledc0_default: ledc0_default {
+ group1 {
+ pinmux = <LEDC_CH0_GPIO2>;
+ output-enable;
+ };
+ };
+};
+
+&ledc0 {
+ pinctrl-0 = <&ledc0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel0@0 {
+ reg = <0x0>;
+ timer = <0>;
+ };
+};
diff --git a/tests/drivers/retained_mem/api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/retained_mem/api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
new file mode 100644
index 0000000..e304ecb
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/ {
+ cpuapp_sram@2002e000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ reg = <0x2002e000 DT_SIZE_K(4)>;
+ zephyr,memory-region = "RetainedMem";
+ status = "okay";
+
+ retainedmem0: retainedmem {
+ compatible = "zephyr,retained-ram";
+ status = "okay";
+ };
+ };
+
+ aliases {
+ retainedmemtestdevice = &retainedmem0;
+ };
+};
+
+&cpuapp_sram {
+ reg = <0x20000000 DT_SIZE_K(184)>;
+ ranges = <0x0 0x20000000 0x2e000>;
+};
diff --git a/tests/drivers/retained_mem/api/testcase.yaml b/tests/drivers/retained_mem/api/testcase.yaml
index d557160..7b23fd3 100644
--- a/tests/drivers/retained_mem/api/testcase.yaml
+++ b/tests/drivers/retained_mem/api/testcase.yaml
@@ -5,7 +5,7 @@
- drivers
- retained_mem
drivers.retained_mem.api.ram:
- platform_allow: qemu_cortex_m3
+ platform_allow: qemu_cortex_m3 nrf54l15pdk/nrf54l15/cpuapp
tags:
- drivers
- retained_mem
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf
new file mode 100644
index 0000000..a325815
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf
@@ -0,0 +1,7 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_MCUX_LPSPI_DMA=n
+CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay
new file mode 100644
index 0000000..0e47064
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect
+ * LPSPI3 MOSI(J2-8, P1_0/FC3_P0) --> LPSPI5 MISO(J2-10, P1_2/FC3_P2)
+ */
+&flexcomm3_lpspi3 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.conf b/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.conf
new file mode 100644
index 0000000..c8f823b
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.overlay
new file mode 100644
index 0000000..9fb3620
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32655evkit_max32655_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.conf b/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.conf
new file mode 100644
index 0000000..c8f823b
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.overlay b/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.overlay
new file mode 100644
index 0000000..fbfd7be
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32655fthr_max32655_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32662evkit.conf b/tests/drivers/spi/spi_loopback/boards/max32662evkit.conf
new file mode 100644
index 0000000..8318755
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32662evkit.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32662evkit.overlay b/tests/drivers/spi/spi_loopback/boards/max32662evkit.overlay
new file mode 100644
index 0000000..d713eed
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32662evkit.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Increase SRAM2 size to get enough space for image */
+&sram2 {
+ reg = <20008000 DT_SIZE_K(32)>;
+};
+
+&spi0 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.conf b/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.conf
new file mode 100644
index 0000000..c8f823b
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.overlay
new file mode 100644
index 0000000..fbfd7be
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32666fthr_max32666_cpu0.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32670evkit.conf b/tests/drivers/spi/spi_loopback/boards/max32670evkit.conf
new file mode 100644
index 0000000..b407e37
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32670evkit.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32670evkit.overlay b/tests/drivers/spi/spi_loopback/boards/max32670evkit.overlay
new file mode 100644
index 0000000..902eaa2
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32670evkit.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32672evkit.conf b/tests/drivers/spi/spi_loopback/boards/max32672evkit.conf
new file mode 100644
index 0000000..8318755
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32672evkit.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32672evkit.overlay b/tests/drivers/spi/spi_loopback/boards/max32672evkit.overlay
new file mode 100644
index 0000000..9cb8d2e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32672evkit.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32672fthr.conf b/tests/drivers/spi/spi_loopback/boards/max32672fthr.conf
new file mode 100644
index 0000000..8318755
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32672fthr.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32672fthr.overlay b/tests/drivers/spi/spi_loopback/boards/max32672fthr.overlay
new file mode 100644
index 0000000..9cb8d2e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32672fthr.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32675evkit.conf b/tests/drivers/spi/spi_loopback/boards/max32675evkit.conf
new file mode 100644
index 0000000..b407e37
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32675evkit.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32675evkit.overlay b/tests/drivers/spi/spi_loopback/boards/max32675evkit.overlay
new file mode 100644
index 0000000..9cb8d2e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32675evkit.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.conf b/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.conf
new file mode 100644
index 0000000..b407e37
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.overlay b/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.overlay
new file mode 100644
index 0000000..902eaa2
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max32680evkit_max32680_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+ slow@0 {
+ compatible = "test-spi-loopback-slow";
+ reg = <0>;
+ spi-max-frequency = <128000>;
+ };
+ fast@0 {
+ compatible = "test-spi-loopback-fast";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/spi/spi_loopback/boards/max32690evkit_max32690_m4.overlay
index f0b0214..902eaa2 100644
--- a/tests/drivers/spi/spi_loopback/boards/max32690evkit_max32690_m4.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/max32690evkit_max32690_m4.overlay
@@ -5,10 +5,6 @@
*/
&spi0 {
- status = "okay";
- pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29 &spi0b_ss1_p2_26>;
- pinctrl-names = "default";
-
slow@0 {
compatible = "test-spi-loopback-slow";
reg = <0>;
diff --git a/tests/drivers/tee/optee/boards/native_posix_64.overlay b/tests/drivers/tee/optee/boards/native_sim_64.overlay
similarity index 100%
rename from tests/drivers/tee/optee/boards/native_posix_64.overlay
rename to tests/drivers/tee/optee/boards/native_sim_64.overlay
diff --git a/tests/drivers/tee/optee/testcase.yaml b/tests/drivers/tee/optee/testcase.yaml
index ff7d592..c412b5a 100644
--- a/tests/drivers/tee/optee/testcase.yaml
+++ b/tests/drivers/tee/optee/testcase.yaml
@@ -9,6 +9,6 @@
- optee
timeout: 500
integration_platforms:
- - native_posix/native/64
+ - native_sim/native/64
platform_allow:
- - native_posix/native/64
+ - native_sim/native/64
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay
new file mode 100644
index 0000000..10121b5
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 1, 9)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 1, 10)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay
new file mode 100644
index 0000000..e73ba99
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 6, 1)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay
new file mode 100644
index 0000000..dbef642
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 3)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 2, 2)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay
new file mode 100644
index 0000000..dbef642
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 3)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 2, 2)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay
new file mode 100644
index 0000000..eafbefd
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci7_default: sci7_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
+ <RA_PSEL(RA_PSEL_SCI_7, 6, 14)>;
+ };
+ };
+};
+
+&sci7 {
+ pinctrl-0 = <&sci7_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay
new file mode 100644
index 0000000..eafbefd
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci7_default: sci7_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
+ <RA_PSEL(RA_PSEL_SCI_7, 6, 14)>;
+ };
+ };
+};
+
+&sci7 {
+ pinctrl-0 = <&sci7_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay
new file mode 100644
index 0000000..c80fe08
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 6, 1)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay
new file mode 100644
index 0000000..10121b5
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+ sci9_default: sci9_default {
+ group1 {
+ /* tx rx */
+ psels = <RA_PSEL(RA_PSEL_SCI_9, 1, 9)>,
+ <RA_PSEL(RA_PSEL_SCI_9, 1, 10)>;
+ };
+ };
+};
+
+&sci9 {
+ pinctrl-0 = <&sci9_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ dut: uart {
+ current-speed = <115200>;
+ status = "okay";
+ };
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/frdm_mcxn236.overlay b/tests/drivers/uart/uart_async_api/boards/frdm_mcxn236.overlay
new file mode 100644
index 0000000..910350c
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/frdm_mcxn236.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * To test this sample connect P4_2 to P4_3
+ */
+dut: &flexcomm2_lpuart2 {};
diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c3_devkitm.conf b/tests/drivers/uart/uart_async_api/socs/esp32c3.conf
similarity index 100%
rename from tests/drivers/uart/uart_async_api/boards/esp32c3_devkitm.conf
rename to tests/drivers/uart/uart_async_api/socs/esp32c3.conf
diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c3_devkitm.overlay b/tests/drivers/uart/uart_async_api/socs/esp32c3.overlay
similarity index 100%
rename from tests/drivers/uart/uart_async_api/boards/esp32c3_devkitm.overlay
rename to tests/drivers/uart/uart_async_api/socs/esp32c3.overlay
diff --git a/tests/drivers/udc/src/main.c b/tests/drivers/udc/src/main.c
index 64298b1..66bf469 100644
--- a/tests/drivers/udc/src/main.c
+++ b/tests/drivers/udc/src/main.c
@@ -6,6 +6,7 @@
#include <zephyr/ztest.h>
#include <zephyr/drivers/usb/udc.h>
+#include <zephyr/sys/byteorder.h>
#include <zephyr/usb/usb_ch9.h>
#include <zephyr/logging/log.h>
@@ -95,7 +96,7 @@
static void test_udc_ep_try_config(const struct device *dev,
struct usb_ep_descriptor *ed)
{
- uint16_t mps = ed->wMaxPacketSize;
+ uint16_t mps = sys_le16_to_cpu(ed->wMaxPacketSize);
int err;
err = udc_ep_try_config(dev, ed->bEndpointAddress,
@@ -129,13 +130,17 @@
int err1, err2, err3, err4;
err1 = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ ed->bInterval);
err2 = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ ed->bInterval);
err3 = udc_ep_enable(dev, FALSE_EP_ADDR, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ ed->bInterval);
err4 = udc_ep_enable(dev, ctrl_ep, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ ed->bInterval);
if (!udc_is_initialized(dev) && !udc_is_enabled(dev)) {
zassert_equal(err1, -EPERM, "Not failed to enable endpoint");
@@ -192,7 +197,7 @@
struct net_buf *buf;
buf = udc_ep_buf_alloc(dev, ed->bEndpointAddress,
- ed->wMaxPacketSize);
+ USB_MPS_TO_TPL(sys_le16_to_cpu(ed->wMaxPacketSize)));
zassert_not_null(buf, "Failed to allocate request");
@@ -326,13 +331,14 @@
for (int i = 0; i < num_of_iterations; i++) {
err = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
- ed->wMaxPacketSize, ed->bInterval);
+ sys_le16_to_cpu(ed->wMaxPacketSize),
+ ed->bInterval);
zassert_ok(err, "Failed to enable endpoint");
/* It needs a little reserve for memory management overhead. */
for (int n = 0; n < (CONFIG_UDC_BUF_COUNT - 4); n++) {
buf = udc_ep_buf_alloc(dev, ed->bEndpointAddress,
- ed->wMaxPacketSize);
+ USB_MPS_TO_TPL(sys_le16_to_cpu(ed->wMaxPacketSize)));
zassert_not_null(buf,
"Failed to allocate request (%d) for 0x%02x",
n, ed->bEndpointAddress);
@@ -362,7 +368,7 @@
.bDescriptorType = USB_DESC_ENDPOINT,
.bEndpointAddress = 0x01,
.bmAttributes = type,
- .wMaxPacketSize = 0,
+ .wMaxPacketSize = sys_cpu_to_le16(0),
.bInterval = 0,
};
const struct device *dev;
@@ -399,7 +405,7 @@
continue;
}
- ed.wMaxPacketSize = mps[i];
+ ed.wMaxPacketSize = sys_cpu_to_le16(mps[i]);
test_udc_ep_api(dev, &ed);
ed.bEndpointAddress |= USB_EP_DIR_IN;
@@ -440,7 +446,7 @@
.bDescriptorType = USB_DESC_ENDPOINT,
.bEndpointAddress = USB_CONTROL_EP_OUT,
.bmAttributes = USB_EP_TYPE_CONTROL,
- .wMaxPacketSize = 64,
+ .wMaxPacketSize = sys_cpu_to_le16(64),
.bInterval = 0,
};
@@ -449,7 +455,7 @@
.bDescriptorType = USB_DESC_ENDPOINT,
.bEndpointAddress = USB_CONTROL_EP_IN,
.bmAttributes = USB_EP_TYPE_CONTROL,
- .wMaxPacketSize = 64,
+ .wMaxPacketSize = sys_cpu_to_le16(64),
.bInterval = 0,
};
@@ -458,7 +464,7 @@
.bDescriptorType = USB_DESC_ENDPOINT,
.bEndpointAddress = 0x01,
.bmAttributes = USB_EP_TYPE_BULK,
- .wMaxPacketSize = 64,
+ .wMaxPacketSize = sys_cpu_to_le16(64),
.bInterval = 0,
};
@@ -467,7 +473,7 @@
.bDescriptorType = USB_DESC_ENDPOINT,
.bEndpointAddress = 0x81,
.bmAttributes = USB_EP_TYPE_BULK,
- .wMaxPacketSize = 64,
+ .wMaxPacketSize = sys_cpu_to_le16(64),
.bInterval = 0,
};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay
new file mode 100644
index 0000000..94e0d71
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+ status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay
new file mode 100644
index 0000000..94e0d71
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+ status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
index a92e54e..3166176 100644
--- a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
+++ b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
@@ -107,7 +107,7 @@
#define WDT_TEST_MAX_WINDOW 200U
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(raspberrypi_pico_watchdog)
-#define WDT_TEST_MAX_WINDOW 20000U
+#define WDT_TEST_MAX_WINDOW 8000U
#define TIMEOUTS 0
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(intel_tco_wdt)
diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay
new file mode 100644
index 0000000..d540137
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+ status = "okay";
+};
+
+&wdt011 {
+ status = "disabled";
+};
+
+&wdt131 {
+ status = "disabled";
+};
+
+&wdt132 {
+ status = "disabled";
+};
diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay
new file mode 100644
index 0000000..7793fed
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+ status = "disabled";
+};
+
+&wdt011 {
+ status = "okay";
+};
+
+&wdt131 {
+ status = "disabled";
+};
+
+&wdt132 {
+ status = "disabled";
+};
diff --git a/tests/drivers/watchdog/wdt_error_cases/src/main.c b/tests/drivers/watchdog/wdt_error_cases/src/main.c
index b16dacc..c1adc43 100644
--- a/tests/drivers/watchdog/wdt_error_cases/src/main.c
+++ b/tests/drivers/watchdog/wdt_error_cases/src/main.c
@@ -42,7 +42,7 @@
#define DEFAULT_WINDOW_MIN (0U)
/* Align tests to the specific target: */
-#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20)
+#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
#define WDT_TEST_FLAGS \
(WDT_DISABLE_SUPPORTED | WDT_FLAG_RESET_SOC_SUPPORTED | \
WDT_FLAG_ONLY_ONE_TIMEOUT_VALUE_SUPPORTED | WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED | \
diff --git a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
index 4fdbfaa..738008c 100644
--- a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
+++ b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
@@ -11,5 +11,7 @@
- nrf54l15pdk/nrf54l15/cpuapp
- nrf54h20dk/nrf54h20/cpuapp
- nrf54h20dk/nrf54h20/cpurad
+ - nrf9280pdk/nrf9280/cpuapp
+ - nrf9280pdk/nrf9280/cpurad
integration_platforms:
- nrf54l15pdk/nrf54l15/cpuapp
diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c
index 516ddb1..d8ce8fc 100644
--- a/tests/kernel/context/src/main.c
+++ b/tests/kernel/context/src/main.c
@@ -57,7 +57,7 @@
#elif defined(CONFIG_SPARC)
#elif defined(CONFIG_MIPS)
#elif defined(CONFIG_ARCH_POSIX)
-#if defined(CONFIG_BOARD_NATIVE_POSIX)
+#if defined(CONFIG_BOARD_NATIVE_POSIX) || defined(CONFIG_BOARD_NATIVE_SIM)
#define TICK_IRQ TIMER_TICK_IRQ
#else
/*
diff --git a/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.conf b/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.conf
new file mode 100644
index 0000000..198a2a5
--- /dev/null
+++ b/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.conf
@@ -0,0 +1 @@
+CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=0
diff --git a/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.overlay b/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.overlay
new file mode 100644
index 0000000..f1be3ed
--- /dev/null
+++ b/tests/kernel/mem_protect/userspace/boards/frdm_mcxn236.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&sramx {
+ status = "disabled";
+};
diff --git a/tests/kernel/threads/thread_apis/src/main.c b/tests/kernel/threads/thread_apis/src/main.c
index 28e1bc2..162f85e 100644
--- a/tests/kernel/threads/thread_apis/src/main.c
+++ b/tests/kernel/threads/thread_apis/src/main.c
@@ -636,7 +636,7 @@
large_stack(&b);
/* FIXME: Ideally, the follow condition will assert true:
* (a - b) == INT_ARRAY_SIZE * sizeof(int)
- * but it is not the case in native_posix, qemu_leon3 and
+ * but it is not the case in native_sim, qemu_leon3 and
* qemu_cortex_a53. Relax check condition here
*/
zassert_true(b <= a);
diff --git a/tests/lib/c_lib/common/src/main.c b/tests/lib/c_lib/common/src/main.c
index 4380b2c..f7db63c 100644
--- a/tests/lib/c_lib/common/src/main.c
+++ b/tests/lib/c_lib/common/src/main.c
@@ -22,6 +22,7 @@
#include <zephyr/kernel.h>
#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
#include <zephyr/ztest.h>
#include <limits.h>
@@ -1075,7 +1076,7 @@
*
* @see gmtime(),gmtime_r().
*/
-ZTEST(libc_common, test_time)
+ZTEST(libc_common, test_time_gmtime)
{
time_t tests1 = 0;
time_t tests2 = -5;
@@ -1093,6 +1094,86 @@
}
/**
+ * @brief Test time function
+ *
+ * @see asctime(), asctime_r().
+ */
+ZTEST(libc_common, test_time_asctime)
+{
+ char buf[26] = {0};
+ struct tm tp = {
+ .tm_sec = 10, /* Seconds */
+ .tm_min = 30, /* Minutes */
+ .tm_hour = 14, /* Hour (24-hour format) */
+ .tm_wday = 5, /* Day of the week (0-6, 0 = Sun) */
+ .tm_mday = 1, /* Day of the month */
+ .tm_mon = 5, /* Month (0-11, January = 0) */
+ .tm_year = 124, /* Year (current year - 1900) */
+ };
+
+ zassert_not_null(asctime_r(&tp, buf));
+ zassert_equal(strncmp("Fri Jun 1 14:30:10 2024\n", buf, sizeof(buf)), 0);
+
+ zassert_not_null(asctime(&tp));
+ zassert_equal(strncmp("Fri Jun 1 14:30:10 2024\n", asctime(&tp), sizeof(buf)), 0);
+
+ if (IS_ENABLED(CONFIG_COMMON_LIBC_ASCTIME_R)) {
+ zassert_is_null(asctime_r(NULL, buf));
+ zassert_is_null(asctime(NULL));
+
+ zassert_is_null(asctime_r(&tp, NULL));
+
+ tp.tm_wday = 8;
+ zassert_is_null(asctime_r(&tp, buf));
+ zassert_is_null(asctime(&tp));
+
+ tp.tm_wday = 5;
+ tp.tm_mon = 12;
+ zassert_is_null(asctime_r(&tp, buf));
+ zassert_is_null(asctime(&tp));
+ }
+}
+
+/**
+ * @brief Test time function
+ *
+ * @see localtime(), localtime_r().
+ */
+ZTEST(libc_common, test_time_localtime)
+{
+ time_t tests1 = 0;
+ time_t tests2 = -5;
+ time_t tests3 = (time_t) -214748364800;
+ time_t tests4 = 951868800;
+
+ struct tm tp;
+
+ zassert_not_null(localtime(&tests1), "localtime failed");
+ zassert_not_null(localtime(&tests2), "localtime failed");
+
+ tp.tm_wday = -5;
+ zassert_not_null(localtime_r(&tests3, &tp), "localtime_r failed");
+ zassert_not_null(localtime_r(&tests4, &tp), "localtime_r failed");
+}
+
+/**
+ * @brief Test time function
+ *
+ * @see ctime(), ctime_r().
+ */
+ZTEST(libc_common, test_time_ctime)
+{
+ char buf[26] = {0};
+ time_t test1 = 1718260000;
+
+ zassert_not_null(ctime_r(&test1, buf));
+ zassert_equal(strncmp("Thu Jun 13 06:26:40 2024\n", buf, sizeof(buf)), 0);
+
+ zassert_not_null(ctime(&test1));
+ zassert_equal(strncmp("Thu Jun 13 06:26:40 2024\n", ctime(&test1), sizeof(buf)), 0);
+}
+
+/**
*
* @brief Test rand function
*
diff --git a/tests/lib/c_lib/common/testcase.yaml b/tests/lib/c_lib/common/testcase.yaml
index 4d184b9..40a33af 100644
--- a/tests/lib/c_lib/common/testcase.yaml
+++ b/tests/lib/c_lib/common/testcase.yaml
@@ -13,6 +13,8 @@
- CONFIG_MINIMAL_LIBC=y
- CONFIG_MINIMAL_LIBC_NON_REENTRANT_FUNCTIONS=y
- CONFIG_MINIMAL_LIBC_RAND=y
+ - CONFIG_COMMON_LIBC_ASCTIME_R=y
+ - CONFIG_COMMON_LIBC_CTIME_R=y
libraries.libc.common.newlib:
filter: CONFIG_NEWLIB_LIBC_SUPPORTED
min_ram: 32
diff --git a/tests/lib/c_lib/stdio/CMakeLists.txt b/tests/lib/c_lib/stdio/CMakeLists.txt
new file mode 100644
index 0000000..c2b9d4c
--- /dev/null
+++ b/tests/lib/c_lib/stdio/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stdio)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/lib/c_lib/stdio/app.overlay b/tests/lib/c_lib/stdio/app.overlay
new file mode 100644
index 0000000..80f9a8b
--- /dev/null
+++ b/tests/lib/c_lib/stdio/app.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Linumiz
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ ramdisk0 {
+ compatible = "zephyr,ram-disk";
+ disk-name = "RAM";
+ sector-size = <512>;
+ sector-count = <160>;
+ };
+};
diff --git a/tests/lib/c_lib/stdio/prj.conf b/tests/lib/c_lib/stdio/prj.conf
new file mode 100644
index 0000000..10eb46e
--- /dev/null
+++ b/tests/lib/c_lib/stdio/prj.conf
@@ -0,0 +1,6 @@
+CONFIG_ZTEST=y
+CONFIG_TEST_USERSPACE=y
+CONFIG_ZTEST_FATAL_HOOK=y
+CONFIG_MINIMAL_LIBC=y
+CONFIG_FILE_SYSTEM=y
+CONFIG_FAT_FILESYSTEM_ELM=y
diff --git a/tests/lib/c_lib/stdio/src/main.c b/tests/lib/c_lib/stdio/src/main.c
new file mode 100644
index 0000000..2bafdd2
--- /dev/null
+++ b/tests/lib/c_lib/stdio/src/main.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Linumiz
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_error_hook.h>
+#include <ff.h>
+#include <zephyr/fs/fs.h>
+
+#define FATFS_MNTP "/RAM:"
+#define TEST_FILE FATFS_MNTP"/testfile.txt"
+
+static FATFS fat_fs;
+
+static struct fs_mount_t fatfs_mnt = {
+ .type = FS_FATFS,
+ .mnt_point = FATFS_MNTP,
+ .fs_data = &fat_fs,
+};
+
+ZTEST_SUITE(libc_stdio, NULL, NULL, NULL, NULL, NULL);
+
+/**
+ * @brief Test for remove API
+ *
+ * @details Test deletes a file through remove API.
+ */
+ZTEST(libc_stdio, test_remove)
+{
+ struct fs_file_t file;
+
+ fs_file_t_init(&file);
+
+ zassert_ok(fs_mount(&fatfs_mnt), "Error in mount file system\n");
+ zassert_equal(fs_open(&file, TEST_FILE, FS_O_CREATE), 0,
+ "Error creating file\n");
+ zassert_ok(fs_close(&file), "Error closing file\n");
+ zassert_ok(remove(TEST_FILE), "Error removing file: %d\n", errno);
+ zassert_equal(remove(""), -1, "Error Invalid path removed\n");
+ zassert_equal(remove(NULL), -1, "Error Invalid path removed\n");
+ zassert_ok(fs_unmount(&fatfs_mnt), "Error while unmount file system\n");
+}
diff --git a/tests/lib/c_lib/stdio/testcase.yaml b/tests/lib/c_lib/stdio/testcase.yaml
new file mode 100644
index 0000000..e5872fd
--- /dev/null
+++ b/tests/lib/c_lib/stdio/testcase.yaml
@@ -0,0 +1,21 @@
+common:
+ tags:
+ - clib
+ min_ram: 128
+ filter: not CONFIG_NATIVE_LIBC
+tests:
+ libraries.libc.common.stdio.minimal:
+ tags: minimal_libc
+ filter: CONFIG_MINIMAL_LIBC_SUPPORTED
+ extra_configs:
+ - CONFIG_MINIMAL_LIBC=y
+ libraries.libc.common.stdio.picolibc:
+ tags: picolibc
+ filter: CONFIG_PICOLIBC_SUPPORTED
+ extra_configs:
+ - CONFIG_PICOLIBC=y
+ libraries.libc.common.stdio.newlib:
+ tags: newlib
+ filter: TOOLCHAIN_HAS_NEWLIB == 1
+ extra_configs:
+ - CONFIG_NEWLIB_LIBC=y
diff --git a/tests/lib/cpp/cxx/src/main.cpp b/tests/lib/cpp/cxx/src/main.cpp
index 8b14929..1f6864a 100644
--- a/tests/lib/cpp/cxx/src/main.cpp
+++ b/tests/lib/cpp/cxx/src/main.cpp
@@ -99,7 +99,7 @@
/* Check that BUILD_ASSERT compiles. */
BUILD_ASSERT(sizeof(foo) == sizeof(int));
-static struct foo foos[5];
+__maybe_unused static struct foo foos[5];
/* Check that ARRAY_SIZE compiles. */
BUILD_ASSERT(ARRAY_SIZE(foos) == 5, "expected 5 elements");
diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml
index cac167d..e3b7628 100644
--- a/tests/lib/cpp/cxx/testcase.yaml
+++ b/tests/lib/cpp/cxx/testcase.yaml
@@ -34,13 +34,15 @@
# -std=c++98)
cpp.main.cpp98:
arch_exclude: posix
- # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98.
- # Exclude EK_RA8M1 as Renesas RA HAL is not compatible with C++98.
+ # Exclude nRF54L15, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98.
+ # Exclude CONFIG_HAS_RENESAS_RA_FSP as Renesas RA HAL is not compatible with C++98.
platform_exclude:
- nrf54l15pdk/nrf54l15/cpuapp
- nrf54h20dk/nrf54h20/cpuapp
- nrf54h20dk/nrf54h20/cpurad
- - ek_ra8m1
+ - nrf9280pdk/nrf9280/cpuapp
+ - nrf9280pdk/nrf9280/cpurad
+ filter: not CONFIG_HAS_RENESAS_RA_FSP
build_only: true
extra_configs:
- CONFIG_STD_CPP98=y
diff --git a/tests/lib/json/prj.conf b/tests/lib/json/prj.conf
index 700ea22..4a6c852 100644
--- a/tests/lib/json/prj.conf
+++ b/tests/lib/json/prj.conf
@@ -1,3 +1,3 @@
CONFIG_JSON_LIBRARY=y
CONFIG_ZTEST=y
-CONFIG_ZTEST_STACK_SIZE=2048
+CONFIG_ZTEST_STACK_SIZE=3072
diff --git a/tests/lib/json/src/main.c b/tests/lib/json/src/main.c
index b1b4884..ae142f8 100644
--- a/tests/lib/json/src/main.c
+++ b/tests/lib/json/src/main.c
@@ -13,12 +13,15 @@
int nested_int;
bool nested_bool;
const char *nested_string;
+ int64_t nested_int64;
};
struct test_struct {
const char *some_string;
int some_int;
bool some_bool;
+ int64_t some_int64;
+ int64_t another_int64;
struct test_nested some_nested_struct;
int some_array[16];
size_t some_array_len;
@@ -45,6 +48,9 @@
int int_max;
int int_cero;
int int_min;
+ int64_t int64_max;
+ int64_t int64_cero;
+ int64_t int64_min;
};
static const struct json_obj_descr nested_descr[] = {
@@ -52,12 +58,18 @@
JSON_OBJ_DESCR_PRIM(struct test_nested, nested_bool, JSON_TOK_TRUE),
JSON_OBJ_DESCR_PRIM(struct test_nested, nested_string,
JSON_TOK_STRING),
+ JSON_OBJ_DESCR_PRIM(struct test_nested, nested_int64,
+ JSON_TOK_INT64),
};
static const struct json_obj_descr test_descr[] = {
JSON_OBJ_DESCR_PRIM(struct test_struct, some_string, JSON_TOK_STRING),
JSON_OBJ_DESCR_PRIM(struct test_struct, some_int, JSON_TOK_NUMBER),
JSON_OBJ_DESCR_PRIM(struct test_struct, some_bool, JSON_TOK_TRUE),
+ JSON_OBJ_DESCR_PRIM(struct test_struct, some_int64,
+ JSON_TOK_INT64),
+ JSON_OBJ_DESCR_PRIM(struct test_struct, another_int64,
+ JSON_TOK_INT64),
JSON_OBJ_DESCR_OBJECT(struct test_struct, some_nested_struct,
nested_descr),
JSON_OBJ_DESCR_ARRAY(struct test_struct, some_array,
@@ -89,6 +101,9 @@
JSON_OBJ_DESCR_PRIM(struct test_int_limits, int_max, JSON_TOK_NUMBER),
JSON_OBJ_DESCR_PRIM(struct test_int_limits, int_cero, JSON_TOK_NUMBER),
JSON_OBJ_DESCR_PRIM(struct test_int_limits, int_min, JSON_TOK_NUMBER),
+ JSON_OBJ_DESCR_PRIM(struct test_int_limits, int64_max, JSON_TOK_INT64),
+ JSON_OBJ_DESCR_PRIM(struct test_int_limits, int64_cero, JSON_TOK_INT64),
+ JSON_OBJ_DESCR_PRIM(struct test_int_limits, int64_min, JSON_TOK_INT64),
};
struct array {
@@ -180,11 +195,14 @@
struct test_struct ts = {
.some_string = "zephyr 123\uABCD",
.some_int = 42,
+ .some_int64 = 1152921504606846977,
+ .another_int64 = -2305843009213693937,
.some_bool = true,
.some_nested_struct = {
.nested_int = -1234,
.nested_bool = false,
- .nested_string = "this should be escaped: \t"
+ .nested_string = "this should be escaped: \t",
+ .nested_int64 = 4503599627370496,
},
.some_array[0] = 1,
.some_array[1] = 4,
@@ -203,6 +221,7 @@
.nested_int = 1234,
.nested_bool = true,
.nested_string = "no escape necessary",
+ .nested_int64 = 4503599627370496,
},
.nested_obj_array = {
{1, true, "true"},
@@ -212,19 +231,23 @@
};
char encoded[] = "{\"some_string\":\"zephyr 123\uABCD\","
"\"some_int\":42,\"some_bool\":true,"
+ "\"some_int64\":1152921504606846977,"
+ "\"another_int64\":-2305843009213693937,"
"\"some_nested_struct\":{\"nested_int\":-1234,"
"\"nested_bool\":false,\"nested_string\":"
- "\"this should be escaped: \\t\"},"
+ "\"this should be escaped: \\t\","
+ "\"nested_int64\":4503599627370496},"
"\"some_array\":[1,4,8,16,32],"
"\"another_b!@l\":true,"
"\"if\":false,"
"\"another-array\":[2,3,5,7],"
"\"4nother_ne$+\":{\"nested_int\":1234,"
"\"nested_bool\":true,"
- "\"nested_string\":\"no escape necessary\"},"
+ "\"nested_string\":\"no escape necessary\","
+ "\"nested_int64\":4503599627370496},"
"\"nested_obj_array\":["
- "{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\"},"
- "{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\"}]"
+ "{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\",\"nested_int64\":0},"
+ "{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\",\"nested_int64\":0}]"
"}";
char buffer[sizeof(encoded)];
int ret;
@@ -249,10 +272,13 @@
"\"some_bool\":true \t "
"\n"
"\r ,"
+ "\"some_int64\":-4611686018427387904,"
+ "\"another_int64\":-2147483648,"
"\"some_nested_struct\":{ "
"\"nested_int\":-1234,\n\n"
"\"nested_bool\":false,\t"
"\"nested_string\":\"this should be escaped: \\t\","
+ "\"nested_int64\":9223372036854775807,"
"\"extra_nested_array\":[0,-1]},"
"\"extra_struct\":{\"nested_bool\":false},"
"\"extra_bool\":true,"
@@ -262,7 +288,8 @@
"\"another-array\":[2,3,5,7],"
"\"4nother_ne$+\":{\"nested_int\":1234,"
"\"nested_bool\":true,"
- "\"nested_string\":\"no escape necessary\"},"
+ "\"nested_string\":\"no escape necessary\","
+ "\"nested_int64\":-9223372036854775806},"
"\"nested_obj_array\":["
"{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\"},"
"{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\"}]"
@@ -281,8 +308,14 @@
"String not decoded correctly");
zassert_equal(ts.some_int, 42, "Positive integer not decoded correctly");
zassert_equal(ts.some_bool, true, "Boolean not decoded correctly");
+ zassert_equal(ts.some_int64, -4611686018427387904,
+ "int64 not decoded correctly");
+ zassert_equal(ts.another_int64, -2147483648,
+ "int64 not decoded correctly");
zassert_equal(ts.some_nested_struct.nested_int, -1234,
"Nested negative integer not decoded correctly");
+ zassert_equal(ts.some_nested_struct.nested_int64, 9223372036854775807,
+ "Nested int64 not decoded correctly");
zassert_equal(ts.some_nested_struct.nested_bool, false,
"Nested boolean value not decoded correctly");
zassert_str_equal(ts.some_nested_struct.nested_string,
@@ -304,6 +337,8 @@
"Decoded named array not with expected values");
zassert_equal(ts.xnother_nexx.nested_int, 1234,
"Named nested integer not decoded correctly");
+ zassert_equal(ts.xnother_nexx.nested_int64, -9223372036854775806,
+ "Named nested int64 not decoded correctly");
zassert_equal(ts.xnother_nexx.nested_bool, true,
"Named nested boolean not decoded correctly");
zassert_str_equal(ts.xnother_nexx.nested_string,
@@ -330,13 +365,19 @@
int ret = 0;
char encoded[] = "{\"int_max\":2147483647,"
"\"int_cero\":0,"
- "\"int_min\":-2147483648"
+ "\"int_min\":-2147483648,"
+ "\"int64_max\":9223372036854775807,"
+ "\"int64_cero\":0,"
+ "\"int64_min\":-9223372036854775808"
"}";
struct test_int_limits limits = {
.int_max = INT_MAX,
.int_cero = 0,
.int_min = INT_MIN,
+ .int64_max = INT64_MAX,
+ .int64_cero = 0,
+ .int64_min = INT64_MIN,
};
char buffer[sizeof(encoded)];
diff --git a/tests/misc/check_init_priorities/testcase.yaml b/tests/misc/check_init_priorities/testcase.yaml
index 571cba0..53e4cdf 100644
--- a/tests/misc/check_init_priorities/testcase.yaml
+++ b/tests/misc/check_init_priorities/testcase.yaml
@@ -9,4 +9,4 @@
- native_posix
integration_platforms:
- native_sim
- - native_sim
+ - native_sim/native/64
diff --git a/tests/misc/llext-edk/CMakeLists.txt b/tests/misc/llext-edk/CMakeLists.txt
index 788326a..67d3c73 100644
--- a/tests/misc/llext-edk/CMakeLists.txt
+++ b/tests/misc/llext-edk/CMakeLists.txt
@@ -4,6 +4,11 @@
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(llext_edk_test LANGUAGES C)
-target_sources(app PRIVATE src/main.c)
+target_sources(app PRIVATE src/main.c src/foo.c)
zephyr_include_directories(include)
zephyr_include_directories(${ZEPHYR_BASE}/boards/native/common)
+
+if(EXTENSION_DIR)
+ target_include_directories(app PRIVATE ${EXTENSION_DIR})
+ target_compile_definitions(app PRIVATE LOAD_AND_RUN_EXTENSION)
+endif()
diff --git a/tests/misc/llext-edk/extension/CMakeLists.txt b/tests/misc/llext-edk/extension/CMakeLists.txt
index 1b1a914..d9ddfbb 100644
--- a/tests/misc/llext-edk/extension/CMakeLists.txt
+++ b/tests/misc/llext-edk/extension/CMakeLists.txt
@@ -1,5 +1,10 @@
cmake_minimum_required(VERSION 3.20.0)
+set(CMAKE_C_COMPILER arm-zephyr-eabi-gcc)
+set(CMAKE_FIND_ROOT_PATH $ENV{ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi)
+set(CMAKE_C_COMPILER_FORCED TRUE)
+set(CMAKE_CXX_COMPILER_FORCED TRUE)
+
project(extension)
include($ENV{LLEXT_EDK_INSTALL_DIR}/cmake.cflags)
@@ -15,9 +20,15 @@
add_custom_command(
OUTPUT
${PROJECT_BINARY_DIR}/${PROJECT_NAME}.llext
+ ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.inc
COMMAND ${CMAKE_C_COMPILER} ${COMPILE_OPTIONS_PROP}
-o ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.llext
${PROJECT_SOURCE_DIR}/src/main.c
+ COMMAND
+ ${PYTHON_EXECUTABLE}
+ ${PROJECT_SOURCE_DIR}/file2hex.py
+ --file ${PROJECT_NAME}.llext
+ > ${PROJECT_NAME}.inc
)
add_custom_target(extension ALL DEPENDS ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.llext)
diff --git a/tests/misc/llext-edk/extension/src/main.c b/tests/misc/llext-edk/extension/src/main.c
index c4843be..59038de 100644
--- a/tests/misc/llext-edk/extension/src/main.c
+++ b/tests/misc/llext-edk/extension/src/main.c
@@ -5,13 +5,13 @@
*/
#include <zephyr/kernel.h>
+#include <zephyr/llext/symbol.h>
#include <app_api.h>
-int start(void)
+int start(int bar)
{
- int bar = 42;
-
printk("foo(%d) is %d\n", bar, foo(bar));
return 0;
}
+LL_EXTENSION_SYMBOL(start);
diff --git a/tests/misc/llext-edk/prj.conf b/tests/misc/llext-edk/prj.conf
index a479f3a..6f2519a 100644
--- a/tests/misc/llext-edk/prj.conf
+++ b/tests/misc/llext-edk/prj.conf
@@ -1,3 +1,5 @@
CONFIG_APPLICATION_DEFINED_SYSCALL=y
-#CONFIG_USERSPACE=y
CONFIG_LLEXT=y
+CONFIG_USERSPACE=y
+
+CONFIG_MAIN_STACK_SIZE=2048
diff --git a/tests/misc/llext-edk/pytest/test_edk.py b/tests/misc/llext-edk/pytest/test_edk.py
index d85a138..383e0b4 100644
--- a/tests/misc/llext-edk/pytest/test_edk.py
+++ b/tests/misc/llext-edk/pytest/test_edk.py
@@ -4,6 +4,7 @@
import logging
import os
+import pytest
import shutil
import tempfile
@@ -13,15 +14,23 @@
logger = logging.getLogger(__name__)
-def test_edk(dut: DeviceAdapter):
+def test_edk(unlaunched_dut: DeviceAdapter):
+ # Need to have the ZEPHYR_SDK_INSTALL_DIR environment variable set,
+ # otherwise can't actually build the edk
+ if os.environ.get("ZEPHYR_SDK_INSTALL_DIR") is None:
+ logger.warning("ZEPHYR_SDK_INSTALL_DIR is not set, skipping test")
+ pytest.skip("ZEPHYR_SDK_INSTALL_DIR is not set")
+
# Can we build the edk?
command = [
"west",
"build",
+ "-b",
+ unlaunched_dut.device_config.platform,
"-t",
"llext-edk",
"--build-dir",
- dut.device_config.build_dir,
+ unlaunched_dut.device_config.build_dir,
]
output = check_output(command, text=True)
logger.info(output)
@@ -30,7 +39,7 @@
with tempfile.TemporaryDirectory() as tempdir:
# Copy the edk to the temporary directory using python methods
logger.debug(f"Copying llext-edk.tar.xz to {tempdir}")
- edk_path = Path(dut.device_config.build_dir) / "zephyr/llext-edk.tar.xz"
+ edk_path = Path(unlaunched_dut.device_config.build_dir) / "zephyr/llext-edk.tar.xz"
shutil.copy(edk_path, tempdir)
# Extract the edk using tar
@@ -45,6 +54,12 @@
ext_dir = Path(os.environ["ZEPHYR_BASE"]) / "tests/misc/llext-edk/extension"
shutil.copytree(ext_dir, tempdir_extension, dirs_exist_ok=True)
+ # Also copy file2hex.py to the extension directory, so that it's possible
+ # to generate a hex file from the extension binary
+ logger.debug(f"Copying file2hex.py to {tempdir_extension}")
+ file2hex = Path(os.environ["ZEPHYR_BASE"]) / "scripts/build/file2hex.py"
+ shutil.copy(file2hex, tempdir_extension)
+
# Set the LLEXT_EDK_INSTALL_DIR environment variable so that the extension
# knows where the EDK is installed
edk_dir = Path(tempdir) / "llext-edk"
@@ -64,3 +79,35 @@
# Check if the extension was built
assert os.path.exists(Path(tempdir_extension) / "build/extension.llext")
+
+ # Can we run it? First, rebuild the application, now including the extension
+ # build directory in the include path, so that the application can find the
+ # extension code.
+ logger.debug(f"Running application with extension in {tempdir_extension} - west build")
+ command = [
+ "west",
+ "build",
+ "-b",
+ unlaunched_dut.device_config.platform,
+ "--build-dir",
+ unlaunched_dut.device_config.build_dir,
+ "--",
+ f"-DEXTENSION_DIR={tempdir_extension}/build/"
+ ]
+ logger.debug(f"west command: {command}")
+ output = check_output(command, text=True)
+ logger.info(output)
+
+ # Now that the application is built, run it
+ logger.debug(f"Running application with extension in {tempdir_extension}")
+ try:
+ unlaunched_dut.launch()
+ lines = unlaunched_dut.readlines_until("Done")
+
+ assert "Calling extension from kernel" in lines
+ assert "Calling extension from user" in lines
+ assert "foo(42) is 1764" in lines
+ assert "foo(43) is 1849" in lines
+
+ finally:
+ unlaunched_dut.close()
diff --git a/tests/misc/llext-edk/src/foo.c b/tests/misc/llext-edk/src/foo.c
index e7a3d22..3751ecc 100644
--- a/tests/misc/llext-edk/src/foo.c
+++ b/tests/misc/llext-edk/src/foo.c
@@ -5,7 +5,9 @@
*/
#include <app_api.h>
-#include <app_api.h>
+
+#include <zephyr/llext/symbol.h>
+#include <zephyr/internal/syscall_handler.h>
int z_impl_foo(int bar)
{
diff --git a/tests/misc/llext-edk/src/main.c b/tests/misc/llext-edk/src/main.c
index a5e7ab2..cc13b8d 100644
--- a/tests/misc/llext-edk/src/main.c
+++ b/tests/misc/llext-edk/src/main.c
@@ -6,9 +6,94 @@
#include <app_api.h>
+#include <zephyr/kernel.h>
#include <zephyr/llext/llext.h>
+#include <zephyr/llext/buf_loader.h>
+#include <zephyr/app_memory/mem_domain.h>
+
+#ifdef LOAD_AND_RUN_EXTENSION
+static const unsigned char extension_llext[] = {
+ #include <extension.inc>
+};
+static const size_t extension_llext_len = ARRAY_SIZE(extension_llext);
+#endif
+
+#define STACK_SIZE 1024
+#define HEAP_SIZE 1024
+
+#ifdef LOAD_AND_RUN_EXTENSION
+struct k_thread kernel_thread, user_thread;
+
+K_THREAD_STACK_DEFINE(stack_kernel, STACK_SIZE);
+K_THREAD_STACK_DEFINE(stack_user, STACK_SIZE);
+
+K_HEAP_DEFINE(heap_kernel, HEAP_SIZE);
+K_HEAP_DEFINE(heap_user, HEAP_SIZE);
+
+static void thread_entry(void *p1, void *p2, void *p3)
+{
+ int bar;
+ int (*start_fn)(int) = p1;
+
+ printk("Calling extension from %s\n",
+ k_is_user_context() ? "user" : "kernel");
+
+ if (k_is_user_context()) {
+ bar = 42;
+ } else {
+ bar = 43;
+ }
+
+ start_fn(bar);
+}
+
+void load_and_run_extension(int thread_flags, struct k_thread *thread,
+ struct k_mem_domain *domain,
+ k_thread_stack_t *stack, struct k_heap *heap,
+ struct llext **ext)
+{
+ struct llext_buf_loader buf_loader = LLEXT_BUF_LOADER(extension_llext,
+ extension_llext_len);
+ struct llext_loader *loader = &buf_loader.loader;
+ struct llext_load_param ldr_parm = LLEXT_LOAD_PARAM_DEFAULT;
+ int (*start_fn)(int bar);
+
+ llext_load(loader, "extension", ext, &ldr_parm);
+ start_fn = llext_find_sym(&(*ext)->exp_tab, "start");
+
+ llext_add_domain(*ext, domain);
+
+ k_thread_create(thread, stack, STACK_SIZE,
+ thread_entry, start_fn, NULL, NULL, -1,
+ K_INHERIT_PERMS | thread_flags,
+ K_FOREVER);
+ k_mem_domain_add_thread(domain, thread);
+ k_thread_heap_assign(thread, heap);
+
+ k_thread_start(thread);
+ k_thread_join(thread, K_FOREVER);
+
+ llext_unload(ext);
+}
+#endif
int main(void)
{
+#ifdef LOAD_AND_RUN_EXTENSION
+ struct k_mem_domain domain_kernel, domain_user;
+ struct llext *ext_kernel, *ext_user;
+
+ k_mem_domain_init(&domain_kernel, 0, NULL);
+ k_mem_domain_init(&domain_user, 0, NULL);
+
+ load_and_run_extension(0, &kernel_thread, &domain_kernel,
+ stack_kernel, &heap_kernel, &ext_kernel);
+ load_and_run_extension(K_USER, &user_thread, &domain_user,
+ stack_user, &heap_user, &ext_user);
+
+ printk("Done\n");
+#else
+ printk("Extension not loaded\n");
+#endif
return 0;
}
diff --git a/tests/misc/llext-edk/testcase.yaml b/tests/misc/llext-edk/testcase.yaml
index 81f7ce0..596d3ec 100644
--- a/tests/misc/llext-edk/testcase.yaml
+++ b/tests/misc/llext-edk/testcase.yaml
@@ -5,5 +5,5 @@
- pytest
- edk
platform_allow:
- - native_sim
+ - qemu_cortex_r5
toolchain_exclude: llvm
diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c
index 1b01002..5bf1c4c 100644
--- a/tests/net/buf/src/main.c
+++ b/tests/net/buf/src/main.c
@@ -140,8 +140,8 @@
}
k_fifo_init(&fifo);
- net_buf_put(&fifo, head);
- head = net_buf_get(&fifo, K_NO_WAIT);
+ k_fifo_put(&fifo, head);
+ head = k_fifo_get(&fifo, K_NO_WAIT);
destroy_called = 0;
net_buf_unref(head);
@@ -159,7 +159,7 @@
k_sem_give(sema);
- buf = net_buf_get(fifo, TEST_TIMEOUT);
+ buf = k_fifo_get(fifo, TEST_TIMEOUT);
zassert_not_null(buf, "Unable to get buffer");
destroy_called = 0;
@@ -201,7 +201,7 @@
zassert_true(k_sem_take(&sema, TEST_TIMEOUT) == 0,
"Timeout while waiting for semaphore");
- net_buf_put(&fifo, head);
+ k_fifo_put(&fifo, head);
zassert_true(k_sem_take(&sema, TEST_TIMEOUT) == 0,
"Timeout while waiting for semaphore");
diff --git a/tests/net/lib/lwm2m/interop/README.md b/tests/net/lib/lwm2m/interop/README.md
index cac3f9a..0a2f6b2 100644
--- a/tests/net/lib/lwm2m/interop/README.md
+++ b/tests/net/lib/lwm2m/interop/README.md
@@ -2,7 +2,7 @@
This directory contains list of testcases that use
the Twister's Pytest integration to run testcases against Leshan demo server.
-These tests use emulated hardware (native_posix).
+These tests use emulated hardware (native_sim).
These tests require setup that is not done in Twister run, so follow this documentation to set
up the test environment.
@@ -105,7 +105,7 @@
## Running tests
```
-twister -p native_posix -vv --enable-slow -T tests/net/lib/lwm2m/interop
+twister -p native_sim -vv --enable-slow -T tests/net/lib/lwm2m/interop
```
Or use the Docker based testing
diff --git a/tests/net/lib/lwm2m/interop/pytest/leshan.py b/tests/net/lib/lwm2m/interop/pytest/leshan.py
index 198c3fc..024bc67 100644
--- a/tests/net/lib/lwm2m/interop/pytest/leshan.py
+++ b/tests/net/lib/lwm2m/interop/pytest/leshan.py
@@ -420,7 +420,7 @@
Events are notifications, updates and sends.
The event stream must be closed after the use, so this must be used in 'with' statement like this:
- with leshan.get_event_stream('native_posix') as events:
+ with leshan.get_event_stream('native_sim') as events:
data = events.next_event('SEND')
If timeout happens, the event streams returns None.
diff --git a/tests/net/lib/lwm2m/lwm2m_engine/src/main.c b/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
index 7078fbe..d982f3a 100644
--- a/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
+++ b/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
@@ -32,12 +32,15 @@
uint16_t *buffer_len, uint16_t *data_len,
uint8_t *data_flags)
{
- if (buffer_ptr)
+ if (buffer_ptr) {
*buffer_ptr = my_buf;
- if (buffer_len)
+ }
+ if (buffer_len) {
*buffer_len = sizeof(my_buf);
- if (data_len)
+ }
+ if (data_len) {
*data_len = my_data_len;
+ }
return 0;
}
diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c
index 57b0e8b..20d0729 100644
--- a/tests/net/virtual/src/main.c
+++ b/tests/net/virtual/src/main.c
@@ -309,8 +309,9 @@
if ((iface != net_if_lookup_by_dev(DEVICE_GET(eth_test_dummy1))) &&
(iface != net_if_lookup_by_dev(DEVICE_GET(eth_test_dummy2))) &&
(iface != net_if_lookup_by_dev(DEVICE_GET(eth_test))) &&
- (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)))
+ (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL))) {
return;
+ }
DBG("Interface %p (%s) [%d]\n", iface, iface2str(iface),
net_if_get_by_iface(iface));
diff --git a/tests/net/wifi/wifi_nm/testcase.yaml b/tests/net/wifi/wifi_nm/testcase.yaml
index 227f39f..3d2001f 100644
--- a/tests/net/wifi/wifi_nm/testcase.yaml
+++ b/tests/net/wifi/wifi_nm/testcase.yaml
@@ -4,3 +4,8 @@
net.wifi:
min_ram: 32
tags: wifi
+ platform_exclude:
+ - nrf7002dk/nrf5340/cpuapp
+ - nrf7002dk/nrf5340/cpuapp/ns
+ - nrf7002dk/nrf5340/cpuapp/nrf7001
+ - nrf7002dk/nrf5340/cpuapp/nrf7001/ns
diff --git a/tests/posix/fs/src/test_fs_dir.c b/tests/posix/fs/src/test_fs_dir.c
index 6f5f23b..e527412 100644
--- a/tests/posix/fs/src/test_fs_dir.c
+++ b/tests/posix/fs/src/test_fs_dir.c
@@ -150,3 +150,30 @@
zassert_true(test_mkdir() == TC_PASS);
zassert_true(test_lsdir(TEST_DIR, true) == TC_PASS);
}
+
+/**
+ * @brief Test for POSIX rmdir API
+ *
+ * @details Test creates a new directory through POSIX
+ * mkdir API and remove directory using rmdir.
+ */
+ZTEST(posix_fs_dir_test, test_fs_rmdir)
+{
+#define IRWXG 0070
+ /* Create and remove empty directory */
+ zassert_ok(mkdir(TEST_DIR, IRWXG), "Error creating dir: %d", errno);
+ zassert_ok(rmdir(TEST_DIR), "Error removing dir: %d\n", errno);
+
+ /* Create directory and open a file in the directory
+ * now removing the directory will fail, test will
+ * fail in removal of non empty directory
+ */
+ zassert_ok(mkdir(TEST_DIR, IRWXG), "Error creating dir: %d", errno);
+ zassert_not_equal(open(TEST_DIR_FILE, O_CREAT | O_RDWR), -1,
+ "Error creating file: %d", errno);
+ zassert_not_ok(rmdir(TEST_DIR), "Error Non empty dir removed");
+ zassert_not_ok(rmdir(""), "Error Invalid path removed");
+ zassert_not_ok(rmdir(NULL), "Error Invalid path removed");
+ zassert_not_ok(rmdir("TEST_DIR."), "Error Invalid path removed");
+ zassert_not_ok(rmdir(TEST_FILE), "Error file removed");
+}
diff --git a/tests/posix/fs/src/test_fs_file.c b/tests/posix/fs/src/test_fs_file.c
index 43fdaa3..4a22270 100644
--- a/tests/posix/fs/src/test_fs_file.c
+++ b/tests/posix/fs/src/test_fs_file.c
@@ -145,8 +145,9 @@
{
int res = 0;
- if (file < 0)
+ if (file < 0) {
return res;
+ }
res = fsync(file);
if (res < 0) {
@@ -184,8 +185,9 @@
int res = 0;
size_t truncate_size = sizeof(test_str) - 4;
- if (file < 0)
+ if (file < 0) {
return res;
+ }
res = ftruncate(file, truncate_size);
if (res) {
diff --git a/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core.overlay b/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core.overlay
deleted file mode 100644
index eb707ee..0000000
--- a/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core.overlay
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&flash0 {
- partitions {
- /*
- * Reduce storage_partition to make space for
- * coredump_partition
- */
-
- storage_partition: partition@250000 {
- label = "storage";
- reg = <0x00250000 0x00005000>;
- };
-
- coredump_partition: partition@255000 {
- label = "coredump-partition";
- reg = <0x255000 DT_SIZE_K(4)>;
- };
-
- };
-};
diff --git a/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_esp32c3_usb.overlay b/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_esp32c3_usb.overlay
deleted file mode 100644
index eb707ee..0000000
--- a/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_esp32c3_usb.overlay
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&flash0 {
- partitions {
- /*
- * Reduce storage_partition to make space for
- * coredump_partition
- */
-
- storage_partition: partition@250000 {
- label = "storage";
- reg = <0x00250000 0x00005000>;
- };
-
- coredump_partition: partition@255000 {
- label = "coredump-partition";
- reg = <0x255000 DT_SIZE_K(4)>;
- };
-
- };
-};
diff --git a/tests/subsys/debug/coredump_backends/boards/esp32c3_devkitm.overlay b/tests/subsys/debug/coredump_backends/socs/esp32c3.overlay
similarity index 100%
rename from tests/subsys/debug/coredump_backends/boards/esp32c3_devkitm.overlay
rename to tests/subsys/debug/coredump_backends/socs/esp32c3.overlay
diff --git a/tests/subsys/debug/thread_analyzer/testcase.yaml b/tests/subsys/debug/thread_analyzer/testcase.yaml
index dfe2405..58cdca6 100644
--- a/tests/subsys/debug/thread_analyzer/testcase.yaml
+++ b/tests/subsys/debug/thread_analyzer/testcase.yaml
@@ -2,12 +2,18 @@
integration_platforms:
- mps2/an385
- qemu_x86_64
+ platform_allow:
+ # Representative platforms to make sure this builds without issues
+ # and the analyzer actually runs and outputs something.
+ - mps2/an385
+ - qemu_cortex_a53
+ - qemu_x86
+ - qemu_x86_64
+ - qemu_riscv32
+ - qemu_riscv64
tags:
- debug
- thread_analyzer
- arch_exclude:
- # The thread analyzer depends on !ARCH_POSIX
- - posix
tests:
debug.thread_analyzer.printk:
extra_configs:
diff --git a/tests/subsys/fs/fat_fs_api/prj_sdmmc.conf b/tests/subsys/fs/fat_fs_api/prj_sdmmc.conf
new file mode 100644
index 0000000..89e4b21
--- /dev/null
+++ b/tests/subsys/fs/fat_fs_api/prj_sdmmc.conf
@@ -0,0 +1,6 @@
+CONFIG_FILE_SYSTEM=y
+CONFIG_LOG=y
+CONFIG_FAT_FILESYSTEM_ELM=y
+CONFIG_ZTEST=y
+CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_ZTEST_STACK_SIZE=2048
diff --git a/tests/subsys/fs/fat_fs_api/src/common.c b/tests/subsys/fs/fat_fs_api/src/common.c
index fd4aa46..348aa84 100644
--- a/tests/subsys/fs/fat_fs_api/src/common.c
+++ b/tests/subsys/fs/fat_fs_api/src/common.c
@@ -6,12 +6,24 @@
*/
#include "test_fat.h"
+#ifdef CONFIG_DISK_DRIVER_FLASH
+#include <zephyr/storage/flash_map.h>
+#else
+#include <zephyr/storage/disk_access.h>
+#endif
/* FatFs work area */
FATFS fat_fs;
struct fs_file_t filep;
const char test_str[] = "hello world!";
+/* For large disks, we only send 1024 erase requests
+ * This assumption relies on the fact that any filesystem headers will be
+ * stored within this range, and is made to improve execution time of this
+ * test
+ */
+#define MAX_ERASES 1024
+
int check_file_dir_exists(const char *path)
{
int res;
@@ -22,3 +34,74 @@
return !res;
}
+
+#ifdef CONFIG_DISK_DRIVER_FLASH
+int wipe_partition(void)
+{
+ /* In this test the first partition on flash device is used for FAT */
+ unsigned int id = 0;
+ const struct flash_area *pfa;
+ int rc = flash_area_open(id, &pfa);
+
+ if (rc < 0) {
+ TC_PRINT("Error accessing flash area %u [%d]\n",
+ id, rc);
+ return TC_FAIL;
+ }
+
+ TC_PRINT("Erasing %zu (0x%zx) bytes\n", pfa->fa_size, pfa->fa_size);
+ rc = flash_area_flatten(pfa, 0, pfa->fa_size);
+ (void)flash_area_close(pfa);
+
+ if (rc < 0) {
+ TC_PRINT("Error wiping flash area %u [%d]\n",
+ id, rc);
+ return TC_FAIL;
+ }
+
+ return TC_PASS;
+}
+#else
+static uint8_t erase_buffer[4096] = { 0 };
+
+int wipe_partition(void)
+{
+ uint32_t sector_size;
+ uint32_t sector_count;
+ uint32_t sector_wr_jmp;
+ uint32_t sector_wr_size;
+
+ if (disk_access_init(DISK_NAME)) {
+ TC_PRINT("Failed to init disk "DISK_NAME"\n");
+ return TC_FAIL;
+ }
+ if (disk_access_ioctl(DISK_NAME, DISK_IOCTL_GET_SECTOR_COUNT, §or_count)) {
+ TC_PRINT("Failed to get disk "DISK_NAME" sector count\n");
+ return TC_FAIL;
+ }
+ if (disk_access_ioctl(DISK_NAME, DISK_IOCTL_GET_SECTOR_SIZE, §or_size)) {
+ TC_PRINT("Failed to get disk "DISK_NAME" sector size\n");
+ return TC_FAIL;
+ }
+
+ if (sector_size > ARRAY_SIZE(erase_buffer)) {
+ TC_PRINT("Predefined \"erase_buffer\" to small to handle single sector\n");
+ return TC_FAIL;
+ }
+
+ sector_wr_size = MIN(sector_size, ARRAY_SIZE(erase_buffer));
+ sector_wr_jmp = sector_wr_size / sector_wr_size;
+ TC_PRINT("For "DISK_NAME" using sector write size %"PRIu32" to write %"PRIu32" at once\n",
+ sector_wr_size, sector_wr_jmp);
+
+ for (uint32_t sector_idx = 0; sector_idx < sector_count; sector_idx += sector_wr_jmp) {
+ if (disk_access_write(DISK_NAME, erase_buffer, sector_idx, 1)) {
+ TC_PRINT("Failed to \"erase\" sector %"PRIu32" to "DISK_NAME"\n",
+ sector_idx);
+ return TC_FAIL;
+ }
+ }
+
+ return TC_PASS;
+}
+#endif
diff --git a/tests/subsys/fs/fat_fs_api/src/test_fat.h b/tests/subsys/fs/fat_fs_api/src/test_fat.h
index 8048ef0..c5ef9b1 100644
--- a/tests/subsys/fs/fat_fs_api/src/test_fat.h
+++ b/tests/subsys/fs/fat_fs_api/src/test_fat.h
@@ -39,6 +39,7 @@
extern FATFS fat_fs;
int check_file_dir_exists(const char *path);
+int wipe_partition(void);
void test_fat_mount(void);
void test_fat_unmount(void);
diff --git a/tests/subsys/fs/fat_fs_api/src/test_fat_mkfs.c b/tests/subsys/fs/fat_fs_api/src/test_fat_mkfs.c
index 5af5b53..ad8248f 100644
--- a/tests/subsys/fs/fat_fs_api/src/test_fat_mkfs.c
+++ b/tests/subsys/fs/fat_fs_api/src/test_fat_mkfs.c
@@ -7,11 +7,6 @@
#include "test_fat.h"
#include <ff.h>
-#ifdef CONFIG_DISK_DRIVER_FLASH
-#include <zephyr/storage/flash_map.h>
-#else
-#include <zephyr/storage/disk_access.h>
-#endif
/* mounting info */
static struct fs_mount_t fatfs_mnt = {
@@ -30,77 +25,6 @@
const char *some_file_path = "/"DISK_NAME":/SOME";
const char *other_dir_path = "/"DISK_NAME":/OTHER";
-#ifdef CONFIG_DISK_DRIVER_FLASH
-static int wipe_partition(void)
-{
- /* In this test the first partition on flash device is used for FAT */
- unsigned int id = 0;
- const struct flash_area *pfa;
- int rc = flash_area_open(id, &pfa);
-
- if (rc < 0) {
- TC_PRINT("Error accessing flash area %u [%d]\n",
- id, rc);
- return TC_FAIL;
- }
-
- TC_PRINT("Erasing %zu (0x%zx) bytes\n", pfa->fa_size, pfa->fa_size);
- rc = flash_area_flatten(pfa, 0, pfa->fa_size);
- (void)flash_area_close(pfa);
-
- if (rc < 0) {
- TC_PRINT("Error wiping flash area %u [%d]\n",
- id, rc);
- return TC_FAIL;
- }
-
- return TC_PASS;
-}
-#else
-static uint8_t erase_buffer[4096] = { 0 };
-
-static int wipe_partition(void)
-{
- uint32_t sector_size;
- uint32_t sector_count;
- uint32_t sector_wr_jmp;
- uint32_t sector_wr_size;
-
- if (disk_access_init(DISK_NAME)) {
- TC_PRINT("Failed to init disk "DISK_NAME"\n");
- return TC_FAIL;
- }
- if (disk_access_ioctl(DISK_NAME, DISK_IOCTL_GET_SECTOR_COUNT, §or_count)) {
- TC_PRINT("Failed to get disk "DISK_NAME" sector count\n");
- return TC_FAIL;
- }
- if (disk_access_ioctl(DISK_NAME, DISK_IOCTL_GET_SECTOR_SIZE, §or_size)) {
- TC_PRINT("Failed to get disk "DISK_NAME" sector size\n");
- return TC_FAIL;
- }
-
- if (sector_size > ARRAY_SIZE(erase_buffer)) {
- TC_PRINT("Predefined \"erase_buffer\" to small to handle single sector\n");
- return TC_FAIL;
- }
-
- sector_wr_size = MIN(sector_size, ARRAY_SIZE(erase_buffer));
- sector_wr_jmp = sector_wr_size / sector_wr_size;
- TC_PRINT("For "DISK_NAME" using sector write size "PRIu32" to write "PRIu32" at once\n",
- sector_wr_size, sector_wr_jmp);
-
- for (uint32_t sector_idx = 0; sector_idx < sector_count; sector_idx += sector_wr_jmp) {
- if (disk_access_write(DISK_NAME, erase_buffer, sector_idx, 1)) {
- TC_PRINT("Faield to \"erase\" sector "PRIu32" to "DISK_NAME"\n",
- sector_idx);
- return TC_FAIL;
- }
- }
-
- return TC_PASS;
-}
-#endif
-
ZTEST(fat_fs_mkfs, test_mkfs_simple)
{
int ret;
diff --git a/tests/subsys/fs/fat_fs_api/src/test_fat_mount.c b/tests/subsys/fs/fat_fs_api/src/test_fat_mount.c
index d0c7de8..93748c8 100644
--- a/tests/subsys/fs/fat_fs_api/src/test_fat_mount.c
+++ b/tests/subsys/fs/fat_fs_api/src/test_fat_mount.c
@@ -85,6 +85,7 @@
void test_fat_mount(void)
{
+ zassert_true(wipe_partition() == 0);
zassert_false(test_unmount() == TC_PASS);
zassert_true(test_mount_no_format() == TC_PASS);
zassert_true(test_mount_rd_only_no_sys() == TC_PASS);
diff --git a/tests/subsys/fs/fat_fs_api/testcase.yaml b/tests/subsys/fs/fat_fs_api/testcase.yaml
index 59cd603..964b5e7 100644
--- a/tests/subsys/fs/fat_fs_api/testcase.yaml
+++ b/tests/subsys/fs/fat_fs_api/testcase.yaml
@@ -15,6 +15,9 @@
filesystem.fat.api.mmc:
extra_args: CONF_FILE="prj_mmc.conf"
filter: dt_compat_enabled("zephyr,mmc-disk")
+ filesystem.fat.api.sdmmc:
+ extra_args: CONF_FILE="prj_sdmmc.conf"
+ filter: dt_compat_enabled("zephyr,sdmmc-disk")
filesystem.fat.ram.api:
platform_allow:
- native_sim
diff --git a/tests/subsys/input/double_tap/CMakeLists.txt b/tests/subsys/input/double_tap/CMakeLists.txt
new file mode 100644
index 0000000..55f5841e
--- /dev/null
+++ b/tests/subsys/input/double_tap/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(input_double_tap)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/subsys/input/double_tap/boards/native_sim.overlay b/tests/subsys/input/double_tap/boards/native_sim.overlay
new file mode 100644
index 0000000..fa74ae6
--- /dev/null
+++ b/tests/subsys/input/double_tap/boards/native_sim.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2024 Kelly Helmut Lord
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ fake_input_device: fake-device {
+ compatible = "vnd,input-device";
+ };
+
+ double_tap: doubletap {
+ input = <&fake_input_device>;
+ compatible = "zephyr,input-double-tap";
+ input-codes = <INPUT_KEY_0>, <INPUT_KEY_1>;
+ double-tap-codes = <INPUT_KEY_X>, <INPUT_KEY_Y>;
+ double-tap-delay-ms = <300>;
+ };
+};
diff --git a/tests/subsys/input/double_tap/boards/native_sim_native_64.overlay b/tests/subsys/input/double_tap/boards/native_sim_native_64.overlay
new file mode 100644
index 0000000..091e5d6
--- /dev/null
+++ b/tests/subsys/input/double_tap/boards/native_sim_native_64.overlay
@@ -0,0 +1,6 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "native_sim.overlay"
diff --git a/tests/subsys/input/double_tap/prj.conf b/tests/subsys/input/double_tap/prj.conf
new file mode 100644
index 0000000..bc713698bb
--- /dev/null
+++ b/tests/subsys/input/double_tap/prj.conf
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ZTEST=y
+CONFIG_INPUT=y
+CONFIG_INPUT_MODE_SYNCHRONOUS=y
diff --git a/tests/subsys/input/double_tap/src/main.c b/tests/subsys/input/double_tap/src/main.c
new file mode 100644
index 0000000..34c30d6
--- /dev/null
+++ b/tests/subsys/input/double_tap/src/main.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2024 Kelly Helmut Lord
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/input/input.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+static const struct device *const fake_dev = DEVICE_DT_GET(
+ DT_NODELABEL(fake_input_device));
+static const struct device *const double_tap_dev = DEVICE_DT_GET(
+ DT_NODELABEL(double_tap));
+
+DEVICE_DT_DEFINE(DT_INST(0, vnd_input_device), NULL, NULL, NULL, NULL,
+ PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
+
+static int event_count;
+static struct input_event last_events[2];
+
+static void test_cb(struct input_event *evt, void *user_data)
+{
+ TC_PRINT("%s: %d %x %d\n", __func__, event_count, evt->code, evt->value);
+
+ event_count++;
+ memcpy(&last_events[1], &last_events[0], sizeof(struct input_event));
+ memcpy(&last_events[0], evt, sizeof(struct input_event));
+}
+INPUT_CALLBACK_DEFINE(double_tap_dev, test_cb, NULL);
+
+ZTEST(double_tap, test_double_tap_test)
+{
+ zassert_equal(event_count, 0);
+
+ /* ignored */
+ input_report_key(fake_dev, INPUT_KEY_3, 1, true, K_FOREVER);
+ input_report_key(fake_dev, INPUT_KEY_3, 0, true, K_FOREVER);
+ zassert_equal(event_count, 0);
+ input_report_abs(fake_dev, INPUT_KEY_0, 1, true, K_FOREVER);
+ input_report_abs(fake_dev, INPUT_KEY_0, 0, true, K_FOREVER);
+ zassert_equal(event_count, 0);
+
+ /* double tap*/
+ input_report_key(fake_dev, INPUT_KEY_0, 1, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_0, 0, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_0, 1, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_0, 0, true, K_FOREVER);
+ zassert_equal(event_count, 2);
+ zassert_equal(last_events[1].type, INPUT_EV_KEY);
+ zassert_equal(last_events[1].code, INPUT_KEY_X);
+ zassert_equal(last_events[1].value, 1);
+ zassert_equal(last_events[0].type, INPUT_EV_KEY);
+ zassert_equal(last_events[0].code, INPUT_KEY_X);
+ zassert_equal(last_events[0].value, 0);
+
+ /* double tap - other key */
+ input_report_key(fake_dev, INPUT_KEY_1, 1, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_1, 0, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_1, 1, true, K_FOREVER);
+ k_sleep(K_MSEC(50));
+ input_report_key(fake_dev, INPUT_KEY_1, 0, true, K_FOREVER);
+ zassert_equal(event_count, 4);
+ zassert_equal(last_events[1].type, INPUT_EV_KEY);
+ zassert_equal(last_events[1].code, INPUT_KEY_Y);
+ zassert_equal(last_events[1].value, 1);
+ zassert_equal(last_events[0].type, INPUT_EV_KEY);
+ zassert_equal(last_events[0].code, INPUT_KEY_Y);
+ zassert_equal(last_events[0].value, 0);
+}
+
+ZTEST_SUITE(double_tap, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/input/double_tap/testcase.yaml b/tests/subsys/input/double_tap/testcase.yaml
new file mode 100644
index 0000000..7460cd6
--- /dev/null
+++ b/tests/subsys/input/double_tap/testcase.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+ input.input_double_tap:
+ platform_allow:
+ - native_sim
+ - native_sim/native/64
+ tags:
+ - drivers
+ - input
+ integration_platforms:
+ - native_sim
diff --git a/tests/subsys/logging/log_output/prj.conf b/tests/subsys/logging/log_output/prj.conf
index 1d715c5..ca82305 100644
--- a/tests/subsys/logging/log_output/prj.conf
+++ b/tests/subsys/logging/log_output/prj.conf
@@ -4,3 +4,4 @@
CONFIG_LOG_OUTPUT=y
CONFIG_LOG_PRINTK=n
CONFIG_ZTEST_STACK_SIZE=1152
+CONFIG_LOG_DBG_COLOR_BLUE=y
diff --git a/tests/subsys/logging/log_output/src/log_output_test.c b/tests/subsys/logging/log_output/src/log_output_test.c
index 21ee039..fd59baa 100644
--- a/tests/subsys/logging/log_output/src/log_output_test.c
+++ b/tests/subsys/logging/log_output/src/log_output_test.c
@@ -192,13 +192,14 @@
#define LOG_COLOR_CODE_RED "\x1B[1;31m"
#define LOG_COLOR_CODE_GREEN "\x1B[1;32m"
#define LOG_COLOR_CODE_YELLOW "\x1B[1;33m"
+#define LOG_COLOR_CODE_BLUE "\x1B[1;34m"
char package[256];
static const char *const exp_strs[] = {
LOG_COLOR_CODE_RED "<err> " SNAME ": " TEST_STR LOG_COLOR_CODE_DEFAULT "\r\n",
LOG_COLOR_CODE_YELLOW "<wrn> " SNAME ": " TEST_STR LOG_COLOR_CODE_DEFAULT "\r\n",
LOG_COLOR_CODE_DEFAULT "<inf> " SNAME ": " TEST_STR LOG_COLOR_CODE_DEFAULT "\r\n",
- LOG_COLOR_CODE_DEFAULT "<dbg> " SNAME ": " TEST_STR LOG_COLOR_CODE_DEFAULT "\r\n"
+ LOG_COLOR_CODE_BLUE "<dbg> " SNAME ": " TEST_STR LOG_COLOR_CODE_DEFAULT "\r\n"
};
uint8_t levels[] = {LOG_LEVEL_ERR, LOG_LEVEL_WRN, LOG_LEVEL_INF, LOG_LEVEL_DBG};
uint32_t flags = LOG_OUTPUT_FLAG_LEVEL | LOG_OUTPUT_FLAG_COLORS;
diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml
index efceb4a..b34d7fb 100644
--- a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml
+++ b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml
@@ -15,6 +15,7 @@
- arduino_portenta_h7/stm32h747xx/m4
- lpcxpresso51u68
- nucleo_h745zi_q/stm32h745xx/m4
+ - nucleo_h755zi_q/stm32h755xx/m4
- stm32h747i_disco/stm32h747xx/m4
- lpcxpresso55s69/lpc55s69/cpu1
- mpfs_icicle
diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml
index 203e44f..63ef2f2 100644
--- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml
+++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml
@@ -11,6 +11,8 @@
- twr_ke18f
- mimxrt595_evk/mimxrt595s/cm33
- rd_rw612_bga
+ - frdm_ke17z
+ - frdm_ke17z512
tags: pm
integration_platforms:
- mec15xxevb_assy6853
diff --git a/west.yml b/west.yml
index 8aedafc..99b7f1c 100644
--- a/west.yml
+++ b/west.yml
@@ -157,7 +157,7 @@
groups:
- hal
- name: hal_espressif
- revision: e2902b60bc8b540b49f1012e6d45f8eef067f5bb
+ revision: e05b24f5caee741e0f3b43123bf2082e8cc908e7
path: modules/hal/espressif
west-commands: west/west-commands.yml
groups:
@@ -188,7 +188,7 @@
groups:
- hal
- name: hal_nordic
- revision: 0b6040d9b440b769a65f25c6fd9320eeff88ee94
+ revision: 91654ddc7ce0da523eb4d6be2171208ae2b8fb35
path: modules/hal/nordic
groups:
- hal
@@ -198,7 +198,7 @@
groups:
- hal
- name: hal_nxp
- revision: 42ea394cbd2d8632339bbecb1efffffa696d11e6
+ revision: e400b5dba27d9abe1403fc799d48b58fa1b1daee
path: modules/hal/nxp
groups:
- hal
@@ -214,7 +214,7 @@
- hal
- name: hal_renesas
path: modules/hal/renesas
- revision: af77d7cdfeeff290593e7e99f54f0c1e2a3f91e6
+ revision: d17dc07ba2af3cedf869454c9cb9c293d8379fe4
groups:
- hal
- name: hal_rpi_pico
@@ -228,7 +228,7 @@
groups:
- hal
- name: hal_st
- revision: b77157f6bc4395e398d90ab02a7d2cbc01ab2ce7
+ revision: b2f548fe672f24122c7f92027b2c9eeea8a0483a
path: modules/hal/st
groups:
- hal
@@ -259,7 +259,7 @@
- hal
- name: hostap
path: modules/lib/hostap
- revision: a941086775a865d170743a5d4790f1fa213ec6a4
+ revision: 77a4cad575c91f1b234c8d15630f87999881cde2
- name: libmetal
revision: a6851ba6dba8c9e87d00c42f171a822f7a29639b
path: modules/hal/libmetal
@@ -310,7 +310,7 @@
path: modules/lib/openthread
- name: percepio
path: modules/debug/percepio
- revision: a49e5f3947faad0dd654eddd5a750127fb81e50d
+ revision: b68d17993109b9bee6b45dc8c9794e7b7bce236d
groups:
- debug
- name: picolibc
