IAR LDR{,B,H}T fix (#242)

Inline assembler constraints were incorrect.

(cherry picked from commit 06d952b6713a2ca41c9224a62075e4059402a151)

Original-Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
GitOrigin-RevId: 06d952b6713a2ca41c9224a62075e4059402a151
Cr-Build-Id: 8711229266785233873
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8711229266785233873
Copybot-Job-Name: zephyr-cmsis_6-copybot-downstream
Change-Id: Iac2a8d8f0dd0ba1d8de6cd36aadf43b17551035b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/cmsis_6/+/6665386
Commit-Queue: ChromeOS Copybot <copybot@chops-service-accounts.iam.gserviceaccount.com>
Tested-by: ChromeOS Copybot <copybot@chops-service-accounts.iam.gserviceaccount.com>
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CMSIS/Core/Include/cmsis_iccarm.h

diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h
index 1628446..722126e 100644
--- a/CMSIS/Core/Include/cmsis_iccarm.h
+++ b/CMSIS/Core/Include/cmsis_iccarm.h
@@ -348,21 +348,21 @@
 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRBT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return ((uint8_t)res);
 }
 
 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRHT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return ((uint16_t)res);
 }
 
 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return res;
 }