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| <div class="title">crashpad::MinidumpContextAMD64 Struct Reference</div> </div> |
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| |
| <p>An x86_64 (AMD64) CPU context (register state) carried in a minidump file. |
| <a href="structcrashpad_1_1MinidumpContextAMD64.html#details">More...</a></p> |
| |
| <p><code>#include "minidump/minidump_context.h"</code></p> |
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| <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> |
| Public Attributes</h2></td></tr> |
| <tr class="memitem:a086c5c2655800e91e080241317aa3ace"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a086c5c2655800e91e080241317aa3ace">context_flags</a></td></tr> |
| <tr class="memdesc:a086c5c2655800e91e080241317aa3ace"><td class="mdescLeft"> </td><td class="mdescRight">A bitfield composed of values of <a class="el" href="namespacecrashpad.html#a835e6bd6cb3f97c99c572596878c1573" title="Architecture-independent flags for context_flags fields in Minidump context structures.">MinidumpContextFlags</a> and <a class="el" href="namespacecrashpad.html#aa197c419950bae99f1ba663f10b1891c" title="x86_64-specific flags for MinidumpContextAMD64::context_flags.">MinidumpContextAMD64Flags</a>. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a086c5c2655800e91e080241317aa3ace">More...</a><br /></td></tr> |
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| uint32_t </td><td class="memItemRight" valign="bottom"><b>mx_csr</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>cs</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>ds</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>es</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>fs</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>gs</b></td></tr> |
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| uint16_t </td><td class="memItemRight" valign="bottom"><b>ss</b></td></tr> |
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| uint32_t </td><td class="memItemRight" valign="bottom"><b>eflags</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>dr0</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>dr1</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>dr2</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>dr7</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rcx</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rdx</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rbx</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rsp</b></td></tr> |
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| <tr class="memitem:a89d0f4d6202ae1a17e54bde25b8640bf"><td class="memItemLeft" align="right" valign="top"><a id="a89d0f4d6202ae1a17e54bde25b8640bf"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>rbp</b></td></tr> |
| <tr class="separator:a89d0f4d6202ae1a17e54bde25b8640bf"><td class="memSeparator" colspan="2"> </td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rsi</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>rdi</b></td></tr> |
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| uint64_t </td><td class="memItemRight" valign="bottom"><b>r8</b></td></tr> |
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| <tr class="memitem:a84f595eac39877108d64302f419f998f"><td class="memItemLeft" align="right" valign="top"><a id="a84f595eac39877108d64302f419f998f"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r9</b></td></tr> |
| <tr class="separator:a84f595eac39877108d64302f419f998f"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ad3286628398c9105a08ad839022adb39"><td class="memItemLeft" align="right" valign="top"><a id="ad3286628398c9105a08ad839022adb39"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r10</b></td></tr> |
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| <tr class="memitem:a9415020fc9b69f81a8337836e9d17c91"><td class="memItemLeft" align="right" valign="top"><a id="a9415020fc9b69f81a8337836e9d17c91"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r11</b></td></tr> |
| <tr class="separator:a9415020fc9b69f81a8337836e9d17c91"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a5dd5112e630183c9d1579543ea3e2a9d"><td class="memItemLeft" align="right" valign="top"><a id="a5dd5112e630183c9d1579543ea3e2a9d"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r12</b></td></tr> |
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| <tr class="memitem:a26a68c09a49f01f77667047c86ae9514"><td class="memItemLeft" align="right" valign="top"><a id="a26a68c09a49f01f77667047c86ae9514"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r13</b></td></tr> |
| <tr class="separator:a26a68c09a49f01f77667047c86ae9514"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ad34b33ba199433165c8a7dbf065de6f6"><td class="memItemLeft" align="right" valign="top"><a id="ad34b33ba199433165c8a7dbf065de6f6"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r14</b></td></tr> |
| <tr class="separator:ad34b33ba199433165c8a7dbf065de6f6"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a2d7c0f14ab185d7d0879e0235fc39e1c"><td class="memItemLeft" align="right" valign="top"><a id="a2d7c0f14ab185d7d0879e0235fc39e1c"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>r15</b></td></tr> |
| <tr class="separator:a2d7c0f14ab185d7d0879e0235fc39e1c"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a2cb073fc7b0e674c66ac7c260f1efc9a"><td class="memItemLeft" align="right" valign="top"><a id="a2cb073fc7b0e674c66ac7c260f1efc9a"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>rip</b></td></tr> |
| <tr class="separator:a2cb073fc7b0e674c66ac7c260f1efc9a"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a1ac65a6fc721914dc7e3213359a9afe2"><td class="memItemLeft" align="right" valign="top"><a id="a1ac65a6fc721914dc7e3213359a9afe2"></a> |
| <a class="el" href="structcrashpad_1_1CPUContextX86__64_1_1Fxsave.html">CPUContextX86_64::Fxsave</a> </td><td class="memItemRight" valign="bottom"><b>fxsave</b></td></tr> |
| <tr class="separator:a1ac65a6fc721914dc7e3213359a9afe2"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ac6c75c863540809be40f106c8a553f77"><td class="memItemLeft" align="right" valign="top"><a id="ac6c75c863540809be40f106c8a553f77"></a> |
| <a class="el" href="structcrashpad_1_1uint128__struct.html">uint128_struct</a> </td><td class="memItemRight" valign="bottom"><b>vector_register</b> [26]</td></tr> |
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| <tr class="memitem:a7a584ac26cb8014a7f295c2960b0f524"><td class="memItemLeft" align="right" valign="top"><a id="a7a584ac26cb8014a7f295c2960b0f524"></a> |
| uint64_t </td><td class="memItemRight" valign="bottom"><b>vector_control</b></td></tr> |
| <tr class="separator:a7a584ac26cb8014a7f295c2960b0f524"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr><td colspan="2"><div class="groupHeader"></div></td></tr> |
| <tr class="memitem:a271872f6ec607dd3a8d97a9bfcefbe13"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a271872f6ec607dd3a8d97a9bfcefbe13">p1_home</a></td></tr> |
| <tr class="memdesc:a271872f6ec607dd3a8d97a9bfcefbe13"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a271872f6ec607dd3a8d97a9bfcefbe13">More...</a><br /></td></tr> |
| <tr class="separator:a271872f6ec607dd3a8d97a9bfcefbe13"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:aa548961f860ebd3d074d72dfcf237cd6"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#aa548961f860ebd3d074d72dfcf237cd6">p2_home</a></td></tr> |
| <tr class="memdesc:aa548961f860ebd3d074d72dfcf237cd6"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#aa548961f860ebd3d074d72dfcf237cd6">More...</a><br /></td></tr> |
| <tr class="separator:aa548961f860ebd3d074d72dfcf237cd6"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ad3d714fb27531dc884be11e6f58404cd"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#ad3d714fb27531dc884be11e6f58404cd">p3_home</a></td></tr> |
| <tr class="memdesc:ad3d714fb27531dc884be11e6f58404cd"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#ad3d714fb27531dc884be11e6f58404cd">More...</a><br /></td></tr> |
| <tr class="separator:ad3d714fb27531dc884be11e6f58404cd"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a99325e3ed2c5dde13cb746e4464a6d67"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a99325e3ed2c5dde13cb746e4464a6d67">p4_home</a></td></tr> |
| <tr class="memdesc:a99325e3ed2c5dde13cb746e4464a6d67"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a99325e3ed2c5dde13cb746e4464a6d67">More...</a><br /></td></tr> |
| <tr class="separator:a99325e3ed2c5dde13cb746e4464a6d67"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a885ad96bcc6d7506490062255132bb14"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a885ad96bcc6d7506490062255132bb14">p5_home</a></td></tr> |
| <tr class="memdesc:a885ad96bcc6d7506490062255132bb14"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a885ad96bcc6d7506490062255132bb14">More...</a><br /></td></tr> |
| <tr class="separator:a885ad96bcc6d7506490062255132bb14"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ae6afc90e3d597f7db2f24b5a613e2490"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#ae6afc90e3d597f7db2f24b5a613e2490">p6_home</a></td></tr> |
| <tr class="memdesc:ae6afc90e3d597f7db2f24b5a613e2490"><td class="mdescLeft"> </td><td class="mdescRight">Register parameter home address. <a href="structcrashpad_1_1MinidumpContextAMD64.html#ae6afc90e3d597f7db2f24b5a613e2490">More...</a><br /></td></tr> |
| <tr class="separator:ae6afc90e3d597f7db2f24b5a613e2490"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr><td colspan="2"><div class="groupHeader"></div></td></tr> |
| <tr class="memitem:a65f302dd9d5ad77f4fca9cb0b176ac91"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a65f302dd9d5ad77f4fca9cb0b176ac91">debug_control</a></td></tr> |
| <tr class="memdesc:a65f302dd9d5ad77f4fca9cb0b176ac91"><td class="mdescLeft"> </td><td class="mdescRight">Model-specific debug extension register. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a65f302dd9d5ad77f4fca9cb0b176ac91">More...</a><br /></td></tr> |
| <tr class="separator:a65f302dd9d5ad77f4fca9cb0b176ac91"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a97d843d787b98ac66727eec0370f5fba"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a97d843d787b98ac66727eec0370f5fba">last_branch_to_rip</a></td></tr> |
| <tr class="memdesc:a97d843d787b98ac66727eec0370f5fba"><td class="mdescLeft"> </td><td class="mdescRight">Model-specific debug extension register. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a97d843d787b98ac66727eec0370f5fba">More...</a><br /></td></tr> |
| <tr class="separator:a97d843d787b98ac66727eec0370f5fba"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a12fa155fe145da64a263608a730a8bd0"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a12fa155fe145da64a263608a730a8bd0">last_branch_from_rip</a></td></tr> |
| <tr class="memdesc:a12fa155fe145da64a263608a730a8bd0"><td class="mdescLeft"> </td><td class="mdescRight">Model-specific debug extension register. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a12fa155fe145da64a263608a730a8bd0">More...</a><br /></td></tr> |
| <tr class="separator:a12fa155fe145da64a263608a730a8bd0"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a428db4b73e349e452c15f74aab491631"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a428db4b73e349e452c15f74aab491631">last_exception_to_rip</a></td></tr> |
| <tr class="memdesc:a428db4b73e349e452c15f74aab491631"><td class="mdescLeft"> </td><td class="mdescRight">Model-specific debug extension register. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a428db4b73e349e452c15f74aab491631">More...</a><br /></td></tr> |
| <tr class="separator:a428db4b73e349e452c15f74aab491631"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a9ccedfe70b69c6d4fd4479578a859698"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structcrashpad_1_1MinidumpContextAMD64.html#a9ccedfe70b69c6d4fd4479578a859698">last_exception_from_rip</a></td></tr> |
| <tr class="memdesc:a9ccedfe70b69c6d4fd4479578a859698"><td class="mdescLeft"> </td><td class="mdescRight">Model-specific debug extension register. <a href="structcrashpad_1_1MinidumpContextAMD64.html#a9ccedfe70b69c6d4fd4479578a859698">More...</a><br /></td></tr> |
| <tr class="separator:a9ccedfe70b69c6d4fd4479578a859698"><td class="memSeparator" colspan="2"> </td></tr> |
| </table> |
| <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> |
| <div class="textblock"><p>An x86_64 (AMD64) CPU context (register state) carried in a minidump file. </p> |
| <p>This is analogous to the <code>CONTEXT</code> structure on Windows when targeting x86_64. This structure is used instead of <code>CONTEXT</code> to make it available when targeting other architectures.</p> |
| <dl class="section note"><dt>Note</dt><dd>This structure doesn’t carry <code>dr4</code> or <code>dr5</code>, which are obsolete and normally alias <code>dr6</code> and <code>dr7</code>, respectively. See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-052), 17.2.2 “Debug Registers DR4 and DR5”. </dd></dl> |
| </div><h2 class="groupheader">Member Data Documentation</h2> |
| <a id="a086c5c2655800e91e080241317aa3ace"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a086c5c2655800e91e080241317aa3ace">◆ </a></span>context_flags</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint32_t crashpad::MinidumpContextAMD64::context_flags</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>A bitfield composed of values of <a class="el" href="namespacecrashpad.html#a835e6bd6cb3f97c99c572596878c1573" title="Architecture-independent flags for context_flags fields in Minidump context structures.">MinidumpContextFlags</a> and <a class="el" href="namespacecrashpad.html#aa197c419950bae99f1ba663f10b1891c" title="x86_64-specific flags for MinidumpContextAMD64::context_flags.">MinidumpContextAMD64Flags</a>. </p> |
| <p>This field identifies the context structure as an x86_64 CPU context, and indicates which other fields in the structure are valid. </p> |
| |
| </div> |
| </div> |
| <a id="a65f302dd9d5ad77f4fca9cb0b176ac91"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a65f302dd9d5ad77f4fca9cb0b176ac91">◆ </a></span>debug_control</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::debug_control</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Model-specific debug extension register. </p> |
| <p>See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording Overview”, and AMD Architecture Programmer’s Manual, Volume 2: System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint Features”. </p> |
| |
| </div> |
| </div> |
| <a id="a12fa155fe145da64a263608a730a8bd0"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a12fa155fe145da64a263608a730a8bd0">◆ </a></span>last_branch_from_rip</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::last_branch_from_rip</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Model-specific debug extension register. </p> |
| <p>See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording Overview”, and AMD Architecture Programmer’s Manual, Volume 2: System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint Features”. </p> |
| |
| </div> |
| </div> |
| <a id="a97d843d787b98ac66727eec0370f5fba"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a97d843d787b98ac66727eec0370f5fba">◆ </a></span>last_branch_to_rip</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::last_branch_to_rip</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Model-specific debug extension register. </p> |
| <p>See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording Overview”, and AMD Architecture Programmer’s Manual, Volume 2: System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint Features”. </p> |
| |
| </div> |
| </div> |
| <a id="a9ccedfe70b69c6d4fd4479578a859698"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a9ccedfe70b69c6d4fd4479578a859698">◆ </a></span>last_exception_from_rip</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::last_exception_from_rip</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Model-specific debug extension register. </p> |
| <p>See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording Overview”, and AMD Architecture Programmer’s Manual, Volume 2: System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint Features”. </p> |
| |
| </div> |
| </div> |
| <a id="a428db4b73e349e452c15f74aab491631"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a428db4b73e349e452c15f74aab491631">◆ </a></span>last_exception_to_rip</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::last_exception_to_rip</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Model-specific debug extension register. </p> |
| <p>See Intel Software Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording Overview”, and AMD Architecture Programmer’s Manual, Volume 2: System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint Features”. </p> |
| |
| </div> |
| </div> |
| <a id="a271872f6ec607dd3a8d97a9bfcefbe13"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a271872f6ec607dd3a8d97a9bfcefbe13">◆ </a></span>p1_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p1_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <a id="aa548961f860ebd3d074d72dfcf237cd6"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#aa548961f860ebd3d074d72dfcf237cd6">◆ </a></span>p2_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p2_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <a id="ad3d714fb27531dc884be11e6f58404cd"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#ad3d714fb27531dc884be11e6f58404cd">◆ </a></span>p3_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p3_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <a id="a99325e3ed2c5dde13cb746e4464a6d67"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a99325e3ed2c5dde13cb746e4464a6d67">◆ </a></span>p4_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p4_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <a id="a885ad96bcc6d7506490062255132bb14"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#a885ad96bcc6d7506490062255132bb14">◆ </a></span>p5_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p5_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <a id="ae6afc90e3d597f7db2f24b5a613e2490"></a> |
| <h2 class="memtitle"><span class="permalink"><a href="#ae6afc90e3d597f7db2f24b5a613e2490">◆ </a></span>p6_home</h2> |
| |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">uint64_t crashpad::MinidumpContextAMD64::p6_home</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Register parameter home address. </p> |
| <p>On Windows, this field may contain the “home” address (on-stack, in the shadow area) of a parameter passed by register. This field is present for convenience but is not necessarily populated, even if a corresponding parameter was passed by register. </p> |
| |
| </div> |
| </div> |
| <hr/>The documentation for this struct was generated from the following file:<ul> |
| <li>minidump/minidump_context.h</li> |
| </ul> |
| </div><!-- contents --> |
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