i#1551 port to ARM: add INSTR_CREATE_ macros for aliases
Adds macros for pop, pop_list, push, push_list, and neg.
git-svn-id: https://dynamorio.googlecode.com/svn/trunk@3015 49cc7528-f6fd-11dd-9d1a-b59b2e1864b6
diff --git a/core/arch/arm/instr_create.h b/core/arch/arm/instr_create.h
index 51c0c6e..7fdebd7 100644
--- a/core/arch/arm/instr_create.h
+++ b/core/arch/arm/instr_create.h
@@ -247,19 +247,57 @@
* Manually-added ARM-specific INSTR_CREATE_* macros
*/
-/** @name Alias with 1 destination, 0 sources */
-/* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */
/**
- * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given
- * explicit operands, automatically supplying any implicit operands.
+ * This macro creates an instr_t for a pop instruction into a single
+ * register, automatically supplying any implicit operands.
* \param dc The void * dcontext used to allocate memory for the instr_t.
- * \param d The opnd_t explicit destination operand for the instruction.
+ * \param Rd The destination register opnd_t operand.
*/
-#define INSTR_CREATE_pop(dc, d) \
- instr_create_2dst_2src((dc), OP_pop, (d), opnd_create_reg(DR_REG_XSP), \
- opnd_create_reg(DR_REG_XSP), \
- opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_VARSTACK))
-/* @} */ /* end doxygen group */
+#define INSTR_CREATE_pop(dc, Rd) \
+ INSTR_CREATE_ldr_wbimm((dc), (Rd), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), \
+ OPND_CREATE_INT16(sizeof(void*)))
+
+/**
+ * This macro creates an instr_t for a pop instruction into a list of
+ * registers, automatically supplying any implicit operands.
+ * \param dc The void * dcontext used to allocate memory for the instr_t.
+ * \param list_len The number of registers in the register list.
+ * \param ... The register list as separate opnd_t arguments.
+ */
+#define INSTR_CREATE_pop_list(dc, list_len, ...) \
+ INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), list_len, __VA_ARGS__)
+
+/**
+ * This macro creates an instr_t for a push instruction of a single
+ * register, automatically supplying any implicit operands.
+ * \param dc The void * dcontext used to allocate memory for the instr_t.
+ * \param Rd The destination register opnd_t operand.
+ */
+#define INSTR_CREATE_push(dc, Rt) \
+ INSTR_CREATE_str_wbimm((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), (Rt), \
+ OPND_CREATE_INT16(sizeof(void*)))
+
+/**
+ * This macro creates an instr_t for a push instruction of a list of
+ * registers, automatically supplying any implicit operands.
+ * \param dc The void * dcontext used to allocate memory for the instr_t.
+ * \param list_len The number of registers in the register list.
+ * \param ... The register list as separate opnd_t arguments.
+ */
+#define INSTR_CREATE_push_list(dc, list_len, ...) \
+ INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), list_len, __VA_ARGS__)
+
+/**
+ * This macro creates an instr_t for a negate instruction,
+ automatically supplying any implicit operands.
+ * \param dc The void * dcontext used to allocate memory for the instr_t.
+ * \param Rd The destination register opnd_t operand.
+ * \param Rn The source register opnd_t operand.
+ */
+#define INSTR_CREATE_neg(dc, Rd, Rn) \
+ INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0))
+
+/* XXX i#1551: add macros for the other opcode aliases */
/****************************************************************************
diff --git a/core/arch/arm/table_a32_pred.c b/core/arch/arm/table_a32_pred.c
index 6cd1b15..425b23f 100644
--- a/core/arch/arm/table_a32_pred.c
+++ b/core/arch/arm/table_a32_pred.c
@@ -131,7 +131,7 @@
{OP_ldrbt, 0x04700000, "ldrbt", RBw, RAw, Mb, RAw, n12, pred, x, top4y[11][0x00]},/*PUW=001*/
/* 48 */
{OP_str, 0x04800000, "str", Mw, RAw, RBw, RAw, i12, pred, x, top8[0x40]},/*PUW=010*/
- {OP_ldr, 0x04900000, "ldr", RBw, RAw, Mw, RAw, i12, pred, x, top8[0x41]},/*PUW=010*//* XXX: RA=SP + imm12=8, then "pop RBw" */
+ {OP_ldr, 0x04900000, "ldr", RBw, RAw, Mw, RAw, i12, pred, x, top8[0x41]},/*PUW=010*//* XXX: RA=SP + imm12=4, then "pop RBw" */
{OP_strt, 0x04a00000, "strt", Mw, RAw, RBw, RAw, i12, pred, x, top8[0x42]},/*PUW=011*/
{OP_ldrt, 0x04b00000, "ldrt", RBw, RAw, Mw, RAw, i12, pred, x, top8[0x43]},/*PUW=011*/
{OP_strb, 0x04c00000, "strb", Mb, RAw, RBb, RAw, i12, pred, x, top8[0x44]},/*PUW=010*/
@@ -141,7 +141,7 @@
/* 50 */
{OP_str, 0x05000000, "str", MN12w, xx, RBw, xx, xx, pred, x, top8[0x5a]},/*PUW=100*/
{OP_ldr, 0x05100000, "ldr", RBw, xx, MN12w, xx, xx, pred, x, top8[0x79]},/*PUW=100*/
- {OP_str, 0x05200000, "str", MN12w, RAw, RBw, RAw, n12, pred, x, tb4[3][0x00]},/*PUW=101*/
+ {OP_str, 0x05200000, "str", MN12w, RAw, RBw, RAw, n12, pred, x, tb4[3][0x00]},/*PUW=101*//* XXX: RA=SP + imm12=4, then "push RBw" */
{OP_ldr, 0x05300000, "ldr", RBw, RAw, MN12w, RAw, n12, pred, x, tb4[4][0x00]},/*PUW=101*/
{OP_strb, 0x05400000, "strb", MN12b, xx, RBb, xx, xx, pred, x, top8[0x5e]},/*PUW=100*/
{OP_ldrb, 0x05500000, "ldrb", RBw, xx, MN12b, xx, xx, pred, x, tb4[8][0x00]},/*PUW=100*/
@@ -205,7 +205,7 @@
{OP_stm, 0x08800000, "stm", Ml, xx, L16w, xx, xx, pred, x, END_LIST},/*PUW=010*//* XXX: "stmia" alias (used inconsistently by gdb) */
{OP_ldm, 0x08900000, "ldm", L16w, xx, Ml, xx, xx, pred, x, END_LIST},/*PUW=010*//* XXX: "ldmia" and "ldmfb" aliases */
{OP_stm, 0x08a00000, "stm", Ml, RAw, L16w, RAw, xx, pred, x, top8[0x88]},/*PUW=011*/
- {OP_ldm, 0x08b00000, "ldm", L16w, RAw, Ml, RAw, xx, pred, x, top8[0x89]},/*PUW=011*/
+ {OP_ldm, 0x08b00000, "ldm", L16w, RAw, Ml, RAw, xx, pred, x, top8[0x89]},/*PUW=011*//* XXX: RA=SP, then "pop <list>" */
{OP_stm_priv,0x08c00000, "stm", Ml, xx, L16w, xx, xx, pred, x, END_LIST},/*PUW=010*/
{OP_ldm_priv,0x08d00000, "ldm", L16w, xx, Ml, xx, xx, pred, x, END_LIST},/*PUW=010*/
{INVALID, 0x08e00000, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
