| /* ********************************************************** |
| * Copyright (c) 2011-2014 Google, Inc. All rights reserved. |
| * Copyright (c) 2002-2010 VMware, Inc. All rights reserved. |
| * **********************************************************/ |
| |
| /* |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * * Redistributions of source code must retain the above copyright notice, |
| * this list of conditions and the following disclaimer. |
| * |
| * * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * * Neither the name of VMware, Inc. nor the names of its contributors may be |
| * used to endorse or promote products derived from this software without |
| * specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE |
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| * DAMAGE. |
| */ |
| |
| /* Copyright (c) 2003-2007 Determina Corp. */ |
| /* Copyright (c) 2002-2003 Massachusetts Institute of Technology */ |
| |
| #ifndef _INSTR_CREATE_H_ |
| #define _INSTR_CREATE_H_ 1 |
| |
| #include "../instr_create_shared.h" |
| |
| /* DR_API EXPORT TOFILE dr_ir_macros_arm.h */ |
| /* DR_API EXPORT BEGIN */ |
| |
| /** |
| * Create an absolute address operand encoded as pc-relative. |
| * Encoding will fail if addr is out of the maximum signed displacement |
| * reach for the architecture and ISA mode. |
| */ |
| #define OPND_CREATE_ABSMEM(addr, size) \ |
| opnd_create_rel_addr(addr, size) |
| |
| /** Create a negated register operand. */ |
| #define OPND_CREATE_NEG_REG(reg) opnd_create_reg_ex(reg, 0, DR_OPND_NEGATED) |
| |
| /** The immediate opnd_t for use with OP_msr to write the nzcvq status flags. */ |
| #define OPND_CREATE_INT_MSR_NZCVQ() opnd_create_immed_int(0x8, OPSZ_4b) |
| |
| /** The immediate opnd_t for use with OP_msr to write the apsr_g status flags. */ |
| #define OPND_CREATE_INT_MSR_G() opnd_create_immed_int(0x8, OPSZ_4b) |
| |
| /** The immediate opnd_t for use with OP_msr to write the apsr_nzcvqg status flags. */ |
| #define OPND_CREATE_INT_MSR_NZCVQG() opnd_create_immed_int(0xc, OPSZ_4b) |
| |
| |
| /* Macros for building instructions, one for each opcode. |
| * Each INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The macro parameter types, encoded by name, are: |
| * dc = DR Context* |
| * op = uint = opcode |
| * s = opnd_t = source operand |
| * i = opnd_t = source operand that is an immediate |
| * ri = opnd_t = source operand that can be a register or an immediate |
| * t = opnd_t = source operand that is a jump target |
| * m = opnd_t = source operand that can only reference memory |
| * f = opnd_t = floating point register operand |
| * d = opnd_t = destination operand |
| */ |
| |
| /**************************************************************************** |
| * Platform-independent INSTR_CREATE_* macros |
| */ |
| /** @name Platform-independent macros */ |
| /* @{ */ /* doxygen start group */ |
| |
| /** |
| * This platform-independent macro creates an instr_t for a debug trap |
| * instruction, automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| */ |
| #define XINST_CREATE_debug_instr(dc) INSTR_CREATE_bkpt((dc), OPND_CREATE_INT8(1)) |
| |
| /** |
| * This platform-independent creates an instr_t for a memory load instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param r The destination register opnd. |
| * \param m The source memory opnd. |
| */ |
| #define XINST_CREATE_load(dc, r, m) INSTR_CREATE_ldr((dc), (r), (m)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a memory store instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param m The destination memory opnd. |
| * \param r The source register opnd. |
| */ |
| #define XINST_CREATE_store(dc, m, r) INSTR_CREATE_str((dc), (m), (r)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a register |
| * to register move instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The destination register opnd. |
| * \param s The source register opnd. |
| */ |
| #define XINST_CREATE_move(dc, d, s) INSTR_CREATE_mov((dc), (d), (s)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a multimedia |
| * register load instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param r The destination register opnd. |
| * \param m The source memory opnd. |
| * |
| * \note Loading to 128-bit registers is not supported on 32-bit ARM. |
| */ |
| #define XINST_CREATE_load_simd(dc, r, m) INSTR_CREATE_vldr((dc), (r), (m)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a multimedia |
| * register store instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param m The destination memory opnd. |
| * \param r The source register opnd. |
| * |
| * \note Storing from 128-bit registers is not supported on 32-bit ARM. |
| */ |
| #define XINST_CREATE_store_simd(dc, m, r) INSTR_CREATE_vstr((dc), (m), (r)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for an indirect |
| * jump through memory instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param m The memory opnd holding the target. |
| */ |
| #define XINST_CREATE_jump_mem(dc, m) \ |
| INSTR_CREATE_ldr((dc), opnd_create_reg(DR_REG_PC), (m)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for an immediate |
| * integer load instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param r The destination register opnd. |
| * \param i The source immediate integer opnd. |
| */ |
| #define XINST_CREATE_load_int(dc, r, i) \ |
| (opnd_get_immed_int(i) < 0 ? \ |
| INSTR_CREATE_mvn((dc), (r), OPND_CREATE_INTPTR(-opnd_get_immed_int(i))) : \ |
| INSTR_CREATE_movw((dc), (r), (i))) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a return instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| */ |
| #define XINST_CREATE_return(dc) INSTR_CREATE_pop(dc, opnd_create_reg(DR_REG_PC)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for an unconditional |
| * branch instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param t The opnd_t target operand for the instruction, which can be |
| * either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). |
| * Be sure to ensure that the limited reach of this short branch will reach |
| * the target (a pc operand is not suitable for most uses unless you know |
| * precisely where this instruction will be encoded). |
| */ |
| #define XINST_CREATE_jump(dc, t) INSTR_CREATE_b((dc), (t)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for an addition |
| * instruction that does not affect the status flags. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The opnd_t explicit destination operand for the instruction. |
| * \param s The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_add(dc, d, s) INSTR_CREATE_add((dc), (d), (d), (s)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for an addition |
| * instruction that does affect the status flags. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The opnd_t explicit destination operand for the instruction. |
| * \param s The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_add_s(dc, d, s) INSTR_CREATE_adds((dc), (d), (d), (s)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a subtraction |
| * instruction that does not affect the status flags. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The opnd_t explicit destination operand for the instruction. |
| * \param s The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_sub(dc, d, s) INSTR_CREATE_sub((dc), (d), (d), (s)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a subtraction |
| * instruction that does affect the status flags. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The opnd_t explicit destination operand for the instruction. |
| * \param s The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_sub_s(dc, d, s) INSTR_CREATE_subs((dc), (d), (d), (s)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a bitwise and |
| * instruction that does affect the status flags. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param d The opnd_t explicit destination operand for the instruction. |
| * \param s The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_and_s(dc, d, s) \ |
| instr_create_1dst_2src((dc), OP_ands, (d), (s), (d)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a comparison |
| * instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param s1 The opnd_t explicit destination operand for the instruction. |
| * \param s2 The opnd_t explicit source operand for the instruction. |
| */ |
| #define XINST_CREATE_cmp(dc, s1, s2) \ |
| instr_create_0dst_2src((dc), OP_cmp, (s1), (s2)) |
| |
| /** |
| * This platform-independent macro creates an instr_t for a software |
| * interrupt instruction. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param i The source integer constant opnd_t operand. |
| */ |
| #define XINST_CREATE_interrupt(dc, i) INSTR_CREATE_svc(dc, (i)) |
| /* @} */ /* end doxygen group */ |
| |
| |
| /**************************************************************************** |
| * Manually-added ARM-specific INSTR_CREATE_* macros |
| */ |
| |
| /** |
| * This macro creates an instr_t for a pop instruction into a single |
| * register, automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| */ |
| #define INSTR_CREATE_pop(dc, Rd) \ |
| INSTR_CREATE_ldr_wbimm((dc), (Rd), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), \ |
| OPND_CREATE_INT16(sizeof(void*))) |
| |
| /** |
| * This macro creates an instr_t for a pop instruction into a list of |
| * registers, automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_pop_list(dc, list_len, ...) \ |
| INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), list_len, __VA_ARGS__) |
| |
| /** |
| * This macro creates an instr_t for a push instruction of a single |
| * register, automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| */ |
| #define INSTR_CREATE_push(dc, Rt) \ |
| INSTR_CREATE_str_wbimm((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), (Rt), \ |
| OPND_CREATE_INT16(sizeof(void*))) |
| |
| /** |
| * This macro creates an instr_t for a push instruction of a list of |
| * registers, automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_push_list(dc, list_len, ...) \ |
| INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), list_len, __VA_ARGS__) |
| |
| /** |
| * This macro creates an instr_t for a negate instruction, |
| automatically supplying any implicit operands. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_neg(dc, Rd, Rn) \ |
| INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0)) |
| |
| /* XXX i#1551: add macros for the other opcode aliases */ |
| |
| |
| /**************************************************************************** |
| * Automatically-generated ARM-specific INSTR_CREATE_* macros. |
| * These were generated from tools/arm_macros_gen.pl. |
| * DO NOT EDIT THESE MANUALLY so we can continue using the script for easy |
| * updates on table changes. |
| */ |
| |
| /** @name Signature: () */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| */ |
| #define INSTR_CREATE_clrex(dc) \ |
| instr_create_0dst_0src((dc), OP_clrex) |
| #define INSTR_CREATE_eret(dc) \ |
| instr_create_0dst_0src((dc), OP_eret) |
| #define INSTR_CREATE_nop(dc) \ |
| instr_create_0dst_0src((dc), OP_nop) |
| #define INSTR_CREATE_sev(dc) \ |
| instr_create_0dst_0src((dc), OP_sev) |
| #define INSTR_CREATE_sevl(dc) \ |
| instr_create_0dst_0src((dc), OP_sevl) |
| #define INSTR_CREATE_wfe(dc) \ |
| instr_create_0dst_0src((dc), OP_wfe) |
| #define INSTR_CREATE_wfi(dc) \ |
| instr_create_0dst_0src((dc), OP_wfi) |
| #define INSTR_CREATE_yield(dc) \ |
| instr_create_0dst_0src((dc), OP_yield) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| */ |
| #define INSTR_CREATE_vmrs(dc, Rd) \ |
| instr_create_1dst_1src((dc), OP_vmrs, (Rd), opnd_create_reg(DR_REG_FPSCR)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_blx_ind(dc, Rm) \ |
| instr_create_1dst_1src((dc), OP_blx_ind, opnd_create_reg(DR_REG_LR), (Rm)) |
| #define INSTR_CREATE_bx(dc, Rm) \ |
| instr_create_0dst_1src((dc), OP_bx, (Rm)) |
| #define INSTR_CREATE_bxj(dc, Rm) \ |
| instr_create_0dst_1src((dc), OP_bxj, (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rt) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rt The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_vmsr(dc, Rt) \ |
| instr_create_1dst_1src((dc), OP_vmsr, opnd_create_reg(DR_REG_FPSCR), (Rt)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_clz(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_clz, (Rd), (Rm)) |
| #define INSTR_CREATE_rbit(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_rbit, (Rd), (Rm)) |
| #define INSTR_CREATE_rev(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_rev, (Rd), (Rm)) |
| #define INSTR_CREATE_rev16(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_rev16, (Rd), (Rm)) |
| #define INSTR_CREATE_revsh(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_revsh, (Rd), (Rm)) |
| #define INSTR_CREATE_rrx(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_rrx, (Rd), (Rm)) |
| #define INSTR_CREATE_rrxs(dc, Rd, Rm) \ |
| instr_create_1dst_1src((dc), OP_rrxs, (Rd), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, statreg) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param statreg The status register (usually DR_REG_CPSR) opnd_t operand. |
| */ |
| #define INSTR_CREATE_mrs(dc, Rd, statreg) \ |
| instr_create_1dst_1src((dc), OP_mrs, (Rd), (statreg)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm, Rn) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_qsub(dc, Rd, Rm, Rn) \ |
| instr_create_1dst_2src((dc), OP_qsub, (Rd), (Rm), (Rn)) |
| #define INSTR_CREATE_smulbb(dc, Rd, Rm, Rn) \ |
| instr_create_1dst_2src((dc), OP_smulbb, (Rd), (Rm), (Rn)) |
| #define INSTR_CREATE_smulbt(dc, Rd, Rm, Rn) \ |
| instr_create_1dst_2src((dc), OP_smulbt, (Rd), (Rm), (Rn)) |
| #define INSTR_CREATE_smultb(dc, Rd, Rm, Rn) \ |
| instr_create_1dst_2src((dc), OP_smultb, (Rd), (Rm), (Rn)) |
| #define INSTR_CREATE_smultt(dc, Rd, Rm, Rn) \ |
| instr_create_1dst_2src((dc), OP_smultt, (Rd), (Rm), (Rn)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_crc32b(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32b, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_crc32cb(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32cb, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_crc32ch(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32ch, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_crc32cw(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32cw, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_crc32h(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32h, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_crc32w(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_crc32w, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_mul(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_mul, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_muls(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_muls, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qadd(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qadd, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qdadd(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qdadd, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qdsub(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qdsub, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qsax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qsax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qsub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qsub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_qsub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_qsub8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_sadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_sadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_sadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_sadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_sasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_sasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_sdiv(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_sdiv, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_sel(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_sel, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shsax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shsax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shsub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shsub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_shsub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_shsub8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_smulwb(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_smulwb, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_smulwt(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_smulwt, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_ssax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_ssax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_ssub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_ssub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_ssub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_ssub8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_udiv(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_udiv, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhsax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhsax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhsub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhsub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uhsub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uhsub8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqadd16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqadd16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqadd8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqadd8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqasx(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqasx, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqsax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqsax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqsub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqsub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_uqsub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_uqsub8, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_usax(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_usax, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_usub16(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_usub16, (Rd), (Rn), (Rm)) |
| #define INSTR_CREATE_usub8(dc, Rd, Rn, Rm) \ |
| instr_create_1dst_2src((dc), OP_usub8, (Rd), (Rn), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm, Ra) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param Ra The third source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_mla(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_mla, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_mlas(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_mlas, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_mls(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_mls, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlabb(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlabb, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlabt(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlabt, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlad(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlad, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smladx(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smladx, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlatb(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlatb, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlatt(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlatt, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlawb(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlawb, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smlawt(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smlawt, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smmla(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smmla, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smmlar(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smmlar, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smmls(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smmls, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_smmlsr(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_smmlsr, (Rd), (Rn), (Rm), (Ra)) |
| #define INSTR_CREATE_usada8(dc, Rd, Rn, Rm, Ra) \ |
| instr_create_1dst_3src((dc), OP_usada8, (Rd), (Rn), (Rm), (Ra)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rd2, Rm, Rn) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rd2 The second destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_smlalbb(dc, Rd, Rd2, Rm, Rn) \ |
| instr_create_2dst_4src((dc), OP_smlalbb, (Rd), (Rd2), (Rd), (Rd2), (Rm), (Rn)) |
| #define INSTR_CREATE_smlalbt(dc, Rd, Rd2, Rm, Rn) \ |
| instr_create_2dst_4src((dc), OP_smlalbt, (Rd), (Rd2), (Rd), (Rd2), (Rm), (Rn)) |
| #define INSTR_CREATE_smlaltb(dc, Rd, Rd2, Rm, Rn) \ |
| instr_create_2dst_4src((dc), OP_smlaltb, (Rd), (Rd2), (Rd), (Rd2), (Rm), (Rn)) |
| #define INSTR_CREATE_smlaltt(dc, Rd, Rd2, Rm, Rn) \ |
| instr_create_2dst_4src((dc), OP_smlaltt, (Rd), (Rd2), (Rd), (Rd2), (Rm), (Rn)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rd2, Rn, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rd2 The second destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_smlal(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlal, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlald(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlald, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlaldx(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlaldx, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlals(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlals, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlsd(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlsd, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlsdx(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlsdx, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlsld(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlsld, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smlsldx(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smlsldx, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smull(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smull, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_smulls(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_smulls, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_umaal(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_umaal, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_umlal(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_umlal, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_umlals(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_umlals, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_umull(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_umull, (Rd), (Rd2), (Rn), (Rm)) |
| #define INSTR_CREATE_umulls(dc, Rd, Rd2, Rn, Rm) \ |
| instr_create_2dst_2src((dc), OP_umulls, (Rd), (Rd2), (Rn), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_b(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_b, (imm)) |
| #define INSTR_CREATE_bkpt(dc, imm) \ |
| instr_create_1dst_0src((dc), OP_bkpt, (imm)) |
| #define INSTR_CREATE_bl(dc, imm) \ |
| instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_LR), (imm)) |
| #define INSTR_CREATE_blx(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_blx, (imm)) |
| #define INSTR_CREATE_cps(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_cps, (imm)) |
| #define INSTR_CREATE_cpsid(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_cpsid, (imm)) |
| #define INSTR_CREATE_cpsie(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_cpsie, (imm)) |
| #define INSTR_CREATE_dbg(dc, imm) \ |
| instr_create_1dst_0src((dc), OP_dbg, (imm)) |
| #define INSTR_CREATE_dmb(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_dmb, (imm)) |
| #define INSTR_CREATE_dsb(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_dsb, (imm)) |
| #define INSTR_CREATE_hlt(dc, imm) \ |
| instr_create_1dst_0src((dc), OP_hlt, (imm)) |
| #define INSTR_CREATE_hvc(dc, imm) \ |
| instr_create_1dst_0src((dc), OP_hvc, (imm)) |
| #define INSTR_CREATE_isb(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_isb, (imm)) |
| #define INSTR_CREATE_setend(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_setend, (imm)) |
| #define INSTR_CREATE_smc(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_smc, (imm)) |
| #define INSTR_CREATE_svc(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_svc, (imm)) |
| #define INSTR_CREATE_udf(dc, imm) \ |
| instr_create_0dst_1src((dc), OP_udf, (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_movt(dc, Rd, imm) \ |
| instr_create_1dst_1src((dc), OP_movt, (Rd), (imm)) |
| #define INSTR_CREATE_movw(dc, Rd, imm) \ |
| instr_create_1dst_1src((dc), OP_movw, (Rd), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (imm, imm2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param imm The integer constant opnd_t operand. |
| * \param imm2 The second integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_cpsid_noflags(dc, imm, imm2) \ |
| instr_create_0dst_2src((dc), OP_cpsid, (imm), (imm2)) |
| #define INSTR_CREATE_cpsie_noflags(dc, imm, imm2) \ |
| instr_create_0dst_2src((dc), OP_cpsie, (imm), (imm2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm_or_imm The source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_mov(dc, Rd, Rm_or_imm) \ |
| instr_create_1dst_1src((dc), OP_mov, (Rd), (Rm_or_imm)) |
| #define INSTR_CREATE_movs(dc, Rd, Rm_or_imm) \ |
| instr_create_1dst_1src((dc), OP_movs, (Rd), (Rm_or_imm)) |
| #define INSTR_CREATE_mvn(dc, Rd, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_mvn_shimm((dc), (Rd), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_1src((dc), OP_mvn, (Rd), (Rm_or_imm))) |
| #define INSTR_CREATE_mvns(dc, Rd, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_mvns_shimm((dc), (Rd), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_1src((dc), OP_mvns, (Rd), (Rm_or_imm))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rn, Rm_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm_or_imm The second source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_cmn(dc, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_cmn_shimm((dc), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_0dst_2src((dc), OP_cmn, (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_cmp(dc, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_cmp_shimm((dc), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_0dst_2src((dc), OP_cmp, (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_teq(dc, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_teq_shimm((dc), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_0dst_2src((dc), OP_teq, (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_tst(dc, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_tst_shimm((dc), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_0dst_2src((dc), OP_tst, (Rn), (Rm_or_imm))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, imm, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_ssat16(dc, Rd, imm, Rm) \ |
| instr_create_1dst_2src((dc), OP_ssat16, (Rd), (imm), (Rm)) |
| #define INSTR_CREATE_usat16(dc, Rd, imm, Rm) \ |
| instr_create_1dst_2src((dc), OP_usat16, (Rd), (imm), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, imm, imm2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param imm2 The second integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_bfc(dc, Rd, imm, imm2) \ |
| instr_create_1dst_2src((dc), OP_bfc, (Rd), (imm), (imm2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm, Rn_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param Rn_or_imm The source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_asr(dc, Rd, Rm, Rn_or_imm) \ |
| instr_create_1dst_2src((dc), OP_asr, (Rd), (Rm), (Rn_or_imm)) |
| #define INSTR_CREATE_asrs(dc, Rd, Rm, Rn_or_imm) \ |
| instr_create_1dst_2src((dc), OP_asrs, (Rd), (Rm), (Rn_or_imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm_or_imm The second source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_adc(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_adc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_adc, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_adcs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_adcs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_adcs, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_add(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_add_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_add, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_adds(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_adds_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_adds, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_and(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_and_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_and, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_ands(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_ands_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_ands, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_bic(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_bic_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_bic, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_bics(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_bics_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_bics, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_eor(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_eor_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_eor, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_eors(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_eors_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_eors, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_lsl(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_lsl, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_lsls(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_lsls, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_lsr(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_lsr, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_lsrs(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_lsrs, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_orr(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_orr_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_orr, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_orrs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_orrs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_orrs, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_ror(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_ror, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_rors(dc, Rd, Rn, Rm_or_imm) \ |
| instr_create_1dst_2src((dc), OP_rors, (Rd), (Rn), (Rm_or_imm)) |
| #define INSTR_CREATE_rsb(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_rsb_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_rsb, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_rsbs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_rsbs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_rsbs, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_rsc(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_rsc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_rsc, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_rscs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_rscs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_rscs, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_sbc(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_sbc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_sbc, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_sbcs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_sbcs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_sbcs, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_sub(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_sub_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_sub, (Rd), (Rn), (Rm_or_imm))) |
| #define INSTR_CREATE_subs(dc, Rd, Rn, Rm_or_imm) \ |
| (opnd_is_reg(Rm_or_imm) ? \ |
| INSTR_CREATE_subs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \ |
| OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) : \ |
| instr_create_1dst_2src((dc), OP_subs, (Rd), (Rn), (Rm_or_imm))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, statreg, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param statreg The status register (usually DR_REG_CPSR) opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_mrs_priv(dc, Rd, statreg, imm) \ |
| instr_create_1dst_2src((dc), OP_mrs_priv, (Rd), (statreg), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (statreg, imm, Rn) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param statreg The status register (usually DR_REG_CPSR) opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_msr_priv(dc, statreg, imm, Rn) \ |
| instr_create_1dst_2src((dc), OP_msr_priv, (statreg), (imm), (Rn)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (statreg, imm, imm2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param statreg The status register (usually DR_REG_CPSR) opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param imm2 The second integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_msr_imm(dc, statreg, imm, imm2) \ |
| instr_create_1dst_2src((dc), OP_msr, (statreg), (imm), (imm2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (statreg, imm_msr, Rn) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param statreg The status register (usually DR_REG_CPSR) opnd_t operand. |
| * \param imm_msr The integer constant (typically from OPND_CREATE_INT_MSR*) opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_msr(dc, statreg, imm_msr, Rn) \ |
| instr_create_1dst_2src((dc), OP_msr, (statreg), (imm_msr), (Rn)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_sxtab(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_sxtab, (Rd), (Rn), (Rm), (imm)) |
| #define INSTR_CREATE_sxtab16(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_sxtab16, (Rd), (Rn), (Rm), (imm)) |
| #define INSTR_CREATE_sxtah(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_sxtah, (Rd), (Rn), (Rm), (imm)) |
| #define INSTR_CREATE_uxtab(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_uxtab, (Rd), (Rn), (Rm), (imm)) |
| #define INSTR_CREATE_uxtab16(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_uxtab16, (Rd), (Rn), (Rm), (imm)) |
| #define INSTR_CREATE_uxtah(dc, Rd, Rn, Rm, imm) \ |
| instr_create_1dst_3src((dc), OP_uxtah, (Rd), (Rn), (Rm), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm, imm, imm2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param imm2 The second integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_bfi(dc, Rd, Rm, imm, imm2) \ |
| instr_create_1dst_3src((dc), OP_bfi, (Rd), (Rm), (imm), (imm2)) |
| #define INSTR_CREATE_sbfx(dc, Rd, Rm, imm, imm2) \ |
| instr_create_1dst_3src((dc), OP_sbfx, (Rd), (Rm), (imm), (imm2)) |
| #define INSTR_CREATE_ubfx(dc, Rd, Rm, imm, imm2) \ |
| instr_create_1dst_3src((dc), OP_ubfx, (Rd), (Rm), (imm), (imm2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm, shift, Rs) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param Rs The third source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_mvn_shreg(dc, Rd, Rm, shift, Rs) \ |
| instr_create_1dst_3src((dc), OP_mvn, (Rd), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_mvns_shreg(dc, Rd, Rm, shift, Rs) \ |
| instr_create_1dst_3src((dc), OP_mvns, (Rd), (Rm), (shift), (Rs)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rn, Rm, shift, Rs) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param Rs The third source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_cmn_shreg(dc, Rn, Rm, shift, Rs) \ |
| instr_create_0dst_4src((dc), OP_cmn, (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_cmp_shreg(dc, Rn, Rm, shift, Rs) \ |
| instr_create_0dst_4src((dc), OP_cmp, (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_teq_shreg(dc, Rn, Rm, shift, Rs) \ |
| instr_create_0dst_4src((dc), OP_teq, (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_tst_shreg(dc, Rn, Rm, shift, Rs) \ |
| instr_create_0dst_4src((dc), OP_tst, (Rn), (Rm), (shift), (Rs)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm, shift, Rs) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param Rs The third source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_adc_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_adc, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_adcs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_adcs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_add_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_add, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_adds_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_adds, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_and_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_and, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_ands_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_ands, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_bic_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_bic, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_bics_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_bics, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_eor_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_eor, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_eors_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_eors, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_orr_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_orr, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_orrs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_orrs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_rsb_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_rsb, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_rsbs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_rsbs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_rsc_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_rsc, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_rscs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_rscs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_sbc_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_sbc, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_sbcs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_sbcs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_sub_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_sub, (Rd), (Rn), (Rm), (shift), (Rs)) |
| #define INSTR_CREATE_subs_shreg(dc, Rd, Rn, Rm, shift, Rs) \ |
| instr_create_1dst_4src((dc), OP_subs, (Rd), (Rn), (Rm), (shift), (Rs)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rm, shift, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_mvn_shimm(dc, Rd, Rm, shift, imm) \ |
| instr_create_1dst_3src((dc), OP_mvn, (Rd), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_mvns_shimm(dc, Rd, Rm, shift, imm) \ |
| instr_create_1dst_3src((dc), OP_mvns, (Rd), (Rm), (shift), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rn, Rm, shift, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_cmn_shimm(dc, Rn, Rm, shift, imm) \ |
| instr_create_0dst_4src((dc), OP_cmn, (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_cmp_shimm(dc, Rn, Rm, shift, imm) \ |
| instr_create_0dst_4src((dc), OP_cmp, (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_teq_shimm(dc, Rn, Rm, shift, imm) \ |
| instr_create_0dst_4src((dc), OP_teq, (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_tst_shimm(dc, Rn, Rm, shift, imm) \ |
| instr_create_0dst_4src((dc), OP_tst, (Rn), (Rm), (shift), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rn, Rm, shift, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rn The source register opnd_t operand. |
| * \param Rm The second source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_adc_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_adc, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_adcs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_adcs, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_add_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_add, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_adds_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_adds, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_and_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_and, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_ands_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_ands, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_bic_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_bic, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_bics_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_bics, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_eor_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_eor, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_eors_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_eors, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_orr_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_orr, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_orrs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_orrs, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_pkhbt_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_pkhbt, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_pkhtb_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_pkhtb, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_rsb_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_rsb, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_rsbs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_rsbs, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_rsc_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_rsc, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_rscs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_rscs, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_sbc_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_sbc, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_sbcs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_sbcs, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_sub_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_sub, (Rd), (Rn), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_subs_shimm(dc, Rd, Rn, Rm, shift, imm) \ |
| instr_create_1dst_4src((dc), OP_subs, (Rd), (Rn), (Rm), (shift), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, imm, Rm, shift, imm2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm2 The second integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_ssat_shimm(dc, Rd, imm, Rm, shift, imm2) \ |
| instr_create_1dst_4src((dc), OP_ssat, (Rd), (imm), (Rm), (shift), (imm2)) |
| #define INSTR_CREATE_usat_shimm(dc, Rd, imm, Rm, shift, imm2) \ |
| instr_create_1dst_4src((dc), OP_usat, (Rd), (imm), (Rm), (shift), (imm2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| */ |
| #define INSTR_CREATE_pld(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_pld, (mem)) |
| #define INSTR_CREATE_pldw(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_pldw, (mem)) |
| #define INSTR_CREATE_pli(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_pli, (mem)) |
| #define INSTR_CREATE_rfeda(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_rfeda, (mem)) |
| #define INSTR_CREATE_rfeda_wb(dc, mem) \ |
| instr_create_1dst_2src((dc), OP_rfeda, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_rfedb(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_rfedb, (mem)) |
| #define INSTR_CREATE_rfedb_wb(dc, mem) \ |
| instr_create_1dst_2src((dc), OP_rfedb, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_rfeia(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_rfeia, (mem)) |
| #define INSTR_CREATE_rfeia_wb(dc, mem) \ |
| instr_create_1dst_2src((dc), OP_rfeia, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_rfeib(dc, mem) \ |
| instr_create_0dst_1src((dc), OP_rfeib, (mem)) |
| #define INSTR_CREATE_rfeib_wb(dc, mem) \ |
| instr_create_1dst_2src((dc), OP_rfeib, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_srsda(dc, mem) \ |
| instr_create_1dst_0src((dc), OP_srsda, (mem)) |
| #define INSTR_CREATE_srsda_wb(dc, mem) \ |
| instr_create_2dst_1src((dc), OP_srsda, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_srsdb(dc, mem) \ |
| instr_create_1dst_0src((dc), OP_srsdb, (mem)) |
| #define INSTR_CREATE_srsdb_wb(dc, mem) \ |
| instr_create_2dst_1src((dc), OP_srsdb, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_srsia(dc, mem) \ |
| instr_create_1dst_0src((dc), OP_srsia, (mem)) |
| #define INSTR_CREATE_srsia_wb(dc, mem) \ |
| instr_create_2dst_1src((dc), OP_srsia, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem))) |
| #define INSTR_CREATE_srsib(dc, mem) \ |
| instr_create_1dst_0src((dc), OP_srsib, (mem)) |
| #define INSTR_CREATE_srsib_wb(dc, mem) \ |
| instr_create_2dst_1src((dc), OP_srsib, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| */ |
| #define INSTR_CREATE_lda(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_lda, (Rd), (mem)) |
| #define INSTR_CREATE_ldab(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldab, (Rd), (mem)) |
| #define INSTR_CREATE_ldaex(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldaex, (Rd), (mem)) |
| #define INSTR_CREATE_ldaexb(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldaexb, (Rd), (mem)) |
| #define INSTR_CREATE_ldaexh(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldaexh, (Rd), (mem)) |
| #define INSTR_CREATE_ldah(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldah, (Rd), (mem)) |
| #define INSTR_CREATE_ldr(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldr, (Rd), (mem)) |
| #define INSTR_CREATE_ldrb(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrb, (Rd), (mem)) |
| #define INSTR_CREATE_ldrex(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrex, (Rd), (mem)) |
| #define INSTR_CREATE_ldrexb(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrexb, (Rd), (mem)) |
| #define INSTR_CREATE_ldrexh(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrexh, (Rd), (mem)) |
| #define INSTR_CREATE_ldrh(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrh, (Rd), (mem)) |
| #define INSTR_CREATE_ldrsb(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrsb, (Rd), (mem)) |
| #define INSTR_CREATE_ldrsh(dc, Rd, mem) \ |
| instr_create_1dst_1src((dc), OP_ldrsh, (Rd), (mem)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_stl(dc, mem, Rm) \ |
| instr_create_1dst_1src((dc), OP_stl, (mem), (Rm)) |
| #define INSTR_CREATE_stlb(dc, mem, Rm) \ |
| instr_create_1dst_1src((dc), OP_stlb, (mem), (Rm)) |
| #define INSTR_CREATE_stlh(dc, mem, Rm) \ |
| instr_create_1dst_1src((dc), OP_stlh, (mem), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_str(dc, mem, Rt) \ |
| instr_create_1dst_1src((dc), OP_str, (mem), (Rt)) |
| #define INSTR_CREATE_strb(dc, mem, Rt) \ |
| instr_create_1dst_1src((dc), OP_strb, (mem), (Rt)) |
| #define INSTR_CREATE_strh(dc, mem, Rt) \ |
| instr_create_1dst_1src((dc), OP_strh, (mem), (Rt)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rd2, mem) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rd2 The second destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldaexd(dc, Rd, Rd2, mem) \ |
| instr_create_2dst_1src((dc), OP_ldaexd, (Rd), (Rd2), (mem)) |
| #define INSTR_CREATE_ldrd(dc, Rd, Rd2, mem) \ |
| instr_create_2dst_1src((dc), OP_ldrd, (Rd), (Rd2), (mem)) |
| #define INSTR_CREATE_ldrexd(dc, Rd, Rd2, mem) \ |
| instr_create_2dst_1src((dc), OP_ldrexd, (Rd), (Rd2), (mem)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldrh_wbreg(dc, Rd, mem, Rm) \ |
| instr_create_2dst_3src((dc), OP_ldrh, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm)) |
| #define INSTR_CREATE_ldrsb_wbreg(dc, Rd, mem, Rm) \ |
| instr_create_2dst_3src((dc), OP_ldrsb, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm)) |
| #define INSTR_CREATE_ldrsh_wbreg(dc, Rd, mem, Rm) \ |
| instr_create_2dst_3src((dc), OP_ldrsh, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rd, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_stlex(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_stlex, (mem), (Rd), (Rm)) |
| #define INSTR_CREATE_stlexb(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_stlexb, (mem), (Rd), (Rm)) |
| #define INSTR_CREATE_stlexh(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_stlexh, (mem), (Rd), (Rm)) |
| #define INSTR_CREATE_strex(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_strex, (mem), (Rd), (Rm)) |
| #define INSTR_CREATE_strexb(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_strexb, (mem), (Rd), (Rm)) |
| #define INSTR_CREATE_strexh(dc, mem, Rd, Rm) \ |
| instr_create_2dst_1src((dc), OP_strexh, (mem), (Rd), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_strh_wbreg(dc, mem, Rt, Rm) \ |
| instr_create_2dst_3src((dc), OP_strh, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rt2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rt2 The second source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_strd(dc, mem, Rt, Rt2) \ |
| instr_create_1dst_2src((dc), OP_strd, (mem), (Rt), (Rt2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rd2, mem, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rd2 The second destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldrd_wbreg(dc, Rd, Rd2, mem, Rm) \ |
| instr_create_3dst_3src((dc), OP_ldrd, (Rd), (Rd2), opnd_create_reg(opnd_get_base(mem)), (mem), (Rm), opnd_create_reg(opnd_get_base(mem))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rd, Rt, Rt2) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rt2 The second source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_stlexd(dc, mem, Rd, Rt, Rt2) \ |
| instr_create_2dst_2src((dc), OP_stlexd, (mem), (Rd), (Rt), (Rt2)) |
| #define INSTR_CREATE_strexd(dc, mem, Rd, Rt, Rt2) \ |
| instr_create_2dst_2src((dc), OP_strexd, (mem), (Rd), (Rt), (Rt2)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rt2, Rm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rt2 The second source register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| */ |
| #define INSTR_CREATE_strd_wbreg(dc, mem, Rt, Rt2, Rm) \ |
| instr_create_2dst_4src((dc), OP_strd, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), (Rt2), (Rm), opnd_create_reg(opnd_get_base(mem))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldr_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldr, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrb_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrb, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrbt_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrbt, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrh_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrh, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrsb_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrsb, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrsh_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrsh, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_ldrt_wbimm(dc, Rd, mem, imm) \ |
| instr_create_2dst_3src((dc), OP_ldrt, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_str_wbimm(dc, mem, Rt, imm) \ |
| instr_create_2dst_3src((dc), OP_str, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_strb_wbimm(dc, mem, Rt, imm) \ |
| instr_create_2dst_3src((dc), OP_strb, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_strbt_wbimm(dc, mem, Rt, imm) \ |
| instr_create_2dst_3src((dc), OP_strbt, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_strh_wbimm(dc, mem, Rt, imm) \ |
| instr_create_2dst_3src((dc), OP_strh, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| #define INSTR_CREATE_strt_wbimm(dc, mem, Rt, imm) \ |
| instr_create_2dst_3src((dc), OP_strt, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem, Rm_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param Rm_or_imm The source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldrht_wbreg(dc, Rd, mem, Rm_or_imm) \ |
| instr_create_2dst_3src((dc), OP_ldrht, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm_or_imm)) |
| #define INSTR_CREATE_ldrsbt_wbreg(dc, Rd, mem, Rm_or_imm) \ |
| instr_create_2dst_3src((dc), OP_ldrsbt, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm_or_imm)) |
| #define INSTR_CREATE_ldrsht_wbreg(dc, Rd, mem, Rm_or_imm) \ |
| instr_create_2dst_3src((dc), OP_ldrsht, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm_or_imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rm_or_imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rm_or_imm The source register, or integer constant, opnd_t operand. |
| */ |
| #define INSTR_CREATE_strht_wbreg(dc, mem, Rt, Rm_or_imm) \ |
| instr_create_2dst_3src((dc), OP_strht, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm_or_imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, Rd2, mem, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param Rd2 The second destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldrd_wbimm(dc, Rd, Rd2, mem, imm) \ |
| instr_create_3dst_3src((dc), OP_ldrd, (Rd), (Rd2), opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rt2, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rt2 The second source register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_strd_wbimm(dc, mem, Rt, Rt2, imm) \ |
| instr_create_2dst_4src((dc), OP_strd, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), (Rt2), (imm), opnd_create_reg(opnd_get_base(mem))) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem, Rm, shift, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_ldr_wbreg(dc, Rd, mem, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_ldr, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_ldrb_wbreg(dc, Rd, mem, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_ldrb, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_ldrbt_wbreg(dc, Rd, mem, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_ldrbt, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_ldrt_wbreg(dc, Rd, mem, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_ldrt, (Rd), opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rt, Rm, shift, imm) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rt The source register opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param shift The shift type integer constant opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| */ |
| #define INSTR_CREATE_str_wbreg(dc, mem, Rt, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_str, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_strb_wbreg(dc, mem, Rt, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_strb, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_strbt_wbreg(dc, mem, Rt, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_strbt, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| #define INSTR_CREATE_strt_wbreg(dc, mem, Rt, Rm, shift, imm) \ |
| instr_create_2dst_5src((dc), OP_strt, (mem), opnd_create_reg(opnd_get_base(mem)), (Rt), opnd_create_reg(opnd_get_base(mem)), (Rm), (shift), (imm)) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_ldm(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldm_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldm_priv, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldm_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmda(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldmda_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmda_priv, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldmda_priv_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmda_priv, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmda_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmdb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldmdb_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb_priv, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldmdb_priv_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb_priv, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmdb_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmia_priv_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmia_priv, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_ldmib(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_ldmib_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_stm(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stm_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stm_priv, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stm_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 2, 1, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_stmda(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stmda_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmda_priv, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stmda_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 2, 1, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_stmdb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stmdb_priv(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb_priv, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stmdb_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 2, 1, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_stmib(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 1, 0, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_stmib_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 2, 1, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_8(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_8, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_8_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_8, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_8(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_8, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_8_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_8, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_8(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_8, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_8_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_8, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_8(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_8, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_8_wb(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_8, 1, 2, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vldmia(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vldmia, 0, 1, list_len, (mem), __VA_ARGS__) |
| #define INSTR_CREATE_vstmia(dc, mem, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vstmia, 1, 0, list_len, (mem), __VA_ARGS__) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rm, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_vld1_dup_8_wbreg(dc, mem, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_8_wbreg(dc, mem, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_8_wbreg(dc, mem, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_8_wbreg(dc, mem, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, imm, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_vld1_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_64(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_64, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_64_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_64, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_16, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_16, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_32, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_dup_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_32, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_8, 0, 2, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_8, 1, 3, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_16, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_16, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_32, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_32, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_64(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_64, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_64_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_64, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst1_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_16, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_16, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_32, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_32, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst2_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_16, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_16, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_32, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_32, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst3_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_16(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_16, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_16_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_16, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_32(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_32, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_32_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_32, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_lane_8(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_8, 1, 1, list_len, (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vst4_lane_8_wbimm(dc, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_8, 2, 2, list_len, (mem), opnd_create_reg(opnd_get_base(mem)), (imm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (Rd, mem, imm, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param Rd The destination register opnd_t operand. |
| * \param mem The memory opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_vldmdb(dc, Rd, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vldmdb, 1, 2, list_len, (Rd), (mem), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vldmia_imm(dc, Rd, mem, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vldmia, 1, 2, list_len, (Rd), (mem), (imm), __VA_ARGS__) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, Rd, imm, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param Rd The destination register opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_vstmdb(dc, mem, Rd, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vstmdb, 2, 1, list_len, (mem), (Rd), (imm), __VA_ARGS__) |
| #define INSTR_CREATE_vstmia_imm(dc, mem, Rd, imm, list_len, ...) \ |
| instr_create_Ndst_Msrc_varsrc((dc), OP_vstmia, 2, 1, list_len, (mem), (Rd), (imm), __VA_ARGS__) |
| /* @} */ /* end doxygen group */ |
| |
| /** @name Signature: (mem, imm, Rm, list_len, ...) */ |
| /* @{ */ /* start doxygen group (via DISTRIBUTE_GROUP_DOC=YES). */ |
| /** |
| * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and |
| * the given explicit operands, automatically supplying any implicit operands. |
| * The operands should be listed with destinations first, followed by sources. |
| * The ordering within these two groups should follow the conventional |
| * assembly ordering. |
| * \param dc The void * dcontext used to allocate memory for the instr_t. |
| * \param mem The memory opnd_t operand. |
| * \param imm The integer constant opnd_t operand. |
| * \param Rm The source register opnd_t operand. |
| * \param list_len The number of registers in the register list. |
| * \param ... The register list as separate opnd_t arguments. |
| */ |
| #define INSTR_CREATE_vld1_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_64_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_64, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_8_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_8, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld1_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_8_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_8, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld2_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_8, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_8_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_8, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_32, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld3_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_8, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (Rm), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__) |
| #define INSTR_CREATE_vld4_16_wbreg(dc, mem, imm, Rm, list_len, ...) \ |
| instr_create_Ndst_Msrc_vardst((dc), OP_vld4_16, 1, 4, list_len, opnd_create_reg(opnd_get_base(mem)), (mem), (imm |
