commit f90243dfbf007accd4f5137fa8222f8e3ca928f7
author derek.bruening <derek.bruening> Thu Nov 13 17:33:13 2014
committer derek.bruening <derek.bruening> Thu Nov 13 17:33:13 2014
tree 4aa684a4982545a9c004803cb15c12bfca067a03
parent 96927150e61887476fc3aadfd7cb2f62755e33e4

i#1551 port to ARM: remove sub-GPR enums

We decided to throw out DR_REG_RN_TH (top half), DR_REG_RN_BH (bottom half
for 32-bit as we have the W versions for 64-bit), and DR_REG_RN_BB (bottom
byte) as they are not available in the ISA and which portion of a GPR is
selected purely by the opcode.  Our decoder will create a partial register
for these to help tools, but it won't specify which part of the register,
just like for SIMD regs on x86.

This makes reg_32_to_16() and reg_32_to_8() x86-only.

git-svn-id: https://dynamorio.googlecode.com/svn/trunk@2960 49cc7528-f6fd-11dd-9d1a-b59b2e1864b6