| commit | 75d2e605f763f3220793c3bb52a6b6effffe4d9c | [log] [tgz] |
|---|---|---|
| author | Stephane Eranian <eranian@gmail.com> | Fri May 16 04:53:17 2025 |
| committer | Stephane Eranian <eranian@gmail.com> | Fri May 16 05:02:32 2025 |
| tree | 0a3097494c520bcfca2ab1f4def8eaf6f5d815f0 | |
| parent | c5587f9931123be6fcb6f8133497d93cab36bdcd [diff] |
fix AMD Zen5 umasks for L2_PREFETCH_MISS_L3 and L2_FILL_RESPONSE_SRC The umasks tables were swapped between the two events. Simplify umasks names for L2_FILL_RESPONSE_SRC Signed-off-by: Stephane Eranian <eranian@gmail.com>