)]}' { "log": [ { "commit": "b5eaba47efc5e4e3029086d5c25eee0e8dbb0129", "tree": "f83adf54bf08650f89e2faecb3cf5ae7eeca6046", "parents": [ "b4751218bc5a77fd7b9747ecf3286f30c4e31f30", "ba86a1e844732a7faa877e3221249e98fbbede58" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Jul 08 19:13:22 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 08 19:13:22 2026" }, "message": "Merge \"fix(cpufeat): correct comments to reflect forced override behavior\" into integration" }, { "commit": "ba86a1e844732a7faa877e3221249e98fbbede58", "tree": "a045e8a6fbf5b869ad88b10adf61c1296ce95c4d", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd" ], "author": { "name": "Karthick Shanmugham", "email": "kartshan@qti.qualcomm.com", "time": "Wed Jul 01 05:56:11 2026" }, "committer": { "name": "Karthick Shanmugham", "email": "kartshan@qti.qualcomm.com", "time": "Wed Jul 08 09:13:46 2026" }, "message": "fix(cpufeat): correct comments to reflect forced override behavior\n\nThe comments in arch_features.mk incorrectly stated that FEAT_LIST\nfeatures are set to \u00271\u0027 only if not yet defined. However, the\nset_ones macro (defined in make_helpers/defaults.mk) uses the :\u003d\noperator, which performs immediate assignment and always overrides\nany previous platform or command-line settings.\n\nThis behavior is intentional: when ARM_ARCH_{MAJOR,MINOR} is set,\narchitecturally mandatory features must be forced to FEAT_STATE_ALWAYS\n(\u003d1) because these settings propagate to the compiler and implicitly\nenable code paths that assume the feature is present and cannot be\nconditionally disabled at runtime.\n\nUpdate comments to accurately reflect that:\n- Mandatory features are forced to FEAT_STATE_ALWAYS (1), overriding\n any platform settings including FEAT_STATE_CHECK (\u003d2)\n- This prevents platforms from using runtime detection for features\n that are architecturally mandatory for the configured version\n\nThis is a documentation-only change with no functional impact on the\nbuild or runtime behavior.\n\nChange-Id: I1532ecda67d50c2d1cd03eeb7aa8c2507e5e1327\nSigned-off-by: Karthick Shanmugham \u003ckartshan@qti.qualcomm.com\u003e\n" }, { "commit": "b4751218bc5a77fd7b9747ecf3286f30c4e31f30", "tree": "88f11c361868cd5b646f02006307eb867ede829b", "parents": [ "26fd8c936899b66796391924ef21d2c38172d724", "5028f4c809fef7554c3894cd18b4795851968d35" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 08 08:02:40 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 08 08:02:40 2026" }, "message": "Merge changes Id61ef426,If8df342c into integration\n\n* changes:\n feat(mediatek): cleaner DFD support disablement in production\n fix(mt8189): fix label followed by declaration error in mt_spm.c\n" }, { "commit": "26fd8c936899b66796391924ef21d2c38172d724", "tree": "69887ec84e66696b868ac213cb53dd4b4c706038", "parents": [ "ec6a82ad71b31b53767d1b06e3e0d01821ced81f", "93a21910e9fa1f84d4ac4570b8ab333098931acb" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Jul 07 14:07:11 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 14:07:11 2026" }, "message": "Merge \"feat(build): add per-library ASFLAGS support to MAKE_S_LIB\" into integration" }, { "commit": "ec6a82ad71b31b53767d1b06e3e0d01821ced81f", "tree": "a117ffbddcf20caac80af2943ece0153ccdb55c5", "parents": [ "1dc6b16cd08ba27b0b19d42678c70613bd3aa57a", "9fb8c7aaabf236daf26a1b5dd3a5f3c0702096ea" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Jul 07 13:30:47 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 13:30:47 2026" }, "message": "Merge \"fix(fvp): write RNG data to the buffer, do not return it\" into integration" }, { "commit": "1dc6b16cd08ba27b0b19d42678c70613bd3aa57a", "tree": "d4b7610a924b5349ca452b503b8c529fc3ac5e19", "parents": [ "433220587ba4ed2384d76d250f3e535fddc32924", "c4bc885c4285a20205aeb29b57ac7685a673cd51" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 07 11:36:51 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 11:36:51 2026" }, "message": "Merge \"fix(xilinx): validate UART baud rate from DTB\" into integration" }, { "commit": "433220587ba4ed2384d76d250f3e535fddc32924", "tree": "5e1493d9bc96f6910665603e1d3ccda53edb4bfb", "parents": [ "e738d01f3c7f7f3d7cabb6635575d02495a425f5", "3a7b3fc981967e0f2ff7bde602905dc256e39c65" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jul 07 10:13:20 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 10:13:20 2026" }, "message": "Merge \"fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL cores\" into integration" }, { "commit": "93a21910e9fa1f84d4ac4570b8ab333098931acb", "tree": "b6bb886c77262a99b80d02c96e3e4d7ad4ab4822", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce" ], "author": { "name": "dongnanw", "email": "dongnanw@qti.qualcomm.com", "time": "Wed Jul 01 08:12:57 2026" }, "committer": { "name": "dongnanwu", "email": "dongnanw@qti.qualcomm.com", "time": "Tue Jul 07 09:42:35 2026" }, "message": "feat(build): add per-library ASFLAGS support to MAKE_S_LIB\n\nAdd $$(LIB$(4)_ASFLAGS) to the MAKE_S_LIB assembly compilation line,\nallowing library-specific assembly flags to be passed when building .S\nfiles. This mirrors the existing $$(LIB$(4)_CFLAGS) support already\npresent in MAKE_C_LIB.\n\nChange-Id: I372b4a9b99f302f30714b38fa424f9deb62c6d64\nSigned-off-by: dongnanw \u003cdongnanw@qti.qualcomm.com\u003e\n" }, { "commit": "e738d01f3c7f7f3d7cabb6635575d02495a425f5", "tree": "88151e6426e8837e7125563b72de809e091e841d", "parents": [ "33dc5c33c7277ad9eebc466462ce545674be3428", "9147a572a1e2c755d43c7247880f40825a93e2f9" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Jul 07 08:56:35 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:56:35 2026" }, "message": "Merge \"docs(build): drop refs to openssl 1.x\" into integration" }, { "commit": "33dc5c33c7277ad9eebc466462ce545674be3428", "tree": "fdfcb4eea5766105acd6cae09fd2730b5abc2964", "parents": [ "0f6cb7d3adbf45e60362bea70815f6266550fddc", "c63762d39c0e723cb9c6e0ee36dac6e1f7812283" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:44:47 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:44:47 2026" }, "message": "Merge \"feat(mt8196): modify CPUPM_READY_MS form 40s to 60s\" into integration" }, { "commit": "0f6cb7d3adbf45e60362bea70815f6266550fddc", "tree": "a6ed0497e12eca2cdc1c10c162792708777b31c0", "parents": [ "aa2222ac957eeca6bbef068123137f045bf227a4", "4f53045e6a15cd76faf60b71fa0f38daa6408950" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:43:27 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:43:27 2026" }, "message": "Merge \"fix(cpus): remove duplicate comments from lib/cpus/cpu-ops.mk\" into integration" }, { "commit": "aa2222ac957eeca6bbef068123137f045bf227a4", "tree": "74ed45e66b18b271d007d6baa27d401639770cb5", "parents": [ "97a63a3494b6bb819dc39b1ea6dd5f3cf91e7ffc", "a177e23466ffbe3959e3852bbcf67170ce1b00d1" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:41:59 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:41:59 2026" }, "message": "Merge changes from topic \"ar/brbev1p1\" into integration\n\n* changes:\n fix(docs): update stale reference to the CI all configs\n fix(tsp): unify tsp_setup() and tsp_main()\n chore(cpufeat): remove unused macros\n fix(cpus): use standard checker for FEAT_MTE2 on Cortex A715\n fix(cpufeat): mark FEAT_TLBID as unimplemented\n fix(docs): fix EXTRACT macro documentation\n" }, { "commit": "97a63a3494b6bb819dc39b1ea6dd5f3cf91e7ffc", "tree": "537ddff9a9ff8bcd83d7a5779e9651364c1d7327", "parents": [ "c9bed3962d11817de59bf958449643c5acd3718c", "3f68aee34d425002ac6cc22f9000e02452c64748" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:34:19 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:34:19 2026" }, "message": "Merge \"refactor(mediatek): update platform code for emi protection init\" into integration" }, { "commit": "c9bed3962d11817de59bf958449643c5acd3718c", "tree": "6a8a8d592d0ef7f89176c8ebe0255bcf5ac5c8be", "parents": [ "d127ba7c3b25fe95cee113ecd49021481771b0a4", "4a087faf0704c466fcc2f344099cad50ba289fdb" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:24:41 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:24:41 2026" }, "message": "Merge \"fix(mediatek): cirq: limiting num_of_events against possible OOB access\" into integration" }, { "commit": "d127ba7c3b25fe95cee113ecd49021481771b0a4", "tree": "bd5941d82e614a94d91e668bb0a1a35f6a6b4236", "parents": [ "34596f9aea5e502cc278fa4c602dcd00588262c2", "ce48a765555f7dfd38abb1aaa6d2397501e81d44" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jul 07 08:15:14 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 08:15:14 2026" }, "message": "Merge changes Ie0d2c89a,I163ed09d,Ia1e99219,I34fa37cb,I17d90078 into integration\n\n* changes:\n fix(mt8196): secure APU DEVAPC configuration for ARE1\n fix(mediatek): lpm: validate IRQ index during suspend\n fix(mediatek): lpm: validate array index in mt_lp_irqremain_set\n fix(mediatek): validate aff_lvl in validate_power_state\n fix(mediatek): validate dev_id in mtk_cpc_prof_dev_name\n" }, { "commit": "34596f9aea5e502cc278fa4c602dcd00588262c2", "tree": "a85fdcd2c870fb41ab4207421736e799f618e262", "parents": [ "ebb927bebdf97a234439012f5a47fcdb131a6ae6", "1c5498126c159bd4141d426a99960dd8149e5356" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 07 06:52:40 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 06:52:40 2026" }, "message": "Merge \"fix(smccc): also report 64-bit FID for ARCH_SOC_ID\" into integration" }, { "commit": "ebb927bebdf97a234439012f5a47fcdb131a6ae6", "tree": "678c3e00da89a1e0803cf4d75a533ad5c6143532", "parents": [ "2021bc37e9b6cec22e549ff1e5456c5d3a57ff98", "e045b38e7abea266ef55a114df7b37f0aea3989a" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 07 06:48:35 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 07 06:48:35 2026" }, "message": "Merge \"fix(qemu-sbsa): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "4a087faf0704c466fcc2f344099cad50ba289fdb", "tree": "5350bd8e7f5b5bd2c0e75e7e04400eac3c2f7e4b", "parents": [ "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76" ], "author": { "name": "Leo Chen", "email": "shf.chen@mediatek.com", "time": "Tue Jul 07 02:33:29 2026" }, "committer": { "name": "Leo Chen", "email": "shf.chen@mediatek.com", "time": "Tue Jul 07 02:34:37 2026" }, "message": "fix(mediatek): cirq: limiting num_of_events against possible OOB access\n\nIf \u0027num_of_events\u0027 is set to a value larger than the allocated size\nof \u0027wakeup_events\u0027, the loop will read beyond the array bounds,\npotentially accessing invalid memory or leaking sensitive data from\nadjacent memory locations.\n\nFixing this by limiting the \u0027num_of_events\u0027 in set_wakeup_sources().\n\nChange-Id: I176be7306a77eb94b08bb592217fee9576af8232\nSigned-off-by: Leo Chen \u003cshf.chen@mediatek.com\u003e\n" }, { "commit": "ce48a765555f7dfd38abb1aaa6d2397501e81d44", "tree": "d5d25f209b6365883ee72997f034afc4973ea24f", "parents": [ "37babca502c732c9c66d25b166f234db85dc13fc" ], "author": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jun 02 09:43:12 2026" }, "committer": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jul 07 02:32:12 2026" }, "message": "fix(mt8196): secure APU DEVAPC configuration for ARE1\n\nThe APU DEVAPC permission for Domain 0 (AP) accessing the SLAVE_ARE1\ninterface is configured with NO_PROTECTION.\n\nHarden the APU DEVAPC table by restricting Domain 0 to SEC_RW_ONLY\nfor the SLAVE_ARE1 slave. Set SLAVE_RPC to SEC_RW_NS_R to allow\nnecessary read polling while keeping SLAVE_SMMU_IP_REG as NO_PROTECTION.\n\nChange-Id: Ie0d2c89aa590b0c3fcd4ba412adaa75de9488f60\nSigned-off-by: Yu-Ping Wu \u003cyupingso@google.com\u003e\n" }, { "commit": "37babca502c732c9c66d25b166f234db85dc13fc", "tree": "9cb575aa0cd6d25a58cd6bf153bf3b67740f8df9", "parents": [ "e9274764590f49d8570ec400f7a19583ded136de" ], "author": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jun 09 08:24:46 2026" }, "committer": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jul 07 02:32:09 2026" }, "message": "fix(mediatek): lpm: validate IRQ index during suspend\n\nThe IRQ numbers used as indices in mt_lp_irqremain_set() are not\nfully validated.\n\nAdd bounds checking on the IRQ index in mt_lp_irqremain_set()\nand verify the calculated register index in collect_all_wakeup_events()\nbefore performing memory accesses.\n\nChange-Id: I163ed09dd91b5e86e9451e63f3d0b7990a09528d\nSigned-off-by: Yu-Ping Wu \u003cyupingso@google.com\u003e\n" }, { "commit": "e9274764590f49d8570ec400f7a19583ded136de", "tree": "3a3bc12d2e33d2dcfa5fdac0a6eb91f2674de370", "parents": [ "49a8c0c0f1c271c3fbd53d9e3a1172de42e88891" ], "author": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jun 30 10:03:22 2026" }, "committer": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jul 07 02:31:33 2026" }, "message": "fix(mediatek): lpm: validate array index in mt_lp_irqremain_set\n\nIn mt_lp_irqremain_set(), remain_irqs.count is used as an index to\naccess the wakeup configuration arrays.\n\nAdd an index bounds check against MT_IRQ_REMAIN_MAX before accessing\nthe array elements.\n\nChange-Id: Ia1e992198ce6f4139bfe3020495aaad3a7a44bd2\nSigned-off-by: Yu-Ping Wu \u003cyupingso@google.com\u003e\n" }, { "commit": "49a8c0c0f1c271c3fbd53d9e3a1172de42e88891", "tree": "3a48cd387215d457f816c6f9e1b8a2fc87245380", "parents": [ "feba8e73942ad8fbf03f628ac93fb821db85d1b3" ], "author": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jun 23 06:58:18 2026" }, "committer": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jul 07 02:26:22 2026" }, "message": "fix(mediatek): validate aff_lvl in validate_power_state\n\nIn validate_power_state(), the aff_lvl field extracted from the\npower_state parameter is not checked against the maximum power level\nlimit.\n\nAdd a boundary check to ensure aff_lvl does not exceed\nPLAT_MAX_PWR_LVL in both armv8_2 and armv9_0 pwr_ctrl.c to prevent\nunclamped array indexing.\n\nChange-Id: I34fa37cb86b957836003bdffe29a303d4cd35ccf\nSigned-off-by: Yu-Ping Wu \u003cyupingso@google.com\u003e\n" }, { "commit": "feba8e73942ad8fbf03f628ac93fb821db85d1b3", "tree": "4a0ac78e6670cf9b1e5244e07d23911da9c2a0ee", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd" ], "author": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jun 23 07:15:40 2026" }, "committer": { "name": "Yu-Ping Wu", "email": "yupingso@google.com", "time": "Tue Jul 07 02:18:04 2026" }, "message": "fix(mediatek): validate dev_id in mtk_cpc_prof_dev_name\n\nThe dev_id parameter passed to mtk_cpc_prof_dev_name() is used as\nan index to read the prof_dev_name array without bounds checking.\n\nAdd a bounds check using ARRAY_SIZE to ensure dev_id is within\nthe array limit.\n\nChange-Id: I17d900785f4fb11a27481ff7cd3f7ba9cb9d29c5\nSigned-off-by: Yu-Ping Wu \u003cyupingso@google.com\u003e\n" }, { "commit": "2021bc37e9b6cec22e549ff1e5456c5d3a57ff98", "tree": "fca3df6feab344cde9bad3ba5ea82b60df2be7f7", "parents": [ "d5cba65e8bdfe3be48929bd00417797d8e0c9869", "251e1dfa197454cf0af3b3aa668c6e1cf1180cc5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 06 13:15:49 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 06 13:15:49 2026" }, "message": "Merge \"perf(el3-runtime): do no check for AArch32 when not supported\" into integration" }, { "commit": "d5cba65e8bdfe3be48929bd00417797d8e0c9869", "tree": "491a9088dec28611b23560f660552e6eda7a5c07", "parents": [ "696341ec6eb7b1cfca31a6e130cf7c82b0e29a9b", "d56b395747d38ec0a9eca18bde4dcd312a3c88d3" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jul 06 09:36:16 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 06 09:36:16 2026" }, "message": "Merge changes from topic \"pm_apu_ipi_cleanup\" into integration\n\n* changes:\n refactor(xilinx): remove primary_proc global\n refactor(xilinx): drop unused proc argument from pm_ipi API\n refactor(xilinx): use shared apu_ipi channel for PM IPI\n" }, { "commit": "696341ec6eb7b1cfca31a6e130cf7c82b0e29a9b", "tree": "42db829b386187c48c9a0f16f55d19e864cb01ee", "parents": [ "e5097743901ced6570d61c5606b5e16a31872025", "14033e3afcf5681285804f616c36e53fdc2885f7" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jul 06 08:39:29 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 06 08:39:29 2026" }, "message": "Merge \"fix(fvp): correct attest token length\" into integration" }, { "commit": "e5097743901ced6570d61c5606b5e16a31872025", "tree": "947c9132dd1147b9aaeae91e018af364fce3e5a8", "parents": [ "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76", "44ca4228a45f3e087c559854364d2a79bef75e45" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jul 06 08:25:58 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 06 08:25:58 2026" }, "message": "Merge \"fix(fvp): unmatch BL32_BASE between IMAGE_BL1 and IMAGE_BL2\" into integration" }, { "commit": "d56b395747d38ec0a9eca18bde4dcd312a3c88d3", "tree": "6da529a9f37263b1fefe6d3f12853591bea594c6", "parents": [ "29de873a57e52e78244ed5c130a204e696d5e247" ], "author": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Wed Jun 24 12:06:01 2026" }, "committer": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Mon Jul 06 05:46:30 2026" }, "message": "refactor(xilinx): remove primary_proc global\n\nprimary_proc was only an alias for the first entry of the pm_procs\ntable. Drop the global and use pm_get_proc(0U) instead.\n\nChange-Id: Id27130245a86eda4bd0e2a51057a5429481995b6\nSigned-off-by: Naman Trivedi \u003cnaman.trivedimanojbhai@amd.com\u003e\n" }, { "commit": "3f68aee34d425002ac6cc22f9000e02452c64748", "tree": "b0b04178dfe2bca3a9631510f5bf1717eba7e220", "parents": [ "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76" ], "author": { "name": "Leo Chen", "email": "shf.chen@mediatek.com", "time": "Mon Jul 06 05:36:46 2026" }, "committer": { "name": "Leo Chen", "email": "shf.chen@mediatek.com", "time": "Mon Jul 06 05:36:46 2026" }, "message": "refactor(mediatek): update platform code for emi protection init\n\nRefactor the EMI initialization implementation:\n- Move EMI region protection setup to public TF-A repository to\n better align with the SPD configuration\n- Add error handling for emi protection init\n\nChange-Id: I12fbc5ac1ed25ca78027bb03ae4ba58c6a8c1994\nSigned-off-by: Leo Chen \u003cshf.chen@mediatek.com\u003e\n" }, { "commit": "29de873a57e52e78244ed5c130a204e696d5e247", "tree": "5bc2c12585a991cfbdca404767fd1d07d813feeb", "parents": [ "fec0cf368dc806a561f7c75544000da3a32ad0c8" ], "author": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Wed Jun 24 12:05:03 2026" }, "committer": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Mon Jul 06 05:03:15 2026" }, "message": "refactor(xilinx): drop unused proc argument from pm_ipi API\n\nThe \"proc\" argument in the pm_ipi_* functions is unused, so remove it\nfrom all the pm_ipi_* functions.\n\nChange-Id: I5436fd304a9928467f841092f62e05bbb99c6d07\nSigned-off-by: Naman Trivedi \u003cnaman.trivedimanojbhai@amd.com\u003e\n" }, { "commit": "fec0cf368dc806a561f7c75544000da3a32ad0c8", "tree": "25f3c2c30b3e86271772a30f853b7d8317149d83", "parents": [ "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76" ], "author": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Wed Jun 24 12:04:05 2026" }, "committer": { "name": "Naman Trivedi", "email": "naman.trivedimanojbhai@amd.com", "time": "Mon Jul 06 05:02:31 2026" }, "message": "refactor(xilinx): use shared apu_ipi channel for PM IPI\n\nAll APU cores talk to the platform management controller over a single\nIPI channel, so the .ipi field in struct pm_proc is redundant.\nSo, drop the per-processor .ipi field from struct pm_proc.\n\nChange-Id: I9adc3c82f5f2f12133f0d569bb4d894ae8488908\nSigned-off-by: Naman Trivedi \u003cnaman.trivedimanojbhai@amd.com\u003e\n" }, { "commit": "14033e3afcf5681285804f616c36e53fdc2885f7", "tree": "99831c18c08c0b377a84ef33587f26c3ebd137fe", "parents": [ "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Tue Jun 30 13:40:49 2026" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Sat Jul 04 06:25:03 2026" }, "message": "fix(fvp): correct attest token length\n\nFixup attest token sign to return the actual\nsignature length.\n\nChange-Id: Id12ff409805bfc1cbccff9264a2db1452a9d5335\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "2f8d0868872a27b23ef8cbf1c44caaeb3b23cc76", "tree": "75d020483031d0cab4ef79c7ea7f15b78861a4a3", "parents": [ "40562384431151f3c91369a92c1e5efdc182441e", "3afb28ed07ea9279181d066d1d517e1c96ce9cc7" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Jul 03 14:26:39 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 03 14:26:39 2026" }, "message": "Merge changes from topic \"hm/mecid\" into integration\n\n* changes:\n fix(firme): refine handling of the COMMON_MECID_WIDTH\n fix(firme): bump advertised MECID version\n" }, { "commit": "40562384431151f3c91369a92c1e5efdc182441e", "tree": "0cef60b4ac2cb983faf8364bd1608ed1328bf34c", "parents": [ "a22d6791eb682d70721eb2dd35c9276eeaacc157", "789a4950a86c1e37ebb1adb8c51f76d50f1c1ff7" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Fri Jul 03 13:40:34 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 03 13:40:34 2026" }, "message": "Merge changes I018938df,Ie0cde2e8 into integration\n\n* changes:\n refactor(io): use check_size_t_overflow\n feat(lib): introduce check_size_t_overflow\n" }, { "commit": "a22d6791eb682d70721eb2dd35c9276eeaacc157", "tree": "37817d84647e7d5f36e03ec0bc33d0af5dfdb1e1", "parents": [ "be097a3a02847b53271a184957a4f5dcc663da1f", "019af1a9f16a008eb4959d22b3f7f34b2f582da9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Jul 03 09:19:22 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 03 09:19:22 2026" }, "message": "Merge \"fix(zynqmp): replace magic number 64 with IOCTL_MAX_ID\" into integration" }, { "commit": "c63762d39c0e723cb9c6e0ee36dac6e1f7812283", "tree": "9a17ad02ea6018e51e99856ea68e96b6628ee841", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce" ], "author": { "name": "Zhigang Qin", "email": "zhigang.qin@mediatek.corp-partner.google.com", "time": "Thu Jul 02 02:21:36 2026" }, "committer": { "name": "Zhigang Qin", "email": "zhigang.qin@mediatek.corp-partner.google.com", "time": "Fri Jul 03 07:25:44 2026" }, "message": "feat(mt8196): modify CPUPM_READY_MS form 40s to 60s\n\nAvoid entering cpuidle during the first 60s after boot to prevent\nsystem hang.\n\nChange-Id: I828dbd64afb2d43f5d2e873b0a668ef6f2eb4393\nSigned-off-by: Zhigang Qin \u003czhigang.qin@mediatek.corp-partner.google.com\u003e\n" }, { "commit": "44ca4228a45f3e087c559854364d2a79bef75e45", "tree": "ced6948acfb70f40712138081d0497e2dc362008", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce" ], "author": { "name": "Yeoreum Yun", "email": "yeoreum.yun@arm.com", "time": "Thu Jul 02 09:54:22 2026" }, "committer": { "name": "Yeoreum Yun", "email": "yeoreum.yun@arm.com", "time": "Thu Jul 02 13:28:43 2026" }, "message": "fix(fvp): unmatch BL32_BASE between IMAGE_BL1 and IMAGE_BL2\n\ncommit f21705d3e716 (\"feat(measured-boot): calculate ev log size\")\nintroduce to PLAT_ARM_EVENT_LOG_MAX_SIZE and this size will be added\ninto PLAT_ARM_MAX_BL1_RW_SIZE.\n\nUnfortunately, the PLAT_ARM_EVENT_LOG_MAX_SIZE is different\nbetween IMAGE_BL1 and IMAGE_BL2 that means the value of BL2_BASE\nis different between two images.\n\nSince BL2\u0027s PLAT_ARM_EVENT_LOG_MAX_SIZE is bigger than BL1,\nThe BL1 tries to load image BL2 in higher address than the start\naddress of BL2 at the time of compilation.\n\n // BL2 loaded address by BL1:\n INFO: BL1: Loading BL2\n INFO: Loading image id\u003d1 at address 0x4034000\n\nBut the BL2\u0027s start address in the binary (bl2.dump):\n\n // start address located in lower.\n ...\n architecture: aarch64, flags 0x00000112:\n EXEC_P, HAS_SYMS, D_PAGED\n start address 0x0000000004033000\n\nTo address this inconsistency, introduce PLAT_ARM_BL1_EXTRA_SIZE to\nmake BL2_BASE coherent regardless of BL1 and BL2.\n\nfixes: f21705d3e716 (\"feat(measured-boot): calculate ev log size\")\nChange-Id: I186de5c9f741630c35e88d1d7ee380f327eca5b3\nSigned-off-by: Yeoreum Yun \u003cyeoreum.yun@arm.com\u003e\n" }, { "commit": "be097a3a02847b53271a184957a4f5dcc663da1f", "tree": "b77494608665eb1fbeea5590765569e266ad57fe", "parents": [ "28d37d3bc39f32898394126eca4de5a8dd2bfc17", "75c5ca2d5a4a74e3d54a42b58d57f6df3851fe0a" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jul 02 10:02:41 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 02 10:02:41 2026" }, "message": "Merge \"feat(imx93): add Cortex-M33 lifecycle management\" into integration" }, { "commit": "28d37d3bc39f32898394126eca4de5a8dd2bfc17", "tree": "4bb5c951f9525470166a163e22c390f26bbcf4fe", "parents": [ "3d8d1bb4efb53bc8d3c7f0dda76a506de023abc8", "f373e933377c8c3e7c5f1d0c6f5e552c84afad98" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Jul 02 09:21:54 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 02 09:21:54 2026" }, "message": "Merge \"feat(build): add Marvell DDR driver submodule\" into integration" }, { "commit": "3d8d1bb4efb53bc8d3c7f0dda76a506de023abc8", "tree": "fb547f3f9f82e1052bf9d71005d59dcbcec83be4", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce", "cdb7cb965e6a5201a868a7cca33171a951c35c3f" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jul 02 08:43:08 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 02 08:43:08 2026" }, "message": "Merge \"feat(cpufeat): add support for FEAT_SRMASK\" into integration" }, { "commit": "cdb7cb965e6a5201a868a7cca33171a951c35c3f", "tree": "1aa0c6f98979d5be272db7efbd92f950262fcc75", "parents": [ "5da9bc26bb5bfbb466a092d2169f0c82ea49b938" ], "author": { "name": "Johann Scott", "email": "johann.scott@arm.com", "time": "Tue Jun 23 14:12:37 2026" }, "committer": { "name": "johann.scott", "email": "johann.scott@arm.com", "time": "Thu Jul 02 08:27:26 2026" }, "message": "feat(cpufeat): add support for FEAT_SRMASK\n\nFEAT_SRMASK adds a series of aliases and bitwise write masks for\nsome EL1 controls registers. The purpose of this is to reduce\ntrapping of EL1 system register accesses to EL2.\n\nThis feature can be found in the M.a version of the Arm ARM.\n\nChange-Id: I15e26c4570da070562dec990cc3bacde240d4ad5\nSigned-off-by: Johann Scott \u003cjohann.scott@arm.com\u003e\n" }, { "commit": "75c5ca2d5a4a74e3d54a42b58d57f6df3851fe0a", "tree": "83594f54d78a9e39223a79e3132d64587a3b142b", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Thu Jan 06 07:03:25 2022" }, "committer": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Thu Jul 02 08:12:25 2026" }, "message": "feat(imx93): add Cortex-M33 lifecycle management\n\nAdd SiP service support for Cortex-M33 processor lifecycle\nmanagement, enabling the A55 cores to control M33 execution state.\n\nThe following SIP calls are implemented:\n- IMX_SIP_SRC_M4_START: Release M33 from wait state and begin\n execution at the specified entry address. If no address is\n provided, the default entry point (0xFFE0000) is used.\n- IMX_SIP_SRC_M4_STARTED: Query whether M33 is currently running.\n- IMX_SIP_SRC_M4_STOP: Perform a safe reset of M33 by placing it\n in wait state and triggering a watchdog reset to ensure clean\n shutdown of the M33 subsystem.\n\nThe M33 entry address is configured via BLK_CTRL_S M33_INITSVTOR\nregister and stored in SRC_GLOBAL_GPR9 for firmware reference.\n\nChange-Id: Ieb7cda4976f05bb1fb9d1eaecb30668188d8f77a\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n" }, { "commit": "f373e933377c8c3e7c5f1d0c6f5e552c84afad98", "tree": "6626d4244ca9728b623ef93196f7a71d7c38a515", "parents": [ "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon May 18 15:48:28 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 18:29:58 2026" }, "message": "feat(build): add Marvell DDR driver submodule\n\nThis change adds the Marvell DDR drivers as a submodule to the TF-A\nrepository. It is no longer a requirement to pass `MV_DDR_PATH` to the\nbuild system when building configurations which require it, as the build\nsystem will now look inside the `contrib` directory if the parameter is\nmissing.\n\nIf you cloned TF-A without the `--recurse-submodules` flag, you can\nensure that this submodule is present by running:\n\n git submodule update --init --recursive\n\nBREAKING-CHANGE: Marvell DDR drivers are now included in the TF-A\n repository, and it is no longer a requirement to pass `MV_DDR_PATH` to\n the build system. Please run `git submodule update --init --recursive`\n if you encounter issues after migrating to the latest version of TF-A.\n\nChange-Id: I2a6608a85bd91724c2694656fd3b2ddde8229f1c\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "789a4950a86c1e37ebb1adb8c51f76d50f1c1ff7", "tree": "847728d3576764c5fb3512e1f0becf8d7e7c1b7d", "parents": [ "1d5817e7840b45d0070534da230e0f8461a648d8" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 22 08:11:31 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jul 01 16:22:43 2026" }, "message": "refactor(io): use check_size_t_overflow\n\nUse the new check_size_t_overflow helper.\n\nOn aarch32 platform, and when enabling -Wsign-compare flag, there is a\nwarning:\ndrivers/io/io_block.c: In function \u0027block_open\u0027:\ninclude/lib/utils_def.h:215:17: error: comparison of promoted bitwise\n complement of an unsigned value with unsigned [-Werror\u003dsign-compare]\n 215 | ((_u64) \u003e (UINT64_MAX - (_inc)))\n | ^\ndrivers/io/io_block.c:146:13: note: in expansion of macro\n \u0027check_u64_overflow\u0027\n 146 | if (check_u64_overflow((uint64_t)region-\u003eoffset,\n | ^~~~~~~~~~~~~~~~~~\n\nUsing this helper corrects that.\n\nChange-Id: I018938dfa55f83bc4b2267fbaa25498889a15113\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "1d5817e7840b45d0070534da230e0f8461a648d8", "tree": "fd31efdff0b9931d5042d7e3a21c022a8845a066", "parents": [ "358eafe50df5e146fd69e18c1bb8407e5921adce" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 22 08:09:39 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jul 01 16:22:43 2026" }, "message": "feat(lib): introduce check_size_t_overflow\n\nCreate a check_size_t_overflow that will default to either:\n- check_u64_overflow for __aarch64__ platforms\n- check_u32_overflow otherwise (aarch32 platforms)\n\nOn aarch32 platform, and when enabling -Wsign-compare flag, there is a\nwarning:\ndrivers/io/io_block.c: In function \u0027block_open\u0027:\ninclude/lib/utils_def.h:215:17: error: comparison of promoted bitwise\n complement of an unsigned value with unsigned [-Werror\u003dsign-compare]\n 215 | ((_u64) \u003e (UINT64_MAX - (_inc)))\n | ^\ndrivers/io/io_block.c:146:13: note: in expansion of macro\n \u0027check_u64_overflow\u0027\n 146 | if (check_u64_overflow((uint64_t)region-\u003eoffset,\n | ^~~~~~~~~~~~~~~~~~\n\nAdding this helper corrects that.\n\nChange-Id: Ie0cde2e8478fcb2a6e8f88cf8bfa4e6ac00b080d\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "358eafe50df5e146fd69e18c1bb8407e5921adce", "tree": "3dceec7d66db85504a61ed5e2ae03efac0811203", "parents": [ "58ef9a392bd70cd976a04387eb297f18827cf55e", "320434130576e328fdc91ac8860525fc1a51af2e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:14:45 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:14:45 2026" }, "message": "Merge \"fix(marvell): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "58ef9a392bd70cd976a04387eb297f18827cf55e", "tree": "ecc2d67047971ab2f02a69a0845edde9ea8e6dfd", "parents": [ "e08cf049cc0acc794a7c491c19f0e601b70b633e", "ee90225da9b361617ee80295838cc77f012e65f3" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:14:37 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:14:37 2026" }, "message": "Merge \"fix(versal): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "e08cf049cc0acc794a7c491c19f0e601b70b633e", "tree": "c9a1c35943c435bc3fbc65fbbf7247dfe65db48d", "parents": [ "6106c8031ec4f185032c8f117a651561bc53f687", "b7cd69c33b2b06e2295644794ff05823ad33b4ed" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:14:30 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:14:30 2026" }, "message": "Merge \"fix(optee): always evaluate OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC\" into integration" }, { "commit": "6106c8031ec4f185032c8f117a651561bc53f687", "tree": "797e255f3a47ca18812d96a15161a36ffbce86f4", "parents": [ "0bdc117455051a95a766f8ced799bb141076a540", "2bb56899084f44c929477bbd4fd750059ca829cb" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:13:52 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:13:52 2026" }, "message": "Merge \"fix(mediatek): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "0bdc117455051a95a766f8ced799bb141076a540", "tree": "b0d0e896f25df82d6123b2935e358ec872768c0b", "parents": [ "09df5d2d0b93729e7c8efa100310bdb9ace9f848", "7533d34f4a1e193c45e76a10be9199d83257eb53" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:13:23 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:13:23 2026" }, "message": "Merge \"fix(brcm): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "09df5d2d0b93729e7c8efa100310bdb9ace9f848", "tree": "9fe3ce9bd078c7926a0bcd26954ca7b17a48384a", "parents": [ "1bc44a6857e887a3f3332e909b0247ac60e45ba2", "b1e9fc6b0a64a8ffb84ab0e85256ad0b402d869d" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 15:13:02 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 15:13:02 2026" }, "message": "Merge \"fix(renesas): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "1bc44a6857e887a3f3332e909b0247ac60e45ba2", "tree": "7cb893a0913233d30cde60516be171644427d217", "parents": [ "f03a949d5aca1efd946d1b6882692af3c78e5a6b", "462edf1a7ddef52517d79632c47a2e7935c4b4b0" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 13:07:52 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 13:07:52 2026" }, "message": "Merge changes from topic \"xlnx_fix_mpidr_api\" into integration\n\n* changes:\n fix(versal2): fix invalid mpidr in pwr_domain_on\n fix(versal): drop MT bit insertion in mpidr hash\n fix(zynqmp): remove dead api_id check\n" }, { "commit": "f03a949d5aca1efd946d1b6882692af3c78e5a6b", "tree": "3fd489601ad69647af9fb01cc5844e83f33750aa", "parents": [ "e85c1895cb7ed8930819f78baedc523de3127c8e", "b805ef53ebe99ecc1c0991cc7e53bb4659450f7d" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 12:58:51 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 12:58:51 2026" }, "message": "Merge \"fix(rockchip): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "e85c1895cb7ed8930819f78baedc523de3127c8e", "tree": "cb7993b619ea1a7d220fb823739fc877a899eeb4", "parents": [ "0a0bee84b4996972ea29448ad137d443667ef1de", "442e7077299e162d1ff0947e6e5971f3ab398b9e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 01 12:51:34 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 12:51:34 2026" }, "message": "Merge changes from topic \"firme_ide_km\" into integration\n\n* changes:\n fix(rmmd): deprecate RMM EL3 interface for IDE\n feat(firme): implement FIRME IDE key management service\n" }, { "commit": "0a0bee84b4996972ea29448ad137d443667ef1de", "tree": "2a2cebef3cd787c5b7a17f06b352913e25bdce1e", "parents": [ "82cdd1dcac867a44531670f572f92ea19648fd6e", "ee5d942a3af6e17c27ac649601dceffe7be371f9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Jul 01 12:30:04 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 12:30:04 2026" }, "message": "Merge \"fix(qti): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "1c5498126c159bd4141d426a99960dd8149e5356", "tree": "ee6c13139acc6172749930c2744905ba48681c2d", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 13 13:37:24 2026" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Jul 01 12:01:08 2026" }, "message": "fix(smccc): also report 64-bit FID for ARCH_SOC_ID\n\nThe ARCH_SOC_ID SMC calls use a 32-bit FID (bit 30 clear), but require\nits 64-bit cousin for the \"name\" subcall (x1\u003d2), because this relies on\n64-bit registers and on more registers being available.\nWe handle this correctly in the actual call, but the\nARCH_FEATURES call only reports success for the 32-bit version.\n\nAdd the 64-bit FID to the list of FIDs to be checked.\n\nChange-Id: Ic87277c342917e7c63821b9dead3396f0b13023b\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "82cdd1dcac867a44531670f572f92ea19648fd6e", "tree": "660edc2a8ed0bb835feebc3bb51b4e7fb12c9ed8", "parents": [ "8ec5972ebf9d03424e4bc9917b3d71e40f4bf921", "8fcc6def437e1270176bd2992a95c0e6955e02ff" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 01 11:51:49 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 11:51:49 2026" }, "message": "Merge \"fix(socionext): use #ifdef PLAT_RO_XLAT_TABLES\" into integration" }, { "commit": "8ec5972ebf9d03424e4bc9917b3d71e40f4bf921", "tree": "9951a101ff8d4331e3fc539956723de033838b3d", "parents": [ "f341010b8dde46db6243755163b6c4a68288963c", "4ea668399e916844e34baf3692ee26503d582f95" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 01 11:51:18 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 11:51:18 2026" }, "message": "Merge \"fix(amd): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "f341010b8dde46db6243755163b6c4a68288963c", "tree": "ac74d2bad9e90042f0ba6bdf037f719b08f0c59e", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd", "adf41e1237ac283c40873a1ea404eec65004fb8e" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Jul 01 10:43:35 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 01 10:43:35 2026" }, "message": "Merge changes from topic \"ahmaze01/rdaspen-rse-comms-refac\" into integration\n\n* changes:\n docs(rdaspen): document BL2 RSE comms build option\n refactor(rdaspen): remove rse comms from measured boot\n" }, { "commit": "adf41e1237ac283c40873a1ea404eec65004fb8e", "tree": "ac74d2bad9e90042f0ba6bdf037f719b08f0c59e", "parents": [ "aec921e3cd4cfbb9734d38f158ef5f72f6d6af41" ], "author": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Fri Jun 12 14:17:10 2026" }, "committer": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Wed Jul 01 09:29:22 2026" }, "message": "docs(rdaspen): document BL2 RSE comms build option\n\nDocument the RDASPEN_ENABLE_RSE_COMMS_BL2 build option\nfor the RD-Aspen platform.\n\nThe option includes the RSE communication sources in the\nRD-Aspen BL2 build independently of MEASURED_BOOT. This is\npreparatory build-time plumbing for follow-up support that\nwill add a non-measured-boot BL2 consumer of the RSE\ncommunication layer.\n\nEnabling this option alone does not introduce a new BL2\nruntime flow. Also clarify that measured boot enables this\noption automatically because the measured boot flow requires\nBL2 communication with RSE.\n\nChange-Id: Ie8b53559c37416eff3de4c7a5c1a3773c060fad0\nSigned-off-by: Ahmed Azeem \u003cahmed.azeem@arm.com\u003e\n" }, { "commit": "aec921e3cd4cfbb9734d38f158ef5f72f6d6af41", "tree": "e4bcf563235f628aa5fdc4c697943027838b603e", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd" ], "author": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Mon Jan 19 10:50:16 2026" }, "committer": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Wed Jul 01 09:29:22 2026" }, "message": "refactor(rdaspen): remove rse comms from measured boot\n\nMove the RD-Aspen BL2 RSE communication build wiring out of the\nmeasured boot path so that the RSE comms sources can be included\nindependently of MEASURED_BOOT.\n\nThis is preparatory work for follow-up changes that require BL2 to\ncommunicate with RSE when measured boot is disabled. This patch only\nmakes the RSE communication layer available in the BL2 build; it does\nnot introduce a new non-measured-boot BL2 runtime flow.\n\nIntroduce ENABLE_RSE_COMMS_BL2 to conditionally include the RSE comms\nsources in BL2.\n\nChange-Id: Ie2c05fc13a7ee3ecfcdb1034f8076758e87eeda2\nSigned-off-by: Ahmed Azeem \u003cahmed.azeem@arm.com\u003e\n" }, { "commit": "5028f4c809fef7554c3894cd18b4795851968d35", "tree": "3bba00a41413b8f445da05f8a6ed722bebb3eb12", "parents": [ "87cb2c0d13f7726cd6189df6588ba29444026a2f" ], "author": { "name": "Yidi Lin", "email": "yidilin@google.com", "time": "Wed Jul 01 04:05:48 2026" }, "committer": { "name": "Yidi Lin", "email": "yidilin@google.com", "time": "Wed Jul 01 06:50:49 2026" }, "message": "feat(mediatek): cleaner DFD support disablement in production\n\nIntroduce MTK_DFD_SUPPORT build flag to control DFD (Debug Dump) support.\nIt defaults to DEBUG, but can be overridden.\n\nWhen MTK_DFD_SUPPORT is 0, the DFD driver files are not compiled, and\ndummy inline implementations are provided in headers.\nThis is cleaner than scatter-grafting #if !DEBUG in driver files.\n\nAlso fix the generic SMC dispatcher to return MTK_SIP_E_NOT_SUPPORTED\nif a service is registered in the table but has no handler compiled in.\n\nRefactor DFD headers to make `dfd.h` the unified entry point.\n`dfd.h` now includes `plat_dfd.h`, and C files include `dfd.h` instead\nof `plat_dfd.h`. Duplicate declarations were removed.\n\nMove `dfd_smc_dispatcher` declaration to the unified `dfd.h` and remove\nit from platform headers. Rename the static `dfd_smc_dispatcher` in\n`dfd.c` to `mtk_dfd_smc_handler` to avoid naming conflicts.\n\nMake `dfd_setup` non-static on MT8186/92/95 to match MT8188/89 and avoid\ndeclaration conflicts when including the unified `dfd.h`.\n\nFor MT8188/89, always include the DFD module in `MODULES-y` to ensure\nits include paths are always available, but conditionally compile its\nsource files in `rules.mk` based on `MTK_DFD_SUPPORT`. This avoids\ndefining manual include paths in platform Makefiles.\n\nChange-Id: Id61ef426042fb0069b1d50532eca7e802adce94a\nSigned-off-by: Yidi Lin \u003cyidilin@google.com\u003e\n" }, { "commit": "87cb2c0d13f7726cd6189df6588ba29444026a2f", "tree": "8fa16d9b9b6b44f8c15420067fbfeee4b3886db0", "parents": [ "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd" ], "author": { "name": "Yidi Lin", "email": "yidilin@google.com", "time": "Thu Jun 11 04:31:33 2026" }, "committer": { "name": "Yidi Lin", "email": "yidilin@google.com", "time": "Wed Jul 01 06:43:53 2026" }, "message": "fix(mt8189): fix label followed by declaration error in mt_spm.c\n\nWrap the case block for PLAT_AP_SPM_RESOURCE_REQUEST_UPDATE in braces to\nsatisfy C standards where a label cannot be directly followed by a\nvariable declaration.\n\nChange-Id: If8df342ce0dbb8ee8c1f9d8e68e78b1abd076414\nSigned-off-by: Yidi Lin \u003cyidilin@google.com\u003e\n" }, { "commit": "c64fe42d75709fc3da7d0820caf15bce2ca8a2cd", "tree": "518f75362d7407e2d247d434c1c853c033897fa3", "parents": [ "599baaa539b3996067b9ce8f0f225c8baa6e0757", "7196825ce71266d6656165657d4936d185bd439b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Jun 30 20:34:41 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 20:34:41 2026" }, "message": "Merge changes from topic \"bl31_lfa_integration\" into integration\n\n* changes:\n feat(lfa): harden cancel handling and lock around LFA_CANCEL\n feat(lfa): serialize activate across CPUs and manage rendezvous policy\n feat(docs): add documentation page for BL31 LFA\n feat(fvp): add FVP platform support for BL31 live activation\n feat(lfa): update LFA service to support BL31 live activation\n feat(lfa): lfa service updates\n feat(lfa): add relocatable code for BL31 live activation\n feat(lfa): xlat changes for BL31 LFA\n feat(lfa): bl31 linker file updates for lfa\n feat(lfa): add build flag for BL31 LFA support\n feat: place errata into their own section\n" }, { "commit": "7196825ce71266d6656165657d4936d185bd439b", "tree": "cb08336180e5168637032f0c4e42a126deb41cb5", "parents": [ "7a5b0839b5b95b21c82cd0a5d10dc13901e53185" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Mar 05 22:45:36 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 20:25:11 2026" }, "message": "feat(lfa): harden cancel handling and lock around LFA_CANCEL\n\n - block cancel once all active CPUs have entered ACTIVATE\n - take lfa_lock during cancel SMC handling\n\nChange-Id: I1443644845d19e0322f5d188461a1c4083c57707\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "7a5b0839b5b95b21c82cd0a5d10dc13901e53185", "tree": "f60173c63d16ee7ce324aa5ead3b726f5113b454", "parents": [ "8936385d33a3ee77642f1bf3dda41c538d935fca" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu May 21 00:18:05 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 20:25:03 2026" }, "message": "feat(lfa): serialize activate across CPUs and manage rendezvous policy\n\nTrack activation state across CPUs so skip-rendezvous activations don’t\nblock or interleave. Split activate into prepare/finish to latch the\nrendezvous policy, notify the platform once per activation, and only\nclear activation_pending after all callers finish. Return LFA_BUSY for\nconflicting skip requests and LFA_CALL_AGAIN for multi‑stage activations.\n\nChange-Id: Id5a71fb6db12fe240e2bc1c9000606df935374b2\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "8936385d33a3ee77642f1bf3dda41c538d935fca", "tree": "1ba6dc4bc88dd440aab523cf0388d7ae4c61dea5", "parents": [ "c457b88f839c2bc88da003e6cc17baeeaf544a7e" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Jan 29 19:07:51 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 20:24:53 2026" }, "message": "feat(docs): add documentation page for BL31 LFA\n\nThis patch adds a documentation page about the BL31 LFA\nimplementation and outlines the limitations and requirements\nto use it.\n\nChange-Id: I55008a5a45561918bbf386bc1da96f6d281638a3\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "c457b88f839c2bc88da003e6cc17baeeaf544a7e", "tree": "71e182c87501de69d900eed7977ce2eb0adfec0f", "parents": [ "c6ca1acd3238b3d3aed1ea3bef4b2ae64a2a6a53" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Mon May 18 18:16:40 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 20:24:39 2026" }, "message": "feat(fvp): add FVP platform support for BL31 live activation\n\nThis patch adds the platform components of BL31 live\nactivation.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I5c08eecdc0420f05462740b72a59ee2e837cf701\n" }, { "commit": "c6ca1acd3238b3d3aed1ea3bef4b2ae64a2a6a53", "tree": "77c50bd19058a890bb9c4a0705d5ba20dcafa85c", "parents": [ "e6bccf43c4f93a25a0e1c7877107022537a17cad" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Fri Jun 26 18:53:38 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 15:43:17 2026" }, "message": "feat(lfa): update LFA service to support BL31 live activation\n\nThis patch adds the bulk of the BL31 live activation service\nframework including the warm reset handler.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Id9cbeeddbc023ee2540b88008e6c2502d816ee24\n" }, { "commit": "599baaa539b3996067b9ce8f0f225c8baa6e0757", "tree": "c3f0344f46879c0dd70ef0b00a3283bd6fee44d7", "parents": [ "55e1d9beaed61abe77e554bccf03d6cd8a6ee3ea", "df0ee912fee0f07cd533889dd3c410636625b8ff" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 15:42:49 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 15:42:49 2026" }, "message": "Merge \"fix(platforms): check MIN_SGI_ID at compile time\" into integration" }, { "commit": "e6bccf43c4f93a25a0e1c7877107022537a17cad", "tree": "23c99170f8f2f431345d7e370c7b7b8826bf5a8b", "parents": [ "567e4357fb29be24ab5917102d2a5ed6f6feba4d" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Fri Jun 26 18:52:52 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 15:42:43 2026" }, "message": "feat(lfa): lfa service updates\n\nThis patch updates the LFA service components in preparation for\nBL31 specific changes.\n\nChange-Id: I6d4dd90b11fa1d8729c4f9026d2ddce0272aea76\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "55e1d9beaed61abe77e554bccf03d6cd8a6ee3ea", "tree": "9fe97140011e036123f7820fa0f250429e321ddb", "parents": [ "1836963e944169f13a2f7d6947a5b59232c48369", "43a605dc8d0f8e0524a92c9153a968f4da5e020a" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 15:42:00 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 15:42:00 2026" }, "message": "Merge \"fix(errata-abi): update management of REPORT_ERRATA\" into integration" }, { "commit": "1836963e944169f13a2f7d6947a5b59232c48369", "tree": "f93b8ce5b10473d0fe73f671c9ccb0278f462140", "parents": [ "a0b0452186ef40ee5dee6de35fc3bfacbf2efe10", "c02a89b2d330b93d7df1b8b0afb5cd73c39bd285" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 15:41:29 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 15:41:29 2026" }, "message": "Merge \"fix(io): use simple braces for uuid_null definition\" into integration" }, { "commit": "a0b0452186ef40ee5dee6de35fc3bfacbf2efe10", "tree": "bc7a4e0b20f020e1b18c30660832236a80c1e6aa", "parents": [ "365bbb200226cbfd46363978b296224cdbf0fc96", "f2f23d2535ecc0d79d3e451272d946aeb542d0bd" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 15:41:08 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 15:41:08 2026" }, "message": "Merge \"refactor(context-mgmt): move ICC_SRE definitions to arch.h file\" into integration" }, { "commit": "365bbb200226cbfd46363978b296224cdbf0fc96", "tree": "a5a311cc6cb55317ada95f57bf28487c5724ebc7", "parents": [ "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0", "a3ba8ce34a6b575406f6d410d7fece30c8536e9c" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 15:16:37 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 15:16:37 2026" }, "message": "Merge \"fix(st-drivers): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "567e4357fb29be24ab5917102d2a5ed6f6feba4d", "tree": "44f0d832d3f468c5893409a53e40ffd8966823e9", "parents": [ "779393ae1b092ec6f4e02c3a522b8e9ab8acd345" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Mon May 18 17:52:12 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 14:56:36 2026" }, "message": "feat(lfa): add relocatable code for BL31 live activation\n\nThis patch adds the relocatable code functions that are copied\nout of the main BL31 image during a live activation and updates\nthe holding pen code to have a relocatable variant.\n\nChange-Id: I30ba6e118a6b888e0adf4dbd605d15ac0b40bea8\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "779393ae1b092ec6f4e02c3a522b8e9ab8acd345", "tree": "8fb6cb8f66876357e37ecc80089c5d87aaf9f6bd", "parents": [ "769380b33b0a20f6c05b22e6897680a9e28f573d" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Mon May 18 17:29:33 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 14:56:26 2026" }, "message": "feat(lfa): xlat changes for BL31 LFA\n\nThis patch adds xlat library changes needed to support live\nactivation of BL31 images.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I3956542b7978133dddcb0d1ace5512b6cfbfedc0\n" }, { "commit": "769380b33b0a20f6c05b22e6897680a9e28f573d", "tree": "266fee0f77e19b014a2202d42fcf1a0d11e48a11", "parents": [ "1a95ccecd33ed1ac13c748461cdd5df5c9a41657" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed May 20 21:42:56 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 14:56:12 2026" }, "message": "feat(lfa): bl31 linker file updates for lfa\n\nThis patch modifies the BL31 linker script to carve out regions\nneeded by BL31 live activation framework.\n\nChange-Id: I8b5f38a62e159bf1cad8dc4ab74cf6a9bb137074\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "1a95ccecd33ed1ac13c748461cdd5df5c9a41657", "tree": "5a5bc076308d4e2e13eda4908f64a3ed4b598ffd", "parents": [ "8e41e5c6e976b4a8ede38a3932a6d89dc0259842" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed May 20 21:10:03 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 14:56:12 2026" }, "message": "feat(lfa): add build flag for BL31 LFA support\n\nThis is the first patch in the series to enable live firmware\nactivation in BL31, and it adds the build flag to enable this to\nthe makefiles.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I0b6f511e61f9cdcc8ee786507ee1c2e721147da7\n" }, { "commit": "8e41e5c6e976b4a8ede38a3932a6d89dc0259842", "tree": "4825c203babe41ebd6e093afc377ce6fe8775186", "parents": [ "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Mon Jun 22 21:54:01 2026" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Tue Jun 30 14:56:12 2026" }, "message": "feat: place errata into their own section\n\nThis patch moves CPU reset functions and reset errata workarounds\ninto their own linker subsections .text.errata and .rodata.errata,\nas well as modifies CPU macros to allow this.\n\nWhen BL31 LFA is integrated later, this allows these subsections\nto be grouped together and padded, allowing them to be updated\nduring live activation without affectinn the rest of the BL31\nimage.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Id6f248fa796a998152e4e0b946fa3717cb0cfbf6\n" }, { "commit": "442e7077299e162d1ff0947e6e5971f3ab398b9e", "tree": "ab792c8ad396cddcf259625828030433165ee3e8", "parents": [ "3f3dc8227f1f79c424c9dc34ec918368ced7383f" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon May 11 16:19:58 2026" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 30 13:29:54 2026" }, "message": "fix(rmmd): deprecate RMM EL3 interface for IDE\n\nBL31 supports FIRME IDE key management service for Realm instance. The\nexisting RMM EL3 interface for managing IDE keys are deprecated. R-EL2\npayload can now query and use FIRME support for IDE key management.\n\nThis patch also add the missing documentation for the existing build\nflag RMMD_ENABLE_IDE_KEY_PROG and fixes the conditional inclusion of\nrelevant code when RMMD_ENABLE_IDE_KEY_PROG is enabled.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I5c9d4193a00235e616e483c7f8402311103beb1a\n" }, { "commit": "3f3dc8227f1f79c424c9dc34ec918368ced7383f", "tree": "278682f9de8f0bae210bda93f142311145c18f03", "parents": [ "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Mon May 11 15:03:45 2026" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Tue Jun 30 13:29:54 2026" }, "message": "feat(firme): implement FIRME IDE key management service\n\nAdd support for IDE key management service in FIRME.\n\nThis implements the FIRME_IDE_KEYSET_PROG, FIRME_IDE_KEYSET_GO,\nand FIRME_IDE_KEYSET_STOP ABIs in blocking mode. These ABIs implemented\nin EL3 firmware provide a standardized mechanism for managing IDE keys\nthrough the platform IMPDEF key programming interface at a PCIe Root\nPort (RP).\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I92567feeb569fd3eb8d858cccdfdabd6b2cc1e54\n" }, { "commit": "3afb28ed07ea9279181d066d1d517e1c96ce9cc7", "tree": "e213444a15b5b3fb9d65310f580cbbee0f79844c", "parents": [ "55442106e08ce249ee3521693aa9c4596d32511e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 11:08:17 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 11:09:32 2026" }, "message": "fix(firme): refine handling of the COMMON_MECID_WIDTH\n\nFix validation to treat common width as a bit width, not as the max\nMECID value.\n\nChange-Id: I84d0a9e1e8e42b9dc215d58dc51fb267322fb435\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "55442106e08ce249ee3521693aa9c4596d32511e", "tree": "7508099c3569511e784ed8f00c800ea8d21a8f74", "parents": [ "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 11:04:05 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 11:09:32 2026" }, "message": "fix(firme): bump advertised MECID version\n\nBump the advertised version of the MECID service. There\u0027s two sets of\nMECID defintions. The split definitions in firme_mecid.h are supposed to\ncome in later clean-up. Drop that header for now and keep the\ndefinitions in firme_svc.h.\n\nChange-Id: I3be139eedb0b1c50824576f86e36f9c66b238d99\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "5b3df813f8cc9d1f22c84051ced1a9a5d2474bd0", "tree": "0b7d26149540194eabb1462fece201d7a60e2a18", "parents": [ "92a7a4ecb95949b3b454e09fd72cf240ee037ca4", "ea9f5d1232f9d72567731fb82085867e789bf9c3" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 30 09:48:08 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 09:48:08 2026" }, "message": "Merge changes I0a0dbc9e,I0d7b679c into integration\n\n* changes:\n fix(arm): validate last_at_pwrlvl before forwarding it\n fix(psci): validate last_at_pwrlvl bounds before use\n" }, { "commit": "92a7a4ecb95949b3b454e09fd72cf240ee037ca4", "tree": "07884c0665e0e9d9093f224e5d56c6fdbccb4907", "parents": [ "c1d91527b58f7865bb23ca8a55223b4e10f7db29", "5c74c653e5c68e0556ef38a8ec0a6584661c5af9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 08:26:41 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 08:26:41 2026" }, "message": "Merge changes I6b98eead,Ib4ecae1e into integration\n\n* changes:\n refactor(el3-runtime)!: remove PLAT_PCPU_DATA_SIZE\n fix(el3-runtime): improve PLAT_PCPU_DATA_SIZE check\n" }, { "commit": "c1d91527b58f7865bb23ca8a55223b4e10f7db29", "tree": "aa2bd4ee7816ccfdea01cee103c4f7c418aff24a", "parents": [ "7cb424365cb80e4d7e45e2f16bc5eab1c0351475", "1266b4492d33780d5cf075b5cf028fc238022da8" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 08:26:08 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 08:26:08 2026" }, "message": "Merge \"fix(cpus): check __clang_major__ is defined\" into integration" }, { "commit": "7cb424365cb80e4d7e45e2f16bc5eab1c0351475", "tree": "249af5f92732d90d55be1c5b45f9f5fa265bac9d", "parents": [ "b35299d6fc5164ccff06abcbf47dba8f7ebedccd", "14a445843e041f0aadb22affa7d233ea4dd1ffe3" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Jun 30 08:24:37 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 08:24:37 2026" }, "message": "Merge \"fix(ti): use #ifdef for IMAGE_BL flags\" into integration" }, { "commit": "b35299d6fc5164ccff06abcbf47dba8f7ebedccd", "tree": "151998fdd7e7131151abeba248fe6e471bc000da", "parents": [ "26a394c916b8d44a6ff8e0033212d9cb155b0ee5", "d07bf271545c61b98ab1fd1c5f4ff543faa986a6" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Jun 30 07:37:15 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 30 07:37:15 2026" }, "message": "Merge \"fix(zynqmp): fix enum pointer write in pm_pll_get_mode()\" into integration" }, { "commit": "019af1a9f16a008eb4959d22b3f7f34b2f582da9", "tree": "a7e4e9b5ecf24d237a8439c459f5f305cfee9e4e", "parents": [ "31255dd9b2e14c1ebe4eab1b8f4984cde72c51d5" ], "author": { "name": "Sai Varun Venkatapuram", "email": "saivarun.venkatapuram@amd.com", "time": "Mon Jun 15 09:57:23 2026" }, "committer": { "name": "Sai Varun Venkatapuram", "email": "saivarun.venkatapuram@amd.com", "time": "Tue Jun 30 06:03:03 2026" }, "message": "fix(zynqmp): replace magic number 64 with IOCTL_MAX_ID\n\nThe literal 64U used to guard against out-of-bounds access on the\nuint32_t[2] bitmap is a magic number whose meaning is not self-evident.\nThe value represents the total number of IOCTL IDs representable in the\nbitmap (2 elements x 32 bits \u003d 64), beyond which ioctl_id / 32U would\nproduce an out-of-bounds array index. Replace it with the enum value\nIOCTL_MAX_ID defined alongside the IOCTL ID definitions to make the\nboundary explicit at the point of use.\n\nChange-Id: If975a8480efa0eb381bd270051bc84ea83640102\nSigned-off-by: Sai Varun Venkatapuram \u003csaivarun.venkatapuram@amd.com\u003e\n" }, { "commit": "26a394c916b8d44a6ff8e0033212d9cb155b0ee5", "tree": "6802010df5ac3bba2ee3cb4c12eee5e02d1841d6", "parents": [ "51d431f4486a0a4c624525d3e77e4696dc9ce087", "9f24a02f57c6deff9f7299c941e31f8374f784f0" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jun 29 14:15:59 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 29 14:15:59 2026" }, "message": "Merge changes I4c66f31c,Iab216270,I60f76ff0,I859a1183,I19f42c68, ... into integration\n\n* changes:\n fix(st): cast clk_get_rate return when setting console\n fix(st): cast the read_cntfrq_el0() return to unsigned int\n fix(st-clock): correct some STM32MP15 clock driver function\n fix(st-pmic): store regulator ID as an uint8_t\n fix(st-regulator): remove const for driver_data\n fix(st-pmic): stub some functions for STPMIC1L\n fix(st-sdmmc2): update plat_sdmmc2_use_dma prototype\n fix(st-drivers): use BIT_32/GENMASK_32 in ST drivers\n" }, { "commit": "9f24a02f57c6deff9f7299c941e31f8374f784f0", "tree": "52da9c166ea3b9dc8252eb14da92fdfc0edb0e91", "parents": [ "566e896ff33244c3cecb00d1de598f470cb9376e" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 22 11:35:38 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:56 2026" }, "message": "fix(st): cast clk_get_rate return when setting console\n\nThe return of clk_get_rate() is an unsigned long. But for console, it\nwill never be above 4GHz, so it is safe to cast it to uint32_t, before\npassing the parameter to set_console().\n\nThis corrects the warning:\nplat/st/common/stm32mp_common.c:303:13: warning: implicit conversion\n loses integer precision: \u0027unsigned long\u0027 to \u0027uint32_t\u0027 (aka \u0027unsigned\n int\u0027)\n [-Wshorten-64-to-32]\n 303 | clk_rate \u003d\n\t\t \tclk_get_rate((unsigned long)dt_uart_info.clock);\n | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nChange-Id: I4c66f31ce5c002f39ffd8811fdf50496aa46f39d\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "566e896ff33244c3cecb00d1de598f470cb9376e", "tree": "af9fa0374512614709ca3e39e7163c3ec0c50269", "parents": [ "ddcc8db85b1660c8234be0f26776c471c030cae3" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed May 06 14:08:12 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:56 2026" }, "message": "fix(st): cast the read_cntfrq_el0() return to unsigned int\n\nThe function plat_get_syscnt_freq2() returns an unsigned int type, but\nread_cntfrq_el0() that is used inside will return an uint64_t value\non aarch64 platforms (STM32MP2). But this value is usually 64MHz (HSI)\nor 24MHz (HSE). It will never be above 4GHz, so it is safe to cast its\nreturn value.\nThe issue was found with clang -Wshorten-64-to-32 warning.\n\nChange-Id: Iab2162701cabfde4a4416bd4cea45eb15dbeeb5d\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ddcc8db85b1660c8234be0f26776c471c030cae3", "tree": "c6b9f2d1eff36b73f9c2ba6f13b2413fbd2de992", "parents": [ "cc050178952812ffa541a232f775b74b4c2b56d5" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed May 27 13:25:23 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:56 2026" }, "message": "fix(st-clock): correct some STM32MP15 clock driver function\n\nThe function clk_mux_get_parent() is not used in this driver, remove it.\nSet clk_stm32_set_div() static as it is only used in this file for\nSTM32MP15.\nThis corrects the following warnings, when compiling with W\u003d2:\ndrivers/st/clk/stm32mp1_clk.c:214:5: warning: no previous prototype\nfor \u0027clk_mux_get_parent\u0027 [-Wmissing-prototypes]\n 214 | int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t\n\t\t\t mux_id)\n | ^~~~~~~~~~~~~~~~~~\ndrivers/st/clk/stm32mp1_clk.c:267:5: warning: no previous prototype for\n \u0027clk_stm32_set_div\u0027 [-Wmissing-prototypes]\n 267 | int clk_stm32_set_div(struct stm32_clk_priv *priv,\n\t\t\t uint32_t div_id, uint32_t value)\n | ^~~~~~~~~~~~~~~~~\n\nChange-Id: I60f76ff0c7c591c5907caa08260987139bb57b7e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "cc050178952812ffa541a232f775b74b4c2b56d5", "tree": "84b186f59e98fee2946a45246936faf429c05c5d", "parents": [ "f3fa63baf64d7e8097df22f6b69d8c7b2e572c24" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 22 14:05:47 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:56 2026" }, "message": "fix(st-pmic): store regulator ID as an uint8_t\n\nThe number of supported STPMIC2 regulators is 22, it is then less than\n255 and can then be stored in an uint8_t field in the regul_handle_s\nstructure. And the STPMIC2 low level functions API always awaits the ID\nas an uint8_t. This saves 88 bytes of data.\nThis also corrects the following warning:\ndrivers/st/pmic/stm32mp_pmic2.c:315:57: warning: conversion from\n \u0027uint32_t\u0027 {aka \u0027unsigned int\u0027} to \u0027uint8_t\u0027 {aka \u0027unsigned char\u0027} may\n change value [-Wconversion]\n 315 | ret \u003d stpmic2_regulator_set_prop(pmic2, id,\n\t\t\t\t STPMIC2_PULL_DOWN, 1U);\n | ^~\n\nChange-Id: I859a1183f1f561bbc3b1a103267bf6fe62be6a60\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "f3fa63baf64d7e8097df22f6b69d8c7b2e572c24", "tree": "0c783c07750532083fefb7e7b1f72fa4a1f57676", "parents": [ "a33a522d6d7a48f0eb5165e8847063ec4d6b9229" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 22 14:09:34 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:56 2026" }, "message": "fix(st-regulator): remove const for driver_data\n\nThe driver_data will be used to store regul_handle_s data, but bypass_mv\nis not const and will be updated at driver init. The driver_data should\nthen not be const.\nThe issue was seen when trying to correct issues seen with the GCC flag:\n-Wdiscarded-qualifiers.\n\nChange-Id: I19f42c6812bf6ed604ceca0a196e3103bec58dd2\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "a33a522d6d7a48f0eb5165e8847063ec4d6b9229", "tree": "ce2a1ed20263238de729643227dcde4545fce14c", "parents": [ "7991c8967300ae85f91c4cd0cca341034b3661c4" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Apr 21 16:53:11 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Jun 29 13:31:41 2026" }, "message": "fix(st-pmic): stub some functions for STPMIC1L\n\nIf STM32MP_STPMIC1L is enabled, we use the STPMIC2 driver, with STPMIC1\ninclude file. And the functions print_pmic_info_and_debug() and\npmic_voltages_init() do nothing in that case. Instead of defining them\nin STPMIC2 driver, stub them in STPMIC1 include file under the flag\nSTM32MP_STPMIC1L.\n\nChange-Id: I503327daa5098c99c48bbd78fb2253cebfbf390b\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "51d431f4486a0a4c624525d3e77e4696dc9ce087", "tree": "24706c12016fed4f997875bcafccda4b9e51e812", "parents": [ "31255dd9b2e14c1ebe4eab1b8f4984cde72c51d5", "dd6bd54c40c7f51e59428afb31a4e79fa2ef0e07" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 29 13:05:39 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 29 13:05:39 2026" }, "message": "Merge changes from topic \"hm/mecid\" into integration\n\n* changes:\n feat(firme): add COMMON_MECID_WIDTH feat reporting\n refactor(firme): suffix FIRME func IDs with _FID\n feat(rmmd): route MEC refresh via FIRME\n feat(firme): introduce FIRME MECID service\n" }, { "commit": "dd6bd54c40c7f51e59428afb31a4e79fa2ef0e07", "tree": "3eef60918134a52430786528416730eceb5f26c6", "parents": [ "460c722841566b05e7afd8f3e4072dad624453e2" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 18 12:03:00 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jun 29 12:37:46 2026" }, "message": "feat(firme): add COMMON_MECID_WIDTH feat reporting\n\nIntroduce COMMON_MECID_WIDTH in the FIRME MECID feature registers. The\nvalue is initialized as the minimum of the architectural MECID width and\nthe maximum MECID width supported by platform peripherals. Note, this\nfeature register was accidentally omitted from ALP2 version of the\nspecification. It will be added in the next version of the\nspecification.\n\nChange-Id: I6766c319b81dabacef76f771546ef7979e98c07d\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "460c722841566b05e7afd8f3e4072dad624453e2", "tree": "ee6c6df7a52c329560b32c42465cb92e743f1f0f", "parents": [ "5bfbf4b83974aefc109415454eaf00fcb7cccee6" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jun 08 21:46:34 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Jun 29 12:37:46 2026" }, "message": "refactor(firme): suffix FIRME func IDs with _FID\n\nRename FIRME function ID macros that were missing the _FID suffix and\nupdate their call sites and documentation references for consistency.\n\nChange-Id: Id34a2e5a71a027f2d9d3724fc7fe44852540875e\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" } ], "next": "5bfbf4b83974aefc109415454eaf00fcb7cccee6" }