| # "C" Standard Extension for Compressed Instructions. |
| # Version 2.0 |
| |
| c.lwsp | ci | clwsp_imm crd | 010...........10 |
| c.fldsp | ci | cldsp_imm crd(fp) | 001...........10 |
| c.swsp | css | cswsp_imm crs2 | 110...........10 |
| c.fsdsp | css | csdsp_imm crs2(fp) | 101...........10 |
| c.lw | cl | clw_imm crs1_ crd_ | 010...........00 |
| c.fld | cl | cld_imm crs1_ crd_(fp) | 001...........00 |
| c.sw | cs | csw_imm crs1_ crs2_ | 110...........00 |
| c.fsd | cs | csd_imm crs1_ crs2_(fp) | 101...........00 |
| c.j | cj | cj_imm ird_zero | 101...........01 |
| c.jr | cr | iimm_0 crs1 ird_zero | 1000.....0000010 |
| c.jalr | cr | iimm_0 crs1 ird_ra | 1001.....0000010 |
| c.beqz | cb | cb_imm crs1_ irs2_zero | 110...........01 |
| c.bnez | cb | cb_imm crs1_ irs2_zero | 111...........01 |
| c.li | ci | cimm5 irs1_zero crd | 010...........01 |
| c.lui | ci | clui_imm crd | 011...........01 |
| c.addi | ci | cimm5 icrs1 crd | 000...........01 |
| c.addi16sp | ci | caddi16sp_imm irs1_sp ird_sp | 011.00010.....01 |
| c.addi4spn | ciw | ciw_imm irs1_sp crd_ | 000...........00 |
| c.slli | ci | cshamt icrs1 crd | 000...........10 |
| c.srli | cb | cshamt icrs1__ crd__ | 100.00........01 |
| c.srai | cb | cshamt icrs1__ crd__ | 100.01........01 |
| c.andi | cb | cimm5 icrs1__ crd__ | 100.10........01 |
| c.mv | cr | crs2 irs1_zero crd | 1000..........10 |
| c.add | cr | crs2 icrs1 crd | 1001..........10 |
| c.and | ca | crs2_ icrs1__ crd__ | 100011...11...01 |
| c.or | ca | crs2_ icrs1__ crd__ | 100011...10...01 |
| c.xor | ca | crs2_ icrs1__ crd__ | 100011...01...01 |
| c.sub | ca | crs2_ icrs1__ crd__ | 100011...00...01 |
| c.nop | ci | | 0000000000000001 |
| c.ebreak | cr | | 1001000000000010 |
| |
| # 0x0 is an illegal instruction by ISA specification. However it is often used |
| # as a canary after non-reachable code therefore it's included here. |
| unimp | ci | | 0000000000000000 |
