commit 3c5af1553ec09118eda16f6f59b0bf7babdc9ea8
author Jack Gallagher <jack.gallagher@arm.com> Wed Feb 22 08:40:45 2023
committer GitHub <noreply@github.com> Wed Feb 22 08:40:45 2023
tree 9751f2077cb21d6f15bde0869a2910de540c1606
parent 068bb90b2b26dcc96e3b47cce2a3263822f9e425

i#3044 AArch64 SVE codec: Add ADR instructions (#5866)

This patch adds the appropriate macros, tests and codec entries to
encode the following variants:
```
ADR     <Zd>.D, [<Zn>.D, <Zm>.D, SXTW <amount>]
ADR     <Zd>.D, [<Zn>.D, <Zm>.D, UXTW <amount>]
ADR     <Zd>.<Ts>, [<Zn>.<Ts>, <Zm>.<Ts>, <extend> <amount>]
```

and the required changes to support the use of vector registers in
base+disp adress operands.

This required two main changes:

1) Adding element size to base disp operand

 ADR uses Z vector registers for the base and index register so we
 need to be able to specify the element size in the operand.

 This adds an element size field to base+disp operands (AArch64
 only). The following sizes are supported:
     OPSZ_4: Single
     OPSZ_8: Double

 For example, the memory operand for:
```
     adr z0.d, [z1.d, z2.d, lsl 2]
```

 could be created with the call:
```
  opnd_create_vector_base_disp_aarch64(DR_REG_Z1, DR_REG_Z2,
                                       OPSZ_8, // Element size
                                       DR_EXTEND_UXTX, // LSL
                                       true, 0, 0,
                                       OPSZ_0, // Transfers 0 bytes
                                       2); // Shift amount
```
 This will also be needed for SVE scatter/gather instructions.

2) Move DR_REG_Z* < 256

 opnd_t only stores the first 8 bits of the reg_id_t values for the base
and index, so in order to use a Z register in an address operand we need
 to make sure the DR_REG_Z* constants are < 256.

 While I was there I also added the Z and P registers and one system
 register to the dr_reg_fixer array as they were previously missing.
 The B, H, S, D, Q registers have been changed to map to the Z registers
 because they overlap with the lower 128 bits of the Z registers.

Issues: #3044