commit 62a70d5c54e785d2099a785476bc6250751fd138
author Zhi An Ng <zhin@google.com> Thu Jul 21 22:34:43 2022
committer XNNPACK Team <xnnpack-github-robot@google.com> Thu Jul 21 22:35:52 2022
tree 81f1e27aea3a111ee678f197a24f3da3d04c02e9
parent 55ff666716ea7323bd92c423e47b354ff670c390

Add some AArch64 assemblers methods

PiperOrigin-RevId: 462485140

src/jit/aarch64-assembler.cc

diff --git a/src/jit/aarch64-assembler.cc b/src/jit/aarch64-assembler.cc
index 9a48022..e6aec59 100644
--- a/src/jit/aarch64-assembler.cc
+++ b/src/jit/aarch64-assembler.cc
@@ -390,6 +390,15 @@
   emit32(0x5E000400 | imm5 << 16 | rn(vn) | rd(dd));
 }
 
+void Assembler::fabs(VRegister vd, VRegister vn) {
+  if (!is_same_shape(vd, vn)) {
+    error_ = Error::kInvalidOperand;
+    return;
+  }
+
+  emit32(0x0EA0F800 | q(vd) | fp_sz(vn) | rn(vn) | rd(vd));
+}
+
 void Assembler::fadd(VRegister vd, VRegister vn, VRegister vm) {
   if (!is_same_shape(vd, vn, vm)) {
     error_ = Error::kInvalidOperand;
@@ -430,6 +439,24 @@
   emit32(0x0F801000 | q(vd) | fp_sz(vd) | hl(vm) | rm(vm) | rn(vn) | rd(vd));
 }
 
+void Assembler::fmul(VRegister vd, VRegister vn, VRegister vm) {
+  if (!is_same_shape(vd, vn, vm)) {
+    error_ = Error::kInvalidOperand;
+    return;
+  }
+
+  emit32(0x2E20DC00 | q(vd) | fp_sz(vn) | rm(vm) | rn(vn) | rd(vd));
+}
+
+void Assembler::fneg(VRegister vd, VRegister vn) {
+  if (!is_same_shape(vd, vn)) {
+    error_ = Error::kInvalidOperand;
+    return;
+  }
+
+  emit32(0x2EA0F800 | q(vd) | fp_sz(vn) | rn(vn) | rd(vd));
+}
+
 void Assembler::ld1(VRegisterList vs, MemOperand xn, int32_t imm) {
   VRegister vt = vs.vt1;
 

src/xnnpack/aarch64-assembler.h

diff --git a/src/xnnpack/aarch64-assembler.h b/src/xnnpack/aarch64-assembler.h
index ce7671d..18d6e78 100644
--- a/src/xnnpack/aarch64-assembler.h
+++ b/src/xnnpack/aarch64-assembler.h
@@ -361,10 +361,13 @@
 
   // SIMD instructions
   void dup(DRegister dd, VRegisterLane vn);
+  void fabs(VRegister vd, VRegister vn);
   void fadd(VRegister vd, VRegister vn, VRegister vm);
   void fmax(VRegister vd, VRegister vn, VRegister vm);
   void fmin(VRegister vd, VRegister vn, VRegister vm);
   void fmla(VRegister vd, VRegister vn, VRegisterLane vm);
+  void fmul(VRegister vd, VRegister vn, VRegister vm);
+  void fneg(VRegister vd, VRegister vn);
   void ld1(VRegisterList vs, MemOperand xn, int32_t imm);
   void ld1r(VRegisterList xs, MemOperand xn);
   void ld2r(VRegisterList xs, MemOperand xn);

test/aarch64-assembler.cc

diff --git a/test/aarch64-assembler.cc b/test/aarch64-assembler.cc
index bd80e95..ec99b84 100644
--- a/test/aarch64-assembler.cc
+++ b/test/aarch64-assembler.cc
@@ -121,6 +121,9 @@
   EXPECT_ERROR(Error::kInvalidOperand, a.dup(d16, v16.d()[2]));
   EXPECT_ERROR(Error::kInvalidOperand, a.dup(d16, v16.s()[1]));
 
+  CHECK_ENCODING(0x4EA0F8B0, a.fabs(v16.v4s(), v5.v4s()));
+  EXPECT_ERROR(Error::kInvalidOperand, a.fabs(v16.v4s(), v5.v2s()));
+
   CHECK_ENCODING(0x4E25D690, a.fadd(v16.v4s(), v20.v4s(), v5.v4s()));
   EXPECT_ERROR(Error::kInvalidOperand, a.fadd(v16.v4s(), v20.v4s(), v5.v2s()));
 
@@ -135,6 +138,12 @@
   EXPECT_ERROR(Error::kInvalidOperand, a.fmla(v16.v2d(), v20.v2d(), v0.s()[0]));
   EXPECT_ERROR(Error::kInvalidLaneIndex, a.fmla(v16.v4s(), v20.v4s(), v0.s()[4]));
 
+  CHECK_ENCODING(0x6E29DC61, a.fmul(v1.v4s(), v3.v4s(), v9.v4s()));
+  EXPECT_ERROR(Error::kInvalidOperand, a.fmul(v16.v4s(), v20.v4s(), v5.v2s()));
+
+  CHECK_ENCODING(0x6EA0FBC2, a.fneg(v2.v4s(), v30.v4s()));
+  EXPECT_ERROR(Error::kInvalidOperand, a.fneg(v2.v4s(), v30.v16b()));
+
   CHECK_ENCODING(0x0CDF7060, a.ld1({v0.v8b()}, mem[x3], 8));
   EXPECT_ERROR(Error::kInvalidOperand, a.ld1({v0.v8b()}, mem[x3], 16));
   EXPECT_ERROR(Error::kInvalidOperand, a.ld1({v0.v16b()}, mem[x3], 8));