)]}' { "log": [ { "commit": "e3de4913ee7367c2baf0f904a05f73ff24159aa1", "tree": "d58deaa5d836fe302af372fe56b46d7466db1941", "parents": [ "a936a0e9d09e2be96962353e989d21d13bb595e2" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 09 19:44:51 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 09 19:46:51 2026" }, "message": "Fix qd8 HVX GEMM/IGEMM build on Hexagon V69\n\nThe qd8-f32-qc4w/qc8w HVX GEMM and qd8-f32-qc8w HVX IGEMM kernels\nconverted int32 accumulators with Q6_Vsf_equals_Vw (vconv.sf.w),\nwhich only exists on Hexagon V73 and later, so XNNPACK HVX builds for\nV69 (Snapdragon 8 Gen 1) failed to compile.\n\nAdd xnn_cvt_f32_s32 to the HVX s32 SIMD header: vconv.sf.w on V73+,\nand an exact integer-only conversion with round-to-nearest-even on\nolder HVX. A qf32-based conversion is not exact on V69 (0 converts to\na denormal), so it is not used. Add a CvtF32S32 HVX SIMD test.\n\nPiperOrigin-RevId: 1017515267\n" }, { "commit": "a936a0e9d09e2be96962353e989d21d13bb595e2", "tree": "e684dd69c18f5c1f9167cd6e24f90fb07a09f83b", "parents": [ "b94680ba0e174647e053d2c9edd992cdc0f53a8c" ], "author": { "name": "Jeff Lee", "email": "jeffleetw@google.com", "time": "Mon Nov 09 04:19:32 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 09 04:20:42 2026" }, "message": "Add ARM SME2 and SME ACLE GEMM microkernels for `pf32-qc8w` and `pf32-qc4w` along with SME `x32` LHS packing microkernels, unit tests, and benchmarks.\n- Add `1x32` and `32x32` `pf32-qc8w` and `pf32-qc4w` GEMM microkernels for both ARM SME2 (`__sme2`) and ARM SME (`__sme`), plus the `xnn_x32_pack_lh` SME (`__sme`) LHS packing microkernel.\n- Unpack 4-bit weights in SME2 `pf32-qc4w` with `ZT0`/`LUTI4`. SME `pf32-qc4w` uses a 16-entry f32 lookup table held in a Z register (`and`/`lsr` + `svtbl`) when SVL \u003e\u003d 512, and an fp16 magic-number conversion (`sli`/`bsl`, one `fsub.h`, `fcvt`/`fcvtlt`) at SVL 128/256, selected at run time from `svcntsw()`.\n- Make `pf32-qc8w`/`pf32-qc4w` results independent of how N is split across calls: `1x32` keeps four K-accumulation chains per tile in every `nc` branch, and `32x32` accumulates `nc_rem \u003c\u003d vl` tails sequentially into `ZA0`/`ZA2` inside the same single `__arm_locally_streaming` call as `nc_rem \u003e vl`.\n- Seed the bias before the K-loop in every `1x32` `nc` branch and match odd-`K` remainder accumulation so `__sme` and `__sme2` produce bit-identical IEEE-754 results (including signed zero).\n- Use explicit C99 type-suffixed ACLE intrinsics, `XNN_PRAGMA_CLANG`, `XNN_ARCH_ARM64` guards, and `cn_stride \u003d\u003d sizeof(float)` assertions across all SME/SME2 microkernels.\n- `GemmMicrokernelTester`: check that `pf32-qc8w`/`pf32-qc4w` results are bit-identical when N is split into multiple-of-`nr` chunks.\n\nPiperOrigin-RevId: 1017005596\n" }, { "commit": "b94680ba0e174647e053d2c9edd992cdc0f53a8c", "tree": "228e01e0b8e4f1354c48a4413875173325ac8dda", "parents": [ "163fab0d681bed635bbcc7f4e35e13458db98cf4" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 09 03:11:56 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 09 03:13:31 2026" }, "message": "Add qp8_f32_qc2w_gemm benchmark for SME2 and add k_large unit tests\n\nGenerate `qp8_f32_qc2w_gemm_bench` from `qp8-f32-qc2w-gemm-minmax.yaml`,\nupdate `gemm-benchmark` to support 2-bit weight packing and `x8` LHS\npacking replicated across benchmark buffers, and add `k_large` (`k \u003d 64,\n128`) unit tests for `qp8_qc2w`.\n\nPiperOrigin-RevId: 1016979250\n" }, { "commit": "163fab0d681bed635bbcc7f4e35e13458db98cf4", "tree": "231a866dd9d604f3f8ce7cff05f708bfdf8e6fe1", "parents": [ "52fd02e78fee1832d621e664caf4f95b358d341f" ], "author": { "name": "Marie White", "email": "mariewhite@google.com", "time": "Sat Nov 07 10:08:33 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sat Nov 07 10:10:05 2026" }, "message": "When `A` has unit extent along `m` and `C` has `m \u003e 1`, compute `dot(A, B)`\nfirst and add `C` with a binary add so `add` performs the broadcast instead of\nredundantly computing the broadcasted dot output (and avoiding broadcasting\n`A` across `m` inside `transpose_a` dot paths).\n\nPiperOrigin-RevId: 1016205731\n" }, { "commit": "52fd02e78fee1832d621e664caf4f95b358d341f", "tree": "58a390c6138c9ab34af6e2994e70d880d8d43f00", "parents": [ "020575c2af6a7144d230ce14a592834b23b4f370" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 19:05:30 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 19:06:53 2026" }, "message": "Account for subnormal flush-to-zero in fully connected test tolerance.\n\nOn architectures running in flush-to-zero mode for FP16 (such as AArch64\nNEON), subnormal outputs can be flushed to zero, producing a discrepancy\nup to the smallest normal value (2^-14). When testing with small scales,\nthe accumulated tolerance could be smaller than this threshold, causing\nspurious test failures. Include the smallest normal value in the\nfloating-point tolerance calculation to prevent flakiness.\n\nPiperOrigin-RevId: 1015698335\n" }, { "commit": "020575c2af6a7144d230ce14a592834b23b4f370", "tree": "fb2005e969adc47027b47a7c34c12471ca74c2ba", "parents": [ "d4269f5f7712a96c6ce2fc04a68a3f2ea8601ccd" ], "author": { "name": "Jeff Lee", "email": "jeffleetw@google.com", "time": "Fri Nov 06 18:11:29 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 18:12:34 2026" }, "message": "Add ARM SME and SME2 ACLE x8-packq (f32qp8) microkernels and build rules\n\nKleidiAI SME and SME2 LHS packing implementations are written in\nassembly and require `XNN_ENABLE_KLEIDIAI`.\n\nAdd native C ACLE `x8-packq` (`f32qp8`) LHS dynamic quantization and\npacking microkernels (`xnn_x8_packq_f32qp8_ukernel__sme` and\n`xnn_x8_packq_f32qp8_ukernel__sme2`) using `\u003carm_sme.h\u003e` ZA-tile\ntransposes and `svprfb` software prefetching, along with `sme` and\n`sme2` C microkernel build targets and weak SME ABI runtime fallback\nstubs (`arm-sme-abi-stubs.c`).\n\n```bash\nbazel build -c opt //bench:x8_packq_bench\nbazel-bin/bench/x8_packq_bench \\\n --benchmark_filter\u003dx8_packq_f32qp8 --benchmark_min_time\u003d100x\n```\n\nPiperOrigin-RevId: 1015651561\n" }, { "commit": "d4269f5f7712a96c6ce2fc04a68a3f2ea8601ccd", "tree": "07a2f12e8990616fe9b59b77f4652a84878c71df", "parents": [ "46b694380b1108a9b674effc40525d0361b132b3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 18:02:17 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 18:03:54 2026" }, "message": "Fix infinity range and bf16 domains in test random generators\n\nClamp uniform float ranges to the type\u0027s finite range so an infinite\nbound no longer yields inf/NaN samples, and add bf16 domains for unary\nop tests. Subnormals are still allowed as test inputs; the generator\ntests no longer require that none are produced.\n\nPiperOrigin-RevId: 1015643419\n" }, { "commit": "46b694380b1108a9b674effc40525d0361b132b3", "tree": "5f5a200d976d6852e8d8f08475b5fdb6872c7a28", "parents": [ "6fb94d5bcac9d2ad7f375d4a046a21334cda1e7a" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Nov 06 11:04:31 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 11:05:37 2026" }, "message": "Look up deconvolution weights in the cache before packing them.\n\nThis avoids repacking uselessly.\n\nPiperOrigin-RevId: 1015404639\n" }, { "commit": "6fb94d5bcac9d2ad7f375d4a046a21334cda1e7a", "tree": "83e2deeb276aadaba54b7e31f836d98f0a95922c", "parents": [ "95a0001b2045774a8a655ed6d03e42ae1dbc192d" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 10:33:49 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 10:35:23 2026" }, "message": "Add build configuration flags (disabled by default via\n`--define\u003dxnnpack_enable_ace\u003dtrue` / `XNNPACK_ENABLE_ACE\u003dOFF`), CPUID\ndetection (`xnn_arch_x86_ace` / `YNN_ARCH_X86_ACE`), and deterministic\n8-bit signed outer-product (`TOP4BSSD`) GEMM microkernels (`16x32c4`\nand `1x32c4`) for x86 ACEv1 in XNNPACK and YNNPACK:\n\n```bash\nbazel build -c opt --define\u003dxnnpack_enable_ace\u003dtrue //bench:qd8_f32_qc8w_gemm_bench\nbazel-bin/bench/qd8_f32_qc8w_gemm_bench --benchmark_filter\u003dace --benchmark_min_time\u003d100x\n```\n\nPiperOrigin-RevId: 1015388582\n" }, { "commit": "95a0001b2045774a8a655ed6d03e42ae1dbc192d", "tree": "9aacecca9be4d83b787c2eca7db9a73985343927", "parents": [ "5c7bdb4b56c680f4301858bcfb7a942ffc735c59" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 10:00:25 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 10:01:19 2026" }, "message": "Disable ARM64 SME features when kernel SME is disabled.\n\nOn ARM64 Linux kernels where SME is disabled (such as kernels built\nwith CONFIG_ARM64_SME\u003dn or booted with arm64.nosme, or the Android\nemulator on an Apple M-series host), HWCAP2_SME is clear and\nprctl(PR_SME_GET_VL) fails (smelen \u003d\u003d 0), yet HWCAP2_SME2 and other\nSME sub-feature bits can remain set. Executing any SME instruction\nwhen base SME is disabled traps with SIGILL.\n\nGate SME feature detection on cpuinfo_has_arm_sme() and\ncpuinfo_get_max_arm_sme_length() \u003e 0 in XNNPACK and YNNPACK until\nhttps://github.com/pytorch/cpuinfo/issues/442 is fixed and smelen is\nimplemented for Windows on ARM.\n\nPiperOrigin-RevId: 1015373918\n" }, { "commit": "5c7bdb4b56c680f4301858bcfb7a942ffc735c59", "tree": "7e97f23b665982a33c0e2f65eed634e32aabc848", "parents": [ "38762be913c8654a79432a9968f9b143d2258b38" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 09:39:24 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 09:40:48 2026" }, "message": "Simplify AMX IGEMM microkernels for m \u003c 16 and remove 7x16c4 kernels.\n\nStage gathered input rows for 16xN AMX IGEMM microkernels directly into\nres[0] for 0 \u003c\u003d m \u003c mr instead of unconditionally resolving and loading\nall 16 rows into a separate 2 KB stack buffer. This eliminates the\nduplicate mr \u003d\u003d 1 branch inside the 16xN microkernels, reduces stack\nusage by 2 KB, shrinks compiled 16xN AMX IGEMM microkernels by 12-34%,\nand speeds up m \u003c 16 by up to 6.6% on Intel Granite Rapids.\n\nAlso remove the 5 unused 7x16c4 AMX GEMM and IGEMM microkernels.\n\nPiperOrigin-RevId: 1015363478\n" }, { "commit": "38762be913c8654a79432a9968f9b143d2258b38", "tree": "dce7899b9caa18d5e4383fb4a998409053d45607", "parents": [ "af32a5ebb9ff00b4281931ad553275161d28e253" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 08:37:52 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 08:39:22 2026" }, "message": "Detect RISC-V uarch via hwprobe to enable RVV FP16 on SiFive X280/X390.\n\nQuery `RISCV_HWPROBE_KEY_MVENDORID`, `RISCV_HWPROBE_KEY_MARCHID`, and\n`RISCV_HWPROBE_KEY_MIMPID` alongside `RISCV_HWPROBE_KEY_IMA_EXT_0` in\n`hardware-config.c` to decode `xnn_uarch_sifive_x280` and\n`xnn_uarch_sifive_x390` in a manner compatible with `cpuinfo`. Use the\ndetected microarchitecture as a fallback to enable\n`xnn_arch_riscv_vector_fp16_arith` on kernels where DeviceTree ISA\nstrings omit `Zfhmin`/`Zvfhmin` and cause `RISCV_HWPROBE_EXT_ZVFH` to\nbe cleared.\n\nPiperOrigin-RevId: 1015334273\n" }, { "commit": "af32a5ebb9ff00b4281931ad553275161d28e253", "tree": "3b4d7a726c7767a98da8c514083c4c7d95e7ba0c", "parents": [ "b57d7c656a109bc4c4b2b1b4b05fa25815dbefd0" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Nov 06 03:32:39 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 03:34:02 2026" }, "message": "Fix return types and signedness of HVX s8 and u8 SIMD reductions\n\n`xnn_reduce_max_s8` and `xnn_reduce_min_s8` in `s8-hvx.h` had a `float`\nreturn type, and `xnn_reduce_max_s8` dereferenced the result as\n`uint8_t`, causing negative `int8_t` results to be zero-extended to\n`[128.0f, 255.0f]` before being cast back to `int8_t` (which is\nundefined behavior for values `\u003e 127`). Similarly, `xnn_reduce_max_u8`\nand `xnn_reduce_min_u8` in `u8-hvx.h` had a `float` return type instead\nof `uint8_t`.\n\nRefactor the `s8` and `u8` SIMD unit tests into single source files\n(`test/simd/s8-simd.cc` and `test/simd/u8-simd.cc`) compiled per-ISA via\n`XNN_SIMD_\u003cARCH\u003e` defines, remove the generated per-ISA `.cc` files, and\nadd `ReduceMin` and `ReduceMax` unit tests.\n\nPiperOrigin-RevId: 1015179867\n" }, { "commit": "b57d7c656a109bc4c4b2b1b4b05fa25815dbefd0", "tree": "d464017cd94018b4708ba7343ec18d97cdeff8cb", "parents": [ "3552b033137169923ffce121d35eb3821c9ea12c" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Fri Nov 06 00:29:19 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Nov 06 00:30:34 2026" }, "message": "Add multiply_add elementwise kernels for (int8, int8, int32), (bf16, bf16, fp32), and (fp16, fp16, fp32).\n\nPiperOrigin-RevId: 1015078955\n" }, { "commit": "3552b033137169923ffce121d35eb3821c9ea12c", "tree": "74cbe2bf453e6c06cf12c381f44962e530005d51", "parents": [ "aa4235ff811a5ad7907fb060593ec88dc6d2428d" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Thu Nov 05 21:31:29 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Nov 05 21:32:56 2026" }, "message": "Update XNNPACK dependencies\n\nPiperOrigin-RevId: 1014954030\n" }, { "commit": "aa4235ff811a5ad7907fb060593ec88dc6d2428d", "tree": "52d033baba78e853cf90fcbfc4aef9014e670a01", "parents": [ "8d7a8efe3e9a635392fb38f5ef50df4e33b866c8" ], "author": { "name": "Samuel Fuller", "email": "samfuller@google.com", "time": "Thu Nov 05 18:32:09 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Nov 05 18:33:33 2026" }, "message": "In the 8-bit view of ZA, horizontal slices of 4 consecutive rows each,\ncorrespond to a single row from each of the 32-bit tiles 0, 1, 2 and 3. This change uses\n`svwrite_hor_za8_u8_vg4` / `svread_hor_za8_u8_vg4` together with `svld1_u8_x4` /\n`svst1_u8_x4` to load and store all four 32-bit tiles of row `m` with a single\n4-vector `MOVA` and a single 4-vector contiguous load/store (controlled by a\nsingle `svcount_t` predicate) instead of four separate `svld1_hor_za32` /\n`svst1_hor_za32` instructions per row.\n\nPiperOrigin-RevId: 1014816488\n" }, { "commit": "8d7a8efe3e9a635392fb38f5ef50df4e33b866c8", "tree": "e5968018022114b527435de865f90d91946310ba", "parents": [ "c9024d15c795f63af5f7ff887c6ea7ec3acbef8e" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Thu Nov 05 09:44:33 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Nov 05 09:46:05 2026" }, "message": "Support transposed inputs in pack_b and absorb transposes.\n\nAdd a transpose flag to the pack_b operator and packing kernel, allowing\ntransposed inputs (swapping K and N dimensions) to be packed directly,\nincluding for sub-byte types (such as int4 and int2).\n\nUpdate rewrite_pack_b_transpose to rewrite pack_b(transpose(x)) into\npack_b with the updated transpose flag, retaining a minimal aliased\ntranspose when remaining batch dimensions are permuted.\n\nPiperOrigin-RevId: 1014505651\n" }, { "commit": "c9024d15c795f63af5f7ff887c6ea7ec3acbef8e", "tree": "ecc0fa9b3e7815beb724a7d6d300bdc91575aad1", "parents": [ "82be86388c131862c3673c177d9dbcd5d3e3844d" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Nov 05 02:45:47 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Nov 05 02:47:11 2026" }, "message": "Add Qualcomm Hexagon HMX c4 qs8-qc4w and qs8-qc8w GEMM microkernels.\n\nImplements `xnn_qs8_qc4w_gemm_minmax_fp32_ukernel_32x64c4__hmx` and\n`xnn_qs8_qc8w_gemm_minmax_fp32_ukernel_32x64c4__hmx` for Qualcomm\nHexagon HMX (v73, v75, v79, v81), achieving up to 1.53 TOPS on\n`qs8_qc4w_gemm` and 1.38 TOPS on `qs8_qc8w_gemm` on Snapdragon 8\nElite Gen 5 (Hexagon v81).\n\nMeasured on Samsung S26 Ultra (Hexagon v81):\n\n`qs8_qc4w_gemm_fp32_bench` (`M\u003d256, N\u003d1024, K\u003d1024`):\n\n| Kernel | Latency | Throughput | vs. Scalar |\n| :----------------- | ---------: | ---------: | ---------: |\n| 4x4__scalar_fmagic | 838155 us | 0.64 GOPS | 1.0x |\n| 4x128c4__hvx | 15192 us | 35.3 GOPS | 55.2x |\n| 32x64c4__hmx | 351 us | 1.53 TOPS | 2,388x |\n\n`qs8_qc8w_gemm_fp32_bench` (`M\u003d256, N\u003d1024, K\u003d1024`):\n\n| Kernel | Latency | Throughput | vs. Scalar |\n| :----------------- | ---------: | ---------: | ---------: |\n| 3x4__scalar_lrintf | 1008202 us | 0.53 GOPS | 1.0x |\n| 4x128c4__hvx | 17779 us | 30.2 GOPS | 56.7x |\n| 32x64c4__hmx | 389 us | 1.38 TOPS | 2,590x |\n\nMobileNet v1 1x1 Convolutions (`qs8_qc8w_gemm_fp32_bench`):\n\n| Kernel | Latency | Throughput | vs. Scalar |\n| :----------------- | ---------: | ---------: | ---------: |\n| 3x4__scalar_lrintf | 2969320 us | 0.36 GOPS | 1.0x |\n| 4x128c4__hvx | 37630 us | 28.7 GOPS | 78.9x |\n| 32x64c4__hmx | 2294 us | 470.3 GOPS | 1,294x |\n\nMobileNet v2 End-to-End Subgraph (`QS8MobileNetV2`):\n\n| Kernel | Latency | Throughput | vs. Scalar |\n| :----------------- | ---------: | ---------: | ---------: |\n| Scalar (no HVX) | 635051 us | 0.94 GOPS | 1.0x |\n| HVX (4x128c4__hvx) | 18520 us | 32.4 GOPS | 34.3x |\n| HMX (32x64c4__hmx) | 14613 us | 41.1 GOPS | 43.5x |\n\n```bash\nbazel build -c opt --config\u003dhexagon_s26 \\\n //bench:qs8_qc4w_gemm_fp32_bench \\\n //bench:qs8_qc8w_gemm_fp32_bench \\\n //bench/subgraph:mobilenet\nbazel-bin/bench/qs8_qc4w_gemm_fp32_bench \\\n --benchmark_filter\u003d32x64c4__hmx --benchmark_min_time\u003d0.5s\nbazel-bin/bench/qs8_qc8w_gemm_fp32_bench \\\n --benchmark_filter\u003d32x64c4__hmx --benchmark_min_time\u003d0.5s\nbazel-bin/bench/subgraph/mobilenet \\\n --benchmark_filter\u003dQS8 --benchmark_min_time\u003d0.5s\n```\n\nPiperOrigin-RevId: 1014306555\n" }, { "commit": "82be86388c131862c3673c177d9dbcd5d3e3844d", "tree": "ef05332d99e47507e19cfe60ee71a03781eeeab3", "parents": [ "d6d1497364c47a405e94f9a5a26b5abf177b93a0" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Nov 04 01:42:40 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Nov 04 01:44:00 2026" }, "message": "Fix Hexagon HVX FP16 subgraph fallback and optimize f16\u003c-\u003ef32 vcvt\n\nFall back scalar_u1 FP16 elementwise and pooling configs to vectorized\nFP32 when FP16 arithmetic is not natively supported, keep FP16 GEMM ops\nin FP16 across fallback boundaries, and vectorize HVX f16\u003c-\u003ef32 vcvt\nacross 64-element blocks on all HVX versions.\n\n```bash\nbazel build -c opt //bench:vunary_bench\nbazel-bin/bench/vunary_bench --benchmark_filter\u003d\"f(16_f32|32_f16)_vcvt\" --benchmark_min_time\u003d0.05s\n```\n\nPiperOrigin-RevId: 1013424761\n" }, { "commit": "d6d1497364c47a405e94f9a5a26b5abf177b93a0", "tree": "501dd0f24b580d9d691e31dee26b096a8d792d2b", "parents": [ "81e7d0d2ed119b596c3eaeab57653153a08db281" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Nov 04 01:31:53 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Nov 04 01:34:04 2026" }, "message": "Remove unit input dimensions in reduction normalization.\n\nRemove input dimensions of size 1 in `xnn_normalize_reduction` unless\nthe reduction is over a single element, allowing reductions with\ntrailing unit non-reduced dimensions to use contiguous reduction\nmicrokernels.\n\n```bash\nbazel build -c opt //bench/subgraph:static_reduce\nbazel-bin/bench/subgraph/static_reduce --benchmark_filter\u003d\"FP32(Sum|Mean|Max)/\" --benchmark_min_time\u003d0.05s\n```\n\nPiperOrigin-RevId: 1013418806\n" }, { "commit": "81e7d0d2ed119b596c3eaeab57653153a08db281", "tree": "602a2bd8f6ac1e51bb79a0d329b10769a5391da0", "parents": [ "7528581228c09553283be2cee1738af5c73d03ff" ], "author": { "name": "Reilly Grant", "email": "reillyg@google.com", "time": "Wed Nov 04 01:15:46 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Nov 04 01:17:27 2026" }, "message": "Enforce 4D input shape in deconvolution-2d reshape\n\nUpdate the reshape function for the 2D deconvolution operator to strictly require 4-dimensional inputs instead of allowing 3D, matching the documentation\non xnn_define_deconvolution_2d.\n\nPiperOrigin-RevId: 1013409654\n" }, { "commit": "7528581228c09553283be2cee1738af5c73d03ff", "tree": "cee0f12d31ac0613c366550773e1d6fa9d4bd534", "parents": [ "d1d59d4b05f51c14103119d4985834ff6867c8c1" ], "author": { "name": "Reilly Grant", "email": "reillyg@google.com", "time": "Tue Nov 03 23:56:14 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Nov 03 23:57:15 2026" }, "message": "Avoid lowering tensor rank in LUT fusion when broadcasting static operands\n\nEnsure that a static operand does not broadcast a non-static operand to a higher rank before treating a binary node as a unary operation during LUT fusion. Otherwise, the fused unary node would be rewired to the lower-rank input, shrinking the output tensor\u0027s rank at reshape time and breaking downstream operators that expect the higher broadcasted rank.\n\nPiperOrigin-RevId: 1013358313\n" }, { "commit": "d1d59d4b05f51c14103119d4985834ff6867c8c1", "tree": "03cf0853905d40c67a3280980637b37c4ec4343a", "parents": [ "f745c33321c292e0adf1deaa0f4f588c55d935dd" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Mon Nov 02 21:26:55 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 21:28:16 2026" }, "message": "Replace the internal static_reshape, split_dim, fuse_dim, split_dims, and fuse_dims nodes with a single reshape node. A reshape is described by groups of input dimensions that are fused and split into groups of output dimensions. The public API is unchanged.\n\nAdd a fusion rewrite that combines reshape(reshape(x)) into one reshape.\n\nPiperOrigin-RevId: 1012407225\n" }, { "commit": "f745c33321c292e0adf1deaa0f4f588c55d935dd", "tree": "e4d0adae46ca7b6403ebf22bcce9f9a3493766fb", "parents": [ "40f3bc4d570bf69c87112ae5ca520c1ab356c772" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 21:18:08 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 21:19:42 2026" }, "message": "Fix 1x1 dynamic quantization check in convolution-2d subgraph test.\n\n`xnn_define_convolution_2d` only rewrites 1x1 stride-1 unpadded\n`groups \u003d\u003d 1` convolutions to `fully_connected` (with per-channel\ndynamic quantization `num_nonbatch_dims \u003d 1`) when\n`group_input_channels + group_output_channels \u003e 2`. Match this\ncondition in `test/subgraph/convolution-2d.cc` when choosing the\n`FakeDynamicQuantize` batch dimensions.\n\nPiperOrigin-RevId: 1012399981\n" }, { "commit": "40f3bc4d570bf69c87112ae5ca520c1ab356c772", "tree": "ea5e1f03a1e53e2ee3c6877eeada59d8ff7047a8", "parents": [ "46c2f295c38def1425e749da10e15e28a1353ec8" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 21:01:52 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 21:03:42 2026" }, "message": "Fix slow random shapes and increase shard count in YNNPACK dot test\n\nIn `TestStaticB` and `RandomDotShapes`, tensor dimensions are ordered\nouter-to-inner (`[m, k3, k2, k1]` for `a` and `[k3, k2, k1, n]` for\n`b`), so `k23_dim_dist` (`1..5`) should constrain the outer reduction\ndimensions `0..num_k_dims - 2` rather than `1..num_k_dims - 1` (which\nleft `k3`/`k2` up to 512 and shrank `k1` to `1..5`). Also bound `m` and\n`n` by `max_output_dim` in `RandomDotShapes` and increase `shard_count`\nfrom 24 to 36 so each parameterized test case runs in its own shard.\n\nPiperOrigin-RevId: 1012388199\n" }, { "commit": "46c2f295c38def1425e749da10e15e28a1353ec8", "tree": "0dbcf784170db7b9c6cbfa930d5d5a848eb4b2ac", "parents": [ "80bc909ef74295862090d17e53d42f500b0f8954" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Mon Nov 02 13:27:21 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 13:28:53 2026" }, "message": "Check unary datatypes when the node is defined.\n\nAn unimplemented datatype combination in `xnn_define_unary` now returns\n`unsupported_parameter` instead of failing (or asserting, for sub-byte\nconverts) when the runtime is created.\n\nAn unknown operator, or a non-convert operator whose input and output datatypes\ndiffer, returns `invalid_parameter`.\n\nPiperOrigin-RevId: 1012095078\n" }, { "commit": "80bc909ef74295862090d17e53d42f500b0f8954", "tree": "6bb1cb3dbc9ed82ea5f24746225d929858db02c6", "parents": [ "a7b933c539fbe3c13039a3118da40d7885565f51" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Mon Nov 02 10:19:34 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 10:20:57 2026" }, "message": "Add fp64 support to dot_bench\n\nPiperOrigin-RevId: 1012008086\n" }, { "commit": "a7b933c539fbe3c13039a3118da40d7885565f51", "tree": "b925053f802dd53d68a54403ec2547e41aa54684", "parents": [ "9b706e7a72a8c706ef1fa949749db1b3a419e5ca" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 09:44:25 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 09:46:13 2026" }, "message": "Add Qualcomm Hexagon HMX c2 f16-gemm microkernel.\n\nAdd the Qualcomm Hexagon HMX (`32x64c2`) `f16-gemm` microkernel with\n`XNN_ENABLE_HMX` build and runtime hardware detection to accelerate\nFP16 matrix multiplication on Hexagon cDSP.\n\nThe HMX `32x64c2` microkernel acquires the shared DSP HMX unit and VTCM\nworking set, double-buffers `c2`-packed RHS weight tiles in VTCM across\noutput channel panels, splits `K \u003e 1024` reductions into 64 KB chunks,\nand falls back to an HVX `Wqf32` loop on the same `c2`-packed weights\nwhen HMX or VTCM is unavailable.\n\nPiperOrigin-RevId: 1011990514\n" }, { "commit": "9b706e7a72a8c706ef1fa949749db1b3a419e5ca", "tree": "d56e47867dd36227761f14486201360bb89b7cf5", "parents": [ "9075d64edba547aae359699d0c1cb4ed70112761" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 09:23:50 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 09:25:47 2026" }, "message": "Use AVX-512 masked loads for AMX GEMM and IGEMM k remainders.\n\nWhen `kc` is not a multiple of the AMX K-tile width (`32` for `f16`\n`c2` microkernels or `64` for `qs8`/`qd8` `c4` microkernels), loading\nthe input tile directly from `a` with `_tile_loadd` when `kc` is not a\nmultiple of the channel group (`2` or `4`) reads up to `1` (`f16`) or\n`3` (`qs8`/`qd8`) uninitialized elements past the end of each input\nrow because AMX `tile_data.colsb` must be a multiple of 4 bytes.\n\nUnconditionally stage the `k !\u003d 0` input remainder through the stack\nbuffer using `_mm512_maskz_loadu_epi16` in `f16-gemm` (`c2`) and\n`_mm512_maskz_loadu_epi8` in `qs8-gemm` and `qs8-igemm` (`c4`),\nremoving the `(k \u0026 2) !\u003d 0` branch in `f16-gemm` and preventing\nout-of-bounds reads in `qs8`/`qd8` GEMM and IGEMM when `kc % 4 !\u003d 0`.\nAlso zero-pad trailing `N` channels in the `x8-packw` scalar `gio`\nremainder loop so packed weights contain no uninitialized bytes under\nMemorySanitizer.\n\n```bash\nbazel build -c opt //bench:f16_gemm_minmax_bench //bench:qs8_qc8w_gemm_fp32_bench\nbazel-bin/bench/f16_gemm_minmax_bench 128 128 63 128 128 64 --benchmark_filter\u003df16_gemm_minmax_ukernel_16x64c2__avx512amxfp16 --benchmark_min_time\u003d0.2s\nbazel-bin/bench/qs8_qc8w_gemm_fp32_bench 128 128 63 128 128 64 --benchmark_filter\u003dqs8_qc8w_gemm_minmax_fp32_ukernel_16x64c4__avx512amx --benchmark_min_time\u003d0.2s\n```\n\nPiperOrigin-RevId: 1011978521\n" }, { "commit": "9075d64edba547aae359699d0c1cb4ed70112761", "tree": "72a95a6a0012fd6d7e2d7c3f63405630ae74affd", "parents": [ "51b179de6f1d0ab8494357aa58b459619e053a50" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 08:46:03 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 08:47:53 2026" }, "message": "Extend Hexagon HVX `c4-hvx.c.in` GEMM and IGEMM templates to support\n`qs8`, `qs8_qc8w`, and `qs8_qc4w` with `fmagic` float-to-int rounding on\nHVX V73+/V81, 8-channel IGEMM loop unrolling, and `mr \u003d 4` (`1x128c4`\nand `4x128c4`) dispatch in `gemm-config.c`.\n\nBenchmarks on Samsung Galaxy S26 (Qualcomm Snapdragon 8 Elite Gen 5,\nHexagon V81 @ 2.112 GHz):\n\n| Model | Before | After | Improvement |\n| --- | ---: | ---: | ---: |\n| MobileNet v1 | 10,636 us | 9,847 us | 1.08x |\n| MobileNet v2 | 12,084 us | 11,153 us | 1.08x |\n| ResNet-18 | 25,348 us | 22,875 us | 1.11x |\n| ResNet-50 | 47,284 us | 43,362 us | 1.09x |\n| FullyConnected | 708 us | 642 us | 1.10x |\n\n```bash\nbazel build -c opt //bench/operators:convolution_bench //bench/subgraph:fully_connected\nbazel-bin/bench/operators/convolution_bench --benchmark_filter\u003dxnnpack_convolution_qs8 --benchmark_min_time\u003d0.02s\nbazel-bin/bench/subgraph/fully_connected --benchmark_filter\u003dQS8QC4WFullyConnected/M:128/K:512/N:1024 --benchmark_min_time\u003d0.05s\n```\n\nPiperOrigin-RevId: 1011958099\n" }, { "commit": "51b179de6f1d0ab8494357aa58b459619e053a50", "tree": "393b354a7d7033356bf2c95dbd02c4ceaf91e399", "parents": [ "08cc38b61f7589f84e91c6e343e0f130ae3279ca" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Nov 02 05:38:56 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Nov 02 05:39:58 2026" }, "message": "Disable ARM SME on Windows ARM64 and guard naked SME stubs for GCC.\n\nMSVC on Windows ARM64 does not support ARM SME/SME2 ACLE or inline\nassembly, and AArch64 GCC does not support __attribute__((naked)).\nDisable ARM SME, SME2, and SME ACLE on Windows ARM64 in Bazel, GN, and\nCMake, disable SME ACLE on GCC in Bazel, and guard the naked inline\nassembly stubs in arm-sme-abi-stubs.c with XNN_COMPILER_CLANG.\n\nPiperOrigin-RevId: 1011870057\n" }, { "commit": "08cc38b61f7589f84e91c6e343e0f130ae3279ca", "tree": "7f9ae5338f965a43f479b7332cbe12554e9def41", "parents": [ "1043ad9b2a1af853f255fe15bb0404f07a77ef02" ], "author": { "name": "Changming Sun", "email": "changmingsun@google.com", "time": "Sun Nov 01 14:32:17 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sun Nov 01 14:34:17 2026" }, "message": "Rollback Skip dequant BMM rewrite when M \u003e mr.\n\nPiperOrigin-RevId: 1011601006\n" }, { "commit": "1043ad9b2a1af853f255fe15bb0404f07a77ef02", "tree": "02c001e858e70752539506fe4901b70b69382b03", "parents": [ "fc1a2623138f0b7d94d77255d9042034882ad6ac" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Sat Oct 31 04:42:37 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sat Oct 31 04:43:54 2026" }, "message": "Choose order of m or n loops based on the size of A or B\n\nThis allows the example in https://github.com/google/XNNPACK/pull/11657 to fuse much better, reducing the size of our intermediate allocations from ~40MB to ~0.25MB.\n\nPiperOrigin-RevId: 1011010599\n" }, { "commit": "fc1a2623138f0b7d94d77255d9042034882ad6ac", "tree": "61d6df1d95977c80903e2037c7444461bc27189a", "parents": [ "f11425be33b28b803ab4abb894bcbe60ed011da0" ], "author": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sat Oct 31 02:33:00 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sat Oct 31 02:34:02 2026" }, "message": "Disable KleidiAI assembly and Arm64 SVE/SME architecture flags when building with MemorySanitizer, since MSan does not instrument inline assembly in KleidiAI or SVE/SME ACLE intrinsics.\n\nPiperOrigin-RevId: 1010961398\n" }, { "commit": "f11425be33b28b803ab4abb894bcbe60ed011da0", "tree": "c24e0e1fa09f6487638932ef192d77aba0e1541c", "parents": [ "74fc9607957f30740bc90f0373da6f9cd45d91db" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Sat Oct 31 00:41:32 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sat Oct 31 00:42:46 2026" }, "message": "Update XNNPACK dependencies\n\nPiperOrigin-RevId: 1010916082\n" }, { "commit": "74fc9607957f30740bc90f0373da6f9cd45d91db", "tree": "e319be2d547eaa865df4794db09ef51d5c869981", "parents": [ "2691822b57e30173a7a1d417d30747fe59dfc7e3" ], "author": { "name": "Samuel Fuller", "email": "samfuller@google.com", "time": "Fri Oct 30 20:14:01 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 20:15:50 2026" }, "message": "Make ARM SME ABI stubs naked and uninstrumented to preserve caller registers\n\nPiperOrigin-RevId: 1010742801\n" }, { "commit": "2691822b57e30173a7a1d417d30747fe59dfc7e3", "tree": "1696326dbb578de5a5894277cd8c25735a388359", "parents": [ "9167c95da0e4b9993dfee98aecf682b7850a602f" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 17:34:08 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 17:35:30 2026" }, "message": "Return `unsupported_parameter` instead of `invalid_parameter` for unimplemented operator cases.\n\nSome checks are also moved up to keep legitimate `invalid_parameter`\ncases to be returned as such.\n\n- `xnn_define_static_reduce`\n - For more than `XNN_MAX_TENSOR_DIMS` reduction axes.\n - For quantized min/max reductions with mismatched input/output\n quantization.\n\n- `xnn_define_static_reduce_v2`\n - For input datatypes without a kernel.\n - For `sum_squared` or `mean_squared` on qint8/quint8.\n - For more than `XNN_MAX_TENSOR_DIMS` reduction axes.\n\n- `xnn_define_pack_lh`\n - When the input or output datatype has no kernel.\n - Build the pack-lh subgraph test with Bazel.\n\n- `xnn_define_static_slice_v3`\n - For strides other than 1.\n - For datatypes that aren\u0027t byte-addressable.\n\n- `xnn_define_concatenate`\n - When the number of inputs exceeds `XNN_MAX_OPERATOR_OBJECTS`.\n - For datatypes that aren\u0027t byte-addressable.\n\n- `xnn_define_even_split`\n - When the number of outputs exceeds `XNN_MAX_OUTPUTS`.\n - For datatypes that aren\u0027t byte-addressable.\n\n- `xnn_define_rope`\n - When the weights\u0027 datatype is different from the inputs\u0027.\n\n- `xnn_define_space_to_depth_2d`\n- `xnn_define_depth_to_space_2d`\n - For datatypes that aren\u0027t byte-addressable.\n\n The datatype-match check is moved up: mismatched input/output\n datatypes are still reported as `invalid_parameter`.\n\n- `xnn_define_convolution_2d`\n - For datatypes and datatype combinations without a kernel.\n - For a qint8 filter with a non-zero zero point.\n - For a non-static filter or bias.\n - For a qcint8 filter quantized along a dimension other than the output channels.\n - For a qcint8 filter with per-channel zero points.\n\n- `xnn_define_depthwise_convolution_2d`\n - For datatypes and datatype combinations without a kernel.\n - For a qint8 filter with a non-zero zero point.\n - For a non-static filter or bias.\n - For a qcint8 filter quantized along a dimension other than the last one.\n - For a qcint8 filter with per-channel zero points.\n\n- `xnn_define_deconvolution_2d`\n - For datatypes and datatype combinations without a kernel.\n - For a non-static filter or bias.\n - For a qcint8 filter quantized along a dimension other than the output channels.\n - For a qint8 filter with a non-zero zero point.\n - For a qcint8 filter with per-channel zero points.\n\n- `xnn_define_fully_connected`\n - When called with a well-formed combination of datatypes,\n quantization or non-static weights that isn\u0027t implemented.\n - For qbint4 block sizes that aren\u0027t a multiple of `XNN_MIN_BLOCKSIZE`,\n\n The same block size check in the fully connected operator API, which\n runtime creation failed in, now also returns `unsupported_parameter`.\n\n A block size of 0 is still invalid.\n - For transposed qbint4 weights,\n - For non-static fp32 weights or biases with fp16 input and output.\n\n- `xnn_define_fully_connected_sparse`\n - When called with a well-formed combination of datatypes,\n quantization or non-static weights that isn\u0027t implemented.\n - Accepts fp16 filters with fp32 input and output.\n\nPiperOrigin-RevId: 1010622866\n" }, { "commit": "9167c95da0e4b9993dfee98aecf682b7850a602f", "tree": "e8bd96b34af42f1698f53dfa8c94eecd2b69ff12", "parents": [ "e8773373f50a8d7e1965d9952b0b39e00bdd08ee" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 17:15:19 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 17:16:43 2026" }, "message": "Define quantized internal values in `SubgraphTester`.\n\n`SubgraphTester` could only define quantized values with external IDs, so tests\nthat check node definitions with quantized values set up their subgraphs by\nhand.\n\n- `AddInternalDynamicTensor` and `AddInternalStaticTensor` now take optional\n quantization parameters.\n- `AddInternalChannelwiseQuantizedTensor` and\n `AddInternalBlockwiseQuantizedTensor` define channelwise (with optional\n per-channel zero points) and blockwise quantized internal values.\n\nPiperOrigin-RevId: 1010608974\n" }, { "commit": "e8773373f50a8d7e1965d9952b0b39e00bdd08ee", "tree": "5652f5360127edb1ed2a637931ac53c2db83fb7e", "parents": [ "76628313634e62f73f2ad4762a84fb9489d1ad15" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 30 16:40:49 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 16:42:01 2026" }, "message": "YNNPACK: Fix RISC-V Zvfh Clang version check in half.h\n\nIn Clang, `__clang__` is defined as `1` while `__clang_major__` holds\nthe major version number. Because `__clang__ \u003e\u003d 1600` was always false,\n`YNN_ARCH_FLOAT16` was never enabled for RISC-V `Zvfh` targets, causing\n`ynn::half` to fall back to software float-to-half bit manipulation\ninstead of native `_Float16` hardware conversions.\n\nCheck `defined(__clang__) \u0026\u0026 __clang_major__ \u003e\u003d 16` so that\n`YNN_ARCH_FLOAT16` is enabled on RISC-V `Zvfh` with Clang 16+.\n\nPiperOrigin-RevId: 1010582135\n" }, { "commit": "76628313634e62f73f2ad4762a84fb9489d1ad15", "tree": "23b9ed01682946d45a237558f78595c11c6cf520", "parents": [ "4a85b2996f8a17273a70cbcf1ee610ca01333dc2" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 30 16:33:17 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 16:36:07 2026" }, "message": "f16-vlog test fix\n\nPiperOrigin-RevId: 1010576468\n" }, { "commit": "4a85b2996f8a17273a70cbcf1ee610ca01333dc2", "tree": "dc5c62b7316a311cff16f7dc0f985c5441d2677d", "parents": [ "264a9a85b0413c64bcf5c71e8f6f6f3d3e3f47fa" ], "author": { "name": "Samuel Fuller", "email": "samfuller@google.com", "time": "Fri Oct 30 16:31:01 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 16:32:39 2026" }, "message": "Add `+sme` target feature to `sme2_microkernels` in `BUILD.gn`.\n\nPassing `-Xclang -target-feature -Xclang +sme2` directly to Clang\u0027s `cc1` frontend bypasses the driver\u0027s `-march` feature dependency resolution and does not implicitly enable `+sme`. Without `+sme`, compiling SME2 ACLE microkernels fails in `gn-linux-aarch64` with errors that streaming-SVE functions and SVE vector types (`svbool_t`, `svcount_t`, etc.) require `sme`. Note that `+sve` and `+sve2` must not be enabled here so LLVM does not emit non-streaming SVE instructions in helper functions on SME2-without-SVE hardware.\n\nPiperOrigin-RevId: 1010574828\n" }, { "commit": "264a9a85b0413c64bcf5c71e8f6f6f3d3e3f47fa", "tree": "72e9fbab3e90c793e40d52fe779036a4f95fbd30", "parents": [ "09d1f6b9c211f7da9bbfce7c9f538bca02487c21" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 14:12:48 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 14:15:35 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_softmax`.\n\nInstead of `invalid_parameter` when the input or output datatype has no\nkernel, since the call is well-formed but unimplemented.\n\nMalformed calls (e.g. mismatching input/output datatypes) still return\n`invalid_parameter`.\n\nPiperOrigin-RevId: 1010493893\n" }, { "commit": "09d1f6b9c211f7da9bbfce7c9f538bca02487c21", "tree": "20a8905908ebd8842795082de4dff908b9e0b426", "parents": [ "113dc4aec9aa9f9d3704fb6f8183514d4f27b386" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:42:50 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:43:51 2026" }, "message": "Return `unsupported_parameter` for unimplemented `xnn_define_static_transpose` cases.\n\nInstead of `invalid_parameter` for ranks above `XNN_MAX_TENSOR_DIMS` and for\ndatatypes that aren\u0027t byte-addressable.\n\nThe datatype-match check now runs first, so mismatching input and output\ndatatypes are still reported as `invalid_parameter`.\n\nPiperOrigin-RevId: 1010390213\n" }, { "commit": "113dc4aec9aa9f9d3704fb6f8183514d4f27b386", "tree": "d8e08e5ba29b0a999a5ed468732bf91dec309264", "parents": [ "9c1ad7d6efd492bec3fb9119afb551c9cbcd096a" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:36:20 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:37:33 2026" }, "message": "Don\u0027t read sub-byte static scalars as floats in the subgraph optimizer.\n\nThe subgraph optimizer reads every static value with one element as a float to\nfind constants, copying `xnn_datatype_size_bytes` bytes in\n`get_scalar_value_as_float`, which asserts (or is undefined behavior) for\nsub-byte datatypes such as a 1x1 qcint4 filter. It now returns NaN for values\nwhose datatype isn\u0027t byte-addressable.\n\nPiperOrigin-RevId: 1010386779\n" }, { "commit": "9c1ad7d6efd492bec3fb9119afb551c9cbcd096a", "tree": "f555570720b552475296a33998b8c047dd683e31", "parents": [ "31e694a0fd19e59b7664d07582fa62cdf0ca1db6" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:14:38 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:19:09 2026" }, "message": "Reject per-tensor definitions of channelwise and blockwise datatypes.\n\n`xnn_define_quantized_tensor_value` now returns `invalid_parameter` for qcint2,\nqcint4, qcint8 and qbint4, which need\n`xnn_define_channelwise_quantized_tensor_value` or\n`xnn_define_blockwise_quantized_tensor_value`; a per-tensor qcint32 is still\naccepted for biases, whose scale isn\u0027t read as channelwise.\n\nLikewise, a known datatype passed to the wrong tensor definition function\nreturns `invalid_parameter` instead of `unsupported_parameter`; unknown\ndatatypes stay unsupported.\n\nPiperOrigin-RevId: 1010375406\n" }, { "commit": "31e694a0fd19e59b7664d07582fa62cdf0ca1db6", "tree": "0e6548d40db987b8820d56e6b3e374c7223c29e6", "parents": [ "1499bfa35c76e9d0f67744983b89950ff6574f8b" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:12:34 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:14:59 2026" }, "message": "Return `unsupported_parameter` for sub-byte datatypes in copy-like nodes.\n\nInstead of `invalid_parameter` for datatypes that aren\u0027t byte-addressable, in\nthe copy, reshape, broadcast, expand-dims, fuse-dims and split-dim definitions.\n\nThe datatype-match check now runs first, so mismatching input and output\ndatatypes are still reported as `invalid_parameter`.\n\nPiperOrigin-RevId: 1010374525\n" }, { "commit": "1499bfa35c76e9d0f67744983b89950ff6574f8b", "tree": "6863fc4de81a10d23c2daa6a422c235df2c75ba2", "parents": [ "6304ce45de73ad685a6e74b61e794dcd8e6dd3cf" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:11:07 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:14:11 2026" }, "message": "Return `unsupported_parameter` for unimplemented non-zero zero points.\n\nInstead of `invalid_parameter` for a non-zero zero point on qint2, qcint2,\nqcint8, qcint32 and qint32 values, since it is well-formed but not implemented.\n\nZero points outside the datatype\u0027s range ([-2, 1] for 2-bit, [-128, 127] for\nqcint8) still return `invalid_parameter`.\n\nPiperOrigin-RevId: 1010373624\n" }, { "commit": "6304ce45de73ad685a6e74b61e794dcd8e6dd3cf", "tree": "df5f70609a41499f8010fc505297e3ee8a44f96b", "parents": [ "bc2bbfb1488de940c20054b95651affe371126a8" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Fri Oct 30 10:09:53 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 10:11:03 2026" }, "message": "Return `unsupported_parameter` for unimplemented `xnn_define_batch_matrix_multiply` cases.\n\nInstead of `invalid_parameter` when called with datatypes or a combination of\ndatatypes that isn\u0027t implemented.\n\nPiperOrigin-RevId: 1010372869\n" }, { "commit": "bc2bbfb1488de940c20054b95651affe371126a8", "tree": "0ee35c11f5e44d86d499aa9e222004e4e40a5abd", "parents": [ "c58baeeafe3fb0a142ca537b0af86f58fe5bc5d4" ], "author": { "name": "Jeff Lee", "email": "jeffleetw@google.com", "time": "Fri Oct 30 06:08:47 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 06:10:21 2026" }, "message": "Add ARM SME2 ACLE GEMM for pf16 and pf32 and LHS packing microkernels, along with unit tests and benchmarks.\n\nPiperOrigin-RevId: 1010251487\n" }, { "commit": "c58baeeafe3fb0a142ca537b0af86f58fe5bc5d4", "tree": "eea31e81beb50ff43b34423c0aa14c8a1e97817a", "parents": [ "5896bd0940050aa2d094c13e192bb585bd167d80" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Oct 30 04:29:50 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 04:30:44 2026" }, "message": "Fix RISC-V Vector build errors, crashes, and test bugs across Coral\nv3 (RV32 Zve32f, VLEN\u003d128), SiFive X280 (VLEN\u003d512), and SiFive X390\n(VLEN\u003d512/1024).\n\n| Bug | Coral v3 | X280 | X390 |\n| ---------------------------------- | -------- | ------ | ------ |\n| Build: RV32 copts \u0026 Zvfh default | Build | Pass | Pass |\n| Crash: f32-argmaxpool \u003e9 assert | Crash | Crash | Crash |\n| Crash: conv-hwc2chw NULL ukernel | Pass | Crash | Crash |\n| Crash: conv-nchw NULL dwconv | Pass | Crash | Crash |\n| Crash: uint8_t tile VLEN\u003e\u003d512 | Pass | Crash | Crash |\n| Test: f16-vlog unsigned shift | Skip | Fail | Fail |\n| Test: rsum2 2x batch scale | Pass | Pass | Fail |\n| Test: vgelu scalar FMA clamp | Fail | Fail | Fail |\n| Test: xN-transpose bh/bw \u0026 skip | Fail | Fail | Fail |\n\nPiperOrigin-RevId: 1010205930\n" }, { "commit": "5896bd0940050aa2d094c13e192bb585bd167d80", "tree": "1f96bffbcf40d42f5d233393c698e4f5bce4b8bb", "parents": [ "a30d821b11fbcbb18aa739b4e5137b37f734db6f" ], "author": { "name": "Samuel Fuller", "email": "samfuller@google.com", "time": "Fri Oct 30 01:59:33 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 02:04:20 2026" }, "message": "Use uint64_t for Shape dimensions and ops calculation in YNNPACK dot benchmark. The previous usage of `int` would overflow in the calculation if the shape dimensions were too large. (i.e. `m * n * k \u003e\u003d 2^32`). This would make the benchmark erroneously report \"0\" for ops calculations.\n\nPiperOrigin-RevId: 1010140163\n" }, { "commit": "a30d821b11fbcbb18aa739b4e5137b37f734db6f", "tree": "5360e1398b38abb15ff65dc38a79e8e12cc550bd", "parents": [ "f7b069726648094dbde7ae11bfee196e2a9d4dbd" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Fri Oct 30 01:59:20 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 30 02:01:02 2026" }, "message": "Fix Unpooling2D.ReshapeOverflowOutputSize test attempting a huge allocation on 32-bit targets.\n\nPiperOrigin-RevId: 1010140081\n" }, { "commit": "f7b069726648094dbde7ae11bfee196e2a9d4dbd", "tree": "87c95e6ac896b36594ad1423a778025c6bf429dd", "parents": [ "1025db72bf1a102f148b3d43acd5a50a370b5888" ], "author": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 20:40:35 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 20:42:14 2026" }, "message": "[jax-buildcop] [YNNPACK] Use unpacked_kernel in define_dot when pack_b is false\n\nWhen `should_pack_b` returns `false`, `define_dot` still checked `kernel.flags \u0026 dot_flag::transpose_a` and captured `kernel.tile_m` and `kernel.tile_k` from the packed `kernel` instead of `unpacked_kernel`. On ARM CPUs with `neonbf16` or `neoni8mm`, the packed kernel sets `dot_flag::transpose_a` (`tile_k \u003e 1`) while the `tile_k \u003d 1` unpacked kernel does not, causing `make_dot_impl` to query for a non-existent `tile_k \u003d 1` kernel with `transpose_a \u003d true` and dereference a null kernel pointer.\n\nPiperOrigin-RevId: 1009929104\n" }, { "commit": "1025db72bf1a102f148b3d43acd5a50a370b5888", "tree": "bee4f2f85f571e463524298c0344dd6b18f5efa7", "parents": [ "e216faa98df6184d618e7615c6e639bd4571c863" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 15:30:23 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 15:34:47 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_rope`.\n\nInstead of `invalid_parameter` when the input, weights or output\ndatatype has no kernel, since the call is well-formed but unimplemented.\n\nMalformed calls (e.g. mismatching input/output datatypes) still return\n`invalid_parameter`.\n\nPiperOrigin-RevId: 1009708918\n" }, { "commit": "e216faa98df6184d618e7615c6e639bd4571c863", "tree": "4a10dd6f8e6741041166477e42faf55dc5eed0fa", "parents": [ "890fe8a4c3b0263aa0b42c3f618b3b33461ad899" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 15:28:08 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 15:33:22 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_unpooling_2d`.\n\nInstead of `invalid_parameter` when the input value or output datatype\nhas no kernel, since the call is well-formed but unimplemented.\n\nMalformed calls (zero pooling size, bad value IDs, non-dense values)\nstill return `invalid_parameter`.\n\nPiperOrigin-RevId: 1009707616\n" }, { "commit": "890fe8a4c3b0263aa0b42c3f618b3b33461ad899", "tree": "64d17f04f486f2e24cf1584ba035f7a1c12b0813", "parents": [ "98188a5469205f876fbf20c75f33aff40775af9b" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 15:27:16 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 15:28:52 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_average_pooling_2d`.\n\nInstead of `invalid_parameter` when the input or output datatype has no\nkernel, since the call is well-formed but unimplemented.\n\nMalformed calls (zero pooling size or stride, bad output range,\nconflicting padding) still return `invalid_parameter`.\n\nPiperOrigin-RevId: 1009707124\n" }, { "commit": "98188a5469205f876fbf20c75f33aff40775af9b", "tree": "7531745205c35cd96dfdc6dbfcb222895680ec75", "parents": [ "5ebc3f114a6afb65edb0f287c0653d11d0438dcf" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 11:01:33 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 11:02:29 2026" }, "message": "Map XNNPACK statuses to absl status codes.\n\nThe XNNPACK backend turned every XNNPACK failure into `Internal`, so a request\nthat XNNPACK doesn\u0027t support looked like an internal error, and the backend\nre-implemented XNNPACK\u0027s checks to return `Unimplemented` instead.\n\nXNNPACK now reports a well-formed request that it doesn\u0027t implement as\n`xnn_status_unsupported_parameter` and a malformed call as\n`xnn_status_invalid_parameter`. `XnnStatusToAbsl` maps them like\n`YnnStatusToAbsl` does for YNNPACK:\n\n- `xnn_status_unsupported_parameter` and `xnn_status_unsupported_hardware` →\n `Unimplemented`,\n- `xnn_status_invalid_parameter` → `InvalidArgument`,\n- `xnn_status_out_of_memory` → `ResourceExhausted`,\n- anything else → `Internal`.\n\nThe backend\u0027s check that blockwise quantized values are int4 is removed:\nXNNPACK reports other blockwise datatypes as unsupported when the value is\ndefined.\n\nPiperOrigin-RevId: 1009578530\n" }, { "commit": "5ebc3f114a6afb65edb0f287c0653d11d0438dcf", "tree": "01eb5e8230a1d49b1498f31d1435516f7996c7be", "parents": [ "cde841723ad744339015032cc26355777119bb86" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 29 10:53:05 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 10:54:34 2026" }, "message": "Add AVX512SKX c2 x16-packw microkernels for AMX-FP16 GEMM.\n\nAdd AVX512SKX GOI and GIO `x16-packw` microkernels with `kr \u003d 2` (`c2`)\nfor `nr \u003d 16, 32, 64` and wire `x64c2` into the AMX-FP16 GEMM config to\nreplace scalar reference packing for dynamic FP16 weights.\n\nIntel Granite Rapids single-core `FP16Attention` subgraph latency\n(T / H / N / S):\n\n| Model / Shape | Before | After | Improvement |\n| :--- | ---: | ---: | ---: |\n| `FP16Attention` (1 / 64 / 8 / 256) | 358 us | 58.1 us | -83.8% (6.16x) |\n| `FP16Attention` (1 / 64 / 8 / 512) | 732 us | 166 us | -77.3% (4.41x) |\n| `FP16Attention` (1 / 64 / 8 / 1024) | 1,567 us | 420 us | -73.2% (3.73x) |\n| `FP16Attention` (1 / 64 / 32 / 1024) | 7,500 us | 2,914 us | -61.1% (2.57x) |\n| `FP16Attention` (1 / 64 / 32 / 4096) | 29,953 us | 11,543 us | -61.5% (2.59x) |\n| `FP16Attention` (64 / 64 / 32 / 64) | 563 us | 260 us | -53.8% (2.17x) |\n| `FP16Attention` (256 / 64 / 8 / 256) | 865 us | 564 us | -34.8% (1.53x) |\n| `FP16Attention` (256 / 64 / 32 / 256) | 3,560 us | 2,406 us | -32.4% (1.48x) |\n| `FP16Attention` (512 / 64 / 8 / 512) | 2,318 us | 1,753 us | -24.4% (1.32x) |\n| `FP16Attention` (1024 / 64 / 8 / 1024) | 7,199 us | 6,090 us | -15.4% (1.18x) |\n| `FP16Attention` (1024 / 64 / 32 / 1024) | 30,385 us | 25,747 us | -15.3% (1.18x) |\n| `FP16Attention` (4096 / 64 / 32 / 4096) | 434,915 us | 414,939 us | -4.6% (1.05x) |\n\nAMD Zen 4 `x16-packw` microkernel latency:\n\n| Kernel | N\u003d4096, K\u003d1024 | Speedup |\n| :--- | ---: | ---: |\n| `xnn_pack_f16_gemm_goi_w` | 8,967.8 us | 1.00x |\n| `goi_ukernel_x32__avx512skx_u16` | 763.1 us | 11.8x |\n| `goi_ukernel_x64__avx512skx_u16_prfm` | 653.1 us | 13.7x |\n| `goi_ukernel_x16c2__avx512skx_u16` | 478.1 us | 18.8x |\n| `goi_ukernel_x16c2__avx512skx_u16_prfm` | 552.0 us | 16.2x |\n| `goi_ukernel_x32c2__avx512skx_u16` | 590.0 us | 15.2x |\n| `goi_ukernel_x32c2__avx512skx_u16_prfm` | 521.4 us | 17.2x |\n| `goi_ukernel_x64c2__avx512skx_u16` | 699.4 us | 12.8x |\n| `goi_ukernel_x64c2__avx512skx_u16_prfm` | 530.9 us | 16.9x |\n| `gio_ukernel_x16c2__avx512skx_u2` | 1,209.5 us | 7.4x |\n| `gio_ukernel_x32c2__avx512skx_u2` | 682.1 us | 13.1x |\n| `gio_ukernel_x32c2__avx512skx_u2_prfm` | 621.1 us | 14.4x |\n| `gio_ukernel_x64c2__avx512skx_u2` | 603.4 us | 14.9x |\n| `gio_ukernel_x64c2__avx512skx_u2_prfm` | 489.7 us | 18.3x |\n\n```bash\nbazel build -c opt //bench/subgraph:attention //bench:x16_packw_bench\nbazel-bin/bench/subgraph/attention --benchmark_filter\u003dFP16Attention --benchmark_min_time\u003d1s --benchmark_repetitions\u003d3\nbazel-bin/bench/x16_packw_bench --benchmark_filter\u003d\"x64(__scalar|c2__avx512skx)\" --benchmark_min_time\u003d0.5s 8 1 256 64 8 1 1024 64 32 1 1024 64 32 1 4096 64\n```\n\nPiperOrigin-RevId: 1009574849\n" }, { "commit": "cde841723ad744339015032cc26355777119bb86", "tree": "02d85f9c8f7744dc252ea371d777d98d22f309af", "parents": [ "cb7afb3d422631f173cd3007095a5cccfac8ac9c" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 29 09:55:09 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:58:05 2026" }, "message": "[YNNPACK] Fix src2 operand in GCC Intel-syntax AMX tile dot product\n\nThe -masm\u003dintel alternative of YNN_TILE_DP_IMPL passed src1 as both\nsource operands instead of src1 and src2, so GCC builds with\n-masm\u003dintel encoded A*A instead of A*B, which the assembler\nrejects (\"all tmm registers must be distinct\").\nPiperOrigin-RevId: 1009546363\n" }, { "commit": "cb7afb3d422631f173cd3007095a5cccfac8ac9c", "tree": "3f11e5d1e5106c11c6dc857592f655bb871fb16f", "parents": [ "d1002e131182ffd5af2f42950a758de0d6d57d93" ], "author": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:53:06 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:54:45 2026" }, "message": "Use dynamic pre-shift in qs8/qu8 vcvt to increase fixed-point scale precision from 8 bits to up to 15 bits.\n\nPiperOrigin-RevId: 1009545405\n" }, { "commit": "d1002e131182ffd5af2f42950a758de0d6d57d93", "tree": "ed06bd81ea1d7e8305648eae7b609e4d8e1609c3", "parents": [ "d2b705e2338daba360982ac555eaf3a1d97e7073" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 09:39:27 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:43:47 2026" }, "message": "Check the constant pad datatype before defining the node.\n\n`xnn_define_static_constant_pad_v2` converted the padding value after adding the\nnode and hit `XNN_UNREACHABLE` for datatypes it doesn\u0027t handle, such as int32.\nThe conversion now runs before the node is added, and other datatypes return\n`xnn_status_unsupported_parameter`.\n\nPiperOrigin-RevId: 1009538865\n" }, { "commit": "d2b705e2338daba360982ac555eaf3a1d97e7073", "tree": "7e3c44b9c1be7a0199d1036bb33919c9504ffd05", "parents": [ "f1e70ce3680fc74e402fd497f1c8b2527e806849" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 09:37:35 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:42:34 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_max_pooling_2d`.\n\nReturn `unsupported_parameter` when the input or output datatype has no\nkernel, since the call is well-formed but unimplemented.\n\nMalformed calls (bad parameters, mismatching datatypes or quantization)\nstill return invalid_parameter.\n\nPiperOrigin-RevId: 1009538121\n" }, { "commit": "f1e70ce3680fc74e402fd497f1c8b2527e806849", "tree": "a0243162cae0bd66c5a58c6cfcffc000ceb8ddbb", "parents": [ "a18e5fe0132f52d4c8bceccd64db503a0667d508" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 09:37:10 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:39:11 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_argmax_pooling_2d`.\n\nInstead of invalid_parameter when the input or output value datatype\nhas no kernel, since the call is well-formed but unimplemented.\n\nMalformed calls (zero pooling size, bad value IDs, non-dense values)\nstill return invalid_parameter.\n\nPiperOrigin-RevId: 1009537927\n" }, { "commit": "a18e5fe0132f52d4c8bceccd64db503a0667d508", "tree": "8e613508484a3727111cc8bb05a479a50b6a63f2", "parents": [ "12e669268a6998c4398dd06da69a47b00e1967b6" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 29 09:31:16 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 09:32:48 2026" }, "message": "Return `unsupported_parameter` for unsupported datatypes in `xnn_define_static_resize_bilinear_2d`.\n\nInstead of `invalid_parameter` when the input or output datatype has no\nkernel, since the call is well-formed but unimplemented.\n\nMalformed calls (zero output dimensions, unknown or conflicting flags,\nmismatching quantization) still return invalid_parameter.\n\nPiperOrigin-RevId: 1009535075\n" }, { "commit": "12e669268a6998c4398dd06da69a47b00e1967b6", "tree": "55a9f94f3475bfd81c12cb03b9f67abb9ad92ede", "parents": [ "4d9ce95f8a03b3c554d8c335670905365781a580" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Thu Oct 29 07:55:56 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 07:57:52 2026" }, "message": "Make all x86 and ARM tile_k \u003d 1 dot kernels unaligned_b.\n\nKernels with tile_k \u003d 1 don\u0027t require B to be packed across K, and can support unaligned B pointers and unaligned N dimensions. This enables using these kernels directly without packing passes or tensor realignment.\n\nThis required improving the `should_pack_b` heuristic to avoid regressions due to the new unaligned_b kernels. The previous threshold of 10 blocks of m was not correct for many of the new kernels. The new heuristic uses the cost models of the packed and unpacked kernels to decide how many blocks of m to permit, and adds an exception for cases that we think will have excessive wasted memory traffic.\n\nDetails:\n- Add `dot_flag::unaligned_b` and alignment settings to each tile_k \u003d 1 generator on x86 and ARM.\n- Ensure all tile_k \u003d 1 kernel generators use unaligned loads for B tiles.\n- Use AVX-512 masked loads for tail loading in AVX-512 generators (`x86_avx512_fp32`, `x86_avx512_fp64`, `x86_avx512_bf16_bf16_fp32_k1`, `x86_avx512_fp16_fp16_fp32`, `x86_avx512_int8_int8_int32_k1`).\n- Implement `load_b_tile_tail` using `std::memcpy` for generators lacking hardware masked loads (SSE2, NEON, AVX2 bf16/int8/fp16).\nPiperOrigin-RevId: 1009488148\n" }, { "commit": "4d9ce95f8a03b3c554d8c335670905365781a580", "tree": "5a6edab85788712519708154332661e7d391e9f4", "parents": [ "c36131109468292635343fad91ca23f85e61e846" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 29 06:43:06 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 06:44:19 2026" }, "message": "Use tail- and mask-undisturbed RVV intrinsics in reductions and vlrelu.\n\nIn RISC-V Vector (RVV) intrinsics, unsuffixed operations default to\ntail-agnostic and mask-agnostic, allowing hardware to overwrite\ninactive lanes with all-1s (`NaN` for floats, `-1` or `255` for ints):\n\n- `_tu` (tail-undisturbed) preserves destination elements past `vl`\n (`vl .. vlmax - 1`) instead of clobbering them on `vl \u003c vlmax` tails.\n- `_mu` (mask-undisturbed) preserves destination elements in masked-off\n lanes (`mask[i] \u003d\u003d 0`) instead of clobbering them.\n\nSwitch RVV `rsum`, `rsum2`, `rminmax`, and `raddstoreexpminusmax`\naccumulators to `_tu` so tail iterations preserve accumulated lanes for\nthe final `vlmax` reduction, and switch `f16-vlrelu` masked multiply to\n`_mu` to preserve non-negative lanes.\n\nPiperOrigin-RevId: 1009453061\n" }, { "commit": "c36131109468292635343fad91ca23f85e61e846", "tree": "47660680442e6fc21b440e4d5a27ab4ceefb7fcd", "parents": [ "8140a977c7cc5c52aa4d6e1f0fa4c0c15a724fd3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 29 02:45:32 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 29 02:46:56 2026" }, "message": "Skip unused tiles in AVX512-AMX INT8 GEMM and IGEMM microkernels.\n\nWhen computing 2-tile (`nr \u003d 32`) or 4-tile (`nr \u003d 64`) INT8 AMX GEMM\nand IGEMM microkernels with `nc \u003c nr`, guard tiles with `N \u003e 0` by\n`nc \u003e N` so unused tiles skip 4-bit weight unpacking, `_tile_loadd`,\n`_tile_dpbssd`, `_tile_stored`, and AVX-512 output post-processing.\nAlso remove the unused `7x32c4` and `7x64c4` `avx512amx` microkernels.\n\nIntel Granite Rapids single-core subgraph and microkernel (`M \u003d 16`,\n`K \u003d 1024`) latency:\n\n| Model / Benchmark | Before | After | Improvement |\n| :--- | ---: | ---: | ---: |\n| `QS8MobileNetV2` | 2,878 us | 2,595 us | -9.8% (1.11x) |\n| `QS8ResNet50` | 7,433 us | 7,433 us | 0.0% (1.00x) |\n| `QD8ResNet50` | 12,395 us | 12,395 us | 0.0% (1.00x) |\n| `qs8_qc8w_gemm_16x64c4__avx512amx` (N\u003d16) | 4,147 ns | 3,248 ns | -21.7% (1.28x) |\n| `qs8_qc8w_gemm_16x64c4__avx512amx` (N\u003d32) | 4,123 ns | 3,353 ns | -18.7% (1.23x) |\n| `qs8_qc8w_gemm_16x64c4__avx512amx` (N\u003d48) | 4,138 ns | 3,815 ns | -7.8% (1.08x) |\n| `qs8_qc8w_gemm_16x64c4__avx512amx` (N\u003d64) | 4,132 ns | 4,156 ns | +0.6% (0.99x) |\n| `qd8_f32_qc8w_gemm_16x64c4__avx512amx` (N\u003d16) | 2,794 ns | 2,017 ns | -27.8% (1.39x) |\n| `qd8_f32_qc8w_gemm_16x64c4__avx512amx` (N\u003d32) | 2,799 ns | 2,210 ns | -21.0% (1.27x) |\n| `qd8_f32_qc8w_gemm_16x64c4__avx512amx` (N\u003d48) | 2,811 ns | 2,571 ns | -8.5% (1.09x) |\n| `qd8_f32_qc8w_gemm_16x64c4__avx512amx` (N\u003d64) | 2,861 ns | 2,813 ns | -1.7% (1.02x) |\n| `qd8_f16_qc8w_gemm_16x64c4__avx512amx` (N\u003d16) | 2,801 ns | 1,959 ns | -30.1% (1.43x) |\n| `qd8_f16_qc8w_gemm_16x64c4__avx512amx` (N\u003d32) | 2,803 ns | 2,220 ns | -20.8% (1.26x) |\n| `qd8_f16_qc8w_gemm_16x64c4__avx512amx` (N\u003d48) | 2,844 ns | 2,555 ns | -10.2% (1.11x) |\n| `qd8_f16_qc8w_gemm_16x64c4__avx512amx` (N\u003d64) | 2,794 ns | 2,839 ns | +1.6% (0.98x) |\n| `qd8_f32_qc4w_gemm_16x64c4__avx512amx` (N\u003d16) | 2,251 ns | 1,273 ns | -43.4% (1.77x) |\n| `qd8_f32_qc4w_gemm_16x64c4__avx512amx` (N\u003d32) | 2,250 ns | 1,557 ns | -30.8% (1.45x) |\n| `qd8_f32_qc4w_gemm_16x64c4__avx512amx` (N\u003d48) | 2,263 ns | 1,882 ns | -16.8% (1.20x) |\n| `qd8_f32_qc4w_gemm_16x64c4__avx512amx` (N\u003d64) | 2,265 ns | 2,255 ns | -0.4% (1.00x) |\n\n```bash\nbazel build -c opt //bench/subgraph:mobilenet //bench/subgraph:resnet50 //bench:qs8_qc8w_gemm_fp32_bench //bench:qd8_f32_qc8w_gemm_bench //bench:qd8_f16_qc8w_gemm_bench //bench:qd8_f32_qc4w_gemm_bench\nbazel-bin/bench/subgraph/mobilenet --benchmark_filter\u003dQS8MobileNetV2 --benchmark_min_time\u003d2s\nbazel-bin/bench/subgraph/resnet50 --benchmark_filter\u003d\"QD8ResNet50|QS8ResNet50\" --benchmark_min_time\u003d2s\nbazel-bin/bench/qs8_qc8w_gemm_fp32_bench --benchmark_filter\u003d\"16x64c4__avx512amx/\" --benchmark_min_time\u003d1s 16 16 1024 16 32 1024 16 48 1024 16 64 1024\nbazel-bin/bench/qd8_f32_qc8w_gemm_bench --benchmark_filter\u003d\"16x64c4__avx512amx/\" --benchmark_min_time\u003d1s 16 16 1024 16 32 1024 16 48 1024 16 64 1024\nbazel-bin/bench/qd8_f16_qc8w_gemm_bench --benchmark_filter\u003d\"16x64c4__avx512amx/\" --benchmark_min_time\u003d1s 16 16 1024 16 32 1024 16 48 1024 16 64 1024\nbazel-bin/bench/qd8_f32_qc4w_gemm_bench --benchmark_filter\u003d\"16x64c4__avx512amx/\" --benchmark_min_time\u003d1s 16 16 1024 16 32 1024 16 48 1024 16 64 1024\n```\n\nPiperOrigin-RevId: 1009350287\n" }, { "commit": "8140a977c7cc5c52aa4d6e1f0fa4c0c15a724fd3", "tree": "ed5eef11321f218a62e3e7a316b40c9109a3d727", "parents": [ "d3025566b0bfc47477938c40ced7bb923e8097d7" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Wed Oct 28 21:38:45 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 21:39:46 2026" }, "message": "Check binary datatypes when the node is defined.\n\nCheck binary datatypes in `xnn_define_binary`:\n\n- an unknown operator returns `xnn_status_invalid_parameter`,\n- a datatype the operator doesn\u0027t implement (e.g. `bitwise_and` on fp32)\n returns `xnn_status_unsupported_parameter` instead of failing when the\n runtime is created.\n\nPiperOrigin-RevId: 1009185042\n" }, { "commit": "d3025566b0bfc47477938c40ced7bb923e8097d7", "tree": "f958a005fe84e9dcbe9de007de0ff292a516a0e4", "parents": [ "9b0b1bf972658b77f3b715629adea0e06a6ca5fd" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Wed Oct 28 20:48:33 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 20:52:11 2026" }, "message": "Return unsupported_parameter for unimplemented constant pad requests.\n\n`xnn_define_static_constant_pad_v2` now returns\n`xnn_status_unsupported_parameter` instead of `xnn_status_invalid_parameter` for\nmore than `XNN_MAX_TENSOR_DIMS` padded dimensions and for datatypes that aren\u0027t\nbyte-addressable.\n\nThe check is moved after the datatype-match check. That way we can only\ndo one check.\n\nPiperOrigin-RevId: 1009151166\n" }, { "commit": "9b0b1bf972658b77f3b715629adea0e06a6ca5fd", "tree": "0754d53d1de59b276a1e9beabe4ac98aafc2c2a4", "parents": [ "f967326487202547f3b699514273507561824bb7" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Wed Oct 28 20:46:49 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 20:48:26 2026" }, "message": "Fix AMX IGEMM row-stride crash by using direct _tile_loadd for mr \u003d\u003d 1\n\nIn AMX IGEMM microkernels (`c4-avx512amx.c.in` and\n`c2-avx512amxfp16.c.in`), the `mr \u003c\u003d 2` fast path loaded rows `a0` and\n`a1` with a single `_tile_loadd(4, a0, a_stride)` using a synthetic\npointer difference `a_stride \u003d (intptr_t) a1 - (intptr_t) a0`. Because\nIGEMM indirection pointers can reference unrelated buffers (such as\n`input` vs. `zero_buffer`), `a1 - a0` can be negative or exceed 2 GiB,\ncrashing on MSVC where `zmmintrin.h` declares `_tile_loadd`\u0027s `stride`\nas a 32-bit `int`. In `f16-igemm`, `mr \u003d\u003d 1` also read past the end of\nthe indirection buffer via `a[1] + a_offset` on the remainder path.\n\nRestrict the direct `_tile_loadd` fast path to `mr \u003d\u003d 1` with a\nconstant stride of 64 bytes and use the `vintile` staging buffer for\n`mr \u003e 1`, avoiding pointer subtraction across indirection rows and\nkeeping control flow independent of memory allocation addresses. Also\npass `/arch:AVX512` to MSVC for `AVX512VNNIGFNI`, `AVX512AMX`, and\n`AVX512AMXFP16` microkernel sources in `CMakeLists.txt`.\n\nPiperOrigin-RevId: 1009149806\n" }, { "commit": "f967326487202547f3b699514273507561824bb7", "tree": "ea056204cd4d57031ef8537fb3272ad24140f513", "parents": [ "1380e8494cd6acc81cf312593b641639321f7137" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Wed Oct 28 19:04:19 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 19:05:52 2026" }, "message": "Document when XNNPACK returns invalid_parameter vs unsupported_parameter.\n\n`xnn_status_invalid_parameter` means a malformed call and\n`xnn_status_unsupported_parameter` means a well-formed request that this\nbuild of XNNPACK doesn\u0027t implement.\n\nPiperOrigin-RevId: 1009080528\n" }, { "commit": "1380e8494cd6acc81cf312593b641639321f7137", "tree": "c2036e9da201d6c09777d336a8b7c71911c7daef", "parents": [ "9dd61a662f8f66b77fd419291094188038f2eb37" ], "author": { "name": "Samuel Fuller", "email": "samfuller@google.com", "time": "Wed Oct 28 17:41:08 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 17:43:19 2026" }, "message": "Fix SIGSEGV in pf32 SME/SME2 GEMM microkernel benchmarks.\n\nPiperOrigin-RevId: 1009020130\n" }, { "commit": "9dd61a662f8f66b77fd419291094188038f2eb37", "tree": "bd49ce587062df056301344855ad70740988f575", "parents": [ "e8039b8a061a7e61fb1ecc209e724c43102d1d86" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Wed Oct 28 17:22:47 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 17:27:02 2026" }, "message": "Lower ML Drift quantizations to real float to int conversions.\n\nThe ML Drift backend lowered `Quantize` to ML Drift\u0027s `QuantizeAndDequantize`,\nTFLite\u0027s FakeQuant, which outputs the quantized and dequantized floats instead\nof the integers of the 8-bit integer output tensor. It also didn\u0027t set the\nscale of the FakeQuant, which then divided by 0.\n\n`Quantize` now computes `clamp(round(x / scale) + zero_point, min, max)` in\nfp32 on the GPU and writes it to an int8 or uint8 tensor, in a single kernel,\nlike the other backends. Other output types and per-channel quantization return\nUnimplemented. `Dequantize` converts these integers back to floats since the\nprevious change.\n\nThis re-enables the shared `QuantizeOp` test on ML Drift, and the ML Drift\n`QuantizeOp` test as `QuantizeThenDequantizeOp`, since its test fixture can only\nread float outputs.\n\nPiperOrigin-RevId: 1009007391\n" }, { "commit": "e8039b8a061a7e61fb1ecc209e724c43102d1d86", "tree": "4964cae000627def15f93c4218e586e4ea17ebda", "parents": [ "bd35a701de79801228398caba798fa3120bf3eb0" ], "author": { "name": "Marie White", "email": "mariewhite@google.com", "time": "Wed Oct 28 17:22:44 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 17:24:12 2026" }, "message": "Improve performance on large square shapes.\n\nPiperOrigin-RevId: 1009007343\n" }, { "commit": "bd35a701de79801228398caba798fa3120bf3eb0", "tree": "9bb944aaead0d84b253472e8e054498f449c3b92", "parents": [ "4206de516cfb2fef7a76eb04b7c30b31da5194bf" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Wed Oct 28 14:58:03 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 15:00:05 2026" }, "message": "Lower ML Drift dequantizations of 8-bit integers to int to float conversions.\n\nThe ML Drift backend lowered `Dequantize` to ML Drift\u0027s\n`QuantizeAndDequantize`. This is TFLite\u0027s `FakeQuant`, which rounds\nfloat values to the quantization grid and keeps the type of its input.\n\nThis only gives the dequantized values when the input holds floats\n(which is the case for the output of the ML Drift lowering of\n`Quantize`) but this backend gives 8-bit integer tensors (graph inputs,\nquantized constants...) an integer ML Drift type, so the kernel didn\u0027t\ncompile for them. It also:\n\n- only used the first scale and zero point,\n- read the first zero point of an empty vector, which aborted,\n- dereferenced the missing quantization of fp16 inputs,\n- didn\u0027t map its output when its input was already an fp32 tensor.\n\n`Dequantize` now converts 8-bit integers to floats on the GPU:\n`(x - zero_point) * scale`:\n\n- as a single kernel for per-tensor quantization\n- as a cast followed by a subtraction and a multiplication by constant tensors\nbroadcast along the other dimensions for per-channel quantization.\n\nBoth compute in fp32 and convert the result to the output type to avoid\nfp16 models rounding the scales.\n\nTensor API handles with a float data type (fp16/fp32) are cast to the\nouptut type if needed. Handles with quantization information with a GPU\nfloat buffer (as `Quantize` would produce) are passed through.\n\nConstants, sub-byte and blockwise inputs return `Unimplemented`:\nconstants may have been uploaded in the packed layout of a fully\nconnected op.\n\nThis re-enables, on ML Drift, the shared `DequantizeOp` and\n`DequantizePerChannelOp` tests, the ML Drift `DequantizeOp` test, and\n`QuantizedWeightsSharedByDotAndAddOp` (now skipped).\n\nPiperOrigin-RevId: 1008910508\n" }, { "commit": "4206de516cfb2fef7a76eb04b7c30b31da5194bf", "tree": "910d5c483201adac97709d1d10976636d3c929a9", "parents": [ "80bfb76c29189e81a42a0345a0021f1a2ae9730d" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Wed Oct 28 07:15:21 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 07:17:06 2026" }, "message": "Only use tail loads when out of bounds in unaligned_b dot kernels.\n\nIn dot generators, separate full tile loads and tail tile loads for A\nand B tiles (load_a_tile / load_a_tile_tail and load_b_tile /\nload_b_tile_tail). When unaligned_b is enabled in tail mode, emit an\nin-bounds loop using unmasked loads that stops when reaching B_end,\nfollowed by masked tail loads for any remaining out-of-bounds iterations.\n\nThis makes the performance of the tail case much less important, because it only runs in the tail case of *both* the j and k loops, which is very rare. This allows us to prioritize simpler, smaller code for this corner case.\n\nPiperOrigin-RevId: 1008684484\n" }, { "commit": "80bfb76c29189e81a42a0345a0021f1a2ae9730d", "tree": "97017cbc5fcf875b6d969aa0817436afd72c8d0c", "parents": [ "f71e54d3b87029e4393731923708eff2c987d69b" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Wed Oct 28 01:08:16 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Wed Oct 28 01:10:17 2026" }, "message": "Fix premature overflow in SIMD exp and expm1\n\nYNNPACK\u0027s SIMD exponential implementations (exp_taylor1 and exp_taylor2)\nevaluate exp(x) and expm1(x) via range reduction x ≈ b ln(2) + r, followed\nby computing 2^b as exp2_round(b) and multiplying by the remainder\npolynomial e^r.\n\nNear the overflow boundary (e.g. [88.376266, 88.72284] for float32),\nb rounds up to 128. Even though r \u003c 0 ensures 2^128 · e^r is finite and\nrepresentable (up to FLT_MAX), evaluating 2^128 in single precision\noverflows to +inf, causing premature overflow across all 45,426 inputs in\nthat range.\n\nFix this by:\n1. Clamping b to max_b \u003d max_exponent - 1 (127 for float, 1023 for double)\n when evaluating exp2_round(min(b, max_b)).\n2. Doubling the result via select(b \u003e max_b, exp_x + exp_x, exp_x). For\n inputs at or above max_x, exp_x + exp_x naturally overflows IEEE-754\n addition to +inf, avoiding an extra explicit select.\n3. Updating max_x for double to 709.78271289338409 so inputs at or above\n max_x consistently overflow on addition.\n4. Fixing the ULP tolerance calculation in test_unary (generic.h) to multiply\n (epsilon * epsilons) first, preventing the test\u0027s own tolerance from\n overflowing when |k| \u003e FLT_MAX / 2.\n5. Tightening the test tolerance for exp from 2 to 1 ULP across SIMD test\n suites.\n\nPiperOrigin-RevId: 1008516683\n" }, { "commit": "f71e54d3b87029e4393731923708eff2c987d69b", "tree": "807a747d8819267fbe7d628b326e6c051c28664c", "parents": [ "2ebdb70f929ae0156e85d46bce25bae7b0aa3b42" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Tue Oct 27 18:33:52 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 18:35:17 2026" }, "message": "Don\u0027t lose a fused producer\u0027s parallelism to a consumer\u0027s single-iteration loop\n\nFix three cases where a producer fused into a consumer\u0027s single-iteration loop loses the parallelism of its own split of that loop:\n- Count the reduction dimensions in the work of a function proposing a split, so a dot with a small output but a large reduction can propose one.\n- Only skip the proposed split if a loop below it provably runs more than one iteration, rather than if a loop below might.\n- If a function\u0027s proposed split doesn\u0027t apply, fall back to an earlier proposal rather than displacing it.\n\nPiperOrigin-RevId: 1008256354\n" }, { "commit": "2ebdb70f929ae0156e85d46bce25bae7b0aa3b42", "tree": "b9618b70387f6cdc4ae293795c7025e0edb21344", "parents": [ "48e3be0109030701754fd845e93595c0dddde1d0" ], "author": { "name": "Anshul Nigham", "email": "nigham@google.com", "time": "Tue Oct 27 17:16:40 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 17:18:19 2026" }, "message": "Fix unused-variable warnings\n\nPiperOrigin-RevId: 1008195850\n" }, { "commit": "48e3be0109030701754fd845e93595c0dddde1d0", "tree": "09c9d87f161e47dfeabbd323a783d5269508e958", "parents": [ "0b1f641de5d64925170fe5bf3f4e0727980d3812" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 27 11:35:09 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 11:36:14 2026" }, "message": "Add AVX512-AMX-FP16 GEMM and IGEMM microkernels for Granite Rapids.\n\nAdapt the INT8 AMX GEMM and IGEMM templates into new c2-avx512amxfp16\ntemplates for FP16 inference on Intel Granite Rapids and later using c2\npacking (`_tile_dpfp16ps`) with FP32 internal accumulation and FP16\noutput conversion, and add the `avx512amxfp16` ISA target across Bazel,\nCMake, and GN.\n\nIntel Granite Rapids single-core FP16 subgraph latency:\n\n| Model | Before | After | Improvement |\n| :--- | ---: | ---: | ---: |\n| FP16MobileNetV1 | 3,888 us | 1,742 us | -55.2% (2.23x) |\n| FP16MobileNetV2 | 2,501 us | 1,915 us | -23.4% (1.31x) |\n| FP16MobileNetV3Large | 2,717 us | 2,346 us | -13.7% (1.16x) |\n| FP16MobileNetV3Small | 989 us | 967 us | -2.2% (1.02x) |\n| FP16ResNet50 | 27,623 us | 11,439 us | -58.6% (2.41x) |\n\n```bash\nbazel build -c opt //bench/subgraph:mobilenet //bench/subgraph:resnet50\nbazel-bin/bench/subgraph/mobilenet --benchmark_filter\u003dFP16MobileNet --benchmark_min_time\u003d2s\nbazel-bin/bench/subgraph/resnet50 --benchmark_filter\u003dFP16ResNet50 --benchmark_min_time\u003d2s\n```\n\nPiperOrigin-RevId: 1007999988\n" }, { "commit": "0b1f641de5d64925170fe5bf3f4e0727980d3812", "tree": "3b0de779cb9513a3c114c7bb68acf425d5738ddd", "parents": [ "a404f8ff98e241cfc0a436ce247e378b3d4c11a1" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Tue Oct 27 09:17:23 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 09:18:28 2026" }, "message": "Zero the column padding of packed B in the transpose packing path\n\nThe kernels compute on the padding, and garbage values (e.g. denormals) there can make the kernels much slower.\n\nPiperOrigin-RevId: 1007930408\n" }, { "commit": "a404f8ff98e241cfc0a436ce247e378b3d4c11a1", "tree": "6cb91cbea1b5050d01fa1920b31097a09925fac2", "parents": [ "818a95488bd98d495a0f17cd1462a1c2c8d9a9a4" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 27 07:03:48 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 07:05:23 2026" }, "message": "Use 5x64 avx512skx microkernel for f16_f32acc GEMM and IGEMM\n\nGenerate 1x64, 4x64, and 5x64 avx512skx_broadcast microkernels for\nf16_f32acc GEMM and IGEMM and update the AVX512SKX f16 GEMM dispatch\nconfiguration from 1x32/4x32 to 1x64/5x64.\n\nWith 4x32 (MR\u003d4, NR\u003d32, 2 ZMM vectors), each K iteration executes 6\nvcvtph2ps instructions for 8 vfmadd231ps instructions (1.33 FMAs per\nconvert), bottlenecking on vcvtph2ps throughput on AMD Zen 4/5 and\ncontending with the Port 5 512-bit FMA unit on Intel Skylake-X/Ice\nLake. Increasing the tile to 5x64 (MR\u003d5, NR\u003d64, 4 ZMM vectors) uses\n20 accumulator ZMM registers without spilling and executes 20\nvfmadd231ps per 9 vcvtph2ps (2.22 FMAs per convert), improving GEMM\nand IGEMM throughput by 30-49% across AMD Zen 4 and Intel Skylake-X:\n\n```bash\nbazel build -c opt //bench:f16_f32acc_gemm_bench\nbazel-bin/bench/f16_f32acc_gemm_bench 1024 1024 1024 \\\n --benchmark_filter\u003davx512skx --benchmark_min_time\u003d0.5s\n```\n\nPiperOrigin-RevId: 1007863282\n" }, { "commit": "818a95488bd98d495a0f17cd1462a1c2c8d9a9a4", "tree": "4834f9940b48a7de688419cc08a652a27a8dd6fb", "parents": [ "059a89b15c720471f04a8e615f2d69605d513880" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Tue Oct 27 06:28:34 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 06:29:38 2026" }, "message": "[YNNPACK] Fix Hexagon HVX dot bitfield overflow, NaN math, and tests\n\n- Widen the signed `block_n` and `tile_n` bitfields in `ynn::dot_kernel`\n from 8 to 16 bits and place them before `block_m`/`block_k` and\n `tile_m`/`tile_k` so all six shape fields still fit in 64 bits. HVX\n `1x128x1` kernels use `block_n \u003d 128`, which wrapped to -128, so the\n subgraph dot path produced no output for that kernel.\n- Guard `!isnan(b)` in `ynn::min` and `ynn::max` under\n `#ifdef YNN_ARCH_HEXAGON`. Without it Hexagon Clang lowers\n `a \u003c b ? a : b` to `sfmin`/`sfmax`, which return the non-NaN operand\n when `b` is NaN.\n- Treat Hexagon like ARM32 in the SIMD tests (HVX float flushes\n denormals), clamp the upper bound in `test_horizontal_min` with\n `std::min\u003cdouble\u003e(type_info\u003cscalar\u003e::max(), N)` so `N \u003d 128` does not\n overflow `int8_t`, and enable the HVX s8x128 horizontal min/max tests.\n- Only pass `hdrs` to the per-arch libraries in `ynn_cc_library` when\n that arch is enabled, so header parsing does not compile headers with\n another arch\u0027s flags (e.g. `-march\u003darmv8.2-a+sve+sme` on x86_64).\n- Fix Hexagon builds of `iota:test` (duplicate gtest dep) and\n `unary:consistent_arithmetic_test` (missing Hexagon linkopts/malloc).\n\nPiperOrigin-RevId: 1007845631\n" }, { "commit": "059a89b15c720471f04a8e615f2d69605d513880", "tree": "7a102aa7e379fbcf8bf3445a0e3d59051270a850", "parents": [ "51645a04b6b7cbe97ef7d863b8ce99cb65679d69" ], "author": { "name": "Richard Townsend", "email": "ritownsend@google.com", "time": "Tue Oct 27 01:14:12 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Tue Oct 27 01:15:15 2026" }, "message": "[gn] Separate prod and non-prod microkernels\n\n* Introduce a new argument (xnnpack_build_all_microkernels)\n* Add build/link testing for this config on x64 linux.\n\nWhen rebasing [1], started to get bot failures relating to the size and\nnumber of compilation artefacts. Whilst building the non-prod\nmicrokernels is (theoretically) harmless, it saves Chromium CI\nresources to skip what\u0027s not required.\n\n[1] https://chromium-review.googlesource.com/c/chromium/src/+/7615883/16\n\nPiperOrigin-RevId: 1007704830\n" }, { "commit": "51645a04b6b7cbe97ef7d863b8ce99cb65679d69", "tree": "58ab8fdee5803bb367ab1638473572662fbe43f8", "parents": [ "401d4501bd5f6e66edea74028fe0b52abcce72e4" ], "author": { "name": "Jeff Lee", "email": "jeffleetw@google.com", "time": "Mon Oct 26 21:07:55 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 21:09:08 2026" }, "message": "Adds new ARM SME2 ACLE based microkernels for QP8 F32 QC4W/QC8W GEMM and packing.\nThese new microkernels are guarded against selection with XNN_ENABLE_ARM_SME_ACLE flag, and are currently only used as an experimental opt-in status.\nTest files have been updated to include these new SME2 implementations.\nMicrokernels are now vector length agnostic and support multiple SVL sizes.\n\nPiperOrigin-RevId: 1007540430\n" }, { "commit": "401d4501bd5f6e66edea74028fe0b52abcce72e4", "tree": "2b3acd34cdac10eaef7562da5da67cd6e766f2e5", "parents": [ "24ab3883b4a44c73920b6faaa4357a4d77f9140b" ], "author": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 18:09:09 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 18:10:15 2026" }, "message": "Unpoison external output buffers in NnpackRunner under MSAN.\n\nPiperOrigin-RevId: 1007406846\n" }, { "commit": "24ab3883b4a44c73920b6faaa4357a4d77f9140b", "tree": "e617efaa414aac03b619e249986cd2febf783b6c", "parents": [ "9e22e5c05a7b08fcfa75654d3597344bf7bcd96b" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Mon Oct 26 17:55:44 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 17:57:07 2026" }, "message": "Optimize AMX GEMM and IGEMM quantization, 4-bit unpacking, and loads\n\nRefactor AMX GEMM and IGEMM microkernels (`c4-avx512amx.c.in`) to\nimprove vector/tile overlap and eliminate register spills:\n- Replace the unrolled 16-row post-processing block with an `m \u003c mr`\n row loop across 1-4 tiles (`NR \u003d 16, 32, 64`), avoiding ZMM register\n spilling, eliminating `c0..c15` pointer clamping, and skipping\n unused rows when `mr \u003c MR`.\n- Specialize `MR \u003d\u003d 1` with constant 1-row tile configuration, fixed\n 64-byte stride, and single-row quantization without loop overhead.\n- Double-buffer `weight_buffer[2][16 * 64]` in `qc4w` GEMM so AVX-512\n 4-bit nibble unpacking of tile `N+1` overlaps with AMX `_tile_loadd`\n and `_tile_dpbssd` of tile `N`.\n- In IGEMM, load `mr \u003c\u003d 2` directly via strided `_tile_loadd` (`a1 - a0`)\n and double-buffer `vintile[2][MR * 16]` when `mr \u003e 2` to avoid memory\n hazards between vector scatter stores and tile loads.\n\n```bash\nbazel build -c opt //bench/subgraph:mobilenet\nbazel-bin/bench/subgraph/mobilenet --benchmark_filter\u003dQS8MobileNetV2 --benchmark_min_time\u003d1s\n```\n\n`QS8MobileNetV2` latency:\n\n| CPU | Before | After | Improvement |\n| --------------------- | ------- | ------- | ----------- |\n| Intel Sapphire Rapids | 3315 us | 3078 us | +7.7% |\n| Intel Emerald Rapids | 2913 us | 2748 us | +6.0% |\n| Intel Granite Rapids | 3058 us | 2865 us | +6.7% |\n\nPiperOrigin-RevId: 1007397330\n" }, { "commit": "9e22e5c05a7b08fcfa75654d3597344bf7bcd96b", "tree": "1bf593c2d35b921b9f4c565732056539f3a6eb78", "parents": [ "c2aa2882b5bde6a9509d72d079a57804e7b4def5" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Mon Oct 26 16:54:43 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 16:56:14 2026" }, "message": "Allow concurrent constant folding across YNNPACK subgraphs.\n\nNarrow the constant cache mutex scope in `ynn_subgraph::fold_constants` to cover only cache lookups and insertions rather than the entire constant-folding evaluation, and deduplicate concurrent insertions in `insert_constant`. This allows multiple subgraphs to fold constants in parallel when initializing partitioned graphs on a thread pool.\n\nPiperOrigin-RevId: 1007353260\n" }, { "commit": "c2aa2882b5bde6a9509d72d079a57804e7b4def5", "tree": "7b16ebd57b6113d752ec9e28efdedc1723037f1b", "parents": [ "f2e3ba2b0363e7beb450cbe625d6f1b647485885" ], "author": { "name": "Misha Gutman", "email": "aelphy@google.com", "time": "Mon Oct 26 09:43:04 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Mon Oct 26 09:44:09 2026" }, "message": "Support std::optional\u003cT\u003e in ScopeGuard::Bind.\n\nComposite graph scopes with optional boundary tensors had to break method chaining on `ScopeGuard::Bind` to guard each `std::optional` with `has_value()`.\n\nAdd a `ScopeGuard::Bind` overload accepting `const std::optional\u003cT\u003e\u0026` that binds `*value` when present and is a no-op on `std::nullopt`, preserving fluent `Bind(...)` chains across optional boundary tensors.\n\nPiperOrigin-RevId: 1007129424\n" }, { "commit": "f2e3ba2b0363e7beb450cbe625d6f1b647485885", "tree": "f6a45f2630c6928ad29414951e1d37b4359bb649", "parents": [ "23dd5070fa002ef0b124817798ae090fa29f9653" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Sun Oct 25 07:03:52 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Sun Oct 25 07:05:38 2026" }, "message": "[HVX] Replace vsplat + vector ops with immediate and unary instructions\n\nVector splats (`Q6_V_vsplat_R`) followed by two-operand vector\ninstructions consume extra HVX registers and execution slots when\nscalar-register, immediate, predicate-and, or HVX v81 unary instructions\ncan perform the operation directly.\n\nReplace `Q6_V_vmux_QVV` with `Q6_V_vand_QV` in `f32-rsum`, use unary\n`Q6_Vsf_vabs_Vsf` and `Q6_Vsf_vfneg_Vsf` on HVX v81+, and simplify\n`xnn_round_f32` and YNNPACK `sign_complement` using scalar-register\npredicate operations. Also guard `arch_copts` with `ynn_if_arch` in\n`ynnpack/build_defs.bzl`.\n\nPiperOrigin-RevId: 1006605506\n" }, { "commit": "23dd5070fa002ef0b124817798ae090fa29f9653", "tree": "b9fa85916dc819258ad0d4c8568f7328dc43a796", "parents": [ "26186f85939753b9a509734b193aad2bcb17518f" ], "author": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 23 20:54:46 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 23 20:56:19 2026" }, "message": "Avoid static initializers for the constant folding cache.\n\nPiperOrigin-RevId: 1005843278\n" }, { "commit": "26186f85939753b9a509734b193aad2bcb17518f", "tree": "ed36effdddca554d18bb83354668e81b359d53fe", "parents": [ "fa0fa363587fcf4cae53d9f09f8234f58d275a1d" ], "author": { "name": "Misha Gutman", "email": "aelphy@google.com", "time": "Fri Oct 23 13:31:54 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Fri Oct 23 13:33:11 2026" }, "message": "Support std::optional\u003cT\u003e in CheckTensors.\n\nComposite graph builders with optional weight or cache tensors had to check each optional tensor separately after calling `CheckTensors` on the required inputs.\n\nAdd `GetTensorStatus` overloads for `TensorHandle` and `std::optional\u003cT\u003e` (treating `std::nullopt` as `absl::OkStatus()`) and update `CheckTensors` to accept `const Tensors\u0026...` and forward through `GetTensorStatus`, allowing callers to validate required and optional tensors in a single call.\n\nPiperOrigin-RevId: 1005552823\n" }, { "commit": "fa0fa363587fcf4cae53d9f09f8234f58d275a1d", "tree": "787db11816f986306514020cb940e6259edd40ce", "parents": [ "0e7357e2667e96b263f3bbac95223311372acc29" ], "author": { "name": "Misha Gutman", "email": "aelphy@google.com", "time": "Thu Oct 22 22:50:29 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 22:51:23 2026" }, "message": "Schedule non-aliasing `static_transpose` over outer batch dimensions (`d \u003e\u003d pin_end`) while omitting loop splits on the inner transposed dimensions (`0..pin_end-1`).\n\nPiperOrigin-RevId: 1005112982\n" }, { "commit": "0e7357e2667e96b263f3bbac95223311372acc29", "tree": "27517b9c76e20c197edc33b01203723c5bd206f3", "parents": [ "78d255d4d6455f0249cfdd229756ee90e476e317" ], "author": { "name": "Dillon Sharlet", "email": "dsharlet@google.com", "time": "Thu Oct 22 22:08:01 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 22:09:37 2026" }, "message": "Support strided and broadcast inputs in matrix packing\n\nThis is an alternative implementation of #11596 that avoids realizing the input broadcast into memory before packing. This includes the reproducer from that PR here. This should fix https://github.com/jax-ml/jax/issues/41414.\n\nThis refactors packer to accept input dimension strides (`stride_m`, `stride_n`)\ninstead of a transpose flag, and add support for packing broadcast\ninputs (stride 0 in either or both dimensions). It handles this similarly to an interleave, but with a replacement for the interleave kernels that performs a broadcast instead.\n\nThis also allows addressing a very old TODO to make transposing the LHS faster when using `transpose_a` dot kernels (e.g. SME). We can now fuse transposes with `transpose_a` the same way we can fuse transposes with `pack_b`\n\nPiperOrigin-RevId: 1005084447\n" }, { "commit": "78d255d4d6455f0249cfdd229756ee90e476e317", "tree": "9cf7193528d99d33e67e8eec7d37521cf82053e3", "parents": [ "115e015b4e7e6fe0dca8e2b1763b10dc4b5a337f" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 22 18:26:08 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 18:27:40 2026" }, "message": "Fix genxnn race where update-microkernels.py ran before codegen finished. Default genxnn is a full regeneration like the old -f; -f adds the gemm_compiler update (rarely changes); -n regenerates changed files only; -u skips update-microkernels.py.\n\nPiperOrigin-RevId: 1004922187\n" }, { "commit": "115e015b4e7e6fe0dca8e2b1763b10dc4b5a337f", "tree": "0d729b0080c494eb16b101fe1b428130848b970e", "parents": [ "533bf3f5afd2ad80016bfd05b81caa558dee729c" ], "author": { "name": "Quentin Khan", "email": "qkhan@google.com", "time": "Thu Oct 22 13:02:43 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 13:04:42 2026" }, "message": "Add a shared numerical test for per-channel dequantizations.\n\n`DequantizePerChannelOp` dequantizes an int8 graph input with per-channel\nquantization along either dimension, with and without zero points, and checks\nthe values. Backends that return Unimplemented skip the test.\n\nIt\u0027s disabled where it fails:\n\n- ML Drift: `Dequantize` lowers to a FakeQuant, and the test crashes with a\n segmentation fault for per-channel int8 inputs. The next change fixes it.\n- TFLite: the interpreter rejects quantization parameters without zero points.\n- XNNPACK: the backend dequantizes per-channel quantized tensors with zero\n points on the host as if they were constants, and fails for graph inputs.\n\nPiperOrigin-RevId: 1004712956\n" }, { "commit": "533bf3f5afd2ad80016bfd05b81caa558dee729c", "tree": "def89d0ef482c741913c4763ef91d899b2b2ddfa", "parents": [ "05576dc44c911777419dec6ad2f2a433690d5aab" ], "author": { "name": "Marie White", "email": "mariewhite@google.com", "time": "Thu Oct 22 12:21:58 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 12:23:35 2026" }, "message": "Enforce consistent arithmetic using fixed k-loop sizes. Reduction dimensions are now only dependent on input shape and data type, and not CPU-dependent parameters like kernel block sizes.\n\nRemoves need for a `consistent_block_n` and enables use of real cache sizes for calculating `m` and `n` sizes.\n\nScheduling logic is changed substantially to leverage real cache sizes and time-based costs:\n* `schedule_dot()` in schedule.cc. Now utilizes multiple levels of cache instead of just L2.\n* `define_pack_b()` in dot.cc. Uses both L1 and L2 to extend `block_n` but caps `block_n` to maintain concurrency.\n* `choose_split_factors()` in dot.cc. Uses 3 phases for deciding splits that incorporates cache sizes, time-based compute and bandwidth costs, load balancing.\n\nPiperOrigin-RevId: 1004693547\n" }, { "commit": "05576dc44c911777419dec6ad2f2a433690d5aab", "tree": "1a73b91e60285cf8d2c2ffde6ec75162f623e8c7", "parents": [ "ef044786d5d45d79fed3e0ca201b0c34290533e3" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 22 12:13:09 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 12:16:19 2026" }, "message": "Add Hexagon HVX `x32_packw_gemm_goi` microkernels (`xnn_x32_packw_gemm_goi_ukernel_x32__hvx_u32` and `xnn_x32_packw_gemm_goi_ukernel_x64__hvx_u32`) using a 5-stage 32x32 HVX `Q6_W_vshuff_VVR` butterfly transpose and wire them into `f32_gemm_config`, `f32_igemm_config`, and `f32_gemm_nr2_config`.\n\n```bash\nbazel build -c opt //bench/subgraph:attention //bench/subgraph:transformer\nbazel-bin/bench/subgraph/attention --benchmark_filter\u003d\"FP32Attention.*\" --benchmark_min_time\u003d0.1s\nbazel-bin/bench/subgraph/transformer --benchmark_filter\u003d\"FP32TransformerBlock.*F:6912.*\" --benchmark_min_time\u003d0.1s\n```\n\nPiperOrigin-RevId: 1004689759\n" }, { "commit": "ef044786d5d45d79fed3e0ca201b0c34290533e3", "tree": "2942bfc580749b290d6a0f4a98df2dca2d9a02d2", "parents": [ "43dd28e795e8caeb904b4d9eabbc1a5a6ccee5df" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 22 11:34:30 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 11:35:40 2026" }, "message": "Define XNN_ENABLE_RISCV_VECTOR in Bazel xnnpack_configurable_defines().\n\n```bash\nbazel build -c opt //bench:f32_gemm_minmax_bench\nbazel-bin/bench/f32_gemm_minmax_bench 128 128 128 --benchmark_filter\u003drvv --benchmark_min_time\u003d100x\n```\n\nPiperOrigin-RevId: 1004672965\n" }, { "commit": "43dd28e795e8caeb904b4d9eabbc1a5a6ccee5df", "tree": "5d5e2666d0472490635df54e8f35150750e2d5a2", "parents": [ "4ac56de4dabe0ca7b59beaf5ba66462f8b387610" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Oct 22 10:13:24 2026" }, "committer": { "name": "XNNPACK Team", "email": "xnnpack-github-robot@google.com", "time": "Thu Oct 22 10:14:43 2026" }, "message": "Add copyright year and clean working tree guidelines to AGENTS.md and CONTRIBUTING.md.\n\nPiperOrigin-RevId: 1004634653\n" } ], "next": "4ac56de4dabe0ca7b59beaf5ba66462f8b387610" }