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.\" ========================================================================
.IX Title "LLI 1"
.TH LLI 1 "2006-03-13" "CVS" "LLVM Command Guide"
lli \- directly execute programs from LLVM bytecode
\&\fBlli\fR [\fIoptions\fR] [\fIfilename\fR] [\fIprogram args\fR]
\&\fBlli\fR directly executes programs in \s-1LLVM\s0 bytecode format. It takes a program
in \s-1LLVM\s0 bytecode format and executes it using a just-in-time compiler, if one is
available for the current architecture, or an interpreter. \fBlli\fR takes all of
the same code generator options as llc, but they are only effective when
\&\fBlli\fR is using the just-in-time compiler.
If \fIfilename\fR is not specified, then \fBlli\fR reads the \s-1LLVM\s0 bytecode for the
program from standard input.
The optional \fIargs\fR specified on the command line are passed to the program as
.IX Header "OPTIONS"
.IP "\fB\-help\fR" 4
.IX Item "-help"
Print a summary of command line options.
.IP "\fB\-stats\fR" 4
.IX Item "-stats"
Print statistics from the code-generation passes. This is only meaningful for
the just-in-time compiler, at present.
.IP "\fB\-time\-passes\fR" 4
.IX Item "-time-passes"
Record the amount of time needed for each code-generation pass and print it to
standard error.
.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4
.IX Item "-mtriple=target triple"
Override the target triple specified in the input bytecode file with the
specified string. This may result in a crash if you pick an
architecture which is not compatible with the current system.
.IP "\fB\-march\fR=\fIarch\fR" 4
.IX Item "-march=arch"
Specify the architecture for which to generate assembly, overriding the target
encoded in the bytecode file. See the output of \fBllc \-\-help\fR for a list of
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4
.IX Item "-mcpu=cpuname"
Specify a specific chip in the current architecture to generate code for.
By default this is inferred from the target triple and autodetected to
the current architecture. For a list of available CPUs, use:
\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR
.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4
.IX Item "-mattr=a1,+a2,-a3,..."
Override or control specific attributes of the target, such as whether \s-1SIMD\s0
operations are enabled or not. The default set of attributes is set by the
current \s-1CPU\s0. For a list of available attributes, use:
\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR
.IP "\fB\-force\-interpreter\fR=\fI{false,true}\fR" 4
.IX Item "-force-interpreter={false,true}"
If set to true, use the interpreter even if a just-in-time compiler is available
for this architecture. Defaults to false.
.IP "\fB\-f\fR=\fIname\fR" 4
.IX Item "-f=name"
Call the function named \fIname\fR to start the program. Note: The
function is assumed to have the C signature \f(CW\*(C`int\*(C'\fR \fIname\fR \f(CW\*(C`(int,
char **, char **)\*(C'\fR. If you try to use this option to call a function of
incompatible type, undefined behavior may result. Defaults to \f(CW\*(C`main\*(C'\fR.
If \fBlli\fR fails to load the program, it will exit with an exit code of 1.
Otherwise, it will return the exit code of the program it executes.
.IX Header "SEE ALSO"
.IX Header "AUTHOR"
Maintained by the \s-1LLVM\s0 Team (<>).