AMDGPU: Remove wrapper around TRI::getRegClass
This shadows the member in the base class, but differs slightly
in behavior. The base method doesn't check for the invalid case.
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 6616b30..44ab771 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1309,10 +1309,11 @@
continue;
const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
- const TargetRegisterClass *MovSrcRC =
- TRI->getRegClass(TII->getOpRegClassID(MovDesc.operands()[SrcIdx]));
- if (MovSrcRC) {
+ int16_t RegClassID = TII->getOpRegClassID(MovDesc.operands()[SrcIdx]);
+ if (RegClassID != -1) {
+ const TargetRegisterClass *MovSrcRC = TRI->getRegClass(RegClassID);
+
if (UseSubReg)
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2ff2d2f..98b9a33 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6031,7 +6031,7 @@
return nullptr;
const MCOperandInfo &OpInfo = TID.operands()[OpNum];
int16_t RegClass = getOpRegClassID(OpInfo);
- return RI.getRegClass(RegClass);
+ return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}
const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
@@ -6049,7 +6049,8 @@
return RI.getPhysRegBaseClass(Reg);
}
- return RI.getRegClass(getOpRegClassID(Desc.operands()[OpNo]));
+ int16_t RegClass = getOpRegClassID(Desc.operands()[OpNo]);
+ return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
}
void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 737c815..8657a83 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3888,17 +3888,6 @@
: &AMDGPU::VReg_64RegClass;
}
-// FIXME: This should be deleted
-const TargetRegisterClass *
-SIRegisterInfo::getRegClass(unsigned RCID) const {
- switch ((int)RCID) {
- case -1:
- return nullptr;
- default:
- return AMDGPUGenRegisterInfo::getRegClass(RCID);
- }
-}
-
// Find reaching register definition
MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 7b91ba7..813f6bb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -391,8 +391,6 @@
MCRegister getExec() const;
- const TargetRegisterClass *getRegClass(unsigned RCID) const;
-
// Find reaching register definition
MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
MachineInstr &Use,
