tree 083ac186aef123824d47996e0eb75955c8f0e654
parent 9c7188a08a929832177505a3d2f9571f69ee5e40
author David Green <david.green@arm.com> 1557924118 +0000
committer David Green <david.green@arm.com> 1557924118 +0000

[ARM] Cortex-M4 schedule

This patch adds a simple Cortex-M4 schedule, renaming the existing M3
schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM:
https://developer.arm.com/docs/ddi0439/latest

Most of these are 1, with the important exception being loads taking 2
cycles. A few others are also higher, but I don't believe they make a
large difference. I've repurposed the M3 schedule as the latencies are
mostly the same between the two cores, with the M4 having more FP and
DSP instructions. We also turn on MISched and UseAA for the cores that
now use this.

It also adds some schedule Write's to various instruction to make things
simpler.

Differential Revision: https://reviews.llvm.org/D54142

llvm-svn: 360768