tree 8d0f4d58bebb34b8372fef3159b2dac989bcff95
parent af6c9df163831b3a977d5dbaa25f2974baf13518
author Craig Topper <craig.topper@intel.com> 1558759669 +0000
committer Craig Topper <craig.topper@intel.com> 1558759669 +0000

[X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms

This copies the Sandy Bridge zero idiom support to later CPUs. Adding the AVX2 and AVX512F/VL instructions as appropriate.

Differential Revision: https://reviews.llvm.org/D62360

llvm-svn: 361690