llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s

--- |
  define i32 @test_cmp_i8(i8 %a, i8 %b) {
    %r = icmp ult i8 %a, %b
    %res = zext i1 %r to i32
    ret i32 %res
  }

  define i32 @test_cmp_i16(i16 %a, i16 %b) {
    %r = icmp ult i16 %a, %b
    %res = zext i1 %r to i32
    ret i32 %res
  }

  define i32 @test_cmp_i32(i32 %a, i32 %b) {
    %r = icmp ult i32 %a, %b
    %res = zext i1 %r to i32
    ret i32 %res
  }

  define i32 @test_cmp_i64(i64 %a, i64 %b) {
    %r = icmp ult i64 %a, %b
    %res = zext i1 %r to i32
    ret i32 %res
  }

  define i32 @test_cmp_p0(i32* %a, i32* %b) {
    %r = icmp ult i32* %a, %b
    %res = zext i1 %r to i32
    ret i32 %res
  }

...
---
name:            test_cmp_i8
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi, $esi

    ; CHECK-LABEL: name: test_cmp_i8
    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
    ; CHECK: $eax = COPY [[ZEXT]](s32)
    ; CHECK: RET 0, implicit $eax
    %0(s8) = COPY $dil
    %1(s8) = COPY $sil
    %2(s1) = G_ICMP intpred(ult), %0(s8), %1
    %3(s32) = G_ZEXT %2(s1)
    $eax = COPY %3(s32)
    RET 0, implicit $eax

...
---
name:            test_cmp_i16
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi, $esi

    ; CHECK-LABEL: name: test_cmp_i16
    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
    ; CHECK: $eax = COPY [[ZEXT]](s32)
    ; CHECK: RET 0, implicit $eax
    %0(s16) = COPY $di
    %1(s16) = COPY $si
    %2(s1) = G_ICMP intpred(ult), %0(s16), %1
    %3(s32) = G_ZEXT %2(s1)
    $eax = COPY %3(s32)
    RET 0, implicit $eax

...
---
name:            test_cmp_i32
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi, $esi

    ; CHECK-LABEL: name: test_cmp_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
    ; CHECK: $eax = COPY [[ZEXT]](s32)
    ; CHECK: RET 0, implicit $eax
    %0(s32) = COPY $edi
    %1(s32) = COPY $esi
    %2(s1) = G_ICMP intpred(ult), %0(s32), %1
    %3(s32) = G_ZEXT %2(s1)
    $eax = COPY %3(s32)
    RET 0, implicit $eax

...
---
name:            test_cmp_i64
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi, $rsi

    ; CHECK-LABEL: name: test_cmp_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
    ; CHECK: $eax = COPY [[ZEXT]](s32)
    ; CHECK: RET 0, implicit $eax
    %0(s64) = COPY $rdi
    %1(s64) = COPY $rsi
    %2(s1) = G_ICMP intpred(ult), %0(s64), %1
    %3(s32) = G_ZEXT %2(s1)
    $eax = COPY %3(s32)
    RET 0, implicit $eax

...
---
name:            test_cmp_p0
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi, $rsi

    ; CHECK-LABEL: name: test_cmp_p0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $rsi
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
    ; CHECK: $eax = COPY [[ZEXT]](s32)
    ; CHECK: RET 0, implicit $eax
    %0(p0) = COPY $rdi
    %1(p0) = COPY $rsi
    %2(s1) = G_ICMP intpred(ult), %0(p0), %1
    %3(s32) = G_ZEXT %2(s1)
    $eax = COPY %3(s32)
    RET 0, implicit $eax

...