commit | 5c714cbdd83166e10b27b8e5ea2700654da2e90b | [log] [tgz] |
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author | Matt Arsenault <Matthew.Arsenault@amd.com> | Thu May 23 19:38:14 2019 |
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Thu May 23 19:38:14 2019 |
tree | 5f0da14a93817c94f6dcef9d2c2c2cbc9af41986 | |
parent | e4b27869c60cb1311c4396e057c21573e19e62cd [diff] |
AMDGPU: Correct maximum possible private allocation size We were assuming a much larger possible per-wave visible stack allocation than is possible: https://github.com/RadeonOpenCompute/ROCR-Runtime/blob/faa3ae51388517353afcdaf9c16621f879ef0a59/src/core/runtime/amd_gpu_agent.cpp#L70 Based on this, we can assume the high 15 bits of a frame index or sret are 0. The frame index value is the per-lane offset, so the maximum frame index value is MAX_WAVE_SCRATCH / wavesize. Remove the corresponding subtarget feature and option that made this configurable. llvm-svn: 361541