[AArch64][SVE2] Asm: add various bitwise shift instructions

Summary:
This patch adds support for the SVE2 saturating/rounding bitwise shift
left (predicated) group of instructions:

    * SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL,
      SQSHLR, UQSHLR, SQRSHLR, UQRSHLR

Immediate forms of the SQSHL and UQSHL instructions are also added to
the existing SVE bitwise shift by immediate (predicated) group, as well
as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in
this group are encoded similarly and are implemented using the same
TableGen class with a minimal change (1 bit in encoding).

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62140

llvm-svn: 361612
32 files changed
tree: 36d1b64133dfb26288fa26e8e442c5379352be6c
  1. .arcconfig
  2. .clang-format
  3. .clang-tidy
  4. .gitignore
  5. README.md
  6. clang-tools-extra/
  7. clang/
  8. compiler-rt/
  9. debuginfo-tests/
  10. libclc/
  11. libcxx/
  12. libcxxabi/
  13. libunwind/
  14. lld/
  15. lldb/
  16. llgo/
  17. llvm/
  18. openmp/
  19. parallel-libs/
  20. polly/
  21. pstl/
README.md

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