[ARM] Cortex-M4 schedule

This patch adds a simple Cortex-M4 schedule, renaming the existing M3
schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM:

Most of these are 1, with the important exception being loads taking 2
cycles. A few others are also higher, but I don't believe they make a
large difference. I've repurposed the M3 schedule as the latencies are
mostly the same between the two cores, with the M4 having more FP and
DSP instructions. We also turn on MISched and UseAA for the cores that
now use this.

It also adds some schedule Write's to various instruction to make things

Differential Revision: https://reviews.llvm.org/D54142

llvm-svn: 360768
12 files changed
tree: 083ac186aef123824d47996e0eb75955c8f0e654
  1. .arcconfig
  2. .clang-format
  3. .clang-tidy
  4. .gitignore
  5. README.md
  6. clang-tools-extra/
  7. clang/
  8. compiler-rt/
  9. debuginfo-tests/
  10. libclc/
  11. libcxx/
  12. libcxxabi/
  13. libunwind/
  14. lld/
  15. lldb/
  16. llgo/
  17. llvm/
  18. openmp/
  19. parallel-libs/
  20. polly/
  21. pstl/

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