commit | dc2fd6a14e710bbe7af867425f36a1e4b6c72d8f | [log] [tgz] |
---|---|---|

author | Huihui Zhang <huihuiz@quicinc.com> | Sat Jun 15 00:33:41 2019 |

committer | Huihui Zhang <huihuiz@quicinc.com> | Sat Jun 15 00:33:41 2019 |

tree | 0e51c4b1e339273ce5e516cf02c5346085259fa1 | |

parent | 9487278010c8aa856ad9a1eb7e5808666f65274a [diff] |

[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc). Summary: For icmp pred (and (sh X, Y), C), 0 When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0, rather than (X & (signbit >> Y)) != 0. When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1, rather than (X & (~C >> Y)) == 0. For icmp pred (and X, (sh signbit, Y)), 0 Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0 Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0 Reviewers: lebedev.ri, efriedma, spatel, craig.topper Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63025 llvm-svn: 363479

- llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll[Added - diff]
- llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll[Added - diff]
- llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll[Added - diff]
- llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll[Added - diff]
- llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll[Added - diff]
- llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll[Added - diff]

6 files changed

tree: 0e51c4b1e339273ce5e516cf02c5346085259fa1