)]}' { "log": [ { "commit": "b443896c13aded8b40d7bae4a5a9adbc96fd0d31", "tree": "60940151fb3abbab3f85a20d54bfa93b14d3cddd", "parents": [ "74aae4e43edbf1843b886516893fd2b880d70dfa" ], "author": { "name": "Ramkumar Ramachandra", "email": "artagnon@tenstorrent.com", "time": "Tue Jul 28 10:18:20 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 10:18:20 2026" }, "message": "[VPlan] Use pointee-range in blocksOnly (NFC) (#212441)\n\nThe map_range can be replaced by make_pointee_range." }, { "commit": "74aae4e43edbf1843b886516893fd2b880d70dfa", "tree": "cf41e85176196a91ef1ff7dfb7002fad3ceb69e6", "parents": [ "b626ec036e8551c4aa7d548e718bc5aa91562be0" ], "author": { "name": "Ramkumar Ramachandra", "email": "artagnon@tenstorrent.com", "time": "Tue Jul 28 09:53:26 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:53:26 2026" }, "message": "[VPlan] Eta-reduce fn in pullOutPermutations (NFC) (#212439)\n\nfun x \u003d\u003e f x can be eta-reduced to just f." }, { "commit": "b626ec036e8551c4aa7d548e718bc5aa91562be0", "tree": "1fd6ccf974986b854b59e56c46b01185ed7981b8", "parents": [ "7e1719546578ed523f5deb4ac499cdc833280d9c" ], "author": { "name": "Peng Sun", "email": "peng.sun@arm.com", "time": "Tue Jul 28 09:42:36 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:42:36 2026" }, "message": "[mlir][tosa] Add FP8 and MXFP support to RESIZE (#212276)\n\n- Added FP8 and all six MXFP extension/type combinations\n- Updated RESIZE availability and enforced NEAREST_NEIGHBOR for MXFP\n- Added positive, negative, version, extension, mixed-type, and verifier\ntests.\n\nSigned-off-by: Peng Sun \u003cpeng.sun@arm.com\u003e" }, { "commit": "7e1719546578ed523f5deb4ac499cdc833280d9c", "tree": "105bf880ab66302021d86af59075a301a1995598", "parents": [ "a1194be1baefa99d20a09bd04b16056be0ab7225" ], "author": { "name": "Wenju He", "email": "wenju.he@intel.com", "time": "Tue Jul 28 09:27:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:27:53 2026" }, "message": "[LoopUnroll] Allow vector types for minmax reductions (#207630)\n\nOur downstream patched RecurrenceDescriptor in IVDescriptors.cpp to\nrecognize min/max reductions on vector-typed phis. After ffa02793,\nvector min/max intrinsic reductions now flow into getReductionIdentity()\nwith vector type and then runtime-unroll-reductions-min-max.ll test\ncrashed.\nThis PR upstreams our RecurrenceDescriptor change to avoid further\ndownstream change to LoopUtils.cpp (in this PR) that fixes the crash.\n\nLIT change in runtime-unroll-reductions-min-max.ll shows a long serial\nreduction chain now breaks into two independent ones, which is the\npurpose of unroll-add-parallel-reductions.\n\n---------\n\nCo-authored-by: skozhukh \u003csergey.s.kozhukhov@intel.com\u003e" }, { "commit": "a1194be1baefa99d20a09bd04b16056be0ab7225", "tree": "d46ac3c14c361582fa2f7e904b494b2b2d676a01", "parents": [ "636d8a253e71651ffa75f3bb515a14de0f20341d" ], "author": { "name": "Arseniy Obolenskiy", "email": "arseniy.obolenskiy@amd.com", "time": "Tue Jul 28 09:05:59 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:05:59 2026" }, "message": "[SPIR-V] Fix hex float exponent for f64 Inf/NaN literals (#212295)\n\nThe asm printer hardcoded the f32 exponent (+128) when printing Inf/NaN\nas hex floats, so f64 Inf/NaN literals were misencoded and silently\nreassembled as finite values by consumers\n\nDerive the exponent from the operand actual semantic instead" }, { "commit": "636d8a253e71651ffa75f3bb515a14de0f20341d", "tree": "6fead69afdd928474e51d501b2da40c31895d5e0", "parents": [ "2d7aaf670d704bbb4bfb3ef023f18ba0b85b58c7" ], "author": { "name": "David Spickett", "email": "david.spickett@arm.com", "time": "Tue Jul 28 09:05:43 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:05:43 2026" }, "message": "[lldb][AArch64][Linux] Track all register cache validity in one place (#197113)\n\nIn this change I\u0027ve expanded the existing RegisterSetType enum\nto be used as part of a singular cache tracking object which replaces\nall the separate booleans. These booleans were hard to track and \nset/reset in the right places.\n\nThis new validity object can be reset by default constructing,\nand uses a member initialiser so everything starts out as invalid.\n\nRegisterSetType is now a bitmask enum for easier storage.\nIt\u0027s 32-bit now which is enough for now. Just in case we expand it. \n(and I previously updated all sizeof calls to use RegisterSetType\ninstead of the raw type)\n\nThe SME and SME 2 entries have been renamed to ZA and ZT\nas this is what ptrace calls them. Note that SME\u0027s pseudo registers\nare still managed in their own unique way, I hope to address that\nlater.\n\nOver time, RegisterSetType will become the key for all the \noperations in the register context. You can see a preview of\nthat \"vision\" in #193174.\n\nFor instance getting the buffer location and size, looking up\nthe ptrace set number, finding out what a set write invalidates,\nand so on.\n\nI did consider using optional for the register storage. I think this\ncould work if we had done it from the beginning but starting from\nthis point it has too many issues with it.\n\n* We cannot assume that sizeof(buffer) \u003d\u003d sizeof(buffer_type). Which\nleads to some places where you have to write sizeof(some_generic_type).\nWhich is not ideal. Being able to use the member variable name is\nclearer.\n* We have to make the buffer \"valid\" before trying to read, then make it\ninvalid if it fails. Rather than read and if it succeeds mark it valid.\n3 steps vs. 2.\n* Some things like SVE resize the buffer when we get the new vector\nlength, then at some point later assume the buffer can hold the result\nof a read. We\u0027d have to track the expected size separately, and use that\nto resize it just before read. Which is not difficult, but it\u0027s a\ndifferent strategy and I don\u0027t want to disturb all the SVE/SME handling\nat this stage.\n* Though our buffer + bool is in theory an optional, the way the class\nis designed where one thing fills the buffer and another reads from it\nlater, the flexibility of when to set the bool does help us. Versus the\nautomatic handling optional does.\n\nOnce this whole class has been simplified and I can see the \"unusual\"\ncode paths more easily, I might revisit the optional idea." }, { "commit": "2d7aaf670d704bbb4bfb3ef023f18ba0b85b58c7", "tree": "fbcc0adadd663a04adfc52fc73d9980f74580152", "parents": [ "6520ac73f22d53e93e5ae8da6351a1714723497c" ], "author": { "name": "Pavel Labath", "email": "pavel@labath.sk", "time": "Tue Jul 28 09:04:03 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:04:03 2026" }, "message": "[libc] Fix path collisions between unit and hermetic tests (#212425)\n\nUse the APPEND_LIBC_TEST macro to ensure each test gets a unique path to\noperate on. Enable the affected tests in hermetic mode." }, { "commit": "6520ac73f22d53e93e5ae8da6351a1714723497c", "tree": "09ce46621151ba59986c52a007c8c19c1ab962ae", "parents": [ "b349bef025f294ef100d02ac8c928836cd979f3f" ], "author": { "name": "David Spickett", "email": "david.spickett@arm.com", "time": "Tue Jul 28 09:03:07 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:03:07 2026" }, "message": "[lldb][test][AArch64] Add test for AArch32 compatibility execution (#211793)\n\nThis should catch obvious problems like the one in #211692 in\nfuture.\n\nTo run AArch32 programs on AArch64 you need a few things:\n* Hardware that has AArch32 mode at EL0.\n* A kernel built with CONFIG_COMPAT on.\n* (usually) A bunch of 32-bit libraries installed.\n\nWe are dodging the 3rd one by compiling a standalone assembly\nprogram that doesn\u0027t use any other libraries.\n\nWith clang being a cross-compiler and lld a cross-linker,\nwe should be able to do this without any 32-bit compatibility\nlibraries being installed.\n\nTo check for the first 2, we run that program normally.\nIf it fails to run, we don\u0027t have them. If it does run,\nwe have to double check that it\u0027s not being emulated. If\nit is not being emulated, finally we can run it with lldb to\ncheck that lldb works correctly.\n\nInside of lldb we place a breakpoint and read some\nregisters. GPRs are set to their own register number,\nand FPR to their register number plus 1. So if we mixed\nup the set order, we would know about it.\n\nTested on a Graviton 3 which allowed AArch32 execution and a Graviton 5\nwhich did not. For the latter, the error without an emulator is:\n```\n$ ~/test.o\n-bash: /home/davspi01/test.o: cannot execute binary file: Exec format error\n```\nThis we detect when `Popen` fails. If you install qemu and setup\nbinfmt_misc, we detect that via. the exe path:\n```\n$ ~/test.o \u0026\n[2] 433187\n$ ls -la /proc/433187/exe\nlrwxrwxrwx 1 davspi01 davspi01 0 Jul 27 11:47 /proc/433187/exe -\u003e /usr/bin/qemu-arm\n```" }, { "commit": "b349bef025f294ef100d02ac8c928836cd979f3f", "tree": "19162ad77a1e98530df2e26044197d77b9aef5f5", "parents": [ "437b42f23250660f9a3f262ca6626324cd32a094" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Jul 28 09:02:44 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:02:44 2026" }, "message": "[AArch64][GlobalISel] Use integer type for cttz icmp type. (#212327)" }, { "commit": "437b42f23250660f9a3f262ca6626324cd32a094", "tree": "fa34193bcd8aebe08f3e38ff1a96c1dc1b14201b", "parents": [ "10d1b41f8cd9aa327fb15f698a0b564a3d5c4118" ], "author": { "name": "Kevin Bravo", "email": "kbravjr@gmail.com", "time": "Tue Jul 28 09:01:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 09:01:53 2026" }, "message": "[TableGen] don\u0027t print redundant diagnostic when parser sees Error token at end of file. (#212410)\n\nFixes #151476. \n\nCurrently TableGen parser emits `error: Unexpected token at top level`\nwhen it sees `tgtok::Error` token after failing to parse the object\nlist, even though that token\u0027s corresponding diagnostics were already\nemitted during lexing. This change makes `ParseFile` return true when it\nsees `tgtok::Error` at end of file, thereby avoiding the redundant\ndiagnostic." }, { "commit": "10d1b41f8cd9aa327fb15f698a0b564a3d5c4118", "tree": "22e2b2fcebda2e63a98212ca6d53babdf2e789ac", "parents": [ "564be89eaee5227ec21980ca2054f00d595044c7" ], "author": { "name": "Lang Hames", "email": "lhames@gmail.com", "time": "Tue Jul 28 08:56:25 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:56:25 2026" }, "message": "[ORC] Fix buildSimpleReexportsAliasMap signature. (#212420)\n\nThe header declared a `const SymbolNameSet\u0026` argument, but the\nimplementation took a `SymbolNameSet` by value. Update the\nimplementation to also take a `const SymbolNameSet\u0026`.\n\nNo testcase. The corrected implementation will be used in an upcoming\ncommit." }, { "commit": "564be89eaee5227ec21980ca2054f00d595044c7", "tree": "fd6d1176382be4a219df3f8572d77287b1a3e5aa", "parents": [ "c6603cce864078da43741e36fb9586a6c72782fe" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Tue Jul 28 08:53:42 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:53:42 2026" }, "message": "clang: Fix subarchless amdgpu triples in offload bundler tests (#212424)" }, { "commit": "c6603cce864078da43741e36fb9586a6c72782fe", "tree": "06f2acaf30c4ceb4026836fea5c7fac983b74f16", "parents": [ "6aeeec83ec1d979ea2a2e3f4629ac361b5cdb70e" ], "author": { "name": "Matthias Wippich", "email": "mfwippich@gmail.com", "time": "Tue Jul 28 08:52:44 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:52:44 2026" }, "message": "[clang][NFC] generate TokenKey from tablegen (#210857)\n\nCurrently the enumerator constants of `TokenKey` are duplicated between\nTokenKinds.h and Traits.td. This patch generates the `TokenKey` enum\nfrom tablegen.\n\nThis is a followup patch for\nhttps://github.com/llvm/llvm-project/pull/201491#discussion_r3567423553" }, { "commit": "6aeeec83ec1d979ea2a2e3f4629ac361b5cdb70e", "tree": "0b6123ec6d23ad6e3c74cfeb14e20577a1282ba9", "parents": [ "697f9892bef88f22f630e7e78541dd29d3cd716b" ], "author": { "name": "David Spickett", "email": "david.spickett@arm.com", "time": "Tue Jul 28 08:40:50 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:40:50 2026" }, "message": "[lldb][test] Skip TestGuiSpawnThreads.py on Linux (#212431)\n\nSee https://github.com/llvm/llvm-project/issues/209874.\n\nWe are still hitting the larger timeout." }, { "commit": "697f9892bef88f22f630e7e78541dd29d3cd716b", "tree": "bf52691dfb4d38a62c3e2cfa9a4bbdcc45343ffb", "parents": [ "8e9802b45829d473bce51197ce95f3ab40d94426" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Jul 28 08:29:32 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:29:32 2026" }, "message": "[AArch64][GlobalISel] Update regbank tests with concrete types. NFC (#212367)" }, { "commit": "8e9802b45829d473bce51197ce95f3ab40d94426", "tree": "193ccdc70eb8269acb2407bea4b1f4a9298fdd47", "parents": [ "162cdf496003e9bed7e7c7d0cbbd507365443b85" ], "author": { "name": "David Spickett", "email": "david.spickett@arm.com", "time": "Tue Jul 28 08:24:14 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:24:14 2026" }, "message": "[lldb][test] Do not return a PID in TestGdbClientModuleLoad (#212256)\n\nThis test has been flaky on x86 Github CI. It expects: \n[ 0] {{.*}} 0x0000000000ee0000 {{.*}}module_load\n[ 1] {{.*}} 0x0000000000ef0000 {{.*}}[vdso]\n\nHowever in one run it got:\n[ 0] 98FC07B8 0x0000000000ef0000 [vdso] (0xef0000)\n[ 1] 75B11BBB-EF8B-5645-B9B1-A7261EC8ABCF-05413284 0x0000000000ed8ed0\n/home/gha/actions-runner/bin/Runner.Worker\n\nThis happened because the responder says it\u0027s debugging PID 0x47, which\nis usually some root process that we cannot read the /proc/pid/exe link\nfor. However when it is readable, we will assume that is the program\nfile and it replaces the \"module_load\" entry (this never happened on\nAArch64 because an AArch64 program file is never compatible with an x86\ntriple).\n\nIn the failing case, 0x47 happened to be a github runner process that\nlldb could get the exe for. I was able to reproduce this by putting a\nlong sleep in the background and replacing 0x47 with that sleep\u0027s PID.\n\nTo fix this I am returning the value of `PID_MAX_LIMIT` which is the\nlimit of what `pid_max` can be set to. This should be parsed by lldb\ninto an invalid PID and cause it to give up looking at the host.\n\nI tried returning 0, this found a process somehow, returning no PID at\nall, again it found a process. The only other way is to make this test\nconnect to a fake remote linux platform first, but this would take much\nmore code to set up." }, { "commit": "162cdf496003e9bed7e7c7d0cbbd507365443b85", "tree": "ebe2f91efa253d5b9f9aaa5f47ed2826f84c6a8e", "parents": [ "7c58d4de4af550ba3d54bf217f27a1e6b3736dbc" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Tue Jul 28 08:20:57 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:20:57 2026" }, "message": "[SCEV] Rewrite more SCEVAddExpr when applying guards. (#159942)\n\nWhen re-writing SCEVAddExprs to apply information from guards, check if\nwe have information for the expression itself. If so, apply it.\n\nWhen we have an expression of the form (Const + A), check if we have\nhave guard info for (Const + 1 + A) and use it. This is needed to avoid\nregressions in a few cases, where we have BTCs with a subtracted\nconstant.\n\nRewriting expressions could cause regressions, e.g. when comparing 2\nSCEV expressions where we are only able to rewrite one side, but I could\nnot find any cases where this happens more with this patch in practice.\n\nDepends on https://github.com/llvm/llvm-project/pull/160012.\n\nProofs for some of the test changes: https://alive2.llvm.org/ce/z/RPX6t_\n\n\nThis comes with a slight compile-time increase, mostly due to changes in\ndownstream optimizations (like extra unrolling).\n\n stage1-O3: +0.03%\n stage1-ReleaseThinLTO: +0.02%\n stage1-ReleaseLTO-g: +0.04%\n stage1-aarch64-O3: +0.04%\n stage2-O3: +0.03%\n\nhttps://llvm-compile-time-tracker.com/compare.php?from\u003d42b4ee6383e340c4c3ab4cfddd17f864ab331e0d\u0026to\u003d7b5221e21c2c18152dcb72a82122730690153aed\u0026stat\u003dinstructions%3Au\n\nImproves optimizations end-to-end in a number of cases on real-world workloads\n(dtcxzyw/llvm-opt-benchmark-nightly#802).\n\nPR: https://github.com/llvm/llvm-project/pull/159942" }, { "commit": "7c58d4de4af550ba3d54bf217f27a1e6b3736dbc", "tree": "5237b93d802f0a7ba8d93a6c4041a9d8dabb3250", "parents": [ "0bcff14b1740cf32f9e0983726238dcf353c6ac8" ], "author": { "name": "Igor Kudrin", "email": "ikudrin@accesssoftek.com", "time": "Tue Jul 28 08:16:59 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 08:16:59 2026" }, "message": "[lldb][AArch64] Fix launching Arm32 applications on AArch64 Linux (#211692)\n\nWhen LLDB runs on an AArch64 Linux, it adds both 64- and 32-bit\narchitectures as supported; see `PlatformLinux` ctor. The triple for the\n32-bit variant is computed by replacing the architecture while keeping\nall other fields; i.e., for the main host triple\n`aarch64-unknown-linux-gnu`, the generated 32-bit triple is\n`arm-unknown-linux-gnu`.\n\nWhen a 32-bit target is created, its triple would be something like\n`arm--linux-eabihf`. This triple is incompatible with the one added to\nthe supported architectures per condition in `ArchSpec::IsMatch()`,\nwhich checks for compatibility between environments. As a result, LLDB\nfails to launch this target:\n\n```\n\u003e arm-linux-gnueabihf-g++ -g test.cpp -o test.out\n\u003e lldb\n(lldb) file test.out\nCurrent executable set to \u0027/tmp/test.out\u0027 (arm).\n(lldb) run\nerror: failed to launch or debug process\n```\n\nClearing the environment of the computed triple for Arm32 allows the\ncompatibility check to pass.\n\n---------\n\nCo-authored-by: David Spickett \u003cdavid.spickett@arm.com\u003e" }, { "commit": "0bcff14b1740cf32f9e0983726238dcf353c6ac8", "tree": "e99029acc3e6ee166fa597cb801691107862d730", "parents": [ "39549cd7c62e9a2db44d186e0fe5d99e1473cb24" ], "author": { "name": "Pavel Labath", "email": "pavel@labath.sk", "time": "Tue Jul 28 07:58:31 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:58:31 2026" }, "message": "[libc] Make \u003csys/mman.h\u003e tests hermetic (#210697)\n\nThe only issue was in pkey_test, which uses function-local static to do\nlazy initialization. This requires the c++ runtime\n(__cxa_guard_acquire/release).\n\nThere are no threads in this test, so we can just use the\n(non-thread-safe) hand-rolled version of that. This is currently our\nonly test with such a pattern.\n\nThis would be something that in gtest would go into a SetUpTestSuite\nmethod, but our test framework currently doesn\u0027t have an equivalent." }, { "commit": "39549cd7c62e9a2db44d186e0fe5d99e1473cb24", "tree": "2c04007c3fd5c8f1dcd3be3b57bacd8e5ae6ca15", "parents": [ "b53f2d57b086d93dc8421c74c17913951122e9d9" ], "author": { "name": "StefanPaulet", "email": "tudor.stefan.paulet@gmail.com", "time": "Tue Jul 28 07:44:52 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:44:52 2026" }, "message": "[clang] Fixed predefined expressions after lambda parameters (#211811)\n\nAfter the parameter declaration of a lambda expression, `Sema` enters\nthe declaration context of the lambda call operator (in\n`ActOnLambdaClosureParameters`), so the lambda specifiers and the\ntrailing return type are analyzed within that context. Because of this,\npredefined expressions such as `__func__` resolve to the lambda call\noperator, and not to the possibly enclosing function. (issue #122657)\n\nAdded a member to `LambdaScopeInfo` to mark whether or not the compound\nstatement of the lambda expression has been entered, to be used when\nresolving a `PredefinedExpr`" }, { "commit": "b53f2d57b086d93dc8421c74c17913951122e9d9", "tree": "6f2c7c2a72e5b189262ee1ea2e2dcc0b734f6df1", "parents": [ "f5437c4d4f2e9920614d856158d9683d650acffa" ], "author": { "name": "forking-google-bazel-bot[bot]", "email": "265904573+forking-google-bazel-bot[bot]@users.noreply.github.com", "time": "Tue Jul 28 07:39:44 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:39:44 2026" }, "message": "[Bazel] Fixes 1e1274b (#212405)\n\nThis fixes 1e1274b2ddfe4643eefdd1c6c83d6c2d61dace1d (#212318).\n\nBuildkite error link:\nhttps://buildkite.com/llvm-project/upstream-bazel/builds?commit\u003d1e1274b2ddfe4643eefdd1c6c83d6c2d61dace1d\n\nCo-authored-by: Google Bazel Bot \u003cgoogle-bazel-bot@google.com\u003e" }, { "commit": "f5437c4d4f2e9920614d856158d9683d650acffa", "tree": "c6f46a83115ebe8761c18167e640d519ddb241b5", "parents": [ "7bc2770064d3afbb4ce49c159d99c69a9e4b5c5b" ], "author": { "name": "Matthias Wippich", "email": "mfwippich@gmail.com", "time": "Tue Jul 28 07:31:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:31:53 2026" }, "message": "[clang][NFC] Refactor flag enum caching (#210632)\n\nExtracts cache insertion logic from `IsValueInFlagEnum`. This allows us\nto drop `mutable` on `FlagBitsCache` while making it reusable as work\nlist for additional flag_enum diagnostics." }, { "commit": "7bc2770064d3afbb4ce49c159d99c69a9e4b5c5b", "tree": "30a6de5902a6816f4ade5ed9c2ce66872224a9eb", "parents": [ "4df68548fcfd82ddfdfe5ae52e691966065cf2e1" ], "author": { "name": "Pavel Labath", "email": "pavel@labath.sk", "time": "Tue Jul 28 07:25:31 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:25:31 2026" }, "message": "[libc] Make assert_test hermetic (#210700)\n\nCall our own close() instead of the system one." }, { "commit": "4df68548fcfd82ddfdfe5ae52e691966065cf2e1", "tree": "d3e99a224db1804ecf20fa4a814fbdd107522ec6", "parents": [ "9ccf2a81a1b86c6b4d953259bbbdc678cc791493" ], "author": { "name": "Lang Hames", "email": "lhames@gmail.com", "time": "Tue Jul 28 07:14:30 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:14:30 2026" }, "message": "[orc-rt] Reorder wrapper-fn args to trailing-callback style. (#212243)\n\nBring the wrapper-function call and return prototypes into line with the\nconvention adopted for orc_rt_Session_callController: the session handle\ncomes first, then the payload buffer, then the completion callback\nimmediately followed by its threaded token, with the token last.\n\n orc_rt_WrapperFunctionReturn: (S, CallId, ResultBytes)\n -\u003e (S, ResultBytes, CallId)\n orc_rt_WrapperFunction: (S, CallId, Return, ArgBytes)\n -\u003e (S, ArgBytes, Return, CallId)\n\nThe C++ adapters that mirror these signatures are updated to match --\nWrapperFunction::handle, SPSWrapperFunction::handle, the\nORC_RT_SPS_WRAPPER macro, and StructuredYield -- along with the Session\ndispatch path and the affected unit tests. No functional change beyond\nargument order." }, { "commit": "9ccf2a81a1b86c6b4d953259bbbdc678cc791493", "tree": "adca5c5d4bd5a17a1bd2b7c6272da492f4a4e8f5", "parents": [ "022bf7ba97fa1897bf52cf3db2e3fa42cd19b29f" ], "author": { "name": "Akimasa Watanuki", "email": "mencotton0410@gmail.com", "time": "Tue Jul 28 07:09:11 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:09:11 2026" }, "message": "[MLIR][LLVM] Preserve default function attributes on invokes (#212263)\n\nRepresent `default_func_attrs` on `LLVM::InvokeOp` and translate the\ncollection onto the generated LLVM invoke instruction. Preserve default\ncall-site attributes when throwing calls are lowered through the LLVM\ndialect, including CIR `try_call` operations." }, { "commit": "022bf7ba97fa1897bf52cf3db2e3fa42cd19b29f", "tree": "a449b9211938c86c7d41a134a799628306cb3229", "parents": [ "f75eef2acb00eb8ff99cf9d7abb0d1649d0cbc90" ], "author": { "name": "Fangrui Song", "email": "i@maskray.me", "time": "Tue Jul 28 07:08:11 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:08:11 2026" }, "message": "[LoopInfo] Take no dominator tree in verify(). NFC (#212414)\n\nSimilar to the recent change that makes analyze() lazy in building\nDomTree." }, { "commit": "f75eef2acb00eb8ff99cf9d7abb0d1649d0cbc90", "tree": "6726204b7f166529255eba5a472bcb70309f4dd0", "parents": [ "ce62aab97e58c52e6bb0972c49d6fd1aaa6a08a0" ], "author": { "name": "Alexis Engelke", "email": "engelke@in.tum.de", "time": "Tue Jul 28 07:07:49 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 07:07:49 2026" }, "message": "[InstCombine] Handle icmp+ptrtoint/addr folds for non-int ptrs (#212101)\n\nFollowup of #211991. icmp ptrtoint, ptrtoint cannot be folded away for\nnon-integral pointers, this is only possible with ptrtoaddr.\n\nFor consistency, this also restricts the inttoptr direction, which\ncauses the change in the phase ordering test. (Note that in this\nparticular case, not doing the folding is actualle beneficial, as it\nkeeps the inttoptr-inttoptr comparison outside the loop avoiding one\ncomparison inside the loop. I wouldn\u0027t expect any practical impact,\nthough.)" }, { "commit": "ce62aab97e58c52e6bb0972c49d6fd1aaa6a08a0", "tree": "4663dbaa107dc4062e40e2694f273466ea0babd3", "parents": [ "b59d69d79e547a432485c18611efd2ec8d9540ca" ], "author": { "name": "Pavel Labath", "email": "pavel@labath.sk", "time": "Tue Jul 28 06:57:05 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:57:05 2026" }, "message": "[libc] Add aligned_alloc and delete[] to hermetic tests (#210693)\n\nThis lets us run (at least) \u003csearch.h\u003e tests in hermetic mode." }, { "commit": "b59d69d79e547a432485c18611efd2ec8d9540ca", "tree": "10f98826010f58893a2fb49b315ded3e1f1c1062", "parents": [ "4b60d133e3f80bac153bef496f56ee85936dfea1" ], "author": { "name": "Craig Topper", "email": "craig.topper@sifive.com", "time": "Tue Jul 28 06:51:52 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:51:52 2026" }, "message": "[RISCV][P-Ext] Unify pncvt(h) intrinsics between RV32 and RV64. (#210996)\n\nUse __builtin_convertvector for pncvt and __builtin_shufflevector for\npncvth.\n\nAlternatively we could use shift+__builtin_convertvector for pncvth but\nthat requires combining psrl+unzip(8/16)p to unzip(8/16)hp. I\u0027m not sure\nwhich is better right now." }, { "commit": "4b60d133e3f80bac153bef496f56ee85936dfea1", "tree": "4f882704830671bf7b62a8f283570fe505188eff", "parents": [ "9a5434468bf5a5aa77f46de98d17ec2eccdce39d" ], "author": { "name": "Sean Clarke", "email": "sclarke@tenstorrent.com", "time": "Tue Jul 28 06:51:29 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:51:29 2026" }, "message": "[RISCV] Add custom lowering for fixed-vector `CLMUL`/`CLMULH` (#210429)\n\n`CLMUL` and `CLMULH` currently expand for fixed vector types on RISC-V,\neven if `Zvbc` and/or `Zvbc32e` are available. Add custom lowering to\nconvert to scalable vector operations according to extension\navailability.\n\nAssisted-by: Claude Opus 4.8" }, { "commit": "9a5434468bf5a5aa77f46de98d17ec2eccdce39d", "tree": "2a86ce8d8f48380bf0791d385ef99f785425899e", "parents": [ "d81bb91dfe1a32bdb9621d483c7a059ddd56970b" ], "author": { "name": "jeanPerier", "email": "jperier@nvidia.com", "time": "Tue Jul 28 06:39:52 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:39:52 2026" }, "message": "[flang][NFC] Extract StackArrays analysis and rewrite into a header - memory passes unification [1/5] (#210721)\n\nMove InsertionPoint, StackArraysAnalysisWrapper, and AllocMemConversion\nout of the anonymous namespace in StackArrays.cpp into a new\nStackArrays.h header (in namespace fir), so the \"which fir.allocmem can\nbe safely moved to the stack, and where\" analysis and the heap-to-stack\nrewrite pattern can be reused by other passes.\n\nThe dataflow internals (AllocationState, LatticePoint,\nAllocationAnalysis), the command-line options, and all method\ndefinitions remain in the .cpp. No functional change intended.\n\nRFC:\nhttps://discourse.llvm.org/t/rfc-flang-improving-temporary-and-local-array-allocations-unify-stackarray-memoryallocation/91353\n\nAssisted-by: AI" }, { "commit": "d81bb91dfe1a32bdb9621d483c7a059ddd56970b", "tree": "ed757259ad55bff2d89b3d979a99e039066c86f6", "parents": [ "ee8bf569630bd45559227434f6cdf7aa67eb6a77" ], "author": { "name": "Yuyang Zhang", "email": "yuyzhang@amd.com", "time": "Tue Jul 28 06:37:54 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:37:54 2026" }, "message": "[DAGCombiner] Fold insert_vector_elt into a shared BUILD_VECTOR (#210905)\n\nThe `insert_vector_elt -\u003e build_vector` fold requires the source\n`BUILD_VECTOR` to have a single use, to avoid duplicating it. Allow it\nfor a multi-use base when the target sets\n`aggressivelyPreferBuildVectorSources`: a `BUILD_VECTOR` is just glue\nthere (e.g. `REG_SEQUENCE` on AMDGPU), so rebuilding re-references the\nbase\u0027s existing scalar operands and adds no real work. This un-shares a\nCSE-shared base produced by `insertelement` on a poison vector, so each\nderived vector is built from scalars independently, as GlobalISel\nalready does.\n\nThe gate mirrors the sibling `extract_vector_elt` fold: `hasOneUse() ||\nTLI.aggressivelyPreferBuildVectorSources(VT)`.\n\nSplit out from #199631 per review. Opted-in targets are AMDGPU, NVPTX,\nand AArch64: AMDGPU and NVPTX improve, AArch64 is unchanged; non-opted\ntargets are unaffected. Affected AMDGPU and NVPTX tests are regenerated.\n\nThe undef-deprecator flag on `splitkit-getsubrangeformask.ll` is a false\npositive — those are MIR subregister-def flags (`undef %reg.sub`), not\nIR `undef` values." }, { "commit": "ee8bf569630bd45559227434f6cdf7aa67eb6a77", "tree": "1a12a53be062b264fe6d07527d14f60a3c32a796", "parents": [ "f2c7e2bcd57ef2a9db23e5071618d3e02ee9c33d" ], "author": { "name": "Heejin Ahn", "email": "aheejin@gmail.com", "time": "Tue Jul 28 06:37:52 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:37:52 2026" }, "message": "[lld][WebAssembly] Fix SharedTagKind in toString (#212385)" }, { "commit": "f2c7e2bcd57ef2a9db23e5071618d3e02ee9c33d", "tree": "37efc1b368f92fcb2f2f80364703988d52602719", "parents": [ "d1ce5f95fb661999bcc99a3a816cc72c1220a36d" ], "author": { "name": "Pavel Labath", "email": "pavel@labath.sk", "time": "Tue Jul 28 06:20:07 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:20:07 2026" }, "message": "[libc] Fix atexit_test in hermetic mode (#210656)\n\nWe never unlocked the ThreadAtExit mutex, which meant the second call to\nexit deadlocked. This was detected in the unit tests as they were\ncalling __cxa_thread_atexit from the system C library." }, { "commit": "d1ce5f95fb661999bcc99a3a816cc72c1220a36d", "tree": "2c6d22bb920bfa86850446af9041221832e9e9e9", "parents": [ "ed4090047fb6c40d8d014559da16cee934f124c0" ], "author": { "name": "Alexis Engelke", "email": "engelke@in.tum.de", "time": "Tue Jul 28 06:18:15 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:18:15 2026" }, "message": "[ASan] Instrument ptrtoaddr as pointer difference (#211988)\n\nWe want to emit ptrtoaddr instead of ptrtoint for pointer differences to\nnot expose the provenance. Adjust ASan instrumentation to handle this\ncase as well." }, { "commit": "ed4090047fb6c40d8d014559da16cee934f124c0", "tree": "5878ee679a90bfb0905777df0dbb17866c2ec643", "parents": [ "de962dda125154abb64446c198b5349cf05311cb" ], "author": { "name": "Kazu Hirata", "email": "kazu@google.com", "time": "Tue Jul 28 06:17:03 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:17:03 2026" }, "message": "[SampleProfile] Fix symbol partitioning in Eytzinger name table (#211906)\n\nThis patch fixes the symbol partitioning between context-sensitive\nand flat profiles in writeEytzingerNameTableSection.\n\nIn split-layout profiles, top-level symbols in the Eytzinger name\ntable are partitioned into two bins -- context-sensitive and flat keys\n-- so that they form parallel arrays with function offsets.\n\nWithout this patch, writeEytzingerNameTableSection uses:\n\n if (Ctx.hasContext())\n\nto decide which bin to use even though splitProfileMapToTwo uses:\n\n if (!I.second.getCallsiteSamples().empty())\n\nto partition the profile. This difference causes certain symbols to\nbe classified into FlatKeys in the name table but into\nContextProfileMap in the LBR profile.\n\nThe patch fixes the problem by using the same condition to partition\nkeys.\n\nThis misclassification happens to top-level symbols (like main or\nun-inlined root callers) that lack context delimiters in their\nfunction names (hasContext() \u003d\u003d false) but still contain inlined\ncallees in their profile hierarchies.\n\nRFC:\nhttps://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/8\n\nAssisted-by: Antigravity" }, { "commit": "de962dda125154abb64446c198b5349cf05311cb", "tree": "c7a6f6e502027039866c29caff1d228f4cc81dab", "parents": [ "0a30b0c8909dca8764d994a748bd7d53c68d94f7" ], "author": { "name": "Hui", "email": "hui.xie1990@gmail.com", "time": "Tue Jul 28 06:15:19 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:15:19 2026" }, "message": "[libc++] Implement P0528R3 `std::atomic` CAS for types with padding (#76180)\n\nFixes #99984\n\nImplement P0528R3 The Curious Case of Padding Bits, Featuring Atomic\nCompare-and-Exchange\n\n\nThe unit test padding.pass.cpp is assisted by Cursor. However, all tests\nhave been modified to test what I wanted to test\n\n---------\n\nCo-authored-by: Louis Dionne \u003cldionne.2@gmail.com\u003e" }, { "commit": "0a30b0c8909dca8764d994a748bd7d53c68d94f7", "tree": "8c26e591144c64d380729002659aad22fa84fcf0", "parents": [ "2f6ec89938aa12ba5190477032b974524c956b54" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Tue Jul 28 06:03:04 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 06:03:04 2026" }, "message": "AMDGPU: Declare FeatureDPP with AMDGPUSubtargetFeature (#212408)\n\nAll other features were defined using the AMDGPUSubtargetFeature\nsubclass of SubtargetFeature, so fix the odd one out." }, { "commit": "2f6ec89938aa12ba5190477032b974524c956b54", "tree": "a22b22ce4ab239ac5b1bbb009258fe9ed9e715e4", "parents": [ "776971a11fdce76b243bd94b1fe7d2b1957da969" ], "author": { "name": "Corentin Jabot", "email": "corentinjabot@gmail.com", "time": "Tue Jul 28 05:46:23 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 05:46:23 2026" }, "message": "[Clang] Implement P3658R1 (#212131)\n\nAs a DR in all C++ language modes.\nBecause we already supported the feature this is only modifying the\nextensions warnings." }, { "commit": "776971a11fdce76b243bd94b1fe7d2b1957da969", "tree": "0ed4b73e756d2a1fc36cce8b44da5e48504b9190", "parents": [ "6a55a52cabb5760902af7aa970dd37a323e255ad" ], "author": { "name": "Pengcheng Wang", "email": "wangpengcheng.pp@bytedance.com", "time": "Tue Jul 28 05:25:15 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 05:25:15 2026" }, "message": "Revert \"[RISCV] Add TuneNoDefaultUnroll to generic CPUs (#135318)\" (#212400)\n\nThis reverts commit 9c5858eb699390c2cac5f7f032279be275fa6aef which\ncauses some regressions." }, { "commit": "6a55a52cabb5760902af7aa970dd37a323e255ad", "tree": "dfca4a5d10255e7c80520d998600bbb146282ccf", "parents": [ "065179637e5331424ffdef8060593c57a53a6391" ], "author": { "name": "Luke Lau", "email": "luke@igalia.com", "time": "Tue Jul 28 04:31:02 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 04:31:02 2026" }, "message": "[VPlan] zext canonical IV in convertToStridedAccesses (#212291)\n\nCurrently we sext it which isn\u0027t correct at TCs \u003e UINT32_MAX. Makes\n#209611 NFC" }, { "commit": "065179637e5331424ffdef8060593c57a53a6391", "tree": "89d9e1258330db710cddf887b7d3c937c2ecca74", "parents": [ "1e1274b2ddfe4643eefdd1c6c83d6c2d61dace1d" ], "author": { "name": "Matsu", "email": "47756807+khaki3@users.noreply.github.com", "time": "Tue Jul 28 04:21:02 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 04:21:02 2026" }, "message": "[mlir][OpenACC] Lower single-block thread-only array reductions (#212369)\n\nExample:\n```fortran\n!$acc parallel loop vector reduction(+:b)\ndo i \u003d 1, n\n b(i) \u003d i\nend do\n```\n\nIn this code the array reduction is thread(vector)-only with no\ngang/block launch dim, so a within-block `all_reduce` is a complete\nreduction. ACCCGToGPU still rejected it as NYI because the accumulate\nhad no block context.\n\nFix: keep the NYI only when the region actually launches block\ndimensions; allow the existing per-element `all_reduce` path for\nsingle-block thread-only array accumulates." }, { "commit": "1e1274b2ddfe4643eefdd1c6c83d6c2d61dace1d", "tree": "6bf0be2eb5e6e6032dd647e6ab17bc23a94eb670", "parents": [ "bba25a8d818e146c132f927cc13b651359da4f26" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Tue Jul 28 04:07:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 04:07:53 2026" }, "message": "AMDGPU: Add -gen-amdgpu-target-def TableGen backend (#212318)" }, { "commit": "bba25a8d818e146c132f927cc13b651359da4f26", "tree": "b53ff096577085f1e029b9bf4dbbe1a2df70ce52", "parents": [ "30b8cb2003f7490eef20d8f31a8daa1cdb95f45d" ], "author": { "name": "Alex MacLean", "email": "amaclean@nvidia.com", "time": "Tue Jul 28 03:30:12 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 03:30:12 2026" }, "message": "[NVPTX] Emit some more PTX directives through target streamer (#212070)\n\nMove `.branchtargets`, `.reg`, `.local`, `.alias`, `.pragma`, and the\nempty `.debug_macinfo` section out of hand-built strings in\n`NVPTXAsmPrinter` and into `NVPTXTargetStreamer` hooks.\nOpportunistically pulled at a few other threads that could use cleanup\nas well.\n\nThree behavior changes: \n1. Jump table labels now come from `MachineFunction::getJTISymbol`, so\n`$L_brx_\u003cidx\u003e` becomes `JTI\u003cfunc\u003e_\u003cidx\u003e` and is no longer shared across\nfunctions\n2. `.alias` names its aliasee by mangled symbol rather than raw IR name,\nfixing `.alias a, ;` for an unnamed aliasee.\n3. The rest of the test diff is a duplicated blank line that functions\nwith no register declarations no longer emit.\n\nCo-Authored by Opus 5" }, { "commit": "30b8cb2003f7490eef20d8f31a8daa1cdb95f45d", "tree": "8bb7be01e1ee9dad90f4b7fa0d1db3cac305a26f", "parents": [ "5e91f5d57a19752fe245ab64c1265e26c44d0d76" ], "author": { "name": "Pengcheng Wang", "email": "wangpengcheng.pp@bytedance.com", "time": "Tue Jul 28 02:58:15 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 02:58:15 2026" }, "message": "[MacroFusion] Add RunPreRA/RunPostRA to select the scheduling stage (#212182)\n\nMacroFusion runs in both the pre-RA and post-RA machine schedulers.\nAdd two `bit` fields to the `Fusion` base class, `RunPreRA` and\n`RunPostRA`, both defaulting to `true`, so a fusion can opt out of a\nscheduling stage. At least one of them must be `true`.\n\nWhen a stage is disabled, `MacroFusionPredicatorEmitter` emits an early\n`return false` guard for that stage (detected via the `NoVRegs` machine\nfunction property) and only keeps the statistic counter for the stage\nthe fusion actually runs in. A pre-RA-only fusion is generated as:\n\n```cpp\n STATISTIC(NumNAMEPreRA, \"Times NAME Triggered (pre-ra)\");\n bool isNAME(...) {\n ...\n if (SecondMI.getMF()-\u003egetProperties().hasNoVRegs())\n return false;\n /* Predicates */\n ++NumNAMEPreRA;\n return true;\n }\n```\n\nSince the guard already establishes the stage, the trailing counter\n`if/else` collapses to a single increment, dropping the redundant\n`hasNoVRegs()` call and the counter that could never fire.\n\nAssisted-by: TRAE CLI (GPT 5.5)" }, { "commit": "5e91f5d57a19752fe245ab64c1265e26c44d0d76", "tree": "debc03979aad842ad8db9068ce7a38f1c756a0e6", "parents": [ "912128312f026605bce4ff11ef8a37d56a1a03f8" ], "author": { "name": "Alexey Bataev", "email": "a.bataev@outlook.com", "time": "Tue Jul 28 00:49:13 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 28 00:49:13 2026" }, "message": "[SLP]Fix dep accounting for expanded binops in non-scheduled entries\n\nThe extra dependency counted for the expanded form was never released\nwhen the expanding entry had no schedule bundle and the block had no\ncopyable elements, leaving the operand\u0027s bundle unscheduled forever.\nTake the pseudo-bundle path also when the instruction is an expanded\nbinop in some tree entry.\n\nFixes #212220\n\nReviewers: \n\nPull Request: https://github.com/llvm/llvm-project/pull/212380" }, { "commit": "912128312f026605bce4ff11ef8a37d56a1a03f8", "tree": "3134cf1d7aaeef661ba4fe5c356d9efde67a99fa", "parents": [ "e364a21086c71a68cac28f25469a7b014d1c2abd" ], "author": { "name": "Patryk Stefanski", "email": "patryk.stefanski@protonmail.com", "time": "Mon Jul 27 23:51:06 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 23:51:06 2026" }, "message": "[clang][Index][USR] Generate USRs for class-type non-type template arguments (#212356)\n\nA class-type non-type template parameter is represented in the AST by a\nTemplateParamObjectDecl, which has an empty DeclarationName.\nUSRGenerator had no visitor for it, so it fell through to\nVisitNamedDecl, where EmitDeclName fails on the empty name and sets\nIgnoreResults. That discarded the USR of the enclosing declaration.\n\nAdd a visitor that encodes the parameter object\u0027s type and value, so\nspecializations on distinct values get distinct USRs and equal values\nagree.\n\nFixes #212351" }, { "commit": "e364a21086c71a68cac28f25469a7b014d1c2abd", "tree": "3c640ab8e341b44d4ebb408f841c963aa0c969c2", "parents": [ "63fe0cfe25e6e438d64c81785b93e500855adb78" ], "author": { "name": "Ethan Luis McDonough", "email": "ethanluismcdonough@gmail.com", "time": "Mon Jul 27 23:43:05 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 23:43:05 2026" }, "message": "[Instrumentor] Reintroduce runtime inlining (#208072)\n\nThe ability to link in and eagerly inline a specified runtime was\npresent in older dev versions of the instrumentor. This patch ports that\nfunctionality to the current instrumentor pass and adds a test.\n\nCo-authored-by: Johannes Doerfert \u003cjohannes@jdoerfert.de\u003e\nCo-authored-by: Kevin Sala \u003csalapenades1@llnl.gov\u003e\nCo-authored-by: Ivan Radanov Ivanov \u003civanov.i.aa@m.titech.ac.jp\u003e" }, { "commit": "63fe0cfe25e6e438d64c81785b93e500855adb78", "tree": "a3377e424d9753dc625361e7c8c0ca102b6940a7", "parents": [ "7d96bd2ac1532e9ec6adf8eada303b5fe646857f" ], "author": { "name": "Arthur Eubanks", "email": "aeubanks@google.com", "time": "Mon Jul 27 23:28:52 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 23:28:52 2026" }, "message": "Reapply \"Disable RelLookupTableConverter on AArch64\" (#212358)\n\nThis reverts commit ce8cf3f0a427f7fcf178a9a64ea48a4167211f82 (#207046).\n\nReland of #204669.\n\n\nhttps://github.com/ARM-software/abi-aa/blob/main/sysvabi64/sysvabi64.rst#code-models\nsays that under the small code model rodata + text must fit in 2GB, but\nthe RelLookupTableConverter pass introduces PREL32 relocations from\n.rodata to .data.rel.ro:\n\n```\n$ cat /tmp/a.c\nextern void ext_func0(void);\nextern void ext_func1(void);\n\ntypedef void (*func_t)(void);\n\nstatic const func_t table0[2] \u003d { ext_func0, ext_func1 };\nstatic const func_t table1[2] \u003d { ext_func1, ext_func0 };\nstatic const func_t table2[2] \u003d { ext_func0, ext_func0 };\nstatic const func_t table3[2] \u003d { ext_func1, ext_func1 };\n\nconst func_t *get_table(unsigned int idx) {\n switch (idx % 4) {\n case 0: return table0;\n case 1: return table1;\n case 2: return table2;\n case 3: return table3;\n }\n return table0;\n}\n$ clang -O2 --target\u003daarch64-linux-gnu -fPIC -c /tmp/repro.c -o /tmp/repro.o\n$ llvm-readelf -r /tmp/repro.o\n...\nRelocation section \u0027.rela.rodata\u0027 at offset 0x370 contains 4 entries:\n Offset Info Type Symbol\u0027s Value Symbol\u0027s Name + Addend\n0000000000000000 0000000500000105 R_AARCH64_PREL32 0000000000000000 .data.rel.ro + 0\n0000000000000004 0000000500000105 R_AARCH64_PREL32 0000000000000000 .data.rel.ro + 14\n0000000000000008 0000000500000105 R_AARCH64_PREL32 0000000000000000 .data.rel.ro + 28\n000000000000000c 0000000500000105 R_AARCH64_PREL32 0000000000000000 .data.rel.ro + 3c\n...\n```" }, { "commit": "7d96bd2ac1532e9ec6adf8eada303b5fe646857f", "tree": "5b77bea51753124d78ff54d78ffda923fcb9b446", "parents": [ "4053f2b96988b69d68c8cc12913f51c149f1ac46" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Mon Jul 27 23:20:30 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 23:20:30 2026" }, "message": "[AMDGPU] Allow scalar operands in V_PK_LSHL_ADD_U64 (#212334)\n\nPatch creates dummy source modifiers for this instruction to use\nwith OPSEL. Even though these do not support modifiers we can reuse\nthe same mechanics as with packed fp64 and other u64 to allow scalar\noperands." }, { "commit": "4053f2b96988b69d68c8cc12913f51c149f1ac46", "tree": "56a00335533361c434e0b6ea98826d5f25902f43", "parents": [ "bd5883c35f43b01ab96bbdba1bc14a81f78694ea" ], "author": { "name": "Matsu", "email": "47756807+khaki3@users.noreply.github.com", "time": "Mon Jul 27 23:02:30 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 23:02:30 2026" }, "message": "[flang-rt][cuda] Keep CUFDeviceIsActive working under runtime/driver skew (#212320)\n\nResolve cuDevicePrimaryCtxGetState via the installed driver version, and\nprefer running scope-exit cleanup when the probe cannot prove teardown,\nso local device allocations are not leaked when the unversioned lookup\nfails." }, { "commit": "bd5883c35f43b01ab96bbdba1bc14a81f78694ea", "tree": "90d263503b855e8151fe9cd588119632b18146bf", "parents": [ "05eba618a37839999d3eb6ca7328337cd4765dfd" ], "author": { "name": "Daniel Paoliello", "email": "danpao@microsoft.com", "time": "Mon Jul 27 22:55:23 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 22:55:23 2026" }, "message": "[clang] Fix record alignment lost via external layout on Arm64 (#212362)\n\nAn external layout source (such as LLDB reading DWARF) supplies a\nrecord\u0027s final alignment directly, since `alignas` / `__declspec(align)`\nattributes are not recoverable from debug info. `finalizeLayout`\ncaptured `NonRequiredAlignment` before applying the external alignment,\nso an externally laid out record published a stale, too-small value.\n\nOn Arm64 this field is used to fold a base\u0027s alignment into the derived\nrecord, so a derived class picked up the stale value instead of the\nbase\u0027s actual alignment. This regressed\n`lldb/test/API/lang/cpp/alignas_base_class` when #210461 was merged,\nwhere `alignof(Derived)` evaluated to 1 instead of 8. Other targets were\nunaffected as they do not read this field.\n\nTreat all of an externally supplied alignment as non-required, as there\nis no way to tell how much of it was imposed by an alignment attribute." }, { "commit": "05eba618a37839999d3eb6ca7328337cd4765dfd", "tree": "f272a41925a78043e1e7a2f98813f8182070045d", "parents": [ "0fa9cfa567277a1fadd71e4c8cf41db5a7c84cff" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Mon Jul 27 22:27:35 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 22:27:35 2026" }, "message": "[VPlan] Add vputils::getEarlyExits helper (NFC) (#212348)\n\nBoth handleUncountableEarlyExits and the countable early-exit disconnect\nin handleEarlyExits walk all exit blocks and skip predecessors coming\nfrom the middle block to find the early exiting blocks.\n\nFactor that walk out into vputils::getEarlyExits, returning the (early\nexiting block, exit block) pairs." }, { "commit": "0fa9cfa567277a1fadd71e4c8cf41db5a7c84cff", "tree": "ec43ebbb7c1640852e0fcf34a72a30ffb19b2974", "parents": [ "d8d33abac0140c0554fd754b2646e142edcca484" ], "author": { "name": "Louis Dionne", "email": "ldionne.2@gmail.com", "time": "Mon Jul 27 22:27:14 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 22:27:14 2026" }, "message": "[CI] Add documentation for self-hosted runners (#211622)\n\nThis patch adds (work in progress) documentation for the various\nself-hosted runner groups we have access to in the LLVM monorepo." }, { "commit": "d8d33abac0140c0554fd754b2646e142edcca484", "tree": "185e460419f648b927ff2044e8f63d76a7e9605a", "parents": [ "61225df551b071f07dbf9fab98242a7477506b49" ], "author": { "name": "William Moses", "email": "gh@wsmoses.com", "time": "Mon Jul 27 22:26:34 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 22:26:34 2026" }, "message": "[MLIR] Allow recovering from semi-affine sets in FlatLinearValueConst… (#212346)\n\n…raints\n\nThe IntegerSet constructor of FlatLinearValueConstraints asserts when\nflattening fails, which happens for semi-affine integer sets. Since the\nfailure is signalled from inside a constructor, callers have no way to\ndetect the unsupported case ahead of time and no way to work around it;\nthey simply crash.\n\nAdd an optional `bool *error` parameter to the constructor. When it is\nnon-null, hitting the unimplemented case sets `*error` to true and\nreturns instead of asserting, letting callers bail out gracefully.\n`*error` is set to false on success. When the pointer is null the\nprevious assert behavior is retained, so existing callers are\nunaffected." }, { "commit": "61225df551b071f07dbf9fab98242a7477506b49", "tree": "4847ce8e802864ac5de26f8dfe07d6cd6c05509b", "parents": [ "4f02e1e45c2711a94dae0eac2051ad7c2e5ca8c2" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 22:03:46 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 22:03:46 2026" }, "message": "RuntimeLibcalls: Migrate to dag libcall predicates (#210674)\n\nSwitch to using dag predicates instead of free-form code predicates.\n\nCo-authored-by: Claude (Claude-Opus-4.8) \u003cnoreply@anthropic.com\u003e" }, { "commit": "4f02e1e45c2711a94dae0eac2051ad7c2e5ca8c2", "tree": "78e6608231d3f58db3289b6e760c79aa1de3adc4", "parents": [ "8a49f8839cdf743af250d3501262da0bb9876c98" ], "author": { "name": "Adrian Prantl", "email": "aprantl@apple.com", "time": "Mon Jul 27 21:59:17 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 21:59:17 2026" }, "message": "[LLDB] Hide unresolvable children from ObjC tagged pointers (#211936)\n\nFoundation\u0027s small value inline representations have valid summaries and\nsometimed synthetic children, but LLDB cannot access any ivars from\ntheir base classes (such as [NSObject isa]).\n\nUse a synthetic child provider to hide them.\n\nrdar://182434208\n\nAssisted-by: claude" }, { "commit": "8a49f8839cdf743af250d3501262da0bb9876c98", "tree": "34031ca71b3c4baadec13f1b17406b04b433b8d7", "parents": [ "a22416ba1ec8894ef98a437275e91f0ade3e2ba1" ], "author": { "name": "Arthur Eubanks", "email": "aeubanks@google.com", "time": "Mon Jul 27 21:57:24 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 21:57:24 2026" }, "message": "[gn build] Add missing deps (#212352)\n\nFrom e7290b1f1815626c4461d38671d93093590bf405" }, { "commit": "a22416ba1ec8894ef98a437275e91f0ade3e2ba1", "tree": "1d5e080013742602dc9f7dcd9f73d1307a5cafcf", "parents": [ "4ca573fb7947b3bebf5c1da512b5142679545905" ], "author": { "name": "Joshua Batista", "email": "jbatista@microsoft.com", "time": "Mon Jul 27 21:40:36 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 21:40:36 2026" }, "message": "[HLSL] Add UsedByAtomic64 shader flag (#211691)\n\nThis PR adds the `UsedByAtomic64` shader flag.\nIt detects any usage of an atomic instruction with a 64 bit type, and if\ndetected, sets the shader flag to true.\nThis is needed to pass DXIL validation.\n\nFixes https://github.com/llvm/llvm-project/issues/104392\nAssisted by: Github Copilot" }, { "commit": "4ca573fb7947b3bebf5c1da512b5142679545905", "tree": "33582cbe5333260343490821cf70d7d3d096d5eb", "parents": [ "295c3a461c7dd9d7f34306a89181ceb7139760ba" ], "author": { "name": "Louis Dionne", "email": "ldionne.2@gmail.com", "time": "Mon Jul 27 21:34:47 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 21:34:47 2026" }, "message": "[libc++] Rename the test suite used on LNT (#212347)\n\nThe LNT instance on http://lnt.llvm.org was wiped since I created the\noriginal schema, and we can now start over clean with a new test suite\nnamed `libcxx`." }, { "commit": "295c3a461c7dd9d7f34306a89181ceb7139760ba", "tree": "01a121460c49bf7374817b46a498448429008a16", "parents": [ "30bff76d3a294fe0882a05472234b25bb752b16a" ], "author": { "name": "Sophia Herrmann", "email": "herrmann15@llnl.gov", "time": "Mon Jul 27 21:30:50 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 21:30:50 2026" }, "message": "[Offload] Decouple CUDA source from NVPTX syncthreads assumption (#212339)\n\nWith the introduction of offloading via LLVM, the frontend language will\nnot necessarily determine the backend target anymore. Thus it is\nnecessary to guard against NVPTX instead of CUDA, since we could have\nCUDA-language device code targeting a non-NVPTX backend, where Clang\ndoes not provide __syncthreads as an NVPTX builtin and the generic shim\nis still needed.\n\nThis also avoids duplicate definitions on NVPTX. Clang already provides\n`__syncthreads` as an NVPTX target builtin, so\n`__clang_gpu_device_functions.h` should not also define an inline\n`__syncthreads` shim for NVPTX targets." }, { "commit": "30bff76d3a294fe0882a05472234b25bb752b16a", "tree": "060e6d9b35b177614fdcec3f59fb511735ff5f83", "parents": [ "aa8942dbf406e9e4c0cae84a6567dac37fac57c6" ], "author": { "name": "Valentin Clement (バレンタイン クレメン)", "email": "clementval@gmail.com", "time": "Mon Jul 27 20:59:07 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 20:59:07 2026" }, "message": "[flang][cuda] Do not emit cuf.register_variable_static for device/constant under unified mode (#212344)" }, { "commit": "aa8942dbf406e9e4c0cae84a6567dac37fac57c6", "tree": "6cae8475db21b0dac2f336e8a0a32f6af48c6386", "parents": [ "cef8432f7d149ef4e5888e29ff4d39ea580a806c" ], "author": { "name": "Sameer Sahasrabuddhe", "email": "sameer.sahasrabuddhe@amd.com", "time": "Mon Jul 27 20:47:23 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 20:47:23 2026" }, "message": "[Docs][AMDGPU] Eliminate incorrect use of double backticks [NFC] (#212343)" }, { "commit": "cef8432f7d149ef4e5888e29ff4d39ea580a806c", "tree": "0ab8cddb2b77baac7f9383b8419c34dcb8340976", "parents": [ "34c7c5ccca260c695d6b212a06c0e620d494adb4" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Mon Jul 27 20:41:47 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 20:41:47 2026" }, "message": "[VPlan] Account for masked VPInstructions in getIntrinsicID. (#212234)\n\ngetIntrinsicID may be called with masked VPInstructions. Update to skip\nthe mask, which is always the last operand.\n\nFixes https://github.com/llvm/llvm-project/issues/212165.\n\nPR: https://github.com/llvm/llvm-project/pull/212234" }, { "commit": "34c7c5ccca260c695d6b212a06c0e620d494adb4", "tree": "976addad0516bc04a939e8c4aa3e74a85d5999d1", "parents": [ "864f9a09887559491ef3f7ad39d57c703bc14f40" ], "author": { "name": "Changpeng Fang", "email": "changpeng.fang@amd.com", "time": "Mon Jul 27 20:35:22 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 20:35:22 2026" }, "message": "[AMDGPU][NFC] Rename packed instruction helper functions for clarity (#211933)\n\nRenames packed instruction helper functions to better reflect their\npurpose:\n - isPackedFP32or64BitInst → isSingleSGPRReadInst\n- isLegalGFX12PlusPackedMathFP32or64BitOperand → isLegalSingleSGPRReadInstOperand" }, { "commit": "864f9a09887559491ef3f7ad39d57c703bc14f40", "tree": "9a29dd0a9c5616e16acdf74ff9ac012086feee4d", "parents": [ "6534ceefd231771466abc9c388b93bb8b0913316" ], "author": { "name": "Björn Schäpers", "email": "bjoern@hazardy.de", "time": "Mon Jul 27 20:11:38 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 20:11:38 2026" }, "message": "[clang-format] Correctly annotate C# UTF 8 string literals (#211919)\n\nFixes #210506" }, { "commit": "6534ceefd231771466abc9c388b93bb8b0913316", "tree": "471dd368e91e8c55ef72570349755c250574be82", "parents": [ "767716657985094ce2e73eafe87d5fa8a24ac843" ], "author": { "name": "Sirraide", "email": "aeternalmail@gmail.com", "time": "Mon Jul 27 19:49:43 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:49:43 2026" }, "message": "[Clang] [NFC] Update OptionalUnsigned ctor to only reject signed integers (#212321)\n\nCurrently, the `OptionalUnsigned(int) \u003d delete;` constructor means that\nconstructing e.g. an `OptionalOrUnsigned\u003cuint64_t\u003e` from an `unsigned`\nfails because overload resolution is ambiguous (because `unsigned` -\u003e\n`int` and `unsigned` -\u003e `uint64_t` are both valid conversions). This\npatch adds a constraint to make sure the deleted constructor only\ncatches signed integer types.\n\nThis is needed for #212319." }, { "commit": "767716657985094ce2e73eafe87d5fa8a24ac843", "tree": "2eaa5eda01c8e933623c88c03cf618e811e9385d", "parents": [ "63e60a2853b1ff6fdac3cbaf668e2d2a63d51fae" ], "author": { "name": "Alex Duran", "email": "alejandro.duran@intel.com", "time": "Mon Jul 27 19:44:06 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:44:06 2026" }, "message": "[OFFLOAD][L0] Fix zero argurment kernel launch (#212296)\n\nPR #205224 changed the path for kernels with no arguments to not use\nappendLaunchKernelWithArgs, while at the same time it removed\nzeKernelSetGroupSize which resulted in incorrect sizing of the kernel.\n\nThis PR removes the alternate path and makes sure all launches go\nthrough appendLaunchKernelWithArgs.\n\nAlternatively we can restore zeKernelSetGroupSize on the alternate path." }, { "commit": "63e60a2853b1ff6fdac3cbaf668e2d2a63d51fae", "tree": "272eaf269171a116ff79e679f35a01f18f69fc2a", "parents": [ "c881d81f6b189f14c56c9bec8842ddba6255d0e5" ], "author": { "name": "Rafael Auler", "email": "rafaelauler@meta.com", "time": "Mon Jul 27 19:35:54 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:35:54 2026" }, "message": "[BOLT] Fix strict mode bug in removal of block referenced by JT (#211940)\n\nSummary:\nBOLT can create a jump table object from a PC-relative operand reference\n(e.g. leaq JT(%rip)) whenever the referenced memory looks like a PIC\njump table -- see\nBinaryContext::handleAddressRef. This is independent of whether BOLT\nrecognizes the indirect jump dispatch itself. The jump table annotation\nis only attached to the jmp instruction later, in\nBinaryFunction::analyzeIndirectBranch, and only when the target-specific\nanalyzeIndirectBranch matcher recognizes the dispatch pattern.\n\nIf the matcher does not recognize the pattern, the annotation is never\nattached to the jmp, even though the jump table object and its entries\nexist and reference basic blocks in the function.\n\nIn strict mode BOLT still fully processes such a function: it stays\nsimple, the block is marked as having unknown control flow, and the jump\ntable object is kept intact. Because the terminator carries no jump\ntable annotation, BinaryBasicBlock::hasJumpTable() returns false for it.\nLater passes then transform the function normally: remove-nops can empty\na jump table target block that consists only of nops, and NormalizeCFG\nthen redirects the block\u0027s predecessor and deletes the empty block - it\ndoes not recognize the block as a jump table target, since the\npredecessor\u0027s hasJumpTable() is false. The jump table object still\nreferences the deleted block by label, which produces an \"Undefined\ntemporary symbol\" error and fails emission.\n\nFix NormalizeCFG so it does not redirect/remove a block whose\npredecessor ends in an indirect branch, not only one flagged by\nhasJumpTable()." }, { "commit": "c881d81f6b189f14c56c9bec8842ddba6255d0e5", "tree": "e1c4f2d931db961c0fe08d5ce4a111ca07fae190", "parents": [ "4d14e9641ddf38d4b6cc2dbb5c882135d94c68c1" ], "author": { "name": "Rafael Auler", "email": "rafaelauler@meta.com", "time": "Mon Jul 27 19:34:36 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:34:36 2026" }, "message": "[BOLT] Release pseudo-probe decoder after emit (#211935)\n\nPseudoProbeRewriter builds sizable data structures and then hold onto\nthem after they are needed.\nPseudoProbeRewriter::postEmitFinalizer() parses the input .pseudo_probe\nsections into an MCPseudoProbeDecoder whose address-to-probe and\nGUID-to-function-desc maps can be very large (tens of GiB on big\nbinaries with many probes). This is not used again once probes have been\nupdated, yet they survive into the memory-heavy DWARF rewrite\n(updateDebugInfo), directly inflating BOLT\u0027s peak RSS at the worst\npossible time.\n\nThis frees them at the end of the postEmitFinalizer() calls, before\nupdateDebugInfo runs.\n\nStacked on top of the .dwo DIE diff, in large binaries you should\nobserve ~17% peak RSS wins if your\nbuild uses pseudo probe maps." }, { "commit": "4d14e9641ddf38d4b6cc2dbb5c882135d94c68c1", "tree": "9a22fe89c185ba30ffff80a4e20a9f3aea26829c", "parents": [ "bd7bb26108bd86eeeef0962577b52d0f435a7ac3" ], "author": { "name": "Arseniy Obolenskiy", "email": "arseniy.obolenskiy@amd.com", "time": "Mon Jul 27 19:16:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:16:53 2026" }, "message": "[mlir][MathToSPIRV] Allow math.cttz lowering for non-i32 integer widths (#206400)\n\nCo-authored-by: Igor Wodiany \u003cdev@wodiany.com\u003e" }, { "commit": "bd7bb26108bd86eeeef0962577b52d0f435a7ac3", "tree": "92bd4c1840ee8b92daff5fb46a696cf00c6f0406", "parents": [ "c2b22642d289413e136da29eaa1ce176ce438484" ], "author": { "name": "Daniel Paoliello", "email": "danpao@microsoft.com", "time": "Mon Jul 27 19:15:35 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:15:35 2026" }, "message": "[clang] Match MSVC ABI for over-aligned base tail padding on Arm64 (#210461)\n\nWhen targeting aarch64-pc-windows-msvc, clang laid out a base following\nan over-aligned, non-standard-layout base at the wrong offset. MSVC on\nArm64 reuses the over-aligned base\u0027s tail padding for the subsequent\nbase, but clang rounded the base up to a full slot, so the two disagreed\non member offsets, breaking interop between clang- and MSVC-built\nbinaries.\n\nFix: store each record\u0027s natural non-virtual alignment (excluding\n`alignas`/`__declspec(align)` over-alignment) as\n`getNonRequiredNVAlignment()`, and on Arm64 fold in a base\u0027s natural\nalignment rather than its full alignment. This is gated to Arm64 only;\nArm64EC and x64 follow the x64 rule (no reuse) and are unchanged.\n\nValidated against MSVC (Hostx64\\arm64\\cl.exe\n/d1reportSingleClassLayout): clang now matches MSVC Arm64 exactly for\nthe reduced repro, the original polymorphic case (vftable + empty base +\ntemplate), and a range of probe cases covering natural vs.\nover-alignment padding and field vs. base reuse. Arm64EC and x64 output\nis byte-identical to before.\n\nFixes #210174" }, { "commit": "c2b22642d289413e136da29eaa1ce176ce438484", "tree": "4d6bbd8f56b4605142ce868fde7a03a6f0333808", "parents": [ "460dbfc7ec59a89cc80f7c03879f60278ec2a6c4" ], "author": { "name": "Tomer Shafir", "email": "tomer.shafir8@gmail.com", "time": "Mon Jul 27 19:06:05 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:06:05 2026" }, "message": "[AArch64][MacroFusion] Add per cluster kind statistic (#212103)\n\nSo we can easily differentiate between different cluster kinds on\nAArch64 backend." }, { "commit": "460dbfc7ec59a89cc80f7c03879f60278ec2a6c4", "tree": "951d27935d2639070baa3c95fc63a3a218a24a85", "parents": [ "a950d4a527311fbfe202d563331f133400fd2c5e" ], "author": { "name": "Sean Clarke", "email": "sclarke@tenstorrent.com", "time": "Mon Jul 27 19:05:17 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:05:17 2026" }, "message": "[HashRecognize] Use loop latch to determine step/start for conditional recurrence (#211916)\n\nThe function `matchConditionalRecurrence` iterates over both PHI inputs\nand attempts to match each one to determine which is `Start` and which\nis `Step`. However, some of the failure conditions in the loop `return\nfalse`, which has the potential to classify some valid CRC loops as not\nhaving a conditional recurrence. The loop here is not really needed at\nall-- instead, use `L.getLoopLatch()` to determine `Start`/`Step`, since\nthe incoming value from the latch block will always be the `Step`. This\nalso avoids the aforementioned false negative classifications.\n\nAssisted-by: Claude Opus 5" }, { "commit": "a950d4a527311fbfe202d563331f133400fd2c5e", "tree": "e871520e4f9c168985d13bfdbb878b993a5773f3", "parents": [ "289a2d901a480e3c0ba8aac80c40f2fcd768506f" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 19:04:10 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 19:04:10 2026" }, "message": "AMDGPU: Use uint8_t for IsaVersion fields (#212311)" }, { "commit": "289a2d901a480e3c0ba8aac80c40f2fcd768506f", "tree": "2b5c47be7cdfa3abc4a2663da07a95b2dfb4c6f2", "parents": [ "a41a3359ec24f019a5a9576631228f0314be38a6" ], "author": { "name": "Stephen Long", "email": "63318318+steplong@users.noreply.github.com", "time": "Mon Jul 27 18:44:04 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:44:04 2026" }, "message": "[mlir][LinalgBlockPackMatmul] Add support for scalable block factors (#211354)\n\nAssisted by: Claude Sonnet 4.6\n\n---------\n\nCo-authored-by: Adam Siemieniuk \u003cadam.siemieniuk@intel.com\u003e" }, { "commit": "a41a3359ec24f019a5a9576631228f0314be38a6", "tree": "cf67688c82ed5cd9a6d6d8901c3cfee67549de1f", "parents": [ "79ea87c8da20263fa54c9f60b4befb3a9bf962cf" ], "author": { "name": "Valentin Clement (バレンタイン クレメン)", "email": "clementval@gmail.com", "time": "Mon Jul 27 18:42:48 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:42:48 2026" }, "message": "[flang][cuda] Do not check dummy in stmt function in device code (#212037)" }, { "commit": "79ea87c8da20263fa54c9f60b4befb3a9bf962cf", "tree": "c9abd894b06a934f56b74b9d3c020e1a0cb4ea1e", "parents": [ "f83fcfbdc7fc1bee6ebf242b110a5c2b46703ae9" ], "author": { "name": "Yingwei Zheng", "email": "dtcxzyw2333@gmail.com", "time": "Mon Jul 27 18:41:46 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:41:46 2026" }, "message": "[llubi] Add support for byte types (#200672)\n\nThis patch implements the support for byte types. The byte order depends\non the endianness for better performance in the fast path. For\nnon-byte-sized byte types, high bits are zeroed out." }, { "commit": "f83fcfbdc7fc1bee6ebf242b110a5c2b46703ae9", "tree": "7a5e652cfcf52112cf870b259cc2629c7616e6ed", "parents": [ "68e94c904067b1b984c6b337819633aee9f0c7da" ], "author": { "name": "Florian Mayer", "email": "fmayer@google.com", "time": "Mon Jul 27 18:41:31 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:41:31 2026" }, "message": "[MachineVerifier] do not use !NoPHI to check if a MF has phi nodes (#211941)\n\nWe were violating the property expressed in MachineFunction.h:\n\n```\nThe properties are stated in \"positive\" form; i.e. a pass could require\nthat the property hold, but not that it does not hold.\n```\n\nResolves a false positive \"MBB has allocatable live-in, [...]\" error in\nour downstream target." }, { "commit": "68e94c904067b1b984c6b337819633aee9f0c7da", "tree": "3a85d227f5d6421c3a5ab26c2f540f9258c0edb8", "parents": [ "7336a38e5c6dea03c243bb37b44a2207471e63d3" ], "author": { "name": "Benedek Kaibas", "email": "82393336+benedekaibas@users.noreply.github.com", "time": "Mon Jul 27 18:20:19 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:20:19 2026" }, "message": "[analyzer] Improve dangling value tracking in DanglingPtrDeref (#211818)\n\nImprove dangling value tracking in the `DanglingPtrDeref` checker by\nadding `trackExpressionValue`. The report with this change now tracks\nthe dangling value and shows where the value originated from. Currently\nthe checker only points at the destruction and use sites which isn\u0027t\nalways useful for the user." }, { "commit": "7336a38e5c6dea03c243bb37b44a2207471e63d3", "tree": "4618a1dd139b7149b9766c99ed04a856cdd1dd04", "parents": [ "0600aeae3ba6c41da80bbb84c10f1cad4c9a58ba" ], "author": { "name": "rdevshp", "email": "rdevshp@gmail.com", "time": "Mon Jul 27 18:18:02 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:18:02 2026" }, "message": "[clang] Add missing VisitAtomicTypeLoc to TypeLoc.cpp GetContainedAutoTypeLocVisitor (#211752)\n\nAdds the missing `VisitAtomicTypeLoc` method to TypeLoc.cpp `GetContainedAutoTypeLocVisitor`.\n\nFixes: https://github.com/llvm/llvm-project/issues/211556 ICE.\n\nAssisted-by: Codex" }, { "commit": "0600aeae3ba6c41da80bbb84c10f1cad4c9a58ba", "tree": "a1419efc90955703e381d722e8aa2d64250612e7", "parents": [ "b9a7aad4a9d50b9ec60b59d197be43a973a0572c" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Jul 27 18:01:35 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 18:01:35 2026" }, "message": "[AArch64][GlobalISel] Use integer types for inline assembly lowering (#212214)\n\nIf we need to generate a trunc then we can use an integer type for the\nlowering." }, { "commit": "b9a7aad4a9d50b9ec60b59d197be43a973a0572c", "tree": "51d1855e9a027648fae7d2bbb120342bf77b6666", "parents": [ "02da01251156c831a54417d4882aad7226cdbbe1" ], "author": { "name": "Tom Stellard", "email": "tstellar@redhat.com", "time": "Mon Jul 27 17:58:58 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:58:58 2026" }, "message": "workflows/release-tasks: Fix permissions for release-documentation (#212310)" }, { "commit": "02da01251156c831a54417d4882aad7226cdbbe1", "tree": "b6d02aa2c816a6b69729867726f6ad17c70b7e97", "parents": [ "751eb22c1b835b675166e4936a93f903b952f28f" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 17:57:14 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:57:14 2026" }, "message": "TableGen: Use a compact table for CPU aliases (#211952)" }, { "commit": "751eb22c1b835b675166e4936a93f903b952f28f", "tree": "3fced47caa1d3924159d0f91528215116d990123", "parents": [ "ad791f26ef495dbc2c3c6c283518872697210898" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Jul 27 17:54:43 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:54:43 2026" }, "message": "[AArch64][GlobalISel] Use integer type for truncating merged call args. (#212208)" }, { "commit": "ad791f26ef495dbc2c3c6c283518872697210898", "tree": "b7b09187d63f133108889135b8313892a4ba24ce", "parents": [ "5565740f2367093b89481ba7371adf820971977d" ], "author": { "name": "Christopher Ferris", "email": "cferris1000@users.noreply.github.com", "time": "Mon Jul 27 17:49:24 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:49:24 2026" }, "message": "[scudo] Test to verify fork and allocate does not deadlock. (#211975)" }, { "commit": "5565740f2367093b89481ba7371adf820971977d", "tree": "89767200fdb10df4f0529af5235d48f6e414f48a", "parents": [ "41a5357e389b3c04d4c44631360dd3661488c629" ], "author": { "name": "Arthur Eubanks", "email": "aeubanks@google.com", "time": "Mon Jul 27 17:39:23 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:39:23 2026" }, "message": "[lld] Don\u0027t drop RELR relocations for late-added GOT entries (#211911)\n\nIn #208959 we started dropping RELR relocations for late-added GOT\nentries when reverting x86-64 GOTPCRELX relaxations in\nX86_64::relaxOnce.\n\nThere is a separate unrelaxation bug where if the object files didn\u0027t\nhave any relocations of a certain type, we\u0027d prune .relr.dyn (or even\n.rela.dyn). Will be addressed separately.\n\nAssisted-by: Gemini" }, { "commit": "41a5357e389b3c04d4c44631360dd3661488c629", "tree": "7e33a59609a1a40a31f3d386d96a3229b60e0b57", "parents": [ "b8bd63c69c83bc13b31e808f9b7d84a562251396" ], "author": { "name": "AZero13", "email": "gfunni234@gmail.com", "time": "Mon Jul 27 17:26:24 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:26:24 2026" }, "message": "[clang][Sema] Allow abstract declarators to specify cv-qualified function types as per CWG1417 (#209836)\n\nAbstract declarator contexts (specifically `DeclaratorContext::TypeName`) now properly bypass this restricted rule, allowing cv-qualified function types in `__typeof__` while maintaining restrictions in other contexts like `typeid`, `sizeof`, C-style casts, and `new` expressions per CWG1417." }, { "commit": "b8bd63c69c83bc13b31e808f9b7d84a562251396", "tree": "c94709cd84712a25b0239c11486fff9f2f873509", "parents": [ "2a323d5bb13890cc0667d5e21e43f41020f4f606" ], "author": { "name": "Razvan Lupusoru", "email": "razvan.lupusoru@gmail.com", "time": "Mon Jul 27 17:10:49 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:10:49 2026" }, "message": "[flang][acc] Emit NYI messages for unsupported directives (#211894)\n\nAdd an OpenACC MLIR pass that emits not-yet-implemented messages for\nunsupported directives immediately after HLFIR generation. This allows\nOpenACC dialect operations to be emitted with -emit-hlfir while making\nfull compilation fail early with clear diagnostics, instead of later\nwhen unhandled OpenACC operations reach LLVM dialect conversion." }, { "commit": "2a323d5bb13890cc0667d5e21e43f41020f4f606", "tree": "1df9c73f5020c6a4245ce1cbf960d24e9d4a6e7f", "parents": [ "e59df8e339bc5bc07991e0a67d3d0cb8c25a94c2" ], "author": { "name": "Fangrui Song", "email": "i@maskray.me", "time": "Mon Jul 27 17:07:56 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:07:56 2026" }, "message": "[ProfileData] Make FunctionSamples profile-format flags atomic (#208964)\n\n`lld/test/ELF/lto/sample-profile.ll` is failing in ThreadSanitizer\nbuild.\n\nIn a parallel in-process ThinLTO link, each backend thread reads the\nsample profile in SampleProfileLoader::doInitialization and writes these\nglobals.\n\nMake the variables std::atomic\u003cbool\u003e so the same-value writes are\nwell-defined. An architectural ideal solution that holds these states in\na container seems very intrusive." }, { "commit": "e59df8e339bc5bc07991e0a67d3d0cb8c25a94c2", "tree": "6a48f313ea2f72b9c2337ec95051bc4317ce36db", "parents": [ "07aa3b710f2622f662cab7a53ddf1288c725a9be" ], "author": { "name": "Diego Novillo", "email": "dnovillo@nvidia.com", "time": "Mon Jul 27 17:06:48 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:06:48 2026" }, "message": "[SPIRV] Emit NonSemantic DebugTypeArray. (#211537)\n\nThis PR adds `DebugTypeArray` to `SPIRVNonSemanticDebugHandler`:\n\n1. `partitionTypes` buckets `DICompositeType` nodes tagged\n`DW_TAG_array_type` without `DINode::FlagVector` (vectors are emitted\nseparately).\n2. `emitNonSemanticGlobalDebugInfo` emits one `DebugTypeArray` per node\nafter the pointer types and records the id in `DebugTypeRegs`.\n3. `emitDebugTypeArray` appends one `OpConstant` component count per\n`DISubrange`, in subrange order. A subrange with no constant count emits\n0, matching `OpTypeRuntimeArray`. An array whose element type is not in\n`DebugTypeRegs` is skipped.\n\nClang lowers a matrix to a `DW_TAG_array_type` with two subranges in\n`CGDebugInfo::CreateType(const ConstantMatrixType *)`, so an HLSL\n`float4x4` emits as a `DebugTypeArray` with two counts.\n`DebugTypeMatrix` needs a distinguishing flag from the frontend.\n\nAdded a couple of tests in `llvm/test/CodeGen/SPIRV/debug-info/`:\n\n1. `debug-type-array.ll` covers a 1D array, a 2D array, a runtime-sized\narray, and an array of vectors, and asserts that we are not emitting\n`DebugTypeMatrix` (this will need to be changed when/if we start\nemitting them).\n2. `debug-type-array-skip-element-not-in-regs.ll` tests arrays of types\nthat cannot have debug info (I used array of pointers wit no DWARF\naddress space)." }, { "commit": "07aa3b710f2622f662cab7a53ddf1288c725a9be", "tree": "d56098b06f09635075656375768cda00847bd78d", "parents": [ "3c6d9cdb08c9245bb4d80e3262f74ea372046bcb" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Mon Jul 27 17:00:23 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 17:00:23 2026" }, "message": "[SLP] Only consider BuildVector inserts into the same object. (#212269)\n\nWhen following insertelement instruction for a BuildVector sequence, we\nmay discover a user that inserts into a different vector.\n\nBail out when that happens instead of crashing.\n\nPR: https://github.com/llvm/llvm-project/pull/212269" }, { "commit": "3c6d9cdb08c9245bb4d80e3262f74ea372046bcb", "tree": "bb73a888c7bfd5db50f4b90ed26aef06c9e996ed", "parents": [ "7baccda8dde277b16cb87318536b3ca70d448db1" ], "author": { "name": "Tom Stellard", "email": "tstellar@redhat.com", "time": "Mon Jul 27 16:58:39 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:58:39 2026" }, "message": "workflows/release-binaries: Add missing action to checkout (#211720)\n\nThe upload-release-artifact action uses the require-team-membership\naction so we need to make sure that latter is checkout out when calling\nupload-release-artifact." }, { "commit": "7baccda8dde277b16cb87318536b3ca70d448db1", "tree": "4192c0d07a25ce67f344a85ed078e836da2984ec", "parents": [ "d53cb74cbbc24fc5deba87b94ec38a7636bb52a9" ], "author": { "name": "Fangrui Song", "email": "i@maskray.me", "time": "Mon Jul 27 16:56:51 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:56:51 2026" }, "message": "[LoopInfo] Build dominator tree only for irreducible CFG (#212098)\n\nanalyze() requires a dominator tree, so LoopAnalysis and\nMachineLoopAnalysis request one for every function, though only an\nirreducible CFG queries it. Clients that build their own, from\nInlineCost to XRayInstrumentation, need it for nothing else.\n\nTake the function and a callback returning the tree instead, and call it\nwhen an edge re-enters a loop. Add an analyze(F) overload for a client\nthat holds no tree.\n\nThe number of dominator tree builds does not change in an -O2 pipeline\nbuilding sqlite3.bc, where SROA and InstCombine cache one before\nLoopAnalysis runs.\n\nTests that observed the tree through LoopAnalysis now require it\nexplicitly.\n\nMachineLoopInfoWrapperPass keeps requiring one: the legacy pass manager\ncannot provide it on demand.\n\nAided by Claude Opus 5" }, { "commit": "d53cb74cbbc24fc5deba87b94ec38a7636bb52a9", "tree": "7519d7ca1075903416facd00232e35abeb8bcf03", "parents": [ "58a6567a166e0cb44227d162914778176a4faf62" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 16:52:48 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:52:48 2026" }, "message": "X86: Use ProcessorAlias for duplicated processor names (#211953)\n\nMany X86 processors were defined multiple times under different names,\nemitting an identical ProcessorModel for each spelling and duplicating\nthe feature masks, tune features, and scheduling model index in the\nsubtype table.\n\nDefine each processor once under its canonical name and express the\nalternate spellings with ProcessorAlias, using the tablegen alias\nmechanism. This deduplicates the redundant subtype table entries and\nsaves about 4.6k with the new alias table (#211952)\n\nCo-Authored-By: Claude (Claude-Opus-4.8) \u003cnoreply@anthropic.com\u003e" }, { "commit": "58a6567a166e0cb44227d162914778176a4faf62", "tree": "fed2029227b45a3badfdd4d5d1b1b3f694b5d8a2", "parents": [ "ec96f85d6d82c5e71b36f9c827f09bb3b4825390" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 16:45:53 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:45:53 2026" }, "message": "AMDGPU: Use ProcessorAlias for legacy arch names (#211776)\n\nOlder targets have aliasing names which were previously implemented\nby defining a second copy of the processor, identical except for the\nname Use the recently improved tablegen mechanism for defining name-only\naliases. This dedupliates some redundant table entries, like the sched model.\n\nCo-authored-by: Claude (Claude-Opus-4.8) \u003cnoreply@anthropic.com\u003e" }, { "commit": "ec96f85d6d82c5e71b36f9c827f09bb3b4825390", "tree": "c87c212a052687b01fcab737d72cb026e0300f22", "parents": [ "de793e832cc5cddf9d8554ec07f42e1298908f72" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Jul 27 16:45:28 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:45:28 2026" }, "message": "TableGen: Add first class support for processor aliases (#211775)\n\nPreviously isCPUStringValid was virtual so TableGen could emit an\nAArch64 specific hack for recognizing cpu aliases. Teach tablegen\nabout aliases, and insert each alias into the CPU subtype table as its\nown entry (sorted by name, carrying the canonical processor\u0027s features\nand scheduling model).\n\nThere is further opportunity for code sharing improvements. AArch64\u0027s\naliases are consumed by ARMTargetDefEmitter to emit a custom inc file\nin TargetParser which should be universalized.\n\nCo-authored-by: Claude (Claude-Opus-4.8) \u003cnoreply@anthropic.com\u003e" }, { "commit": "de793e832cc5cddf9d8554ec07f42e1298908f72", "tree": "fb6d40cb01cfd0b34aca09fb4f766e9d5990aeea", "parents": [ "0733641570c25e6323e39c4ee66693a4668429a8" ], "author": { "name": "Zach Goldthorpe", "email": "Zach.Goldthorpe@amd.com", "time": "Mon Jul 27 16:44:22 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:44:22 2026" }, "message": "[AMDGPU][True16] Retain `hi16` subregisters through v2s copies (#211848)\n\nThe current legalisation for SGPR/VGPR copies with mismatched sizes does\nnot check which VGPR subregister is used, and defaults to using `lo16`.\nIf the `hi16` subregister is used instead, this information is lost, and\nthe subregister is incorrectly replaced with `lo16`.\n\nThis patch retains the subregister used when legalising the copy." }, { "commit": "0733641570c25e6323e39c4ee66693a4668429a8", "tree": "5d800e05257576c6ec15f019f718030c86ccf870", "parents": [ "26bf39cdba0bfcd0ea781f95cf44519922a8eb56" ], "author": { "name": "Hui", "email": "hui.xie1990@gmail.com", "time": "Mon Jul 27 16:32:19 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:32:19 2026" }, "message": "[libc++][test] re-enable clear padding runtime test (#211258)" }, { "commit": "26bf39cdba0bfcd0ea781f95cf44519922a8eb56", "tree": "4d4ecb133c5ea08f8309658e77f031600cb74084", "parents": [ "20f06e490149867d2a261cbcca41fa176bdc87b1" ], "author": { "name": "Jessica Clarke", "email": "jrtc27@jrtc27.com", "time": "Mon Jul 27 16:29:37 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 27 16:29:37 2026" }, "message": "[ELF][PowerPC] Don\u0027t assume TOC pointer is valid in IPLT entries (#207555)\n\nUnlike normal PLT entries, IPLT entries can be called indirectly even\nwhen in PIEs/DSOs, and so there\u0027s no guarantee on what\u0027s in the TOC\npointer register at that time. Therefore we must emit variants of the\nexisting code that work without it, whether r12-relative (playing the\nsame role as MIPS\u0027s $25) in the same number of instructions, or first\nretrieving PC in an i386-like manner, being careful not to clobber LR.\nOn 32-bit PowerPC even direct calls to IPLT entries face the same issue,\nsince we\u0027d use the TOC base of the resolver, which may not be the same\nas the caller, even within the same object.\n\nNormal canonical PLTs still look broken on 64-bit PowerPC as they use\nthe TOC pointer register too, and similarly on 32-bit PowerPC for PIEs.\nWe should probably treat these cases the same as PIE on i386 (except\nincluding PDEs for 64-bit PowerPC), where it\u0027s an error due to the use\nof %ebx in PLT entries." } ], "next": "20f06e490149867d2a261cbcca41fa176bdc87b1" }