| commit | 8b525d2747f2584fc35d8c7e612e66f377858df7 | [log] [tgz] |
|---|---|---|
| author | sstwcw <f0gukp2nk@protonmail.com> | Sun Jun 26 01:51:40 2022 |
| committer | Copybara-Service <copybara-worker@google.com> | Sun Jun 26 02:26:43 2022 |
| tree | 365ad174efdc6b68a87babb4fddb626ecc86b8ef | |
| parent | d8e68153ef75d9c4fdb861cd3c669455767bca5c [diff] |
[clang-format] Parse Verilog if statements This patch mainly handles treating `begin` as block openers. While and for statements will be handled in another patch. Reviewed By: HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D123450 NOKEYCHECK=True GitOrigin-RevId: 9ed2e68c9ae5cf346f938cc095e5448c1ff60f51