)]}' { "log": [ { "commit": "3681f0ce1446167d01dfe125d6db96ba2ac31c3c", "tree": "e7ff9a6a208587e7a4a4ec1ff377fca2a70b2668", "parents": [ "e829e80faba35db623b5e272c867ad72146adcda" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Thu Apr 30 23:06:12 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Apr 30 23:06:12 2026" }, "message": "Add Cortex-A320 to MIDR decode table (#384)\n\nARM Cortex-A320 (MIDR part 0xD8F) is an ARMv9.2-A efficiency core.\nAdd its uarch enum and MIDR mapping so XNNPACK can select optimized\nkernels when running on this core.\n\nSigned-off-by: Nicolas Pitre \u003cnpitre@baylibre.com\u003e" }, { "commit": "e829e80faba35db623b5e272c867ad72146adcda", "tree": "ea1048a5fe1636ffca70830b36b6a731addce6bb", "parents": [ "d05fbcd57dc096718c4979e7c054e628f1f3520b" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Apr 28 16:00:41 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Apr 28 16:00:41 2026" }, "message": "Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC (#381)\n\n* Adding ro.soc.model support to cpuinfo to detect Qualcomm SM8850 SoC.\n\n* style: format src/riscv/linux/riscv-hw.c with clang-format" }, { "commit": "d05fbcd57dc096718c4979e7c054e628f1f3520b", "tree": "0f25b381978e8359626dede347287818002e16ec", "parents": [ "bc3c01e230c6974283e4b89421cfb0e232435589" ], "author": { "name": "Ken Unger", "email": "108287829+ken-unger@users.noreply.github.com", "time": "Wed Apr 15 05:20:00 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Apr 15 05:20:00 2026" }, "message": "Add riscv half-precision floating point detection (#375)\n\nAdd cpuinfo_has_riscv_zfh() and cpuinfo_has_riscv_zvfh for fp16 detection. \n\nThe motivation here is to enable this runtime detection support in xnnpack for its rvv fp16 kernels. (xnnpack uses this library) " }, { "commit": "bc3c01e230c6974283e4b89421cfb0e232435589", "tree": "0f9b497a3f298d624f160784844e566e7626385e", "parents": [ "7607ca500436b37ad23fb8d18614bec7796b68a7" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Apr 13 20:19:06 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Apr 13 20:19:06 2026" }, "message": "Add Sapphire Rapids (Golden Cove) microarchitecture detection (#377)\n\n* Add Sapphire Rapids (Golden Cove) microarchitecture detection\n\n* Add Emerald Rapids and Granite Rapids microarchitecture detection" }, { "commit": "7607ca500436b37ad23fb8d18614bec7796b68a7", "tree": "68fdec874a9b8ead86a941a869ed5d9920e583c1", "parents": [ "7364b490b5f78d58efe23ea76e74210fd6c3c76f" ], "author": { "name": "Rohanjames1997", "email": "rohan.james4@gmail.com", "time": "Thu Mar 12 01:02:42 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 12 01:02:42 2026" }, "message": "Report correct L2 cache size on ARM (Neoverse V1/V2) (#372)\n\nBy fetching the values from `/sys/devices/system/cpu/cpuN/cache/indexM/{size,level,type,...}`, that is populate via \nhttps://github.com/torvalds/linux/blob/master/arch/arm64/kernel/cacheinfo.c\nand\nhttps://github.com/torvalds/linux/blob/master/drivers/acpi/pptt.c\n\nFixes #369 \n\nTested on Arm Neoverse V1 and V2 EC2 instances. I reused the reproducer in #369 \n\n```\n#include \u003ccstddef\u003e\n#include \u003ccstdio\u003e\n#include \u003ccpuinfo.h\u003e\nsize_t l2_bytes() {\n if (!cpuinfo_initialize()) return 0;\n const cpuinfo_processor* p \u003d cpuinfo_get_current_processor();\n if (!p || !p-\u003ecache.l2) return 0;\n return p-\u003ecache.l2-\u003esize; // bytes\n}\nint main() { std::printf(\"%zu\\n\", l2_bytes()); }\n```\n\nThis now returns the expected results on Arm Neoverse V1 and V2\n___\n\nAdditionally, here is the output of `./cache-info`.\n1. On Neoverse-V1:\n```\nMax cache size (upper bound): 4194304 bytes\nL1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL2 data cache: 64 x 1 MB (inclusive), 8-way set associative (2048 sets), 64 byte lines, shared by 1 processors\n```\n2. On Neoverse-V2:\n```\nMax cache size (upper bound): 4194304 bytes\nL1 instruction cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL1 data cache: 64 x 64 KB, 4-way set associative (256 sets), 64 byte lines, shared by 1 processors\nL2 data cache: 64 x 2 MB (inclusive), 8-way set associative (4096 sets), 64 byte lines, shared by 1 processors\n```" }, { "commit": "7364b490b5f78d58efe23ea76e74210fd6c3c76f", "tree": "fd4b8ddff8ff284110131dffa892a24b36b00b2c", "parents": [ "84818a41e074779dbb00521a4731d3e14160ff15" ], "author": { "name": "Alexander Shaposhnikov", "email": "alexander.v.shaposhnikov@gmail.com", "time": "Wed Feb 18 21:35:49 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 18 21:35:49 2026" }, "message": "[cpuinfo] Add linux_ppc64le config (#373)\n\n" }, { "commit": "84818a41e074779dbb00521a4731d3e14160ff15", "tree": "8f75f7ab8b7d0a9a2bd5571dc3b684824068d25a", "parents": [ "f9a03241f8c3d4ed0c9728f5d70bff873d43d4e0" ], "author": { "name": "Redwanul Haque Sourave", "email": "redwanul.sourav@gmail.com", "time": "Fri Jan 30 17:45:09 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 30 17:45:09 2026" }, "message": "Fix buffer size for reading processor core id (#352)\n\n" }, { "commit": "f9a03241f8c3d4ed0c9728f5d70bff873d43d4e0", "tree": "a46fa1d5f805fc69d910992e36b098fa5bc57c2a", "parents": [ "b8ecd2f4455f593be18326b89af19be3f9959293" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Jan 27 20:07:08 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jan 27 20:07:08 2026" }, "message": "Detect AMD Family 26 extended models for cpuinfo_uarch_zen6 (#371)\n\n* Fix cpuinfo_x86_normalize_brand_string unannotated fall-through warning\n\n* Detect AMD Family 26 extended models for cpuinfo_uarch_zen6" }, { "commit": "b8ecd2f4455f593be18326b89af19be3f9959293", "tree": "5734d479a1fee4683d0d0c5ee403bca0ccc0be21", "parents": [ "e7b796ccd140df3264afd3f032debd51b4a776df" ], "author": { "name": "Edward Chen", "email": "18449977+edgchen1@users.noreply.github.com", "time": "Tue Jan 27 15:36:42 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jan 27 15:36:42 2026" }, "message": "Add fallback for ARM Windows fp16 detection. (#348)\n\nBackground: On a Windows ARM system, I observed that `cpuinfo_has_arm_fp16_arith()` started to return false after upgrading to a more recent cpuinfo version.\n\nIn #333, the initialization of `cpuinfo_isa.fp16arith` was updated to use `IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE)`. I suspect that this is not supported on older Windows versions.\n\nThis change adds a fallback path to set `cpuinfo_isa.fp16arith` the old way.\nhttps://github.com/pytorch/cpuinfo/blob/d3a86a813e2bb49d1eb5841ec12e2b135867ab98/src/arm/windows/init.c#L205-L208" }, { "commit": "e7b796ccd140df3264afd3f032debd51b4a776df", "tree": "66919038895214c8affa3da23c8a818ac9b87c4e", "parents": [ "1ce292fdeceb9a4dee168074a84d629a1f57e2fd" ], "author": { "name": "Alfredo Tupone", "email": "tupone@gentoo.org", "time": "Mon Jan 26 22:47:25 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jan 26 22:47:25 2026" }, "message": "cmake will require at least 3.10 compatibility (#319)\n\n" }, { "commit": "1ce292fdeceb9a4dee168074a84d629a1f57e2fd", "tree": "3c5701bc9e364ff2dce86ab05a7295f2c32b28d6", "parents": [ "c4b4f4bf08c0cf486fc3111d0244ebf2a48ad01b" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jan 26 22:25:29 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jan 26 22:25:29 2026" }, "message": "Add ARM Lumex C1 uarch (#370)\n\n* Add ARM Lumex C1 uarch\n\nSoC name: MediaTek MT6993\nMicroarchitectures:\n\t1x Lumex-C1-Ultra\n\t3x Lumex-C1-Premium\n\t4x Lumex-C1-Pro\nCores:\n\t0: 1 processor (0), ARM Lumex-C1-Ultra\n\t1: 1 processor (1), ARM Lumex-C1-Premium\n\t2: 1 processor (2), ARM Lumex-C1-Premium\n\t3: 1 processor (3), ARM Lumex-C1-Premium\n\t4: 1 processor (4), ARM Lumex-C1-Pro\n\t5: 1 processor (5), ARM Lumex-C1-Pro\n\t6: 1 processor (6), ARM Lumex-C1-Pro\n\t7: 1 processor (7), ARM Lumex-C1-Pro\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Lumex-C1-Ultra\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Lumex-C1-Premium\n\t2: 4 processors (4-7),\t2: 4 cores (4-7), ARM Lumex-C1-Pro\nLogical processors (System ID):\n\t0 (7)\n\t1 (4)\n\t2 (5)\n\t3 (6)\n\t4 (0)\n\t5 (1)\n\t6 (2)\n\t7 (3)\n\nPart numbers documented here:\nhttps://en.wikichip.org/wiki/arm_holdings/cortex\n\n* Add ARM Lumex C1 uarch\n\nSoC name: MediaTek MT6993\nMicroarchitectures:\n\t1x Lumex-C1-Ultra\n\t3x Lumex-C1-Premium\n\t4x Lumex-C1-Pro\nCores:\n\t0: 1 processor (0), ARM Lumex-C1-Ultra\n\t1: 1 processor (1), ARM Lumex-C1-Premium\n\t2: 1 processor (2), ARM Lumex-C1-Premium\n\t3: 1 processor (3), ARM Lumex-C1-Premium\n\t4: 1 processor (4), ARM Lumex-C1-Pro\n\t5: 1 processor (5), ARM Lumex-C1-Pro\n\t6: 1 processor (6), ARM Lumex-C1-Pro\n\t7: 1 processor (7), ARM Lumex-C1-Pro\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Lumex-C1-Ultra\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Lumex-C1-Premium\n\t2: 4 processors (4-7),\t2: 4 cores (4-7), ARM Lumex-C1-Pro\nLogical processors (System ID):\n\t0 (7)\n\t1 (4)\n\t2 (5)\n\t3 (6)\n\t4 (0)\n\t5 (1)\n\t6 (2)\n\t7 (3)\n\nPart numbers documented here:\nhttps://en.wikichip.org/wiki/arm_holdings/cortex\n\n* remove dot and fp16\n\n* fix mock naming" }, { "commit": "c4b4f4bf08c0cf486fc3111d0244ebf2a48ad01b", "tree": "7e063fe8afdc3404bd20ed7cd91822dae3e3093b", "parents": [ "0fea7f5f88243ee354df0e0082b5f27d13fc9551" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Jan 14 17:57:04 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 14 17:57:04 2026" }, "message": "Add ARM Cortex A520 little core uarch (#367)\n\nExample Samsung S24 sm-s921u\n\nSoC name: Unknown\nMicroarchitectures:\n\t1x Cortex-X4\n\t5x Cortex-A720\n\t2x Cortex-A520\nCores:\n\t0: 1 processor (0), ARM Cortex-X4\n\t1: 1 processor (1), ARM Cortex-A720\n\t2: 1 processor (2), ARM Cortex-A720\n\t3: 1 processor (3), ARM Cortex-A720\n\t4: 1 processor (4), ARM Cortex-A720\n\t5: 1 processor (5), ARM Cortex-A720\n\t6: 1 processor (6), ARM Cortex-A520\n\t7: 1 processor (7), ARM Cortex-A520\nClusters:\n\t0: 1 processor (0),\t0: 1 core (0), ARM Cortex-X4\n\t1: 3 processors (1-3),\t1: 3 cores (1-3), ARM Cortex-A720\n\t2: 2 processors (4-5),\t2: 2 cores (4-5), ARM Cortex-A720\n\t3: 2 processors (6-7),\t3: 2 cores (6-7), ARM Cortex-A520\nLogical processors (System ID):\n\t0 (7)\n\t1 (2)\n\t2 (3)\n\t3 (4)\n\t4 (5)\n\t5 (6)\n\t6 (0)\n\t7 (1)" }, { "commit": "0fea7f5f88243ee354df0e0082b5f27d13fc9551", "tree": "0f6e76fca4526f1cc23b0d76ef22c3e2592d591b", "parents": [ "315f594e7f4d4c35f357289ae5304af8d38d9fc3" ], "author": { "name": "Alfredo Tupone", "email": "tupone@gentoo.org", "time": "Wed Jan 07 01:51:28 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 07 01:51:28 2026" }, "message": "Upgrade C++ standard from CXX14 to CXX17 (#355)\n\nIt is required by gtest (newest version)" }, { "commit": "315f594e7f4d4c35f357289ae5304af8d38d9fc3", "tree": "c102474e5cb9bf9cfd86e6b217484ead709dfcbb", "parents": [ "2846bafc7c785f274e6e5defb26dabdb05fac148" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Jan 07 00:43:55 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 07 00:43:55 2026" }, "message": "Add Apple M3, M5 and A19 uarch support (#366)\n\n* Fix cpuinfo_x86_normalize_brand_string unannotated fall-through warning\n\n* Add Apple M3, M5 and A19 uarch support\n\n* fix duplicate header uarch" }, { "commit": "2846bafc7c785f274e6e5defb26dabdb05fac148", "tree": "c0cf671fa8a7cea710891b52fcfbb8a1e32e4f01", "parents": [ "b3b25967b5b80406304d575321e572c5f9e5e3c4" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jan 05 21:38:16 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jan 05 21:38:16 2026" }, "message": "Add Apple SME isa and vector length detects (#363)\n\n* Apple SME 2p1 and vector length detect\n\n- similar to windows/init.c but use sysinfo\n hw.optional.arm.FEAT_SME2p1\n hw.optional.arm.sme_max_svl_b\n\nTested on Macbook Pro with M4\n\n* Add Apple SME isa and vector length detects\n\n* clang format applied" }, { "commit": "b3b25967b5b80406304d575321e572c5f9e5e3c4", "tree": "afd1e9430dfbee596c1fe90bc211ef665caf2cb5", "parents": [ "e3f82e8f64f81e7a6987485f6795af6bd5f639e4" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 30 20:40:41 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 30 20:40:41 2025" }, "message": "Apple M4 uarch detect (#362)\n\n* Apple M4 uarch detect\n\n- Detect M4 and M4 Pro p-core and e-core\n\n* clang-format applied\n\n* fix clang-format" }, { "commit": "e3f82e8f64f81e7a6987485f6795af6bd5f639e4", "tree": "c341d4d0872404afe6d94bb77a712c2d959a7672", "parents": [ "38b1af9c619b4546bcfa3e66398a8cd8aa94c25a" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 30 18:13:14 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 30 18:13:14 2025" }, "message": "Blizzard duplicate return removed (#360)\n\n* Fix duplicate blizzard return\n\n- Fix a copy/paste error in uarch detect for Apple blizzard/avalanche uarch\n- Add comment for A14/M1 and A15/M2 cpufamily\n\n* Fix duplicate return for Apple M2 detect uarch\n\n- Add comments for M1 and M2\n\n* Fix comments for CPUFAMILY to match what the case/return are for" }, { "commit": "38b1af9c619b4546bcfa3e66398a8cd8aa94c25a", "tree": "b27aebfe81fe5f1e90b8edd5429dadc664656e11", "parents": [ "002c213d16b9dc3ddfb7ab388b13183df0e81c49" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Dec 29 01:27:38 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Dec 29 01:27:38 2025" }, "message": "Fix typo cpofreq (#358)\n\n- Replace cpofreq with cpufreq" }, { "commit": "002c213d16b9dc3ddfb7ab388b13183df0e81c49", "tree": "682a537d3045465f9993990d0a1e597a09550c4d", "parents": [ "e8b4def4e6e67bc78d1882b2d709d6f6e13097ee" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Dec 29 01:27:30 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Dec 29 01:27:30 2025" }, "message": "Add Oryon V3 uarch detect for pytorch/cpuinfo (#357)\n\nTested with One Plus 15\ndevice:\n - ro.product.device: \"OP611FL1\"\n - ro.product.name: \"CPH2747\"\n - ro.product.brand: \"OnePlus\"\n - ro.product.manufacturer: \"OnePlus\"\n - ro.product.model: \"CPH2747\"\n - ro.soc.manufacturer: \"QTI\"\n - ro.soc.model: \"SM8850\"\nprocessor:\n - chipset: \"Unknown\"\n - core: \"Oryon V3\"\n - MIDR: 0x512F0021" }, { "commit": "e8b4def4e6e67bc78d1882b2d709d6f6e13097ee", "tree": "16009fd34c313340f5f2d0971d7fbbef8f3234a9", "parents": [ "ff24ffee8340fbd9001cce6a9ef41cdd16aa2bd3" ], "author": { "name": "Vertexwahn", "email": "julian.amann@tum.de", "time": "Thu Dec 11 22:49:18 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Dec 11 22:49:18 2025" }, "message": "Bazel support: Sync with current status of BCR and apply fixes for Bazel 9 (#345)\n\n" }, { "commit": "ff24ffee8340fbd9001cce6a9ef41cdd16aa2bd3", "tree": "97c053a1e9792c7626c775501fbb2382f011813f", "parents": [ "161a9ec374884f4b3e85725cb22e05f9458fdc93" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Dec 09 23:14:26 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 09 23:14:26 2025" }, "message": "add Cortex A78C midr detect (#354)\n\n* add Cortex A78C midr detect\n\n- Detect ARM part 0xD4B (Cortex-A78C) and return cpuinfo_uarch_cortex_a78\n\n* fix clang format error for tabs" }, { "commit": "161a9ec374884f4b3e85725cb22e05f9458fdc93", "tree": "d990ead5980dafd52612acd8fbebfb78e7725f8e", "parents": [ "403d652dca4c1046e8145950b1c0997a9f748b57" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Nov 19 17:38:05 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Nov 19 17:38:05 2025" }, "message": "Fix ARM build -Wlogical-op-parentheses for unisoc detect (#347)\n\n- Add parentheses around the \u0027\u0026\u0026\u0027 expression" }, { "commit": "403d652dca4c1046e8145950b1c0997a9f748b57", "tree": "5dcedc8305dd86a04a0a4e2d16144762e0643965", "parents": [ "f858c30bcb16f8effd5ff46996f0514539e17abc" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Nov 18 19:51:03 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 18 19:51:03 2025" }, "message": "Fix overread asan error of brand_string (#344)\n\n- Brand string is 3 rows of cpuid which is 48 bytes.\n- Allow for CPUINFO_PACKAGE_NAME_MAX to be 64 bytes for benefit of Oryon" }, { "commit": "f858c30bcb16f8effd5ff46996f0514539e17abc", "tree": "996d51dc31c2268286a504ab29385e6b9e9ada4b", "parents": [ "1d1dbb4cd620d9d0026872da2d85418263179f20" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Fri Nov 14 19:00:48 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 14 19:00:48 2025" }, "message": "Improve unisoc vendor detection, re-enable neon dot on unknown chipsets (#342)\n\n" }, { "commit": "1d1dbb4cd620d9d0026872da2d85418263179f20", "tree": "7fe6905c070abf50a81ab58612066642e3d247e1", "parents": [ "952a519883239e086e9a78299a6efb8f6614022f" ], "author": { "name": "Bin Bao", "email": "binbao@meta.com", "time": "Fri Nov 14 15:47:39 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 14 15:47:39 2025" }, "message": "Fix missing AMD cache info when running on a VM (#338)\n\nSummary: Fix https://github.com/pytorch/pytorch/issues/138718. This PR is verified to fix the issue and will be guarded on the PyTorch CI.\n\nWhen running on a VM, the AMD TopologyExtensions bit can be cleared, but that shouldn\u0027t stop us from reading the cache information." }, { "commit": "952a519883239e086e9a78299a6efb8f6614022f", "tree": "7f41d52e6d74c277556ba8244fb1c73cf5d12802", "parents": [ "f1f25cbe838f514c6bdbe762574e0e14538bdba8" ], "author": { "name": "Jimothy Branson", "email": "jimothy@bouncingsheep.org", "time": "Thu Nov 13 23:46:12 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 13 23:46:12 2025" }, "message": "Allow for longer CPU names (#320)\n\nIncrease CPUINFO_PACKAGE_NAME_MAX to allow for longer strings,\nsuch as \"Snapdragon® X Elite - X1E78100 - Qualcomm® Oryon™ CPU\",\nwhich is 53 characters and WideCharToMultiByte converts to a\n57 byte string." }, { "commit": "f1f25cbe838f514c6bdbe762574e0e14538bdba8", "tree": "0aa4eb896f4a9f9fe6aa5a7232a459bdffa3fb4c", "parents": [ "735b2ac12f69aaf408784ed251b9bd6319cfc62d" ], "author": { "name": "Byoungchan Lee", "email": "byoungchan.lee@gmx.com", "time": "Thu Nov 13 23:29:49 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 13 23:29:49 2025" }, "message": "Fix Unisoc T618 Chipset Detection (#307)\n\nAdd support for uppercase \"UNISOC T\" prefix in `match_t` function to handle\ndevices like Samsung Galaxy Tab A8 (SM-X205N) that report \"UNISOC T618\"\ninstead of the expected mixed-case \"Unisoc T618\".\n\nThe function now explicitly matches both variants:\n- \"Unisoc T\" (mixed case, existing)\n- \"UNISOC T\" (uppercase, new)\n\nThis ensures proper chipset vendor detection on affected Samsung devices\nwhere the uppercase variant caused match failures.\n\nIncludes test case for \"UNISOC T618\" detection." }, { "commit": "735b2ac12f69aaf408784ed251b9bd6319cfc62d", "tree": "62ac5ec4683862470031e2edbcd40253ffddb6f4", "parents": [ "9a05d3998a5197a31f24b317d86178e81c821fea" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Wed Nov 12 03:16:48 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Nov 12 03:16:48 2025" }, "message": "Rollback Ignore disabled hyperthreads (#340)\n\nFixes #339" }, { "commit": "9a05d3998a5197a31f24b317d86178e81c821fea", "tree": "42d81f4420fd656c866bdb40eff4960d95efb568", "parents": [ "f7b233b2755235c97ef1c2e650820ece1b2869a4" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Tue Nov 11 00:09:48 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 11 00:09:48 2025" }, "message": "Fix windows arm64 build warnings (treated as error) (#332)\n\n- init.c:24:22: error: unused variable \u0027vendor\u0027\n- init-by-logical-sys-info.c:845:11: error: unused variable \u0027converted_chars\u0027\n- init-by-logical-sys-info.c:754:18: error: comparison of array \u0027chip_info-\u003euarchs\u0027 equal to a null pointer" }, { "commit": "f7b233b2755235c97ef1c2e650820ece1b2869a4", "tree": "42d81f4420fd656c866bdb40eff4960d95efb568", "parents": [ "d3a86a813e2bb49d1eb5841ec12e2b135867ab98" ], "author": { "name": "Anthony Shaw", "email": "anthony.p.shaw@gmail.com", "time": "Mon Nov 10 19:00:20 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 10 19:00:20 2025" }, "message": "Implement missing ISA feature flags for ARM64/Windows (#333)\n\n* implement SVE/SVE2 and list out the missing feature flags\n\n* Implement most of the ISA feature flags\n\n* Update notes\n\n* Add more flags to isa info\n\n* Additional flags\n\n* Add conservative values for SVE\n\n* clang formatting\n\n* format headers" }, { "commit": "d3a86a813e2bb49d1eb5841ec12e2b135867ab98", "tree": "1c3a49600adb0216748bb987e83b4e6cc7499b0d", "parents": [ "f01ce870215f9e5d4c32006796994469c5334fd7" ], "author": { "name": "davidbienvenu", "email": "bienvenu@davidbienvenu.org", "time": "Sat Nov 08 00:47:29 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Nov 08 00:47:29 2025" }, "message": "Fix compile warnings in arm/windows (#323)\n\n* Update init-by-logical-sys-info.c\n\nFix compiler warnings\n\n* Update init.c\n\nfix compiler warning\n\n* reformat init.c\n\nattempt to fix clang format errors\n\n* Update init-by-logical-sys-info.c\n\n* Update init-by-logical-sys-info.c\n\nattempt to fix clang format errors" }, { "commit": "f01ce870215f9e5d4c32006796994469c5334fd7", "tree": "e66676eb1ecce5588907b06e79b9f7e847cacc85", "parents": [ "10a95e87a10ae7a7b108bd25ff8a606e53d5af74" ], "author": { "name": "Anthony Shaw", "email": "anthony.p.shaw@gmail.com", "time": "Thu Nov 06 23:01:15 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 06 23:01:15 2025" }, "message": "Add missing ARM-Cortex uarchs (#335)\n\n* Add A720, 725 and X4 identifiers\n\n* Add the X4 successor as well\n\n* Add enumerators" }, { "commit": "10a95e87a10ae7a7b108bd25ff8a606e53d5af74", "tree": "469290f884547169572237b47240962cdf8a32fd", "parents": [ "0d5985d60de2512a2130eede846fc755cb222dc8" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Thu Nov 06 22:52:45 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 06 22:52:45 2025" }, "message": "Update googletest and googlebench deps (#337)\n\n" }, { "commit": "0d5985d60de2512a2130eede846fc755cb222dc8", "tree": "661a39dce3fa3d9e8539b1aafda51eea983655a9", "parents": [ "37b484a5ce3f73f2f37977b86a74698e612936b0" ], "author": { "name": "Alexander Grund", "email": "Flamefire@users.noreply.github.com", "time": "Wed Nov 05 18:10:34 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Nov 05 18:10:34 2025" }, "message": "Ignore disabled hyperthreads (#291)\n\nOnly consider processors with an APIC_ID as valid.\n\nFor processors with Hyperthreads but disabled SMT the APIC_ID will never be set and stays zero for the \"disabled\" threads.\nAmong other inconsistencies this causes the first active thread/processor to be considered \"the same\" as all the disabled ones as they share `APIC_ID\u003d0`\n\nIt also doesn\u0027t make sense to make and decisions based on the APIC_ID if we don\u0027t have any information on it." }, { "commit": "37b484a5ce3f73f2f37977b86a74698e612936b0", "tree": "947877297ee3cc8b5e3063bbc853113c87918cac", "parents": [ "877328f188a3c7d1fa855871a278eb48d530c4c0" ], "author": { "name": "Byoungchan Lee", "email": "byoungchan.lee@gmx.com", "time": "Wed Nov 05 17:51:15 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Nov 05 17:51:15 2025" }, "message": "Fix Samsung Exynos 2000 series chipset detection (#309)\n\n* Fix Samsung Exynos 2000 series chipset detection\n\nAdd support for \"s5e\" prefix pattern matching in `ro.product.board`\nproperty to correctly identify Samsung Exynos 2000 series chipsets.\nThese chipsets use generic identifiers (e.g., `s5e9925`) instead of\nmarketing names like \"Exynos 2200\", but can still be identified and\nmapped to their corresponding models using external resources.\n\nImplements `match_s5e()` function to parse the s5e\u003c4-digit-model\u003e format.\n\n* Clean up whitespace in chipset.c\n\n---------\n\nCo-authored-by: Byoungchan Lee \u003cdaniel.l@hpcnt.com\u003e" }, { "commit": "877328f188a3c7d1fa855871a278eb48d530c4c0", "tree": "f67e0d068d30d0cd26f9efe8cbdbfe3af0d558a4", "parents": [ "8a9210069b5a37dd89ed118a783945502a30a4ae" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Fri Sep 05 22:55:09 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Sep 05 22:55:09 2025" }, "message": "Update CMake minimum requirements to 3.18 (#330)\n\nAs CMake 3.5 support has been removed in cmake-4.x" }, { "commit": "8a9210069b5a37dd89ed118a783945502a30a4ae", "tree": "070437e7039f01f4feb7b7713c0ce6f38bbd9aef", "parents": [ "e414c0446436ed34151de3158d18f8ae32e55d03" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Fri Aug 08 14:49:05 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Aug 08 14:49:05 2025" }, "message": "Add Intel Tremont uarch (#305)\n\nTremont is the e-core (10nm Atom) in Jasperlake,Elkhart Lake, Jacobville and Lakefield\n\nThe family/model are supported by linux\nhttps://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h#L176-L178\nDocumented on wikichip\nhttps://en.wikichip.org/wiki/intel/cpuid#Small_Cores\nSupported by Intel sde -tnt\n\nReordered e-core uarch by generation\ndarkmont is an e-core used in both hybrid laptops and server, so move to ecore\ngracemont model 0xBE is confirmed for Alderlake N, so redocument support\n\nPredecessor Goldmont Plus\nSuccessor Gracemont" }, { "commit": "e414c0446436ed34151de3158d18f8ae32e55d03", "tree": "cd82ad00b8d244cb36675b399c0a8137e9885d8a", "parents": [ "33ed0be77d7767d0e2010e2c3cf972ef36c7c307" ], "author": { "name": "Yuri Khrustalev", "email": "ykhrustalev@users.noreply.github.com", "time": "Tue Aug 05 17:27:21 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Aug 05 17:27:21 2025" }, "message": "Add aarch64 to the windows arm list (#311)\n\n" }, { "commit": "33ed0be77d7767d0e2010e2c3cf972ef36c7c307", "tree": "05920c6ced80e19f2f1ead12b06f77f6f1219b3c", "parents": [ "e4cadd02a8b386c38b84f0a19eddacec3f433baa" ], "author": { "name": "Conan Truong", "email": "Conarnar@users.noreply.github.com", "time": "Thu Jul 24 17:36:24 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 24 17:36:24 2025" }, "message": "Added Emscripten to list of supported systems in CMakeLists.txt (#310)\n\n" }, { "commit": "e4cadd02a8b386c38b84f0a19eddacec3f433baa", "tree": "15eb0f4f823bad997f22133b2f3753ddc5ac7d69", "parents": [ "d7427551d6531037da216d20cd36feb19ed4905f" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Thu Jun 26 04:30:09 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 26 04:30:09 2025" }, "message": "Add Intel Gracemont uarch (#303)\n\n" }, { "commit": "d7427551d6531037da216d20cd36feb19ed4905f", "tree": "2921254f801bd706116cb36996c87a42818d255e", "parents": [ "bac1e85899d8a5663d56a1924aabcaee3de6d8d0" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Tue Jun 10 14:00:39 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 10 14:00:39 2025" }, "message": "Added Willow Cove (#301)\n\n* Added Willow Cove\n\n* Update uarch.c\n\nremoved incomplete modification in naming\n\n* Update cpu-info.c\n\nmoved willow_cove up two lines to be next to sunny_cove\n\n* Update cpuinfo.h\n\nmade the enum consistent with uarch naming following sunny_cove\n\n* Update cpuinfo.h\n\nupdated comments to refer to intel microarchitecture per request to keep consistent." }, { "commit": "bac1e85899d8a5663d56a1924aabcaee3de6d8d0", "tree": "2ae375b51fd33925ae9e0e3f4651f5f92071875d", "parents": [ "6c9eb84ba310f237cea13c478be50102e1128e9b" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jun 09 21:42:28 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 09 21:42:28 2025" }, "message": "Add Intel Darkmont uarch (#298)\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest\n\n* Add Intel Darkmont uarch\n\n- Darkmont is the uarch used in Clearwater Forest" }, { "commit": "6c9eb84ba310f237cea13c478be50102e1128e9b", "tree": "1692e327d01d6ee93d179b94d14100e6dbcb3420", "parents": [ "88b498b9d73acd0b8edb1ec1c31a8fc1cefaf2da" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Tue Jun 03 16:50:51 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 03 16:50:51 2025" }, "message": "Disable neon dot on unknown chipsets on aarch32 (#300)\n\n" }, { "commit": "88b498b9d73acd0b8edb1ec1c31a8fc1cefaf2da", "tree": "5bc2dbc0ed7ead85b497d5516879d8843989266d", "parents": [ "c61fe919607bbc534d7a5a5707bdd7041e72c5ff" ], "author": { "name": "fbarchard", "email": "fbarchard@google.com", "time": "Mon Jun 02 16:54:50 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 02 16:54:50 2025" }, "message": "Add Intel Crestmont uarch (#299)\n\nDarkmont is the uarch used in Sierra Forest\nTested:\nmake cpu-info\nsde -srf -- ./cpu-info" }, { "commit": "c61fe919607bbc534d7a5a5707bdd7041e72c5ff", "tree": "e7b5ddfdaa1868cee79cecddc5efa15f5e96219a", "parents": [ "de0ce7c7251372892e53ce9bc891750d2c9a4fd8" ], "author": { "name": "Kimish Patel", "email": "kimishpatel@fb.com", "time": "Thu May 29 20:26:30 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 29 20:26:30 2025" }, "message": "update apple soc info (#290)\n\n* [WIP] update apple soc info\n\nSummary:\nAdded support for A16, A17, A18, A18 pro. Reg values are found from ncnn and needs validation.\n\nAdditional source\nConstants are taken from https://github.com/apple-oss-distributions/xnu/blob/e3723e1f17661b24996789d8afc084c0c3303b26/osfmk/mach/machine.h#L449\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"[WIP] update apple soc info\"\n\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]\n\n* Update on \"update apple soc info\"\n\n\nSummary:\n\nTest Plan:\n\nReviewers:\n\nSubscribers:\n\nTasks:\n\nTags:\n\n[ghstack-poisoned]" }, { "commit": "de0ce7c7251372892e53ce9bc891750d2c9a4fd8", "tree": "f717b193c93a799c8dab375041f71b2924d17a53", "parents": [ "957b852c5ca521ecb848527a5dc3cc55274aa496" ], "author": { "name": "enh-google", "email": "enh@google.com", "time": "Fri May 23 00:45:30 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri May 23 00:45:30 2025" }, "message": "riscv-hw.c: match kernel type in syscall(). (#292)\n\nsyscall() doesn\u0027t care about these types at all, and the kernel uses cpu_set_t, so we\u0027re better off just removing the cast entirely." }, { "commit": "957b852c5ca521ecb848527a5dc3cc55274aa496", "tree": "ca17fc4c732f43f0d97e488338e19e27cbe397d6", "parents": [ "905918fe9c2a335e99a7092dc028dee927a103a0" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 23:06:17 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 22 23:06:17 2025" }, "message": "[CI] Fix riscv64-in-qemu build (#295)\n\nTried a few things, but looks like all one needs to do is to add `--platform linux/riscv64` flag to `docker run` command" }, { "commit": "905918fe9c2a335e99a7092dc028dee927a103a0", "tree": "e6b8be40051710ca6daab74ba39da8b1edd69da4", "parents": [ "4ab5a589708c6aa9ceb561fb2a6506374107da21" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 21:47:34 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 22 21:47:34 2025" }, "message": "Revert \"cmake: rename duplicate names\" (#296)\n\nReverts pytorch/cpuinfo#284 as it broke Bazel builds" }, { "commit": "4ab5a589708c6aa9ceb561fb2a6506374107da21", "tree": "1cd0b54f3d36f19a6844ddbd6db43deeb99bbdad", "parents": [ "1961df8470beebffa5d82b99b9b9e430436b8d34" ], "author": { "name": "Nikita Shulga", "email": "nshulga@meta.com", "time": "Thu May 22 21:08:46 2025" }, "committer": { "name": "Nikita Shulga", "email": "nshulga@meta.com", "time": "Thu May 22 21:08:46 2025" }, "message": "[CI] Update checkout action to v4\n" }, { "commit": "1961df8470beebffa5d82b99b9b9e430436b8d34", "tree": "208e99d85f47c7298d7619555d3b20200ea9b090", "parents": [ "48a5942c92a3d0590873f1fdfbe1ce3a66412afe" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Thu May 22 15:27:53 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 22 15:27:53 2025" }, "message": "Fix clang format (#294)\n\nRegressions introduced by https://github.com/pytorch/cpuinfo/pull/275 and https://github.com/pytorch/cpuinfo/pull/287" }, { "commit": "48a5942c92a3d0590873f1fdfbe1ce3a66412afe", "tree": "ae00736fc1aaf34057ee88fe2ae580b6ce5c52f5", "parents": [ "b728a23da00ff511275eeaec0122bf28db00fd59", "a8d118ce2824f33c50311cf163c1eb586a8046a5" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu May 22 05:18:27 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 22 05:18:27 2025" }, "message": "Merge pull request #284 from 1480c1/xcode\n\n" }, { "commit": "b728a23da00ff511275eeaec0122bf28db00fd59", "tree": "81ffe159c81447bdbcc32bff5f126d890fc4cd51", "parents": [ "39ea79a3c132f4e678695c579ea9353d2bd29968", "2cd6d6ddb6903a1df42a477940cf306ee9225df8" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu May 22 05:17:38 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 22 05:17:38 2025" }, "message": "Merge pull request #287 from fbarchard/smelen\n\n" }, { "commit": "2cd6d6ddb6903a1df42a477940cf306ee9225df8", "tree": "81ffe159c81447bdbcc32bff5f126d890fc4cd51", "parents": [ "077e89f9b26d2204e7714613b7a42ef21f5d4dc3", "81bc2e04824011c137785f19e80a58cd2a801919" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 20:13:52 2025" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 20:13:52 2025" }, "message": "Merge remote-tracking branch \u0027refs/remotes/origin/smelen\u0027 into smelen\n" }, { "commit": "077e89f9b26d2204e7714613b7a42ef21f5d4dc3", "tree": "81ffe159c81447bdbcc32bff5f126d890fc4cd51", "parents": [ "39ea79a3c132f4e678695c579ea9353d2bd29968" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 00:35:14 2025" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 19:55:22 2025" }, "message": "Add SME vector length detect\n\n- cpuinfo_get_max_arm_sme_length() returns svl vector length in bits\n- Display length of SME vectors in isa-tool\n- Upgrade cmake-linux-riscv64 ubuntu-22.04 runners to ubuntu-24.04\n\nSME may be enabled on cpus that do not have SVE\n" }, { "commit": "81bc2e04824011c137785f19e80a58cd2a801919", "tree": "f6ee41a31576d9c93668dfb92c8af9b9cb6eab98", "parents": [ "39ea79a3c132f4e678695c579ea9353d2bd29968" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 00:35:14 2025" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Fri Mar 28 00:35:14 2025" }, "message": "Add SME vector length detect\n\n- cpuinfo_get_max_arm_sme_length() returns svl vector length in bits\n- Display length of SME vectors in isa-tool\n\nSME may be enabled on cpus that do not have SVE\n" }, { "commit": "39ea79a3c132f4e678695c579ea9353d2bd29968", "tree": "c14f26d49ff0a34b2d3aff8db145d761100dd2f5", "parents": [ "5e3d2445e6a84d9599bee2bf78edbb4d80865e1d", "9d278416b6a5e79d32a618cfeb6893b7652c8b02" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Mar 27 16:18:57 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 27 16:18:57 2025" }, "message": "Merge pull request #285 from fbarchard/sme2\n\nisa-tool display SME and SME2 for arm" }, { "commit": "9d278416b6a5e79d32a618cfeb6893b7652c8b02", "tree": "c14f26d49ff0a34b2d3aff8db145d761100dd2f5", "parents": [ "5e3d2445e6a84d9599bee2bf78edbb4d80865e1d" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Mar 27 09:38:47 2025" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Mar 27 09:38:47 2025" }, "message": "isa-tool display SME and SME2 for arm\n" }, { "commit": "a8d118ce2824f33c50311cf163c1eb586a8046a5", "tree": "1c4e99a97404cc28b8c0d0c26f4cdbbdf3c42208", "parents": [ "5e3d2445e6a84d9599bee2bf78edbb4d80865e1d" ], "author": { "name": "Christopher Degawa", "email": "ccom@randomderp.com", "time": "Wed Feb 12 17:54:08 2025" }, "committer": { "name": "Christopher Degawa", "email": "ccom@randomderp.com", "time": "Fri Mar 21 18:33:53 2025" }, "message": "cmake: rename duplicate names\n\nXcode on macOS cannot handle multiple .c files having the same name as\nit produces an object file like init-\u003chash\u003e.o, but tries to link to\ninit.o\n\nhttps://gitlab.kitware.com/cmake/cmake/-/issues/20501\n\nSigned-off-by: Christopher Degawa \u003cccom@randomderp.com\u003e\n" }, { "commit": "5e3d2445e6a84d9599bee2bf78edbb4d80865e1d", "tree": "f1d21c0c73f853ebe37087c5b176d1b2cd1ddf90", "parents": [ "1a02246bf5af7e9d07c181f995d2a07c07fc6e50", "2624a7e05611cde935da8f57feb558e8f2239bbc" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Fri Mar 21 07:07:22 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 21 07:07:22 2025" }, "message": "Merge pull request #246 from dlenski/main\n\nFor Apple silicon, use machdep.cpu.brand_string in preference to decoding hw.machine" }, { "commit": "1a02246bf5af7e9d07c181f995d2a07c07fc6e50", "tree": "7ff872e131598df7f75cb60a60f635625a16636e", "parents": [ "d6120c73cb6d02f7dac3f2a85f5690fc91f33dbd", "8cb442f4dd0d4ab490aa0d64f9345400c1fca3ed" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Fri Mar 21 06:53:40 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 21 06:53:40 2025" }, "message": "Merge pull request #275 from davidben/func-cast\n\nFix invalid function pointer cast in cpuinfo.c" }, { "commit": "d6120c73cb6d02f7dac3f2a85f5690fc91f33dbd", "tree": "030edbe392e4c2161ad8bfb8b2c70bb002348590", "parents": [ "b73ae6ce38d5dd0b7fe46dbe0a4b5f4bab91c7ea", "48cea9d42553566c7ffda0039a819bb891d3707b" ], "author": { "name": "Eli Uriegas", "email": "1700823+seemethere@users.noreply.github.com", "time": "Thu Mar 20 17:01:21 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Mar 20 17:01:21 2025" }, "message": "Merge pull request #283 from ozanMSFT/users/ozanMSFT/refactor-chip-detection\n\nRefactor windows arm64 for auto cpu detection" }, { "commit": "48cea9d42553566c7ffda0039a819bb891d3707b", "tree": "030edbe392e4c2161ad8bfb8b2c70bb002348590", "parents": [ "7bca5efbabfd8a7f31007a8c120332d629f1645e" ], "author": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Thu Mar 20 09:17:31 2025" }, "committer": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Thu Mar 20 09:17:31 2025" }, "message": "- clang reformat\n" }, { "commit": "7bca5efbabfd8a7f31007a8c120332d629f1645e", "tree": "12104357ffb86ef33027371be479b8f9e7c629f0", "parents": [ "bf43522cb72ec00593237b87c196189fa4a22fe6" ], "author": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Mon Mar 17 08:27:41 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 17 08:27:41 2025" }, "message": "- clang format" }, { "commit": "bf43522cb72ec00593237b87c196189fa4a22fe6", "tree": "89b637fdecae5fa49cff04c31ae7ed0869933e36", "parents": [ "1ba344eb8f4580e5f302dd57453d574ef777617e" ], "author": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Fri Mar 14 18:39:28 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 14 18:39:28 2025" }, "message": "- oryon string" }, { "commit": "1ba344eb8f4580e5f302dd57453d574ef777617e", "tree": "7532dcf2b071ec1f382da3af64d9a79c453863c5", "parents": [ "b73ae6ce38d5dd0b7fe46dbe0a4b5f4bab91c7ea" ], "author": { "name": "Ozan Aydin", "email": "148207261+ozanMSFT@users.noreply.github.com", "time": "Fri Mar 14 12:57:31 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 14 12:57:31 2025" }, "message": "- refactor for auto detection" }, { "commit": "b73ae6ce38d5dd0b7fe46dbe0a4b5f4bab91c7ea", "tree": "c540e99b88e54b400fef9e6f56350283b942e55f", "parents": [ "aaac07ee499895770c89163ce0920ef8bb41ed23", "0bfd15daf1d86f5227affbd2f2a9df1cf7a8296f" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Wed Feb 19 03:41:25 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 19 03:41:25 2025" }, "message": "Merge pull request #277 from 1480c1/pkg-config-name\n\npkg-config: use PROJECT_NAME instead of CMAKE_PROJECT_NAME" }, { "commit": "0bfd15daf1d86f5227affbd2f2a9df1cf7a8296f", "tree": "c540e99b88e54b400fef9e6f56350283b942e55f", "parents": [ "aaac07ee499895770c89163ce0920ef8bb41ed23" ], "author": { "name": "Christopher Degawa", "email": "ccom@randomderp.com", "time": "Tue Feb 11 22:41:28 2025" }, "committer": { "name": "Christopher Degawa", "email": "ccom@randomderp.com", "time": "Tue Feb 11 22:46:22 2025" }, "message": "pkg-config: use PROJECT_NAME instead of CMAKE_PROJECT_NAME\n\n[`PROJECT_NAME`][1] refers to the most recent `project()` call, while\n[`CMAKE_PROJECT_NAME`][2] refers to the top-most `project()` call.\n\nIn the cases where cpuinfo is installed as a standalone project, this is\nperfectly fine and works as intended where the installed pkg-config file\ncontains libcpuinfo as the name. However, if cpuinfo is used as a\nsubproject, such as when using FetchContent, the name of the calling\nproject would be used instead, leading to something like libOuterProject\nrather than libcpuinfo.\n\n[1]: https://cmake.org/cmake/help/latest/variable/PROJECT_NAME.html#variable:PROJECT_NAME\n[2]: https://cmake.org/cmake/help/latest/variable/CMAKE_PROJECT_NAME.html#variable:CMAKE_PROJECT_NAME\n\nSigned-off-by: Christopher Degawa \u003cccom@randomderp.com\u003e\n" }, { "commit": "aaac07ee499895770c89163ce0920ef8bb41ed23", "tree": "a0f04d72edcd6832f435da095d9fa6ce56b89ba4", "parents": [ "8a1772a0c5c447df2d18edf33ec4603a8c9c04a6", "05dd959fa26c7e68fa229495a35f55e06a3b9655" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Mon Feb 03 23:30:36 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 03 23:30:36 2025" }, "message": "Merge pull request #276 from rrwinterton/main\n\n" }, { "commit": "05dd959fa26c7e68fa229495a35f55e06a3b9655", "tree": "a0f04d72edcd6832f435da095d9fa6ce56b89ba4", "parents": [ "501b34bc067edaeae13d695105876bfeb1410c4e" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Mon Feb 03 22:37:06 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 03 22:37:06 2025" }, "message": "Update isa.c\n\nfix the spaces to tab at line 50 to fix indenting issue." }, { "commit": "501b34bc067edaeae13d695105876bfeb1410c4e", "tree": "028dd14cb6164f505d872715d4ddeaf449ccf1e1", "parents": [ "f375d2fdd676bf24d5a8afbff2e7b6186db992d0" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Mon Feb 03 22:10:22 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 03 22:10:22 2025" }, "message": "Update isa.c\n\nUpdate spaces to tabs to fix alignment issues." }, { "commit": "f375d2fdd676bf24d5a8afbff2e7b6186db992d0", "tree": "64a352f065a952dd31c729d6e2faa89451b8600a", "parents": [ "887531f15836fdb42089fd12f53d65e4318f8c04" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Mon Feb 03 22:04:58 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 03 22:04:58 2025" }, "message": "Update isa.c\n\nfixed white spaces changing incorrect tab and space for alignment." }, { "commit": "887531f15836fdb42089fd12f53d65e4318f8c04", "tree": "591f23c105495c8e493070df61c216ff25f60ce6", "parents": [ "afc175a2086ece5e43d6bd01f83a5d6cc320b617" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Fri Jan 31 16:27:04 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 31 16:27:04 2025" }, "message": "Update isa.c\n\nper Frank\u0027s comment of unneeded !! for comparing version number \u003e\u003d 2" }, { "commit": "afc175a2086ece5e43d6bd01f83a5d6cc320b617", "tree": "a9689687c8bd7dc39a53749aa59fe88c23c12d9e", "parents": [ "0c7c32f74c09b765be338b1890f3a2d337ee5273" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Fri Jan 31 06:27:30 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 31 06:27:30 2025" }, "message": "Update isa.c\n\nadded comments to AVX 10 detection for both AVX10.1 and AVX10.2" }, { "commit": "0c7c32f74c09b765be338b1890f3a2d337ee5273", "tree": "3987c25d5825ae3c077766b587357f2afd6d5198", "parents": [ "6fb6cab08eea93b2e028b77aaca2a3b58c42a6f7" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Fri Jan 31 06:17:31 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 31 06:17:31 2025" }, "message": "Update isa.c\n\nThis is the version for the AVX 10 in this case we are testing for AVX 10.2 but it covers the whole 8 bits." }, { "commit": "6fb6cab08eea93b2e028b77aaca2a3b58c42a6f7", "tree": "ffff1f3cd573db0e04e98a08e9e8ee5eddbb1baf", "parents": [ "8a1772a0c5c447df2d18edf33ec4603a8c9c04a6" ], "author": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Fri Jan 31 05:58:07 2025" }, "committer": { "name": "Richard Winterton", "email": "rrwinterton@gmail.com", "time": "Fri Jan 31 05:58:07 2025" }, "message": "Update cpuinfo to support AVX10.2 ISA detection\n" }, { "commit": "8cb442f4dd0d4ab490aa0d64f9345400c1fca3ed", "tree": "d3b9f096d4e521fcf39dcc3866e943206f606722", "parents": [ "8a1772a0c5c447df2d18edf33ec4603a8c9c04a6" ], "author": { "name": "David Benjamin", "email": "davidben@google.com", "time": "Wed Jan 29 22:49:54 2025" }, "committer": { "name": "David Benjamin", "email": "davidben@google.com", "time": "Wed Jan 29 22:49:54 2025" }, "message": "Fix invalid function pointer cast in cpuinfo.c\n\nWhile casting function pointers is allowed in C, the function must\nultimately be called through a pointer with the same type signature as\nthe function itself. Type signature mismatches, even decaying T* to\nvoid* is undefined behavior.\n\nUBSan flags this with -fsanitize\u003dfunction. The easiest way I found to\nrepro this was:\n\n CC\u003dclang-18 CXX\u003dclang++-18 \\\n CFLAGS\u003d\"-fsanitize\u003dfunction -fno-sanitize-recover\u003dfunction\" \\\n CXXFLAGS\u003d\"-fsanitize\u003dfunction -fno-sanitize-recover\u003dfunction\" \\\n cmake -GNinja -B build -DCPUINFO_BUILD_BENCHMARKS\u003dOFF\n\n ninja -C build\n\n ./build/cpu-info\n\nThat gives the following error:\n\n [...]/src/linux/multiline.c:85:11: runtime error: call to function parse_line through pointer to incorrect function type \u0027bool (*)(const char *, const char *, void *, unsigned long)\u0027\n cpuinfo.c: note: parse_line defined here\n SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior [...]/src/linux/multiline.c:85:11\n\nThe fix is fairly straightforward: just keep the function at the type\nsignature the expected, and cast void* instead the function instead.\n" }, { "commit": "8a1772a0c5c447df2d18edf33ec4603a8c9c04a6", "tree": "cd932c46d95041e527ee89d373681650ad2c1824", "parents": [ "ca156f7bc9109c552973414a63d310f76ef0cbf8", "4786c8af141d0e889d4dad7c969ac58366dc61ef" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Fri Jan 10 00:25:44 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 10 00:25:44 2025" }, "message": "Merge pull request #269 from rrwinterton/main\n\nAdded changes to support AVX 10.1 support" }, { "commit": "4786c8af141d0e889d4dad7c969ac58366dc61ef", "tree": "cd932c46d95041e527ee89d373681650ad2c1824", "parents": [ "a404fffd832205b1b0b087947bd50270da75b846" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Wed Jan 08 20:45:17 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 08 20:45:17 2025" }, "message": "Update src/x86/isa.c" }, { "commit": "a404fffd832205b1b0b087947bd50270da75b846", "tree": "1b678a743c0a5f0b4a1fac12fbd6fe5be0b17eae", "parents": [ "9f62392cc7ac476c73b5f25a28d7c3deb029b5ab" ], "author": { "name": "Nikita Shulga", "email": "2453524+malfet@users.noreply.github.com", "time": "Wed Jan 08 20:39:28 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jan 08 20:39:28 2025" }, "message": "Update tools/isa-info.c" }, { "commit": "9f62392cc7ac476c73b5f25a28d7c3deb029b5ab", "tree": "7212d3a8974a2fd1f51507a6aead08df46f356e4", "parents": [ "7215904fd2a29f6771af6b6e81822641fff3ded2" ], "author": { "name": "rrwinterton", "email": "rrwinterton@gmail.com", "time": "Tue Jan 07 23:06:55 2025" }, "committer": { "name": "rrwinterton", "email": "rrwinterton@gmail.com", "time": "Tue Jan 07 23:06:55 2025" }, "message": "change spaces to tab and fix int to bool for RISC.\n" }, { "commit": "2624a7e05611cde935da8f57feb558e8f2239bbc", "tree": "78b9cc5c1550b0955bc50d49fd8ac120f8e21c56", "parents": [ "ca156f7bc9109c552973414a63d310f76ef0cbf8" ], "author": { "name": "Daniel Lenski", "email": "dlenski@gmail.com", "time": "Wed May 22 04:14:36 2024" }, "committer": { "name": "Daniel Lenski", "email": "dlenski@gmail.com", "time": "Thu Jan 02 16:17:17 2025" }, "message": "For Apple silicon, use machdep.cpu.brand_string in preference to decoding hw.machine\n\nThis functionality was implemented in #65 (\"Updated package.name to also\nquery machdep.cpu.brand_string if decode of hw.machine fails\"), but then it was\nomitted from the subsequent #100, probably inadvertently.\n\nAdding that functionality back here, so that the package/device name can be\nshown correctly on recent devices and macOS/iOS versions. I have reversed\nthe order so that `machdep.cpu.brand_string` is checked before attempting to\ndecode `hw.machine`, since the former appears to be more future-proof.\n\nBefore this change, on a recent MacBook Pro:\n\n $ cpu-info\n ...\n Debug (cpuinfo): hw.machine: arm64\n Warning in cpuinfo: parsing \"hw.machine\" failed: Undefined error: 0\n ...\n Packages:\n \t0:\n\nAfter this change:\n\n $ cpu-info\n ...\n Debug (cpuinfo): machdep.cpu.brand_string: Apple M2 Pro\n ...\n Packages:\n \t0: Apple M2 Pro\n" }, { "commit": "7215904fd2a29f6771af6b6e81822641fff3ded2", "tree": "3bb0bdfac912bdca55b2f447b3c1ac4ce4ce2657", "parents": [ "df78d39504e09d47ad332856c8268827ed7e06bc" ], "author": { "name": "richard.winterton", "email": "richard.winterton@intel.com", "time": "Thu Dec 12 01:19:28 2024" }, "committer": { "name": "richard.winterton", "email": "richard.winterton@intel.com", "time": "Thu Dec 12 01:19:28 2024" }, "message": "added check for avx512_regs and hex representation change per request\n" }, { "commit": "df78d39504e09d47ad332856c8268827ed7e06bc", "tree": "edc749649cc8f0280402671293676f950935d4d9", "parents": [ "ca156f7bc9109c552973414a63d310f76ef0cbf8" ], "author": { "name": "richard.winterton", "email": "richard.winterton@intel.com", "time": "Tue Dec 10 01:01:11 2024" }, "committer": { "name": "richard.winterton", "email": "richard.winterton@intel.com", "time": "Tue Dec 10 01:01:11 2024" }, "message": "Added changes to cpuinfo.h, isa.c and isa-info.c\ndetect AVX10.1 ISA\n" }, { "commit": "ca156f7bc9109c552973414a63d310f76ef0cbf8", "tree": "6d47aea51d2c5ba8f845d5e4c5c0edf0e288352c", "parents": [ "cebb0933058d7f181c979afd50601dc311e1bf8c", "45a761d6c4c52e2a5276985c89ee7a2ab15d7006" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Mon Dec 09 16:55:38 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Dec 09 16:55:38 2024" }, "message": "Merge pull request #268 from gonnet/ampere_altra\n\nSet the correct L2 size for Ampere Altra (`aarch64`)." }, { "commit": "45a761d6c4c52e2a5276985c89ee7a2ab15d7006", "tree": "6d47aea51d2c5ba8f845d5e4c5c0edf0e288352c", "parents": [ "5279c5f584168fac841155331d74b62189d5fd2e" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Fri Dec 06 15:20:17 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 06 15:20:17 2024" }, "message": "Fix formatting." }, { "commit": "5279c5f584168fac841155331d74b62189d5fd2e", "tree": "43238664be199851a3368f4a76aed1ab0f8ca810", "parents": [ "41271121c31af0642bb83479bee1001cdea15261" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Fri Dec 06 14:47:59 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 06 14:47:59 2024" }, "message": "Fix formatting" }, { "commit": "41271121c31af0642bb83479bee1001cdea15261", "tree": "d3e7bcdbfea64b2fb296b14a233958932f0f6ffd", "parents": [ "cebb0933058d7f181c979afd50601dc311e1bf8c" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Fri Dec 06 13:39:52 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 06 13:39:52 2024" }, "message": "Set the correct L2 size for Ampere Altra (`aarch64`)." }, { "commit": "cebb0933058d7f181c979afd50601dc311e1bf8c", "tree": "6c4c3b5c0985c38494d946e5f941c0c9e8713fd4", "parents": [ "8df44962d437a0477f07ba6b8843d0b6a48646a4", "68af19c0bce6d95b57ccb4a2784ca1e724fc9a25" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Nov 14 17:03:13 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 14 17:03:13 2024" }, "message": "Merge pull request #266 from fbarchard/zen5\n\n" }, { "commit": "68af19c0bce6d95b57ccb4a2784ca1e724fc9a25", "tree": "6c4c3b5c0985c38494d946e5f941c0c9e8713fd4", "parents": [ "8df44962d437a0477f07ba6b8843d0b6a48646a4" ], "author": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Nov 14 03:00:30 2024" }, "committer": { "name": "Frank Barchard", "email": "fbarchard@google.com", "time": "Thu Nov 14 03:00:30 2024" }, "message": "Detect AMD Zen 5 microarchitecture\n" }, { "commit": "8df44962d437a0477f07ba6b8843d0b6a48646a4", "tree": "2a162fc8605dfc5ae3ff158144c09ddcfca82fa3", "parents": [ "dff2616ddd49122b63abcf44d2c097483b77f861", "5ca8ae1abc8edf76aa5e2a1a722c6a9a20730c3b" ], "author": { "name": "Gregory Comer", "email": "gregoryjcomer@gmail.com", "time": "Tue Oct 29 06:44:11 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 29 06:44:11 2024" }, "message": "Merge pull request #265 from GregoryComer/ums312-dot-disable\n\nDisable neon dot on Unisoc UMS312" }, { "commit": "5ca8ae1abc8edf76aa5e2a1a722c6a9a20730c3b", "tree": "2a162fc8605dfc5ae3ff158144c09ddcfca82fa3", "parents": [ "b3a2db0fba5ea56191730ca4bb7899d496ea21d8" ], "author": { "name": "Gregory James Comer", "email": "gjcomer@meta.com", "time": "Sun Oct 27 04:24:01 2024" }, "committer": { "name": "Gregory James Comer", "email": "gjcomer@meta.com", "time": "Sun Oct 27 05:01:18 2024" }, "message": "Recognize Unisoc UMS, disable neon dot for UMS312\n" }, { "commit": "b3a2db0fba5ea56191730ca4bb7899d496ea21d8", "tree": "5c2c7b64d4c4c7b3c183360b0b0939ae348b14fa", "parents": [ "dff2616ddd49122b63abcf44d2c097483b77f861" ], "author": { "name": "Gregory James Comer", "email": "gjcomer@meta.com", "time": "Sat Oct 26 06:13:26 2024" }, "committer": { "name": "Gregory James Comer", "email": "gjcomer@meta.com", "time": "Sat Oct 26 06:13:26 2024" }, "message": "Add device info for Astro 55R\n" }, { "commit": "dff2616ddd49122b63abcf44d2c097483b77f861", "tree": "b7d5ee6094fccecba971b1a67237960cead15e9f", "parents": [ "1e83a2fdd3102f65c6f1fb602c1b320486218a99", "ff278217bce7da999ad2285fd7e929a1301a30d7" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Tue Oct 22 15:13:39 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 22 15:13:39 2024" }, "message": "Merge pull request #264 from gonnet/sme-for-mach\n\n" }, { "commit": "ff278217bce7da999ad2285fd7e929a1301a30d7", "tree": "b7d5ee6094fccecba971b1a67237960cead15e9f", "parents": [ "f6d058260c06ad6246b4f226895337cb6b7ae11e" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Tue Oct 22 10:29:59 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 22 10:29:59 2024" }, "message": "Remove unrecognized features." }, { "commit": "f6d058260c06ad6246b4f226895337cb6b7ae11e", "tree": "7b160546c7fc0a985b9030f5a795686edc1de284", "parents": [ "973ec72753f8cfabcd50db5a881ea06b92498ae0" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Tue Oct 22 10:18:51 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 22 10:18:51 2024" }, "message": "Fix formatting." }, { "commit": "973ec72753f8cfabcd50db5a881ea06b92498ae0", "tree": "0bcd002a8c05d37cd22db171c5db008bf8874ea4", "parents": [ "1e83a2fdd3102f65c6f1fb602c1b320486218a99" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Tue Oct 22 10:07:53 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 22 10:07:53 2024" }, "message": "Add `sme`/`sme2` detection to `mach/init.c`.\n\nI forgot to add this for `mach` when I did it for `linux` a while back (#262).\r\n\r\nI could not find `hw.optional.arm.FEAT_SME_*` features for all the `sme`-related bits in `cpuinfo_arm_isa`, but I\u0027ve added the ones I could find." }, { "commit": "1e83a2fdd3102f65c6f1fb602c1b320486218a99", "tree": "0171927cae628ee779d366d3fa9e63392dfc087b", "parents": [ "a5ff6df40ce528721cfc310c7ed43946d77404d5", "8f02f6d05164324e39463d16e805caab5bc06d21" ], "author": { "name": "Digant Desai", "email": "digantdesai@meta.com", "time": "Thu Sep 26 15:43:26 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Sep 26 15:43:26 2024" }, "message": "Merge pull request #262 from gonnet/main\n\nAdd `sme2` detection for `aarch64`" }, { "commit": "8f02f6d05164324e39463d16e805caab5bc06d21", "tree": "0171927cae628ee779d366d3fa9e63392dfc087b", "parents": [ "6116dc31c50f8cca1edb9e3fe99ef0341ebc6cf9" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Wed Sep 25 10:45:07 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 25 10:45:07 2024" }, "message": "Update aarch64-isa.c" }, { "commit": "6116dc31c50f8cca1edb9e3fe99ef0341ebc6cf9", "tree": "712b53d8f5054b7d749024a1391c6f8bd7361132", "parents": [ "abec09c93946377df08a901012cb5957dbeac7d1" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Wed Sep 25 10:42:21 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 25 10:42:21 2024" }, "message": "Update cpuinfo.h" }, { "commit": "abec09c93946377df08a901012cb5957dbeac7d1", "tree": "712b53d8f5054b7d749024a1391c6f8bd7361132", "parents": [ "41c6f099195518097311e97400dbc35c476ee987" ], "author": { "name": "Pedro Gonnet", "email": "gonnet@google.com", "time": "Wed Sep 25 10:35:03 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Sep 25 10:35:03 2024" }, "message": "Update cpuinfo.h" } ], "next": "41c6f099195518097311e97400dbc35c476ee987" }