)]}' { "log": [ { "commit": "e5af12796d46cd7788e5f5349da1a27c5f7a8f1a", "tree": "526e8bffa132d868604126a322b62fd3fd22509c", "parents": [ "8772e393f2e6d9e2281415d901d8a17d75ba5e65" ], "author": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Fri Sep 25 12:38:53 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Tue Nov 03 10:22:16 2026" }, "message": "On the road to 1.5.5\n" }, { "commit": "8772e393f2e6d9e2281415d901d8a17d75ba5e65", "tree": "3c7468725fc104c1bb0f2bd02c3d269995a43f7c", "parents": [ "9143ecbe6d25e0f0c3fe95642525138fc1466500" ], "author": { "name": "anematode", "email": "timothy.herchen@gmail.com", "time": "Mon Nov 02 01:09:58 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Mon Nov 02 23:01:22 2026" }, "message": "loopfilter16: x86: optimize shuffles\n" }, { "commit": "9143ecbe6d25e0f0c3fe95642525138fc1466500", "tree": "789f4ea1be3a907c954aedbf22f7213fe0850e4c", "parents": [ "4e3ab21fbbf84a4bd283ea27f96287fcd7c228c1" ], "author": { "name": "az", "email": "azebrowski@mozilla.com", "time": "Thu Oct 29 20:26:56 2026" }, "committer": { "name": "A Zebrowski", "email": "azebrowski@mozilla.com", "time": "Mon Nov 02 18:57:20 2026" }, "message": "decode.c: Reset tile state count when reallocation fails\n" }, { "commit": "4e3ab21fbbf84a4bd283ea27f96287fcd7c228c1", "tree": "ee8178f1b530864dd11a3fbbf41c84dd631a1d35", "parents": [ "097901cf2f193b724dd90b3cf0021fbc8b32c3f3" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Oct 28 17:05:47 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Thu Oct 29 21:09:53 2026" }, "message": "arm: Do unsigned comparisons of pointers in save_tmvs_neon\n\nIn these functions, we compare a pointer with a pointer to the\nend of the array (at the element past the end). It\u0027s possible\n(however very unlikely) that the start of the array is below\n0x7fffffff (for 32 bit) but the end of the array ends up past\n0x80000000. (For 64 bit, the corresponding case is even less\nlikely, due to how the address space usually is laid out.)\n\nTo avoid any potential issues around this, do unsigned comparisons\nfor the pointer values, rather than signed comparisons.\n\nThe issue was caught with an LLM by Mike Sulsenti.\n" }, { "commit": "097901cf2f193b724dd90b3cf0021fbc8b32c3f3", "tree": "bd2e947db3af3be0d7d5560bce92ddd36dce692f", "parents": [ "c6f51c881d80b43830b7c1fff2ba0d48599e8073" ], "author": { "name": "Timothy Herchen", "email": "timothy.herchen@gmail.com", "time": "Thu Oct 29 13:07:29 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Oct 29 13:07:29 2026" }, "message": "loopfilter: Split lf.level into luma and chroma planes\n" }, { "commit": "c6f51c881d80b43830b7c1fff2ba0d48599e8073", "tree": "fb3d996e7d10df65041c15948abf690d769ba037", "parents": [ "e5fd231fe9955a342c60600edb7e0b8777786a6a" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Wed Oct 07 19:34:30 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Tue Oct 27 13:59:56 2026" }, "message": "x86: itx16: optimize idct64 SSE4 and align\n\n- in idct64_mul_16bpc use times 2 dd with movddup loads to eliminate redundant scalar loads (movd) and port-5 shuffle pressure (pshufd) while saving cache footprint\n- align .main_part1 and pad unreachable dead space after its ret to preserve exact byte offsets for all downstream routines\n" }, { "commit": "e5fd231fe9955a342c60600edb7e0b8777786a6a", "tree": "45e4ab26861928ed04f201c62e212e43d65cb55b", "parents": [ "b8b2d726b4b78a2fb174cb45baff441b5969672c" ], "author": { "name": "harbinger markets", "email": "harbingermarkets@gmail.com", "time": "Mon Oct 19 10:25:32 2026" }, "committer": { "name": "James Almer", "email": "jamrial@gmail.com", "time": "Mon Oct 26 20:24:52 2026" }, "message": "obu: fix assert or memory leak after itut-t35 metadata malloc fails\n\nPrevents \"assert(!c-\u003eitut_t35_ref)\" or memory leak. Report was sent\nvia email to security@videolan.org.\n" }, { "commit": "b8b2d726b4b78a2fb174cb45baff441b5969672c", "tree": "a4f6d842c6658b4102a6c71a9d6967df16e3812c", "parents": [ "9433da2daa61bf7029a52b84bafa5daf59cdcc9d" ], "author": { "name": "anematode", "email": "timothy.herchen@gmail.com", "time": "Wed Oct 14 03:37:50 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Oct 24 12:00:13 2026" }, "message": "cdef: hoist some variables in backup2x8\n" }, { "commit": "9433da2daa61bf7029a52b84bafa5daf59cdcc9d", "tree": "3e58b29739632979a4b133a7e34581598063bc2d", "parents": [ "a4958c1e37400eb4bc8a129fa88ab92d89746577" ], "author": { "name": "anematode", "email": "timothy.herchen@gmail.com", "time": "Thu Oct 08 07:29:42 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Oct 21 08:52:19 2026" }, "message": "Remove memset_pow2 dispatch from decomp_tx\n\nZen 5, 1th, CityHall.webm, GCC 16.0.1:\nBase (fps): 93.412 +/- 0.033\nTest (fps): 93.560 +/- 0.033\nPaired delta (test - base): 0.148 +/- 0.038\n" }, { "commit": "a4958c1e37400eb4bc8a129fa88ab92d89746577", "tree": "12e8edc3801f0983246f0bdecb533c38a06eed67", "parents": [ "4c844317b728c1b6e6d86545e6c0bfc88abd119d" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Sun Jun 16 21:22:32 2019" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue Oct 20 16:11:20 2026" }, "message": "arm: Add helpers for debug printing from assembly\n\nThese currently allow printing GPRs, SIMD vectors and memory.\n\nGPRs are printed as signed decimal and unsigned hexadecimal.\n\nSIMD vectors are printed as signed or unsigned decimal, as either\n8, 16 or 32 bit elements.\n\nMemory can be dumped, interpreted as a stored SIMD vector, by\nspecifying a base register and how many vectors to read from that\naddress.\n\nUsage example:\n\n DUMP_SIMD_U8(\"input\", 4, 5) /* Printing v4-v5 as 8 bit unsigned elments */\n DUMP_SIMD_S16(\"sum\", 6, 6) /* Printing v6 as 16 bit signed elments */\n DUMP_GPR(\"w,h\", 4, 5) /* Printing x4-x5 */\n\nWhich prints:\n\n 3450: input:\n v04.16b \u003d { 201, 1, 245, 0, 139, 0, 225, 1, 33, 1, 254, 0, 41, 2, 212, 1 }\n 3451: sum:\n v06.8h \u003d { 20394, -23720, -30625, 32619, -28321, 11312, 30270, 32051 }\n\n 3468: w,h:\n x04 \u003d 16 (0x10)\n x05 \u003d 64 (0x40)\n\n (or)\n\n 3468: w,h:\n x04 \u003d -2401053092612145136 (0xdeadbeef00000010)\n x05 \u003d -2401053092612145148 (0xdeadbeef00000004)\n\nFor inspecting memory:\n\n DUMP_MEM_S16(\"out\", x0, 2) /* Print 2 vectors worth of data from x0, as s16 */\n\nWhich can print:\n\n 3523: out:\n v00.8h \u003d { 12340, 18058, 21605, -10848, -32395, -26577, -15192, 26296 }\n v01.8h \u003d { 1998, 1722, 24014, -17100, 2150, -26619, -23289, -4052 }\n\nUsing these macros requires linking in the debug printing helper\nfunctions, which can be enabled like this (in an already configured\nbuild directory):\n\n meson configure -Dasm_debug\u003dtrue\n" }, { "commit": "4c844317b728c1b6e6d86545e6c0bfc88abd119d", "tree": "dcf9b4d3de9577df3d56e54cdddfb9ecf2dd2180", "parents": [ "9e0d12ef9668a3db279c4d88d5017738e6b8a803" ], "author": { "name": "Christophe Gisquet", "email": "cgisquet@cisco.com", "time": "Mon Oct 19 15:09:00 2026" }, "committer": { "name": "Christophe Gisquet", "email": "christophe.gisquet@gmail.com", "time": "Mon Oct 19 16:57:04 2026" }, "message": "decode: packed lookup for k-th unset bit\n\nReplace the per-bit scan for the k-th unset bit in the priority mask\nwith a precomputed lookup for rank \u003d color_idx - prio_count.\n\nStore each position as its offset from the adjusted rank. At most\nthree priority colors can precede it, so each offset fits in two\nbits, allowing four entries per byte.\n\nClear the two lowest mask bits for indexing and adjust the rank to\nskip newly introduced free colors before the selected position.\nThis reduces the naive 1792-byte rank-by-mask table to 114 bytes.\n\nWhole-decoder speedup vs adapt4/8 (mean of the two Linux CPUs):\n* hiqp: +4.6%\n* loqp: +1.0%\n\nSpeedup is baseline elapsed time / new elapsed time - 1.\n\ndecode.c object-size increase vs adapt4/8: +40 to +208 bytes.\nWindows: +208 bytes; i7-9700: +136 bytes; R7 7775HS: +40 bytes.\n\nVerified all 504 reachable rank/mask pairs against the original loop.\n" }, { "commit": "9e0d12ef9668a3db279c4d88d5017738e6b8a803", "tree": "7f5b23f94c03c5aa34762a6aa28d6a3230133517", "parents": [ "23942c0c77c7bce834255ad35257a33bf5c05a01" ], "author": { "name": "Christophe Gisquet", "email": "cgisquet@cisco.com", "time": "Sat Jul 04 14:50:17 2026" }, "committer": { "name": "Christophe Gisquet", "email": "christophe.gisquet@gmail.com", "time": "Mon Oct 19 16:57:04 2026" }, "message": "decode: use adapt4 for pal_sz 3 and 4\n\nFor pal_sz 3-4 the symbol decode needs n_symbols \u003c\u003d 3, which fits\nin the 4-wide CDF variant and halves the SIMD work vs. adapt8.\nUnlike the pal_sz\u003d\u003d2 bool fast path, ctx 1 is reachable for\npal_sz \u003e\u003d 3 (three distinct neighbour values are possible), so no\ncontext elimination applies; the gain is from the narrower CDF.\n\nWhole-decoder speedup vs parent (mean of both Linux CPUs):\n* hiqp: -0.1%\n* loqp: 0.7%\n\nSpeedup is parent elapsed time / new elapsed time - 1.\n\ndecode.c object-size change vs 52b9d3d3: -464 to +384 bytes.\n" }, { "commit": "23942c0c77c7bce834255ad35257a33bf5c05a01", "tree": "8756e9db44a778161bbf39ab5e39454b7b29e56f", "parents": [ "f422fd459f3eec8de989e41a74fd4ac1c2f632db" ], "author": { "name": "Christophe Gisquet", "email": "cgisquet@cisco.com", "time": "Sat Jul 04 13:51:33 2026" }, "committer": { "name": "Christophe Gisquet", "email": "christophe.gisquet@gmail.com", "time": "Mon Oct 19 16:57:04 2026" }, "message": "decode: use bool decode for binary palettes\n\nWhen pal_sz \u003d\u003d 2 only two palette entries exist, so ctx 1 (which\nrequires 3 distinct neighbours) is unreachable, and the decoded\nrank always either selects the priority value or toggles to the\none other entry. Replace the symbol decode + resolve_pal_color\ncall with a single dav1d_msac_decode_bool_adapt, eliminating the\nCDF renorm overhead of a multi-symbol decode.\n\nWhole-decoder speedup vs parent (mean of both Linux CPUs):\n* hiqp: 4.0%\n* loqp: 1.9%\n\nSpeedup is parent elapsed time / new elapsed time - 1.\n\ndecode.c object-size change vs 52b9d3d3: -464 to +336 bytes.\n" }, { "commit": "f422fd459f3eec8de989e41a74fd4ac1c2f632db", "tree": "1886f28bde13cd0e68fd0bec26745c107dce3120", "parents": [ "d7a83f6e0f9360188a38ceae0883f3d132d87b47" ], "author": { "name": "Christophe Gisquet", "email": "cgisquet@cisco.com", "time": "Sat Jul 04 12:48:02 2026" }, "committer": { "name": "Christophe Gisquet", "email": "christophe.gisquet@gmail.com", "time": "Mon Oct 19 16:57:04 2026" }, "message": "decode: inline palette context and drop array use\n\nReplace order_palette() and its intermediate pal_order[64][8] /\npal_ctx[64] scratch arrays with direct per-pixel computation.\nFor each wavefront pixel, priority candidates and the bitmask of\ntaken palette indices are computed inline, then resolve_pal_color()\nmaps the decoded rank to a palette index in a single pass.\n\nWhole-decoder speedup vs parent (mean of both Linux CPUs):\n* hiqp: 12.7%\n* loqp: 4.8%\n\nSpeedup is parent elapsed time / new elapsed time - 1.\n\ndecode.c object-size change vs 52b9d3d3: -848 to -48 bytes.\n" }, { "commit": "d7a83f6e0f9360188a38ceae0883f3d132d87b47", "tree": "49fd6fdeeea3a2aa63b72f0e6b79669792c7fd35", "parents": [ "99f3354ed0b9b4bf3c7c9347318dbcc522c94af5" ], "author": { "name": "Alejandro Pacheco", "email": "alepacheco99@gmail.com", "time": "Sat Oct 17 08:19:57 2026" }, "committer": { "name": "Alejandro Pacheco", "email": "alepacheco99@gmail.com", "time": "Sat Oct 17 16:07:40 2026" }, "message": "x86: Fix out-of-bounds read in high bitdepth sgr AVX-512 asm\n\nThe horizontal box sum of the 10-bit sgr filters loads 64 bytes of input\nbefore testing for LR_HAVE_RIGHT. On the right-most restoration unit\nthis load can extend up to 76 bytes past the end of the row, which is\nmore than the 64 bytes of padding required by DAV1D_PICTURE_ALIGNMENT.\n\nOnly load the in-bounds part of the input when extending the right edge,\nthe remaining bytes are replaced by the edge pixel anyway.\n" }, { "commit": "99f3354ed0b9b4bf3c7c9347318dbcc522c94af5", "tree": "8af5f8101b00ed1a970dbb6dac5fd091f8bed87e", "parents": [ "7f12cf23560430c02a83e67bb68eec74d93ce5fd" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Thu Oct 01 00:45:50 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Oct 01 23:15:13 2026" }, "message": "x86: mc: avoid redundant blendmask load in warp_affine on SSE4\n" }, { "commit": "7f12cf23560430c02a83e67bb68eec74d93ce5fd", "tree": "4a918332b9a010c04900f51f21de70e5ffba7c69", "parents": [ "9a275d0c9296f2c0ded9d0dd28f99cf22dea2572" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Wed Sep 30 01:13:36 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Sep 30 01:34:15 2026" }, "message": "x86: refmvs: optimize save_tmvs_c using crossplatform memset\n" }, { "commit": "9a275d0c9296f2c0ded9d0dd28f99cf22dea2572", "tree": "aa3a8382b63ace456951b0a16925ba776ad6ed10", "parents": [ "d01a3ff945643de0e4b0f81c86a3db4a39d7f583" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Sat Sep 26 17:52:09 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Tue Sep 29 11:34:11 2026" }, "message": "x86: ipred: optimize SSSE3 smooth_v and smooth_h\n" }, { "commit": "d01a3ff945643de0e4b0f81c86a3db4a39d7f583", "tree": "94ddc179e49451d1dbcfd86ee3824ac50f5716c7", "parents": [ "72942c78ab10c0aa6811cf5954bea0bc005afb6b" ], "author": { "name": "Herman Semenov", "email": "GermanAizek@yandex.ru", "time": "Tue Jun 23 11:49:13 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Mon Sep 28 23:06:20 2026" }, "message": "sgr rotate5_x2: use memmove memcpy SIMD-like optimization\n\nSigned-off-by: Herman Semenoff \u003cGermanAizek@yandex.ru\u003e\n" }, { "commit": "72942c78ab10c0aa6811cf5954bea0bc005afb6b", "tree": "2e9b5476d83bfc2e1f63a43ad388471c46debcdd", "parents": [ "22883c9ca33fda659de661e22f9a703a58d75a73" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Sep 23 09:40:52 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 28 20:51:09 2026" }, "message": "AArch64: Optimize HBD CDEF filters\n\nOptimize the 16bpc Neon CDEF filter kernels.\n\nReplace lane loads with regular scalar/vector loads where possible.\nBesides being cheaper on some cores, this avoids partial-register\ndependencies from lane loads when the destination register is reused.\n\nFor 4-wide filtering, load the two rows independently and combine them\nwith UZP instead of constructing the vector with lane loads. Use\nregular vector loads directly for the 8-wide case.\n\nLoad direction offsets as sign-extended 64-bit values and use them\ndirectly in address calculations. This removes repeated sign extension\nfrom the addressing modes and also allows the offset-table pointer\nupdates to be folded into the loads.\n\nAlso use the already zero-extended 64-bit form of values produced by\n32-bit writes where possible, avoiding redundant UXTW extensions.\n\nRelative run time of cdef_filter_*_16bpc_neon after this patch on some\nCortex CPU cores:\n\n cdef_filter_*_16bpc: 4x4_01 4x4_10 4x4_11\n Cortex-A55: 1.041x 1.036x 1.044x\n Cortex-A510: 0.923x 0.955x 0.926x\n Cortex-A520: 0.921x 0.950x 0.921x\n Cortex-A76: 0.929x 0.961x 0.975x\n Cortex-A78: 0.994x 0.974x 0.979x\n Cortex-A710: 1.005x 1.001x 1.008x\n Cortex-A715: 0.963x 0.955x 0.976x\n Cortex-A720: 0.966x 0.982x 0.987x\n Cortex-A725: 0.957x 0.978x 0.986x\n Cortex-X1: 0.992x 0.983x 0.984x\n Cortex-X2: 0.979x 0.989x 0.976x\n Cortex-X3: 0.991x 0.996x 0.978x\n Cortex-X4: 1.005x 1.000x 1.014x\n Cortex-X925: 1.007x 1.004x 0.991x\n\n cdef_filter_*_16bpc: 4x8_01 4x8_10 4x8_11\n Cortex-A55: 1.044x 1.041x 1.047x\n Cortex-A510: 0.916x 0.945x 0.921x\n Cortex-A520: 0.911x 0.936x 0.918x\n Cortex-A76: 0.928x 0.958x 0.964x\n Cortex-A78: 0.984x 0.979x 0.979x\n Cortex-A710: 0.985x 0.974x 0.988x\n Cortex-A715: 0.948x 0.959x 0.982x\n Cortex-A720: 0.953x 0.960x 0.984x\n Cortex-A725: 0.952x 0.961x 0.982x\n Cortex-X1: 0.960x 0.964x 0.970x\n Cortex-X2: 0.972x 0.914x 0.964x\n Cortex-X3: 0.968x 0.960x 0.978x\n Cortex-X4: 0.965x 0.979x 0.994x\n Cortex-X925: 0.979x 0.984x 0.978x\n\n cdef_filter_*_16bpc: 8x8_01 8x8_10 8x8_11\n Cortex-A55: 0.948x 0.974x 0.959x\n Cortex-A510: 0.986x 1.000x 0.995x\n Cortex-A520: 1.008x 1.014x 1.015x\n Cortex-A76: 0.937x 0.985x 0.982x\n Cortex-A78: 1.000x 0.980x 0.990x\n Cortex-A710: 1.007x 0.988x 0.994x\n Cortex-A715: 0.977x 0.970x 0.986x\n Cortex-A720: 0.980x 0.981x 0.989x\n Cortex-A725: 0.978x 0.984x 0.989x\n Cortex-X1: 0.969x 0.977x 0.983x\n Cortex-X2: 0.981x 0.988x 0.993x\n Cortex-X3: 0.987x 0.989x 0.993x\n Cortex-X4: 0.983x 0.994x 0.995x\n Cortex-X925: 0.986x 0.993x 0.988x\n" }, { "commit": "22883c9ca33fda659de661e22f9a703a58d75a73", "tree": "fe87866409c009501b0f3b5ec69ea629f44d3ed6", "parents": [ "90e00e6ba29852dc5d2cd092636667fb5e61eba6" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 21 12:53:28 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 28 20:51:09 2026" }, "message": "AArch64: Optimize SBD CDEF filters\n\nOptimize the 8bpc Neon CDEF filter kernels.\n\nUse scalar loads and stores where only individual vector lanes are\naccessed, and combine loaded rows with UZP where appropriate. This\nreduces the number of lane load/store instructions and simplifies\naddress generation.\n\nLoad filter offsets directly as sign-extended values and use them in\n64-bit address calculations, avoiding separate extension and pointer\nadjustment instructions.\n\nRelative run time of cdef_filter_*_neon after this patch on some\nCortex CPU cores:\n\n cdef_filter_*_8bpc: 4x4_01 4x4_10 4x4_11\n Cortex-A55: 0.994x 1.002x 0.994x\n Cortex-A510: 0.929x 0.936x 0.932x\n Cortex-A76: 0.941x 0.909x 0.921x\n Cortex-A78: 0.938x 0.935x 0.947x\n Cortex-A715: 0.957x 0.964x 0.942x\n Cortex-A725: 0.950x 0.947x 0.950x\n Cortex-X1: 0.963x 0.945x 0.945x\n Cortex-X3: 0.956x 0.932x 0.953x\n Cortex-X925: 0.943x 0.963x 0.945x\n\n cdef_filter_*_8bpc: 4x8_01 4x8_10 4x8_11\n Cortex-A55: 0.995x 1.001x 0.994x\n Cortex-A510: 0.927x 0.934x 0.929x\n Cortex-A76: 0.899x 0.887x 0.909x\n Cortex-A78: 0.898x 0.871x 0.909x\n Cortex-A715: 0.897x 0.889x 0.910x\n Cortex-A725: 0.883x 0.871x 0.908x\n Cortex-X1: 0.894x 0.883x 0.910x\n Cortex-X3: 0.904x 0.858x 0.899x\n Cortex-X925: 0.872x 0.837x 0.869x\n\n cdef_filter_*_8bpc: 8x8_01 8x8_10 8x8_11\n Cortex-A55: 1.011x 1.011x 1.009x\n Cortex-A510: 0.973x 0.980x 0.965x\n Cortex-A76: 0.927x 0.935x 0.948x\n Cortex-A78: 0.930x 0.902x 0.944x\n Cortex-A715: 0.920x 0.899x 0.935x\n Cortex-A725: 0.916x 0.888x 0.932x\n Cortex-X1: 0.914x 0.867x 0.920x\n Cortex-X3: 0.887x 0.833x 0.905x\n Cortex-X925: 0.822x 0.770x 0.875x\n" }, { "commit": "90e00e6ba29852dc5d2cd092636667fb5e61eba6", "tree": "654c3aa7af409094ce26e70b3b78393760368479", "parents": [ "e74be6294641655d6d96dca02c3a7134d5dc8ccf" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 21 12:52:55 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 28 20:51:09 2026" }, "message": "AArch64: Reschedule CDEF find dir\n\nReschedule the Neon CDEF direction cost calculation to reduce chains of\ndependency and improve instruction scheduling, particularly on Small\nCPU cores.\n\nInterleave independent multiply and multiply-accumulate operations from\nthe different direction cost calculations, and move the pairwise\nreductions out of the cost_alt macro to allow them to be scheduled\nindependently.\n\nAlso replace the structure load of alt_fact with regular vector loads,\nallowing the surrounding unpacking and arithmetic to be scheduled more\nfreely.\n\nRelative run time of cdef_dir_*_neon after this and the prior patch on\nsome Cortex CPU cores:\n\n cdef_dir_*: 8bpc 16bpc\n Cortex-A55: 0.975x 0.970x\n Cortex-A510: 0.921x 0.930x\n Cortex-A520: 0.936x 0.939x\n Cortex-A76: 0.987x 0.993x\n Cortex-A78: 0.973x 0.974x\n Cortex-A710: 0.965x 0.978x\n Cortex-A715: 0.960x 0.965x\n Cortex-A720: 0.965x 0.962x\n Cortex-A725: 0.963x 0.959x\n Cortex-X1: 0.971x 0.963x\n Cortex-X2: 0.977x 0.975x\n Cortex-X3: 0.970x 0.972x\n Cortex-X4: 0.965x 0.962x\n Cortex-X925: 0.942x 0.941x\n" }, { "commit": "e74be6294641655d6d96dca02c3a7134d5dc8ccf", "tree": "4e78025d1ea2fc8fc158acaa7785f68e174bd37d", "parents": [ "22f23d889cd1c4c2b4c1a6cb3e039b5de811d05b" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 21 12:52:26 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 28 20:51:09 2026" }, "message": "AArch64: Optimize CDEF find dir\n\nOptimize the Neon implementation of cdef_find_dir for both 8bpc and\nhigh bitdepth.\n\nCompute pairs of directional costs with pairwise reductions and\ntransfer them directly to GPRs, avoiding separate horizontal reductions\nand the temporary cost array on the stack.\n\nTrack the cost difference for each pair of opposite directions while\nsearching for the best direction. This avoids reloading\ncost[best_dir ^ 4] after the search and removes the associated stack\nstores and loads when calculating the variance.\n\nRelative run time of cdef_dir_*_neon after this patch on some\nCortex CPU cores:\n\n cdef_dir_*: 8bpc 16bpc\n Cortex-A55: 1.056x 1.045x\n Cortex-A510: 0.974x 0.967x\n Cortex-A520: 1.045x 1.043x\n Cortex-A76: 0.987x 0.982x\n Cortex-A78: 0.975x 0.971x\n Cortex-A710: 0.965x 0.971x\n Cortex-A715: 0.982x 0.982x\n Cortex-A720: 0.975x 0.977x\n Cortex-A725: 0.974x 0.974x\n Cortex-X1: 0.966x 0.969x\n Cortex-X2: 0.958x 0.967x\n Cortex-X3: 0.971x 0.968x\n Cortex-X4: 0.984x 0.968x\n Cortex-X925: 0.936x 0.942x\n" }, { "commit": "22f23d889cd1c4c2b4c1a6cb3e039b5de811d05b", "tree": "0e26aae3cc7196b93ffcdf7efd446b93342df5f0", "parents": [ "3e9741c2d39a07a91348047a2b15b036601494bb" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 21 12:55:52 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 28 16:06:00 2026" }, "message": "AArch64: Optimize ipred_filter_8bpc\n\nOptimize the Neon implementation of ipred_filter_8bpc.\n\nReplace lane loads with scalar loads. Lane loads preserve the remaining\nlanes of the destination vector and therefore introduce a loop-carried\ndependency when the same register is reused in successive iterations.\nScalar loads avoid this dependency while also allowing pre-indexed\naddressing to eliminate separate pointer updates.\n\nReduce the use of lane stores as well, since they are relatively\ninefficient on some CPU cores. Prefer scalar or paired stores where the\nrequired elements are already in the low lanes, and use ZIP where this\ncan arrange the output cheaply. Avoid doing this for other elements\nwhen the required extraction or rearrangement would add more\ninstructions than it saves.\n\nReschedule the filter accumulation to reduce its loop-carried critical\npath. Start the MUL/MLA chain with values loaded in the current\niteration and consume values produced by the previous iteration as late\nas possible. This allows OoO cores to overlap the first part of the\naccumulation with the operations producing the loop-carried values,\nexposing more instruction-level parallelism. This scheduling tradeoff\nsignificantly improves performance on wider OoO cores, while causing\nregression on some Small in-order cores.\n\nRemove a redundant UXTW from an address calculation where a preceding\n32-bit write already zero-extends the register to 64 bits.\n\nRelative run time of ipred_filter_*_neon after this patch on some\nCortex CPU cores:\n\n ipred_filter_*_8bpc: w4 w8 w16 w32\n Cortex-A55: 1.053x 1.038x 1.035x 1.051x\n Cortex-A510: 0.908x 0.908x 0.862x 0.851x\n Cortex-A520: 1.014x 1.053x 1.061x 1.053x\n Cortex-A76: 0.702x 0.851x 0.989x 0.918x\n Cortex-A78: 0.697x 0.769x 0.953x 0.698x\n Cortex-A710: 0.698x 0.766x 0.946x 0.692x\n Cortex-A715: 0.723x 0.835x 0.887x 0.712x\n Cortex-A720: 0.737x 0.836x 0.886x 0.710x\n Cortex-A725: 0.702x 0.837x 0.887x 0.709x\n Cortex-X1: 0.665x 0.698x 0.900x 0.665x\n Cortex-X2: 0.626x 0.678x 0.895x 0.630x\n Cortex-X3: 0.639x 0.637x 0.881x 0.626x\n Cortex-X4: 0.567x 0.590x 0.847x 0.636x\n Cortex-X925: 0.675x 0.480x 0.664x 0.567x\n" }, { "commit": "3e9741c2d39a07a91348047a2b15b036601494bb", "tree": "3b0f2da388f20a2316d6a4fca802543f63817207", "parents": [ "99444f13cb6556c22473e3342ba0096b0ef820a3" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Sun Sep 13 11:18:39 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Mon Sep 28 15:36:17 2026" }, "message": "x86: optimize load_tmvs SSE4 SIMD routine\n" }, { "commit": "99444f13cb6556c22473e3342ba0096b0ef820a3", "tree": "6ccf5b64094b1cc9dd4bc3222b63d12c131e8f0d", "parents": [ "173a09ea32a3c3e4391fc9d9a32824b76bf7d496" ], "author": { "name": "Timothy Herchen", "email": "timothy.herchen@gmail.com", "time": "Mon Sep 28 15:27:57 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Mon Sep 28 15:27:57 2026" }, "message": "Improve filling level cache in dav1d_create_lf_mask_intra/dav1d_create_lf_mask_inter\n" }, { "commit": "173a09ea32a3c3e4391fc9d9a32824b76bf7d496", "tree": "d0a2b2e28de6da6da2a495f4ef86320df40358b3", "parents": [ "bf5a8792744ee78c977dfb16503f9156dde6401d" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Fri Aug 28 15:50:43 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Mon Sep 28 11:43:30 2026" }, "message": "x86: optimize loopfilter SIMD routines\n\n- loopfilter (16bpc SSE): Avoid redundant memory loads of [bdmulq]\n- loopfilter (8bpc AVX2): Use vpblendvb instead of pand/pandn/por for p5 in flat16\n" }, { "commit": "bf5a8792744ee78c977dfb16503f9156dde6401d", "tree": "61847c7f7771f432465b97181e21fa5ca8648c74", "parents": [ "5fa003d0785b54b88525a58dd8f504ed8d316d4d" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Thu Sep 24 13:42:59 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Sep 24 17:13:25 2026" }, "message": "x86: ipred: optimize SSSE3 ipred_h\n" }, { "commit": "5fa003d0785b54b88525a58dd8f504ed8d316d4d", "tree": "7e6ea69f54738d86ecdb44b9ba660747e5c7fbcb", "parents": [ "7bebea4748066d843eaefb0bf22d11aeab655760" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Sun Sep 13 11:18:39 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Sep 24 02:19:37 2026" }, "message": "x86: optimize warp_affine SSE4 SIMD routine\n" }, { "commit": "7bebea4748066d843eaefb0bf22d11aeab655760", "tree": "25d892ac47d4f4be1497f7a8c7bcd42e385aa036", "parents": [ "7a82c113ffe9b0f5034d10330e934dcb82eaf769" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Thu Sep 24 00:00:44 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Sep 24 02:02:31 2026" }, "message": "x86/mc_sse: eliminate redundant register moves in MASK macro\n" }, { "commit": "7a82c113ffe9b0f5034d10330e934dcb82eaf769", "tree": "def668991070be5ac6ca96ea33ae2d841617c69e", "parents": [ "854dd6f4cbc4ce92c3d837b12bb0beb5f1ac8336" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Wed Sep 23 23:56:21 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Sep 24 01:22:01 2026" }, "message": "x86/lr_sse/avx2: Optimize Wiener filter tails and SGR 3x3/5x5 cross-lane reductions\n" }, { "commit": "854dd6f4cbc4ce92c3d837b12bb0beb5f1ac8336", "tree": "d373be555310fb7db8fc1a3eb7168a24417cad72", "parents": [ "028ea64cabd3a2e01dd2391d2cefbe3c31870b70" ], "author": { "name": "Timothy Herchen", "email": "timothy.herchen@gmail.com", "time": "Wed Sep 23 14:48:19 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Sep 23 14:48:19 2026" }, "message": "Small optimization in decode_b\n" }, { "commit": "028ea64cabd3a2e01dd2391d2cefbe3c31870b70", "tree": "82c0224936a5092ab873a08d4cb3515f121cc4e9", "parents": [ "9711965b60bb692ae24004659acf61f5c7d9ed61" ], "author": { "name": "Matevz Kovacic", "email": "matevz.celje@gmail.com", "time": "Tue Aug 11 05:20:12 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Sep 23 12:01:53 2026" }, "message": "refmvs: Collapse runs of identical temporal MVs\n\nsave_tmvs() stores one refmvs_temporal_block per 8x8 cell of a coded\nblock, so a 64x64 block writes 64 bit-identical records. The temporal\nscan in dav1d_refmvs_find() walks those cells one at a time and\nre-derives the same projection for each. Across an 8-stream corpus,\n77.5% of all scanned cells are bit-identical to the previously scanned\ncell, ranging from 56.7% to 85.8% per stream. That redundancy is a\nconsequence of the storage granularity, not of the normative scan.\n\nEmit one add_temporal_candidate() per maximal run of identical records,\ncarrying weight 2*n. This is exact rather than approximate:\n\n - the function is pure in (rb-\u003emv, rb-\u003eref) given the loop invariants;\n - an INVALID_MV record is a no-op, so a run of them collapses to one\n no-op. Two such records join the same run whatever their .ref holds,\n and the run test is written to short-circuit before reading it:\n load_tmvs() marks a cell unprojected by writing .mv.n alone, so .ref\n is uninitialized there and add_temporal_candidate() likewise returns\n before touching it;\n - otherwise the first call of a run either merges into entry k or\n inserts at k \u003d last, and every later call of that run recomputes the\n same mv, scans from index 0 and finds the same entry. The first match\n is stable because a repeat never inserts and so never shifts the\n stack. So n identical calls add exactly 2n to mvstack[k].weight,\n whether the run began with a merge or an insert;\n - the stack-full case is a no-op n times and a no-op once;\n - globalmv_ctx is written only by the call at (x, y) \u003d (0, 0), and the\n first run starts there.\n\nWeights only accumulate additively and the sequence of distinct values\nis unchanged, so the final stack contents, order, cnt and every derived\ncontext are bit-identical.\n\nMeasured alone on a 12-stream corpus: +0.68% geometric mean against a\nmeasured A/A noise floor of 0.62%, and nothing at all on streams that\ncode use_ref_frame_mvs \u003d 0, where the scan does not run. Intel Core\ni5-13400, Windows 11, clang-cl 22.1.8, one pinned P-core, AVX2 frozen,\n20 paired samples per cell, counterbalanced A/B ordering. Decoded\noutput is bit-identical to baseline on all 12 corpus streams.\n" }, { "commit": "9711965b60bb692ae24004659acf61f5c7d9ed61", "tree": "ea29c919cfbcd69894c81eabec87f02dc1f3a2a9", "parents": [ "c2e9c9e58ac91b75ed58ec5132eb9f35c8fbb40d" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Fri Aug 28 12:02:11 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Tue Sep 22 21:39:59 2026" }, "message": "x86: Minor optimization to high bitdepth pal_pred AVX2 asm\n\nOptimize 16bpc palette prediction (pal_pred_16bpc) by replacing\nthe two-step pshufd + vpermq with a single vpermd index permutation.\n" }, { "commit": "c2e9c9e58ac91b75ed58ec5132eb9f35c8fbb40d", "tree": "1eae75f5454c6754c81a8b71561263605bd625ce", "parents": [ "409680557206a189cd6e4e53fa2e49a64fa0b17f" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Sep 16 10:47:54 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri Sep 18 06:44:46 2026" }, "message": "AArch64: Simplify MC filter macros using register type aliases\n\nUse the register type renaming helpers to remove redundant arguments\nfrom the MC filter macros.\n\nThe xmx and xmy arguments were only 64-bit aliases of the registers\nalready passed as mx and my. Refer to them directly as x(mx) and x(my)\nwhen they are used as 64-bit values instead.\n\nLikewise, use w(d_strd) and w(s_strd) where the 32-bit forms of the\nstride registers are needed, removing the separate wd_strd and\nws_strd arguments.\n\nThis reduces the number of arguments to filter_*_fn and avoids\nhaving to pass the same physical registers multiple times under\ndifferent register types.\n" }, { "commit": "409680557206a189cd6e4e53fa2e49a64fa0b17f", "tree": "a50438fbfbe0cd72757339a1cf8f94e020c512fc", "parents": [ "cd63c465bc98c3ebf7aabda4bce369177f28f590" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Sep 16 10:46:36 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri Sep 18 06:44:46 2026" }, "message": "AArch64: Use register aliasing macros in load_tmvs_neon\n\nConvert the local GPR aliases in load_tmvs_neon to the new alias_gpr\nhelpers.\n\nThis removes the separate wstride5 alias for the 32-bit view of\nstride5. Use w(stride5) instead wherever the W-register form is\nrequired, while keeping stride5 itself as the X-register alias.\n\nUse unalias_gpr to release all aliases at the end of the function.\n\nThis reduces duplicated register aliases and makes the register width\nused at each instruction explicit.\n" }, { "commit": "cd63c465bc98c3ebf7aabda4bce369177f28f590", "tree": "61fc52e7fed195af8b74690b1611126ecbc50152", "parents": [ "362bc1138228390a0a521ecf3af18b23c6afeb9e" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Sep 16 10:45:30 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri Sep 18 06:44:46 2026" }, "message": "AArch64: Introduce register type renaming macros\n\nAdd helpers for referring to AArch64 registers using a different\nregister type while keeping the same underlying register number.\n\nFor example, x(w0) expands to x0 and w(x0) to w0, while the vector\nvariants allow switching between the b/h/s/d/q/v/z register names.\nThe same syntax also works for registers introduced through .req\naliases.\n\nAdd alias_gpr and alias_vpr helpers to define all corresponding\nregister-type aliases together, along with matching recursive unalias\nhelpers for removing them.\n\nThis allows assembly macros to change the register view explicitly\nwithout requiring separate aliases or knowing whether their argument\nis a physical register name or a local .req alias.\n" }, { "commit": "362bc1138228390a0a521ecf3af18b23c6afeb9e", "tree": "90c8d3e3bd41a21af6bf0c69b9c7c1addd7807e7", "parents": [ "07882a0d2a4268eaf30e02104736d9a246a420a6" ], "author": { "name": "Sungjoon Moon", "email": "sumoon@seoulsaram.org", "time": "Sun Jun 28 15:34:41 2026" }, "committer": { "name": "Sungjoon Moon", "email": "sumoon@seoulsaram.org", "time": "Thu Sep 17 10:16:34 2026" }, "message": "CI: Enable rvv_vl_half_avl option for RVV\n\nhttps://lists.gnu.org/archive/html/qemu-commits/2024-10/msg00009.html\n" }, { "commit": "07882a0d2a4268eaf30e02104736d9a246a420a6", "tree": "1f14aa9e781c4dc22d2dff9cf0739fff5f3f9a02", "parents": [ "e91a97f09782a2a53b546157237dbdbd992c7a0f" ], "author": { "name": "Bogdan Gligorijević", "email": "bogdangligorijevic3@gmail.com", "time": "Tue Jul 09 19:36:43 2024" }, "committer": { "name": "Sungjoon Moon", "email": "sumoon@seoulsaram.org", "time": "Thu Sep 17 10:16:34 2026" }, "message": "CI: setup QEMU to clobber unused vector elements for RVV\n\nWhen mask-agnostic and tail-agnostic mode is set, QEMU\u0027s default\nbehaviour is to still act like the mode is set to\ntail-undisturbed and mask-undisturbed, so a programmer could forget to\nset the mode correctly when using masks or differing vector sizes,\nand CI will still pass in some cases.\n\nThese QEMU_CPU flags toggle the behaviour so that *-agnostic modes\nshould be treated as if they always destroy data,\nmaking it more likely to detect these problems, although QEMU might\nnot respect this fully for all operations at the time of writing.\n" }, { "commit": "e91a97f09782a2a53b546157237dbdbd992c7a0f", "tree": "a0a6554269e64cc6fc9c6a28796a2b1c9da6b8f9", "parents": [ "1aed984b0bef34e1d3333a0b6f4c16c89994c1c1" ], "author": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Tue Sep 15 13:01:31 2026" }, "committer": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Tue Sep 15 13:01:31 2026" }, "message": "riscv/filmgrain: fix SIGSEGV in generate_grain_y\n\nOn VLEN\u003d128, AVL\u003dt3 \u003e VLMAX\u003d64 in the following `vsetvli`. It selects\nvl from: ceil(AVL/2) \u003c\u003d vl \u003c\u003d VLMAX.\n\n1:\n li t3, GRAIN_WIDTH // WIDTH\u003d82\n vsetvli t0, t3, e16, m8, ta, ma\n mv t6, t0\n2: ...\n // some code\n ...\n sw t4, 0(a6)\n addi a6, a6, 4\n addi t6, t6, -2\n bnez t6, 2b\n\nWhen vl is an odd number, the loop doesnt hit zero and t6 goes negative\n. This causes an infinite loop and results in a segmentation fault.\n\nThe next vsetvli also uses the value from t0. If it was odd, it wouldnt\nreflect the logic of \"some code\" that calculates 2 \"[value]\"/Gaussian\nsequence indices per loop.\n\nTo fix it, t0 is incremented by 1 after the first `vsetvli`, if its odd\nNow, it becomes an even number that matches the number of values\ngenerated.\n" }, { "commit": "1aed984b0bef34e1d3333a0b6f4c16c89994c1c1", "tree": "7bf3700767c414dacae125aff25fd816f6a9fd3f", "parents": [ "53dc79d979cbe89f7b6aea4bc0f8ec72a70515cb" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 14 14:24:50 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Sep 14 21:17:22 2026" }, "message": "AArch64: Optimize emu_edge_16bpc_neon\n\nUse pointer comparisons instead of decrementing loop counters in\nemu_edge_16bpc_neon. This allows the CMP + conditional branch pairs to\nbe fused on newer Cortex CPU cores.\n\nUse LDP/STP pairs for the contiguous center copies instead of the\n4-register LD1/ST1 pairs, which provides a small additional performance\nimprovement on several cores. Also duplicate edge samples directly with\nSTP, avoiding the extra vector register copy.\n\nRelative run time of emu_edge_16bpc_neon after this patch on some\nCortex CPU cores:\n\n emu_edge_16bpc: w4 w8 w16 w32 w64\n A55: 0.759x 0.733x 0.817x 0.924x 0.889x\n A510: 0.819x 0.811x 0.909x 1.005x 0.935x\n A520: 0.835x 0.838x 0.896x 0.959x 0.932x\n A76: 0.799x 0.848x 0.956x 0.997x 0.958x\n A78: 0.771x 0.726x 0.816x 0.994x 0.919x\n A710: 0.789x 0.733x 0.793x 0.997x 0.901x\n A715: 0.861x 0.863x 0.912x 0.984x 0.949x\n A720: 0.886x 0.873x 0.919x 0.994x 0.996x\n A725: 0.890x 0.879x 0.919x 0.986x 0.970x\n X1: 0.771x 0.709x 0.829x 0.991x 0.928x\n X2: 0.784x 0.716x 0.785x 0.997x 0.923x\n X3: 0.770x 0.692x 0.779x 1.002x 0.922x\n X4: 0.767x 0.667x 0.770x 0.999x 0.921x\n X925: 0.793x 0.805x 0.737x 1.022x 0.929x\n" }, { "commit": "53dc79d979cbe89f7b6aea4bc0f8ec72a70515cb", "tree": "421e448664ba3462f5021b03a0b392bef79d7d5b", "parents": [ "a34e0685b9111b9eb1d7835ea7bea5b425dced73" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 14 13:37:37 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Mon Sep 14 13:37:37 2026" }, "message": "AArch64: Optimize emu_edge_8bpc_neon\n\nUse pointer comparisons instead of decrementing loop counters in\nemu_edge_8bpc_neon. This allows the CMP + conditional branch pairs to\nbe fused on newer Cortex CPU cores.\n\nAlso use LDP/STP where appropriate for the contiguous 32-byte\nloads/stores.\n\nRelative run time of emu_edge_8bpc_neon after this patch on some\nCortex CPU cores:\n\n emu_edge_8bpc: w4 w8 w16 w32 w64\n A55: 1.003x 1.000x 1.038x 1.009x 1.002x\n A510: 1.005x 1.004x 0.982x 0.999x 0.970x\n A520: 0.957x 0.947x 0.889x 0.942x 0.897x\n A76: 0.986x 1.003x 0.992x 1.011x 0.984x\n A78: 0.966x 0.962x 0.925x 0.955x 0.963x\n A710: 0.947x 0.942x 0.911x 0.941x 0.947x\n A715: 0.888x 0.888x 0.874x 0.874x 0.912x\n A720: 0.900x 0.889x 0.882x 0.892x 0.934x\n A725: 0.903x 0.889x 0.883x 0.885x 0.919x\n X1: 0.967x 0.966x 0.943x 0.969x 0.965x\n X2: 0.965x 0.959x 0.954x 0.981x 0.969x\n X3: 0.969x 0.952x 0.907x 0.970x 0.986x\n X4: 0.980x 0.973x 0.924x 0.978x 1.005x\n X925: 1.004x 1.003x 1.003x 1.000x 1.009x\n" }, { "commit": "a34e0685b9111b9eb1d7835ea7bea5b425dced73", "tree": "472e8afec88ef68731efeacc37d5d644960f2bc8", "parents": [ "060854a5980c94526965124b9761b5c8bfae85df" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Sep 09 09:12:16 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Sep 09 09:32:45 2026" }, "message": "compat: Fix building with newer versions of MSVC\n\nPreviously, MSVC\u0027s preprocessor happily parsed the #if line that\nreferences __has_include_next, and ignored it (and as the start of\nthe line, `defined(__clang__)`, evaluates to zero, it doesn\u0027t make any\ndifference anyway).\n\nSince MSVC around version 19.52.36629 (19.52 is currently in preview,\nnot a stable release), MSVC now errors out on this expression:\n\n ../include/compat/msvc\\stdatomic.h(35): error C7780: function-like macro \u0027__has_include_next\u0027 is not defined\n ../include/compat/msvc\\stdatomic.h(35): fatal error C1017: invalid integer constant expression\n\nAdd a fallback definition of __has_include_next, to let the MSVC\npreprocessor handle this cleanly.\n\nIn practice, this header isn\u0027t ever used with Clang though - if\nstdatomic.h exists, then we don\u0027t add include/compat/msvc at all,\nand we only add this directory if actually compiling with MSVC.\n" }, { "commit": "060854a5980c94526965124b9761b5c8bfae85df", "tree": "602c8f6007ae8b92234ec8303c35b0d178786a22", "parents": [ "aa09a630ef57ee7d9482ffb7ef355a903dbb5302" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Fri Aug 28 11:59:50 2026" }, "committer": { "name": "Victorien Le Couviour--Tuffet", "email": "victorien@videolan.org", "time": "Tue Sep 08 20:06:38 2026" }, "message": "x86: optimize cdef SIMD routines\n\n- cdef (SSSE3): Replace 8-instruction tap clamping sequence with a\n 6-instruction sequence using pw_0xC000, pmaxsw, and pabsw\n" }, { "commit": "aa09a630ef57ee7d9482ffb7ef355a903dbb5302", "tree": "6a1304449c59ecbe7516526863246330946932c0", "parents": [ "52b9d3d3ec525f5a20849145fa0e879d585f4911" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Mon Jun 15 14:48:35 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Sep 03 13:45:29 2026" }, "message": "lf_apply: move out of loop constant-calculated expressions\n" }, { "commit": "52b9d3d3ec525f5a20849145fa0e879d585f4911", "tree": "64300223845e2fbd425bdd95b24e21ee67209572", "parents": [ "54706fc6bc0cdecab7e9593974a4039cc038fca7" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Thu Jul 09 11:50:09 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri Aug 14 18:04:11 2026" }, "message": "aarch64: Always use PIC versions of the movrel macro\n\nThere is little reason to want to generate non-PIC code on aarch64.\nIn practice most (all?) toolchains generate PIC code by default.\n\nHowever, with MSVC, we don\u0027t get the __pic__ macro defined, which\nwe inspect in Meson (and in asm.S), so we never enabled the PIC\ncodepaths with MSVC/armasm64.\n\nTo simplify the number of configurations, remove the non-PIC\nalternative.\n\nThe checks for PIC in Meson and in asm.S are retained as we still\nmay wish to distinguish between the two cases for 32 bit ARM.\n" }, { "commit": "54706fc6bc0cdecab7e9593974a4039cc038fca7", "tree": "37c883895a0fe6cf3fdf3f975525fe8beefdd9c2", "parents": [ "a749472ff010a6e290929b619b580e75083a8120" ], "author": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Tue Jul 14 06:39:09 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Tue Jul 14 06:39:09 2026" }, "message": "Update NEWS for 1.5.4\n" }, { "commit": "a749472ff010a6e290929b619b580e75083a8120", "tree": "13e1cf01994b9d4bec9be517c0cee427496b0a6a", "parents": [ "07f1214d0e688d199f6176108d5247cb74171236" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Sat Jul 11 01:33:55 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jul 11 12:34:52 2026" }, "message": "check_loop_filter_c: make f1,f2 const int without decl\n\nAffected functions\n- check_loop_filter\n- check_loop_filter_h_sb128y\n- check_loop_filter_v_sb128y\n- check_loop_filter_h_sb128uv\n- check_loop_filter_v_sb128uv\n" }, { "commit": "07f1214d0e688d199f6176108d5247cb74171236", "tree": "72d89b39e7a4072105c10b4aa104b20717fc7e88", "parents": [ "bc37d19e3fd8f87e66cfa3beab0d82df99597e7b" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Thu Jul 09 21:07:16 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Fri Jul 10 18:53:20 2026" }, "message": "AArch64: Simplify some Neon load/store addressing\n\nUse post-indexed loads and stores in a few places where the base\nregister is updated immediately after the memory access.\n\nAlso replace single-structure LD1/ST1 instructions with equivalent\nLDR/STR forms where only one register is accessed.\n\nThis removes a few redundant address update instructions without\nchanging behaviour.\n" }, { "commit": "bc37d19e3fd8f87e66cfa3beab0d82df99597e7b", "tree": "55217c2d9bff03d22ed6a63c6d3f22845dfc9d00", "parents": [ "464180b01c87f5320b6e9aed7a55bc00cbbf5646" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Jul 08 14:57:42 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Fri Jul 10 18:53:20 2026" }, "message": "AArch64: Use ldrel for constant loads\n\nReplace movrel+load sequences with ldrel where the address is used only\nfor a single load.\n\nAlign the affected constant tables to 8/16 bytes so they can be loaded\ndirectly with a single 64/128-bit LDR. The immediate offset of this\ninstruction is scaled by 8/16 bytes, so unaligned tables would require\na different addressing sequence, defeating the purpose of ldrel.\n\nThis reduces the generated .text size by 140 bytes.\n" }, { "commit": "464180b01c87f5320b6e9aed7a55bc00cbbf5646", "tree": "f90075e5122298a11e7e1fee4c84e32384c35c5a", "parents": [ "b9c59a5955d2ec0f53a8b8f926cb0673387bfecb" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Jul 08 14:55:51 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Fri Jul 10 18:52:57 2026" }, "message": "AArch64: Add ldrel macro\n\nIntroduce an ldrel macro that combines address materialization with a\nsingle load from a nearby constant.\n\nUnlike movrel, ldrel is intended only for cases where the address is\nused for a single load. It is limited to non-negative offsets that\nsatisfy the alignment and immediate encoding constraints of the final\nload, allowing shorter code sequences on supported targets while\npreserving the existing platform-specific relocation handling.\n\nMSVC\u0027s armasm64 currently fails to apply a symbol offset in ADRP/ADD/LDR\ninstructions. For ADD instructions, gas-preprocessor fixes this\nimplicitly, but that can\u0027t easily be done with LDR [1, 2].\n\nAdditionally, LDR can\u0027t reference symbols that haven\u0027t been parsed\nyet [3], so we can\u0027t safely use it. Therefore, just use MOVREL+LDR for\nMSVC/armasm64.\n\n[1] https://code.ffmpeg.org/FFmpeg/gas-preprocessor/src/commit/ca93666a02f978ac0801e2ae26eee5a385137fd3/gas-preprocessor.pl#L1043\n[2] https://developercommunity.visualstudio.com/t/armasm64-drops-symbol-offset-in-adrpadd/11118860\n[3] https://developercommunity.visualstudio.com/t/armasm64-ldr-fails-to-reference-later-de/11118851\n" }, { "commit": "b9c59a5955d2ec0f53a8b8f926cb0673387bfecb", "tree": "f4547fd6bac67f52e5f6c67b9150f6489ca9879a", "parents": [ "e7bc8896dd9fc7ee033a0dc9f1d713615634516e" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Jul 06 10:48:42 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Mon Jul 06 10:50:04 2026" }, "message": "arm: Fix code style in asm.S\n" }, { "commit": "e7bc8896dd9fc7ee033a0dc9f1d713615634516e", "tree": "caca424ab92340e460b6276e75fe20cd41622c9c", "parents": [ "eb2219f79f7695c4e4dc17db05d5e00f0a48f9de" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Mon Jun 15 14:53:18 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sun Jul 05 14:16:55 2026" }, "message": "lr_apply: move out of loop constant-calculated expressions\n" }, { "commit": "eb2219f79f7695c4e4dc17db05d5e00f0a48f9de", "tree": "4a889898b2dc3294922059146ac94990abc5ecb7", "parents": [ "5a6bce2c0f69daaa4909db536893d957f82a783c" ], "author": { "name": "Herman Semenov", "email": "GermanAizek@yandex.ru", "time": "Thu Jun 25 20:26:33 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sun Jul 05 12:15:11 2026" }, "message": "ipred_cfl_c: use const for variable dc\n\nSigned-off-by: Herman Semenoff \u003cGermanAizek@yandex.ru\u003e\n" }, { "commit": "5a6bce2c0f69daaa4909db536893d957f82a783c", "tree": "07fcd87c6530c5bc1d3aa704dd9b8998bc16524b", "parents": [ "c150ba6c9b9be0956330a9ddfee33ad88f2b1bc5" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Sun Jul 05 00:36:58 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sun Jul 05 12:00:02 2026" }, "message": "decode: move out of loop constant-calculated expressions\n" }, { "commit": "c150ba6c9b9be0956330a9ddfee33ad88f2b1bc5", "tree": "ad36d4bfe9a5f0ed1dab83f90d813285e2b4e462", "parents": [ "b62f72fc260770efe8dbc2d9a5281190edd94a34" ], "author": { "name": "Mohd Zaid", "email": "mdzaid0205@gmail.com", "time": "Sun Jun 28 06:32:12 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Sun Jun 28 06:32:12 2026" }, "message": "riscv64/filmgrain: Implemented `generate_grain_y` for 8bpc in RVV\n" }, { "commit": "b62f72fc260770efe8dbc2d9a5281190edd94a34", "tree": "12ee7af660c08d6a9d51ee3501cf9ee64d861733", "parents": [ "7de554e025aa4ab4e35930d086188780e805535b" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Fri May 22 22:35:51 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jun 27 06:36:58 2026" }, "message": "riscv: mc: remove some failed experiments/debug code\n" }, { "commit": "7de554e025aa4ab4e35930d086188780e805535b", "tree": "5b9f889e8f1a190973a9e93b228c9d702b5108a8", "parents": [ "29c80ca095e101ea34a4c1be40201c08b3675319" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Fri May 22 22:34:00 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jun 27 06:36:58 2026" }, "message": "riscv: mc: make profiles more detailed\n" }, { "commit": "29c80ca095e101ea34a4c1be40201c08b3675319", "tree": "f7512f9ce6dbf13522a81b92833e7a8f8b5ae825", "parents": [ "f009daed89409f18a923c59ebba7d2825104200c" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Fri May 22 22:32:49 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jun 27 06:36:58 2026" }, "message": "riscv: mc: faster 8tap implementation for mx\u003d\u003d0 \u0026\u0026 my\u003d\u003d0\n" }, { "commit": "f009daed89409f18a923c59ebba7d2825104200c", "tree": "99b03bd263b66c3a0dca0307e1072b6f7bfa3b52", "parents": [ "97c431bddb57ff9d76893f99831683b3818fd213" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Wed May 20 19:16:14 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jun 27 06:36:58 2026" }, "message": "riscv: mc: add 6tap optimization for non-sharp filters\n" }, { "commit": "97c431bddb57ff9d76893f99831683b3818fd213", "tree": "f82b8cd86dff9f33af9fee05ca6b303ee199a7d8", "parents": [ "77ef66354d76a3c8aa4b11cde8093294fce23b0f" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Fri May 15 18:15:07 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Sat Jun 27 06:36:58 2026" }, "message": "Implement prep_8tap_c and put_8tap_c in RISC-V assembly\n\nmct_8tap_* (i.e. prep_8tap) on Spacemit K1:\n name ticks +/- stddev time (nanoseconds) (vs ref)\n nop: 13.7 +/- 0.5 7.4 ns +/- 0.6\n mct_8tap_regular_w4_0_8bpc_c: 247.1 +/- 25.3 133.6 ns +/- 16.6\n mct_8tap_regular_w4_0_8bpc_rvv: 183.7 +/- 20.7 99.3 ns +/- 13.2 ( 1.31x)\n mct_8tap_regular_w4_h_8bpc_c: 1210.2 +/- 65.5 654.4 ns +/- 57.5\n mct_8tap_regular_w4_h_8bpc_rvv: 395.5 +/- 31.6 213.9 ns +/- 22.7 ( 3.02x)\n mct_8tap_regular_w4_hv_8bpc_c: 3156.1 +/- 110.0 1706.6 ns +/- 131.6\n mct_8tap_regular_w4_hv_8bpc_rvv: 1019.4 +/- 55.8 551.2 ns +/- 48.6 ( 3.08x)\n mct_8tap_regular_w4_v_8bpc_c: 1242.1 +/- 59.2 671.7 ns +/- 56.4\n mct_8tap_regular_w4_v_8bpc_rvv: 683.4 +/- 47.3 369.6 ns +/- 36.3 ( 1.80x)\n mct_8tap_regular_w8_0_8bpc_c: 511.9 +/- 30.9 276.8 ns +/- 25.4\n mct_8tap_regular_w8_0_8bpc_rvv: 220.9 +/- 19.3 119.4 ns +/- 13.4 ( 2.28x)\n mct_8tap_regular_w8_h_8bpc_c: 3189.3 +/- 105.6 1724.6 ns +/- 131.6\n mct_8tap_regular_w8_h_8bpc_rvv: 810.5 +/- 45.7 438.3 ns +/- 39.2 ( 3.91x)\n mct_8tap_regular_w8_hv_8bpc_c: 7545.8 +/- 165.9 4080.3 ns +/- 294.0\n mct_8tap_regular_w8_hv_8bpc_rvv: 1811.2 +/- 76.1 979.4 ns +/- 79.1 ( 4.15x)\n mct_8tap_regular_w8_v_8bpc_c: 3236.9 +/- 100.5 1750.3 ns +/- 132.0\n mct_8tap_regular_w8_v_8bpc_rvv: 929.4 +/- 45.5 502.6 ns +/- 42.6 ( 3.47x)\n mct_8tap_regular_w16_0_8bpc_c: 1216.4 +/- 49.1 657.7 ns +/- 52.5\n mct_8tap_regular_w16_0_8bpc_rvv: 298.3 +/- 21.2 161.3 ns +/- 16.1 ( 4.04x)\n mct_8tap_regular_w16_h_8bpc_c: 8650.9 +/- 169.5 4677.9 ns +/- 333.7\n mct_8tap_regular_w16_h_8bpc_rvv: 1121.2 +/- 48.5 606.3 ns +/- 49.4 ( 7.69x)\n mct_8tap_regular_w16_hv_8bpc_c: 19245.5 +/- 252.9 10406.8 ns +/- 726.4\n mct_8tap_regular_w16_hv_8bpc_rvv: 2462.2 +/- 78.2 1331.4 ns +/- 100.8 ( 7.80x)\n mct_8tap_regular_w16_v_8bpc_c: 8734.8 +/- 184.2 4723.3 ns +/- 339.1\n mct_8tap_regular_w16_v_8bpc_rvv: 1304.2 +/- 57.9 705.2 ns +/- 57.8 ( 6.67x)\n mct_8tap_regular_w32_0_8bpc_c: 4306.2 +/- 115.5 2328.5 ns +/- 171.7\n mct_8tap_regular_w32_0_8bpc_rvv: 1005.3 +/- 46.7 543.6 ns +/- 45.2 ( 4.27x)\n mct_8tap_regular_w32_h_8bpc_c: 33608.6 +/- 431.1 18173.5 ns +/- 1267.4\n mct_8tap_regular_w32_h_8bpc_rvv: 4139.9 +/- 108.9 2238.6 ns +/- 164.6 ( 8.11x)\n mct_8tap_regular_w32_hv_8bpc_c: 67451.1 +/- 529.1 36473.5 ns +/- 2515.7\n mct_8tap_regular_w32_hv_8bpc_rvv: 9176.4 +/- 188.4 4962.1 ns +/- 355.4 ( 7.34x)\n mct_8tap_regular_w32_v_8bpc_c: 33667.8 +/- 343.0 18205.5 ns +/- 1261.4\n mct_8tap_regular_w32_v_8bpc_rvv: 5104.6 +/- 133.5 2760.3 ns +/- 202.8 ( 6.59x)\n mct_8tap_regular_w64_0_8bpc_c: 11674.5 +/- 263.6 6312.9 ns +/- 456.1\n mct_8tap_regular_w64_0_8bpc_rvv: 2743.7 +/- 114.5 1483.6 ns +/- 119.6 ( 4.24x)\n mct_8tap_regular_w64_h_8bpc_c: 93827.9 +/- 462.2 50736.5 ns +/- 3485.3\n mct_8tap_regular_w64_h_8bpc_rvv: 11476.6 +/- 255.9 6205.8 ns +/- 447.8 ( 8.17x)\n mct_8tap_regular_w64_hv_8bpc_c: 180208.3 +/- 898.7 97445.8 ns +/- 6694.4\n mct_8tap_regular_w64_hv_8bpc_rvv: 24336.9 +/- 339.9 13159.9 ns +/- 920.7 ( 7.40x)\n mct_8tap_regular_w64_v_8bpc_c: 94153.0 +/- 625.3 50912.3 ns +/- 3504.9\n mct_8tap_regular_w64_v_8bpc_rvv: 13947.6 +/- 255.4 7542.0 ns +/- 535.4 ( 6.75x)\n mct_8tap_regular_w128_0_8bpc_c: 32774.8 +/- 1011.1 17722.6 ns +/- 1335.3\n mct_8tap_regular_w128_0_8bpc_rvv: 9312.7 +/- 298.8 5035.8 ns +/- 382.1 ( 3.51x)\n mct_8tap_regular_w128_h_8bpc_c: 266659.9 +/- 1728.1 144193.6 ns +/- 9924.4\n mct_8tap_regular_w128_h_8bpc_rvv: 34046.5 +/- 465.2 18410.3 ns +/- 1287.0 ( 7.83x)\n mct_8tap_regular_w128_hv_8bpc_c: 496508.0 +/- 3682.8 268481.7 ns +/- 18505.0\n mct_8tap_regular_w128_hv_8bpc_rvv: 68054.4 +/- 661.6 36799.7 ns +/- 2547.3 ( 7.29x)\n mct_8tap_regular_w128_v_8bpc_c: 266312.9 +/- 1310.6 144006.0 ns +/- 9892.3\n mct_8tap_regular_w128_v_8bpc_rvv: 40538.4 +/- 594.7 21920.7 ns +/- 1537.0 ( 6.57x)\n mct_8tap_sharp_w4_0_8bpc_c: 241.9 +/- 24.6 130.8 ns +/- 16.2\n mct_8tap_sharp_w4_0_8bpc_rvv: 183.3 +/- 20.4 99.1 ns +/- 13.1 ( 1.29x)\n mct_8tap_sharp_w4_h_8bpc_c: 1217.3 +/- 79.8 658.3 ns +/- 62.9\n mct_8tap_sharp_w4_h_8bpc_rvv: 396.5 +/- 30.6 214.4 ns +/- 22.3 ( 3.03x)\n mct_8tap_sharp_w4_hv_8bpc_c: 3190.5 +/- 200.2 1725.2 ns +/- 161.5\n mct_8tap_sharp_w4_hv_8bpc_rvv: 1019.7 +/- 58.1 551.4 ns +/- 49.5 ( 3.11x)\n mct_8tap_sharp_w4_v_8bpc_c: 1243.8 +/- 71.3 672.6 ns +/- 60.5\n mct_8tap_sharp_w4_v_8bpc_rvv: 679.1 +/- 42.7 367.2 ns +/- 34.4 ( 1.82x)\n mct_8tap_sharp_w8_0_8bpc_c: 517.0 +/- 32.8 279.6 ns +/- 26.3\n mct_8tap_sharp_w8_0_8bpc_rvv: 219.9 +/- 18.4 118.9 ns +/- 13.0 ( 2.32x)\n mct_8tap_sharp_w8_h_8bpc_c: 3196.0 +/- 111.6 1728.2 ns +/- 133.3\n mct_8tap_sharp_w8_h_8bpc_rvv: 807.2 +/- 41.7 436.5 ns +/- 37.7 ( 3.94x)\n mct_8tap_sharp_w8_hv_8bpc_c: 7597.1 +/- 251.6 4108.1 ns +/- 313.6\n mct_8tap_sharp_w8_hv_8bpc_rvv: 1816.4 +/- 89.9 982.2 ns +/- 83.5 ( 4.16x)\n mct_8tap_sharp_w8_v_8bpc_c: 3248.5 +/- 128.5 1756.6 ns +/- 139.5\n mct_8tap_sharp_w8_v_8bpc_rvv: 930.1 +/- 47.4 503.0 ns +/- 43.2 ( 3.47x)\n mct_8tap_sharp_w16_0_8bpc_c: 1215.6 +/- 49.8 657.3 ns +/- 52.7\n mct_8tap_sharp_w16_0_8bpc_rvv: 298.7 +/- 21.0 161.5 ns +/- 16.0 ( 4.03x)\n mct_8tap_sharp_w16_h_8bpc_c: 8654.4 +/- 180.4 4679.8 ns +/- 335.6\n mct_8tap_sharp_w16_h_8bpc_rvv: 1120.7 +/- 50.2 606.0 ns +/- 49.8 ( 7.69x)\n mct_8tap_sharp_w16_hv_8bpc_c: 19230.0 +/- 266.5 10398.4 ns +/- 727.3\n mct_8tap_sharp_w16_hv_8bpc_rvv: 2461.3 +/- 84.1 1330.9 ns +/- 102.2 ( 7.79x)\n mct_8tap_sharp_w16_v_8bpc_c: 8716.5 +/- 174.6 4713.4 ns +/- 336.9\n mct_8tap_sharp_w16_v_8bpc_rvv: 1298.1 +/- 56.9 701.9 ns +/- 57.4 ( 6.69x)\n mct_8tap_sharp_w32_0_8bpc_c: 4337.5 +/- 124.4 2345.5 ns +/- 174.6\n mct_8tap_sharp_w32_0_8bpc_rvv: 1005.5 +/- 47.6 543.7 ns +/- 45.5 ( 4.29x)\n mct_8tap_sharp_w32_h_8bpc_c: 33641.5 +/- 430.1 18191.3 ns +/- 1268.5\n mct_8tap_sharp_w32_h_8bpc_rvv: 4144.4 +/- 115.9 2241.1 ns +/- 166.2 ( 8.10x)\n mct_8tap_sharp_w32_hv_8bpc_c: 67427.0 +/- 454.2 36460.5 ns +/- 2510.4\n mct_8tap_sharp_w32_hv_8bpc_rvv: 9148.1 +/- 168.5 4946.7 ns +/- 351.3 ( 7.37x)\n mct_8tap_sharp_w32_v_8bpc_c: 33694.0 +/- 379.3 18219.7 ns +/- 1265.5\n mct_8tap_sharp_w32_v_8bpc_rvv: 5112.8 +/- 138.7 2764.7 ns +/- 204.2 ( 6.58x)\n mct_8tap_sharp_w64_0_8bpc_c: 11731.5 +/- 439.7 6343.7 ns +/- 497.3\n mct_8tap_sharp_w64_0_8bpc_rvv: 2745.6 +/- 118.5 1484.6 ns +/- 120.8 ( 4.26x)\n mct_8tap_sharp_w64_h_8bpc_c: 93834.9 +/- 499.9 50740.3 ns +/- 3487.1\n mct_8tap_sharp_w64_h_8bpc_rvv: 11464.3 +/- 230.3 6199.2 ns +/- 443.2 ( 8.18x)\n mct_8tap_sharp_w64_hv_8bpc_c: 179581.4 +/- 721.3 97106.8 ns +/- 6664.7\n mct_8tap_sharp_w64_hv_8bpc_rvv: 24274.0 +/- 291.4 13125.9 ns +/- 913.4 ( 7.40x)\n mct_8tap_sharp_w64_v_8bpc_c: 94130.9 +/- 594.7 50900.3 ns +/- 3502.5\n mct_8tap_sharp_w64_v_8bpc_rvv: 13973.8 +/- 314.0 7556.2 ns +/- 545.7 ( 6.73x)\n mct_8tap_sharp_w128_0_8bpc_c: 32477.9 +/- 519.4 17562.1 ns +/- 1236.6\n mct_8tap_sharp_w128_0_8bpc_rvv: 9491.2 +/- 405.8 5132.3 ns +/- 416.4 ( 3.41x)\n mct_8tap_sharp_w128_h_8bpc_c: 264537.8 +/- 979.2 143046.1 ns +/- 9815.0\n mct_8tap_sharp_w128_h_8bpc_rvv: 34011.1 +/- 499.9 18391.2 ns +/- 1289.6 ( 7.77x)\n mct_8tap_sharp_w128_hv_8bpc_c: 491981.0 +/- 1432.9 266033.7 ns +/- 18243.3\n mct_8tap_sharp_w128_hv_8bpc_rvv: 67976.9 +/- 761.5 36757.8 ns +/- 2552.9 ( 7.24x)\n mct_8tap_sharp_w128_v_8bpc_c: 265775.7 +/- 945.2 143715.5 ns +/- 9859.8\n mct_8tap_sharp_w128_v_8bpc_rvv: 40519.1 +/- 717.7 21910.3 ns +/- 1552.0 ( 6.56x)\n\nmc_8tap_* (i.e. put_8tap) on Spacemit K1:\n name ticks +/- stddev time (nanoseconds) (vs ref)\n nop: 17.4 +/- 0.6 7.8 ns +/- 0.5\n mc_8tap_regular_w2_0_8bpc_c: 502.4 +/- 23.5 224.2 ns +/- 15.1\n mc_8tap_regular_w2_0_8bpc_rvv: 247.8 +/- 15.4 110.6 ns +/- 8.7 ( 2.01x)\n mc_8tap_regular_w2_h_8bpc_c: 905.8 +/- 39.7 404.3 ns +/- 26.4\n mc_8tap_regular_w2_h_8bpc_rvv: 500.5 +/- 23.5 223.4 ns +/- 15.1 ( 1.80x)\n mc_8tap_regular_w2_hv_8bpc_c: 2243.3 +/- 60.2 1001.2 ns +/- 55.2\n mc_8tap_regular_w2_hv_8bpc_rvv: 1271.5 +/- 42.0 567.5 ns +/- 33.2 ( 1.76x)\n mc_8tap_regular_w2_v_8bpc_c" }, { "commit": "77ef66354d76a3c8aa4b11cde8093294fce23b0f", "tree": "c4ed2308834c5ce56dc5281c844686eb98f1559f", "parents": [ "953c7139a551e222449c972b144aed58432cb78a" ], "author": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Wed Jun 24 11:01:36 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Wed Jun 24 11:01:36 2026" }, "message": "On the road to 1.5.4\n" }, { "commit": "953c7139a551e222449c972b144aed58432cb78a", "tree": "57118bf4f76974d02a3c689b19721884c5dc637b", "parents": [ "ee0255b3ce0d964b0b5b496c7b9a3a3097fcef76" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Mon Jun 22 19:20:54 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Wed Jun 24 10:02:48 2026" }, "message": "CI: Update image\n\n* Adds xxhash so building with it is tested in CI\n* Updates qemu to 11.0.1 to catch some illegal instructions in RVV\n See: https://code.videolan.org/videolan/dav1d/-/merge_requests/1894#note_555609\n" }, { "commit": "ee0255b3ce0d964b0b5b496c7b9a3a3097fcef76", "tree": "3af9ea1ef906cbca44923932896102d144543145", "parents": [ "a717c62dc3163dfaca75e87948ab10267ee64449" ], "author": { "name": "Mohd Zaid", "email": "mdzaid0205@gmail.com", "time": "Sat Jun 20 16:04:01 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Tue Jun 23 12:11:08 2026" }, "message": "riscv64/ipred: Optimize pal_pred 8 and 16 bpc variant on RVV\n\nremoved redundant instructions from cpu to vector co-processor\n" }, { "commit": "a717c62dc3163dfaca75e87948ab10267ee64449", "tree": "274c1cceb8f5f2e2731ae2386c223e945ecdde2c", "parents": [ "14c73c7db38eebfd3202146b76a1ad4df90dd3a2" ], "author": { "name": "Mohd Zaid", "email": "mdzaid0205@gmail.com", "time": "Sat May 16 12:49:21 2026" }, "committer": { "name": "Mohd Zaid", "email": "mdzaid0205@gmail.com", "time": "Mon Jun 22 05:59:10 2026" }, "message": "riscv/ipred: Optimized ipred_v \u0026 ipred_h for 16bpc on RVV\n\nFirst implementation of `ipred_v_16bpc_rvv` used explicit m8 grouping\nchanged it to m1 and m2 depending upon what fits the use case. Used four\nwrite instruction per loop instead of one to utilize available load\nstore units to their maximum.\n\nOptimizaion involves using multiple vector registers independently for\nthe rows and iteration on rows for larger dimensions (32x32) \u0026 (64x64).\n" }, { "commit": "14c73c7db38eebfd3202146b76a1ad4df90dd3a2", "tree": "765a66fee8296f09d3047a2346cf1fc00b79a99c", "parents": [ "c98979434bbef7a8288e13d7fa90af22d6db2073" ], "author": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Jun 17 11:30:27 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Jun 17 11:30:52 2026" }, "message": "cdef: re-add comments accidentally removed in previous commit\n\n(See c9897943.)\n" }, { "commit": "c98979434bbef7a8288e13d7fa90af22d6db2073", "tree": "05471bba34f6ebe0bcbb57ba6388bba069c6040b", "parents": [ "6b30911e2d9ee485894cefb6a2700b91ed822ea6" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@yandex.ru", "time": "Mon Jun 15 14:44:51 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Jun 17 11:21:07 2026" }, "message": "cdef: move out of loop constant-calculated expressions\n" }, { "commit": "6b30911e2d9ee485894cefb6a2700b91ed822ea6", "tree": "c0f91474be984803d440f3a92c048bc7f8a0f499", "parents": [ "bd953801395ad7df7ea94cf635933f1db5fe586e" ], "author": { "name": "Herman Semenoff", "email": "GermanAizek@tutamail.com", "time": "Mon Jun 15 14:40:51 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Jun 17 10:56:15 2026" }, "message": "refmvs: move out of loop constant-calculated expressions\n\nSigned-off-by: Herman Semenoff \u003cGermanAizek@yandex.ru\u003e\n" }, { "commit": "bd953801395ad7df7ea94cf635933f1db5fe586e", "tree": "81fa1d1e8faec095294d57ab017cc85d4623484e", "parents": [ "e9c5800ace888f1f10a66f7ffb8043a9c96d2508" ], "author": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Sat Nov 22 17:40:26 2025" }, "committer": { "name": "Mikołaj Zalewski", "email": "mikolaj@zalewski.pl", "time": "Tue Jun 16 22:14:17 2026" }, "message": "ipred_dc/dc_left/dc_top/dc_128 implementation in RISC-V assembly\n\nResults on Spacemit K1:\n\nBenchmark results:\n name ticks +/- stddev time (nanoseconds) (vs ref)\n nop: 12.1 +/- 0.5 6.2 ns +/- 0.4\n intra_pred_dc_128_w4_8bpc_c: 41.0 +/- 8.8 20.9 ns +/- 4.7\n intra_pred_dc_128_w4_8bpc_rvv: 31.6 +/- 7.8 16.1 ns +/- 4.1 ( 1.17x)\n intra_pred_dc_128_w4_16bpc_c: 90.1 +/- 13.9 46.0 ns +/- 7.7\n intra_pred_dc_128_w8_8bpc_c: 77.1 +/- 10.7 39.4 ns +/- 6.0\n intra_pred_dc_128_w8_8bpc_rvv: 42.0 +/- 7.7 21.5 ns +/- 4.2 ( 1.73x)\n intra_pred_dc_128_w8_16bpc_c: 200.2 +/- 18.8 102.3 ns +/- 11.4\n intra_pred_dc_128_w16_8bpc_c: 170.7 +/- 15.8 87.2 ns +/- 9.6\n intra_pred_dc_128_w16_8bpc_rvv: 58.3 +/- 8.3 29.8 ns +/- 4.6 ( 2.82x)\n intra_pred_dc_128_w16_16bpc_c: 468.1 +/- 28.8 239.1 ns +/- 20.3\n intra_pred_dc_128_w32_8bpc_c: 397.1 +/- 31.8 202.9 ns +/- 20.2\n intra_pred_dc_128_w32_8bpc_rvv: 75.2 +/- 10.7 38.4 ns +/- 5.9 ( 5.09x)\n intra_pred_dc_128_w32_16bpc_c: 932.1 +/- 51.2 476.2 ns +/- 38.1\n intra_pred_dc_128_w64_8bpc_c: 814.2 +/- 55.7 416.0 ns +/- 37.5\n intra_pred_dc_128_w64_8bpc_rvv: 191.3 +/- 21.1 97.7 ns +/- 12.3 ( 4.16x)\n intra_pred_dc_128_w64_16bpc_c: 2088.5 +/- 85.6 1067.0 ns +/- 75.8\n intra_pred_dc_left_w4_8bpc_c: 141.6 +/- 17.5 72.3 ns +/- 10.0\n intra_pred_dc_left_w4_8bpc_rvv: 96.7 +/- 13.7 49.4 ns +/- 7.6 ( 1.41x)\n intra_pred_dc_left_w4_16bpc_c: 197.3 +/- 20.7 100.8 ns +/- 12.2\n intra_pred_dc_left_w8_8bpc_c: 194.0 +/- 17.8 99.1 ns +/- 10.8\n intra_pred_dc_left_w8_8bpc_rvv: 110.6 +/- 13.0 56.5 ns +/- 7.5 ( 1.71x)\n intra_pred_dc_left_w8_16bpc_c: 358.6 +/- 27.8 183.2 ns +/- 17.8\n intra_pred_dc_left_w16_8bpc_c: 310.1 +/- 22.4 158.4 ns +/- 14.7\n intra_pred_dc_left_w16_8bpc_rvv: 130.1 +/- 12.8 66.5 ns +/- 7.6 ( 2.34x)\n intra_pred_dc_left_w16_16bpc_c: 614.8 +/- 34.3 314.1 ns +/- 25.4\n intra_pred_dc_left_w32_8bpc_c: 543.6 +/- 36.0 277.7 ns +/- 24.5\n intra_pred_dc_left_w32_8bpc_rvv: 144.6 +/- 15.1 73.9 ns +/- 8.9 ( 3.68x)\n intra_pred_dc_left_w32_16bpc_c: 1101.4 +/- 57.5 562.7 ns +/- 44.0\n intra_pred_dc_left_w64_8bpc_c: 979.7 +/- 54.1 500.5 ns +/- 40.2\n intra_pred_dc_left_w64_8bpc_rvv: 257.9 +/- 24.1 131.8 ns +/- 14.6 ( 3.74x)\n intra_pred_dc_left_w64_16bpc_c: 2288.0 +/- 114.4 1168.9 ns +/- 89.7\n intra_pred_dc_top_w4_8bpc_c: 124.6 +/- 16.3 63.7 ns +/- 9.2\n intra_pred_dc_top_w4_8bpc_rvv: 89.8 +/- 13.3 45.9 ns +/- 7.4 ( 1.33x)\n intra_pred_dc_top_w4_16bpc_c: 180.8 +/- 20.8 92.3 ns +/- 12.0\n intra_pred_dc_top_w8_8bpc_c: 189.2 +/- 17.7 96.7 ns +/- 10.7\n intra_pred_dc_top_w8_8bpc_rvv: 103.3 +/- 12.4 52.8 ns +/- 7.1 ( 1.78x)\n intra_pred_dc_top_w8_16bpc_c: 319.4 +/- 24.6 163.2 ns +/- 15.8\n intra_pred_dc_top_w16_8bpc_c: 326.4 +/- 22.3 166.7 ns +/- 15.0\n intra_pred_dc_top_w16_8bpc_rvv: 122.8 +/- 12.1 62.7 ns +/- 7.2 ( 2.61x)\n intra_pred_dc_top_w16_16bpc_c: 633.4 +/- 34.2 323.6 ns +/- 25.7\n intra_pred_dc_top_w32_8bpc_c: 621.5 +/- 37.2 317.5 ns +/- 26.6\n intra_pred_dc_top_w32_8bpc_rvv: 137.7 +/- 14.8 70.4 ns +/- 8.6 ( 4.41x)\n intra_pred_dc_top_w32_16bpc_c: 1158.1 +/- 52.6 591.7 ns +/- 43.7\n intra_pred_dc_top_w64_8bpc_c: 1157.5 +/- 59.6 591.4 ns +/- 46.0\n intra_pred_dc_top_w64_8bpc_rvv: 250.4 +/- 25.0 128.0 ns +/- 14.9 ( 4.53x)\n intra_pred_dc_top_w64_16bpc_c: 2428.9 +/- 115.8 1240.9 ns +/- 93.3\n intra_pred_dc_w4_8bpc_c: 198.1 +/- 28.6 101.2 ns +/- 15.9\n intra_pred_dc_w4_8bpc_rvv: 143.8 +/- 20.3 73.5 ns +/- 11.3 ( 1.33x)\n intra_pred_dc_w4_16bpc_c: 238.4 +/- 24.1 121.8 ns +/- 14.3\n intra_pred_dc_w8_8bpc_c: 285.3 +/- 28.8 145.7 ns +/- 17.1\n intra_pred_dc_w8_8bpc_rvv: 157.9 +/- 16.2 80.7 ns +/- 9.6 ( 1.77x)\n intra_pred_dc_w8_16bpc_c: 422.4 +/- 29.7 215.8 ns +/- 19.8\n intra_pred_dc_w16_8bpc_c: 450.9 +/- 31.7 230.3 ns +/- 21.1\n intra_pred_dc_w16_8bpc_rvv: 179.0 +/- 15.3 91.5 ns +/- 9.5 ( 2.48x)\n intra_pred_dc_w16_16bpc_c: 747.0 +/- 37.7 381.7 ns +/- 29.4\n intra_pred_dc_w32_8bpc_c: 774.5 +/- 44.7 395.7 ns +/- 32.5\n intra_pred_dc_w32_8bpc_rvv: 192.7 +/- 17.4 98.5 ns +/- 10.6 ( 3.96x)\n intra_pred_dc_w32_16bpc_c: 1309.4 +/- 58.3 669.0 ns +/- 49.0\n intra_pred_dc_w64_8bpc_c: 1385.0 +/- 77.7 707.6 ns +/- 57.3\n intra_pred_dc_w64_8bpc_rvv: 305.8 +/- 26.4 156.3 ns +/- 16.3 ( 4.46x)\n intra_pred_dc_w64_16bpc_c: 2636.9 +/- 105.3 1347.2 ns +/- 94.9\n" }, { "commit": "e9c5800ace888f1f10a66f7ffb8043a9c96d2508", "tree": "95e370655777cedc70b64630324a0843685e8197", "parents": [ "6d681d5144ac9e85e395f62f8ff8305b6cf8d9f9" ], "author": { "name": "Chris Davis", "email": "chrdavis@microsoft.com", "time": "Thu Jun 11 18:52:56 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Thu Jun 11 18:52:56 2026" }, "message": "Precompute dav1d quantization matrix tables at build time to eliminate CoW costs\n" }, { "commit": "6d681d5144ac9e85e395f62f8ff8305b6cf8d9f9", "tree": "706c5fb472cb819b4d3325bfb9955b3d788567cf", "parents": [ "46e901735541716e18d90d361e311b58ee95a281" ], "author": { "name": "Cameron Cawley", "email": "ccawley2011@gmail.com", "time": "Thu Jun 04 15:51:01 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Wed Jun 10 10:59:12 2026" }, "message": "Replace platform-specific APIs for getting the program name in getopt fallback\n" }, { "commit": "46e901735541716e18d90d361e311b58ee95a281", "tree": "0d791930d8d856e2232aefffaf20821158ebf961", "parents": [ "720adf9b5b8dd27013e7782c898499af8d8599f6" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Sun Jun 07 21:06:40 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Sun Jun 07 21:15:02 2026" }, "message": "subprojects: Update checkasm to v1.2.0\n\nAmong various fixes it no longer installs the checkasm library, header\nfiles and pkgconfig when installing dav1d.\n" }, { "commit": "720adf9b5b8dd27013e7782c898499af8d8599f6", "tree": "dadc7d0305e8c7bd9469e2c835543b4ea6925146", "parents": [ "beda1b3cda8b348d7bb82448e51c954fe773cc20" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue Jun 02 11:52:01 2026" }, "committer": { "name": "Jean-Baptiste Kempf", "email": "jb@videolan.org", "time": "Sun Jun 07 20:36:10 2026" }, "message": "ci: Add -Dtrim_dsp\u003dfalse in a couple of aarch64/arm configurations\n\nFor the \"release\" build configurations, trim_dsp defaults to true,\nwhile it defaults to false for \"debugoptimized\". This means that\nthe configurations with release mode, without -Dtrim_dsp\u003dfalse\nactually run checkasm before.\n\nIn practice, checkasm is covered by later, full-test configurations,\nbut this ensures that we do test it at this stage as well, as\nintended.\n" }, { "commit": "beda1b3cda8b348d7bb82448e51c954fe773cc20", "tree": "9f11184172d49e8ac15fb22ea525ef880810fbee", "parents": [ "62501cc7db378532d7e85ea434b70d57e1ba2cb0" ], "author": { "name": "Nathan E. Egge", "email": "unlord@xiph.org", "time": "Sun Jun 07 06:37:15 2026" }, "committer": { "name": "Nathan E. Egge", "email": "unlord@xiph.org", "time": "Sun Jun 07 06:52:33 2026" }, "message": "riscv64/itx: Match stack allocation of 16x16 itx\n" }, { "commit": "62501cc7db378532d7e85ea434b70d57e1ba2cb0", "tree": "945015597d862bcbba535f653863d237bccf665c", "parents": [ "dbed372b703ef9d31fcfb46fa3f5b68837a58ad1" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed May 20 11:00:46 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue May 26 12:30:26 2026" }, "message": "AArch64: Optimize ipred_smooth_8bpc_neon\n\nOptimize ipred_smooth_8bpc_neon using simpler arithmetic operations and\nthe removal of jump table.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_smooth: w4 w8 w16 w32 w64\nCortex-A55: 1.041x 0.839x 0.705x 0.765x 0.802x\nCortex-A510: 1.055x 0.880x 0.669x 0.694x 0.729x\nCortex-A520: 1.113x 0.922x 0.659x 0.737x 0.783x\nCortex-A76: 0.763x 0.733x 0.608x 0.707x 0.791x\nCortex-A78: 0.840x 0.712x 0.704x 0.748x 0.786x\nCortex-A715: 0.814x 0.655x 0.798x 0.837x 0.858x\nCortex-A725: 0.813x 0.653x 0.791x 0.830x 0.854x\nCortex-X1: 0.825x 0.686x 0.667x 0.729x 0.756x\nCortex-X3: 0.865x 0.617x 0.649x 0.674x 0.688x\nCortex-X925: 0.825x 0.677x 0.641x 0.686x 0.700x\n" }, { "commit": "dbed372b703ef9d31fcfb46fa3f5b68837a58ad1", "tree": "f8813b1f7e11e2aee5c3050324029c59b56bb5f5", "parents": [ "a38236491a865c9b192bf85d7c851ee98f5793ed" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed May 20 11:48:18 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed May 20 11:48:18 2026" }, "message": "AArch64: Optimize ipred_smooth_v_8bpc_neon further\n\nOptimize ipred_smooth_h_8bpc_neon even further using vertical inner\nloop for w \u003e\u003d 16 cases.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_smooth_v: w4 w8 w16 w32 w64\nCortex-A55: 0.985x 0.981x 0.810x 0.873x 0.907x\nCortex-A510: 0.966x 0.951x 0.950x 1.013x 1.047x\nCortex-A520: 0.924x 0.924x 0.890x 0.984x 1.030x\nCortex-A76: 0.978x 1.036x 0.899x 0.919x 0.918x\nCortex-A78: 0.997x 0.993x 0.986x 0.972x 0.983x\nCortex-A710: 1.002x 0.973x 0.984x 0.958x 1.002x\nCortex-A715: 1.073x 1.049x 1.005x 1.018x 1.012x\nCortex-A720: 1.001x 1.004x 0.990x 1.007x 1.008x\nCortex-A725: 1.002x 1.001x 0.985x 1.007x 1.006x\nCortex-X1: 0.996x 1.077x 0.927x 0.962x 0.970x\nCortex-X2: 1.012x 0.989x 0.881x 0.971x 0.981x\nCortex-X3: 1.006x 1.034x 0.841x 0.966x 0.962x\nCortex-X4: 1.020x 1.022x 0.915x 0.964x 0.985x\nCortex-X925: 1.000x 0.947x 0.936x 0.982x 0.996x\n" }, { "commit": "a38236491a865c9b192bf85d7c851ee98f5793ed", "tree": "621ba4ed0325f7c90fc44e9003f4e6c399f19fd1", "parents": [ "1718ff9aded99f0a89f5c7940d6afb8948301e33" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed May 20 11:44:22 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed May 20 11:44:22 2026" }, "message": "AArch64: Optimize ipred_smooth_h_8bpc_neon further\n\nOptimize ipred_smooth_h_8bpc_neon even further using vertical inner\nloop for w \u003e\u003d 16 cases. Reorder instructions in the w \u003d 4 handler for\nSmall CPUs.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_smooth_h: w4 w8 w16 w32 w64\nCortex-A55: 0.964x 1.003x 0.891x 0.979x 1.030x\nCortex-A510: 0.952x 0.936x 0.928x 1.004x 1.050x\nCortex-A520: 0.921x 0.925x 0.921x 0.995x 1.032x\nCortex-A76: 0.993x 1.005x 0.977x 0.995x 0.996x\nCortex-A78: 0.991x 0.998x 1.042x 0.978x 1.015x\nCortex-A710: 1.020x 0.966x 1.015x 1.015x 1.008x\nCortex-A715: 1.026x 1.051x 1.039x 1.007x 1.024x\nCortex-A720: 0.954x 0.999x 1.018x 0.999x 1.020x\nCortex-A725: 0.962x 1.000x 1.018x 1.000x 1.021x\nCortex-X1: 1.019x 0.993x 0.924x 0.983x 0.989x\nCortex-X2: 1.013x 0.991x 0.872x 0.964x 1.023x\nCortex-X3: 1.030x 0.996x 0.840x 0.953x 1.024x\nCortex-X4: 1.026x 1.005x 0.952x 0.970x 0.986x\nCortex-X925: 1.000x 0.980x 0.865x 0.899x 0.892x\n" }, { "commit": "1718ff9aded99f0a89f5c7940d6afb8948301e33", "tree": "2e08f763c405ec67891e2b65c933fa0654617f81", "parents": [ "c85856e36078b874f8f68381db47d01f54767758" ], "author": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Thu Mar 19 17:41:49 2026" }, "committer": { "name": "Ronald S. Bultje", "email": "rsbultje@gmail.com", "time": "Fri May 15 15:40:14 2026" }, "message": "riscv64/ipred_h: Implement ipred_h in RISC-V asm\n" }, { "commit": "c85856e36078b874f8f68381db47d01f54767758", "tree": "fbe92c90d1bbf2a5f73b17ea035733de9a85c6a6", "parents": [ "1cfad6dbca24fa5b4ab4853617e275281c5b8f78" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri May 15 11:24:57 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri May 15 11:24:57 2026" }, "message": "aarch64: Fix a name mismatch in a macro error message\n\nFor the 64 bit assembly, the macro is just named \"sub_sp\", while it\nwas named \"sub_sp_align\" in the 32 bit form.\n" }, { "commit": "1cfad6dbca24fa5b4ab4853617e275281c5b8f78", "tree": "e80085bfe486e2c062ba7d10018ad9e33a426e87", "parents": [ "de223ad6abda14ee2804bd30bbe9317ba322d2fe" ], "author": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Wed Mar 18 14:54:40 2026" }, "committer": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Tue May 12 11:26:56 2026" }, "message": "riscv64/ipred_v: Remove redundent vxrm set instr\n\nIn function ipred_v_8bpc_rvv, rvv instructions vsetvli, vle8.v,\nvse8.v do not use vxrm.\n\nKendryte K230 Before After Delta\n\nintra_pred_v_w4_8bpc_c: 419.2 ( 1.00x) 405.2 ( 1.00x) -3.34%\nintra_pred_v_w4_8bpc_rvv: 56.7 ( 6.88x) 48.5 ( 7.73x) -14.46%\nintra_pred_v_w8_8bpc_c: 772.9 ( 1.00x) 753.3 ( 1.00x) -2.54%\nintra_pred_v_w8_8bpc_rvv: 69.9 (10.54x) 61.5 (11.67x) -12.02%\nintra_pred_v_w16_8bpc_c: 1209.7 ( 1.00x) 1221.9 ( 1.00x) 1.01%\nintra_pred_v_w16_8bpc_rvv: 88.5 (13.25x) 79.4 (14.93x) -10.28%\nintra_pred_v_w32_8bpc_c: 1898.5 ( 1.00x) 1888.9 ( 1.00x) -0.51%\nintra_pred_v_w32_8bpc_rvv: 104.9 (17.49x) 95.3 (19.18x) -9.15%\nintra_pred_v_w64_8bpc_c: 3266.0 ( 1.00x) 3138.6 ( 1.00x) -3.90%\nintra_pred_v_w64_8bpc_rvv: 196.1 (16.24x) 184.6 (16.59x) -5.86%\n\nSpacemiT K1 Before After Delta\n\nintra_pred_v_w4_8bpc_c: 419.2 ( 1.00x) 403.5 ( 1.00x) -3.75%\nintra_pred_v_w4_8bpc_rvv: 56.7 ( 6.88x) 31.9 (11.57x) -43.74%\nintra_pred_v_w8_8bpc_c: 772.9 ( 1.00x) 756.8 ( 1.00x) -2.08%\nintra_pred_v_w8_8bpc_rvv: 69.9 (10.54x) 43.9 (16.39x) -37.20%\nintra_pred_v_w16_8bpc_c: 1209.7 ( 1.00x) 1136.5 ( 1.00x) -6.05%\nintra_pred_v_w16_8bpc_rvv: 88.5 (13.25x) 61.1 (18.00x) -30.96%\nintra_pred_v_w32_8bpc_c: 1898.5 ( 1.00x) 1837.0 ( 1.00x) -3.24%\nintra_pred_v_w32_8bpc_rvv: 104.9 (17.49x) 77.5 (22.93x) -26.12%\nintra_pred_v_w64_8bpc_c: 3266.0 ( 1.00x) 3110.6 ( 1.00x) -4.76%\nintra_pred_v_w64_8bpc_rvv: 196.1 (16.24x) 166.2 (18.28x) -15.25%\n\nBlackhole p100a Before After Delta\n\nintra_pred_v_w4_8bpc_c: 368.5 ( 1.00x) 370.1 ( 1.00x) 0.43%\nintra_pred_v_w4_8bpc_rvv: 36.7 ( 9.37x) 23.7 (13.99x) -35.42%\nintra_pred_v_w8_8bpc_c: 666.6 ( 1.00x) 670.2 ( 1.00x) 0.54%\nintra_pred_v_w8_8bpc_rvv: 44.4 (14.34x) 33.2 (18.92x) -25.23%\nintra_pred_v_w16_8bpc_c: 970.4 ( 1.00x) 971.9 ( 1.00x) 0.15%\nintra_pred_v_w16_8bpc_rvv: 58.5 (16.07x) 48.5 (19.28x) -17.09%\nintra_pred_v_w32_8bpc_c: 1577.3 ( 1.00x) 1575.8 ( 1.00x) -0.10%\nintra_pred_v_w32_8bpc_rvv: 81.5 (18.79x) 65.9 (23.11x) -19.14%\nintra_pred_v_w64_8bpc_c: 2720.1 ( 1.00x) 2724.9 ( 1.00x) 0.18%\nintra_pred_v_w64_8bpc_rvv: 134.9 (19.65x) 91.6 (28.67x) -32.10%\n\nBenchmark results provided by Sungjoon Moon.\n" }, { "commit": "de223ad6abda14ee2804bd30bbe9317ba322d2fe", "tree": "1be8b79fafa9a2529312775b21740c7625df610b", "parents": [ "51b67010e21302d5d233dbb4f1767b704688a41c" ], "author": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Sun May 10 13:58:55 2026" }, "committer": { "name": "Najmus Sakib Afsan", "email": "ns.afsan@proton.me", "time": "Sun May 10 13:58:55 2026" }, "message": "riscv64/cdef: Fix up code style\n\nThe functions of cdef_filter did not use the conventional names and\nthe macros for declarations.\n\nThis commit matches the style used for other archs and adjusts the\nfollowing:\n\n - decl_cdef_fn() macro for declaration\n - dav1d_cdef_filter_wxh as the name\n" }, { "commit": "51b67010e21302d5d233dbb4f1767b704688a41c", "tree": "a760f7ee6b70e3177d16c28eaa8c0fdafef04b4b", "parents": [ "4db1a05aadaa908bfd95516b7fed3e84548c131e" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Fri Apr 24 17:12:06 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 20:18:03 2026" }, "message": "AArch64: Optimize ipred_smooth_v_8bpc_neon\n\nOptimize ipred_smooth_v_8bpc_neon using simpler arithmetic operations\nand the removal of jump table.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_smooth_v: w4 w8 w16 w32 w64\nCortex-A55: 1.025x 0.847x 0.821x 0.830x 0.852x\nCortex-A510: 1.017x 0.923x 0.915x 0.883x 0.840x\nCortex-A520: 1.080x 0.972x 0.999x 0.934x 0.876x\nCortex-A76: 0.818x 0.575x 0.599x 0.723x 0.744x\nCortex-A78: 0.782x 0.571x 0.595x 0.641x 0.685x\nCortex-A715: 0.801x 0.586x 0.593x 0.651x 0.694x\nCortex-A725: 0.801x 0.579x 0.596x 0.649x 0.692x\nCortex-X1: 0.782x 0.560x 0.553x 0.623x 0.682x\nCortex-X3: 0.792x 0.594x 0.526x 0.526x 0.604x\nCortex-X925: 0.757x 0.678x 0.525x 0.554x 0.577x\n" }, { "commit": "4db1a05aadaa908bfd95516b7fed3e84548c131e", "tree": "4ca2246e242cf656d173402d188c2b4a3f20c730", "parents": [ "037430193a2a542301737028aa7f0ea6c3270bae" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Fri Apr 24 17:10:08 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 20:18:03 2026" }, "message": "AArch64: Optimize ipred_smooth_h_8bpc_neon\n\nOptimize ipred_smooth_h_8bpc_neon using simpler arithmetic operations.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_smooth_h: w4 w8 w16 w32 w64\nCortex-A55: 1.015x 0.857x 0.819x 0.835x 0.862x\nCortex-A510: 0.988x 0.860x 0.915x 0.879x 0.837x\nCortex-A520: 0.999x 0.883x 0.967x 0.929x 0.873x\nCortex-A76: 0.804x 0.637x 0.517x 0.573x 0.613x\nCortex-A78: 0.800x 0.586x 0.548x 0.639x 0.640x\nCortex-A715: 0.722x 0.642x 0.563x 0.627x 0.646x\nCortex-A725: 0.710x 0.639x 0.567x 0.622x 0.645x\nCortex-X1: 0.758x 0.570x 0.565x 0.548x 0.557x\nCortex-X3: 0.789x 0.589x 0.528x 0.563x 0.571x\nCortex-X925: 0.855x 0.739x 0.541x 0.551x 0.567x\n" }, { "commit": "037430193a2a542301737028aa7f0ea6c3270bae", "tree": "2e382b3770b946c09d364e27b13eb7c45d149fca", "parents": [ "7b9ab8373eebc33ae32b38f73fc425db311adbbb" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Fri May 01 11:17:10 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 15:32:26 2026" }, "message": "arm: Fix up code style slightly\n\nThe existing code has been written striving to align columns so\nthat the largest register names can be typed, e.g. r10 on ARM\n(and similarly for x10 or q10 on AArch64), or v31.16b for AArch64\nvectors.\n\nFix some cases, where the current forms were clearly\ninconsistent/wrong. Not all cases have been fixed up to match this\nnorm, but some individual ones that were clearly wrong have been\nfixed.\n" }, { "commit": "7b9ab8373eebc33ae32b38f73fc425db311adbbb", "tree": "1d8fa3b1b361d9f6645c4e133be8e08143373fc5", "parents": [ "ac5dfb0a851c32acfa8f0a10fbe91fd390931ef3" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue May 05 19:56:22 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 15:11:16 2026" }, "message": "ci: Update the main CI image\n\nThis version includes llvm-symbolizer, which should improve\nbacktraces in sanitizer builds with Clang.\n" }, { "commit": "ac5dfb0a851c32acfa8f0a10fbe91fd390931ef3", "tree": "ca72aa6e4211e734146001a5b8340b4d70978bb9", "parents": [ "556c5202b489babeee58f2ccf911ff7b1c8dea05" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 10:38:57 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed May 06 11:00:31 2026" }, "message": "examples: Treat SDL2 headers as system headers\n\nThis makes those headers included with -isystem rather than -I,\nwhich makes the compiler skip producing any warnings about them\n(as they\u0027re expected to be out of the user code\u0027s control).\n\nThis avoids warnings with newer versions of the\ndav1d-debian-unstable CI image, warnings (treated as errors in CI)\nlike this:\n\n In file included from /usr/include/SDL2/SDL_config.h:51,\n from /usr/include/SDL2/SDL_stdinc.h:33,\n from /usr/include/SDL2/SDL_main.h:25,\n from /usr/include/SDL2/SDL.h:31,\n from ../examples/dav1dplay.c:33:\n /usr/include/SDL2/SDL_config_unix.h:186:9: error: \u0027HAVE_GETAUXVAL\u0027 redefined [-Werror]\n 186 | #define HAVE_GETAUXVAL 1\n | ^~~~~~~~~~~~~~\n In file included from ../examples/dav1dplay.c:27:\n ./config.h:66:9: note: this is the location of the previous definition\n 66 | #define HAVE_GETAUXVAL 0\n | ^~~~~~~~~~~~~~\n\nRecently, Debian Unstable has switched from providing the\nactual SDL 2 to providing the SDL 2 API through the sdl2-compat\npackage on top of SDL 3.\n\nThe SDL 2 headers expose their full config.h as part of their\ninstalled headers (that the user code ends up including). This\nincludes unnamespaced defines, such as \"#define HAVE_GETAUXVAL 1\".\n\nThis issue hasn\u0027t shown up with the original SDL 2 package in\nDebian, due to a Debian packaging detail. While most SDL 2\nheaders are installed in /usr/include/SDL2 (and user code\nincludes it as \u003cSDL.h\u003e, requiring the build system to include\n/usr/include/SDL2), the Debian packaging has replaced\n/usr/include/SDL2/SDL_config.h with a header that includes\n\u003cSDL2/_real_SDL_config.h\u003e, which then gets resolved in\n/usr/include/x86_64-linux-gnu/SDL2. Due to this being included\nfrom a compiler default system include path\n(/usr/include/x86_64-linux-gnu), no warnings about the header\nwas printed, even though that one also produced the same kind\nof conflicting redefinitions. (We could also avoid the same issue\nby attempting to include \u003cSDL2/SDL.h\u003e instead of \u003cSDL.h\u003e,\navoiding the use of the build system provided include directory,\nresolving that from /usr/include, and having the compiler consider\nit a system header.)\n\nThe sdl2-compat package in Debian doesn\u0027t redirect that header\nin the same way, but includes SDL_config_unix.h in the same\ndirectory in /usr/include/SDL2. Due to this being included\nfrom a user specified -I (as long as it is included as \u003cSDL.h\u003e,\nnot \u003cSDL2/SDL.h\u003e), it\u0027s considered a user header, and warnings\nare printed for it.\n\nIt seems like SDL 3 no longer exposes their config.h headers as\npart of the installed headers.\n\nThe conflict between SDL 2\u0027s config.h\u0027s HAVE_GETAUXVAL and\nour stems from the fact that we only try to detect GETAUXVAL\non architectures where we want to use it (arm/aarch64, loongarch,\nppc or riscv). On x86, where we don\u0027t need it, we don\u0027t try\nto detect it, and set \"#define HAVE_GETAUXVAL 0\" in our\nconfig.h.\n\nTo avoid warnings due to the conflict, we can declare the\nSDL 2 dependency with the argument \"include_type: \u0027system\u0027\",\nwhich should silence any warnings in the SDL headers. This\nMeson feature is available since Meson 0.52.0 (and we currently\nrequire Meson 0.54.0).\n\nAn alternative way to avoid the redefinition conflict would be\nto always try to detect getauxval on all architectures, to make\nour config.h agree with SDL 2\u0027s config headers.\n\nA third (and much more hacky way) around the conflict would be\nto avoid the public SDL headers including the SDL_config header\nby defining \"SDL_config_h_\" before including SDL.h. Doing this\nalso requires manually including a couple more standard headers\nbefore SDL.h (stdint.h, stdio.h, stddef.h).\n" }, { "commit": "556c5202b489babeee58f2ccf911ff7b1c8dea05", "tree": "15f04814fde9e23076e60fc82d8d08edcf31e4ac", "parents": [ "e1bd6f76c29be452cd6f92a9236657db33de79ea" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Sat May 02 22:18:55 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Sun May 03 19:39:01 2026" }, "message": "ci: Add testing on macOS on Apple Silicon too\n" }, { "commit": "e1bd6f76c29be452cd6f92a9236657db33de79ea", "tree": "6bfca8a441a72966f81dbe3d6b42663bf56d898e", "parents": [ "5cfc3832687e3229117203905faf5425ac6bc0d7" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Sun May 03 09:42:39 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Sun May 03 09:42:39 2026" }, "message": "checkasm: Readd a dependency on threads\n\n3a2a874994809a51bc4f9ec5bac51bd6af69767e, which switched to using\nthe checkasm core from the separate checkasm project, removed the\nthread dependency from the checkasm executable, as the checkasm\nlibrary itself has a thread dependency.\n\nHowever, checkasm doesn\u0027t always include that thread dependency,\nit only does that when pthread_setaffinity_np is detected.\n\nThe dav1d object files themselves use pthreads as well, causing\nundefined symbols if checkasm doesn\u0027t link in pthreads.\n\nThis should fix linking on OpenBSD after\n3a2a874994809a51bc4f9ec5bac51bd6af69767e, fixing issue #467.\n" }, { "commit": "5cfc3832687e3229117203905faf5425ac6bc0d7", "tree": "626d031e37fe255146744e832a88dba6cb620722", "parents": [ "727d0f984b76843e00fb2452ea57cfc5f26b2048" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Apr 29 11:46:00 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Apr 29 12:56:01 2026" }, "message": "arm: mc: Optimize prep_neon for the w4/w8 cases\n\nUse alternating registers for immediately sequential loads/stores,\npack two 4 pixel rows into one register.\n\nBefore: Cortex A7 A8 A53 A55 A72 A73 A76\nmct_8tap_regular_w4_0_8bpc_neon: 112.0 68.6 79.7 82.9 45.3 39.4 24.4\nmct_8tap_regular_w8_0_8bpc_neon: 158.2 89.5 108.4 113.4 55.4 53.0 30.0\nAfter:\nmct_8tap_regular_w4_0_8bpc_neon: 89.7 69.9 76.3 85.1 36.2 35.2 25.0\nmct_8tap_regular_w8_0_8bpc_neon: 149.0 92.7 102.6 115.8 56.6 52.8 31.4\n\nThe numbers aren\u0027t entirely consistent, but this is mostly favourable.\n" }, { "commit": "727d0f984b76843e00fb2452ea57cfc5f26b2048", "tree": "e81cc4659778fed869d58dc3e3b0ae902f3afb86", "parents": [ "f995e1fbf9379027367a93aafd2b5711ba76f81e" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Apr 29 10:46:05 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Wed Apr 29 12:56:01 2026" }, "message": "arm: mc: Fix a comment typo\n\nThis seems to be right in all the other similar places\n(arm/64/mc.S, arm/32/mc16.S and arm/64/mc16.S).\n" }, { "commit": "f995e1fbf9379027367a93aafd2b5711ba76f81e", "tree": "b2120dfac345eff458035d58d348a71008b81ee8", "parents": [ "c0f2fe3135e2f193e31089ff013f628b01aa8d21" ], "author": { "name": "Victorien Le Couviour--Tuffet", "email": "victorien@videolan.org", "time": "Mon Apr 27 18:51:25 2026" }, "committer": { "name": "Victorien Le Couviour--Tuffet", "email": "victorien@videolan.org", "time": "Mon Apr 27 19:09:28 2026" }, "message": "threading: Schedule TILE tasks for all passes at once\n\nCloses #465.\n" }, { "commit": "c0f2fe3135e2f193e31089ff013f628b01aa8d21", "tree": "f453d2b1d39086c691a28412bcd1a173c545e44b", "parents": [ "c5726277ffa8764665ea08f865e46912a41f2309" ], "author": { "name": "Henrik Gramner", "email": "gramner@twoorioles.com", "time": "Thu Apr 16 14:20:25 2026" }, "committer": { "name": "Henrik Gramner", "email": "gramner@twoorioles.com", "time": "Wed Apr 22 19:02:05 2026" }, "message": "build: Update meson version requirement to 0.54.0\n\nUse of the meson \u0027fallback arg in dependency\u0027 feature was introduced\nby the switch to external checkasm in 3a2a874.\n" }, { "commit": "c5726277ffa8764665ea08f865e46912a41f2309", "tree": "03e062f5af63cc7f56ba8e555884db5c104d8290", "parents": [ "47e2607e6c04de1c2a019bf2f559402045145a1d" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Apr 15 15:41:10 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Thu Apr 16 14:02:28 2026" }, "message": "AArch64: Optimize ipred_h_8bpc_neon\n\nOptimize ipred_h_8bpc_neon using simpler stores and simpler indexing.\n\nRelative runtime after this patch on some Cortex CPUs:\n\nipred_h: w4 w8 w16 w32 w64\nCortex-A55: 1.054x 1.054x 0.978x 1.149x 1.097x\nCortex-A510: 0.455x 0.970x 0.973x 1.010x 1.002x\nCortex-A520: 0.973x 0.975x 0.979x 1.002x 1.000x\nCortex-A76: 0.791x 0.934x 0.912x 1.010x 0.999x\nCortex-A78: 0.771x 0.933x 0.957x 0.519x 0.510x\nCortex-A715: 0.838x 0.860x 0.893x 0.585x 0.661x\nCortex-A720: 0.839x 0.860x 0.892x 0.580x 0.659x\nCortex-A725: 0.809x 0.837x 0.871x 0.580x 0.660x\nCortex-X1: 0.973x 0.982x 0.989x 0.498x 0.660x\nCortex-X3: 0.971x 0.992x 0.987x 0.495x 0.661x\nCortex-X925: 0.950x 1.000x 1.000x 0.474x 0.655x\n" }, { "commit": "47e2607e6c04de1c2a019bf2f559402045145a1d", "tree": "0ce094ed1bc814b58f3e2ed8794a854b1847ad58", "parents": [ "aa4504729c82420cde1791101722788d6ed7cbf6" ], "author": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Apr 15 15:37:46 2026" }, "committer": { "name": "Arpad Panyik", "email": "Arpad.Panyik@arm.com", "time": "Wed Apr 15 15:37:46 2026" }, "message": "AArch64: Optimize ipred_v_8bpc_neon\n\nOptimize the width \u003d 4 case of ipred_v_8bpc_neon by using simple stores\ninstead of the lane stores which can improve performance on some CPUs.\n\nRelative runtime after this patch on some Cortex CPUs:\n\n ipred_v: w4\nCortex-A55: 1.041x\nCortex-A510: 0.297x\nCortex-A520: 0.748x\nCortex-A76: 0.866x\nCortex-A78: 0.856x\nCortex-A715: 0.874x\nCortex-A720: 0.875x\nCortex-A725: 0.868x\nCortex-X1: 1.013x\nCortex-X3: 1.000x\nCortex-X925: 1.000x\n" }, { "commit": "aa4504729c82420cde1791101722788d6ed7cbf6", "tree": "d2376d74ece44039f2502208063d50d45a8a39f9", "parents": [ "d69235dd804b24c04ed05639cffcc912cd6cfd75" ], "author": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue Mar 31 10:48:15 2026" }, "committer": { "name": "Martin Storsjö", "email": "martin@martin.st", "time": "Tue Mar 31 10:48:43 2026" }, "message": "arm: Fix a typo in a URL\n\nThis was added in a00289b6d8ebf0ffef9b2c08c0c63b7ad330fa47.\n" }, { "commit": "d69235dd804b24c04ed05639cffcc912cd6cfd75", "tree": "c951f4a8bb65e3c9e41468d3ad2271921aee8e41", "parents": [ "bfbd7d467775fba3f5ddc0999f0c92c46a28a544" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 20:07:48 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 21:00:03 2026" }, "message": "CI: Use shortform QEMU_CPU for loongarch64\n\nSince qemu commit 979bf44af8483cedc00c63b3e79407de08e75a30 the cpu\nargument accepts just \u0027max\u0027 as a shorthand.\n" }, { "commit": "bfbd7d467775fba3f5ddc0999f0c92c46a28a544", "tree": "69b567da4002e2dae8abc0fbd84aeca101d33c1a", "parents": [ "afcdb781cb71cba442268cc9076c095863b11fe3" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 19:54:11 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 21:00:03 2026" }, "message": "CI: loongarch64: Move QEMU_LD_PREFIX to crossfile\n\nSimplifies developement builds on local machines.\n" }, { "commit": "afcdb781cb71cba442268cc9076c095863b11fe3", "tree": "5752aa038451e90dde220bc116a702d004e795aa", "parents": [ "42ac98706aefb8d24769bbcc7d7e914457a0c251" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 19:47:55 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 21:00:03 2026" }, "message": "CI: riscv64: Move QEMU_LD_PREFIX to crossfile\n\nSimplifies developement builds on local machines.\n" }, { "commit": "42ac98706aefb8d24769bbcc7d7e914457a0c251", "tree": "15442434cc5abc6528a2f44c02f3fc0612222067", "parents": [ "8feb8526bbb064370f0a5f80644260783315b6fe" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 19:40:11 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 21:00:03 2026" }, "message": "CI: aarch64: Move QEMU_LD_PREFIX to crossfile\n\nSimplifies developement builds on local machines.\n" }, { "commit": "8feb8526bbb064370f0a5f80644260783315b6fe", "tree": "d80eaceb47f7d917f7fe4fe9a0f3f80c80098825", "parents": [ "594d1601ff5a83b565a75cb96eff37db6de82ffa" ], "author": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 19:33:29 2026" }, "committer": { "name": "Matthias Dressel", "email": "code@deadcode.eu", "time": "Tue Mar 17 21:00:03 2026" }, "message": "CI: Remove outdated version suffix from job name\n" } ], "next": "594d1601ff5a83b565a75cb96eff37db6de82ffa" }