stm32cube: update stm32mp1 to version V1.4.0
Update Cube version for STM32MP1xx series
on https://github.com/STMicroelectronics
from version v1.2.0
to version v1.4.0
Signed-off-by: Francois Ramu <francois.ramu@st.com>
diff --git a/stm32cube/stm32mp1xx/CMakeLists.txt b/stm32cube/stm32mp1xx/CMakeLists.txt
index f82304c..5171a9d 100644
--- a/stm32cube/stm32mp1xx/CMakeLists.txt
+++ b/stm32cube/stm32mp1xx/CMakeLists.txt
@@ -31,14 +31,20 @@
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C_EX drivers/src/stm32mp1xx_hal_i2c_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IPCC drivers/src/stm32mp1xx_hal_ipcc.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32mp1xx_hal_lptim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDIOS drivers/src/stm32mp1xx_hal_mdios.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDMA drivers/src/stm32mp1xx_hal_mdma.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32mp1xx_hal_pwr.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR_EX drivers/src/stm32mp1xx_hal_pwr_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_QSPI drivers/src/stm32mp1xx_hal_qspi.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG drivers/src/stm32mp1xx_hal_rng.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC drivers/src/stm32mp1xx_hal_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC_EX drivers/src/stm32mp1xx_hal_rtc_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI drivers/src/stm32mp1xx_hal_sai.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI_EX drivers/src/stm32mp1xx_hal_sai_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD drivers/src/stm32mp1xx_hal_sd.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD_EX drivers/src/stm32mp1xx_hal_sd_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32mp1xx_hal_smartcard.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32mp1xx_hal_smartcard_ex.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32mp1xx_hal_smbus.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPDIFRX drivers/src/stm32mp1xx_hal_spdifrx.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32mp1xx_hal_spi.c)
@@ -55,11 +61,13 @@
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DELAYBLOCK drivers/src/stm32mp1xx_ll_delayblock.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DMA drivers/src/stm32mp1xx_ll_dma.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_EXTI drivers/src/stm32mp1xx_ll_exti.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_FMC drivers/src/stm32mp1xx_ll_fmc.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_GPIO drivers/src/stm32mp1xx_ll_gpio.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_I2C drivers/src/stm32mp1xx_ll_i2c.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPTIM drivers/src/stm32mp1xx_ll_lptim.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_PWR drivers/src/stm32mp1xx_ll_pwr.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RCC drivers/src/stm32mp1xx_ll_rcc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RTC drivers/src/stm32mp1xx_ll_rtc.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SDMMC drivers/src/stm32mp1xx_ll_sdmmc.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SPI drivers/src/stm32mp1xx_ll_spi.c)
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32mp1xx_ll_tim.c)
diff --git a/stm32cube/stm32mp1xx/README b/stm32cube/stm32mp1xx/README
index 835519a..2b06a55 100644
--- a/stm32cube/stm32mp1xx/README
+++ b/stm32cube/stm32mp1xx/README
@@ -6,7 +6,7 @@
https://github.com/STMicroelectronics/STM32CubeMP1
Status:
- version 1.2.0
+ version 1.4.0
Purpose:
ST Microelectronics official MCU package for STM32MP1 series.
@@ -23,7 +23,7 @@
https://github.com/STMicroelectronics/STM32CubeMP1
Commit:
- c604fa0965c73e430eebd5fa780180beb9a71b44
+ 8206e534360c77f22f616243c3ccf9311af83f33
Maintained-by:
External
@@ -36,18 +36,8 @@
Patch List:
- * Fix LL RCC definition
- The CONFIG_ prefix is reserved in Zephyr, rename CONFIG_SHIFT and
- associated constants by adding a RCC_ prefix
- Impacted files:
- ext/hal/st/stm32cube/stm32mp1xx/README
- ext/hal/st/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h
- ST Bug tracker ID: BZ65410
-
- * Add new API to get stm32 ipcc num of channel
- allow to read the The IPCC peripheral HWCFGR register to get IPCC number of channels capability.
- Impacted files:
- ext/hal/st/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h
- ST Bug tracker ID: 68247
+ *Changes from official delivery:
+ -dos2unix applied
+ -trailing white spaces removed
See release_note.html from STM32Cube
diff --git a/stm32cube/stm32mp1xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32mp1xx/drivers/include/Legacy/stm32_hal_legacy.h
index 72a5e2c..d303fd6 100644
--- a/stm32cube/stm32mp1xx/drivers/include/Legacy/stm32_hal_legacy.h
+++ b/stm32cube/stm32mp1xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -315,6 +314,11 @@
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
@@ -378,7 +382,6 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
-
/**
* @}
*/
@@ -591,24 +594,24 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -643,6 +646,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@@ -765,49 +772,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-/** @brief Constants defining the events that can be selected to configure the
- * set/reset crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
-
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
-
-/** @brief Constants defining the event filtering applied to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@@ -960,6 +924,11 @@
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
/**
* @}
@@ -971,15 +940,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -1114,16 +1083,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -1450,7 +1419,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1472,7 +1441,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1486,7 +1455,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1494,7 +1464,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@@ -1517,9 +1488,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1529,20 +1500,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1554,9 +1526,9 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
@@ -1611,9 +1583,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1862,15 +1834,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -2081,8 +2053,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -2138,7 +2110,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -2275,7 +2247,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3243,9 +3216,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3356,7 +3328,6 @@
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-
/**
* @}
*/
@@ -3373,7 +3344,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3393,19 +3364,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3589,6 +3560,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
@@ -3751,7 +3729,7 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal.h
index 6acc858..293b672 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal.h
@@ -70,7 +70,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
@@ -80,7 +80,7 @@
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
-
+
/** @defgroup HAL_Exported_Constants_Group1 SYSCFG VREFBUF Voltage Scale
* @{
*/
@@ -158,7 +158,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_Exported_Constants_Group5 SYSCFG IOCompenstionCell Config
* @{
*/
@@ -234,7 +234,7 @@
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
- */
+ */
#if defined (CORE_CM4)
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
@@ -720,7 +720,7 @@
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
-
+
/* Initialization and de-initialization functions ******************************/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
@@ -736,7 +736,7 @@
/**
* @}
*/
-
+
/* Peripheral Control functions ************************************************/
/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
* @{
@@ -784,11 +784,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc.h
index 0eb4822..04a1976 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc.h
@@ -117,8 +117,8 @@
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
- Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
- to free the IRQ vector sequencer.
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
@@ -152,7 +152,7 @@
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
- uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
This parameter can be a value of @ref ADC_ConversionDataManagement.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups
@@ -334,7 +334,7 @@
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
@@ -361,7 +361,7 @@
typedef struct __ADC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
@@ -715,7 +715,6 @@
* @}
*/
-
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
@@ -813,10 +812,10 @@
* @param __HANDLE__ ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled)
*/
-#define ADC_IS_ENABLE(__HANDLE__) \
- (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
- ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
- ) ? SET : RESET)
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
/**
* @brief Check if conversion is on going on regular group.
@@ -1063,7 +1062,7 @@
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @brief Enable ADC interrupt.
@@ -1214,7 +1213,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
- *
+ *
* (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
* (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1257,7 +1256,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
- *
+ *
* (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
* (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).\n
@@ -1312,7 +1311,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
- *
+ *
* (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
* (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1362,7 +1361,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
- *
+ *
* (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
* (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1411,7 +1410,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
- *
+ *
* (1) On STM32MP1, parameter available only on ADC instance: ADC2.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
@@ -1435,7 +1434,7 @@
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -1509,10 +1508,10 @@
*/
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
- (__ADC_RESOLUTION_CURRENT__), \
- (__ADC_RESOLUTION_TARGET__))
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -1533,10 +1532,10 @@
*/
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
- (__ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -1548,7 +1547,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -1565,9 +1564,9 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1596,7 +1595,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -1617,10 +1616,10 @@
*/
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1672,13 +1671,13 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
- (__TEMPSENSOR_TYP_CALX_V__), \
- (__TEMPSENSOR_CALX_TEMP__), \
- (__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @}
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc_ex.h
index 698ec56..53bd652 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc_ex.h
@@ -396,7 +396,7 @@
* Usage of this macro is not the Standard way of multimode
* configuration and can lead to have HAL ADC handles status
* misaligned. Usage of this macro must be limited to cases
- * mentionned above.
+ * mentioned above.
* @param __HANDLE__ ADC handle.
* @retval None
*/
@@ -439,7 +439,8 @@
* @param __RANKNB__ Rank number.
* @retval None
*/
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
+ & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
@@ -509,7 +510,8 @@
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval None
*/
-#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\
+ & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
/**
* @brief Calibration factor in differential mode to be retrieved from calibration register.
@@ -1078,7 +1080,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ ADC_InjectionConfTypeDef *sConfigInjected);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* ADC_MULTIMODE_SUPPORT */
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_conf.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_conf.h
index dab85ac..07f523d 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_conf.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_conf.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_CONF_H
@@ -30,7 +30,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
@@ -59,9 +59,11 @@
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
@@ -77,6 +79,7 @@
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
@@ -93,15 +96,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
@@ -110,25 +113,25 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 64000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
+#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
@@ -170,8 +173,8 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<4U) - 1U) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
@@ -182,14 +185,14 @@
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -288,6 +291,10 @@
#include "stm32mp1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32mp1xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
@@ -300,6 +307,10 @@
#include "stm32mp1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32mp1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
@@ -322,7 +333,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -331,8 +342,8 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cortex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cortex.h
index 74b27ff..702efa3 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cortex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cortex.h
@@ -42,31 +42,31 @@
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
+ * @brief MPU Region initialization structure
* @{
*/
typedef struct
{
- uint8_t Enable; /*!< Specifies the status of the region.
+ uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
+ uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
+ uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
@@ -105,7 +105,7 @@
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
-#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
@@ -173,44 +173,44 @@
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
+/**
* @}
*/
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
@@ -219,11 +219,11 @@
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
@@ -243,7 +243,7 @@
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
-
+
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
@@ -284,7 +284,7 @@
* @}
*/
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@@ -374,13 +374,13 @@
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
- * @brief CORTEX private functions
+ * @brief CORTEX private functions
* @{
*/
@@ -393,15 +393,15 @@
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
+
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
@@ -413,7 +413,7 @@
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
+
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
@@ -430,7 +430,7 @@
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cryp.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cryp.h
index d1b060c..d3cf8ce 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cryp.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_cryp.h
@@ -64,6 +64,9 @@
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
@@ -128,6 +131,13 @@
uint32_t Version; /*!< CRYP1 IP version*/
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
@@ -286,6 +296,16 @@
* @}
*/
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+
+/**
+ * @}
+ */
/**
* @}
@@ -468,6 +488,9 @@
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_def.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_def.h
index d6e9d65..997cc40 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_def.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_def.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32mp1xx_hal_def.h
* @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
******************************************************************************
* @attention
*
@@ -35,10 +35,10 @@
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
@@ -46,13 +46,13 @@
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
-/**
- * @brief HAL Lock structures definition
+/**
+ * @brief HAL Lock structures definition
*/
-typedef enum
+typedef enum
{
HAL_UNLOCKED = 0x00U,
- HAL_LOCKED = 0x01U
+ HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
@@ -69,7 +69,7 @@
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U)
-
+
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
@@ -124,23 +124,23 @@
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
+ #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
+ #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
-/**
+/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
@@ -174,10 +174,10 @@
/**
* @brief __NOINLINE definition
- */
+ */
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
+/* ARM & GNUCompiler
+ ----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm.h
index cb55f17..d4beb1a 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm.h
@@ -34,16 +34,16 @@
/** @addtogroup DFSDM
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
* @{
*/
-/**
- * @brief HAL DFSDM Channel states definition
- */
+/**
+ * @brief HAL DFSDM Channel states definition
+ */
typedef enum
{
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
@@ -51,9 +51,9 @@
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
}HAL_DFSDM_Channel_StateTypeDef;
-/**
- * @brief DFSDM channel output clock structure definition
- */
+/**
+ * @brief DFSDM channel output clock structure definition
+ */
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
@@ -63,9 +63,9 @@
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
-/**
- * @brief DFSDM channel input structure definition
- */
+/**
+ * @brief DFSDM channel input structure definition
+ */
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
@@ -76,9 +76,9 @@
This parameter can be a value of @ref DFSDM_Channel_InputPins */
}DFSDM_Channel_InputTypeDef;
-/**
- * @brief DFSDM channel serial interface structure definition
- */
+/**
+ * @brief DFSDM channel serial interface structure definition
+ */
typedef struct
{
uint32_t Type; /*!< SPI or Manchester modes.
@@ -87,9 +87,9 @@
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
}DFSDM_Channel_SerialInterfaceTypeDef;
-/**
- * @brief DFSDM channel analog watchdog structure definition
- */
+/**
+ * @brief DFSDM channel analog watchdog structure definition
+ */
typedef struct
{
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
@@ -98,9 +98,9 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}DFSDM_Channel_AwdTypeDef;
-/**
- * @brief DFSDM channel init structure definition
- */
+/**
+ * @brief DFSDM channel init structure definition
+ */
typedef struct
{
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
@@ -113,15 +113,19 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
}DFSDM_Channel_InitTypeDef;
-/**
- * @brief DFSDM channel handle structure definition
- */
+/**
+ * @brief DFSDM channel handle structure definition
+ */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Channel_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
@@ -129,7 +133,7 @@
#endif
}DFSDM_Channel_HandleTypeDef;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief DFSDM channel callback ID enumeration definition
*/
@@ -147,9 +151,9 @@
typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
#endif
-/**
- * @brief HAL DFSDM Filter states definition
- */
+/**
+ * @brief HAL DFSDM Filter states definition
+ */
typedef enum
{
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
@@ -160,9 +164,9 @@
HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
}HAL_DFSDM_Filter_StateTypeDef;
-/**
- * @brief DFSDM filter regular conversion parameters structure definition
- */
+/**
+ * @brief DFSDM filter regular conversion parameters structure definition
+ */
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
@@ -171,9 +175,9 @@
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
}DFSDM_Filter_RegularParamTypeDef;
-/**
- * @brief DFSDM filter injected conversion parameters structure definition
- */
+/**
+ * @brief DFSDM filter injected conversion parameters structure definition
+ */
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
@@ -186,9 +190,9 @@
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
}DFSDM_Filter_InjectedParamTypeDef;
-/**
- * @brief DFSDM filter parameters structure definition
- */
+/**
+ * @brief DFSDM filter parameters structure definition
+ */
typedef struct
{
uint32_t SincOrder; /*!< Sinc filter order.
@@ -199,9 +203,9 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
}DFSDM_Filter_FilterParamTypeDef;
-/**
- * @brief DFSDM filter init structure definition
- */
+/**
+ * @brief DFSDM filter init structure definition
+ */
typedef struct
{
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
@@ -209,10 +213,14 @@
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
}DFSDM_Filter_InitTypeDef;
-/**
- * @brief DFSDM filter handle structure definition
- */
+/**
+ * @brief DFSDM filter handle structure definition
+ */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Filter_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
@@ -226,8 +234,8 @@
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
- uint32_t ErrorCode; /*!< DFSDM filter error code */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+ uint32_t ErrorCode; /*!< DFSDM filter error code */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
@@ -240,9 +248,9 @@
#endif
}DFSDM_Filter_HandleTypeDef;
-/**
- * @brief DFSDM filter analog watchdog parameters structure definition
- */
+/**
+ * @brief DFSDM filter analog watchdog parameters structure definition
+ */
typedef struct
{
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
@@ -259,7 +267,7 @@
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief DFSDM filter callback ID enumeration definition
*/
@@ -283,7 +291,7 @@
/**
* @}
- */
+ */
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -432,12 +440,12 @@
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{
- */
+ */
#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
#endif
/**
@@ -465,7 +473,7 @@
- in 16-bit MSB the channel number is set
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- - the channel number 5 is 0x00050000
+ - the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#define DFSDM_CHANNEL_0 0x00000001U
#define DFSDM_CHANNEL_1 0x00010002U
@@ -499,7 +507,7 @@
/**
* @}
- */
+ */
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
@@ -511,7 +519,7 @@
* @param __HANDLE__ DFSDM channel handle.
* @retval None
*/
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@@ -525,7 +533,7 @@
* @param __HANDLE__ DFSDM filter handle.
* @retval None
*/
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@@ -557,7 +565,7 @@
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Channel callbacks register/unregister functions ****************************/
HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
@@ -613,7 +621,7 @@
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Filter callbacks register/unregister functions ****************************/
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
@@ -779,12 +787,12 @@
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
/**
* @}
- */
+ */
/* End of private macros -----------------------------------------------------*/
/**
* @}
- */
+ */
/**
* @}
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm_ex.h
index 5d7f352..52f3d06 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_dfsdm_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_DFSDM_EX_H
@@ -27,7 +27,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
-
+
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
@@ -54,11 +54,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
@@ -70,11 +70,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_exti.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_exti.h
index c16c8f7..ff289d0 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_exti.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_exti.h
@@ -108,7 +108,7 @@
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) /* RTC timestamp and SecureError wakeup */
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) /* TAMP tamper and SecureError wakeup */
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) /* RTC Wakeup timer and Alarms (A and B) and SecureError wakeup */
-#define EXTI_LINE_20 (EXTI_RESERVED | | EXTI_REG1 | 0x14u) /* RESERVED */
+#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) /* RESERVED */
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) /* I2C1 wakeup */
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) /* I2C2 wakeup */
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /* I2C3 wakeup */
@@ -175,7 +175,6 @@
*/
#define EXTI_MODE_C1_NONE 0x00000010u
#define EXTI_MODE_C1_INTERRUPT 0x00000011u
-#define EXTI_MODE_C1_EVENT 0x00000012u
#define EXTI_MODE_C2_NONE 0x00000020u
#define EXTI_MODE_C2_INTERRUPT 0x00000021u
#define EXTI_MODE_C2_EVENT 0x00000022u
@@ -254,7 +253,8 @@
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
-#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
+#define EXTI_REG3 (0x02uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
#define EXTI_PIN_MASK 0x0000001Fu
/**
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_gpio_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_gpio_ex.h
index f45fcc7..1047335 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_gpio_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_gpio_ex.h
@@ -276,12 +276,12 @@
/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIOEx_Exported_Functions GPIO Extended Exported Functions
* @{
*/
-/** @addtogroup GPIOEx_Exported_Functions_Group1 Extended Peripheral Control functions
+/** @addtogroup GPIOEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @{
*/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdios.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdios.h
index 872ab86..e8c859c 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdios.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdios.h
@@ -28,7 +28,7 @@
#endif
#if defined (MDIOS)
-
+
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
@@ -38,13 +38,13 @@
/** @addtogroup MDIOS
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
* @{
*/
-
+
/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
* @{
*/
@@ -57,7 +57,7 @@
HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_MDIOS_StateTypeDef;
-/**
+/**
* @}
*/
@@ -67,13 +67,13 @@
typedef struct
{
- uint32_t PortAddress; /*!< Specifies the MDIOS port address.
+ uint32_t PortAddress; /*!< Specifies the MDIOS port address.
This parameter can be a value from 0 to 31 */
- uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
- This parameter can be a value of @ref MDIOS_Preamble_Check */
+ uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
+ This parameter can be a value of @ref MDIOS_Preamble_Check */
}MDIOS_InitTypeDef;
-/**
+/**
* @}
*/
@@ -84,19 +84,19 @@
typedef struct
{
MDIOS_TypeDef *Instance; /*!< Register base address */
-
+
MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
-
+
__IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
-
+
HAL_LockTypeDef Lock; /*!< MDIOS Lock */
}MDIOS_HandleTypeDef;
-/**
+/**
* @}
*/
-/**
+/**
* @}
*/
@@ -109,7 +109,7 @@
* @{
*/
#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
-#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
+#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
/**
* @}
*/
@@ -151,7 +151,7 @@
#define MDIOS_REG31 ((uint32_t)0x0000001FU)
/**
* @}
- */
+ */
/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
* @{
@@ -220,7 +220,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
@@ -251,7 +251,7 @@
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
@@ -263,7 +263,7 @@
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
@@ -288,7 +288,7 @@
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
- * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+ * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval The state of the error flag
*/
#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
@@ -299,7 +299,7 @@
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
- * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+ * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval none
*/
#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
@@ -311,7 +311,7 @@
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
* @retval The state of the interrupt source
*/
#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
@@ -320,7 +320,7 @@
* @brief Enable the MDIOS WAKEUP Exti Line.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR2 |= (__EXTI_LINE__))
@@ -329,16 +329,16 @@
* @brief Enable the MDIOS WAKEUP Exti Line by Domain2.
* @param __EXTILINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
-#define __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR2 |= (__EXTI_LINE__))
+#define __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR2 |= (__EXTI_LINE__))
/**
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @param __EXTILINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval EXTI MDIOS WAKEUP Line Status.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 & (__EXTI_LINE__))
@@ -347,7 +347,7 @@
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @param __EXTILINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval EXTI MDIOS WAKEUP Line Status.
*/
#define __HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR2 & (__EXTI_LINE__))
@@ -356,7 +356,7 @@
* @brief Clear the MDIOS WAKEUP Exti flag.
* @param __EXTILINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
@@ -365,7 +365,7 @@
* @brief Clear the MDIOS WAKEUP Exti flag.
* @param __EXTILINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
+ * @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR2 = (__EXTI_LINE__))
@@ -378,7 +378,7 @@
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
- (EXTI->RTSR2 |= (__EXTI_LINE__))
+ (EXTI->RTSR2 |= (__EXTI_LINE__))
/**
* @brief enable falling edge interrupt on selected EXTI line.
@@ -407,7 +407,7 @@
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None
*/
-#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
+#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
/**
* @}
@@ -470,7 +470,7 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
@@ -505,7 +505,7 @@
/**
* @}
*/
-
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
* @{
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdma.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdma.h
index 5f4585b..4a74a11 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdma.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_mdma.h
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32mp1xx_hal_mdma.h
* @author MCD Application Team
- * @version V0.3.0
- * @date 9-December-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -17,11 +15,11 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32MP1xx_HAL_MDMA_H
-#define __STM32MP1xx_HAL_MDMA_H
+#ifndef STM32MP1xx_HAL_MDMA_H
+#define STM32MP1xx_HAL_MDMA_H
#ifdef __cplusplus
extern "C" {
@@ -36,131 +34,132 @@
/** @addtogroup MDMA
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDMA_Exported_Types MDMA Exported Types
- * @brief MDMA Exported Types
+ * @brief MDMA Exported Types
* @{
*/
-/**
+/**
* @brief MDMA Configuration Structure definition
*/
typedef struct
{
-
+
uint32_t Request; /*!< Specifies the MDMA request.
This parameter can be a value of @ref MDMA_Request_selection*/
-
+
uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a :
- a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
- This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
-
+ a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+ This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
+
uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx.
This parameter can be a value of @ref MDMA_Priority_level */
- uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode.
- This parameter can be a value of @ref MDMA_Secure_Mode */
-
- uint32_t Endianess; /*!< Specifies if the MDMA transactions preserve the Little endianess.
- This parameter can be a value of @ref MDMA_Endianess */
-
+ uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode.
+ This parameter can be a value of @ref MDMA_Secure_Mode */
+
+ uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness.
+ This parameter can be a value of @ref MDMA_Endianness */
+
uint32_t SourceInc; /*!< Specifies if the Source increment mode .
This parameter can be a value of @ref MDMA_Source_increment_mode */
-
+
uint32_t DestinationInc; /*!< Specifies if the Destination increment mode .
This parameter can be a value of @ref MDMA_Destination_increment_mode */
-
+
uint32_t SourceDataSize; /*!< Specifies the source data size.
This parameter can be a value of @ref MDMA_Source_data_size */
-
+
uint32_t DestDataSize; /*!< Specifies the destination data size.
This parameter can be a value of @ref MDMA_Destination_data_size */
-
-
+
+
uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode.
- This parameter can be a value of @ref MDMA_data_Alignment */
+ This parameter can be a value of @ref MDMA_data_Alignment */
uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes),
this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
-
- uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+
+ uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
transaction.
- This parameter can be a value of @ref MDMA_Source_burst
+ This parameter can be a value of @ref MDMA_Source_burst
@note : the burst may be FIXED/INCR based on SourceInc value ,
the BURST must be programmed as to ensure that the burst size will be lower than than
BufferTransferLength */
-
- uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+
+ uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
transaction.
- This parameter can be a value of @ref MDMA_Destination_burst
+ This parameter can be a value of @ref MDMA_Destination_burst
@note : the burst may be FIXED/INCR based on DestinationInc value ,
the BURST must be programmed as to ensure that the burst size will be lower than than
BufferTransferLength */
-
+
int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset
signed value : if > 0 then increment the next block source Address by offset from where the last block ends
if < 0 then decrement the next block source Address by offset from where the last block ends
if == 0, the next block source address starts from where the last block ends
- */
+ */
int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset
signed value : if > 0 then increment the next block destination Address by offset from where the last block ends
if < 0 then decrement the next block destination Address by offset from where the last block ends
if == 0, the next block destination address starts from where the last block ends
- */
-
+ */
+
}MDMA_InitTypeDef;
-/**
- * @brief HAL MDMA linked list node structure definition
- * @note The Linked list node allows to define a new MDMA configuration
+/**
+ * @brief HAL MDMA linked list node structure definition
+ * @note The Linked list node allows to define a new MDMA configuration
* (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
* When CLAR register is configured to a non NULL value , each time a transfer ends,
- * a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+ * a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
*/
typedef struct
{
- uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
- uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
- uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
- uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
- uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
- uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
- uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
- uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
- uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
-
+ __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
+ __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
+ __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
+ __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
+ __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
+ __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
+ __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
+ __IO uint32_t Reserved; /*!< Reserved register */
+ __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
+ __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
+
}MDMA_LinkNodeTypeDef;
-/**
- * @brief HAL MDMA linked list node configuration structure definition
- * @note used with HAL_MDMA_LinkedList_CreateNode function
+/**
+ * @brief HAL MDMA linked list node configuration structure definition
+ * @note used with HAL_MDMA_LinkedList_CreateNode function
*/
typedef struct
-{
- MDMA_InitTypeDef Init; /* !< configuration of the specified MDMA Linked List Node */
- uint32_t SrcAddress; /* !< The source memory address for the Linked list Node */
- uint32_t DstAddress; /* !< The destination memory address for the Linked list Node */
- uint32_t BlockDataLength; /* !< The length of a block transfer in bytes */
- uint32_t BlockCount; /* !< The number of a blocks to be transfer */
+{
+ MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */
+ uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */
+ uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */
+ uint32_t BlockDataLength; /*!< The data length of a block in bytes */
+ uint32_t BlockCount; /*!< The number of blocks to be transferred */
uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
-
-
+
+
}MDMA_LinkNodeConfTypeDef;
-/**
+/**
* @brief HAL MDMA State structure definition
*/
typedef enum
@@ -168,13 +167,13 @@
HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */
HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */
HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */
- HAL_MDMA_STATE_TIMEOUT = 0x03U, /*!< MDMA timeout state */
- HAL_MDMA_STATE_ERROR = 0x04U, /*!< MDMA error state */
- HAL_MDMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
+ HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */
+ HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */
+ HAL_MDMA_STATE_TIMEOUT = 0x05U, /*!< MDMA timeout state */
}HAL_MDMA_StateTypeDef;
-/**
+/**
* @brief HAL MDMA Level Complete structure definition
*/
typedef enum
@@ -183,10 +182,10 @@
HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */
HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */
HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */
-
+
}HAL_MDMA_LevelCompleteTypeDef;
-/**
+/**
* @brief HAL MDMA Callbacks IDs structure definition
*/
typedef enum
@@ -202,47 +201,46 @@
}HAL_MDMA_CallbackIDTypeDef;
-/**
+/**
* @brief MDMA handle Structure definition
*/
typedef struct __MDMA_HandleTypeDef
{
MDMA_Channel_TypeDef *Instance; /*!< Register base address */
-
+
MDMA_InitTypeDef Init; /*!< MDMA communication parameters */
-
HAL_LockTypeDef Lock; /*!< MDMA locking object */
-
+
__IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */
-
+
void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */
void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */
-
+
void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */
void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */
- void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
-
+ void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
- MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
+
+ MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
(after the initial node defined by the Init struct)
- this parameter is used internally by the MDMA driver
- to construct the liked list node
+ this parameter is used internally by the MDMA driver
+ to construct the linked list node
*/
MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list
this parameter is used internally by the MDMA driver
- to construct the liked list node
+ to construct the linked list node
*/
- uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
-
+ uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
+
__IO uint32_t ErrorCode; /*!< MDMA Error code */
} MDMA_HandleTypeDef;
@@ -254,14 +252,14 @@
/* Exported constants --------------------------------------------------------*/
/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
- * @brief MDMA Exported constants
+ * @brief MDMA Exported constants
* @{
*/
/** @defgroup MDMA_Error_Codes MDMA Error Codes
- * @brief MDMA Error Codes
+ * @brief MDMA Error Codes
* @{
- */
+ */
#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */
#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */
@@ -270,9 +268,9 @@
#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */
#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */
#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
-#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
-#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
-
+#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
+#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
+
/**
* @}
*/
@@ -316,7 +314,6 @@
#define MDMA_REQUEST_I2C6_RX ((uint32_t)0x00000026U) /*!< MDMA HW request is I2C6 Rx Transfer Complete Flag */
#define MDMA_REQUEST_I2C6_TX ((uint32_t)0x00000027U) /*!< MDMA HW request is I2C6 Tx Transfer Complete Flag */
#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
-
/**
* @}
*/
@@ -325,12 +322,12 @@
* @brief MDMA Transfer Trigger Mode
* @{
*/
-#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
-#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
-#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
+#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
+#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
+#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
-/**
+/**
* @}
*/
@@ -345,8 +342,8 @@
/**
* @}
- */
-
+ */
+
/** @defgroup MDMA_Secure_Mode MDMA Secure Mode
* @brief MDMA Secure Mode
* @{
@@ -358,64 +355,64 @@
* @}
*/
-/** @defgroup MDMA_Endianess MDMA Endianess
- * @brief MDMA Endianess
+/** @defgroup MDMA_Endianness MDMA Endianness
+ * @brief MDMA Endianness
* @{
*/
-#define MDMA_LITTLE_ENDIANESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianess preserve */
-#define MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianess exchange when destination data size is > Byte */
-#define MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianess exchange when destination data size is > HALF WORD*/
-#define MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianess exchange when destination data size is > DOUBLE WORD */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
/**
* @}
*/
-
+
/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
* @brief MDMA Source increment mode
* @{
*/
-#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
-#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
+#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
+#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
+#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
+#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
+#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
* @}
- */
-
+ */
+
/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
* @brief MDMA Destination increment mode
* @{
*/
-#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
-#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
+#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
+#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
+#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
+#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
+#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
* @}
- */
-
+ */
+
/** @defgroup MDMA_Source_data_size MDMA Source data size
* @brief MDMA Source data size
* @{
*/
-#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
-#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
-#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
+#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
+#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
+#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
-
+
/**
* @}
*/
@@ -424,88 +421,88 @@
* @brief MDMA Destination data size
* @{
*/
-#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
-#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
-#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
+#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
+#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
+#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
-
+
/**
* @}
*/
/** @defgroup MDMA_data_Alignment MDMA data alignment
- * @brief MDMA MDMA data alignment
+ * @brief MDMA data alignment
* @{
*/
#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
- All data are right aligned, in Little Endien mode. */
-#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
-#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
- Note : this mode is allowed only if the Source data size smaller than Destination data size */
-#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
-
+ All data are right aligned, in Little Endien mode. */
+#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
+#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
+ Note : this mode is allowed only if the Source data size is smaller than Destination data size */
+#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
+
/**
* @}
*/
-
+
/** @defgroup MDMA_Source_burst MDMA Source burst
* @brief MDMA Source burst
* @{
*/
-#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
-#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
-#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
-#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
-#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
-#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
-#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
-#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
-
+#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
+#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
+#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
+#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
+#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
+#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
+#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
+
/**
* @}
*/
-
+
/** @defgroup MDMA_Destination_burst MDMA Destination burst
* @brief MDMA Destination burst
* @{
*/
-#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
-#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
-#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
-#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
-#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
-#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
-#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
-#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
+#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
+#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
+#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
+#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
+#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
+#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
+#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
/**
* @}
*/
-
+
/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
* @brief MDMA interrupt enable definitions
* @{
*/
-#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
+#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
-#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
-#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
-#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
+#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
+#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
/**
* @}
- */
-
+ */
+
/** @defgroup MDMA_flag_definitions MDMA flag definitions
* @brief MDMA flag definitions
* @{
*/
-#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
-#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
+#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
+#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
-#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
-#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
-#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
+#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
+#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
+#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
/**
* @}
@@ -527,9 +524,9 @@
* @retval None
*/
#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
-
+
/**
- * @brief Disable the specified DMA Channel.
+ * @brief Disable the specified MDMA Channel.
* @param __HANDLE__: MDMA handle
* @retval None
*/
@@ -545,10 +542,10 @@
* @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
* @arg MDMA_FLAG_BT : Block Transfer complete flag.
* @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
- * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+ * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
* @retval The state of FLAG (SET or RESET).
*/
-#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
/**
* @brief Clear the MDMA Stream pending flags.
@@ -559,21 +556,21 @@
* @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
* @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
* @arg MDMA_FLAG_BT : Block Transfer complete flag.
- * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+ * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
* @retval None
*/
#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
/**
- * @brief Enables the specified DMA Channel interrupts.
+ * @brief Enables the specified MDMA Channel interrupts.
* @param __HANDLE__: MDMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval None
*/
#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
@@ -581,34 +578,49 @@
/**
* @brief Disables the specified MDMA Channel interrupts.
* @param __HANDLE__: MDMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval None
*/
#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * @param __HANDLE__: MDMA handle
+ * @param __INTERRUPT__: specifies the MDMA interrupt source to check.
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval The state of MDMA_IT (SET or RESET).
*/
#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
+ * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx.
+ * @param __HANDLE__ : MDMA handle
+ * @param __COUNTER__: Number of data in bytes to be transferred.
+ * @retval None
+ */
+#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT))
+
+/**
+ * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer.
+ * @param __HANDLE__ : MDMA handle
+ * @retval The number of remaining data in bytes in the current MDMA Channelx transfer.
+ */
+#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT)
+
+/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDMA_Exported_Functions MDMA Exported Functions
* @{
@@ -616,7 +628,7 @@
/* Initialization and de-initialization functions *****************************/
/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
@@ -628,43 +640,45 @@
/**
* @}
- */
+ */
/* Linked list operation functions ********************************************/
/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
- * @brief Linked list operation functions
+ * @brief Linked list operation functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
/**
* @}
- */
+ */
/* IO operation functions *****************************************************/
/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
- * @brief I/O operation functions
+ * @brief I/O operation functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
/**
* @}
- */
+ */
/* Peripheral State and Error functions ***************************************/
/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+ * @brief Peripheral State functions
* @{
*/
HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
@@ -672,13 +686,14 @@
void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma);
void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
+
/**
* @}
*/
/**
* @}
- */
+ */
/* Private types -------------------------------------------------------------*/
/** @defgroup MDMA_Private_Types MDMA Private Types
@@ -687,7 +702,7 @@
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup MDMA_Private_Defines MDMA Private Defines
@@ -696,8 +711,8 @@
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDMA_Private_Variables MDMA Private Variables
* @{
@@ -705,7 +720,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup MDMA_Private_Constants MDMA Private Constants
@@ -714,36 +729,30 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup MDMA_Private_Macros MDMA Private Macros
* @{
*/
-/** @defgroup MDMA_IS_Definitions MDMA Private macros to check input parameters
- * @{
- */
-
#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \
((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
-#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
- ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
- ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
- ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
#define IS_MDMA_SECURE_MODE(__SECURE_MODE__) (((__SECURE_MODE__) == MDMA_SECURE_MODE_DISABLE ) || \
((__SECURE_MODE__) == MDMA_SECURE_MODE_ENABLE))
-
-#define IS_MDMA_ENDIANESS_MODE(__ENDIANESS__) (((__ENDIANESS__) == MDMA_LITTLE_ENDIANESS_PRESERVE ) || \
- ((__ENDIANESS__) == MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE) || \
- ((__ENDIANESS__) == MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE) || \
- ((__ENDIANESS__) == MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE))
-
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
+ ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
+ ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+ ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_I2C6_TX))
@@ -778,9 +787,9 @@
((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
@@ -792,7 +801,7 @@
((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
-
+
#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
@@ -803,25 +812,21 @@
((__BURST__) == MDMA_DEST_BURST_128BEATS))
#define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
- ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
- ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
- ((__MODE__) == MDMA_FULL_TRANSFER))
+ ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
+ ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+ ((__MODE__) == MDMA_FULL_TRANSFER))
-#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
-#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
-#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
@@ -853,6 +858,6 @@
}
#endif
-#endif /* __STM32MP1xx_HAL_MDMA_H */
+#endif /* STM32MP1xx_HAL_MDMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc.h
index b20a630..6166c16 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc.h
@@ -325,10 +325,10 @@
/** @defgroup RCC_HSI_Clock_Prescaler RCC_HSI_Clock_Prescaler
* @{
*/
-#define RCC_HSI_DIV1 RCC_HSICFGR_HSIDIV_0 /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/
-#define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_1 /* Division by 2, ck_hsi(_ker) = 32 MHz*/
-#define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_2 /* Division by 4, ck_hsi(_ker) = 16 MHz*/
-#define RCC_HSI_DIV8 RCC_HSICFGR_HSIDIV_3 /* Division by 8, ck_hsi(_ker) = 8 MHz*/
+#define RCC_HSI_DIV1 0U /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/
+#define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_0 /* Division by 2, ck_hsi(_ker) = 32 MHz*/
+#define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_1 /* Division by 4, ck_hsi(_ker) = 16 MHz*/
+#define RCC_HSI_DIV8 (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1) /* Division by 8, ck_hsi(_ker) = 8 MHz*/
#define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \
((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) )
@@ -374,11 +374,11 @@
/** @defgroup RCC_MCO1_Clock_Source RCC_MCO1_Clock_Source
* @{
*/
-#define RCC_MCO1SOURCE_HSI RCC_MCO1CFGR_MCO1SEL_0
-#define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_1
-#define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_2
-#define RCC_MCO1SOURCE_LSI RCC_MCO1CFGR_MCO1SEL_3
-#define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_4
+#define RCC_MCO1SOURCE_HSI 0U
+#define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_0
+#define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_1
+#define RCC_MCO1SOURCE_LSI (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1)
+#define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_2
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
@@ -391,12 +391,12 @@
/** @defgroup RCC_MCO2_Clock_Source RCC_MCO2_Clock_Source
* @{
*/
-#define RCC_MCO2SOURCE_MPU RCC_MCO2CFGR_MCO2SEL_0
-#define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_1
-#define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_2
-#define RCC_MCO2SOURCE_PLL4 RCC_MCO2CFGR_MCO2SEL_3
-#define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_4
-#define RCC_MCO2SOURCE_HSI RCC_MCO2CFGR_MCO2SEL_5
+#define RCC_MCO2SOURCE_MPU 0U
+#define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_0
+#define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_1
+#define RCC_MCO2SOURCE_PLL4 (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0)
+#define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_2
+#define RCC_MCO2SOURCE_HSI (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0)
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_MPU) || ((SOURCE) == RCC_MCO2SOURCE_AXI) || \
((SOURCE) == RCC_MCO2SOURCE_MCU) || ((SOURCE) == RCC_MCO2SOURCE_PLL4) || \
@@ -409,22 +409,22 @@
* @{
* @note: MCO1 division factors are used for MCODIV values as they are the same for MCO2
*/
-#define RCC_MCODIV_1 RCC_MCO1CFGR_MCO1DIV_0
-#define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_1
-#define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_2
-#define RCC_MCODIV_4 RCC_MCO1CFGR_MCO1DIV_3
-#define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_4
-#define RCC_MCODIV_6 RCC_MCO1CFGR_MCO1DIV_5
-#define RCC_MCODIV_7 RCC_MCO1CFGR_MCO1DIV_6
-#define RCC_MCODIV_8 RCC_MCO1CFGR_MCO1DIV_7
-#define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_8
-#define RCC_MCODIV_10 RCC_MCO1CFGR_MCO1DIV_9
-#define RCC_MCODIV_11 RCC_MCO1CFGR_MCO1DIV_10
-#define RCC_MCODIV_12 RCC_MCO1CFGR_MCO1DIV_11
-#define RCC_MCODIV_13 RCC_MCO1CFGR_MCO1DIV_12
-#define RCC_MCODIV_14 RCC_MCO1CFGR_MCO1DIV_13
-#define RCC_MCODIV_15 RCC_MCO1CFGR_MCO1DIV_14
-#define RCC_MCODIV_16 RCC_MCO1CFGR_MCO1DIV_15
+#define RCC_MCODIV_1 0U
+#define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_0
+#define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_1
+#define RCC_MCODIV_4 (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_2
+#define RCC_MCODIV_6 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_7 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)
+#define RCC_MCODIV_8 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_3
+#define RCC_MCODIV_10 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_11 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1)
+#define RCC_MCODIV_12 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_13 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2)
+#define RCC_MCODIV_14 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)
+#define RCC_MCODIV_15 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)
+#define RCC_MCODIV_16 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)
@@ -444,10 +444,10 @@
/** @defgroup RCC_MPU_Clock_Source RCC_MPU_Clock_Source
* @{
*/
-#define RCC_MPUSOURCE_HSI RCC_MPCKSELR_MPUSRC_0
-#define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_1
-#define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2
-#define RCC_MPUSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3
+#define RCC_MPUSOURCE_HSI 0U
+#define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_0
+#define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_1
+#define RCC_MPUSOURCE_MPUDIV (RCC_MPCKSELR_MPUSRC_0 | RCC_MPCKSELR_MPUSRC_1)
#define IS_RCC_MPUSOURCE(SOURCE) (((SOURCE) == RCC_MPUSOURCE_HSI) || \
((SOURCE) == RCC_MPUSOURCE_HSE) || \
@@ -460,10 +460,10 @@
/** @defgroup RCC_AXISS_Clock_Source RCC_AXISS_Clock_Source
* @{
*/
-#define RCC_AXISSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0
-#define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1
-#define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2
-#define RCC_AXISSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3
+#define RCC_AXISSOURCE_HSI 0U
+#define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_0
+#define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_1
+#define RCC_AXISSOURCE_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0)
#define IS_RCC_AXISSOURCE(SOURCE) (((SOURCE) == RCC_AXISSOURCE_HSI) || \
((SOURCE) == RCC_AXISSOURCE_HSE) || \
@@ -476,10 +476,10 @@
/** @defgroup RCC_MCU_Clock_Source RCC_MCU_Clock_Source
* @{
*/
-#define RCC_MCUSSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0
-#define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1
-#define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2
-#define RCC_MCUSSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3
+#define RCC_MCUSSOURCE_HSI 0U
+#define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_0
+#define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_1
+#define RCC_MCUSSOURCE_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0)
#define IS_RCC_MCUSSOURCE(SOURCE) (((SOURCE) == RCC_MCUSSOURCE_HSI) || \
((SOURCE) == RCC_MCUSSOURCE_HSE) || \
@@ -493,7 +493,7 @@
/** @defgroup RCC_RTC_Division_Factor RCC_RTC_Division_Factor
* @{
*/
-#define RCC_RTCDIV(x) RCC_RTCDIVR_RTCDIV_(y)
+#define RCC_RTCDIV(x) (uint32_t)(x - 1U)
#define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
/**
@@ -503,11 +503,11 @@
/** @defgroup RCC_MPU_Clock_Divider RCC_MPU_Clock_Divider
* @{
*/
-#define RCC_MPU_DIV_OFF RCC_MPCKDIVR_MPUDIV_0
-#define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_1
-#define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_2
-#define RCC_MPU_DIV8 RCC_MPCKDIVR_MPUDIV_3
-#define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_4
+#define RCC_MPU_DIV_OFF 0U
+#define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_0
+#define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_1
+#define RCC_MPU_DIV8 (RCC_MPCKDIVR_MPUDIV_1 | RCC_MPCKDIVR_MPUDIV_0)
+#define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_2
#define IS_RCC_MPUDIV(DIVIDER) ( ((DIVIDER) == RCC_MPU_DIV2) || \
((DIVIDER) == RCC_MPU_DIV4) || \
@@ -520,10 +520,10 @@
/** @defgroup RCC_AXI_Clock_Divider RCC_AXI_Clock_Divider
* @{
*/
-#define RCC_AXI_DIV1 RCC_AXIDIVR_AXIDIV_0
-#define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_1
-#define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_2
-#define RCC_AXI_DIV4 RCC_AXIDIVR_AXIDIV_3
+#define RCC_AXI_DIV1 0U
+#define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_0
+#define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_1
+#define RCC_AXI_DIV4 (RCC_AXIDIVR_AXIDIV_0 | RCC_AXIDIVR_AXIDIV_1)
#define IS_RCC_AXIDIV(DIVIDER) (((DIVIDER) == RCC_AXI_DIV1) || \
((DIVIDER) == RCC_AXI_DIV2) || \
@@ -536,11 +536,11 @@
/** @defgroup RCC_APB4_Clock_Divider RCC_APB4_Clock_Divider
* @{
*/
-#define RCC_APB4_DIV1 RCC_APB4DIVR_APB4DIV_0
-#define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_1
-#define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_2
-#define RCC_APB4_DIV8 RCC_APB4DIVR_APB4DIV_3
-#define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_4
+#define RCC_APB4_DIV1 0U
+#define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_0
+#define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_1
+#define RCC_APB4_DIV8 (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0)
+#define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_2
#define IS_RCC_APB4DIV(DIVIDER) (((DIVIDER) == RCC_APB4_DIV1) || \
((DIVIDER) == RCC_APB4_DIV2) || \
@@ -554,11 +554,11 @@
/** @defgroup RCC_APB5_Clock_Divider RCC_APB5_Clock_Divider
* @{
*/
-#define RCC_APB5_DIV1 RCC_APB5DIVR_APB5DIV_0
-#define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_1
-#define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_2
-#define RCC_APB5_DIV8 RCC_APB5DIVR_APB5DIV_3
-#define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_4
+#define RCC_APB5_DIV1 0U
+#define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_0
+#define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_1
+#define RCC_APB5_DIV8 (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0)
+#define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_2
#define IS_RCC_APB5DIV(DIVIDER) (((DIVIDER) == RCC_APB5_DIV1) || \
((DIVIDER) == RCC_APB5_DIV2) || \
@@ -572,16 +572,16 @@
/** @defgroup RCC_MCU_Clock_Divider RCC_MCU_Clock_Divider
* @{
*/
-#define RCC_MCU_DIV1 RCC_MCUDIVR_MCUDIV_0
-#define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_1
-#define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_2
-#define RCC_MCU_DIV8 RCC_MCUDIVR_MCUDIV_3
-#define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_4
-#define RCC_MCU_DIV32 RCC_MCUDIVR_MCUDIV_5
-#define RCC_MCU_DIV64 RCC_MCUDIVR_MCUDIV_6
-#define RCC_MCU_DIV128 RCC_MCUDIVR_MCUDIV_7
-#define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_8
-#define RCC_MCU_DIV512 RCC_MCUDIVR_MCUDIV_9
+#define RCC_MCU_DIV1 0U
+#define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_0
+#define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_1
+#define RCC_MCU_DIV8 (RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0)
+#define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_2
+#define RCC_MCU_DIV32 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_0)
+#define RCC_MCU_DIV64 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1)
+#define RCC_MCU_DIV128 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0)
+#define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_3
+#define RCC_MCU_DIV512 (RCC_MCUDIVR_MCUDIV_3 | RCC_MCUDIVR_MCUDIV_0)
#define IS_RCC_MCUDIV(DIVIDER) (((DIVIDER) == RCC_MCU_DIV1) || \
((DIVIDER) == RCC_MCU_DIV2) || \
@@ -600,11 +600,11 @@
/** @defgroup RCC_APB1_Clock_Divider RCC_APB1_Clock_Divider
* @{
*/
-#define RCC_APB1_DIV1 RCC_APB1DIVR_APB1DIV_0
-#define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_1
-#define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_2
-#define RCC_APB1_DIV8 RCC_APB1DIVR_APB1DIV_3
-#define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_4
+#define RCC_APB1_DIV1 0U
+#define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_0
+#define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_1
+#define RCC_APB1_DIV8 (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0)
+#define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_2
#define IS_RCC_APB1DIV(DIVIDER) (((DIVIDER) == RCC_APB1_DIV1) || \
((DIVIDER) == RCC_APB1_DIV2) || \
@@ -618,11 +618,11 @@
/** @defgroup RCC_APB2_Clock_Divider RCC_APB2_Clock_Divider
* @{
*/
-#define RCC_APB2_DIV1 RCC_APB2DIVR_APB2DIV_0
-#define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_1
-#define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_2
-#define RCC_APB2_DIV8 RCC_APB2DIVR_APB2DIV_3
-#define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_4
+#define RCC_APB2_DIV1 0U
+#define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_0
+#define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_1
+#define RCC_APB2_DIV8 (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0)
+#define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_2
#define IS_RCC_APB2DIV(DIVIDER) (((DIVIDER) == RCC_APB2_DIV1) || \
((DIVIDER) == RCC_APB2_DIV2) || \
@@ -636,11 +636,11 @@
/** @defgroup RCC_APB3_Clock_Divider RCC_APB3_Clock_Divider
* @{
*/
-#define RCC_APB3_DIV1 RCC_APB3DIVR_APB3DIV_0
-#define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_1
-#define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_2
-#define RCC_APB3_DIV8 RCC_APB3DIVR_APB3DIV_3
-#define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_4
+#define RCC_APB3_DIV1 0U
+#define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_0
+#define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_1
+#define RCC_APB3_DIV8 (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0)
+#define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_2
#define IS_RCC_APB3DIV(DIVIDER) (((DIVIDER) == RCC_APB3_DIV1) || \
((DIVIDER) == RCC_APB3_DIV2) || \
@@ -744,9 +744,9 @@
/** @defgroup RCC_PLL12_Clock_Source RCC_PLL12_Clock_Source
* @{
*/
-#define RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0
-#define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1
-#define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_2
+#define RCC_PLL12SOURCE_HSI 0U
+#define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_0
+#define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_1
#define IS_RCC_PLL12SOURCE(SOURCE) (((SOURCE) == RCC_PLL12SOURCE_HSI) || \
((SOURCE) == RCC_PLL12SOURCE_HSE) || \
@@ -759,10 +759,10 @@
/** @defgroup RCC_PLL3_Clock_Source RCC_PLL3_Clock_Source
* @{
*/
-#define RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0
-#define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1
-#define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2
-#define RCC_PLL3SOURCE_OFF RCC_RCK3SELR_PLL3SRC_3
+#define RCC_PLL3SOURCE_HSI 0U
+#define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_0
+#define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_1
+#define RCC_PLL3SOURCE_OFF (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0)
#define IS_RCC_PLL3SOURCE(SOURCE) (((SOURCE) == RCC_PLL3SOURCE_HSI) || \
@@ -778,10 +778,10 @@
/** @defgroup RCC_PLL4_Clock_Source RCC_PLL4_Clock_Source
* @{
*/
-#define RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0
-#define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1
-#define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2
-#define RCC_PLL4SOURCE_I2S_CKIN RCC_RCK4SELR_PLL4SRC_3
+#define RCC_PLL4SOURCE_HSI 0U
+#define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_0
+#define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_1
+#define RCC_PLL4SOURCE_I2S_CKIN (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0)
#define IS_RCC_PLL4SOURCE(SOURCE) (((SOURCE) == RCC_PLL4SOURCE_HSI) || \
@@ -911,8 +911,8 @@
/** @defgroup RCC_PLL3_IF_Range RCC_PLL3_IF_Range
* @{
*/
-#define RCC_PLL3IFRANGE_0 RCC_PLL3CFGR1_IFRGE_0
-#define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_1
+#define RCC_PLL3IFRANGE_0 0U
+#define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_0
/**
* @}
*/
@@ -920,8 +920,8 @@
/** @defgroup RCC_PLL4_IF_Range RCC_PLL4_IF_Range
* @{
*/
-#define RCC_PLL4IFRANGE_0 RCC_PLL4CFGR1_IFRGE_0
-#define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_1
+#define RCC_PLL4IFRANGE_0 0U
+#define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_0
/**
* @}
*/
@@ -930,10 +930,10 @@
/** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source
* @{
*/
-#define RCC_RTCCLKSOURCE_OFF RCC_BDCR_RTCSRC_0 /* No clock (default after backup domain reset)*/
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_1
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_2
-#define RCC_RTCCLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /* HSE clock divided by RTCDIV value is used as RTC clock*/
+#define RCC_RTCCLKSOURCE_OFF 0U /* No clock (default after backup domain reset)*/
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_0
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_1
+#define RCC_RTCCLKSOURCE_HSE_DIV (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0) /* HSE clock divided by RTCDIV value is used as RTC clock*/
#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_OFF) || ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV))
@@ -1117,10 +1117,10 @@
/** @defgroup RCC_LSEDrive_Config RCC_LSEDrive_Config
* @{
*/
-#define RCC_LSEDRIVE_LOW RCC_BDCR_LSEDRV_0 /*!< LSE low drive capability */
-#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< LSE medium low drive capability */
-#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_2 /*!< LSE medium high drive capability */
-#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV_3 /*!< LSE high drive capability */
+#define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0) /*!< LSE high drive capability */
#define IS_RCC_LSEDRIVE(VALUE) (((VALUE) == RCC_LSEDRIVE_LOW) || ((VALUE) == RCC_LSEDRIVE_MEDIUMLOW) || \
((VALUE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((VALUE) == RCC_LSEDRIVE_HIGH))
@@ -1285,7 +1285,6 @@
#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST)
#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST)
#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_DTSRST)
-#define __HAL_RCC_PMBCTRL_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_PMBCTRLRST)
#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU)
#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST)
@@ -1296,7 +1295,6 @@
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST)
#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST)
#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_DTSRST)
-#define __HAL_RCC_PMBCTRL_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_PMBCTRLRST)
/** @brief Force or release the AHB2 peripheral reset. */
#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U)
@@ -1460,187 +1458,185 @@
/** @brief Enable or disable the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN)
-#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN)
-#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN)
-#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN)
-#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN)
-#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN)
-#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN)
-#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN)
-#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN)
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN)
-#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN)
-#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN)
-#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN)
-#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN)
-#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN)
-#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN)
-#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN)
-#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN)
-#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN)
-#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN)
-#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN)
-#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN)
-#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN)
-#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN)
-#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN)
-#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN)
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART2EN)
+#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART3EN)
+#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART4EN)
+#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART5EN)
+#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART7EN)
+#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_CECEN)
+#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_MDIOSEN)
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN)
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN)
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN)
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN)
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN)
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN)
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN)
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN)
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN)
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN)
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN)
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN)
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN)
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN)
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN)
-#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN)
-#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN)
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN)
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN)
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN)
-#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN)
-#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN)
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN)
-#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN)
-#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART5EN)
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_MDIOSEN)
/** @brief Enable or disable the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN)
-#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN)
-#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN)
-#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN)
-#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN)
-#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN)
-#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN)
-#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN)
-#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN)
-#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN)
-#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN)
-#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN)
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN)
-#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN)
-#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN)
+#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_FDCANEN)
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN)
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN)
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN)
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN)
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN)
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN)
-#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN)
-#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN)
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN)
-#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN)
-#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN)
-#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN)
-#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN)
-#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN)
-#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN)
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_FDCANEN)
/** @brief Enable or disable the APB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN)
-#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN)
-#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN)
-#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN)
-#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN)
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN)
-#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN)
-#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN)
-#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN)
-#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN)
+#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_VREFEN)
+#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_DTSEN)
+#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_HDPEN)
-#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN)
-#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN)
-#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN)
-#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN)
-#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN)
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN)
-#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN)
-#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN)
-#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN)
-#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_VREFEN)
+#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_DTSEN)
+#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_HDPEN)
/** @brief Enable or disable the APB4 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN)
-#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN)
-#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN)
+#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DDRPERFMEN)
#define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN)
-#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN)
-#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN)
+#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_STGENROEN)
-#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN)
-#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN)
-#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN)
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DDRPERFMEN)
#define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN)
-#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN)
-#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN)
+#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_STGENROEN)
/** @brief Enable or disable the APB5 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN)
-#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN)
-#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN)
-#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN)
-#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN)
-#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN)
-#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN)
+#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZPCEN)
#define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN)
-#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN)
-#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN)
+#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_STGENEN)
-#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN)
-#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN)
-#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN)
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN)
-#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN)
-#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN)
-#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN)
-#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN)
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZPCEN)
#define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN)
-#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN)
-#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN)
+#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_STGENEN)
/** @brief Enable or disable the AHB5 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN)
+#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_GPIOZEN)
#if defined(CRYP1)
-#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN)
+#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_CRYP1EN)
#endif
-#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN)
-#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN)
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN)
+#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_HASH1EN)
+#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_RNG1EN)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_BKPSRAMEN)
#define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN)
#if defined(CRYP1)
@@ -1653,116 +1649,116 @@
/** @brief Enable or disable the AHB6 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN)
-#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN)
-#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN)
-#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN)
-#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN)
-#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN)
-#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN)
-#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN)
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN)
-#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN)
-#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN)
-#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN)
+#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_USBHEN)
-#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN)
-#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN)
-#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN)
-#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN)
-#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN)
-#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN)
-#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN)
-#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN)
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN)
-#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN)
-#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN)
-#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN)
+#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_USBHEN)
/** @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN)
-#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN)
-#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN)
-#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN)
-#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN)
-#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN)
+#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_SDMMC3EN)
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN)
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN)
-#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN)
-#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN)
-#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN)
-#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN)
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_SDMMC3EN)
/** @brief Enable or disable the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN)
+#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_DCMIEN)
#if defined(CRYP2)
-#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN)
+#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRYP2EN)
#endif
-#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN)
-#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN)
-#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN)
-#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN)
-#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN)
+#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_IPCCEN)
-#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_DCMIEN)
#if defined(CRYP2)
-#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN)
+#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRYP2EN)
#endif
-#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN)
-#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN)
-#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN)
-#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN)
-#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN)
+#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_IPCCEN)
/** @brief Enable or disable the AHB4 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN)
-#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN)
-#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN)
-#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN)
-#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN)
-#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN)
-#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN)
-#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN)
-#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN)
+#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOKEN)
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN)
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN)
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN)
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN)
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN)
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN)
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN)
-#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN)
-#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN)
-#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN)
-#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN)
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOKEN)
/** @brief Enable or disable the MLAHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
- * using it. It shall be used to allocate a peripheral to the MCU.
+ * using it. It shall be used to allocate a peripheral to the MPU.
*/
-#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN)
+#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MP_MLAHBENSETR_RETRAMEN)
-#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN)
+#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MP_MLAHBENCLRR_RETRAMEN)
/** @brief MCU reset
* @note It generates a reset of the MCU core
@@ -1786,59 +1782,59 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN)
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN)
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN)
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN)
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN)
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN)
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN)
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN)
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN)
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN)
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN)
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN)
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN)
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN)
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN)
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN)
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN)
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN)
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN)
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN)
-#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN)
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN)
-#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN)
-#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN)
-#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN)
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_MDIOSLPEN)
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN)
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN)
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN)
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN)
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN)
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN)
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN)
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN)
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN)
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN)
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN)
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN)
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN)
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN)
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN)
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN)
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN)
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN)
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN)
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN)
-#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN)
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN)
-#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN)
-#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN)
-#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN)
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_MDIOSLPEN)
/** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode.
@@ -1847,37 +1843,37 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN)
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN)
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN)
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN)
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN)
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN)
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN)
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN)
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN)
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN)
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN)
-#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN)
-#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN)
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_FDCANLPEN)
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN)
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN)
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN)
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN)
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN)
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN)
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN)
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN)
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN)
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN)
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN)
-#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN)
-#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN)
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_FDCANLPEN)
/** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode.
@@ -1886,25 +1882,23 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN)
-#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN)
-#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN)
-#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN)
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN)
-#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN)
-#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN)
-#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_DTSLPEN)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN)
-#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN)
-#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN)
-#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN)
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN)
-#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN)
-#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN)
-#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_DTSLPEN)
/** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -1912,21 +1906,21 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN)
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN)
-#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DDRPERFMLPEN)
#define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2APBLPEN)
-#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN)
-#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN)
-#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROSTPEN)
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN)
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN)
-#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DDRPERFMLPEN)
#define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2APBLPEN)
-#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN)
-#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN)
-#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROSTPEN)
/** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -1934,27 +1928,27 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN)
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN)
-#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN)
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN)
-#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN)
-#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN)
-#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN)
-#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN)
-#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_STGENLPEN)
-#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN)
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN)
-#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN)
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN)
-#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN)
-#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN)
-#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN)
-#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN)
-#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_STGENLPEN)
/** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode.
@@ -1963,21 +1957,21 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN)
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_GPIOZLPEN)
#if defined(CRYP1)
-#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_CRYP1LPEN)
#endif
-#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN)
-#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN)
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN)
+#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_BKPSRAMLPEN)
-#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN)
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_GPIOZLPEN)
#if defined(CRYP1)
-#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_CRYP1LPEN)
#endif
-#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN)
-#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN)
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN)
+#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN)
/** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode.
@@ -1986,31 +1980,31 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN)
-#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN)
-#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN)
-#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN)
-#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN)
-#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN)
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN)
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN)
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN)
-#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN)
-#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN)
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_USBHLPEN)
-#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN)
-#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN)
-#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN)
-#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN)
-#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN)
-#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN)
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN)
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN)
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN)
-#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN)
-#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN)
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_USBHLPEN)
/** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode.
@@ -2019,19 +2013,19 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN)
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN)
-#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN)
-#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN)
-#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN)
-#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN)
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_SDMMC3LPEN)
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN)
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN)
-#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN)
-#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN)
-#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN)
-#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN)
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_SDMMC3LPEN)
/** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -2039,25 +2033,25 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN)
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_DCMILPEN)
#if defined(CRYP2)
-#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRYP2LPEN)
#endif
-#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN)
-#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN)
-#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN)
-#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN)
-#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN)
+#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_IPCCLPEN)
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN)
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_DCMILPEN)
#if defined(CRYP2)
-#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRYP2LPEN)
#endif
-#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN)
-#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN)
-#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN)
-#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN)
-#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN)
+#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_IPCCLPEN)
/** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode.
@@ -2066,29 +2060,29 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN)
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN)
-#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN)
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOKLPEN)
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN)
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN)
-#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN)
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOKLPEN)
/** @brief Enable or disable the AXI peripheral clock during CSLEEP mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -2096,9 +2090,9 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN)
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MP_AXIMLPENSETR_SYSRAMLPEN)
-#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN)
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MP_AXIMLPENCLRR_SYSRAMLPEN)
/** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode.
@@ -2107,9 +2101,9 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during CSLEEP mode.
*/
-#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN)
+#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MP_MLAHBLPENSETR_RETRAMLPEN)
-#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN)
+#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MP_MLAHBLPENCLRR_RETRAMLPEN)
@@ -2231,7 +2225,6 @@
#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN)
#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN)
#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN)
-#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN)
#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN)
#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN)
@@ -2242,7 +2235,6 @@
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN)
#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN)
#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN)
-#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN)
#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN)
/** @brief Enable or disable the APB4 peripheral clock.
@@ -2554,7 +2546,6 @@
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN)
#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN)
#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN)
-#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN)
#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN)
#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN)
@@ -2564,7 +2555,6 @@
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN)
#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN)
#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN)
-#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN)
/** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc_ex.h
index 0c555f8..915255e 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rcc_ex.h
@@ -355,10 +355,10 @@
/** @defgroup RCCEx_I2C12_Clock_Source I2C12 Clock Source
* @{
*/
-#define RCC_I2C12CLKSOURCE_PCLK1 RCC_I2C12CKSELR_I2C12SRC_0
-#define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_1
-#define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_2
-#define RCC_I2C12CLKSOURCE_CSI RCC_I2C12CKSELR_I2C12SRC_3
+#define RCC_I2C12CLKSOURCE_PCLK1 0U
+#define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_0
+#define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_1
+#define RCC_I2C12CLKSOURCE_CSI (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0)
#define IS_RCC_I2C12CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1) || \
@@ -372,10 +372,10 @@
/** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source
* @{
*/
-#define RCC_I2C35CLKSOURCE_PCLK1 RCC_I2C35CKSELR_I2C35SRC_0
-#define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_1
-#define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_2
-#define RCC_I2C35CLKSOURCE_CSI RCC_I2C35CKSELR_I2C35SRC_3
+#define RCC_I2C35CLKSOURCE_PCLK1 0U
+#define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_0
+#define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_1
+#define RCC_I2C35CLKSOURCE_CSI (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0)
#define IS_RCC_I2C35CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \
@@ -390,10 +390,10 @@
/** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source
* @{
*/
-#define RCC_I2C46CLKSOURCE_PCLK5 RCC_I2C46CKSELR_I2C46SRC_0
-#define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_1
-#define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_2
-#define RCC_I2C46CLKSOURCE_CSI RCC_I2C46CKSELR_I2C46SRC_3
+#define RCC_I2C46CLKSOURCE_PCLK5 0U
+#define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_0
+#define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_1
+#define RCC_I2C46CLKSOURCE_CSI (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0)
#define IS_RCC_I2C46CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5) || \
@@ -407,11 +407,11 @@
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
* @{
*/
-#define RCC_SAI1CLKSOURCE_PLL4 RCC_SAI1CKSELR_SAI1SRC_0
-#define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_1
-#define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_2
-#define RCC_SAI1CLKSOURCE_PER RCC_SAI1CKSELR_SAI1SRC_3
-#define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_4
+#define RCC_SAI1CLKSOURCE_PLL4 0U
+#define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_0
+#define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_1
+#define RCC_SAI1CLKSOURCE_PER (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_2
#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4) || \
@@ -427,12 +427,12 @@
/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
* @{
*/
-#define RCC_SAI2CLKSOURCE_PLL4 RCC_SAI2CKSELR_SAI2SRC_0
-#define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_1
-#define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_2
-#define RCC_SAI2CLKSOURCE_PER RCC_SAI2CKSELR_SAI2SRC_3
-#define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_4
-#define RCC_SAI2CLKSOURCE_PLL3_R RCC_SAI2CKSELR_SAI2SRC_5
+#define RCC_SAI2CLKSOURCE_PLL4 0U
+#define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_0
+#define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_1
+#define RCC_SAI2CLKSOURCE_PER (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_2
+#define RCC_SAI2CLKSOURCE_PLL3_R (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0)
#define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \
@@ -449,11 +449,11 @@
/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
* @{
*/
-#define RCC_SAI3CLKSOURCE_PLL4 RCC_SAI3CKSELR_SAI3SRC_0
-#define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_1
-#define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_2
-#define RCC_SAI3CLKSOURCE_PER RCC_SAI3CKSELR_SAI3SRC_3
-#define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_4
+#define RCC_SAI3CLKSOURCE_PLL4 0U
+#define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_0
+#define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_1
+#define RCC_SAI3CLKSOURCE_PER (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0)
+#define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_2
#define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4) || \
@@ -469,11 +469,11 @@
/** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source
* @{
*/
-#define RCC_SAI4CLKSOURCE_PLL4 RCC_SAI4CKSELR_SAI4SRC_0
-#define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_1
-#define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_2
-#define RCC_SAI4CLKSOURCE_PER RCC_SAI4CKSELR_SAI4SRC_3
-#define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_4
+#define RCC_SAI4CLKSOURCE_PLL4 0U
+#define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_0
+#define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_1
+#define RCC_SAI4CLKSOURCE_PER (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0)
+#define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_2
#define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4) || \
@@ -489,11 +489,11 @@
/** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source
* @{
*/
-#define RCC_SPI1CLKSOURCE_PLL4 RCC_SPI2S1CKSELR_SPI1SRC_0
-#define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_1
-#define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_2
-#define RCC_SPI1CLKSOURCE_PER RCC_SPI2S1CKSELR_SPI1SRC_3
-#define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_4
+#define RCC_SPI1CLKSOURCE_PLL4 0U
+#define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_0
+#define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_1
+#define RCC_SPI1CLKSOURCE_PER (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0)
+#define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_2
#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4) || \
@@ -508,11 +508,11 @@
/** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source
* @{
*/
-#define RCC_SPI23CLKSOURCE_PLL4 RCC_SPI2S23CKSELR_SPI23SRC_0
-#define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_1
-#define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_2
-#define RCC_SPI23CLKSOURCE_PER RCC_SPI2S23CKSELR_SPI23SRC_3
-#define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_4
+#define RCC_SPI23CLKSOURCE_PLL4 0U
+#define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_0
+#define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_1
+#define RCC_SPI23CLKSOURCE_PER (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0)
+#define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_2
#define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4) || \
@@ -527,11 +527,11 @@
/** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source
* @{
*/
-#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CKSELR_SPI45SRC_0
-#define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_1
-#define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_2
-#define RCC_SPI45CLKSOURCE_CSI RCC_SPI45CKSELR_SPI45SRC_3
-#define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_4
+#define RCC_SPI45CLKSOURCE_PCLK2 0U
+#define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_0
+#define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_1
+#define RCC_SPI45CLKSOURCE_CSI (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0)
+#define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_2
#define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \
@@ -546,12 +546,12 @@
/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
* @{
*/
-#define RCC_SPI6CLKSOURCE_PCLK5 RCC_SPI6CKSELR_SPI6SRC_0
-#define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_1
-#define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_2
-#define RCC_SPI6CLKSOURCE_CSI RCC_SPI6CKSELR_SPI6SRC_3
-#define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_4
-#define RCC_SPI6CLKSOURCE_PLL3 RCC_SPI6CKSELR_SPI6SRC_5
+#define RCC_SPI6CLKSOURCE_PCLK5 0U
+#define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_0
+#define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_1
+#define RCC_SPI6CLKSOURCE_CSI (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0)
+#define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_2
+#define RCC_SPI6CLKSOURCE_PLL3 (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0)
#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \
@@ -568,12 +568,12 @@
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
* @{
*/
-#define RCC_USART1CLKSOURCE_PCLK5 RCC_UART1CKSELR_UART1SRC_0
-#define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_1
-#define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_2
-#define RCC_USART1CLKSOURCE_CSI RCC_UART1CKSELR_UART1SRC_3
-#define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_4
-#define RCC_USART1CLKSOURCE_HSE RCC_UART1CKSELR_UART1SRC_5
+#define RCC_USART1CLKSOURCE_PCLK5 0U
+#define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_0
+#define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_1
+#define RCC_USART1CLKSOURCE_CSI (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0)
+#define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_2
+#define RCC_USART1CLKSOURCE_HSE (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0)
#define IS_RCC_USART1CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \
@@ -589,11 +589,11 @@
/** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source
* @{
*/
-#define RCC_UART24CLKSOURCE_PCLK1 RCC_UART24CKSELR_UART24SRC_0
-#define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_1
-#define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_2
-#define RCC_UART24CLKSOURCE_CSI RCC_UART24CKSELR_UART24SRC_3
-#define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_4
+#define RCC_UART24CLKSOURCE_PCLK1 0U
+#define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_0
+#define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_1
+#define RCC_UART24CLKSOURCE_CSI (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0)
+#define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_2
#define IS_RCC_UART24CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \
@@ -608,11 +608,11 @@
/** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source
* @{
*/
-#define RCC_UART35CLKSOURCE_PCLK1 RCC_UART35CKSELR_UART35SRC_0
-#define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_1
-#define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_2
-#define RCC_UART35CLKSOURCE_CSI RCC_UART35CKSELR_UART35SRC_3
-#define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_4
+#define RCC_UART35CLKSOURCE_PCLK1 0U
+#define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_0
+#define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_1
+#define RCC_UART35CLKSOURCE_CSI (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0)
+#define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_2
#define IS_RCC_UART35CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \
@@ -627,11 +627,11 @@
/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source
* @{
*/
-#define RCC_USART6CLKSOURCE_PCLK2 RCC_UART6CKSELR_UART6SRC_0
-#define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_1
-#define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_2
-#define RCC_USART6CLKSOURCE_CSI RCC_UART6CKSELR_UART6SRC_3
-#define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_4
+#define RCC_USART6CLKSOURCE_PCLK2 0U
+#define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_0
+#define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_1
+#define RCC_USART6CLKSOURCE_CSI (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0)
+#define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_2
#define IS_RCC_USART6CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
@@ -646,11 +646,11 @@
/** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source
* @{
*/
-#define RCC_UART78CLKSOURCE_PCLK1 RCC_UART78CKSELR_UART78SRC_0
-#define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_1
-#define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_2
-#define RCC_UART78CLKSOURCE_CSI RCC_UART78CKSELR_UART78SRC_3
-#define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_4
+#define RCC_UART78CLKSOURCE_PCLK1 0U
+#define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_0
+#define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_1
+#define RCC_UART78CLKSOURCE_CSI (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0)
+#define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_2
#define IS_RCC_UART78CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \
@@ -665,10 +665,10 @@
/** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source
* @{
*/
-#define RCC_SDMMC12CLKSOURCE_HCLK6 RCC_SDMMC12CKSELR_SDMMC12SRC_0
-#define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_1
-#define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_2
-#define RCC_SDMMC12CLKSOURCE_HSI RCC_SDMMC12CKSELR_SDMMC12SRC_3
+#define RCC_SDMMC12CLKSOURCE_HCLK6 0U
+#define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_0
+#define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_1
+#define RCC_SDMMC12CLKSOURCE_HSI (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0)
#define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \
@@ -682,10 +682,10 @@
/** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source
* @{
*/
-#define RCC_SDMMC3CLKSOURCE_HCLK2 RCC_SDMMC3CKSELR_SDMMC3SRC_0
-#define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_1
-#define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_2
-#define RCC_SDMMC3CLKSOURCE_HSI RCC_SDMMC3CKSELR_SDMMC3SRC_3
+#define RCC_SDMMC3CLKSOURCE_HCLK2 0U
+#define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_0
+#define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_1
+#define RCC_SDMMC3CLKSOURCE_HSI (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0)
#define IS_RCC_SDMMC3CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \
@@ -699,9 +699,9 @@
/** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source
* @{
*/
-#define RCC_ETHCLKSOURCE_PLL4 RCC_ETHCKSELR_ETHSRC_0
-#define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_1
-#define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_2
+#define RCC_ETHCLKSOURCE_PLL4 0U
+#define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_0
+#define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1
#define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4) || \
@@ -715,22 +715,22 @@
/** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider
* @{
*/
-#define RCC_ETHPTPDIV_1 RCC_ETHCKSELR_ETHPTPDIV_0 /*Bypass (default after reset*/
-#define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 2*/
-#define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 3*/
-#define RCC_ETHPTPDIV_4 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 4*/
-#define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_4 /*Division by 5*/
-#define RCC_ETHPTPDIV_6 RCC_ETHCKSELR_ETHPTPDIV_5 /*Division by 6*/
-#define RCC_ETHPTPDIV_7 RCC_ETHCKSELR_ETHPTPDIV_6 /*Division by 7*/
-#define RCC_ETHPTPDIV_8 RCC_ETHCKSELR_ETHPTPDIV_7 /*Division by 8*/
-#define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_8 /*Division by 9*/
-#define RCC_ETHPTPDIV_10 RCC_ETHCKSELR_ETHPTPDIV_9 /*Division by 10*/
-#define RCC_ETHPTPDIV_11 RCC_ETHCKSELR_ETHPTPDIV_10 /*Division by 11*/
-#define RCC_ETHPTPDIV_12 RCC_ETHCKSELR_ETHPTPDIV_11 /*Division by 12*/
-#define RCC_ETHPTPDIV_13 RCC_ETHCKSELR_ETHPTPDIV_12 /*Division by 13*/
-#define RCC_ETHPTPDIV_14 RCC_ETHCKSELR_ETHPTPDIV_13 /*Division by 14*/
-#define RCC_ETHPTPDIV_15 RCC_ETHCKSELR_ETHPTPDIV_14 /*Division by 15*/
-#define RCC_ETHPTPDIV_16 RCC_ETHCKSELR_ETHPTPDIV_15 /*Division by 16*/
+#define RCC_ETHPTPDIV_1 0U /*Bypass (default after reset*/
+#define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_0 /*Division by 2*/
+#define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 3*/
+#define RCC_ETHPTPDIV_4 (RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 4*/
+#define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 5*/
+#define RCC_ETHPTPDIV_6 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 6*/
+#define RCC_ETHPTPDIV_7 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 7*/
+#define RCC_ETHPTPDIV_8 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 8*/
+#define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 9*/
+#define RCC_ETHPTPDIV_10 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 10*/
+#define RCC_ETHPTPDIV_11 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 11*/
+#define RCC_ETHPTPDIV_12 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 12*/
+#define RCC_ETHPTPDIV_13 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2) /*Division by 13*/
+#define RCC_ETHPTPDIV_14 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 14*/
+#define RCC_ETHPTPDIV_15 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 15*/
+#define RCC_ETHPTPDIV_16 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 16*/
#define IS_RCC_ETHPTPDIV(SOURCE) (((SOURCE) == RCC_ETHPTPDIV_1) || \
@@ -757,10 +757,10 @@
/** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source
* @{
*/
-#define RCC_QSPICLKSOURCE_ACLK RCC_QSPICKSELR_QSPISRC_0
-#define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_1
-#define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_2
-#define RCC_QSPICLKSOURCE_PER RCC_QSPICKSELR_QSPISRC_3
+#define RCC_QSPICLKSOURCE_ACLK 0U
+#define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_0
+#define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_1
+#define RCC_QSPICLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0)
#define IS_RCC_QSPICLKSOURCE(SOURCE) \
(((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \
@@ -774,10 +774,10 @@
/** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source
* @{
*/
-#define RCC_FMCCLKSOURCE_ACLK RCC_FMCCKSELR_FMCSRC_0
-#define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_1
-#define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_2
-#define RCC_FMCCLKSOURCE_PER RCC_FMCCKSELR_FMCSRC_3
+#define RCC_FMCCLKSOURCE_ACLK 0U
+#define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_0
+#define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_1
+#define RCC_FMCCLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0)
#define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK) || \
((SOURCE) == RCC_FMCCLKSOURCE_PLL3) || \
@@ -791,10 +791,10 @@
/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
* @{
*/
-#define RCC_FDCANCLKSOURCE_HSE RCC_FDCANCKSELR_FDCANSRC_0
-#define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_1
-#define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_2
-#define RCC_FDCANCLKSOURCE_PLL4_R RCC_FDCANCKSELR_FDCANSRC_3
+#define RCC_FDCANCLKSOURCE_HSE 0U
+#define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_0
+#define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_1
+#define RCC_FDCANCLKSOURCE_PLL4_R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0)
@@ -811,9 +811,9 @@
/** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source
* @{
*/
-#define RCC_SPDIFRXCLKSOURCE_PLL4 RCC_SPDIFCKSELR_SPDIFSRC_0
-#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_1
-#define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_2
+#define RCC_SPDIFRXCLKSOURCE_PLL4 0U
+#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_0
+#define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1
#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \
(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4) || \
@@ -826,9 +826,9 @@
/** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source
* @{
*/
-#define RCC_CECCLKSOURCE_LSE RCC_CECCKSELR_CECSRC_0
-#define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_1
-#define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_2
+#define RCC_CECCLKSOURCE_LSE 0U
+#define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0
+#define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1
#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
@@ -840,9 +840,9 @@
/** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source
* @{
*/
-#define RCC_USBPHYCLKSOURCE_HSE RCC_USBCKSELR_USBPHYSRC_0
-#define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_1
-#define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_2
+#define RCC_USBPHYCLKSOURCE_HSE 0U
+#define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_0
+#define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1
#define IS_RCC_USBPHYCLKSOURCE(SOURCE) \
(((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \
@@ -855,8 +855,8 @@
/** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source
* @{
*/
-#define RCC_USBOCLKSOURCE_PLL4 RCC_USBCKSELR_USBOSRC_0
-#define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC_1
+#define RCC_USBOCLKSOURCE_PLL4 0U
+#define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC
#define IS_RCC_USBOCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \
((SOURCE) == RCC_USBOCLKSOURCE_PHY))
@@ -868,10 +868,10 @@
/** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source
* @{
*/
-#define RCC_RNG1CLKSOURCE_CSI RCC_RNG1CKSELR_RNG1SRC_0
-#define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_1
-#define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_2
-#define RCC_RNG1CLKSOURCE_LSI RCC_RNG1CKSELR_RNG1SRC_3
+#define RCC_RNG1CLKSOURCE_CSI 0U
+#define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_0
+#define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_1
+#define RCC_RNG1CLKSOURCE_LSI (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0)
#define IS_RCC_RNG1CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG1CLKSOURCE_CSI) || \
((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \
@@ -886,10 +886,10 @@
/** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source
* @{
*/
-#define RCC_RNG2CLKSOURCE_CSI RCC_RNG2CKSELR_RNG2SRC_0
-#define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_1
-#define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_2
-#define RCC_RNG2CLKSOURCE_LSI RCC_RNG2CKSELR_RNG2SRC_3
+#define RCC_RNG2CLKSOURCE_CSI 0U
+#define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_0
+#define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_1
+#define RCC_RNG2CLKSOURCE_LSI (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0)
#define IS_RCC_RNG2CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG2CLKSOURCE_CSI) || \
((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \
@@ -904,10 +904,10 @@
/** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source
* @{
*/
-#define RCC_CKPERCLKSOURCE_HSI RCC_CPERCKSELR_CKPERSRC_0
-#define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_1
-#define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_2
-#define RCC_CKPERCLKSOURCE_OFF RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/
+#define RCC_CKPERCLKSOURCE_HSI 0U
+#define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0
+#define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1
+#define RCC_CKPERCLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/
#define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \
((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \
@@ -921,9 +921,9 @@
/** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source
* @{
*/
-#define RCC_STGENCLKSOURCE_HSI RCC_STGENCKSELR_STGENSRC_0
-#define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_1
-#define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_2
+#define RCC_STGENCLKSOURCE_HSI 0U
+#define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0
+#define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1
#define IS_RCC_STGENCLKSOURCE(SOURCE) \
(((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \
@@ -937,8 +937,8 @@
/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
* @{
*/
-#define RCC_DSICLKSOURCE_PHY RCC_DSICKSELR_DSISRC_0
-#define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC_1
+#define RCC_DSICLKSOURCE_PHY 0U
+#define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC
#define IS_RCC_DSICLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
@@ -951,9 +951,9 @@
/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
* @{
*/
-#define RCC_ADCCLKSOURCE_PLL4 RCC_ADCCKSELR_ADCSRC_0
-#define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_1
-#define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_2
+#define RCC_ADCCLKSOURCE_PLL4 0U
+#define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0
+#define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_1
#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4) || \
((SOURCE) == RCC_ADCCLKSOURCE_PER) || \
@@ -966,13 +966,13 @@
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
* @{
*/
-#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CKSELR_LPTIM1SRC_0
-#define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_1
-#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_2
-#define RCC_LPTIM1CLKSOURCE_LSE RCC_LPTIM1CKSELR_LPTIM1SRC_3
-#define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_4
-#define RCC_LPTIM1CLKSOURCE_PER RCC_LPTIM1CKSELR_LPTIM1SRC_5
-#define RCC_LPTIM1CLKSOURCE_OFF RCC_LPTIM1CKSELR_LPTIM1SRC_6
+#define RCC_LPTIM1CLKSOURCE_PCLK1 0U
+#define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_0
+#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_1
+#define RCC_LPTIM1CLKSOURCE_LSE (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_2
+#define RCC_LPTIM1CLKSOURCE_PER (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define RCC_LPTIM1CLKSOURCE_OFF (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1)
#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \
(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
@@ -989,12 +989,12 @@
/** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source
* @{
*/
-#define RCC_LPTIM23CLKSOURCE_PCLK3 RCC_LPTIM23CKSELR_LPTIM23SRC_0
-#define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_1
-#define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_2
-#define RCC_LPTIM23CLKSOURCE_LSE RCC_LPTIM23CKSELR_LPTIM23SRC_3
-#define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_4
-#define RCC_LPTIM23CLKSOURCE_OFF RCC_LPTIM23CKSELR_LPTIM23SRC_5
+#define RCC_LPTIM23CLKSOURCE_PCLK3 0U
+#define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_0
+#define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_1
+#define RCC_LPTIM23CLKSOURCE_LSE (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)
+#define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_2
+#define RCC_LPTIM23CLKSOURCE_OFF (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)
#define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \
@@ -1011,13 +1011,13 @@
/** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source
* @{
*/
-#define RCC_LPTIM45CLKSOURCE_PCLK3 RCC_LPTIM45CKSELR_LPTIM45SRC_0
-#define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_1
-#define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_2
-#define RCC_LPTIM45CLKSOURCE_LSE RCC_LPTIM45CKSELR_LPTIM45SRC_3
-#define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_4
-#define RCC_LPTIM45CLKSOURCE_PER RCC_LPTIM45CKSELR_LPTIM45SRC_5
-#define RCC_LPTIM45CLKSOURCE_OFF RCC_LPTIM45CKSELR_LPTIM45SRC_6
+#define RCC_LPTIM45CLKSOURCE_PCLK3 0U
+#define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_0
+#define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_1
+#define RCC_LPTIM45CLKSOURCE_LSE (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_2
+#define RCC_LPTIM45CLKSOURCE_PER (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define RCC_LPTIM45CLKSOURCE_OFF (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1)
@@ -1037,8 +1037,8 @@
/** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection
* @{
*/
-#define RCC_TIMG1PRES_DEACTIVATED RCC_TIMG1PRER_TIMG1PRE_0
-#define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE_1
+#define RCC_TIMG1PRES_DEACTIVATED 0U
+#define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE
#define IS_RCC_TIMG1PRES(PRES) (((PRES) == RCC_TIMG1PRES_DEACTIVATED) || \
((PRES) == RCC_TIMG1PRES_ACTIVATED))
@@ -1050,8 +1050,8 @@
/** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection
* @{
*/
-#define RCC_TIMG2PRES_DEACTIVATED RCC_TIMG2PRER_TIMG2PRE_0
-#define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE_1
+#define RCC_TIMG2PRES_DEACTIVATED 0U
+#define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE
#define IS_RCC_TIMG2PRES(PRES) (((PRES) == RCC_TIMG2PRES_DEACTIVATED) || \
((PRES) == RCC_TIMG2PRES_ACTIVATED))
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rtc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rtc.h
index 5692065..41e055c 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rtc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_rtc.h
@@ -702,8 +702,6 @@
#elif defined(CORE_CA7)
-#else /* !CORE_CA7 */
-
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
@@ -724,6 +722,8 @@
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#else /* !CORE_CA7 */
+
#error Please #define CORE_CM4 or CORE_CA7
#endif
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sai.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sai.h
index c9b6c12..2a5b410 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sai.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sai.h
@@ -66,7 +66,7 @@
{
FunctionalState Activation; /*!< Enable/disable PDM interface */
uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
- This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
} SAI_PdmInitTypeDef;
@@ -113,9 +113,10 @@
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 63. */
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
@@ -152,6 +153,7 @@
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition
+ * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
* @{
*/
typedef struct
@@ -184,6 +186,8 @@
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition
+ * @note For SPDIF protocol, these parameters are not used (set by hardware).
+ * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
* @{
*/
typedef struct
@@ -285,17 +289,17 @@
/** @defgroup SAI_Error_Code SAI Error Code
* @{
*/
-#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */
-#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */
-#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */
-#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */
-#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */
-#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
-#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */
+#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-#define HAL_SAI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid callback error */
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif
/**
* @}
@@ -304,9 +308,9 @@
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{
*/
-#define SAI_SYNCEXT_DISABLE 0
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
+#define SAI_SYNCEXT_DISABLE 0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
/**
* @}
*/
@@ -314,8 +318,8 @@
/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
* @{
*/
-#define SAI_MCK_OUTPUT_DISABLE ((uint32_t)0x00000000U)
-#define SAI_MCK_OUTPUT_ENABLE ((uint32_t)SAI_xCR1_MCKEN)
+#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
+#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
/**
* @}
*/
@@ -323,11 +327,11 @@
/** @defgroup SAI_Protocol SAI Supported protocol
* @{
*/
-#define SAI_I2S_STANDARD 0
-#define SAI_I2S_MSBJUSTIFIED 1
-#define SAI_I2S_LSBJUSTIFIED 2
-#define SAI_PCM_LONG 3
-#define SAI_PCM_SHORT 4
+#define SAI_I2S_STANDARD 0U
+#define SAI_I2S_MSBJUSTIFIED 1U
+#define SAI_I2S_LSBJUSTIFIED 2U
+#define SAI_PCM_LONG 3U
+#define SAI_PCM_SHORT 4U
/**
* @}
*/
@@ -335,10 +339,10 @@
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
* @{
*/
-#define SAI_PROTOCOL_DATASIZE_16BIT 0
-#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
-#define SAI_PROTOCOL_DATASIZE_24BIT 2
-#define SAI_PROTOCOL_DATASIZE_32BIT 3
+#define SAI_PROTOCOL_DATASIZE_16BIT 0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT 2U
+#define SAI_PROTOCOL_DATASIZE_32BIT 3U
/**
* @}
*/
@@ -346,16 +350,16 @@
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
* @{
*/
-#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
-#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
-#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
-#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
-#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
-#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
-#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
-#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
-#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
-#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
+#define SAI_AUDIO_FREQUENCY_192K 192000U
+#define SAI_AUDIO_FREQUENCY_96K 96000U
+#define SAI_AUDIO_FREQUENCY_48K 48000U
+#define SAI_AUDIO_FREQUENCY_44K 44100U
+#define SAI_AUDIO_FREQUENCY_32K 32000U
+#define SAI_AUDIO_FREQUENCY_22K 22050U
+#define SAI_AUDIO_FREQUENCY_16K 16000U
+#define SAI_AUDIO_FREQUENCY_11K 11025U
+#define SAI_AUDIO_FREQUENCY_8K 8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
/**
* @}
*/
@@ -363,8 +367,8 @@
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
* @{
*/
-#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)
-#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)
+#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
+#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
/**
* @}
*/
@@ -372,9 +376,8 @@
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
* @{
*/
-#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)
-#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)
-
+#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
+#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
/**
* @}
*/
@@ -382,10 +385,10 @@
/** @defgroup SAI_Block_Mode SAI Block Mode
* @{
*/
-#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
-#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
-#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
-#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+#define SAI_MODEMASTER_TX 0x00000000U
+#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
+#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
+#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
/**
* @}
@@ -394,9 +397,9 @@
/** @defgroup SAI_Block_Protocol SAI Block Protocol
* @{
*/
-#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
-#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
-#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
+#define SAI_FREE_PROTOCOL 0x00000000U
+#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
+#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
/**
* @}
*/
@@ -404,12 +407,12 @@
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{
*/
-#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
-#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
-#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
-#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_8 SAI_xCR1_DS_1
+#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_16 SAI_xCR1_DS_2
+#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
+#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
/**
* @}
*/
@@ -417,8 +420,8 @@
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
* @{
*/
-#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
-#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
+#define SAI_FIRSTBIT_MSB 0x00000000U
+#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
/**
* @}
*/
@@ -426,8 +429,8 @@
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
* @{
*/
-#define SAI_CLOCKSTROBING_FALLINGEDGE 0
-#define SAI_CLOCKSTROBING_RISINGEDGE 1
+#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
+#define SAI_CLOCKSTROBING_RISINGEDGE 1U
/**
* @}
*/
@@ -435,10 +438,16 @@
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
* @{
*/
-#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */
-#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */
+#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
+#if defined(SAI3)
+#define SAI_SYNCHRONOUS_EXT_SAI3 4U /*!< Synchronous with other SAI, SAI3 */
+#endif
+#if defined(SAI4)
+#define SAI_SYNCHRONOUS_EXT_SAI4 5U /*!< Synchronous with other SAI, SAI4 */
+#endif
/**
* @}
*/
@@ -446,8 +455,8 @@
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
* @{
*/
-#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
-#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
+#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
/**
* @}
*/
@@ -455,8 +464,8 @@
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
* @{
*/
-#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
-#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
+#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
/**
* @}
*/
@@ -464,8 +473,8 @@
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{
*/
-#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
-#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
+#define SAI_FS_STARTFRAME 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
/**
* @}
*/
@@ -473,8 +482,8 @@
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
* @{
*/
-#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
-#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
+#define SAI_FS_ACTIVE_LOW 0x00000000U
+#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
/**
* @}
*/
@@ -482,8 +491,8 @@
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
* @{
*/
-#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
-#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
+#define SAI_FS_FIRSTBIT 0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
/**
* @}
*/
@@ -491,9 +500,9 @@
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{
*/
-#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
-#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
-#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+#define SAI_SLOTSIZE_DATASIZE 0x00000000U
+#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
+#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
/**
* @}
*/
@@ -501,24 +510,24 @@
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
* @{
*/
-#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
-#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
-#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
-#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
-#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
-#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
-#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
-#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
-#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
-#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
-#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
-#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
-#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
-#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
-#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
-#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
-#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
-#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
+#define SAI_SLOT_NOTACTIVE 0x00000000U
+#define SAI_SLOTACTIVE_0 0x00000001U
+#define SAI_SLOTACTIVE_1 0x00000002U
+#define SAI_SLOTACTIVE_2 0x00000004U
+#define SAI_SLOTACTIVE_3 0x00000008U
+#define SAI_SLOTACTIVE_4 0x00000010U
+#define SAI_SLOTACTIVE_5 0x00000020U
+#define SAI_SLOTACTIVE_6 0x00000040U
+#define SAI_SLOTACTIVE_7 0x00000080U
+#define SAI_SLOTACTIVE_8 0x00000100U
+#define SAI_SLOTACTIVE_9 0x00000200U
+#define SAI_SLOTACTIVE_10 0x00000400U
+#define SAI_SLOTACTIVE_11 0x00000800U
+#define SAI_SLOTACTIVE_12 0x00001000U
+#define SAI_SLOTACTIVE_13 0x00002000U
+#define SAI_SLOTACTIVE_14 0x00004000U
+#define SAI_SLOTACTIVE_15 0x00008000U
+#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
/**
* @}
*/
@@ -526,8 +535,8 @@
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
* @{
*/
-#define SAI_STEREOMODE ((uint32_t)0x00000000U)
-#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
+#define SAI_STEREOMODE 0x00000000U
+#define SAI_MONOMODE SAI_xCR1_MONO
/**
* @}
*/
@@ -535,8 +544,8 @@
/** @defgroup SAI_TRIState_Management SAI TRIState Management
* @{
*/
-#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
-#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
+#define SAI_OUTPUT_NOTRELEASED 0x00000000U
+#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
/**
* @}
*/
@@ -544,11 +553,11 @@
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
* @{
*/
-#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
-#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
-#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
+#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
+#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
+#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
/**
* @}
*/
@@ -556,11 +565,11 @@
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
* @{
*/
-#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)
-#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
-#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
-#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
-#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+#define SAI_NOCOMPANDING 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
+#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
+#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
+#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
/**
* @}
*/
@@ -568,8 +577,8 @@
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
* @{
*/
-#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)
-#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
+#define SAI_ZERO_VALUE 0x00000000U
+#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
/**
* @}
*/
@@ -577,13 +586,13 @@
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
* @{
*/
-#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
-#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
-#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
-#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
-#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
-#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
-#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
+#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
+#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
+#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
+#define SAI_IT_FREQ SAI_xIMR_FREQIE
+#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
+#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
+#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
/**
* @}
*/
@@ -591,13 +600,13 @@
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
* @{
*/
-#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
-#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
-#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
-#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
-#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
-#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
-#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
+#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
+#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
+#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
+#define SAI_FLAG_FREQ SAI_xSR_FREQ
+#define SAI_FLAG_CNRDY SAI_xSR_CNRDY
+#define SAI_FLAG_AFSDET SAI_xSR_AFSDET
+#define SAI_FLAG_LFSDET SAI_xSR_LFSDET
/**
* @}
*/
@@ -605,12 +614,12 @@
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
* @{
*/
-#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
-#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
-#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
-#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
-#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
-#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
+#define SAI_FIFOSTATUS_EMPTY 0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
+#define SAI_FIFOSTATUS_FULL 0x00050000U
/**
* @}
*/
@@ -815,7 +824,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup SAI_Private_Macros
+/** @defgroup SAI_Private_Macros SAI Private Macros
* @{
*/
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
@@ -842,7 +851,7 @@
#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
-#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
+#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U))
#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
(((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
@@ -869,10 +878,19 @@
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+#if defined(SAI3) && defined(SAI4)
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
+#else
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+#endif
#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
((VALUE) == SAI_MCK_OUTPUT_DISABLE))
@@ -883,7 +901,7 @@
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
((VALUE) == SAI_LAST_SENT_VALUE))
@@ -908,13 +926,13 @@
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
((SIZE) == SAI_SLOTSIZE_16B) || \
((SIZE) == SAI_SLOTSIZE_32B))
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
@@ -925,11 +943,11 @@
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63)
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
/**
* @}
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd.h
index 4b6f2ed..2ee5740 100755
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_SD_H
@@ -38,16 +38,16 @@
/** @defgroup SD SD
* @brief SD HAL module driver
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup SD_Exported_Types SD Exported Types
* @{
*/
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
* @{
- */
+ */
typedef enum
{
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
@@ -59,71 +59,71 @@
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
}HAL_SD_StateTypeDef;
-/**
+/**
* @}
*/
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
- */
+ */
typedef enum
{
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
+ HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
}HAL_SD_CardStateTypedef;
-/**
+/**
* @}
*/
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
* @{
*/
-#define SD_InitTypeDef SDMMC_InitTypeDef
+#define SD_InitTypeDef SDMMC_InitTypeDef
#define SD_TypeDef SDMMC_TypeDef
-/**
+/**
* @brief SD Card Information Structure definition
- */
+ */
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
-
+
uint32_t CardVersion; /*!< Specifies the card version */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
+
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
+
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
+
uint32_t CardSpeed; /*!< Specifies the card Speed */
-
+
}HAL_SD_CardInfoTypeDef;
-/**
+/**
* @brief SD handle Structure definition
*/
typedef struct __SD_HandleTypeDef
{
SD_TypeDef *Instance; /*!< SD registers base address */
-
+
SD_InitTypeDef Init; /*!< SD required parameters */
-
+
HAL_LockTypeDef Lock; /*!< SD locking object */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
@@ -131,19 +131,19 @@
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
-
+
__IO uint32_t Context; /*!< SD transfer context */
-
+
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
-
- __IO uint32_t ErrorCode; /*!< SD Card Error codes */
-
+
+ __IO uint32_t ErrorCode; /*!< SD Card Error codes */
+
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
-
+
uint32_t CSD[4]; /*!< SD card specific data table */
-
+
uint32_t CID[4]; /*!< SD card identification number table */
-
+
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
@@ -160,16 +160,16 @@
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
-#endif
+#endif
}SD_HandleTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
- */
+ */
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
@@ -210,7 +210,7 @@
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CardCSDTypedef;
-/**
+/**
* @}
*/
@@ -231,11 +231,11 @@
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CardCIDTypedef;
-/**
+/**
* @}
*/
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
* @{
*/
typedef struct
@@ -254,12 +254,12 @@
__IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
__IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
}HAL_SD_CardStatusTypedef;
-/**
+/**
* @}
*/
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
typedef enum
@@ -276,35 +276,35 @@
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
}HAL_SD_CallbackIDTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
* @{
*/
typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#endif
-/**
+/**
* @}
*/
#endif
-/**
+/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SD_Exported_Constants Exported Constants
* @{
- */
+ */
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
- */
+ */
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
@@ -313,12 +313,12 @@
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
@@ -330,36 +330,36 @@
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
-
-/**
+
+/**
* @}
*/
-
+
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
- */
+ */
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
/**
* @}
@@ -376,7 +376,7 @@
#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED ((uint32_t)0x00000003U)
-
+
/**
* @}
*/
@@ -393,7 +393,7 @@
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
@@ -412,10 +412,10 @@
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
#endif
-
+
/**
* @brief Enable the SD device interrupt.
- * @param __HANDLE__: SD Handle
+ * @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -447,7 +447,7 @@
/**
* @brief Disable the SD device interrupt.
- * @param __HANDLE__: SD Handle
+ * @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -478,9 +478,9 @@
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
- * @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to check.
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -517,8 +517,8 @@
/**
* @brief Clear the SD's pending flags.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -546,8 +546,8 @@
/**
* @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -585,7 +585,7 @@
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -614,7 +614,7 @@
/**
* @}
*/
-
+
/* Include SD HAL Extension module */
#include "stm32mp1xx_hal_sd_ex.h"
@@ -622,7 +622,7 @@
/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
-
+
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -634,7 +634,7 @@
/**
* @}
*/
-
+
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
@@ -676,7 +676,7 @@
/**
* @}
*/
-
+
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
@@ -684,7 +684,7 @@
/**
* @}
*/
-
+
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
@@ -697,7 +697,7 @@
/**
* @}
*/
-
+
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
@@ -706,7 +706,7 @@
/**
* @}
*/
-
+
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
@@ -715,7 +715,7 @@
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/** @defgroup SD_Private_Types SD Private Types
* @{
@@ -723,7 +723,7 @@
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup SD_Private_Defines SD Private Defines
@@ -732,8 +732,8 @@
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup SD_Private_Variables SD Private Variables
* @{
@@ -741,7 +741,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup SD_Private_Constants SD Private Constants
@@ -750,7 +750,7 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup SD_Private_Macros SD Private Macros
@@ -782,12 +782,12 @@
/**
* @}
- */
+ */
/**
* @}
*/
-
+
/**
* @}
*/
@@ -797,6 +797,6 @@
#endif
-#endif /* STM32MP1xx_HAL_SD_H */
+#endif /* STM32MP1xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd_ex.h
index 89d2b44..fd3f462 100755
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_sd_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_SDEX_H
@@ -35,7 +35,7 @@
/** @defgroup SDEx SDEx
* @brief SD HAL extended module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDEx_Exported_Types SDEx Exported Types
@@ -44,7 +44,7 @@
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
* @{
- */
+ */
typedef enum
{
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
@@ -53,20 +53,20 @@
}HAL_SDEx_DMABuffer_MemoryTypeDef;
-/**
+/**
* @}
*/
-
-/**
+
+/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
*/
-
+
/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
@@ -83,11 +83,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -95,7 +95,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+
/**
* @}
*/
@@ -108,6 +108,6 @@
#endif
-#endif /* stm32mp1xx_HAL_SDEX_H */
+#endif /* stm32mp1xx_HAL_SDEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard.h
new file mode 100644
index 0000000..aed79b0
--- /dev/null
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard.h
@@ -0,0 +1,1253 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_SMARTCARD_H
+#define STM32MP1xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
+ where usart_ker_ckpres is the USART input clock divided by a prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter @ref SMARTCARD_Word_Length can only be
+ set to 9 (8 data + 1 parity bits). */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note The parity is enabled by default (PCE is forced to 1).
+ Since the WordLength is forced to 8 bits + parity, M is
+ forced to 1 and the parity bit is the 9th bit. */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
+ is selected. Selecting the single sample method increases
+ the receiver tolerance to clock deviations. This parameter can be a value
+ of @ref SMARTCARD_OneBit_Sampling. */
+
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+ multiplied by 2 to give the division factor of the source clock frequency */
+
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFF */
+
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
+ This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
+
+} SMARTCARD_InitTypeDef;
+
+/**
+ * @brief SMARTCARD advanced features initialization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value
+ of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+} SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL SMARTCARD State definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates:
+ * gState and RxState (see @ref SMARTCARD_State_Definition).
+ * - gState contains SMARTCARD state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct __SMARTCARD_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
+ This parameter can be a value of
+ @ref SMARTCARDEx_FIFO_mode. */
+
+ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
+ Handle management and also related to Tx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
+
+ void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
+
+ void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
+
+ void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */
+
+ void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */
+
+ void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMARTCARD Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
+ HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
+ HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
+ HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
+ HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
+ HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
+ HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */
+ HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */
+
+ HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
+ HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Callback pointer definition
+ */
+typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief SMARTCARD clock sources
+ */
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK5 = 0x02U, /*!< PCLK5 clock source (only used by UART1) */
+ SMARTCARD_CLOCKSOURCE_PLL3Q = 0x40U, /*!< PLL3Q clock source */
+ SMARTCARD_CLOCKSOURCE_PLL4Q = 0x08U, /*!< PLL4Q clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x10U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */
+ SMARTCARD_CLOCKSOURCE_HSE = 0x40U, /*!< HSE clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x80U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x100U /*!< undefined clock source */
+} SMARTCARD_ClockSourceTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
+ * @{
+ */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
+ is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
+ use. Value is allowed for gState
+ and RxState */
+#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
+ process is ongoing Not to be used for
+ neither gState nor RxState.
+ Value is result of combination (Or)
+ between gState and RxState values */
+#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */
+#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+ * @{
+ */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+ * @{
+ */
+#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+ * @{
+ */
+#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler
+ * @{
+ */
+#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+ * @{
+ */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */
+#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */
+#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */
+#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle states.
+ * @param __HANDLE__ SMARTCARD handle.
+ * @retval None
+ */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/** @brief Flush the Smartcard Data registers.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
+ * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
+ * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
+ * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
+ * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
+ * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
+ * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
+ * @arg @ref SMARTCARD_FLAG_NE Noise error flag
+ * @arg @ref SMARTCARD_FLAG_FE Framing error flag
+ * @arg @ref SMARTCARD_FLAG_PE Parity error flag
+ * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
+ * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
+ * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
+ * guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
+ * time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (0x01UL << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\
+ ? SET : RESET)
+
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
+ * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
+ * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
+ * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
+ * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
+ * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x01U)?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x02U)?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) &\
+ (0x01UL << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific SMARTCARD request flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+ * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+/** @brief Report the SMARTCARD clock source.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK5: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK5; \
+ break; \
+ case RCC_USART1CLKSOURCE_PLL3: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_UART24_SOURCE()) \
+ { \
+ case RCC_UART24CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART24CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_UART35_SOURCE()) \
+ { \
+ case RCC_UART35CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART35CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART6CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+
+/** @brief Check the Baud rate range.
+ * @note The maximum Baud Rate is derived from the maximum clock on MP1 (100 MHz)
+ * divided by the oversampling used on the SMARTCARD (i.e. 16).
+ * @param __BAUDRATE__ Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__ block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__ number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
+
+/** @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__ SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/** @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__ SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/** @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__ SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__ SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+ || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/** @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__ SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__ SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__ SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/** @brief Ensure that SMARTCARD clock Prescaler is valid.
+ * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
+
+/** @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__ SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__ SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__ SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__ SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__ SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/** @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__ SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32mp1xx_hal_smartcard_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+ * @{
+ */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard_ex.h
new file mode 100644
index 0000000..c95e6fd
--- /dev/null
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_smartcard_ex.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_smartcard_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_SMARTCARD_EX_H
+#define STM32MP1xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+ * @{
+ */
+#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
+ * @brief SMARTCARD FIFO mode
+ * @{
+ */
+#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
+ * @brief SMARTCARD TXFIFO level
+ * @{
+ */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
+ * @brief SMARTCARD RXFIFO level
+ * @{
+ */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
+#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
+#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */
+#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
+#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5 bits)
+ * - XX : Interrupt source register (2 bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5 bits)
+ * @{
+ */
+#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */
+#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */
+#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
+
+#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
+#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
+
+#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */
+#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */
+#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */
+#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+ * @{
+ */
+
+/** @brief Set the Transmission Completion flag
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+ * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+ * to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+ * @retval None
+ */
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
+ { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } \
+ else \
+ { \
+ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+ } \
+ } while(0U)
+
+/** @brief Return the transmission completion flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+ * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+ * reported.
+ * @retval Transmission completion flag
+ */
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
+
+
+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+ * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
+ * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+ */
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
+ ((__TXCOMPLETE__) == SMARTCARD_TC))
+
+/** @brief Ensure that SMARTCARD FIFO mode is valid.
+ * @param __STATE__ SMARTCARD FIFO mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
+ ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
+
+/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
+
+/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart.h
index 083e3c3..341a3ed 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart.h
@@ -48,11 +48,15 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
- @note Oversampling by 8 is systematically applied to achieve high baud rates. */
+ Baud Rate Register[2:0] = (((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency (fclk)
+ divided by a prescaler.
+ @note Oversampling by 8 is systematically applied to
+ achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@@ -225,16 +229,17 @@
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -270,15 +275,6 @@
* @}
*/
-/** @defgroup USART_Over_Sampling USART Over Sampling
- * @{
- */
-#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
/** @defgroup USART_Clock USART Clock
* @{
*/
@@ -359,6 +355,7 @@
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
@@ -413,6 +410,7 @@
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@@ -444,10 +442,10 @@
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_USART_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -469,6 +467,7 @@
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@@ -489,6 +488,7 @@
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
@@ -554,9 +554,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@@ -576,10 +579,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -601,7 +606,9 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -623,10 +630,13 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
-
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
@@ -638,6 +648,7 @@
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
@@ -709,10 +720,12 @@
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+ (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
@@ -860,14 +873,6 @@
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
- * @brief Ensure that USART oversampling is valid.
- * @param __SAMPLING__ USART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-
-/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
@@ -947,7 +952,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -962,13 +968,16 @@
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart_ex.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart_ex.h
index 763c4da..1108d62 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart_ex.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_usart_ex.h
@@ -45,9 +45,9 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
@@ -130,45 +130,44 @@
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU; \
- } \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x0000U; \
- } \
-} while(0U)
-
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
/**
* @brief Ensure that USART frame length is valid.
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_adc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_adc.h
index 8a3980f..3f38789 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_adc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_adc.h
@@ -73,7 +73,8 @@
#define ADC_SQR3_REGOFFSET (0x00000200UL)
#define ADC_SQR4_REGOFFSET (0x00000300UL)
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
@@ -110,7 +111,8 @@
#define ADC_JDR3_REGOFFSET (0x00000200UL)
#define ADC_JDR4_REGOFFSET (0x00000300UL)
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
@@ -193,7 +195,8 @@
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+ | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
@@ -214,25 +217,26 @@
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
-#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+ ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
@@ -340,7 +344,8 @@
#define ADC_OFR2_REGOFFSET (0x00000001UL)
#define ADC_OFR3_REGOFFSET (0x00000002UL)
#define ADC_OFR4_REGOFFSET (0x00000003UL)
-#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+ | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
@@ -413,7 +418,7 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 serie, if ADC group injected is used, some
+ @note On this STM32 series, if ADC group injected is used, some
clock ratio constraints between ADC clock and AHB clock
must be respected. Refer to reference manual.
@@ -498,7 +503,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
@@ -558,7 +563,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
@@ -632,7 +637,7 @@
#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -665,7 +670,7 @@
#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -700,7 +705,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
@@ -1316,8 +1321,8 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
-/* - ADC calibration time: maximum delay is 16384/fADC. */
+/* STM32 series: */
+/* - ADC calibration time: maximum delay is 16384/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
/* (refer to device datasheet, parameter "tSTAB") */
@@ -1338,22 +1343,22 @@
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "ts_vrefint"). */
/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_RUN"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
/* Fixed timeout value for ADC linearity word bit set/clear delay. */
/* Values defined to be higher than worst cases: low clock frequency, */
@@ -1452,10 +1457,10 @@
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
- ? ( \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
+ ( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
- ) \
+ ) \
: \
( \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
@@ -1505,12 +1510,12 @@
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9UL) \
- ? ( \
+ (((__DECIMAL_NB__) <= 9UL) ? \
+ ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
+ ) \
: \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
@@ -1902,7 +1907,7 @@
*/
#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
(((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
#if defined(ADC_MULTIMODE_SUPPORT)
/**
@@ -1924,7 +1929,7 @@
: \
(__ADCx__) \
)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -1999,11 +2004,11 @@
*/
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- (((__DATA__) \
- << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
- >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
- )
+ __ADC_RESOLUTION_TARGET__) \
+(((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+)
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -2024,10 +2029,10 @@
*/
#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- )
+ __ADC_RESOLUTION__) \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+)
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -2039,7 +2044,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 16 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -2056,11 +2061,12 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
- / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_16B))
+ __ADC_RESOLUTION__) \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_16B) \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2089,7 +2095,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 16 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -2110,17 +2116,17 @@
*/
#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_16B) \
- * (__VREFANALOG_VOLTAGE__)) \
- / TEMPSENSOR_CAL_VREFANALOG) \
- - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
- ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
- ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
- ) + TEMPSENSOR_CAL1_TEMP \
- )
+ __ADC_RESOLUTION__) \
+(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_16B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2172,18 +2178,17 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((( ( \
- (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- * 1000UL) \
- - \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- * 1000UL) \
- ) \
- ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
- ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
- )
+ __ADC_RESOLUTION__) \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+)
/**
* @}
@@ -2236,7 +2241,7 @@
#if defined(ADC_MULTIMODE_SUPPORT)
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
@@ -2260,7 +2265,7 @@
/* Retrieve address of register DR */
return (uint32_t) &(ADCx->DR);
}
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
@@ -2272,11 +2277,11 @@
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
- * @note On this STM32 serie, if ADC group injected is used, some
+ * @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2356,7 +2361,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2408,7 +2413,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2449,7 +2454,7 @@
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2533,7 +2538,7 @@
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2578,7 +2583,9 @@
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
- return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+ return (uint32_t)(READ_BIT(ADCx->CALFACT,
+ (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+ ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
}
/**
@@ -2586,7 +2593,7 @@
* @note This function is intended to set linear calibration parameters
* without having to perform a new calibration using
* @ref LL_ADC_StartCalibration().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2605,7 +2612,7 @@
*/
__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
{
- register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))
@@ -2632,7 +2639,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
{
- register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
CLEAR_BIT(ADCx->CR, LinearityWord);
while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))
{
@@ -2644,7 +2651,7 @@
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2698,9 +2705,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -2718,7 +2728,7 @@
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2751,9 +2761,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -2797,7 +2810,7 @@
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2857,7 +2870,7 @@
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
@@ -2929,7 +2942,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
@@ -2955,7 +2968,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
@@ -3020,8 +3033,8 @@
*/
__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
- MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
}
/**
@@ -3043,7 +3056,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
}
@@ -3059,7 +3072,7 @@
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -3067,7 +3080,7 @@
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3141,11 +3154,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
@@ -3174,7 +3187,7 @@
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3235,7 +3248,7 @@
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3327,7 +3340,7 @@
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3380,17 +3393,17 @@
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3467,7 +3480,7 @@
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -3477,7 +3490,7 @@
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -3565,7 +3578,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -3581,7 +3594,7 @@
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3617,9 +3630,9 @@
* @brief Set ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
- * - Transfered by DMA in one shot mode
- * - Transfered by DMA in circular mode
- * - Transfered to DFSDM data register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
* @param ADCx ADC instance
* @param DataTransferMode This parameter can be one of the following values:
@@ -3639,9 +3652,9 @@
* @brief Get ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
- * - Transfered by DMA in one shot mode
- * - Transfered by DMA in circular mode
- * - Transfered to DFSDM data register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
@@ -3665,7 +3678,7 @@
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3707,7 +3720,7 @@
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -3715,7 +3728,7 @@
* function @ref LL_ADC_INJ_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3789,11 +3802,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
@@ -3822,7 +3835,7 @@
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3862,7 +3875,7 @@
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3939,13 +3952,13 @@
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32MP1, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4091,7 +4104,7 @@
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4149,7 +4162,7 @@
* on either groups regular or injected.
* @note A modification of the context mode (bit JQDIS) causes the contexts
* queue to be flushed and the register JSQR is cleared.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4199,13 +4212,13 @@
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32MP1, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4391,7 +4404,7 @@
/* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */
- register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
MODIFY_REG(ADCx->JSQR,
ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN |
@@ -4431,7 +4444,7 @@
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4440,7 +4453,7 @@
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4512,7 +4525,7 @@
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
@@ -4525,7 +4538,7 @@
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4593,7 +4606,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
@@ -4623,7 +4636,7 @@
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
@@ -4713,7 +4726,7 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -4734,7 +4747,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4843,8 +4856,8 @@
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
@@ -4866,7 +4879,7 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -4887,7 +4900,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4978,10 +4991,10 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
- register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+ uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
@@ -5038,7 +5051,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5064,7 +5077,7 @@
* on oversampling intermediate computation (after ratio, before shift
* application): intermediate register bitfield [32:7]
* (26 most significant bits).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either ADC groups regular or injected.
@@ -5093,7 +5106,7 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
@@ -5125,7 +5138,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
@@ -5149,7 +5162,7 @@
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5203,11 +5216,11 @@
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
- * @note On this STM32 serie, oversampling discontinuous mode
+ * @note On this STM32 series, oversampling discontinuous mode
* (triggered mode) can be used only when oversampling is
* set on group regular only and in resumed mode.
* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
@@ -5247,7 +5260,7 @@
* @note This function set the 2 items of oversampling configuration:
* - ratio
* - shift
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5320,7 +5333,7 @@
*/
/**
* @brief Set ADC boost mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
@@ -5338,7 +5351,7 @@
/**
* @brief Get ADC boost mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
@@ -5360,7 +5373,7 @@
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5439,7 +5452,7 @@
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
@@ -5507,7 +5520,7 @@
* - ADC resolution 10 bits can have maximum delay of 10 cycles.
* - ADC resolution 8 bits can have maximum delay of 8 cycles.
* - ADC resolution 6 bits can have maximum delay of 6 cycles.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5586,7 +5599,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
@@ -5609,7 +5622,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
@@ -5637,12 +5650,12 @@
/**
* @brief Enable ADC instance internal voltage regulator.
- * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
@@ -5661,7 +5674,7 @@
/**
* @brief Disable ADC internal voltage regulator.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
@@ -5686,14 +5699,14 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
@@ -5712,7 +5725,7 @@
/**
* @brief Disable the selected ADC instance.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
@@ -5732,7 +5745,7 @@
/**
* @brief Get the selected ADC instance enable state.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
@@ -5758,7 +5771,7 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note Calibration duration:
@@ -5773,7 +5786,7 @@
* Calibration of linearity is common to both
* single-ended and differential modes
* (calibration run can be performed only once).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
@@ -5819,14 +5832,14 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
@@ -5847,7 +5860,7 @@
/**
* @brief Stop ADC group regular conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
@@ -6016,14 +6029,14 @@
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
@@ -6044,7 +6057,7 @@
/**
* @brief Stop ADC group injected conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
@@ -6103,7 +6116,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6130,7 +6143,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6157,7 +6170,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6184,7 +6197,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6211,7 +6224,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6238,7 +6251,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6255,7 +6268,7 @@
/**
* @brief Get flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
@@ -6379,7 +6392,7 @@
/**
* @brief Clear flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_bus.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_bus.h
index f93ecb2..b1fb805 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_bus.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_bus.h
@@ -139,7 +139,6 @@
#define LL_AHB5_GRP1_PERIPH_HASH1 RCC_MC_AHB5ENSETR_HASH1EN
#define LL_AHB5_GRP1_PERIPH_RNG1 RCC_MC_AHB5ENSETR_RNG1EN
#define LL_AHB5_GRP1_PERIPH_BKPSRAM RCC_MC_AHB5ENSETR_BKPSRAMEN
-#define LL_AHB5_GRP1_PERIPH_AXIMC RCC_MC_AHB5ENSETR_AXIMC
/**
* @}
*/
@@ -258,7 +257,6 @@
#define LL_APB3_GRP1_PERIPH_SYSCFG RCC_MC_APB3ENSETR_SYSCFGEN
#define LL_APB3_GRP1_PERIPH_VREF RCC_MC_APB3ENSETR_VREFEN
#define LL_APB3_GRP1_PERIPH_TMPSENS RCC_MC_APB3ENSETR_DTSEN
-#define LL_APB3_GRP1_PERIPH_PMBCTRL RCC_MC_APB3ENSETR_PMBCTRLEN
#define LL_APB3_GRP1_PERIPH_HDP RCC_MC_APB3ENSETR_HDPEN
/**
* @}
@@ -1017,7 +1015,6 @@
* @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
* @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
* @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
- * @arg @ref LL_AHB5_GRP1_PERIPH_AXIMC
*
* (*) value not defined in all devices.
* @retval None
@@ -1040,7 +1037,6 @@
* @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
* @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
* @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
- * @arg @ref LL_AHB5_GRP1_PERIPH_AXIMC
*
* (*) value not defined in all devices.
* @retval None
@@ -2295,7 +2291,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @arg @ref LL_APB3_GRP1_PERIPH_HDP
* @retval None
*/
@@ -2329,7 +2324,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @arg @ref LL_APB3_GRP1_PERIPH_HDP
* @retval State of Periphs (1 or 0).
*/
@@ -2359,7 +2353,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @arg @ref LL_APB3_GRP1_PERIPH_HDP
* @retval None
*/
@@ -2389,7 +2382,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
@@ -2418,7 +2410,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
@@ -2447,7 +2438,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -2479,7 +2469,6 @@
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
- * @arg @ref LL_APB3_GRP1_PERIPH_PMBCTRL
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_delayblock.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_delayblock.h
index 338da58..873c379 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_delayblock.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_delayblock.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32MP1xx_LL_DLYB_H
@@ -34,18 +34,18 @@
/** @addtogroup DELAYBLOCK_LL
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
* @{
*/
-
+
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
* @{
@@ -66,8 +66,8 @@
/**
* @}
- */
-
+ */
+
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions
* @{
@@ -78,8 +78,8 @@
/**
* @}
*/
-
-
+
+
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h
index 7979454..734bced 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_rcc.h
@@ -288,10 +288,10 @@
/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
* @{
*/
-#define LL_RCC_HSI_DIV_1 RCC_HSICFGR_HSIDIV_0
-#define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_1
-#define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_2
-#define LL_RCC_HSI_DIV_8 RCC_HSICFGR_HSIDIV_3
+#define LL_RCC_HSI_DIV_1 0U
+#define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_0
+#define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_1
+#define LL_RCC_HSI_DIV_8 (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1)
/**
* @}
*/
@@ -299,18 +299,18 @@
/** @defgroup RCC_LL_EC_MCOxSOURCE MCO SOURCE selection
* @{
*/
-#define LL_RCC_MCO1SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0)
-#define LL_RCC_MCO1SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1)
-#define LL_RCC_MCO1SOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2)
-#define LL_RCC_MCO1SOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_3)
-#define LL_RCC_MCO1SOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_4)
+#define LL_RCC_MCO1SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, 0)
+#define LL_RCC_MCO1SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0)
+#define LL_RCC_MCO1SOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1)
+#define LL_RCC_MCO1SOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1))
+#define LL_RCC_MCO1SOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2)
-#define LL_RCC_MCO2SOURCE_MPU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0)
-#define LL_RCC_MCO2SOURCE_AXI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1)
-#define LL_RCC_MCO2SOURCE_MCU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2)
-#define LL_RCC_MCO2SOURCE_PLL4 LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_3)
-#define LL_RCC_MCO2SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_4)
-#define LL_RCC_MCO2SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_5)
+#define LL_RCC_MCO2SOURCE_MPU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, 0)
+#define LL_RCC_MCO2SOURCE_AXI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0)
+#define LL_RCC_MCO2SOURCE_MCU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1)
+#define LL_RCC_MCO2SOURCE_PLL4 LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0))
+#define LL_RCC_MCO2SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2)
+#define LL_RCC_MCO2SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0))
/**
* @}
*/
@@ -318,22 +318,22 @@
/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
* @{
*/
-#define LL_RCC_MCO1_DIV_1 RCC_MCO1CFGR_MCO1DIV_0 /*!< MCO not divided */
-#define LL_RCC_MCO1_DIV_2 RCC_MCO1CFGR_MCO1DIV_1 /*!< MCO divided by 2 */
-#define LL_RCC_MCO1_DIV_3 RCC_MCO1CFGR_MCO1DIV_2 /*!< MCO divided by 3 */
-#define LL_RCC_MCO1_DIV_4 RCC_MCO1CFGR_MCO1DIV_3 /*!< MCO divided by 4 */
-#define LL_RCC_MCO1_DIV_5 RCC_MCO1CFGR_MCO1DIV_4 /*!< MCO divided by 5 */
-#define LL_RCC_MCO1_DIV_6 RCC_MCO1CFGR_MCO1DIV_5 /*!< MCO divided by 6 */
-#define LL_RCC_MCO1_DIV_7 RCC_MCO1CFGR_MCO1DIV_6 /*!< MCO divided by 7 */
-#define LL_RCC_MCO1_DIV_8 RCC_MCO1CFGR_MCO1DIV_7 /*!< MCO divided by 8 */
-#define LL_RCC_MCO1_DIV_9 RCC_MCO1CFGR_MCO1DIV_8 /*!< MCO divided by 9 */
-#define LL_RCC_MCO1_DIV_10 RCC_MCO1CFGR_MCO1DIV_9 /*!< MCO divided by 10 */
-#define LL_RCC_MCO1_DIV_11 RCC_MCO1CFGR_MCO1DIV_10 /*!< MCO divided by 11 */
-#define LL_RCC_MCO1_DIV_12 RCC_MCO1CFGR_MCO1DIV_11 /*!< MCO divided by 12 */
-#define LL_RCC_MCO1_DIV_13 RCC_MCO1CFGR_MCO1DIV_12 /*!< MCO divided by 13 */
-#define LL_RCC_MCO1_DIV_14 RCC_MCO1CFGR_MCO1DIV_13 /*!< MCO divided by 14 */
-#define LL_RCC_MCO1_DIV_15 RCC_MCO1CFGR_MCO1DIV_14 /*!< MCO divided by 15 */
-#define LL_RCC_MCO1_DIV_16 RCC_MCO1CFGR_MCO1DIV_15 /*!< MCO divided by 16 */
+#define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_MCO1CFGR_MCO1DIV_0 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_3 RCC_MCO1CFGR_MCO1DIV_1 /*!< MCO divided by 3 */
+#define LL_RCC_MCO1_DIV_4 (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_5 RCC_MCO1CFGR_MCO1DIV_2 /*!< MCO divided by 5 */
+#define LL_RCC_MCO1_DIV_6 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 6 */
+#define LL_RCC_MCO1_DIV_7 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 7 */
+#define LL_RCC_MCO1_DIV_8 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1| RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_9 RCC_MCO1CFGR_MCO1DIV_3 /*!< MCO divided by 9 */
+#define LL_RCC_MCO1_DIV_10 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 10 */
+#define LL_RCC_MCO1_DIV_11 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 11 */
+#define LL_RCC_MCO1_DIV_12 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 12 */
+#define LL_RCC_MCO1_DIV_13 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2) /*!< MCO divided by 13 */
+#define LL_RCC_MCO1_DIV_14 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 14 */
+#define LL_RCC_MCO1_DIV_15 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 15 */
+#define LL_RCC_MCO1_DIV_16 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 16 */
/**
* @}
*/
@@ -435,10 +435,10 @@
/** @defgroup RCC_LL_EC_MPU_CLKSOURCE MPU clock switch
* @{
*/
-#define LL_RCC_MPU_CLKSOURCE_HSI RCC_MPCKSELR_MPUSRC_0 /*!< HSI selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_HSE RCC_MPCKSELR_MPUSRC_1 /*!< HSE selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2 /*!< PLL1 selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3 /*!< MPUDIV selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_HSI 0U /*!< HSI selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_HSE RCC_MPCKSELR_MPUSRC_0 /*!< HSE selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_MPUDIV (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV selection as MPU clock */
/**
* @}
*/
@@ -469,10 +469,10 @@
/** @defgroup RCC_LL_EC_AXISS_CLKSOURCE AXISS clock switch
* @{
*/
-#define LL_RCC_AXISS_CLKSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0 /*!< HSI selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1 /*!< HSE selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */
+#define LL_RCC_AXISS_CLKSOURCE_HSI 0U /*!< HSI selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_HSE RCC_ASSCKSELR_AXISSRC_0 /*!< HSE selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
/**
* @}
*/
@@ -480,10 +480,10 @@
/** @defgroup RCC_LL_EC_AXISS_CLKSOURCE_STATUS AXISS clock switch status
* @{
*/
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI RCC_ASSCKSELR_AXISSRC_0 /*!< HSI used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE RCC_ASSCKSELR_AXISSRC_1 /*!< HSE used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2 RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE RCC_ASSCKSELR_AXISSRC_0 /*!< HSE used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2 RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
/**
* @}
*/
@@ -502,10 +502,10 @@
/** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE MCUSS clock switch
* @{
*/
-#define LL_RCC_MCUSS_CLKSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0 /*!< HSI selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1 /*!< HSE selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2 /*!< CSI selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3 /*!< PLL3 selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_HSI 0U /*!< HSI selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 selection as MCUSS clock */
/**
* @}
*/
@@ -541,11 +541,11 @@
/** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
* @{
*/
-#define LL_RCC_APB1_DIV_1 RCC_APB1DIVR_APB1DIV_0 /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB1_DIV_2 RCC_APB1DIVR_APB1DIV_1 /*!< mlhclk divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_APB1DIVR_APB1DIV_2 /*!< mlhclk divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_APB1DIVR_APB1DIV_3 /*!< mlhclk divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_APB1DIVR_APB1DIV_4 /*!< mlhclk divided by 16 */
+#define LL_RCC_APB1_DIV_1 0U /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB1_DIV_2 RCC_APB1DIVR_APB1DIV_0 /*!< mlhclk divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_APB1DIVR_APB1DIV_1 /*!< mlhclk divided by 4 */
+#define LL_RCC_APB1_DIV_8 (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0) /*!< mlhclk divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_APB1DIVR_APB1DIV_2 /*!< mlhclk divided by 16 */
/**
* @}
*/
@@ -553,11 +553,11 @@
/** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
* @{
*/
-#define LL_RCC_APB2_DIV_1 RCC_APB2DIVR_APB2DIV_0 /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB2_DIV_2 RCC_APB2DIVR_APB2DIV_1 /*!< mlhclk divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_APB2DIVR_APB2DIV_2 /*!< mlhclk divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_APB2DIVR_APB2DIV_3 /*!< mlhclk divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_APB2DIVR_APB2DIV_4 /*!< mlhclk divided by 16 */
+#define LL_RCC_APB2_DIV_1 0U /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB2_DIV_2 RCC_APB2DIVR_APB2DIV_0 /*!< mlhclk divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_APB2DIVR_APB2DIV_1 /*!< mlhclk divided by 4 */
+#define LL_RCC_APB2_DIV_8 (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0) /*!< mlhclk divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_APB2DIVR_APB2DIV_2 /*!< mlhclk divided by 16 */
/**
* @}
*/
@@ -565,11 +565,11 @@
/** @defgroup RCC_LL_EC_APB3_DIV APB3 prescaler
* @{
*/
-#define LL_RCC_APB3_DIV_1 RCC_APB3DIVR_APB3DIV_0 /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB3_DIV_2 RCC_APB3DIVR_APB3DIV_1 /*!< mlhclk divided by 2 */
-#define LL_RCC_APB3_DIV_4 RCC_APB3DIVR_APB3DIV_2 /*!< mlhclk divided by 4 */
-#define LL_RCC_APB3_DIV_8 RCC_APB3DIVR_APB3DIV_3 /*!< mlhclk divided by 8 */
-#define LL_RCC_APB3_DIV_16 RCC_APB3DIVR_APB3DIV_4 /*!< mlhclk divided by 16 */
+#define LL_RCC_APB3_DIV_1 0U /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB3_DIV_2 RCC_APB3DIVR_APB3DIV_0 /*!< mlhclk divided by 2 */
+#define LL_RCC_APB3_DIV_4 RCC_APB3DIVR_APB3DIV_1 /*!< mlhclk divided by 4 */
+#define LL_RCC_APB3_DIV_8 (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0) /*!< mlhclk divided by 8 */
+#define LL_RCC_APB3_DIV_16 RCC_APB3DIVR_APB3DIV_2 /*!< mlhclk divided by 16 */
/**
* @}
*/
@@ -577,11 +577,11 @@
/** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler
* @{
*/
-#define LL_RCC_APB4_DIV_1 RCC_APB4DIVR_APB4DIV_0 /*!< aclk not divided (default after reset) */
-#define LL_RCC_APB4_DIV_2 RCC_APB4DIVR_APB4DIV_1 /*!< aclk divided by 2 */
-#define LL_RCC_APB4_DIV_4 RCC_APB4DIVR_APB4DIV_2 /*!< aclk divided by 4 */
-#define LL_RCC_APB4_DIV_8 RCC_APB4DIVR_APB4DIV_3 /*!< aclk divided by 8 */
-#define LL_RCC_APB4_DIV_16 RCC_APB4DIVR_APB4DIV_4 /*!< aclk divided by 16 */
+#define LL_RCC_APB4_DIV_1 0U /*!< aclk not divided (default after reset) */
+#define LL_RCC_APB4_DIV_2 RCC_APB4DIVR_APB4DIV_0 /*!< aclk divided by 2 */
+#define LL_RCC_APB4_DIV_4 RCC_APB4DIVR_APB4DIV_1 /*!< aclk divided by 4 */
+#define LL_RCC_APB4_DIV_8 (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0) /*!< aclk divided by 8 */
+#define LL_RCC_APB4_DIV_16 RCC_APB4DIVR_APB4DIV_2 /*!< aclk divided by 16 */
/**
* @}
*/
@@ -589,11 +589,11 @@
/** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler
* @{
*/
-#define LL_RCC_APB5_DIV_1 RCC_APB5DIVR_APB5DIV_0 /*!< aclk not divided (default after reset) */
-#define LL_RCC_APB5_DIV_2 RCC_APB5DIVR_APB5DIV_1 /*!< aclk divided by 2 */
-#define LL_RCC_APB5_DIV_4 RCC_APB5DIVR_APB5DIV_2 /*!< aclk divided by 4 */
-#define LL_RCC_APB5_DIV_8 RCC_APB5DIVR_APB5DIV_3 /*!< aclk divided by 8 */
-#define LL_RCC_APB5_DIV_16 RCC_APB5DIVR_APB5DIV_4 /*!< aclk divided by 16 */
+#define LL_RCC_APB5_DIV_1 0U /*!< aclk not divided (default after reset) */
+#define LL_RCC_APB5_DIV_2 RCC_APB5DIVR_APB5DIV_0 /*!< aclk divided by 2 */
+#define LL_RCC_APB5_DIV_4 RCC_APB5DIVR_APB5DIV_1 /*!< aclk divided by 4 */
+#define LL_RCC_APB5_DIV_8 (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0) /*!< aclk divided by 8 */
+#define LL_RCC_APB5_DIV_16 RCC_APB5DIVR_APB5DIV_2 /*!< aclk divided by 16 */
/**
* @}
*/
@@ -624,20 +624,20 @@
/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
* @{
*/
-#define LL_RCC_I2C12_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0)
-#define LL_RCC_I2C12_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1)
-#define LL_RCC_I2C12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_2)
-#define LL_RCC_I2C12_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_3)
+#define LL_RCC_I2C12_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, 0)
+#define LL_RCC_I2C12_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0)
+#define LL_RCC_I2C12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1)
+#define LL_RCC_I2C12_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0))
-#define LL_RCC_I2C35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0)
-#define LL_RCC_I2C35_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1)
-#define LL_RCC_I2C35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_2)
-#define LL_RCC_I2C35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_3)
+#define LL_RCC_I2C35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, 0)
+#define LL_RCC_I2C35_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0)
+#define LL_RCC_I2C35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1)
+#define LL_RCC_I2C35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0))
-#define LL_RCC_I2C46_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0)
-#define LL_RCC_I2C46_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1)
-#define LL_RCC_I2C46_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_2)
-#define LL_RCC_I2C46_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_3)
+#define LL_RCC_I2C46_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, 0)
+#define LL_RCC_I2C46_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0)
+#define LL_RCC_I2C46_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1)
+#define LL_RCC_I2C46_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0))
/**
* @}
*/
@@ -645,30 +645,30 @@
/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
* @{
*/
-#define LL_RCC_SAI1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1)
-#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2)
-#define LL_RCC_SAI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_3)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_4)
+#define LL_RCC_SAI1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0)
+#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1)
+#define LL_RCC_SAI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0))
+#define LL_RCC_SAI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2)
-#define LL_RCC_SAI2_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0)
-#define LL_RCC_SAI2_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1)
-#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2)
-#define LL_RCC_SAI2_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_3)
-#define LL_RCC_SAI2_CLKSOURCE_SPDIF LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_4)
-#define LL_RCC_SAI2_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_5)
+#define LL_RCC_SAI2_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, 0)
+#define LL_RCC_SAI2_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0)
+#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1)
+#define LL_RCC_SAI2_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0))
+#define LL_RCC_SAI2_CLKSOURCE_SPDIF LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2)
+#define LL_RCC_SAI2_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0))
-#define LL_RCC_SAI3_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0)
-#define LL_RCC_SAI3_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1)
-#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2)
-#define LL_RCC_SAI3_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_3)
-#define LL_RCC_SAI3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_4)
+#define LL_RCC_SAI3_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, 0)
+#define LL_RCC_SAI3_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0)
+#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1)
+#define LL_RCC_SAI3_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0))
+#define LL_RCC_SAI3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2)
-#define LL_RCC_SAI4_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0)
-#define LL_RCC_SAI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1)
-#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2)
-#define LL_RCC_SAI4_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_3)
-#define LL_RCC_SAI4_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_4)
+#define LL_RCC_SAI4_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, 0)
+#define LL_RCC_SAI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0)
+#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1)
+#define LL_RCC_SAI4_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0))
+#define LL_RCC_SAI4_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2)
/**
* @}
*/
@@ -676,30 +676,30 @@
/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI/I2S clock source selection
* @{
*/
-#define LL_RCC_SPI1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0)
-#define LL_RCC_SPI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1)
-#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2)
-#define LL_RCC_SPI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_3)
-#define LL_RCC_SPI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_4)
+#define LL_RCC_SPI1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, 0)
+#define LL_RCC_SPI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0)
+#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1)
+#define LL_RCC_SPI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0))
+#define LL_RCC_SPI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2)
-#define LL_RCC_SPI23_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0)
-#define LL_RCC_SPI23_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1)
-#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2)
-#define LL_RCC_SPI23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_3)
-#define LL_RCC_SPI23_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_4)
+#define LL_RCC_SPI23_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, 0)
+#define LL_RCC_SPI23_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0)
+#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1)
+#define LL_RCC_SPI23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0))
+#define LL_RCC_SPI23_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2)
-#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0)
-#define LL_RCC_SPI45_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1)
-#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2)
-#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_3)
-#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_4)
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, 0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0)
+#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0))
+#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2)
-#define LL_RCC_SPI6_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0)
-#define LL_RCC_SPI6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1)
-#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2)
-#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_3)
-#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_4)
-#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_5)
+#define LL_RCC_SPI6_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, 0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0)
+#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0))
+#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0))
/**
* @}
*/
@@ -707,36 +707,36 @@
/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
* @{
*/
-#define LL_RCC_USART1_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0)
-#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1)
-#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2)
-#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_3)
-#define LL_RCC_USART1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_4)
-#define LL_RCC_USART1_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_5)
+#define LL_RCC_USART1_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, 0)
+#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0)
+#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1)
+#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0))
+#define LL_RCC_USART1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2)
+#define LL_RCC_USART1_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0))
-#define LL_RCC_UART24_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0)
-#define LL_RCC_UART24_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1)
-#define LL_RCC_UART24_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2)
-#define LL_RCC_UART24_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_3)
-#define LL_RCC_UART24_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_4)
+#define LL_RCC_UART24_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, 0)
+#define LL_RCC_UART24_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0)
+#define LL_RCC_UART24_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1)
+#define LL_RCC_UART24_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0))
+#define LL_RCC_UART24_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2)
-#define LL_RCC_UART35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0)
-#define LL_RCC_UART35_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1)
-#define LL_RCC_UART35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2)
-#define LL_RCC_UART35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_3)
-#define LL_RCC_UART35_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_4)
+#define LL_RCC_UART35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, 0)
+#define LL_RCC_UART35_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0)
+#define LL_RCC_UART35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1)
+#define LL_RCC_UART35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0))
+#define LL_RCC_UART35_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2)
-#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0)
-#define LL_RCC_USART6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1)
-#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2)
-#define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_3)
-#define LL_RCC_USART6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_4)
+#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, 0)
+#define LL_RCC_USART6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0)
+#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1)
+#define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0))
+#define LL_RCC_USART6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2)
-#define LL_RCC_UART78_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0)
-#define LL_RCC_UART78_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1)
-#define LL_RCC_UART78_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2)
-#define LL_RCC_UART78_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_3)
-#define LL_RCC_UART78_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_4)
+#define LL_RCC_UART78_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, 0)
+#define LL_RCC_UART78_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0)
+#define LL_RCC_UART78_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1)
+#define LL_RCC_UART78_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0))
+#define LL_RCC_UART78_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2)
/**
* @}
*/
@@ -744,15 +744,15 @@
/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
* @{
*/
-#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6 LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0)
-#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1)
-#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_2)
-#define LL_RCC_SDMMC12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_3)
+#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6 LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, 0)
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0)
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1)
+#define LL_RCC_SDMMC12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0))
-#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2 LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0)
-#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1)
-#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_2)
-#define LL_RCC_SDMMC3_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_3)
+#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2 LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, 0)
+#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0)
+#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1)
+#define LL_RCC_SDMMC3_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0))
/**
* @}
*/
@@ -760,9 +760,9 @@
/** @defgroup RCC_LL_EC_ETH_CLKSOURCE Peripheral ETH clock source selection
* @{
*/
-#define LL_RCC_ETH_CLKSOURCE_PLL4P RCC_ETHCKSELR_ETHSRC_0
-#define LL_RCC_ETH_CLKSOURCE_PLL3Q RCC_ETHCKSELR_ETHSRC_1
-#define LL_RCC_ETH_CLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_2
+#define LL_RCC_ETH_CLKSOURCE_PLL4P 0U
+#define LL_RCC_ETH_CLKSOURCE_PLL3Q RCC_ETHCKSELR_ETHSRC_0
+#define LL_RCC_ETH_CLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1
/**
* @}
*/
@@ -770,10 +770,10 @@
/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection
* @{
*/
-#define LL_RCC_QSPI_CLKSOURCE_ACLK RCC_QSPICKSELR_QSPISRC_0
-#define LL_RCC_QSPI_CLKSOURCE_PLL3R RCC_QSPICKSELR_QSPISRC_1
-#define LL_RCC_QSPI_CLKSOURCE_PLL4P RCC_QSPICKSELR_QSPISRC_2
-#define LL_RCC_QSPI_CLKSOURCE_PER RCC_QSPICKSELR_QSPISRC_3
+#define LL_RCC_QSPI_CLKSOURCE_ACLK 0U
+#define LL_RCC_QSPI_CLKSOURCE_PLL3R RCC_QSPICKSELR_QSPISRC_0
+#define LL_RCC_QSPI_CLKSOURCE_PLL4P RCC_QSPICKSELR_QSPISRC_1
+#define LL_RCC_QSPI_CLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0)
/**
* @}
*/
@@ -781,10 +781,10 @@
/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
* @{
*/
-#define LL_RCC_FMC_CLKSOURCE_ACLK RCC_FMCCKSELR_FMCSRC_0
-#define LL_RCC_FMC_CLKSOURCE_PLL3R RCC_FMCCKSELR_FMCSRC_1
-#define LL_RCC_FMC_CLKSOURCE_PLL4P RCC_FMCCKSELR_FMCSRC_2
-#define LL_RCC_FMC_CLKSOURCE_PER RCC_FMCCKSELR_FMCSRC_3
+#define LL_RCC_FMC_CLKSOURCE_ACLK 0U
+#define LL_RCC_FMC_CLKSOURCE_PLL3R RCC_FMCCKSELR_FMCSRC_0
+#define LL_RCC_FMC_CLKSOURCE_PLL4P RCC_FMCCKSELR_FMCSRC_1
+#define LL_RCC_FMC_CLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0)
/**
* @}
*/
@@ -793,10 +793,10 @@
/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
* @{
*/
-#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_FDCANCKSELR_FDCANSRC_0
-#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q RCC_FDCANCKSELR_FDCANSRC_1
-#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q RCC_FDCANCKSELR_FDCANSRC_2
-#define LL_RCC_FDCAN_CLKSOURCE_PLL4R RCC_FDCANCKSELR_FDCANSRC_3
+#define LL_RCC_FDCAN_CLKSOURCE_HSE 0U
+#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q RCC_FDCANCKSELR_FDCANSRC_0
+#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q RCC_FDCANCKSELR_FDCANSRC_1
+#define LL_RCC_FDCAN_CLKSOURCE_PLL4R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0)
/**
* @}
*/
@@ -805,9 +805,9 @@
/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
* @{
*/
-#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P RCC_SPDIFCKSELR_SPDIFSRC_0
-#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q RCC_SPDIFCKSELR_SPDIFSRC_1
-#define LL_RCC_SPDIFRX_CLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_2
+#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P 0U
+#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q RCC_SPDIFCKSELR_SPDIFSRC_0
+#define LL_RCC_SPDIFRX_CLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1
/**
* @}
*/
@@ -815,9 +815,9 @@
/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
* @{
*/
-#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CECCKSELR_CECSRC_0
-#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CECCKSELR_CECSRC_1
-#define LL_RCC_CEC_CLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_2
+#define LL_RCC_CEC_CLKSOURCE_LSE 0U
+#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0
+#define LL_RCC_CEC_CLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1
/**
* @}
*/
@@ -825,9 +825,9 @@
/** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection
* @{
*/
-#define LL_RCC_USBPHY_CLKSOURCE_HSE RCC_USBCKSELR_USBPHYSRC_0
-#define LL_RCC_USBPHY_CLKSOURCE_PLL4R RCC_USBCKSELR_USBPHYSRC_1
-#define LL_RCC_USBPHY_CLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_2
+#define LL_RCC_USBPHY_CLKSOURCE_HSE 0U
+#define LL_RCC_USBPHY_CLKSOURCE_PLL4R RCC_USBCKSELR_USBPHYSRC_0
+#define LL_RCC_USBPHY_CLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1
/**
* @}
*/
@@ -835,8 +835,8 @@
/** @defgroup RCC_LL_EC_USBO_CLKSOURCE Peripheral USBO clock source selection
* @{
*/
-#define LL_RCC_USBO_CLKSOURCE_PLL4R RCC_USBCKSELR_USBOSRC_0
-#define LL_RCC_USBO_CLKSOURCE_PHY RCC_USBCKSELR_USBOSRC_1
+#define LL_RCC_USBO_CLKSOURCE_PLL4R 0U
+#define LL_RCC_USBO_CLKSOURCE_PHY RCC_USBCKSELR_USBOSRC
/**
* @}
*/
@@ -844,15 +844,15 @@
/** @defgroup RCC_LL_EC_RNGx_CLKSOURCE Peripheral RNG clock source selection
* @{
*/
-#define LL_RCC_RNG1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0)
-#define LL_RCC_RNG1_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1)
-#define LL_RCC_RNG1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_2)
-#define LL_RCC_RNG1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_3)
+#define LL_RCC_RNG1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, 0)
+#define LL_RCC_RNG1_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0)
+#define LL_RCC_RNG1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1)
+#define LL_RCC_RNG1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0))
-#define LL_RCC_RNG2_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0)
-#define LL_RCC_RNG2_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1)
-#define LL_RCC_RNG2_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_2)
-#define LL_RCC_RNG2_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_3)
+#define LL_RCC_RNG2_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, 0)
+#define LL_RCC_RNG2_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0)
+#define LL_RCC_RNG2_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1)
+#define LL_RCC_RNG2_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0))
/**
* @}
*/
@@ -860,10 +860,10 @@
/** @defgroup RCC_LL_EC_CKPER_CLKSOURCE Peripheral CKPER clock source selection
* @{
*/
-#define LL_RCC_CKPER_CLKSOURCE_HSI RCC_CPERCKSELR_CKPERSRC_0
-#define LL_RCC_CKPER_CLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_1
-#define LL_RCC_CKPER_CLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_2
-#define LL_RCC_CKPER_CLKSOURCE_OFF RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/
+#define LL_RCC_CKPER_CLKSOURCE_HSI 0U
+#define LL_RCC_CKPER_CLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0
+#define LL_RCC_CKPER_CLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1
+#define LL_RCC_CKPER_CLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/
/**
* @}
*/
@@ -871,9 +871,9 @@
/** @defgroup RCC_LL_EC_STGEN_CLKSOURCE Peripheral STGEN clock source selection
* @{
*/
-#define LL_RCC_STGEN_CLKSOURCE_HSI RCC_STGENCKSELR_STGENSRC_0
-#define LL_RCC_STGEN_CLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_1
-#define LL_RCC_STGEN_CLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_2
+#define LL_RCC_STGEN_CLKSOURCE_HSI 0U
+#define LL_RCC_STGEN_CLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0
+#define LL_RCC_STGEN_CLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1
/**
* @}
*/
@@ -882,8 +882,8 @@
/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
* @{
*/
-#define LL_RCC_DSI_CLKSOURCE_PHY RCC_DSICKSELR_DSISRC_0
-#define LL_RCC_DSI_CLKSOURCE_PLL4P RCC_DSICKSELR_DSISRC_1
+#define LL_RCC_DSI_CLKSOURCE_PHY 0U
+#define LL_RCC_DSI_CLKSOURCE_PLL4P RCC_DSICKSELR_DSISRC
/**
* @}
*/
@@ -892,9 +892,9 @@
/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
* @{
*/
-#define LL_RCC_ADC_CLKSOURCE_PLL4R RCC_ADCCKSELR_ADCSRC_0
-#define LL_RCC_ADC_CLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_1
-#define LL_RCC_ADC_CLKSOURCE_PLL3Q RCC_ADCCKSELR_ADCSRC_2
+#define LL_RCC_ADC_CLKSOURCE_PLL4R 0U
+#define LL_RCC_ADC_CLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0
+#define LL_RCC_ADC_CLKSOURCE_PLL3Q RCC_ADCCKSELR_ADCSRC_1
/**
* @}
*/
@@ -902,28 +902,28 @@
/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
* @{
*/
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_3)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_4)
-#define LL_RCC_LPTIM1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_5)
-#define LL_RCC_LPTIM1_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_6)
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, 0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
+#define LL_RCC_LPTIM1_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1))
-#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0)
-#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1)
-#define LL_RCC_LPTIM23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2)
-#define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_3)
-#define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_4)
-#define LL_RCC_LPTIM23_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_5)
+#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, 0)
+#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0)
+#define LL_RCC_LPTIM23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1)
+#define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
+#define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2)
+#define LL_RCC_LPTIM23_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
-#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0)
-#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1)
-#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2)
-#define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_3)
-#define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_4)
-#define LL_RCC_LPTIM45_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_5)
-#define LL_RCC_LPTIM45_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_6)
+#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, 0)
+#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1)
+#define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
+#define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2)
+#define LL_RCC_LPTIM45_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
+#define LL_RCC_LPTIM45_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1))
/**
* @}
*/
@@ -931,11 +931,11 @@
/** @defgroup RCC_LL_EC_TIMGx_Prescaler_Selection TIMG Prescaler selection
* @{
*/
-#define LL_RCC_TIMG1PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_0)
-#define LL_RCC_TIMG1PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_1)
+#define LL_RCC_TIMG1PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, 0)
+#define LL_RCC_TIMG1PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE)
-#define LL_RCC_TIMG2PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_0)
-#define LL_RCC_TIMG2PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_1)
+#define LL_RCC_TIMG2PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, 0)
+#define LL_RCC_TIMG2PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE)
/**
* @}
*/
@@ -943,10 +943,10 @@
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
-#define LL_RCC_RTC_CLKSOURCE_NONE RCC_BDCR_RTCSRC_0 /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSRC_1 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSRC_2 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSRC_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSRC_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0) /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */
/**
* @}
*/
@@ -1144,9 +1144,9 @@
/** @defgroup RCC_LL_EC_PLL12SOURCE PLL1 and PLL2 entry clock source
* @{
*/
-#define LL_RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0 /*!< HSI clock selected as PLL12 entry clock source */
-#define LL_RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1 /*!< HSE clock selected as PLL12 entry clock source */
-#define LL_RCC_PLL12SOURCE_NONE RCC_RCK12SELR_PLL12SRC_2 /*!< No clock */
+#define LL_RCC_PLL12SOURCE_HSI 0U /*!< HSI clock selected as PLL12 entry clock source */
+#define LL_RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_0 /*!< HSE clock selected as PLL12 entry clock source */
+#define LL_RCC_PLL12SOURCE_NONE RCC_RCK12SELR_PLL12SRC_1 /*!< No clock */
/**
* @}
*/
@@ -1154,10 +1154,10 @@
/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source
* @{
*/
-#define LL_RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0 /*!< HSI clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1 /*!< HSE clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2 /*!< CSI clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_NONE RCC_RCK3SELR_PLL3SRC_3 /*!< No clock */
+#define LL_RCC_PLL3SOURCE_HSI 0U /*!< HSI clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_0 /*!< HSE clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_1 /*!< CSI clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_NONE (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0) /*!< No clock */
/**
* @}
*/
@@ -1165,10 +1165,10 @@
/** @defgroup RCC_LL_EC_PLL4SOURCE PLL4 entry clock source
* @{
*/
-#define LL_RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0 /*!< HSI clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1 /*!< HSE clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2 /*!< CSI clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_I2SCKIN RCC_RCK4SELR_PLL4SRC_3 /*!< Signal I2S_CKIN selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_HSI 0U /*!< HSI clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_0 /*!< HSE clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_1 /*!< CSI clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_I2SCKIN (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0) /*!< Signal I2S_CKIN selected as PLL4 entry clock source */
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_sdmmc.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_sdmmc.h
index 2c0cddf..ae45424 100755
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_sdmmc.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_sdmmc.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_LL_SDMMC_H
@@ -34,15 +34,15 @@
/** @addtogroup SDMMC_LL
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
* @{
*/
-
-/**
- * @brief SDMMC Configuration Structure definition
+
+/**
+ * @brief SDMMC Configuration Structure definition
*/
typedef struct
{
@@ -61,27 +61,27 @@
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
-
-}SDMMC_InitTypeDef;
-
-/**
- * @brief SDMMC Command Control structure
+}SDMMC_InitTypeDef;
+
+
+/**
+ * @brief SDMMC Command Control structure
*/
-typedef struct
+typedef struct
{
uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register. */
- uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
+ uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
Max_Data = 64 */
uint32_t Response; /*!< Specifies the SDMMC response type.
This parameter can be a value of @ref SDMMC_LL_Response_Type */
- uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
@@ -91,25 +91,25 @@
}SDMMC_CmdInitTypeDef;
-/**
- * @brief SDMMC Data Control structure
+/**
+ * @brief SDMMC Data Control structure
*/
typedef struct
{
uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
+
uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
-
+
uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
-
+
uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
-
+
uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_DPSM_State */
@@ -118,7 +118,7 @@
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
@@ -131,12 +131,12 @@
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
@@ -148,7 +148,7 @@
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
@@ -160,19 +160,19 @@
#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
-/**
- * @brief SDMMC Commands Index
+/**
+ * @brief SDMMC Commands Index
*/
#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
@@ -181,17 +181,17 @@
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
@@ -201,40 +201,40 @@
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
+#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
-/**
+/**
* @brief Following commands are SD Card Specific commands.
- * SDMMC_APP_CMD should be sent before sending these commands.
+ * SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
-/**
+/**
* @brief Following commands are SD Card Specific security commands.
- * SDMMC_CMD_APP_CMD should be sent before sending these commands.
+ * SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
@@ -248,8 +248,8 @@
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
-/**
- * @brief Masks for errors Card Status R1 (OCR Register)
+/**
+ * @brief Masks for errors Card Status R1 (OCR Register)
*/
#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
@@ -272,8 +272,8 @@
#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
-/**
- * @brief Masks for R6 Response
+/**
+ * @brief Masks for R6 Response
*/
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
@@ -289,7 +289,7 @@
#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
-
+
#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
@@ -309,7 +309,7 @@
#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
-/**
+/**
* @brief Command Class supported
*/
#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
@@ -367,7 +367,7 @@
/**
* @}
*/
-
+
/** @defgroup SDMMC_LL_Clock_Division Clock Division
* @{
*/
@@ -375,8 +375,8 @@
#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
/**
* @}
- */
-
+ */
+
/** @defgroup SDMMC_LL_Command_Index Command Index
* @{
@@ -404,7 +404,7 @@
* @{
*/
#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
-#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
+#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
@@ -424,7 +424,7 @@
((CPSM) == SDMMC_CPSM_ENABLE))
/**
* @}
- */
+ */
/** @defgroup SDMMC_LL_Response_Registers Response Register
* @{
@@ -442,7 +442,7 @@
/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
* @{
*/
-#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
+#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
@@ -473,7 +473,7 @@
#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
@@ -492,7 +492,7 @@
((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@@ -532,7 +532,7 @@
/**
* @}
*/
-
+
/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
@@ -543,7 +543,7 @@
((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
/**
* @}
- */
+ */
/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
* @{
@@ -573,7 +573,7 @@
#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
/**
* @}
- */
+ */
/** @defgroup SDMMC_LL_Flags Flags
* @{
@@ -630,19 +630,19 @@
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
* @{
*/
-
+
/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
* @brief SDMMC_LL registers bit address in the alias region
* @{
*/
/* ---------------------- SDMMC registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
+/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
SDMMC_CLKCR_WIDBUS |\
SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
@@ -677,7 +677,7 @@
/**
* @brief Enable the SDMMC device interrupt.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -709,7 +709,7 @@
/**
* @brief Disable the SDMMC device interrupt.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -740,9 +740,9 @@
#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
- * @brief Checks whether the specified SDMMC flag is set or not.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __FLAG__: specifies the flag to check.
+ * @brief Checks whether the specified SDMMC flag is set or not.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -780,8 +780,8 @@
/**
* @brief Clears the SDMMC pending flags.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __FLAG__: specifies the flag to clear.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -809,8 +809,8 @@
/**
* @brief Checks whether the specified SDMMC interrupt has occurred or not.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -847,8 +847,8 @@
/**
* @brief Clears the SDMMC's interrupt pending bits.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -876,73 +876,73 @@
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
+ */
#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+ */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
+ */
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
+ */
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
-
+ */
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
+
/**
* @brief Enable the CMDTRANS mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
+ */
+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
/**
* @brief Disable the CMDTRANS mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
+ * @param __INSTANCE__ : Pointer to SDMMC register base
* @retval None
- */
-#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
+ */
+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
/**
* @brief Enable the CMDSTOP mode.
@@ -964,13 +964,13 @@
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDMMC_LL_Exported_Functions
* @{
*/
-
+
/* Initialization/de-initialization functions **********************************/
/** @addtogroup HAL_SDMMC_LL_Group1
* @{
@@ -979,7 +979,7 @@
/**
* @}
*/
-
+
/* I/O operation functions *****************************************************/
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
@@ -989,7 +989,7 @@
/**
* @}
*/
-
+
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_SDMMC_LL_Group3
* @{
@@ -1044,14 +1044,14 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/**
* @}
@@ -1060,10 +1060,10 @@
/**
* @}
*/
-
+
/**
* @}
- */
+ */
#ifdef __cplusplus
}
#endif
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_system.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_system.h
index 5ccae04..7fcbf45 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_system.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_system.h
@@ -407,7 +407,7 @@
}
/**
- * @brief Enable the Analog GPIO switch to control voltage selection
+ * @brief Enable the Analog GPIO switch to control voltage selection
* when the supply voltage is supplied by VDDA
* @rmtoll SYSCFG_PMCSETR ANASWVDD LL_SYSCFG_EnableAnalogGpioSwitch
* @note Activating the gpio switch enable IOs analog switches supplied by VDDA
@@ -419,7 +419,7 @@
}
/**
- * @brief Disable the Analog GPIO switch to control voltage selection
+ * @brief Disable the Analog GPIO switch to control voltage selection
* when the supply voltage is supplied by VDDA
* @rmtoll SYSCFG_PMCCLRR ANASWVDD LL_SYSCFG_DisableAnalogGpioSwitch
* @note Activating the gpio switch enable IOs analog switches supplied by VDDA
@@ -869,7 +869,7 @@
/**
* @brief Get connections to TIM1/8/15/16/17 Break inputs
* @note this feature is available on STM32MP1 rev.B and above
- * @rmtoll
+ * @rmtoll
* SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
diff --git a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_usart.h b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_usart.h
index e2a4a63..f66107f 100644
--- a/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_usart.h
+++ b/stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_usart.h
@@ -44,33 +44,26 @@
* @{
*/
/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
-static const uint16_t USART_PRESCALER_TAB[] =
+static const uint32_t USART_PRESCALER_TAB[] =
{
- (uint16_t)1,
- (uint16_t)2,
- (uint16_t)4,
- (uint16_t)6,
- (uint16_t)8,
- (uint16_t)10,
- (uint16_t)12,
- (uint16_t)16,
- (uint16_t)32,
- (uint16_t)64,
- (uint16_t)128,
- (uint16_t)256
+ 1UL,
+ 2UL,
+ 4UL,
+ 6UL,
+ 8UL,
+ 10UL,
+ 12UL,
+ 16UL,
+ 32UL,
+ 64UL,
+ 128UL,
+ 256UL
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -95,41 +88,49 @@
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
@@ -148,20 +149,23 @@
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
@@ -364,18 +368,18 @@
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -570,7 +574,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -592,7 +598,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -790,7 +798,8 @@
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@@ -1864,22 +1873,31 @@
* @param BaudRate Baud Rate
* @retval None
*/
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling,
uint32_t BaudRate)
{
- register uint32_t usartdiv;
- register uint32_t brrtemp;
+ uint32_t usartdiv;
+ uint32_t brrtemp;
- if (OverSampling == LL_USART_OVERSAMPLING_8)
+ if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
- usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
+ /* Do not overstep the size of USART_PRESCALER_TAB */
+ }
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
USARTx->BRR = brrtemp;
}
else
{
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
}
}
@@ -1909,11 +1927,12 @@
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling)
{
- register uint32_t usartdiv;
- register uint32_t brrresult = 0x0U;
- register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
@@ -2650,7 +2669,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@@ -2686,7 +2706,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@@ -2726,7 +2747,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@@ -2764,7 +2786,8 @@
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@@ -2804,7 +2827,8 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@@ -2847,7 +2871,8 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@@ -2885,7 +2910,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
@@ -3264,7 +3290,7 @@
/**
* @brief Clear Noise Error detected Flag
- * @rmtoll ICR NECF LL_USART_ClearFlag_NE
+ * @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
*/
@@ -4195,17 +4221,17 @@
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
- data_reg_addr = (uint32_t) & (USARTx->TDR);
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
- data_reg_addr = (uint32_t) & (USARTx->RDR);
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
@@ -4227,7 +4253,7 @@
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
- return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal.c
index ca4d580..4ba8e61 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal.c
@@ -49,12 +49,12 @@
/** @defgroup HAL_Private_Defines HAL Private Defines
* @{
*/
-
+
/**
* @brief STM32MP1xx HAL Driver version number
*/
#define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32MP1xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
#define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\
@@ -703,8 +703,8 @@
{
/* Check the parameter */
assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
- SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCSETR_ETH_SEL|SYSCFG_PMCSETR_ETH_SELMII_SEL);
- SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_ETHInterface));
+ SYSCFG->PMCCLRR = SYSCFG_PMCSETR_ETH_SEL|SYSCFG_PMCSETR_ETH_SELMII_SEL;
+ SYSCFG->PMCSETR = (uint32_t)(SYSCFG_ETHInterface);
}
/**
@@ -727,8 +727,8 @@
/* Check the parameter */
assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
- SET_BIT(SYSCFG->PMCCLRR, SYSCFG_AnalogSwitch);
- SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_SwitchState));
+ SYSCFG->PMCCLRR = SYSCFG_AnalogSwitch;
+ SYSCFG->PMCSETR = (uint32_t)(SYSCFG_SwitchState);
}
@@ -743,7 +743,8 @@
*/
void HAL_SYSCFG_EnableBOOST(void)
{
- SET_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_EN_BOOSTER) ;
+ SYSCFG->PMCSETR = SYSCFG_PMCSETR_EN_BOOSTER;
+
}
/**
@@ -755,7 +756,7 @@
*/
void HAL_SYSCFG_DisableBOOST(void)
{
- SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_EN_BOOSTER) ;
+ SYSCFG->PMCCLRR = SYSCFG_PMCCLRR_EN_BOOSTER;
}
@@ -768,9 +769,9 @@
void HAL_EnableCompensationCell(void)
{
#if defined(CORE_CM4)
- SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MCU_EN) ;
+ SYSCFG->CMPENSETR = SYSCFG_CMPENSETR_MCU_EN;
#elif defined(CORE_CA7)
- SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MPU_EN) ;
+ SYSCFG->CMPENSETR = SYSCFG_CMPENSETR_MPU_EN;
#endif
}
@@ -783,9 +784,9 @@
void HAL_DisableCompensationCell(void)
{
#if defined(CORE_CM4)
- SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MCU_EN) ;
+ SYSCFG->CMPENCLRR = SYSCFG_CMPENCLRR_MCU_EN;
#elif defined(CORE_CA7)
- SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MPU_EN) ;
+ SYSCFG->CMPENCLRR = SYSCFG_CMPENCLRR_MPU_EN;
#endif
}
@@ -806,7 +807,7 @@
*/
void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
{
- SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_HighSpeedSignal) ;
+ SYSCFG->IOCTRLSETR = SYSCFG_HighSpeedSignal;
}
/**
@@ -825,7 +826,7 @@
*/
void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
{
- SET_BIT(SYSCFG->IOCTRLCLRR, SYSCFG_HighSpeedSignal) ;
+ SYSCFG->IOCTRLCLRR = SYSCFG_HighSpeedSignal;
}
/**
@@ -872,8 +873,8 @@
uint32_t nmos_val = 0;
/* Get I/O compensation cell values for PMOS and NMOS transistors */
- pmos_val = __HAL_SYSCFG_GET_PMOS_CMP();
- nmos_val = __HAL_SYSCFG_GET_NMOS_CMP();
+ pmos_val = (__HAL_SYSCFG_GET_PMOS_CMP() >> 28);
+ nmos_val = (__HAL_SYSCFG_GET_NMOS_CMP() >> 24);
/* Copy actual value of SYSCFG_CMPCR.APSRC[3:0]/ANSRC[3:0] in
* SYSCFG_CMPCR.RAPSRC[3:0]/RANSRC[3:0]
@@ -921,7 +922,7 @@
return status;
}
-
+
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc.c
index e3630ff..e432009 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc.c
@@ -3,7 +3,7 @@
* @file stm32mp1xx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
@@ -321,13 +321,11 @@
#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
- when no regular conversion is on-going */
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
- ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
- (neither regular nor injected) is on-going */
+ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
@@ -889,10 +887,10 @@
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
- /* DeInit the low level hardware: RCC clock, NVIC */
+ /* DeInit the low level hardware */
hadc->MspDeInitCallback(hadc);
#else
- /* DeInit the low level hardware: RCC clock, NVIC */
+ /* DeInit the low level hardware */
HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
@@ -969,7 +967,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2154,7 +2153,7 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
- /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@@ -2357,7 +2356,7 @@
/* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
/* to determine if conversion has been triggered from EOC or EOS, */
/* possibility to use: */
- /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
@@ -2412,44 +2411,46 @@
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -2457,8 +2458,8 @@
/* Injected Conversion complete callback */
/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
interruption has been triggered by end of conversion or end of
sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
@@ -2713,7 +2714,7 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0UL;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
@@ -2853,7 +2854,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
{
/* Configuration of common ADC parameters */
@@ -2865,7 +2866,8 @@
{
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
@@ -2951,7 +2953,7 @@
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
- * @note On this STM32 serie, analog watchdog thresholds cannot be modified
+ * @note On this STM32 series, analog watchdog thresholds cannot be modified
* while ADC conversion is on going.
* @param hadc ADC handle
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
@@ -3393,8 +3395,6 @@
return HAL_OK;
}
-
-
/**
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
@@ -3413,7 +3413,8 @@
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
- if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3448,12 +3449,12 @@
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
- if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
LL_ADC_Enable(hadc->Instance);
}
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3662,7 +3663,7 @@
void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
{
uint32_t freq;
- if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
+ if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
{
freq = HAL_RCC_GetHCLK2Freq();
switch(hadc->Init.ClockPrescaler)
@@ -3711,7 +3712,7 @@
}
}
- if(freq > 20000000UL)
+ if (freq > 20000000UL)
{
SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
}
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc_ex.c
index a1886cb..cd8962b 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc_ex.c
@@ -3,7 +3,7 @@
* @file stm32mp1xx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
@@ -62,8 +62,7 @@
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
- ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
- once the ADC is enabled */
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: maximum ratio between ADC */
@@ -230,14 +229,14 @@
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
- if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
tmp_hal_status = ADC_Enable(hadc);
}
if (tmp_hal_status == HAL_OK)
{
- if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
LL_ADC_REG_StopConversion(hadc->Instance);
temp_REG_IsConversionOngoing = 1UL;
@@ -246,7 +245,7 @@
{
LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
}
- if(temp_REG_IsConversionOngoing != 0UL)
+ if (temp_REG_IsConversionOngoing != 0UL)
{
LL_ADC_REG_StartConversion(hadc->Instance);
}
@@ -265,7 +264,8 @@
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
@@ -2057,19 +2057,23 @@
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
@@ -2091,7 +2095,9 @@
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+ + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
@@ -2100,7 +2106,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cortex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cortex.c
index f6bb2df..d12d313 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cortex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cortex.c
@@ -24,9 +24,9 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
- (#) please refer to programming manual for details in how to configure priority.
+ (#) please refer to programming manual for details in how to configure priority.
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
@@ -131,7 +131,7 @@
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
@@ -183,7 +183,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
@@ -199,7 +199,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
@@ -238,7 +238,7 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
+ (NVIC, SYSTICK, MPU) functionalities.
@endverbatim
@@ -341,7 +341,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
@@ -359,7 +359,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
@@ -375,7 +375,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
@@ -392,7 +392,7 @@
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
+
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp.c
index 294560d..9d4f16f 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp.c
@@ -66,6 +66,12 @@
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+ without having to configure again the Key or the Initialization Vector between each API call,
+ the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+ Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
+ or HAL_CRYP_Decrypt_DMA().
+
[..]
The cryptographic processor supports following standards:
(#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@@ -139,13 +145,15 @@
(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
- =============================================
+ =============================
+ [..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
+ [..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
@@ -155,6 +163,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -166,6 +175,7 @@
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
+ [..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@@ -175,6 +185,7 @@
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@@ -183,6 +194,7 @@
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function.
+ [..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -412,6 +424,7 @@
assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+ assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
if (hcryp->State == HAL_CRYP_STATE_RESET)
@@ -448,6 +461,9 @@
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+ /* Reset peripheral Key and IV configuration flag */
+ hcryp->KeyIVConfig = 0U;
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -1219,6 +1235,7 @@
/* Enable CRYP to start DES/TDES process*/
__HAL_CRYP_ENABLE(hcryp);
+ status = HAL_OK;
break;
case CRYP_AES_ECB:
@@ -1387,6 +1404,7 @@
{
uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1467,18 +1485,38 @@
case CRYP_AES_CBC:
case CRYP_AES_CTR:
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
- hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
- hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -1893,12 +1931,12 @@
hcryp->CrypInCount++;
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
-
+
if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Disable interruption */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
@@ -1926,16 +1964,16 @@
{
/* Disable interruption */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
@@ -1944,7 +1982,7 @@
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
}
}
}
@@ -1974,19 +2012,40 @@
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
- hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
- hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2021,18 +2080,40 @@
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
{
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
- hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
- hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2066,7 +2147,27 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
{
@@ -2111,6 +2212,8 @@
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
+} /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2146,7 +2249,27 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
@@ -2194,6 +2317,8 @@
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
+} /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
@@ -2224,7 +2349,27 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
@@ -2274,6 +2419,8 @@
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
+} /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2339,20 +2486,20 @@
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp; /* Temporary CrypOutBuff */
- uint32_t temp_cr_algodir;
+ uint32_t temp_cr_algodir;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-
+
+
/* Disable the DMA transfer for output FIFO */
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-
+
/* Last block transfer in case of GCM or CCM with Size not %16*/
if (((hcryp->Size) % 16U) != 0U)
{
/* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
hcryp->CrypOutCount = hcryp->CrypInCount;
-
+
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
/* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
@@ -2362,14 +2509,14 @@
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
-
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
-
+
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
@@ -2779,9 +2926,10 @@
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t i;
/*Temporary CrypOutCount Value*/
incount = hcryp->CrypInCount;
@@ -2825,18 +2973,17 @@
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
}
}
@@ -2850,9 +2997,10 @@
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t i;
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
@@ -2892,18 +3040,17 @@
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable interrupts */
@@ -2998,11 +3145,37 @@
uint32_t tickstart;
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
- uint32_t temp ; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t index ;
uint32_t lastwordsize ;
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@@ -3069,6 +3242,7 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
+} /* if (DoKeyIVConfig == 1U) */
if ((hcryp->Size % 16U) != 0U)
{
@@ -3177,15 +3351,16 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUT;
+ }
+ for (index=0; index<lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
hcryp->CrypOutCount++;
}
}
}
-
/* Return function status */
return HAL_OK;
}
@@ -3199,7 +3374,34 @@
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
+ {
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@@ -3243,7 +3445,7 @@
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ } /* end of if (DoKeyIVConfig == 1U) */
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
@@ -3268,8 +3470,35 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
- /* Reset CrypHeaderCount */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/*************************** Init phase ************************************/
@@ -3329,6 +3558,8 @@
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+} /* if (DoKeyIVConfig == 1U) */
+
if (hcryp->Size == 0U)
{
/* Process unLocked */
@@ -3421,11 +3652,14 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUT;
+ }
+ for (index=0; index<lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -3451,10 +3685,36 @@
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
uint32_t lastwordsize ;
- uint32_t temp ; /* Temporary CrypOutBuff */
+ uint32_t temp[4] ; /* Temporary CrypOutBuff */
uint32_t index ;
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@@ -3528,6 +3788,8 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
+} /* if (DoKeyIVConfig == 1U) */
+
if ((hcryp->Size % 16U) != 0U)
{
/* recalculate wordsize */
@@ -3635,9 +3897,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUT;
+ }
+ for (index=0; index<lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
}
@@ -3656,7 +3920,34 @@
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
+ {
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@@ -3704,7 +3995,7 @@
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+} /* end of if (DoKeyIVConfig == 1U) */
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
@@ -3727,8 +4018,34 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@@ -3794,6 +4111,7 @@
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+ } /* if (DoKeyIVConfig == 1U) */
if (hcryp->Size == 0U)
{
@@ -3885,11 +4203,14 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUT;
+ }
+ for (index=0; index<lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -3902,7 +4223,7 @@
}
/**
- * @brief Sets the payload phase in iterrupt mode
+ * @brief Sets the payload phase in interrupt mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval state
@@ -3910,11 +4231,12 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t temp_cr_algodir;
uint8_t negative = 0U;
+ uint32_t i;
/***************************** Payload phase *******************************/
@@ -3934,7 +4256,7 @@
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
}
-
+
else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
(negative == 0U))
{
@@ -3953,7 +4275,6 @@
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@@ -3963,38 +4284,37 @@
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
- if (hcryp->CrypOutCount < (hcryp->Size / 4U))
+
+ if (hcryp->CrypOutCount < (hcryp->Size / 4U))
{
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Output complete callback*/
@@ -4015,19 +4335,19 @@
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
-
+
/* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
-
+
if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
-
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
@@ -4062,18 +4382,29 @@
/*Read the output block from the output FIFO */
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
+ for (i = 0U; i < 4U; i++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ if (( (hcryp->Size)/4U)==0U)
+ {
+ for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ }
+ }
+ i = 0U;
+ while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
+ i++;
}
}
/* Disable the output FIFO Interrupt */
- if (hcryp->CrypOutCount > ((hcryp->Size) / 4U))
+ if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp_ex.c
index da38848..24b201a 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_cryp_ex.c
@@ -110,7 +110,7 @@
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if (hcryp->State == HAL_CRYP_STATE_READY)
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac.c
index ea3c868..2e5824d 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac.c
@@ -1474,7 +1474,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac_ex.c
index 61d37f7..e03c3c0 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dac_ex.c
@@ -541,7 +541,7 @@
/**
* @}
*/
-
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm.c
index b3cf476..539ed37 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32mp1xx_hal_dfsdm.c
* @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
+ * @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
* + Initialization and configuration of channels and filters
@@ -15,7 +15,7 @@
* + Extremes detector feature
* + Clock absence detector feature
* + Break generation on analog watchdog or short-circuit event
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -32,7 +32,7 @@
(++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the output clock, input, serial interface, analog watchdog,
- offset and data right bit shift parameters for this channel using the
+ offset and data right bit shift parameters for this channel using the
HAL_DFSDM_ChannelInit() function.
*** Channel clock absence detector ***
@@ -46,36 +46,36 @@
clock absence is detected.
(#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
HAL_DFSDM_ChannelCkabStop_IT().
- (#) Please note that the same mode (polling or interrupt) has to be used
+ (#) Please note that the same mode (polling or interrupt) has to be used
for all channels because the channels are sharing the same interrupt.
(#) Please note also that in interrupt mode, if clock absence detector is
stopped for one channel, interrupt will be disabled for all channels.
*** Channel short circuit detector ***
======================================
- [..]
+ [..]
(#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
or HAL_DFSDM_ChannelScdStart_IT().
(#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
circuit.
- (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
+ (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
short circuit is detected.
(#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
or HAL_DFSDM_ChannelScdStop_IT().
- (#) Please note that the same mode (polling or interrupt) has to be used
+ (#) Please note that the same mode (polling or interrupt) has to be used
for all channels because the channels are sharing the same interrupt.
(#) Please note also that in interrupt mode, if short circuit detector is
stopped for one channel, interrupt will be disabled for all channels.
*** Channel analog watchdog value ***
=====================================
- [..]
+ [..]
(#) Get analog watchdog filter value of a channel using
HAL_DFSDM_ChannelGetAwdValue().
*** Channel offset value ***
=====================================
- [..]
+ [..]
(#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
*** Filter initialization ***
@@ -94,21 +94,21 @@
*** Filter regular channel conversion ***
=========================================
- [..]
+ [..]
(#) Select regular channel and enable/disable continuous mode using
HAL_DFSDM_FilterConfigRegChannel().
(#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
HAL_DFSDM_FilterRegularMsbStart_DMA().
- (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
+ (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
the end of regular conversion.
(#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
at the end of regular conversion.
- (#) Get value of regular conversion and corresponding channel using
+ (#) Get value of regular conversion and corresponding channel using
HAL_DFSDM_FilterGetRegularValue().
- (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
+ (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
- half transfer and at the transfer complete. Please note that
+ half transfer and at the transfer complete. Please note that
HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
circular mode.
(#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
@@ -121,15 +121,15 @@
(#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
HAL_DFSDM_FilterInjectedMsbStart_DMA().
- (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
+ (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
the end of injected conversion.
(#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
at the end of injected conversion.
- (#) Get value of injected conversion and corresponding channel using
+ (#) Get value of injected conversion and corresponding channel using
HAL_DFSDM_FilterGetInjectedValue().
- (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
+ (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
- half transfer and at the transfer complete. Please note that
+ half transfer and at the transfer complete. Please note that
HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
circular mode.
(#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
@@ -157,23 +157,26 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
- @ref HAL_DFSDM_Filter_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+ Use functions HAL_DFSDM_Channel_RegisterCallback(),
+ HAL_DFSDM_Filter_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
- Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Channel_RegisterCallback() allows to register
following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Filter_RegisterCallback() allows to register
following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -182,26 +185,33 @@
(+) ErrorCallback : DFSDM filter error callback.
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- For specific DFSDM filter analog watchdog callback use dedicated register callback:
- @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+ [..]
+ For specific DFSDM filter analog watchdog callback use dedicated register callback:
+ HAL_DFSDM_Filter_RegisterAwdCallback().
- Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
- @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
+ HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
- @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -211,28 +221,32 @@
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
- @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+ HAL_DFSDM_Filter_UnRegisterAwdCallback().
- By default, after the call of init function and if the state is RESET
- all callbacks are reset to the corresponding legacy weak functions:
- examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+ [..]
+ By default, after the call of init function and if the state is RESET
+ all callbacks are reset to the corresponding legacy weak functions:
+ examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak functions in the init and de-init only when these
+ reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
- In that case first register the MspInit/MspDeInit user callbacks using
- @ref HAL_DFSDM_Channel_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ In that case first register the MspInit/MspDeInit user callbacks using
+ HAL_DFSDM_Channel_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ [..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak callbacks are used.
@endverbatim
@@ -261,7 +275,7 @@
/** @defgroup DFSDM DFSDM
* @brief DFSDM HAL driver module
* @{
- */
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -313,7 +327,7 @@
*/
/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
- * @brief Channel initialization and de-initialization functions
+ * @brief Channel initialization and de-initialization functions
*
@verbatim
==============================================================================
@@ -352,14 +366,14 @@
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
-
+
/* Check that channel has not been already initialized */
if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
{
return HAL_ERROR;
}
-
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
@@ -374,10 +388,10 @@
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
#endif
-
+
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
-
+
/* Configure output serial clock and enable global DFSDM interface only for first channel */
if(v_dfsdm1ChannelCounter == 1U)
{
@@ -385,52 +399,52 @@
/* Set the output serial clock source */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
-
+
/* Reset clock divider */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
- DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
+ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
-
+
/* enable the DFSDM global interface */
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
}
-
+
/* Set channel input parameters */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
DFSDM_CHCFGR1_CHINSEL);
- hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
- hdfsdm_channel->Init.Input.DataPacking |
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
+ hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Init.Input.Pins);
-
+
/* Set serial interface parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
- hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Init.SerialInterface.SpiClock);
-
+
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
- hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
+ hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
- hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
-
+
/* Set DFSDM Channel to ready state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
/* Store channel handle in DFSDM channel handle table */
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
-
+
return HAL_OK;
}
@@ -449,7 +463,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check that channel has not been already deinitialized */
if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
{
@@ -458,10 +472,10 @@
/* Disable the DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
-
+
/* Update the channel counter */
v_dfsdm1ChannelCounter--;
-
+
/* Disable global DFSDM at deinit of last channel */
if(v_dfsdm1ChannelCounter == 0U)
{
@@ -469,7 +483,7 @@
}
/* Call MSP deinit function */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_channel->MspDeInitCallback == NULL)
{
hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
@@ -497,7 +511,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_channel);
-
+
/* NOTE : This function should not be modified, when the function is needed,
the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
*/
@@ -512,13 +526,13 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_channel);
-
+
/* NOTE : This function should not be modified, when the function is needed,
the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
*/
}
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user DFSDM channel callback
* to be used instead of the weak predefined callback.
@@ -693,7 +707,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -738,12 +752,12 @@
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
uint32_t channel;
-
+
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
@@ -757,7 +771,7 @@
{
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
+
/* Get timeout */
tickstart = HAL_GetTick();
@@ -774,10 +788,10 @@
}
}
}
-
+
/* Clear clock absence detection flag */
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
-
+
/* Return function status */
return HAL_OK;
}
@@ -795,7 +809,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -806,7 +820,7 @@
{
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
-
+
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
@@ -832,7 +846,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -875,7 +889,7 @@
}
/**
- * @brief Clock absence detection callback.
+ * @brief Clock absence detection callback.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
@@ -883,7 +897,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_channel);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
*/
@@ -902,7 +916,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -913,7 +927,7 @@
{
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
-
+
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
@@ -945,7 +959,7 @@
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -958,7 +972,7 @@
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
-
+
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}
@@ -972,12 +986,12 @@
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
uint32_t channel;
-
+
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
@@ -991,7 +1005,7 @@
{
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
+
/* Get timeout */
tickstart = HAL_GetTick();
@@ -1008,10 +1022,10 @@
}
}
}
-
+
/* Clear short circuit detection flag */
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
-
+
/* Return function status */
return HAL_OK;
}
@@ -1029,7 +1043,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1040,7 +1054,7 @@
{
/* Stop short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
-
+
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
@@ -1069,7 +1083,7 @@
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1085,7 +1099,7 @@
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
-
+
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}
@@ -1094,7 +1108,7 @@
}
/**
- * @brief Short circuit detection callback.
+ * @brief Short circuit detection callback.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
@@ -1102,7 +1116,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_channel);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
*/
@@ -1121,7 +1135,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1132,7 +1146,7 @@
{
/* Stop short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
-
+
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
@@ -1169,7 +1183,7 @@
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1219,7 +1233,7 @@
*/
/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
- * @brief Filter initialization and de-initialization functions
+ * @brief Filter initialization and de-initialization functions
*
@verbatim
==============================================================================
@@ -1259,8 +1273,8 @@
assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
/* Check parameters compatibility */
- if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
- ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
+ if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
+ ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
{
return HAL_ERROR;
@@ -1271,8 +1285,8 @@
hdfsdm_filter->InjectedChannelsNbr = 1;
hdfsdm_filter->InjConvRemaining = 1;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
-
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
@@ -1338,7 +1352,7 @@
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
}
-
+
/* Set filter parameters */
hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
@@ -1350,13 +1364,13 @@
hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
-
+
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
/* Set DFSDM filter to ready state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
-
+
return HAL_OK;
}
@@ -1375,12 +1389,12 @@
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
+
/* Disable the DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
+
/* Call MSP deinit function */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_filter->MspDeInitCallback == NULL)
{
hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
@@ -1405,7 +1419,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the function is needed,
the HAL_DFSDM_FilterMspInit could be implemented in the user file.
*/
@@ -1420,13 +1434,13 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the function is needed,
the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
*/
}
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user DFSDM filter callback
* to be used instead of the weak predefined callback.
@@ -1695,14 +1709,14 @@
uint32_t ContinuousMode)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
-
+
/* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel and continuous mode for regular conversion */
@@ -1718,7 +1732,7 @@
}
/* Store continuous mode information */
hdfsdm_filter->RegularContMode = ContinuousMode;
- }
+ }
else
{
status = HAL_ERROR;
@@ -1743,9 +1757,9 @@
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
-
+
/* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel for injected conversion */
@@ -1800,7 +1814,7 @@
/**
* @brief This function allows to start regular conversion in polling mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -1852,7 +1866,7 @@
else
{
/* Get timeout */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
/* Wait end of regular conversion */
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
@@ -1872,7 +1886,7 @@
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -1924,7 +1938,7 @@
/**
* @brief This function allows to start regular conversion in interrupt mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -1942,7 +1956,7 @@
{
/* Enable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
-
+
/* Start regular conversion */
DFSDM_RegConvStart(hdfsdm_filter);
}
@@ -1978,7 +1992,7 @@
{
/* Disable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
-
+
/* Stop regular conversion */
DFSDM_RegConvStop(hdfsdm_filter);
}
@@ -1988,7 +2002,7 @@
/**
* @brief This function allows to start regular conversion in DMA mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed regular conversion
* value on 24 most significant bits and corresponding channel on 3 least
@@ -2040,7 +2054,7 @@
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
-
+
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2066,7 +2080,7 @@
/**
* @brief This function allows to start regular conversion in DMA mode and to get
* only the 16 most significant bits of conversion.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of regular conversion.
@@ -2117,7 +2131,7 @@
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
-
+
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2190,14 +2204,14 @@
{
uint32_t reg;
int32_t value;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != (void *)0);
/* Get value of data register for regular channel */
reg = hdfsdm_filter->Instance->FLTRDATAR;
-
+
/* Extract channel and regular conversion value */
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
/* Regular conversion value is a signed value located on 24 MSB of register */
@@ -2211,7 +2225,7 @@
/**
* @brief This function allows to start injected conversion in polling mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2263,7 +2277,7 @@
else
{
/* Get timeout */
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
/* Wait end of injected conversions */
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
@@ -2283,7 +2297,7 @@
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2303,7 +2317,7 @@
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}
-
+
/* end of injected sequence, reset the value */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
@@ -2345,7 +2359,7 @@
/**
* @brief This function allows to start injected conversion in interrupt mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2363,7 +2377,7 @@
{
/* Enable interrupts for injected conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
-
+
/* Start injected conversion */
DFSDM_InjConvStart(hdfsdm_filter);
}
@@ -2399,7 +2413,7 @@
{
/* Disable interrupts for injected conversions */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
-
+
/* Stop injected conversion */
DFSDM_InjConvStop(hdfsdm_filter);
}
@@ -2409,7 +2423,7 @@
/**
* @brief This function allows to start injected conversion in DMA mode.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed injected conversion
* value on 24 most significant bits and corresponding channel on 3 least
@@ -2459,7 +2473,7 @@
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
-
+
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2485,7 +2499,7 @@
/**
* @brief This function allows to start injected conversion in DMA mode and to get
* only the 16 most significant bits of conversion.
- * @note This function should be called only when DFSDM filter instance is
+ * @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of injected conversion.
@@ -2534,7 +2548,7 @@
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
-
+
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2602,19 +2616,19 @@
* @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
-int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg;
int32_t value;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != (void *)0);
/* Get value of data register for injected channel */
reg = hdfsdm_filter->Instance->FLTJDATAR;
-
+
/* Extract channel and injected conversion value */
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
/* Injected conversion value is a signed value located on 24 MSB of register */
@@ -2645,7 +2659,7 @@
assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
-
+
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -2687,7 +2701,7 @@
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
+
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -2702,7 +2716,7 @@
/* Clear all analog watchdog flags */
hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
-
+
/* Reset thresholds and break signals */
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
@@ -2729,7 +2743,7 @@
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
-
+
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -2741,7 +2755,7 @@
{
/* Set channels for extreme detector */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
- hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
+ hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
}
/* Return function status */
return status;
@@ -2760,7 +2774,7 @@
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
+
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -2775,7 +2789,7 @@
/* Clear extreme detector values */
reg1 = hdfsdm_filter->Instance->FLTEXMAX;
- reg2 = hdfsdm_filter->Instance->FLTEXMIN;
+ reg2 = hdfsdm_filter->Instance->FLTEXMIN;
UNUSED(reg1); /* To avoid GCC warning */
UNUSED(reg2); /* To avoid GCC warning */
}
@@ -2795,14 +2809,14 @@
{
uint32_t reg;
int32_t value;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != (void *)0);
/* Get value of extreme detector maximum register */
reg = hdfsdm_filter->Instance->FLTEXMAX;
-
+
/* Extract channel and extreme detector maximum value */
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
/* Extreme detector maximum value is a signed value located on 24 MSB of register */
@@ -2826,14 +2840,14 @@
{
uint32_t reg;
int32_t value;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != (void *)0);
/* Get value of extreme detector minimum register */
reg = hdfsdm_filter->Instance->FLTEXMIN;
-
+
/* Extract channel and extreme detector minimum value */
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
/* Extreme detector minimum value is a signed value located on 24 MSB of register */
@@ -2855,13 +2869,13 @@
{
uint32_t reg;
uint32_t value;
-
+
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
/* Get value of conversion timer register */
reg = hdfsdm_filter->Instance->FLTCNVTIMR;
-
+
/* Extract conversion time value */
value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
@@ -2891,7 +2905,7 @@
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
/* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2908,7 +2922,7 @@
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
/* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2919,7 +2933,7 @@
((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
{
/* Call regular conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
@@ -2942,7 +2956,7 @@
((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
{
/* Call injected conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
@@ -2974,7 +2988,7 @@
uint32_t reg;
uint32_t threshold;
uint32_t channel = 0;
-
+
/* Get channel and threshold */
reg = hdfsdm_filter->Instance->FLTAWSR;
threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
@@ -2993,7 +3007,7 @@
(1UL << channel);
/* Call analog watchdog callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
#else
HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
@@ -3006,7 +3020,7 @@
{
uint32_t reg;
uint32_t channel = 0;
-
+
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM1_CHANNEL_NUMBER)
@@ -3021,7 +3035,7 @@
hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
@@ -3039,7 +3053,7 @@
{
uint32_t reg;
uint32_t channel = 0;
-
+
/* Get channel */
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while(((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U)))
@@ -3047,12 +3061,12 @@
channel++;
reg = reg >> 1;
}
-
+
/* Clear short circuit detection flag */
hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Call short circuit detection callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
@@ -3061,7 +3075,7 @@
}
/**
- * @brief Regular conversion complete callback.
+ * @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetRegularValue.
* @param hdfsdm_filter DFSDM filter handle.
@@ -3071,14 +3085,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
*/
}
/**
- * @brief Half regular conversion complete callback.
+ * @brief Half regular conversion complete callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3086,14 +3100,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
*/
}
/**
- * @brief Injected conversion complete callback.
+ * @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetInjectedValue.
* @param hdfsdm_filter DFSDM filter handle.
@@ -3103,14 +3117,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
*/
}
/**
- * @brief Half injected conversion complete callback.
+ * @brief Half injected conversion complete callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3118,14 +3132,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
*/
}
/**
- * @brief Filter analog watchdog callback.
+ * @brief Filter analog watchdog callback.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel.
* @param Threshold Low or high threshold has been reached.
@@ -3138,14 +3152,14 @@
UNUSED(hdfsdm_filter);
UNUSED(Channel);
UNUSED(Threshold);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
*/
}
/**
- * @brief Error callback.
+ * @brief Error callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3153,7 +3167,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdfsdm_filter);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
*/
@@ -3213,17 +3227,17 @@
*/
/**
- * @brief DMA half transfer complete callback for regular conversion.
+ * @brief DMA half transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular half conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
@@ -3231,17 +3245,17 @@
}
/**
- * @brief DMA transfer complete callback for regular conversion.
+ * @brief DMA transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
@@ -3249,17 +3263,17 @@
}
/**
- * @brief DMA half transfer complete callback for injected conversion.
+ * @brief DMA half transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected half conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
@@ -3267,17 +3281,17 @@
}
/**
- * @brief DMA transfer complete callback for injected conversion.
+ * @brief DMA transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
-static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
@@ -3285,11 +3299,11 @@
}
/**
- * @brief DMA error callback.
+ * @brief DMA error callback.
* @param hdma DMA handle.
* @retval None
*/
-static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -3298,7 +3312,7 @@
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
/* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -3314,7 +3328,7 @@
{
uint32_t nbChannels = 0;
uint32_t tmp;
-
+
/* Get the number of channels from bitfield */
tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
while(tmp != 0U)
@@ -3336,7 +3350,7 @@
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef* Instance)
{
uint32_t channel;
-
+
/* Get channel from instance */
if(Instance == DFSDM1_Channel0)
{
@@ -3366,14 +3380,10 @@
{
channel = 6;
}
- else if(Instance == DFSDM1_Channel7)
+ else /* DFSDM1_Channel7 */
{
channel = 7;
}
- else
- {
- channel = 0;
- }
return channel;
}
@@ -3395,13 +3405,13 @@
{
/* Disable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
+
/* Set RSYNC bit in DFSDM_FLTCR1 register */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
+
/* If injected conversion was in progress, restart it */
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
{
@@ -3437,7 +3447,7 @@
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
+
/* If injected conversion was in progress, restart it */
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
{
@@ -3449,7 +3459,7 @@
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}
-
+
/* Update DFSDM filter state */
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
@@ -3472,7 +3482,7 @@
{
/* Disable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
+
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
{
/* Set JSYNC bit in DFSDM_FLTCR1 register */
@@ -3483,7 +3493,7 @@
/* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
}
-
+
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
@@ -3526,7 +3536,7 @@
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
+
/* If regular conversion was in progress, restart it */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm_ex.c
index 0818071..63865d1 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_dfsdm_ex.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32mp1xx_hal_dfsdm_ex.c
* @author MCD Application Team
- * @brief DFSDM Extended HAL module driver.
+ * @brief DFSDM Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionality of the DFSDM Peripheral Controller:
* + Set and get pulses skipping on channel.
@@ -19,7 +19,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -70,10 +70,10 @@
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check pulses value */
assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue));
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -96,7 +96,7 @@
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check DFSDM channel state */
if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_exti.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_exti.c
index 9f81b64..efbace7 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_exti.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_exti.c
@@ -245,25 +245,6 @@
/* Store interrupt mode */
*regaddr = regval;
- /* The event mode cannot be configured if the line does not support it */
- assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
-
- regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
-
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
- {
- regval |= maskline;
- }
- else
- {
- regval &= ~maskline;
- }
-
- /* Store event mode */
- *regaddr = regval;
}
/*Set Interrupt And Event Mask for Core 2 if configuration for Core 2 given into parameter mode */
@@ -356,16 +337,6 @@
pExtiConfig->Mode = EXTI_MODE_C1_NONE;
}
- /* Get Core 1 mode : event */
- regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if selected line is enable */
- if ((regval & maskline) != 0x00u)
- {
- pExtiConfig->Mode |= EXTI_MODE_C1_EVENT;
- }
-
/* Get core 2 mode : interrupt */
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
@@ -476,9 +447,6 @@
*regaddr = regval;
/* 2] Clear event mode */
- regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_gpio.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_gpio.c
index f726c9d..7099c5d 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_gpio.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_gpio.c
@@ -25,8 +25,8 @@
[..]
During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
[..]
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_hash.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_hash.c
index 6e1def2..672caf1 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_hash.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_hash.c
@@ -1475,42 +1475,42 @@
uint32_t inputaddr;
uint32_t buffersize;
HAL_StatusTypeDef status ;
-
+
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
-
+
/* Disable the DMA transfer */
CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
-
+
if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
{
/* If no HMAC processing, input data transfer is now over */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
}
else
{
/* HMAC processing: depending on the current HMAC step and whether or
not multi-buffer processing is on-going, the next step is initiated
and MDMAT bit is set. */
-
-
+
+
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/* This is the end of HMAC processing */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back
(note that the last DMA transfer was that of the key
for the outer HASH operation). */
@@ -1519,7 +1519,7 @@
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
return;
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
@@ -1527,11 +1527,11 @@
inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
-
+
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
/* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
if (hhash->DigestCalculationDisable != RESET)
@@ -1568,34 +1568,34 @@
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
}
}
-
+
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
/* Set the HASH DMA transfert completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
+
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4-(buffersize %4U)))/4U):(buffersize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update DAC state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ hhash->State = HAL_HASH_STATE_ERROR;
}
else
{
/* Change DAC state */
hhash->State = HAL_HASH_STATE_READY;
- }
+ }
}
}
@@ -2240,46 +2240,46 @@
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hhash);
-
+
/* Check if initialization phase has not been already performed */
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
-
+
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
+
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
-
+
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
-
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
/* if the IP has already been initialized, two cases are possible */
-
+
/* Process resumption time ... */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
@@ -2306,48 +2306,48 @@
{
/* Phase error */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_ERROR;
}
-
-
+
+
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
-
+
/* If the process has not been suspended, carry on to digest calculation */
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
-
+
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* Read the message digest */
HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
+
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
-
+
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_OK;
-
+
}
else
{
@@ -2373,14 +2373,14 @@
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* Make sure the input buffer size (in bytes) is a multiple of 4 */
assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
{
@@ -2473,7 +2473,7 @@
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
{
@@ -2561,7 +2561,7 @@
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ( (pInBuffer == NULL ) || (Size == 0U) ||
/* Check phase coherency. Phase must be
@@ -2631,31 +2631,31 @@
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4-(inputSize %4U)))/4U):(inputSize/4U)));
-
+
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Process Unlock */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ hhash->State = HAL_HASH_STATE_ERROR;
}
else
{
/* Change HASH state */
hhash->State = HAL_HASH_STATE_READY;
}
-
+
return status;
}
else
{
return HAL_BUSY;
- }
+ }
}
/**
@@ -2726,11 +2726,11 @@
*/
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2796,11 +2796,11 @@
*/
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2906,13 +2906,13 @@
uint32_t inputaddr;
uint32_t inputSize;
HAL_StatusTypeDef status ;
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
/* Check phase coherency. Phase must be
@@ -3027,7 +3027,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
@@ -3040,7 +3040,7 @@
hhash->State = HAL_HASH_STATE_READY;
}
/* Return function status */
- return status;
+ return status;
}
else
{
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdios.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdios.c
index 4dda4a9..3ecd71a 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdios.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdios.c
@@ -5,15 +5,15 @@
* @version V0.0.1
* @date 01-July-2016
* @brief MDIOS HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
*
- *
- @verbatim
+ *
+ @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
@@ -48,18 +48,18 @@
(##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
(#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
- the MDIOS will generate an interrupt in the following cases:
+ the MDIOS will generate an interrupt in the following cases:
(##) a DINn register written by the Master
(##) a DOUTn register read by the Master
(##) an error occur
- (@) A callback is executed for each genereted interrupt, so the driver provide the following
+ (@) A callback is executed for each genereted interrupt, so the driver provide the following
HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
(@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
-
+
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
- (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
+ (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
(GPIO, Clocks, NVIC configuration ...)
@@ -75,7 +75,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -90,9 +90,9 @@
* @{
*/
#ifdef HAL_MDIOS_MODULE_ENABLED
-
+
#if defined (MDIOS)
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
@@ -102,7 +102,7 @@
#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)
-/* Private macro -------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -111,16 +111,16 @@
* @{
*/
-/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the MDIOS
- (+) The following parameters can be configured:
+ (+) The following parameters can be configured:
(++) Port Address
(++) Preamble Check
@@ -129,7 +129,7 @@
*/
/**
- * @brief Initializes the MDIOS according to the specified parameters in
+ * @brief Initializes the MDIOS according to the specified parameters in
* the MDIOS_InitTypeDef and creates the associated handle .
* @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
* the configuration information for MDIOS module
@@ -144,44 +144,44 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
-
+
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
/* Init the low level hardware */
HAL_MDIOS_MspInit(hmdios);
}
-
+
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
-
+
/* Get the MDIOS CR value */
tmpcr = hmdios->Instance->CR;
-
+
/* Clear PORT_ADDRESS, DPC and EN bits */
tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
-
+
/* Set MDIOS control parametrs and enable the peripheral */
tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\
(hmdios->Init.PreambleCheck) | \
(MDIOS_CR_EN));
-
+
/* Write the MDIOS CR */
hmdios->Instance->CR = tmpcr;
-
+
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_READY;
-
+
/* Release Lock */
__HAL_UNLOCK(hmdios);
-
+
/* Return function status */
return HAL_OK;
@@ -199,25 +199,25 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
-
+
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_MDIOS_DISABLE(hmdios);
-
+
/* DeInit the low level hardware */
HAL_MDIOS_MspDeInit(hmdios);
-
+
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hmdios);
-
+
/* Return function status */
return HAL_OK;
}
@@ -234,7 +234,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspInit can be implemented in the user file
- */
+ */
}
/**
@@ -249,25 +249,25 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspDeInit can be implemented in the user file
- */
+ */
}
-/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
- * @brief MDIOS Read/Write functions
+/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
+ * @brief MDIOS Read/Write functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- This subsection provides a set of functions allowing to manage the MDIOS
+ This subsection provides a set of functions allowing to manage the MDIOS
read and write operations.
- (#) APIs that allow to the MDIOS to read/write from/to the
+ (#) APIs that allow to the MDIOS to read/write from/to the
values of one of the DINn/DOUTn registers:
(+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
- (#) APIs that provide if there are some Slave registres have been
+ (#) APIs that provide if there are some Slave registres have been
read or written by the Master:
(+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
@@ -279,7 +279,7 @@
(#) A set of Callbacks are provided:
(+) HAL_MDIOS_WriteCpltCallback()
(+) HAL_MDIOS_ReadCpltCallback()
- (+) HAL_MDIOS_ErrorCallback()
+ (+) HAL_MDIOS_ErrorCallback()
@endverbatim
* @{
@@ -295,25 +295,25 @@
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
{
uint32_t tmpreg;
-
+
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
-
+
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
/* Get the addr of output register to be written by the MDIOS */
tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);
-
+
/* Write to DOUTn register */
- *((uint32_t *)tmpreg) = Data;
-
+ *((uint32_t *)tmpreg) = Data;
+
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
-
- return HAL_OK;
+
+ return HAL_OK;
}
-
+
/**
* @brief Reads an MDIOS input register
* @param hmdios: mdios handle
@@ -324,13 +324,13 @@
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
{
uint32_t tmpreg;
-
+
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
/* Get the addr of input register to be read by the MDIOS */
tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);
@@ -349,8 +349,8 @@
* @retval bit map of written registers addresses
*/
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
-{
- return hmdios->Instance->WRFR;
+{
+ return hmdios->Instance->WRFR;
}
/**
@@ -359,31 +359,31 @@
* @retval bit map of read registers addresses
*/
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
-{
- return hmdios->Instance->RDFR;
+{
+ return hmdios->Instance->RDFR;
}
/**
* @brief Clears Write registers flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
- * @retval HAL status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
-
+
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
/* Clear write registers flags */
hmdios->Instance->CWRFR |= (RegNum);
-
+
/* Release Lock */
__HAL_UNLOCK(hmdios);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -396,36 +396,36 @@
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
-
+
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
/* Clear read registers flags */
- hmdios->Instance->CRDFR |= (RegNum);
-
+ hmdios->Instance->CRDFR |= (RegNum);
+
/* Release Lock */
__HAL_UNLOCK(hmdios);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Enables Events for MDIOS peripheral
+ * @brief Enables Events for MDIOS peripheral
* @param hmdios: mdios handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
-{
+{
/* Process Locked */
__HAL_LOCK(hmdios);
-
+
/* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
__HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
-
+
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -443,12 +443,12 @@
{
/* Write callback function */
HAL_MDIOS_WriteCpltCallback(hmdios);
-
+
/* Clear write register flag */
HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
-
+
/* Read Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)
{
@@ -457,12 +457,12 @@
{
/* Read callback function */
HAL_MDIOS_ReadCpltCallback(hmdios);
-
+
/* Clear read register flag */
HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
-
+
/* Error Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)
{
@@ -471,13 +471,13 @@
{
/* Error Callback */
HAL_MDIOS_ErrorCallback(hmdios);
-
+
/* Clear errors flag */
__HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
}
}
#if defined(DUAL_CORE)
-
+
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
@@ -488,9 +488,9 @@
HAL_MDIOS_WakeUpCallback(hmdios);
}
}
- else
+ else
{
- if(__HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
+ if(__HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
{
/* Clear MDIOS WAKEUP Exti D2 pending bit */
__HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
@@ -498,7 +498,7 @@
HAL_MDIOS_WakeUpCallback(hmdios);
}
}
-#else
+#else
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
{
@@ -522,7 +522,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -537,7 +537,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -552,7 +552,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
@@ -564,36 +564,36 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MDIOS_WakeUpCallback could be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
- * @brief MDIOS control functions
+/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
+ * @brief MDIOS control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the MDIOS.
- (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
- (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
-
+ (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
+ (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
+
@endverbatim
* @{
*/
/**
- * @brief Gets MDIOS error flags
+ * @brief Gets MDIOS error flags
* @param hmdios: mdios handle
- * @retval bit map of occured errors
+ * @retval bit map of occured errors
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
{
@@ -615,11 +615,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#endif /* MDIOS */
#endif /* HAL_MDIOS_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdma.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdma.c
index 0066e81..3f80e62 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdma.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_mdma.c
@@ -2,140 +2,141 @@
******************************************************************************
* @file stm32mp1xx_hal_mdma.c
* @author MCD Application Team
- * @version V0.3.0
- * @date 9-December-2016
- * @brief MDMA HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ * @brief This file provides firmware functions to manage the following
* functionalities of the Master Direct Memory Access (MDMA) peripheral:
* + Initialization/de-initialization functions
* + I/O operation functions
* + Peripheral State and errors functions
- *
- *
- @verbatim
- ==============================================================================
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ==============================================================================
+ ==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the MDMA Channel
- (except for internal SRAM/FLASH memories: no initialization is
+ (except for internal SRAM/FLASH memories: no initialization is
necessary) please refer to Reference manual for connection between peripherals
- and MDMA requests.
-
- (#)
- (+) For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
- HW request (if any), channel priority, data endianness, request, Source increment,
- destination increment , source data size, destination data size, data alignment, source Burst,
- destination Burst , buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
- or full transfer) source and destination block address offset, mask address and data.
-
- (+) If using the MDMA in linked list mode then use function HAL_MDMA_CreateLinkedListNode to fill a transfer node.
- Parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
- Use function HAL_MDMA_ConnectLinkedListNode connect the created node to the linked list at a given position.
- User can make a circular linked list by connecting the first node at the end of the list (i.e after the last node)
- In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
- note the initial transfer itself (node 0).
- Function HAL_MDMA_DisConnectLinkedListNode can be used to remove (disconnect) a node from the transfer linked list.
- When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops),
- the linked list remains circular and node 2 becomes the first one.
- If the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+ and MDMA requests.
+ (#)
+ For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+ transfer request , channel priority, data endianness, Source increment, destination increment ,
+ source data size, destination data size, data alignment, source Burst, destination Burst ,
+ buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+ or full transfer) source and destination block address offset, mask address and data.
+ If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
+ Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+ Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
+ User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
+ last node of the list to the first one in order to make the list circular.
+ In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+
+ -@- The initial transfer itself (node 0 corresponding to the Init).
+ User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
+ the connection between last node and first one.
+
+ Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
+ When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops),
+ the linked list remains circular and node 2 becomes the first one.
+ Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+ [..]
(+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
transfer upon a request :
- + MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+ (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
with BufferTransferLength defined within the HAL_MDMA_Init.
- + MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
- with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT.
- + MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
- with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT.
- + MDMA_FULL_TRANSFER : each request triggers a full transfer
- all blocks and all nodes(if a linked list hase been created using HAL_MDMA_CreateLinkedListNode\HAL_MDMA_ConnectLinkedListNode).
+ (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+ with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+ or within the current linked list node parameters.
+ (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+ with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+ or within the current linked list node parameters.
+ (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
+ all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
*** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+ =================================
+ [..]
+ (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
address and destination address and the Length of data to be transferred.
(+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
- In this case a fixed Timeout can be configured by User depending from his application.
- (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+ In this case a fixed Timeout can be configured by User depending from his application.
+ (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
when the abort ends or timeout (should not be called from an interrupt service routine).
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
(+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred. In this
- case the MDMA interrupt is configured.
+ (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred. In this
+ case the MDMA interrupt is configured.
(+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of MDMA handle structure).
-
- (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API returns immediately
- then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel hase effectively aborted.
+ (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of MDMA handle structure).
+
+ (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
+ then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel has effectively aborted.
(could be called from an interrupt service routine).
-
+
(+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
from the following list :
(++) XferCpltCallback : transfer complete callback.
(++) XferBufferCpltCallback : buffer transfer complete callback.
(++) XferBlockCpltCallback : block transfer complete callback.
- (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
- (++) XferErrorCallback : transfer error callback.
- (++) XferAbortCallback : transfer abort complete callback.
-
+ (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+ (++) XferErrorCallback : transfer error callback.
+ (++) XferAbortCallback : transfer abort complete callback.
+
[..]
(+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
- trigger requests manually. function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
- - this function returns an error if used while the Transfer hase ends or not started.
- - if used while the current request hase not been served yet (current request transfer on going)
+ trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+ (++) This function returns an error if used while the Transfer has ended or not started.
+ (++) If used while the current request has not been served yet (current request transfer on going)
this function returns an error and the new request is ignored.
-
- Generally this function should be used in conjunctions with the MDMA callbacks:
- example 1:
- + Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
- + Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
- + After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
- + When the buffer transfer complete callback is asserted first buffer hase been transferred and user can ask for a new buffer transfer
- request using HAL_MDMA_GenerateSWRequest.
-
- example 2:
- + Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
- + Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
- + After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
- + When the block transfer complete callback is asserted the fisrt block hase been transferred and user can ask
- for a new block transfer request using HAL_MDMA_GenerateSWRequest.
- [..]
- (#) Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error
- detection.
+ Generally this function should be used in conjunctions with the MDMA callbacks:
+ (++) example 1:
+ (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+ (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+ (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+ (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
+ request using HAL_MDMA_GenerateSWRequest.
+
+ (++) example 2:
+ (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+ (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+ (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+ (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
+ for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+ [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
*** MDMA HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in MDMA HAL driver.
-
- (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Stream.
- (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Stream.
- (+) __HAL_MDMA_GET_FLAG: Get the MDMA Stream pending flags.
- (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Stream pending flags.
- (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Stream interrupts.
- (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Stream interrupts.
- (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Stream interrupt hase occurred or not.
-
- [..]
- (@) You can refer to the MDMA HAL driver header file for more useful macros
-
- @endverbatim
+
+ (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
+ (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
+ (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
+ (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
+ (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
+ (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
+ (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
+
+ [..]
+
+ @endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -144,7 +145,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -165,8 +166,8 @@
/** @addtogroup MDMA_Private_Constants
* @{
*/
-#define HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */
-#define HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */
+#define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */
/**
* @}
*/
@@ -189,48 +190,47 @@
/** @addtogroup MDMA_Exported_Functions_Group1
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
- ===============================================================================
+ ===============================================================================
[..]
This section provides functions allowing to :
Initialize and de-initialize the MDMA channel.
- Define and Add an MDMA linked list node.
- Register and Unregister MDMA callbacks
+ Register and Unregister MDMA callbacks
[..]
The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
- reference manual.
+ reference manual.
The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
- HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows
+ HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows
respectevely to register/unregister an MDMA callback function.
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the MDMA according to the specified
* parameters in the MDMA_InitTypeDef and create the associated handle.
* @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
{
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
assert_param(IS_MDMA_SECURE_MODE(hmdma->Init.SecureMode));
- assert_param(IS_MDMA_ENDIANESS_MODE(hmdma->Init.Endianess));
+ assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
@@ -242,12 +242,12 @@
assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
- assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
-
-
+ assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
/* Allocate lock resource */
__HAL_UNLOCK(hmdma);
-
+
if(hmdma->State == HAL_MDMA_STATE_RESET)
{
/* Init the low level hardware : GPIO, CLOCK */
@@ -256,100 +256,93 @@
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_BUSY;
-
+
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
-
+
/* Check if the MDMA channel is effectively disabled */
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
{
/* Update error code */
hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
-
+
/* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
+ hmdma->State = HAL_MDMA_STATE_ERROR;
+
+ return HAL_ERROR;
}
}
-
- /* Init MDMA channel registers */
+
+ /* Initialize the MDMA channel registers */
MDMA_Init(hmdma);
-
- /* Reset the MDMA first/last linkedlist node addresses and node counter */
- hmdma->FirstLinkedListNodeAddress = 0;
- hmdma->LastLinkedListNodeAddress = 0;
- hmdma->LinkedListNodeCounter = 0;
-
- /* Initialise the error code */
+
+ /* Reset the MDMA first/last linkedlist node addresses and node counter */
+ hmdma->FirstLinkedListNodeAddress = 0;
+ hmdma->LastLinkedListNodeAddress = 0;
+ hmdma->LinkedListNodeCounter = 0;
+
+ /* Initialize the error code */
hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
+
/* Initialize the MDMA state */
hmdma->State = HAL_MDMA_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the MDMA peripheral
+ * @brief DeInitializes the MDMA peripheral
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
-{
-
+{
+
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
}
-
- /* Check the MDMA peripheral state */
- if(hmdma->State == HAL_MDMA_STATE_BUSY)
- {
- hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
- return HAL_ERROR;
- }
-
+
/* Disable the selected MDMA Channelx */
__HAL_MDMA_DISABLE(hmdma);
-
+
/* Reset MDMA Channel control register */
hmdma->Instance->CCR = 0;
hmdma->Instance->CTCR = 0;
hmdma->Instance->CBNDTR = 0;
hmdma->Instance->CSAR = 0;
- hmdma->Instance->CDAR = 0;
+ hmdma->Instance->CDAR = 0;
hmdma->Instance->CBRUR = 0;
hmdma->Instance->CLAR = 0;
hmdma->Instance->CTBR = 0;
hmdma->Instance->CMAR = 0;
hmdma->Instance->CMDR = 0;
-
+
/* Clear all flags */
__HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
-
+
/* DeInit the low level hardware */
HAL_MDMA_MspDeInit(hmdma);
/* Reset the MDMA first/last linkedlist node addresses and node counter */
- hmdma->FirstLinkedListNodeAddress = 0;
- hmdma->LastLinkedListNodeAddress = 0;
- hmdma->LinkedListNodeCounter = 0;
-
- /* Initialise the error code */
+ hmdma->FirstLinkedListNodeAddress = 0;
+ hmdma->LastLinkedListNodeAddress = 0;
+ hmdma->LinkedListNodeCounter = 0;
+
+ /* Initialize the error code */
hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
+
/* Initialize the MDMA state */
hmdma->State = HAL_MDMA_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hmdma);
-
+
return HAL_OK;
}
@@ -361,7 +354,7 @@
* @param MaskData: specifies the value to be written to MaskAddress after a request is served.
* MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -371,34 +364,38 @@
{
return HAL_ERROR;
}
-
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
/* if HW request set Post Request MaskAddress and MaskData, */
- if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0)
+ if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
{
/* Set the HW request clear Mask and Data */
hmdma->Instance->CMAR = MaskAddress;
hmdma->Instance->CMDR = MaskData;
- /*
+ /*
-If the request is done by SW : BWM could be set to 1 or 0.
-If the request is done by a peripheral :
If mask address not set (0) => BWM must be set to 0
If mask address set (different than 0) => BWM could be set to 1 or 0
*/
- if(MaskAddress == 0)
+ if(MaskAddress == 0U)
{
hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM;
- }
+ }
+ else
+ {
+ hmdma->Instance->CTCR |= MDMA_CTCR_BWM;
+ }
}
else
{
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
}
else
@@ -408,8 +405,8 @@
}
/* Release Lock */
__HAL_UNLOCK(hmdma);
-
- return status;
+
+ return status;
}
/**
@@ -419,20 +416,20 @@
* @param CallbackID: User Callback identifier
* @param pCallback: pointer to callbacsk function.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
-{
+{
HAL_StatusTypeDef status = HAL_OK;
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
- }
-
+ }
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
switch (CallbackID)
@@ -440,27 +437,27 @@
case HAL_MDMA_XFER_CPLT_CB_ID:
hmdma->XferCpltCallback = pCallback;
break;
-
+
case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
hmdma->XferBufferCpltCallback = pCallback;
break;
-
+
case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
hmdma->XferBlockCpltCallback = pCallback;
break;
-
+
case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
hmdma->XferRepeatBlockCpltCallback = pCallback;
break;
-
+
case HAL_MDMA_XFER_ERROR_CB_ID:
hmdma->XferErrorCallback = pCallback;
break;
-
+
case HAL_MDMA_XFER_ABORT_CB_ID:
hmdma->XferAbortCallback = pCallback;
break;
-
+
default:
break;
}
@@ -470,10 +467,10 @@
/* Return error status */
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hmdma);
-
+
return status;
}
@@ -494,10 +491,10 @@
{
return HAL_ERROR;
}
-
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
switch (CallbackID)
@@ -505,27 +502,27 @@
case HAL_MDMA_XFER_CPLT_CB_ID:
hmdma->XferCpltCallback = NULL;
break;
-
+
case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
hmdma->XferBufferCpltCallback = NULL;
break;
-
+
case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
hmdma->XferBlockCpltCallback = NULL;
break;
-
+
case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
hmdma->XferRepeatBlockCpltCallback = NULL;
break;
-
+
case HAL_MDMA_XFER_ERROR_CB_ID:
hmdma->XferErrorCallback = NULL;
break;
-
+
case HAL_MDMA_XFER_ABORT_CB_ID:
hmdma->XferAbortCallback = NULL;
- break;
-
+ break;
+
case HAL_MDMA_XFER_ALL_CB_ID:
hmdma->XferCpltCallback = NULL;
hmdma->XferBufferCpltCallback = NULL;
@@ -533,8 +530,8 @@
hmdma->XferRepeatBlockCpltCallback = NULL;
hmdma->XferErrorCallback = NULL;
hmdma->XferAbortCallback = NULL;
- break;
-
+ break;
+
default:
status = HAL_ERROR;
break;
@@ -544,10 +541,10 @@
{
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hmdma);
-
+
return status;
}
@@ -557,14 +554,15 @@
/** @addtogroup MDMA_Exported_Functions_Group2
*
-@verbatim
+@verbatim
===============================================================================
##### Linked list operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Create a linked list node
(+) Add a node to the MDMA linked list
(+) Remove a node from the MDMA linked list
+ (+) Enable/Disable linked list circular mode
@endverbatim
* @{
*/
@@ -572,26 +570,27 @@
/**
* @brief Initializes an MDMA Link Node according to the specified
* parameters in the pMDMA_LinkedListNodeConfig .
- * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
- * registers configurations.
+ * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * registers configurations.
* @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
- * the configuration information for the specified MDMA Linked List Node.
+ * the configuration information for the specified MDMA Linked List Node.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
{
- uint32_t addressMask = 0;
-
+ uint32_t addressMask;
+ uint32_t blockoffset;
+
/* Check the MDMA peripheral state */
if((pNode == NULL) || (pNodeConfig == NULL))
{
return HAL_ERROR;
- }
-
+ }
+
/* Check the parameters */
assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
assert_param(IS_MDMA_SECURE_MODE(pNodeConfig->Init.SecureMode));
- assert_param(IS_MDMA_ENDIANESS_MODE(pNodeConfig->Init.Endianess));
+ assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
@@ -604,82 +603,85 @@
assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
-
+
assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
-
-
- /*configure next Link node Address Register to zero */
+ assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+ /* Configure next Link node Address Register to zero */
pNode->CLAR = 0;
-
- /*Configure the Link Node registers*/
+
+ /* Configure the Link Node registers*/
pNode->CTBR = 0;
- pNode->CMAR = 0;
+ pNode->CMAR = 0;
pNode->CMDR = 0;
-
- /* write new CTCR Register value */
- pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
- pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \
- pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \
- pNodeConfig->Init.DestBurst | \
- ((pNodeConfig->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
+ pNode->Reserved = 0;
+
+ /* Write new CTCR Register value */
+ pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+ pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \
+ pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \
+ pNodeConfig->Init.DestBurst | \
+ ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
pNodeConfig->Init.TransferTriggerMode;
-
+
/* If SW request set the CTCR register to SW Request Mode*/
if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
{
pNode->CTCR |= MDMA_CTCR_SWRM;
}
-
- /*
+
+ /*
-If the request is done by SW : BWM could be set to 1 or 0.
-If the request is done by a peripheral :
If mask address not set (0) => BWM must be set to 0
If mask address set (different than 0) => BWM could be set to 1 or 0
*/
- if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0))
+ if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
{
pNode->CTCR |= MDMA_CTCR_BWM;
}
-
- /* Set the new CBNDTR Register value */
- pNode->CBNDTR = ((pNodeConfig->BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC;
-
+
+ /* Set the new CBNDTR Register value */
+ pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
+
/* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
{
pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
- /*write new CBRUR Register value : source repeat block offset */
- pNode->CBRUR = (((uint32_t)(-1 * pNodeConfig->Init.SourceBlockAddressOffset)) & 0x0000FFFFU);
+ /*write new CBRUR Register value : source repeat block offset */
+ blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
+ pNode->CBRUR = blockoffset & 0x0000FFFFU;
}
else
{
- /*write new CBRUR Register value : source repeat block offset */
- pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
- }
-
+ /*write new CBRUR Register value : source repeat block offset */
+ pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+ }
+
/* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
if(pNodeConfig->Init.DestBlockAddressOffset < 0)
{
pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
- /*write new CBRUR Register value : destination repeat block offset */
- pNode->CBRUR |= (((uint32_t)(-1 * pNodeConfig->Init.DestBlockAddressOffset)) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ /*write new CBRUR Register value : destination repeat block offset */
+ blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
+ pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
}
else
{
- /*write new CBRUR Register value : destination repeat block offset */
- pNode->CBRUR |= (((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
- }
-
+ /*write new CBRUR Register value : destination repeat block offset */
+ pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+ }
+
/* Configure MDMA Link Node data length */
pNode->CBNDTR |= pNodeConfig->BlockDataLength;
-
+
/* Configure MDMA Link Node destination address */
- pNode->CDAR = pNodeConfig->DstAddress;
-
+ pNode->CDAR = pNodeConfig->DstAddress;
+
/* Configure MDMA Link Node Source address */
pNode->CSAR = pNodeConfig->SrcAddress;
-
+
/* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
{
@@ -687,75 +689,75 @@
pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
/* Set the HW request clear Mask and Data */
pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
- pNode->CMDR = pNodeConfig->PostRequestMaskData;
+ pNode->CMDR = pNodeConfig->PostRequestMaskData;
}
-
+
addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
{
/*The AHBSbus is used as source (read operation) on channel x */
- pNode->CTBR |= MDMA_CTBR_SBUS;
+ pNode->CTBR |= MDMA_CTBR_SBUS;
}
-
+
addressMask = pNodeConfig->DstAddress & 0xFF000000U;
if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
{
/*The AHB bus is used as destination (write operation) on channel x */
pNode->CTBR |= MDMA_CTBR_DBUS;
}
-
+
return HAL_OK;
}
/**
- * @brief Connect a node to the linked list
- * parameters in the MDMA_InitTypeDef .
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * @brief Connect a node to the linked list.
+ * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
* to be add to the list.
* @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
- * at the end of the list
+ * at the end of the list
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
{
- MDMA_LinkNodeTypeDef *pNode = 0;
- uint32_t counter = 0, nodeConter = 0, nodeInserted = 0;
- HAL_StatusTypeDef hal_status = HAL_OK;
-
+ MDMA_LinkNodeTypeDef *pNode;
+ uint32_t counter = 0, nodeInserted = 0;
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
/* Check the MDMA peripheral handle */
if((hmdma == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
- }
-
+ }
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_BUSY;
-
+
/* Check if this is the first node (after the Inititlization node) */
- if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0)
+ if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
{
if(pPrevNode == NULL)
{
- /* if this is the first node after the initialization
+ /* if this is the first node after the initialization
connect this node to the node 0 by updating
the MDMA channel CLAR register to this node address */
hmdma->Instance->CLAR = (uint32_t)pNewNode;
/* Set the MDMA handle First linked List node*/
hmdma->FirstLinkedListNodeAddress = pNewNode;
-
+
/*reset New node link */
pNewNode->CLAR = 0;
-
- /* Update the Handle last node address */
+
+ /* Update the Handle last node address */
hmdma->LastLinkedListNodeAddress = pNewNode;
-
+
hmdma->LinkedListNodeCounter = 1;
}
else
@@ -763,150 +765,116 @@
hal_status = HAL_ERROR;
}
}
- else if(((uint32_t)hmdma->LastLinkedListNodeAddress != 0) && (hmdma->LinkedListNodeCounter != 0))
+ else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
{
- /* if new node is equal to first node then linked list is circular */
- if(hmdma->FirstLinkedListNodeAddress == pNewNode)
+ /* Check if the node to insert already exists*/
+ pNode = hmdma->FirstLinkedListNodeAddress;
+ while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
{
- pNode = hmdma->FirstLinkedListNodeAddress;
- if(pPrevNode == 0)
+ if(pNode->CLAR == (uint32_t)pNewNode)
{
- pPrevNode = hmdma->LastLinkedListNodeAddress;
+ hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
}
- while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
+ pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+ counter++;
+ }
+
+ if(hal_status == HAL_OK)
+ {
+ /* Check if the previous node is the last one in the current list or zero */
+ if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
{
- if(pNode == pPrevNode)
- {
- pNode->CLAR = (uint32_t)pNewNode;
- hmdma->LastLinkedListNodeAddress = pNode;
- nodeInserted = 1;
- }
-
- pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
- nodeConter++;
- counter ++;
- }
- if(nodeInserted == 0)
- {
- hal_status = HAL_ERROR;
+ /* insert the new node at the end of the list */
+ pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+ hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+ /* Update the Handle last node address */
+ hmdma->LastLinkedListNodeAddress = pNewNode;
+ /* Increment the linked list node counter */
+ hmdma->LinkedListNodeCounter++;
}
else
{
- /* update linked lis counter */
- hmdma->LinkedListNodeCounter = nodeConter;
+ /*insert the new node after the pPreviousNode node */
+ pNode = hmdma->FirstLinkedListNodeAddress;
+ counter = 0;
+ while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
+ {
+ counter++;
+ if(pNode == pPrevNode)
+ {
+ /*Insert the new node after the previous one */
+ pNewNode->CLAR = pNode->CLAR;
+ pNode->CLAR = (uint32_t)pNewNode;
+ /* Increment the linked list node counter */
+ hmdma->LinkedListNodeCounter++;
+ nodeInserted = 1;
+ }
+ else
+ {
+ pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+ }
+ }
+
+ if(nodeInserted == 0U)
+ {
+ hal_status = HAL_ERROR;
+ }
}
}
- else
- {
- /* Check if the node to insert already exists*/
- pNode = hmdma->FirstLinkedListNodeAddress;
- while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
- {
- if(pNode->CLAR == (uint32_t)pNewNode)
- {
- hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
- }
- pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
- counter++;
- }
-
- if(hal_status == HAL_OK)
- {
- /* Check if the previous node is the last one in the current list or zero */
- if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == 0))
- {
- /* insert the new node at the end of the list. */
- pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
- hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
- /* Update the Handle last node address */
- hmdma->LastLinkedListNodeAddress = pNewNode;
- /* Increment the linked list node counter */
- hmdma->LinkedListNodeCounter++;
- }
- else
- {
- /*insert the new node after the pPreviousNode node */
- pNode = hmdma->FirstLinkedListNodeAddress;
- counter = 0;
- while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
- {
- counter++;
- if(pNode == pPrevNode)
- {
- /*Insert the new node after the previous one */
- pNewNode->CLAR = pNode->CLAR;
- pNode->CLAR = (uint32_t)pNewNode;
- /* Increment the linked list node counter */
- hmdma->LinkedListNodeCounter++;
- nodeInserted = 1;
- }
- else
- {
- pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
- }
- }
-
- if(nodeInserted == 0)
- {
- hal_status = HAL_ERROR;
- }
- }
- }
- }
}
else
{
- hal_status = HAL_ERROR;
+ hal_status = HAL_ERROR;
}
-
+
/* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
+ __HAL_UNLOCK(hmdma);
+
hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
+
+ return hal_status;
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Return error status */
return HAL_BUSY;
- }
+ }
}
/**
- * @brief Disconnect/Remove a node from the transfer linked list
- * parameters in the MDMA_InitTypeDef .
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
- * to be removed from the list.
+ * @brief Disconnect/Remove a node from the transfer linked list.
+ * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * to be removed from the list.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
{
- MDMA_LinkNodeTypeDef *ptmpNode = 0;
+ MDMA_LinkNodeTypeDef *ptmpNode;
uint32_t counter = 0, nodeDeleted = 0;
- HAL_StatusTypeDef hal_status = HAL_OK;
-
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
/* Check the MDMA peripheral handle */
if((hmdma == NULL) || (pNode == NULL))
{
return HAL_ERROR;
- }
-
+ }
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_BUSY;
-
+
/* If first and last node are null (no nodes in the list) : return error*/
- if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
+ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
{
hal_status = HAL_ERROR;
}
@@ -917,11 +885,11 @@
{
/*if the last node is at the same time the first one (1 single node after the init node 0)
then update the last node too */
-
+
hmdma->FirstLinkedListNodeAddress = 0;
hmdma->LastLinkedListNodeAddress = 0;
hmdma->LinkedListNodeCounter = 0;
-
+
hmdma->Instance->CLAR = 0;
}
else
@@ -931,21 +899,21 @@
/* if last node is looping to first (circular list) one update the last node connection */
hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
}
-
- /* if deleting the first node after the initialization
+
+ /* if deleting the first node after the initialization
connect the next node to the node 0 by updating
- the MDMA channel CLAR register to this node address */
+ the MDMA channel CLAR register to this node address */
hmdma->Instance->CLAR = pNode->CLAR;
hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
/* Update the Handle node counter */
- hmdma->LinkedListNodeCounter--;
- }
+ hmdma->LinkedListNodeCounter--;
+ }
}
else /* Deleting any other node */
{
- /*Deleted node is not the first one : find it */
+ /*Deleted node is not the first one : find it */
ptmpNode = hmdma->FirstLinkedListNodeAddress;
- while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0))
+ while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
{
counter++;
if(ptmpNode->CLAR == ((uint32_t)pNode))
@@ -960,36 +928,124 @@
ptmpNode->CLAR = pNode->CLAR;
nodeDeleted = 1;
/* Update the Handle node counter */
- hmdma->LinkedListNodeCounter--;
+ hmdma->LinkedListNodeCounter--;
}
else
{
ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
}
}
-
- if(nodeDeleted == 0)
+
+ if(nodeDeleted == 0U)
{
/* last node reashed without finding the node to delete : return error */
hal_status = HAL_ERROR;
}
}
-
+
/* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
+ __HAL_UNLOCK(hmdma);
+
hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
+
+ return hal_status;
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Return error status */
return HAL_BUSY;
- }
+ }
+}
+
+/**
+ * @brief Make the linked list circular by connecting the last node to the first.
+ * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* If first and last node are null (no nodes in the list) : return error*/
+ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+ {
+ hal_status = HAL_ERROR;
+ }
+ else
+ {
+ /* to enable circular mode Last Node should be connected to first node */
+ hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+ }
+
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return hal_status;
+}
+
+/**
+ * @brief Disable the linked list circular mode by setting the last node connection to null
+ * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* If first and last node are null (no nodes in the list) : return error*/
+ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+ {
+ hal_status = HAL_ERROR;
+ }
+ else
+ {
+ /* to disable circular mode Last Node should be connected to NULL */
+ hmdma->LastLinkedListNodeAddress->CLAR = 0;
+ }
+
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return hal_status;
}
/**
@@ -998,17 +1054,18 @@
/** @addtogroup MDMA_Exported_Functions_Group3
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start MDMA transfer
- (+) Configure the source, destination address and data length and
+ (+) Configure the source, destination address and data length and
Start MDMA transfer with interrupt
(+) Abort MDMA transfer
(+) Poll for transfer complete
- (+) Handle MDMA interrupt request
+ (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
+ (+) Handle MDMA interrupt request
@endverbatim
* @{
@@ -1017,69 +1074,67 @@
/**
* @brief Starts the MDMA Transfer.
* @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @param SrcAddress : The source memory Buffer address
* @param DstAddress : The destination memory Buffer address
* @param BlockDataLength : The length of a block transfer in bytes
* @param BlockCount : The number of a blocks to be transfer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
{
/* Check the parameters */
assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+ assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
}
-
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_BUSY;
-
+
/* Initialize the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
/* Disable the peripheral */
__HAL_MDMA_DISABLE(hmdma);
-
+
/* Configure the source, destination address and the data length */
MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
-
-
+
/* Enable the Peripheral */
__HAL_MDMA_ENABLE(hmdma);
-
-
+
if(hmdma->Init.Request == MDMA_REQUEST_SW)
{
/* activate If SW request mode*/
hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
- }
+ }
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Return error status */
return HAL_BUSY;
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief Starts the MDMA Transfer with interrupts enabled.
* @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @param SrcAddress : The source memory Buffer address
* @param DstAddress : The destination memory Buffer address
* @param BlockDataLength : The length of a block transfer in bytes
@@ -1090,83 +1145,83 @@
{
/* Check the parameters */
assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+ assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
}
-
+
/* Process locked */
__HAL_LOCK(hmdma);
-
+
if(HAL_MDMA_STATE_READY == hmdma->State)
{
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_BUSY;
-
+
/* Initialize the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
/* Disable the peripheral */
__HAL_MDMA_DISABLE(hmdma);
-
+
/* Configure the source, destination address and the data length */
MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
-
+
/* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
__HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
-
+
if(hmdma->XferBlockCpltCallback != NULL)
{
/* if Block transfer complete Callback is set enable the corresponding IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
}
-
+
if(hmdma->XferRepeatBlockCpltCallback != NULL)
{
- /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
- }
-
+ /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+ }
+
if(hmdma->XferBufferCpltCallback != NULL)
{
/* if buffer transfer complete Callback is set enable the corresponding IT*/
__HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
}
-
+
/* Enable the Peripheral */
__HAL_MDMA_ENABLE(hmdma);
-
+
if(hmdma->Init.Request == MDMA_REQUEST_SW)
{
/* activate If SW request mode*/
hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
- }
+ }
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Return error status */
return HAL_BUSY;
}
-
+
return HAL_OK;
-}
+}
/**
* @brief Aborts the MDMA Transfer.
* @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
* the configuration information for the specified MDMA Channel.
- *
- * @note After disabling a MDMA Stream, a check for wait until the MDMA Channel is
- * effectively disabled is added. If a Stream is disabled
+ *
+ * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is
+ * effectively disabled is added. If a Channel is disabled
* while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
+ * and the Channel will be effectively disabled only after the transfer of
+ * this single data is finished.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
@@ -1177,55 +1232,55 @@
if(hmdma == NULL)
{
return HAL_ERROR;
- }
-
+ }
+
if(HAL_MDMA_STATE_BUSY != hmdma->State)
{
hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hmdma);
-
+
return HAL_ERROR;
}
else
{
/* Disable all the transfer interrupts */
__HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
-
+
/* Disable the channel */
__HAL_MDMA_DISABLE(hmdma);
-
+
/* Check if the MDMA Channel is effectively disabled */
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0)
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
{
/* Update error code */
hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
+ hmdma->State = HAL_MDMA_STATE_ERROR;
+
+ return HAL_ERROR;
}
}
-
+
/* Clear all interrupt flags */
__HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
-
+
/* Process Unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Change the MDMA state*/
- hmdma->State = HAL_MDMA_STATE_READY;
+ hmdma->State = HAL_MDMA_STATE_READY;
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -1241,21 +1296,23 @@
{
return HAL_ERROR;
}
-
+
if(HAL_MDMA_STATE_BUSY != hmdma->State)
{
+ /* No transfer ongoing */
hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
return HAL_ERROR;
}
else
{
/* Set Abort State */
hmdma->State = HAL_MDMA_STATE_ABORT;
-
+
/* Disable the stream */
__HAL_MDMA_DISABLE(hmdma);
}
-
+
return HAL_OK;
}
@@ -1263,15 +1320,15 @@
* @brief Polling for transfer complete.
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
* the configuration information for the specified MDMA Channel.
- * @param CompleteLevel: Specifies the MDMA level complete.
+ * @param CompleteLevel: Specifies the MDMA level complete.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
{
- uint32_t levelFlag = 0, errorFlag = 0;
- uint32_t tickstart = 0;
-
+ uint32_t levelFlag, errorFlag;
+ uint32_t tickstart;
+
/* Check the parameters */
assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
@@ -1279,34 +1336,34 @@
if(hmdma == NULL)
{
return HAL_ERROR;
- }
-
+ }
+
if(HAL_MDMA_STATE_BUSY != hmdma->State)
{
/* No transfer ongoing */
hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
-
+
return HAL_ERROR;
- }
-
+ }
+
/* Get the level transfer complete flag */
- levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC :\
- (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC :\
- (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT :\
- MDMA_FLAG_BRT);
-
-
+ levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \
+ (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
+ (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \
+ MDMA_FLAG_BRT);
+
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == RESET)
+
+ while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
{
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
- {
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+ {
/* Get the transfer error source flag */
errorFlag = hmdma->Instance->CESR;
-
- if((errorFlag & MDMA_CESR_TED) == 0)
+
+ if((errorFlag & MDMA_CESR_TED) == 0U)
{
/* Update error code : Read Transfer error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
@@ -1314,174 +1371,186 @@
else
{
/* Update error code : Write Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
}
-
- if((errorFlag & MDMA_CESR_TEMD) != 0)
+
+ if((errorFlag & MDMA_CESR_TEMD) != 0U)
{
/* Update error code : Error Mask Data */
hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
}
-
- if((errorFlag & MDMA_CESR_TELD) != 0)
+
+ if((errorFlag & MDMA_CESR_TELD) != 0U)
{
/* Update error code : Error Linked list */
hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
}
-
- if((errorFlag & MDMA_CESR_ASE) != 0)
+
+ if((errorFlag & MDMA_CESR_ASE) != 0U)
{
/* Update error code : Address/Size alignment error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
}
-
- if((errorFlag & MDMA_CESR_BSE) != 0)
+
+ if((errorFlag & MDMA_CESR_BSE) != 0U)
{
/* Update error code : Block Size error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
- }
-
- HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
-
- /* Clear the transfer error flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change the MDMA state */
- hmdma->State= HAL_MDMA_STATE_READY;
-
+ }
+
+ (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+ /*
+ Note that the Abort function will
+ - Clear all transfer flags
+ - Unlock
+ - Set the State
+ */
+
return HAL_ERROR;
-
+
}
-
+
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return HAL_TIMEOUT;
+
+ (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
+
+ /*
+ Note that the Abort function will
+ - Clear all transfer flags
+ - Unlock
+ - Set the State
+ */
+
+ return HAL_ERROR;
}
}
}
-
+
/* Clear the transfer level flag */
if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
{
__HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
-
+
}
else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
{
__HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
-
+
}
else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
{
- __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
- }
+ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+ }
else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
{
__HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
-
+
/* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
+ __HAL_UNLOCK(hmdma);
+
hmdma->State = HAL_MDMA_STATE_READY;
}
-
+ else
+ {
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
/**
* @brief Generate an MDMA SW request trigger to activate the request on the given Channel.
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
{
+ uint32_t request_mode;
+
/* Check the MDMA peripheral handle */
if(hmdma == NULL)
{
return HAL_ERROR;
}
-
- if((hmdma->Instance->CCR & MDMA_CCR_EN) == RESET)
+
+ /* Get the softawre request mode */
+ request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
+
+ if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U)
{
/* if no Transfer on going (MDMA enable bit not set) retrun error */
hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
- return HAL_ERROR;
+
+ return HAL_ERROR;
}
- else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != RESET) || ((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == RESET))
+ else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
{
- /* if an MDMA ongoing request hase not yet ends or if request mode is not SW request retrun error */
+ /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
- return HAL_ERROR;
+
+ return HAL_ERROR;
}
else
{
/* Set the SW request bit to activate the request on the Channel */
hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
-
+
return HAL_OK;
}
-}
+}
/**
* @brief Handles MDMA interrupt request.
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @retval None
*/
void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
{
__IO uint32_t count = 0;
- uint32_t timeout = SystemCoreClock / 9600;
-
+ uint32_t timeout = SystemCoreClock / 9600U;
+
uint32_t generalIntFlag, errorFlag;
-
- /* General Interrupt Flag management ****************************************/
- if((hmdma->Instance->CCR & MDMA_CCR_SM) != MDMA_CCR_SM)
+
+ /* General Interrupt Flag management ****************************************/
+ generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+ if((hmdma->Instance->CCR & MDMA_CCR_SM) != MDMA_CCR_SM)
{
/*Check non secure mode general flag */
- generalIntFlag = 1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
- if((MDMA->GISR0 & generalIntFlag) == RESET)
+ if((MDMA->GISR0 & generalIntFlag) == 0U)
{
- return; /* the General interrupt flag for the current channel is down , nothing to do */
- }
+ return; /* the General interrupt flag for the current channel is down , nothing to do */
+ }
}
else
{
/*Check secure mode general flag */
- generalIntFlag = 1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
- if((MDMA->SGISR0 & generalIntFlag) == RESET)
+ if((MDMA->SGISR0 & generalIntFlag) == 0U)
{
- return; /* the General interrupt flag for the current channel is down , nothing to do */
- }
+ return; /* the General interrupt flag for the current channel is down , nothing to do */
+ }
}
+
/* Transfer Error Interrupt management ***************************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
{
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != RESET)
- {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+ {
/* Disable the transfer error interrupt */
__HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
-
+
/* Get the transfer error source flag */
errorFlag = hmdma->Instance->CESR;
-
- if((errorFlag & MDMA_CESR_TED) == 0)
+
+ if((errorFlag & MDMA_CESR_TED) == 0U)
{
/* Update error code : Read Transfer error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
@@ -1489,134 +1558,134 @@
else
{
/* Update error code : Write Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
}
-
- if((errorFlag & MDMA_CESR_TEMD) != 0)
+
+ if((errorFlag & MDMA_CESR_TEMD) != 0U)
{
/* Update error code : Error Mask Data */
hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
}
-
- if((errorFlag & MDMA_CESR_TELD) != 0)
+
+ if((errorFlag & MDMA_CESR_TELD) != 0U)
{
/* Update error code : Error Linked list */
hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
}
-
- if((errorFlag & MDMA_CESR_ASE) != 0)
+
+ if((errorFlag & MDMA_CESR_ASE) != 0U)
{
/* Update error code : Address/Size alignment error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
}
-
- if((errorFlag & MDMA_CESR_BSE) != 0)
+
+ if((errorFlag & MDMA_CESR_BSE) != 0U)
{
/* Update error code : Block Size error error */
hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
- }
-
+ }
+
/* Clear the transfer error flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
}
}
-
+
/* Buffer Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != RESET))
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
{
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != RESET)
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
{
/* Clear the buffer transfer complete flag */
__HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
-
+
if(hmdma->XferBufferCpltCallback != NULL)
{
/* Buffer transfer callback */
hmdma->XferBufferCpltCallback(hmdma);
- }
+ }
}
}
-
+
/* Block Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != RESET))
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
{
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != RESET)
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
{
/* Clear the block transfer complete flag */
__HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
-
+
if(hmdma->XferBlockCpltCallback != NULL)
{
/* Block transfer callback */
hmdma->XferBlockCpltCallback(hmdma);
- }
+ }
}
}
-
+
/* Repeated Block Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != RESET))
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
{
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != RESET)
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
{
/* Clear the repeat block transfer complete flag */
__HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
-
+
if(hmdma->XferRepeatBlockCpltCallback != NULL)
{
/* Repeated Block transfer callback */
hmdma->XferRepeatBlockCpltCallback(hmdma);
- }
+ }
}
- }
-
+ }
+
/* Channel Transfer Complete Interrupt management ***********************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != RESET))
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
{
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != RESET)
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
{
/* Disable all the transfer interrupts */
__HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
-
+
if(HAL_MDMA_STATE_ABORT == hmdma->State)
{
/* Process Unlocked */
__HAL_UNLOCK(hmdma);
-
+
/* Change the DMA state */
hmdma->State = HAL_MDMA_STATE_READY;
-
+
if(hmdma->XferAbortCallback != NULL)
{
hmdma->XferAbortCallback(hmdma);
}
return;
-
}
+
/* Clear the Channel Transfer Complete flag */
__HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
+ __HAL_UNLOCK(hmdma);
+
/* Change MDMA peripheral state */
hmdma->State = HAL_MDMA_STATE_READY;
-
+
if(hmdma->XferCpltCallback != NULL)
{
/* Channel Transfer Complete callback */
hmdma->XferCpltCallback(hmdma);
- }
+ }
}
}
-
+
/* manage error case */
if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
{
hmdma->State = HAL_MDMA_STATE_ABORT;
-
+
/* Disable the channel */
__HAL_MDMA_DISABLE(hmdma);
-
+
do
{
if (++count > timeout)
@@ -1624,21 +1693,29 @@
break;
}
}
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET);
-
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+
/* Process Unlocked */
__HAL_UNLOCK(hmdma);
-
- /* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_READY;
-
+
+ if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+ {
+ /* Change the MDMA state to error if MDMA disable fails */
+ hmdma->State = HAL_MDMA_STATE_ERROR;
+ }
+ else
+ {
+ /* Change the MDMA state to Ready if MDMA disable success */
+ hmdma->State = HAL_MDMA_STATE_READY;
+ }
+
+
if (hmdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hmdma->XferErrorCallback(hmdma);
}
}
-
}
/**
@@ -1663,7 +1740,7 @@
/**
* @brief Returns the MDMA state.
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @retval HAL state
*/
HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
@@ -1674,7 +1751,7 @@
/**
* @brief Return the MDMA error code
* @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @retval MDMA Error Code
*/
uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
@@ -1690,50 +1767,51 @@
* @}
*/
-/** @addtogroup JPEG_Private_Functions
+/** @addtogroup MDMA_Private_Functions
* @{
*/
/**
* @brief Sets the MDMA Transfer parameter.
* @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
+ * the configuration information for the specified MDMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param BlockDataLength : The length of a block transfer in bytes
- * @param BlockCount: The number of a blocks to be transfer
+ * @param BlockCount: The number of blocks to be transfered
* @retval HAL status
*/
static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
{
uint32_t addressMask;
- /* Configure MDMA Channel data length */
+
+ /* Configure the MDMA Channel data length */
MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
-
- /*Configure the MDMA block repeat count*/
- MODIFY_REG( hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC);
-
+
+ /* Configure the MDMA block repeat count */
+ MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
+
/* Clear all interrupt flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
-
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
/* Configure MDMA Channel destination address */
- hmdma->Instance->CDAR = DstAddress;
-
+ hmdma->Instance->CDAR = DstAddress;
+
/* Configure MDMA Channel Source address */
hmdma->Instance->CSAR = SrcAddress;
-
+
addressMask = SrcAddress & 0xFF000000U;
if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
{
/*The AHBSbus is used as source (read operation) on channel x */
- hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+ hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
}
else
{
/*The AXI bus is used as source (read operation) on channel x */
- hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+ hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
}
-
+
addressMask = DstAddress & 0xFF000000U;
if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
{
@@ -1743,77 +1821,96 @@
else
{
/*The AXI bus is used as destination (write operation) on channel x */
- hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+ hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
}
-
- /* Set the linked list rgeitser to the first node of the list */
- hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+
+ /* Set the linked list register to the first node of the list */
+ hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
}
+/**
+ * @brief Initializes the MDMA handle according to the specified
+ * parameters in the MDMA_InitTypeDef
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @retval None
+ */
static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
{
+ uint32_t blockoffset;
+
/* Prepare the MDMA Channel configuration */
- hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.SecureMode | hmdma->Init.Endianess;
-
- /* write new CTCR Register value */
- hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \
- hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \
- hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \
- hmdma->Init.DestBurst | \
- ((hmdma->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
- hmdma->Init.TransferTriggerMode;
-
- /* If SW request set the CTCR register to SW Request Mode*/
+ hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.SecureMode | hmdma->Init.Endianness;
+
+ /* Write new CTCR Register value */
+ hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \
+ hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \
+ hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \
+ hmdma->Init.DestBurst | \
+ ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+ hmdma->Init.TransferTriggerMode;
+
+ /* If SW request set the CTCR register to SW Request Mode */
if(hmdma->Init.Request == MDMA_REQUEST_SW)
{
- hmdma->Instance->CTCR |= MDMA_CTCR_SWRM;
+ /*
+ -If the request is done by SW : BWM could be set to 1 or 0.
+ -If the request is done by a peripheral :
+ If mask address not set (0) => BWM must be set to 0
+ If mask address set (different than 0) => BWM could be set to 1 or 0
+ */
+ hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
}
-
- /* Reset CBNDTR Register */
+
+ /* Reset CBNDTR Register */
hmdma->Instance->CBNDTR = 0;
-
+
/* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
if(hmdma->Init.SourceBlockAddressOffset < 0)
{
hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
- /*write new CBRUR Register value : source repeat block offset */
- hmdma->Instance->CBRUR = (((uint32_t)(-1 * hmdma->Init.SourceBlockAddressOffset)) & 0x0000FFFFU);
+ /* Write new CBRUR Register value : source repeat block offset */
+ blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+ hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
}
else
{
- /*write new CBRUR Register value : source repeat block offset */
- hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+ /* Write new CBRUR Register value : source repeat block offset */
+ hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
}
-
- /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+
+ /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
if(hmdma->Init.DestBlockAddressOffset < 0)
{
hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
- /*write new CBRUR Register value : destination repeat block offset */
- hmdma->Instance->CBRUR |= (((uint32_t)(-1 * hmdma->Init.DestBlockAddressOffset)) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ /* Write new CBRUR Register value : destination repeat block offset */
+ blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+ hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
}
else
{
- /*write new CBRUR Register value : destination repeat block offset */
- hmdma->Instance->CBRUR |= (((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
- }
-
- /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+ /*write new CBRUR Register value : destination repeat block offset */
+ hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+ }
+
+ /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
if(hmdma->Init.Request != MDMA_REQUEST_SW)
{
/* Set the HW request in CTRB register */
- hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+ hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
}
else /* SW request : reset the CTBR register */
{
hmdma->Instance->CTBR = 0;
}
-
- /*Write Link Address Register*/
+
+ /* Write Link Address Register */
hmdma->Instance->CLAR = 0;
}
-
+/**
+ * @}
+ */
/**
* @brief MDMA MSP Init
* @param hmdma: MDMA handle
@@ -1841,7 +1938,6 @@
/**
* @}
*/
-
#endif /* HAL_MDMA_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_pwr.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_pwr.c
index 5fe1263..8e7b1a7 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_pwr.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_pwr.c
@@ -607,7 +607,13 @@
SET_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
/* RCC Stop Request Set Register */
+#if defined(RCC_MP_SREQSETR_STPREQ_P0) & defined(RCC_MP_SREQSETR_STPREQ_P1)
+ /* CA7_CORE0 and CA7_CORE1 available */
RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#else
+ /* Only CA7_CORE0 available */
+ RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0;
+#endif /* RCC_MP_SREQSETR_STPREQ_P0 & RCC_MP_SREQSETR_STPREQ_P1 */
#else
/* Prevent unused argument compilation warning */
@@ -635,7 +641,13 @@
#ifdef CORE_CA7
/* RCC Clear Request Set Register */
- RCC->MP_SREQCLRR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#if defined(RCC_MP_SREQCLRR_STPREQ_P0) & defined(RCC_MP_SREQCLRR_STPREQ_P1)
+ /* CA7_CORE0 and CA7_CORE1 available */
+ RCC->MP_SREQCLRR = RCC_MP_SREQCLRR_STPREQ_P0 | RCC_MP_SREQCLRR_STPREQ_P1;
+#else
+ /* Only CA7_CORE0 available */
+ RCC->MP_SREQCLRR = RCC_MP_SREQCLRR_STPREQ_P0;
+#endif /* RCC_MP_SREQCLRR_STPREQ_P0 | RCC_MP_SREQCLRR_STPREQ_P1 */
#endif
}
@@ -672,7 +684,13 @@
CLEAR_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
/* RCC Stop Request Set Register */
+#if defined(RCC_MP_SREQSETR_STPREQ_P0) & defined(RCC_MP_SREQSETR_STPREQ_P1)
+ /* CA7_CORE0 and CA7_CORE1 available */
RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#else
+ /* Only CA7_CORE0 available */
+ RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0;
+#endif /* RCC_MP_SREQSETR_STPREQ_P0 & RCC_MP_SREQSETR_STPREQ_P1 */
#endif
/* Clear Reset Status */
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_qspi.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_qspi.c
index 5963389..189bdfd 100755
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_qspi.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_qspi.c
@@ -725,7 +725,7 @@
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->ErrorCallback(hqspi);
@@ -1303,10 +1303,10 @@
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
+
/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
else
@@ -1396,10 +1396,10 @@
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
+
/* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
@@ -2229,7 +2229,7 @@
{
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Abort Complete callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->AbortCpltCallback(hqspi);
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rcc.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rcc.c
index a07680d..fc609de 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rcc.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rcc.c
@@ -203,37 +203,37 @@
CLEAR_REG(RCC->MCO2CFGR);
/* Reset MPU Clock Selection Register */
- MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), RCC_MPCKSELR_MPUSRC_0);
+ MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), 0U);
/* Reset AXI Sub-System Clock Selection Register */
- MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), RCC_ASSCKSELR_AXISSRC_0);
+ MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), 0U);
/* Reset MCU Sub-System Clock Selection Register */
- MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), RCC_MSSCKSELR_MCUSSRC_0);
+ MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), 0U);
/* Reset RCC MPU Clock Divider Register */
- MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_1);
+ MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_0);
/* Reset RCC AXI Clock Divider Register */
- MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), RCC_AXIDIVR_AXIDIV_0);
+ MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), 0U);
/* Reset RCC APB4 Clock Divider Register */
- MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), RCC_APB4DIVR_APB4DIV_0);
+ MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), 0U);
/* Reset RCC APB5 Clock Divider Register */
- MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), RCC_APB5DIVR_APB5DIV_0);
+ MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), 0U);
/* Reset RCC MCU Clock Divider Register */
- MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), RCC_MCUDIVR_MCUDIV_0);
+ MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), 0U);
/* Reset RCC APB1 Clock Divider Register */
- MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), RCC_APB1DIVR_APB1DIV_0);
+ MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), 0U);
/* Reset RCC APB2 Clock Divider Register */
- MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), RCC_APB2DIVR_APB2DIV_0);
+ MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), 0U);
/* Reset RCC APB3 Clock Divider Register */
- MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), RCC_APB3DIVR_APB3DIV_0);
+ MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), 0U);
/* Disable PLL1 outputs */
CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN | RCC_PLL1CR_DIVQEN |
@@ -324,13 +324,13 @@
CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
/* Reset PLL 1 and 2 Ref. Clock Selection Register */
- MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), RCC_RCK12SELR_PLL12SRC_0);
+ MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), 0U);
/* Reset RCC PLL 3 Ref. Clock Selection Register */
- MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), RCC_RCK3SELR_PLL3SRC_0);
+ MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), 0U);
/* Reset PLL4 Ref. Clock Selection Register */
- MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), RCC_RCK4SELR_PLL4SRC_0);
+ MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), 0U);
/* Reset RCC PLL1 Configuration Register 1 */
WRITE_REG(RCC->PLL1CFGR1, 0x00010031U);
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rtc_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rtc_ex.c
index 940fa3f..8a58080 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rtc_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_rtc_ex.c
@@ -2458,6 +2458,9 @@
* @}
*/
+/**
+ * @}
+ */
#endif /* HAL_RTC_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai.c
index 3c973b7..b0fae23 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai.c
@@ -140,12 +140,13 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+ Use functions HAL_SAI_RegisterCallback() to register a user callback.
- Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ [..]
+ Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@@ -153,13 +154,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
+ [..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@@ -169,23 +173,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
- By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ [..]
+ By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
- and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
- or @ref HAL_SAI_Init function.
+ using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+ or HAL_SAI_Init function.
+ [..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -236,7 +243,6 @@
/** @defgroup SAI_Private_Constants SAI Private Constants
* @{
*/
-#define SAI_FIFO_SIZE 8U
#define SAI_DEFAULT_TIMEOUT 4U
#define SAI_LONG_TIMEOUT 1000U
/**
@@ -250,7 +256,7 @@
* @{
*/
static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
-static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef const *const hsai, uint32_t mode);
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
@@ -413,13 +419,23 @@
{
assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
+
/* Check that SAI sub-block is SAI1 or SAI4 sub-block A, in master RX mode with free protocol */
+#if defined (SAI4)
if (((hsai->Instance != SAI1_Block_A) && (hsai->Instance != SAI4_Block_A)) ||
(hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
(hsai->Init.Protocol != SAI_FREE_PROTOCOL))
{
return HAL_ERROR;
}
+#else
+ if ((hsai->Instance != SAI1_Block_A) ||
+ (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
+ (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
+ {
+ return HAL_ERROR;
+ }
+#endif
}
/* Get the SAI base address according to the SAI handle */
@@ -431,14 +447,22 @@
{
SaiBaseAddress = SAI2;
}
+#if defined(SAI3)
else if ((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
{
SaiBaseAddress = SAI3;
}
- else
+#endif
+#if defined(SAI4)
+ else if ((hsai->Instance == SAI4_Block_A) || (hsai->Instance == SAI4_Block_B))
{
SaiBaseAddress = SAI4;
}
+#endif
+ else
+ {
+ return HAL_ERROR;
+ }
if (hsai->State == HAL_SAI_STATE_RESET)
{
@@ -465,10 +489,13 @@
#endif
}
- hsai->State = HAL_SAI_STATE_BUSY;
-
/* Disable the selected SAI peripheral */
- SAI_Disable(hsai);
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hsai->State = HAL_SAI_STATE_BUSY;
/* SAI Block Synchro Configuration -----------------------------------------*/
/* This setting must be done with both audio block (A & B) disabled */
@@ -503,6 +530,18 @@
syncen_bits = SAI_xCR1_SYNCEN_1;
tmpregisterGCR |= SAI_GCR_SYNCIN_0;
break;
+#if defined(SAI3)
+ case SAI_SYNCHRONOUS_EXT_SAI3 :
+ syncen_bits = SAI_xCR1_SYNCEN_1;
+ tmpregisterGCR |= SAI_GCR_SYNCIN_1;
+ break;
+#endif
+#if defined(SAI4)
+ case SAI_SYNCHRONOUS_EXT_SAI4 :
+ syncen_bits = SAI_xCR1_SYNCEN_1;
+ tmpregisterGCR |= (SAI_GCR_SYNCIN_1 | SAI_GCR_SYNCIN_0);
+ break;
+#endif
default:
syncen_bits = 0;
break;
@@ -525,14 +564,18 @@
{
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
}
+#if defined(SAI3)
if ((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
{
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI3);
}
+#endif
+#if defined(SAI4)
if ((hsai->Instance == SAI4_Block_A) || (hsai->Instance == SAI4_Block_B))
{
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4);
}
+#endif
/* Configure Master Clock Divider using the following formula :
- If NODIV = 1 :
@@ -542,36 +585,62 @@
if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
{
/* NODIV = 1 */
+ uint32_t tmpframelength;
+
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ /* For SPDIF protocol, frame length is set by hardware to 64 */
+ tmpframelength = 64U;
+ }
+ else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
+ {
+ /* For AC97 protocol, frame length is set by hardware to 256 */
+ tmpframelength = 256U;
+ }
+ else
+ {
+ /* For free protocol, frame length is set by user */
+ tmpframelength = hsai->FrameInit.FrameLength;
+ }
+
/* (freq x 10) to keep Significant digits */
- tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
+ tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
}
else
{
/* NODIV = 0 */
uint32_t tmposr;
- tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2 : 1;
+ tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
/* (freq x 10) to keep Significant digits */
- tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256);
+ tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
}
- hsai->Init.Mckdiv = tmpval / 10;
+ hsai->Init.Mckdiv = tmpval / 10U;
/* Round result to the nearest integer */
- if ((tmpval % 10) > 8)
+ if ((tmpval % 10U) > 8U)
{
- hsai->Init.Mckdiv += 1;
+ hsai->Init.Mckdiv += 1U;
+ }
+
+ /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
}
}
+ /* Check the SAI Block master clock divider parameter */
+ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
/* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
{
/* Transmit */
- ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
}
else
{
/* Receive */
- ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
}
/* SAI Block Configuration -------------------------------------------------*/
@@ -596,11 +665,11 @@
/* SAI Frame Configuration -----------------------------------------*/
hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
- hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1) |
+ hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
hsai->FrameInit.FSOffset |
hsai->FrameInit.FSDefinition |
hsai->FrameInit.FSPolarity |
- ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
+ ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
/* SAI Block_x SLOT Configuration ------------------------------------------*/
/* This register has no meaning in AC 97 and SPDIF audio protocol */
@@ -608,10 +677,14 @@
SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
- (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8);
+ (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8);
/* SAI PDM Configuration ---------------------------------------------------*/
+#if defined(SAI4)
if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI4_Block_A))
+#else
+ if (hsai->Instance == SAI1_Block_A)
+#endif
{
/* Disable PDM interface */
SaiBaseAddress->PDMCR &= ~(SAI_PDMCR_PDMEN);
@@ -619,7 +692,7 @@
{
/* Configure and enable PDM interface */
SaiBaseAddress->PDMCR = (hsai->Init.PdmInit.ClockEnable |
- ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_Pos));
+ ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
SaiBaseAddress->PDMCR |= SAI_PDMCR_PDMEN;
}
}
@@ -659,16 +732,33 @@
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable the SAI */
- SAI_Disable(hsai);
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ /* Reset SAI state to ready */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
/* Disable SAI PDM interface */
+#if defined(SAI4)
if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI4_Block_A))
+#else
+ if (hsai->Instance == SAI1_Block_A)
+#endif
{
/* Get the SAI base address according to the SAI handle */
+#if defined(SAI4)
SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : SAI4;
+#else
+ SaiBaseAddress = SAI1;
+#endif
/* Reset PDM delays */
SaiBaseAddress->PDMDLY = 0U;
@@ -966,8 +1056,9 @@
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
+ uint32_t temp;
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -984,7 +1075,7 @@
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
/* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* fill the fifo with data before to enabled the SAI */
SAI_FillFifo(hsai);
@@ -992,24 +1083,35 @@
__HAL_SAI_ENABLE(hsai);
}
- while (hsai->XferCount > 0)
+ while (hsai->XferCount > 0U)
{
/* Write data if the FIFO is not full */
if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
{
if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
{
- hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
}
else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
{
- hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
- hsai->pBuffPtr += 2;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
}
else
{
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr += 4;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
}
hsai->XferCount--;
}
@@ -1025,7 +1127,8 @@
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ /* No need to check return value because state update, unlock and error return will be performed later */
+ (void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1066,8 +1169,9 @@
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
+ uint32_t temp;
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1084,30 +1188,41 @@
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
/* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
/* Receive data */
- while (hsai->XferCount > 0)
+ while (hsai->XferCount > 0U)
{
if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
{
if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
{
- (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+ hsai->pBuffPtr++;
}
else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
{
- *((uint16_t *)hsai->pBuffPtr) = hsai->Instance->DR;
- hsai->pBuffPtr += 2;
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
}
else
{
- *((uint32_t *)hsai->pBuffPtr) = hsai->Instance->DR;
- hsai->pBuffPtr += 4;
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+ hsai->pBuffPtr++;
}
hsai->XferCount--;
}
@@ -1123,7 +1238,8 @@
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ /* No need to check return value because state update, unlock and error return will be performed later */
+ (void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1162,7 +1278,7 @@
*/
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1198,7 +1314,7 @@
__HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
/* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -1224,7 +1340,7 @@
*/
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1257,7 +1373,7 @@
__HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
/* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -1309,7 +1425,7 @@
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
/* If the SAI peripheral is still not enabled, enable it */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -1338,7 +1454,7 @@
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
/* Abort the SAI Tx DMA Stream */
- if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
+ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
{
if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
{
@@ -1352,7 +1468,7 @@
}
/* Abort the SAI Rx DMA Stream */
- if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
+ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
{
if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
{
@@ -1366,7 +1482,10 @@
}
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1400,7 +1519,7 @@
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
/* Abort the SAI Tx DMA Stream */
- if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
+ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
{
if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
{
@@ -1414,7 +1533,7 @@
}
/* Abort the SAI Rx DMA Stream */
- if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
+ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
{
if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
{
@@ -1433,7 +1552,10 @@
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1459,7 +1581,7 @@
{
uint32_t tickstart = HAL_GetTick();
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1517,7 +1639,7 @@
}
/* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -1545,7 +1667,7 @@
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
- if ((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1580,19 +1702,19 @@
return HAL_ERROR;
}
- /* Check if the SAI is already enabled */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
/* Enable the interrupts for error handling */
__HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
/* Enable SAI Rx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+ /* Check if the SAI is already enabled */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hsai);
@@ -1618,7 +1740,7 @@
if (hsai->State != HAL_SAI_STATE_RESET)
{
CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
return HAL_OK;
}
return HAL_ERROR;
@@ -1699,7 +1821,7 @@
uint32_t cr1config = hsai->Instance->CR1;
uint32_t tmperror;
- /* SAI Fifo request interrupt occured ------------------------------------*/
+ /* SAI Fifo request interrupt occurred -----------------------------------*/
if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
{
hsai->InterruptServiceRoutine(hsai);
@@ -1735,6 +1857,9 @@
/* SAI AFSDET interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
{
+ /* Clear the SAI AFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
@@ -1748,7 +1873,18 @@
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
if (hsai->hdmarx != NULL)
{
@@ -1756,13 +1892,25 @@
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
}
else
{
/* Abort SAI */
- HAL_SAI_Abort(hsai);
+ /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+ (void) HAL_SAI_Abort(hsai);
/* Set error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
@@ -1775,6 +1923,9 @@
/* SAI LFSDET interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
{
+ /* Clear the SAI LFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
@@ -1788,7 +1939,18 @@
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
if (hsai->hdmarx != NULL)
{
@@ -1796,13 +1958,25 @@
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
}
else
{
/* Abort SAI */
- HAL_SAI_Abort(hsai);
+ /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+ (void) HAL_SAI_Abort(hsai);
/* Set error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
@@ -1815,6 +1989,9 @@
/* SAI WCKCFG interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
{
+ /* Clear the SAI WCKCFG flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
@@ -1828,7 +2005,18 @@
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
+ if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
if (hsai->hdmarx != NULL)
{
@@ -1836,7 +2024,18 @@
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
+ if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+ {
+ /* Update SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
+ HAL_SAI_ErrorCallback(hsai);
+#endif
+ }
}
}
else
@@ -2048,25 +2247,21 @@
hsai->SlotInit.SlotNumber = nbslot;
/* in IS2 the number of slot must be even */
- if ((nbslot & 0x1) != 0)
+ if ((nbslot & 0x1U) != 0U)
{
return HAL_ERROR;
}
- switch (protocol)
+ if (protocol == SAI_I2S_STANDARD)
{
- case SAI_I2S_STANDARD :
- hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
- hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
- break;
- case SAI_I2S_MSBJUSTIFIED :
- case SAI_I2S_LSBJUSTIFIED :
- hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
- hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
- break;
- default :
- status = HAL_ERROR;
- break;
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ }
+ else
+ {
+ /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
}
/* Frame definition */
@@ -2074,26 +2269,26 @@
{
case SAI_PROTOCOL_DATASIZE_16BIT:
hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 32 * (nbslot / 2);
- hsai->FrameInit.ActiveFrameLength = 16 * (nbslot / 2);
+ hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
break;
case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 64 * (nbslot / 2);
- hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2);
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
case SAI_PROTOCOL_DATASIZE_24BIT:
hsai->Init.DataSize = SAI_DATASIZE_24;
- hsai->FrameInit.FrameLength = 64 * (nbslot / 2);
- hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2);
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
case SAI_PROTOCOL_DATASIZE_32BIT:
hsai->Init.DataSize = SAI_DATASIZE_32;
- hsai->FrameInit.FrameLength = 64 * (nbslot / 2);
- hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2);
+ hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+ hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
default :
@@ -2148,39 +2343,36 @@
hsai->SlotInit.SlotNumber = nbslot;
hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
- switch (protocol)
+ if (protocol == SAI_PCM_SHORT)
{
- case SAI_PCM_SHORT :
- hsai->FrameInit.ActiveFrameLength = 1;
- break;
- case SAI_PCM_LONG :
- hsai->FrameInit.ActiveFrameLength = 13;
- break;
- default :
- status = HAL_ERROR;
- break;
+ hsai->FrameInit.ActiveFrameLength = 1;
+ }
+ else
+ {
+ /* SAI_PCM_LONG */
+ hsai->FrameInit.ActiveFrameLength = 13;
}
switch (datasize)
{
case SAI_PROTOCOL_DATASIZE_16BIT:
hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 16 * nbslot;
+ hsai->FrameInit.FrameLength = 16U * nbslot;
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
break;
case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
case SAI_PROTOCOL_DATASIZE_24BIT :
hsai->Init.DataSize = SAI_DATASIZE_24;
- hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
case SAI_PROTOCOL_DATASIZE_32BIT:
hsai->Init.DataSize = SAI_DATASIZE_32;
- hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
break;
default :
@@ -2199,22 +2391,35 @@
*/
static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
{
+ uint32_t temp;
+
/* fill the fifo with data before to enabled the SAI */
- while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
+ while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
{
if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
{
- hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
}
else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
{
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr += 2;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
}
else
{
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr += 4;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
}
hsai->XferCount--;
}
@@ -2227,7 +2432,7 @@
* @param mode SAI_MODE_DMA or SAI_MODE_IT
* @retval the list of the IT flag to enable
*/
-static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef const *const hsai, uint32_t mode)
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
{
uint32_t tmpIT = SAI_IT_OVRUDR;
@@ -2262,7 +2467,7 @@
*/
static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
{
- register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7 / 1000);
+ register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Disable the SAI instance */
@@ -2271,15 +2476,16 @@
do
{
/* Check for the Timeout */
- if (count-- == 0)
+ if (count == 0U)
{
/* Update error code */
hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
status = HAL_TIMEOUT;
break;
}
+ count--;
}
- while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
+ while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
return status;
}
@@ -2292,7 +2498,7 @@
*/
static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
{
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Handle the end of the transmission */
/* Disable FREQ and OVRUDR interrupts */
@@ -2307,7 +2513,8 @@
else
{
/* Write data on DR register */
- hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->Instance->DR = *hsai->pBuffPtr;
+ hsai->pBuffPtr++;
hsai->XferCount--;
}
}
@@ -2320,7 +2527,7 @@
*/
static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
{
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Handle the end of the transmission */
/* Disable FREQ and OVRUDR interrupts */
@@ -2335,8 +2542,12 @@
else
{
/* Write data on DR register */
- hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
- hsai->pBuffPtr += 2;
+ uint32_t temp;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
hsai->XferCount--;
}
}
@@ -2349,7 +2560,7 @@
*/
static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
{
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Handle the end of the transmission */
/* Disable FREQ and OVRUDR interrupts */
@@ -2364,8 +2575,16 @@
else
{
/* Write data on DR register */
- hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
- hsai->pBuffPtr += 4;
+ uint32_t temp;
+ temp = (uint32_t)(*hsai->pBuffPtr);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+ hsai->pBuffPtr++;
+ temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+ hsai->pBuffPtr++;
+ hsai->Instance->DR = temp;
hsai->XferCount--;
}
}
@@ -2379,11 +2598,12 @@
static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
{
/* Receive data */
- (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+ hsai->pBuffPtr++;
hsai->XferCount--;
/* Check end of the transfer */
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Disable TXE and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
@@ -2408,13 +2628,18 @@
*/
static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
{
+ uint32_t temp;
+
/* Receive data */
- *(uint16_t *)hsai->pBuffPtr = hsai->Instance->DR;
- hsai->pBuffPtr += 2;
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
hsai->XferCount--;
/* Check end of the transfer */
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Disable TXE and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
@@ -2439,13 +2664,22 @@
*/
static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
{
+ uint32_t temp;
+
/* Receive data */
- *(uint32_t *)hsai->pBuffPtr = hsai->Instance->DR;
- hsai->pBuffPtr += 4;
+ temp = hsai->Instance->DR;
+ *hsai->pBuffPtr = (uint8_t)temp;
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+ hsai->pBuffPtr++;
+ *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+ hsai->pBuffPtr++;
hsai->XferCount--;
/* Check end of the transfer */
- if (hsai->XferCount == 0)
+ if (hsai->XferCount == 0U)
{
/* Disable TXE and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
@@ -2573,7 +2807,8 @@
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+ (void) SAI_Disable(hsai);
/* Set the SAI state ready to be able to start again the process */
hsai->State = HAL_SAI_STATE_READY;
@@ -2610,7 +2845,8 @@
if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
{
/* Disable SAI peripheral */
- SAI_Disable(hsai);
+ /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+ (void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai_ex.c
index 5836c84..237abe7 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sai_ex.c
@@ -37,9 +37,15 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
+ * @{
+ */
#define SAI_PDM_DELAY_MASK 0x77U
#define SAI_PDM_DELAY_OFFSET 8U
#define SAI_PDM_RIGHT_DELAY_OFFSET 4U
+/**
+ * @}
+ */
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -71,12 +77,18 @@
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t offset;
SAI_TypeDef *SaiBaseAddress;
+#if defined(SAI4)
/* Get the SAI base address according to the SAI handle */
SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : \
((hsai->Instance == SAI4_Block_A) ? SAI4 : \
NULL);
+#else
+ /* Get the SAI base address according to the SAI handle */
+ SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : NULL;
+#endif
/* Check that SAI sub-block is SAI sub-block A */
if (SaiBaseAddress == NULL)
@@ -90,15 +102,17 @@
assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
- /* Check SAI state */
- if (hsai->State != HAL_SAI_STATE_RESET)
+ /* Compute offset on PDMDLY register according mic pair number */
+ offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
+
+ /* Check SAI state and offset */
+ if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
{
/* Reset current delays for specified microphone */
- SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
+ SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
/* Apply new microphone delays */
- SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \
- (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
+ SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
}
else
{
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd.c
index 59044a2..055cb77 100755
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd.c
@@ -3,129 +3,129 @@
* @file stm32mp1xx_hal_sd.c
* @author MCD Application Team
* @brief SD card HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_SD_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with SD and uSD cards devices.
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with SD and uSD cards devices.
It is used as follows:
-
+
(#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for SD card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
(##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.
-
- (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
*** SD Card Initialization and configuration ***
- ================================================
+ ================================================
[..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- the SD Card and put it into StandBy State (Ready for data transfer).
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ the SD Card and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
-
- (#) Apply the SD Card initialization process at 400KHz and check the SD Card
- type (Standard Capacity or High Capacity). You can change or adapt this
- frequency by adjusting the "ClockDiv" field.
- The SD Card frequency (SDMMC_CK) is computed as follows:
-
- SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
-
- In initialization mode and according to the SD Card standard,
- make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-
- (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
- structure. This structure provide also ready computed SD Card capacity
- and Block size.
-
- -@- These information are stored in SD handle structure in case of future use.
-
- (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+ type (Standard Capacity or High Capacity). You can change or adapt this
frequency by adjusting the "ClockDiv" field.
- In transfer mode and according to the SD Card standard, make sure that the
+ The SD Card frequency (SDMMC_CK) is computed as follows:
+
+ SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+ In initialization mode and according to the SD Card standard,
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+ (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
+ structure. This structure provide also ready computed SD Card capacity
+ and Block size.
+
+ -@- These information are stored in SD handle structure in case of future use.
+
+ (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ In transfer mode and according to the SD Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
-
+
(#) Select the corresponding SD Card according to the address read with the step 2.
-
+
(#) Configure the SD Card in wide bus mode: 4-bits data.
-
+
*** SD Card Read operation ***
==============================
- [..]
- (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function support only 512-bytes block length (the block size should be
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
+ This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
-
+
*** SD Card Write operation ***
- ===============================
- [..]
- (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function support only 512-bytes block length (the block size should be
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
+ This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
-
+
*** SD card status ***
- ======================
+ ======================
[..]
- (+) At any time, you can check the SD Card status and get the SD card state
- by using the HAL_SD_GetStatusInfo() function. This function checks first if the
- SD card is still connected and then get the internal SD Card transfer state.
+ (+) At any time, you can check the SD Card status and get the SD card state
+ by using the HAL_SD_GetStatusInfo() function. This function checks first if the
+ SD card is still connected and then get the internal SD Card transfer state.
*** SD HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SD HAL driver.
-
+
(+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
(+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
(+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
(+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
-
- (@) You can refer to the SD HAL driver header file for more useful macros
-
+
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
*** Callback registration ***
=============================================
[..]
@@ -146,7 +146,7 @@
(+) MspDeInitCallback : SD MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- For specific callbacks TransceiverCallback use dedicated register callbacks:
+ For specific callbacks TransceiverCallback use dedicated register callbacks:
respectively @ref HAL_SD_RegisterTransceiverCallback().
Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
@@ -162,13 +162,13 @@
(+) MspInitCallback : SD MspInit.
(+) MspDeInitCallback : SD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+ For specific callbacks TransceiverCallback use dedicated unregister callbacks:
respectively @ref HAL_SD_UnRegisterTransceiverCallback().
By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -178,11 +178,11 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
or @ref HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
@@ -198,7 +198,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -207,7 +207,7 @@
* @{
*/
-/** @addtogroup SD
+/** @addtogroup SD
* @{
*/
@@ -222,7 +222,7 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -254,28 +254,28 @@
*/
/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to initialize/de-initialize the SD
card device to be ready for use.
-
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the SD according to the specified parameters in the
+ * @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd: Pointer to the SD handle
+ * @param hsd: Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
-{
+{
HAL_SD_CardStatusTypedef CardStatus;
uint32_t speedgrade, unitsize;
uint32_t tickstart;
@@ -412,7 +412,7 @@
/* Initialize the error code */
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
@@ -425,7 +425,7 @@
/**
* @brief Initializes the SD Card.
* @param hsd: Pointer to SD handle
- * @note This function initializes the SD card. It could be used when a card
+ * @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
@@ -434,19 +434,19 @@
uint32_t errorstate;
HAL_StatusTypeDef status;
SD_InitTypeDef Init;
-
+
/* Default SDMMC peripheral configuration for SD card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
-
+
#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
- /* Set Transceiver polarity */
+ /* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
-
+
/* Initialize SDMMC peripheral interface with default configuration */
status = SDMMC_Init(hsd->Instance, Init);
if(status != HAL_OK)
@@ -494,7 +494,7 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
@@ -511,11 +511,11 @@
#else
HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
#endif
-#endif /* USE_SD_TRANSCEIVER */
-
- /* Set SD power state to off */
+#endif /* USE_SD_TRANSCEIVER */
+
+ /* Set SD power state to off */
SD_PowerOFF(hsd);
-
+
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
if(hsd->MspDeInitCallback == NULL)
{
@@ -528,10 +528,10 @@
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
#endif
-
+
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
-
+
return HAL_OK;
}
@@ -571,14 +571,14 @@
*/
/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
+ * @brief Data transfer functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to manage the data
+ This subsection provides a set of functions allowing to manage the data
transfer from/to SD card.
@endverbatim
@@ -586,14 +586,14 @@
*/
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @param hsd: Pointer to SD handle
* @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of SD blocks to read
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of SD blocks to read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
@@ -605,33 +605,33 @@
uint32_t count, data;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
+
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -642,7 +642,7 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@@ -652,19 +652,19 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
+
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
+
+ /* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
+
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
@@ -676,7 +676,7 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Poll on SDMMC flags */
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
@@ -696,7 +696,7 @@
tempbuff++;
}
}
-
+
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
@@ -707,10 +707,10 @@
}
}
__SDMMC_CMDTRANS_DISABLE( hsd->Instance);
-
+
/* Send stop transmission command in case of multiblock read */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -725,7 +725,7 @@
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
@@ -755,12 +755,12 @@
{
/* Nothing to do */
}
-
+
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -772,13 +772,13 @@
/**
* @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
+ * transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @param hsd: Pointer to SD handle
* @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of SD blocks to write
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of SD blocks to write
* @param Timeout: Specify timeout value
* @retval HAL status
*/
@@ -790,7 +790,7 @@
uint32_t count, data;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -800,35 +800,35 @@
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -842,26 +842,26 @@
if(NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
+
+ /* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
+
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write block(s) in polling mode */
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
@@ -881,11 +881,11 @@
(void)SDMMC_WriteFIFO(hsd->Instance, &data);
}
}
-
+
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_TIMEOUT;
@@ -895,7 +895,7 @@
/* Send stop transmission command in case of multiblock write */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -903,14 +903,14 @@
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
@@ -940,12 +940,12 @@
{
/* Nothing to do */
}
-
+
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -956,15 +956,15 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Rx
+ * @note You could also check the IT transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
@@ -973,44 +973,44 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
@@ -1025,26 +1025,26 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
+
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
@@ -1059,15 +1059,15 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Tx
- * interrupt event.
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
* @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
+ * @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
@@ -1076,51 +1076,51 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
/* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
-
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -1135,26 +1135,26 @@
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
- /* Write Multi Block command */
+
+ /* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Write Single Block command */
+
+ /* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -1164,15 +1164,15 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Rx
+ * @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer SD handle
+ * @param hsd: Pointer SD handle
* @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
@@ -1181,48 +1181,48 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
- /* Configure the SD DPSM (Data Path State Machine) */
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -1235,21 +1235,21 @@
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
/* Read Blocks in DMA mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
@@ -1262,7 +1262,7 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -1272,15 +1272,15 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Tx
+ * @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
* @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
+ * @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
@@ -1289,28 +1289,28 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
@@ -1319,12 +1319,12 @@
add *= 512U;
}
- /* Set Block Size for Card */
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
@@ -1339,32 +1339,32 @@
(void)SDMMC_ConfigData(hsd->Instance, &config);
/* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
-
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
+
+ /* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
@@ -1383,7 +1383,7 @@
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @param BlockStartAdd: Start Block address
* @param BlockEndAdd: End Block address
* @retval HAL status
@@ -1393,25 +1393,25 @@
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
if(end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Check if the card command class supports erase command */
if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
@@ -1421,23 +1421,23 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Get start and end block for high capacity cards */
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
start_add *= 512U;
end_add *= 512U;
}
-
+
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
if(hsd->SdCard.CardType != CARD_SECURED)
{
@@ -1446,37 +1446,37 @@
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -1491,22 +1491,22 @@
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
+{
uint32_t errorstate;
uint32_t context = hsd->Context;
-
+
/* Check for SDMMC interrupt flags */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
{
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
SDMMC_IT_RXFIFOHF);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
__SDMMC_CMDTRANS_DISABLE( hsd->Instance);
-
+
if((context & SD_CONTEXT_IT) != 0U)
{
if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
@@ -1522,10 +1522,10 @@
#endif
}
}
-
+
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
hsd->State = HAL_SD_STATE_READY;
if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
@@ -1539,7 +1539,7 @@
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
#endif
}
@@ -1570,7 +1570,7 @@
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
#endif
}
@@ -1588,23 +1588,23 @@
/* Nothing to do */
}
}
-
+
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
{
SD_Write_IT(hsd);
}
-
+
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
{
SD_Read_IT(hsd);
}
-
+
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
{
/* Set Error code */
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
{
@@ -1616,16 +1616,16 @@
}
if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
}
-
+
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
__SDMMC_CMDTRANS_DISABLE( hsd->Instance);
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
@@ -1650,7 +1650,7 @@
/* Disable Internal DMA */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
+
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -1779,7 +1779,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
@@ -1791,10 +1791,10 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_AbortCallback can be implemented in the user file
- */
+ */
}
#if (USE_SD_TRANSCEIVER != 0U)
@@ -1805,7 +1805,7 @@
*/
__weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
{
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_EnableTransceiver could be implemented in the user file
*/
@@ -1815,7 +1815,7 @@
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SD Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1827,8 +1827,8 @@
* @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID
* @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
* @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
@@ -1845,7 +1845,7 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
@@ -1882,7 +1882,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1900,7 +1900,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1909,7 +1909,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1921,7 +1921,7 @@
/**
* @brief Unregister a User SD Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1933,8 +1933,8 @@
* @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID
* @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID
* @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
@@ -1943,7 +1943,7 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
@@ -1980,7 +1980,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1998,7 +1998,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -2007,7 +2007,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -2020,7 +2020,7 @@
#if (USE_SD_TRANSCEIVER != 0U)
/**
* @brief Register a User SD Transceiver Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hsd : SD handle
* @param pCallback : pointer to the Callback function
* @retval status
@@ -2038,7 +2038,7 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = pCallback;
@@ -2046,7 +2046,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -2058,7 +2058,7 @@
/**
* @brief Unregister a User SD Transceiver Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
* @param hsd : SD handle
* @retval status
*/
@@ -2068,7 +2068,7 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
@@ -2076,7 +2076,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -2093,14 +2093,14 @@
*/
/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the SD card
+ This subsection provides a set of functions allowing to control the SD card
operations and get the related information
@endverbatim
@@ -2111,32 +2111,32 @@
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CIDTypedef structure that
- * contains all CID register parameters
+ * @param pCID: Pointer to a HAL_SD_CIDTypedef structure that
+ * contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
{
pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
-
+
pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
-
+
pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
-
+
pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
-
+
pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
-
+
pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
-
+
pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
-
+
pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
pCID->Reserved2 = 1U;
-
+
return HAL_OK;
}
@@ -2144,8 +2144,8 @@
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that
- * contains all CSD register parameters
+ * @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that
+ * contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
@@ -2155,17 +2155,17 @@
pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
-
+
pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
-
+
pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
-
+
pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
-
+
pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
-
+
pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
-
+
pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
@@ -2175,26 +2175,26 @@
pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
pCSD->Reserved2 = 0U; /*!< Reserved */
-
+
if(hsd->SdCard.CardType == CARD_SDSC)
{
pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
-
+
pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
-
+
pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
-
+
hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
hsd->SdCard.LogBlockSize = 512U;
}
else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
@@ -2210,18 +2210,18 @@
else
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
-
+
pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
-
+
pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
@@ -2229,13 +2229,13 @@
pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
-
+
pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
pCSD->Reserved3 = 0;
pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
-
+
pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
@@ -2247,31 +2247,31 @@
pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
-
+
pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
pCSD->Reserved4 = 1;
-
+
return HAL_OK;
}
/**
* @brief Gets the SD status info.
- * @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
{
uint32_t sd_status[16];
uint32_t errorstate;
-
+
errorstate = SD_SendSDStatus(hsd, sd_status);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
@@ -2279,39 +2279,39 @@
else
{
pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
-
+
pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
-
+
pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
-
- pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
+
+ pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
-
+
pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
-
+
pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
-
+
pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
-
+
pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
-
+
pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
}
-
+
return HAL_OK;
}
/**
* @brief Gets the SD card info.
- * @param hsd: Pointer to SD handle
- * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
@@ -2324,15 +2324,15 @@
pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
+
return HAL_OK;
}
/**
- * @brief Enables wide bus operation for the requested card if supported by
+ * @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd: Pointer to SD handle
- * @param WideMode: Specifies the SD card wide bus mode
+ * @param hsd: Pointer to SD handle
+ * @param WideMode: Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
@@ -2343,14 +2343,14 @@
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
-
+
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
-
+
/* Change State */
hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
if(WideMode == SDMMC_BUS_WIDE_8B)
{
@@ -2359,13 +2359,13 @@
else if(WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else if(WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else
@@ -2373,7 +2373,7 @@
/* WideMode is not a valid argument*/
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
}
- }
+ }
else
{
/* MMC Card does not support this feature */
@@ -2394,7 +2394,7 @@
Init.ClockPowerSave = hsd->Init.ClockPowerSave;
Init.BusWide = WideMode;
Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-
+
/* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
{
@@ -2435,7 +2435,7 @@
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0;
-
+
errorstate = SD_SendStatus(hsd, &resp1);
if(errorstate != HAL_SD_ERROR_NONE)
{
@@ -2443,7 +2443,7 @@
}
cardstate = ((resp1 >> 9U) & 0x0FU);
-
+
return (HAL_SD_CardStateTypedef)cardstate;
}
@@ -2456,17 +2456,17 @@
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypedef CardState;
-
+
/* DIsable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
+
hsd->State = HAL_SD_STATE_READY;
/* Initialize the SD operation */
@@ -2493,11 +2493,11 @@
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypedef CardState;
-
+
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
+
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@@ -2506,12 +2506,12 @@
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
-
+
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
-
+
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
@@ -2524,7 +2524,7 @@
HAL_SD_AbortCallback(hsd);
#endif
}
-
+
return HAL_OK;
}
@@ -2535,7 +2535,7 @@
/**
* @}
*/
-
+
/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
@@ -2552,15 +2552,15 @@
HAL_SD_CardCSDTypedef CSD;
uint32_t errorstate;
uint16_t sd_rca = 1;
-
+
/* Check the power State */
- if(SDMMC_GetPowerState(hsd->Instance) == 0U)
+ if(SDMMC_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
@@ -2578,7 +2578,7 @@
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
@@ -2588,11 +2588,11 @@
return errorstate;
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
-
+
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2608,10 +2608,10 @@
hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
}
}
-
+
/* Get the Card Class */
hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
-
+
/* Get CSD parameters */
if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
{
@@ -2624,7 +2624,7 @@
{
return errorstate;
}
-
+
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
}
@@ -2644,14 +2644,14 @@
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t tickstart = HAL_GetTick();
#endif /* USE_SD_TRANSCEIVER */
-
+
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2681,7 +2681,7 @@
{
return errorstate;
}
-
+
/* Send CMD41 */
errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2702,7 +2702,7 @@
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
-
+
if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
@@ -2710,7 +2710,7 @@
if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
-
+
/* Start switching procedue */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
@@ -2747,7 +2747,7 @@
#else
HAL_SD_DriveTransceiver_1_8V_Callback(SET);
#endif
-
+
/* Switch ready */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
@@ -2759,10 +2759,10 @@
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
/* Clear VSWEND Flag */
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
-
+
/* Check BusyD0 status */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
@@ -2770,14 +2770,14 @@
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
/* Switch to 1.8V OK */
-
+
/* Disable VSWITCH FLAG from SDMMC IP */
hsd->Instance->POWER = 0x13U;
/* Clean Status flags */
hsd->Instance->ICR = 0xFFFFFFFFU;
}
-
+
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
}
#endif /* USE_SD_TRANSCEIVER */
@@ -2801,7 +2801,7 @@
/**
* @brief Send Status info command.
* @param hsd: pointer to SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
@@ -2812,13 +2812,13 @@
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t *pData = pSDstatus;
-
+
/* Check SD response */
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2826,7 +2826,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2834,8 +2834,8 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 64;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
@@ -2843,7 +2843,7 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
-
+
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2851,7 +2851,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Get status data */
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
@@ -2863,13 +2863,13 @@
pData++;
}
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
@@ -2891,45 +2891,45 @@
{
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
/* Clear all the static status flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Returns the current card's status.
* @param hsd: Pointer to SD handle
- * @param pCardStatus: pointer to the buffer that will contain the SD card
- * status (Card Status register)
+ * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * status (Card Status register)
* @retval error state
*/
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
uint32_t errorstate;
-
+
if(pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
-
+
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Get SD card status */
*pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
+
return HAL_SD_ERROR_NONE;
}
@@ -2942,19 +2942,19 @@
{
uint32_t scr[2] = {0, 0};
uint32_t errorstate;
-
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports wide bus operation */
if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
@@ -2964,7 +2964,7 @@
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2989,19 +2989,19 @@
{
uint32_t scr[2] = {0, 0};
uint32_t errorstate;
-
+
if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports 1 bit mode operation */
if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
@@ -3011,14 +3011,14 @@
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
return HAL_SD_ERROR_NONE;
}
else
@@ -3026,12 +3026,12 @@
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
-
-
+
+
/**
* @brief Finds the SD card SCR register value.
* @param hsd: Pointer to SD handle
- * @param pSCR: pointer to the buffer that will contain the SCR value
+ * @param pSCR: pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
@@ -3042,7 +3042,7 @@
uint32_t index = 0;
uint32_t tempscr[2] = {0, 0};
uint32_t *scr = pSCR;
-
+
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -3064,14 +3064,14 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
-
+
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
{
if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
@@ -3081,29 +3081,29 @@
index++;
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
+
return HAL_SD_ERROR_DATA_TIMEOUT;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
+
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
+
return HAL_SD_ERROR_RX_OVERRUN;
}
else
@@ -3117,7 +3117,7 @@
scr++;
*scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
-
+
}
return HAL_SD_ERROR_NONE;
@@ -3135,7 +3135,7 @@
uint8_t* tmp;
tmp = hsd->pRxBuffPtr;
-
+
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
@@ -3149,7 +3149,7 @@
*tmp = (uint8_t)((data >> 24U) & 0xFFU);
tmp++;
}
-
+
hsd->pRxBuffPtr = tmp;
}
@@ -3163,9 +3163,9 @@
{
uint32_t count, data;
uint8_t* tmp;
-
+
tmp = hsd->pTxBuffPtr;
-
+
/* Write data to SDMMC Tx FIFO */
for(count = 0U; count < 8U; count++)
{
@@ -3179,7 +3179,7 @@
tmp++;
(void)SDMMC_WriteFIFO(hsd->Instance, &data);
}
-
+
hsd->pTxBuffPtr = tmp;
}
@@ -3236,7 +3236,7 @@
{
SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
}
- loop += 8U;
+ loop ++;
}
if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
@@ -3294,7 +3294,7 @@
/**
* @brief Switches the SD card to High Speed mode.
* This API must be used after "Transfer State"
- * @note This operation should be followed by the configuration
+ * @note This operation should be followed by the configuration
* of PLL to have SDMMCCK clock between 50 and 120 MHz
* @param hsd: SD handle
* @retval SD Card error state
@@ -3306,11 +3306,11 @@
uint32_t SD_hs[16] = {0};
uint32_t count, loop = 0 ;
uint32_t Timeout = HAL_GetTick();
-
+
if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
/* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
@@ -3318,12 +3318,12 @@
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
-
+
if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
sdmmc_datainitstructure.DataLength = 64;
@@ -3342,7 +3342,7 @@
{
return errorstate;
}
-
+
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
@@ -3351,9 +3351,9 @@
{
SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
}
- loop += 8U;
+ loop ++;
}
-
+
if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
@@ -3365,25 +3365,25 @@
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
+
errorstate = 0;
-
+
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
+
errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
-
+
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
+
errorstate = SDMMC_ERROR_RX_OVERRUN;
-
+
return errorstate;
}
else
@@ -3393,7 +3393,7 @@
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
+
/* Test if the switch mode HS is ok */
if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
{
@@ -3431,7 +3431,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
*/
@@ -3446,7 +3446,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
*/
@@ -3461,7 +3461,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
*/
@@ -3476,7 +3476,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
*/
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd_ex.c
index 21462d6..9fed51a 100755
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_sd_ex.c
@@ -3,10 +3,10 @@
* @file stm32mp1xx_hal_sd_ex.c
* @author MCD Application Team
* @brief SD card Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,7 +16,7 @@
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
-
+
@endverbatim
******************************************************************************
* @attention
@@ -30,7 +30,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -58,16 +58,16 @@
*/
/** @addtogroup SDEx_Exported_Functions_Group1
- * @brief Multibuffer functions
+ * @brief Multibuffer functions
*
-@verbatim
+@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
- [..]
- This section provides functions allowing to configure the multibuffer mode and start read and write
+ [..]
+ This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for SD HAL driver.
-
+
@endverbatim
* @{
*/
@@ -87,7 +87,7 @@
hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
-
+
return HAL_OK;
}
else
@@ -95,12 +95,12 @@
return HAL_BUSY;
}
}
-
+
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd: SD handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -110,7 +110,7 @@
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
@@ -118,7 +118,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
@@ -126,12 +126,12 @@
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
/* Clear old Flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
+
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;
@@ -139,8 +139,8 @@
{
add *= 512U;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -148,18 +148,18 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
-
+
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
-
+
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
-
+
/* Read Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -168,21 +168,21 @@
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
{
return HAL_BUSY;
}
-
+
}
/**
* @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd: SD handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -192,7 +192,7 @@
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
@@ -200,7 +200,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
@@ -208,20 +208,20 @@
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
-
+
hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
+
hsd->State = HAL_SD_STATE_BUSY;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -229,16 +229,16 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
-
+
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
+
+ hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
-
+
/* Write Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -247,24 +247,24 @@
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
{
return HAL_BUSY;
- }
+ }
}
-
+
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hsd: pointer to a SD_HandleTypeDef structure.
- * @param Buffer: the buffer to be changed, This parameter can be one of
+ * @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
- * BUFFER1 and the BUFFER1 address can be changed only when the current
+ * BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
@@ -280,7 +280,7 @@
/* change the memory1 address */
hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
-
+
return HAL_OK;
}
@@ -292,7 +292,7 @@
/**
* @}
*/
-
+
#endif /* HAL_SD_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard.c
new file mode 100644
index 0000000..ff92fa4
--- /dev/null
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard.c
@@ -0,0 +1,3201 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard handle Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief HAL SMARTCARD module driver
+ * @{
+ */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
+ USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ The USART frame format is given in the following table:
+
+ Table 1. USART frame format.
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+ if (hsmartcard->MspInitCallback == NULL)
+ {
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsmartcard->MspInitCallback(hsmartcard);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+ }
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the SMARTCARD transmission completion indication */
+ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
+
+ /* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsmartcard->MspDeInitCallback == NULL)
+ {
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsmartcard->MspDeInitCallback(hsmartcard);
+#else
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
+
+ [..]
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ while (hsmartcard->TxXferCount > 0U)
+ {
+ hsmartcard->TxXferCount--;
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+ ptmpdata++;
+ }
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while (hsmartcard->RxXferCount > 0U)
+ {
+ hsmartcard->RxXferCount--;
+
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ ptmpdata++;
+ }
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_TDR register is empty, i.e one interrupt per data to transmit.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * TXFIFO threshold reached. In that case the interrupt rate depends on
+ * TXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->TxIsr function pointer according to
+ * the FIFO mode (data transmission processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+ hsmartcard->TxISR = NULL;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Configure Tx interrupt processing */
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the TX FIFO threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_RDR register can be read, i.e one interrupt per data to receive.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * RXFIFO threshold reached. In that case the interrupt rate depends on
+ * RXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->RxIsr function pointer according to
+ * the FIFO mode (data reception processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Configure Rx interrupt processing */
+ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
+ Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
+ Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3);
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
+ {
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)
+ || ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = hsmartcard->ErrorCode;
+ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
+ {
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (hsmartcard->TxISR != NULL)
+ {
+ hsmartcard->TxISR(hsmartcard);
+ }
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
+ }
+
+ /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ hsmartcard->TxFifoEmptyCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+
+ /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ hsmartcard->RxFifoFullCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Return SMARTCARD handle state */
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hsmartcard->gState;
+ temp2 = (uint32_t)hsmartcard->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle Error Code
+ */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg;
+ SMARTCARD_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ PLL3_ClocksTypeDef pll3_clocks;
+ PLL4_ClocksTypeDef pll4_clocks;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+ assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength));
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
+ /* Configure
+ * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
+ MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ tmpreg = 0U;
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK5:
+ pclk = HAL_RCC_GetPCLK5Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PLL3Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PLL4Q:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ tmpreg = (uint16_t)(((pll4_clocks.PLL4_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_CSI:
+ tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hsmartcard->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tickstart;
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD states */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ if (hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ if (hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear TxISR function pointer */
+ hsmartcard->TxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsmartcard->TxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = hsmartcard->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard_ex.c
new file mode 100644
index 0000000..ad8246d
--- /dev/null
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_smartcard_ex.c
@@ -0,0 +1,496 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+ * @brief SMARTCARD Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
+}
+
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/** @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/** @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+ (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD RX Fifo full callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD TX Fifo empty callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
+ * @brief SMARTCARD control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral FIFO Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SMARTCARD
+ FIFO feature.
+ (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the USART configuration registers.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
+ {
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart.c
index b9265ff..27b6224 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart.c
@@ -39,7 +39,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
(Receiver/Transmitter) in the husart handle Init structure.
@@ -198,7 +199,8 @@
static void USART_MDMATxAbortCallback(MDMA_HandleTypeDef *hmdma);
static void USART_MDMARxAbortCallback(MDMA_HandleTypeDef *hmdma);
#endif
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
@@ -324,7 +326,8 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -429,7 +432,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
+ */
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -537,9 +541,9 @@
}
/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param husart uart handle
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@@ -567,47 +571,47 @@
switch (CallbackID)
{
case HAL_USART_TX_HALFCOMPLETE_CB_ID :
- husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_USART_TX_COMPLETE_CB_ID :
- husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_USART_RX_HALFCOMPLETE_CB_ID :
- husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_USART_RX_COMPLETE_CB_ID :
- husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_USART_TX_RX_COMPLETE_CB_ID :
- husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break;
case HAL_USART_ERROR_CB_ID :
- husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_USART_ABORT_COMPLETE_CB_ID :
- husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_USART_RX_FIFO_FULL_CB_ID :
- husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_USART_TX_FIFO_EMPTY_CB_ID :
- husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_USART_MSPINIT_CB_ID :
- husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_USART_MSPDEINIT_CB_ID :
- husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -726,13 +730,16 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+ error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on USART side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -740,9 +747,12 @@
/**
* @brief Simplex send an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -765,7 +775,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
@@ -833,10 +843,13 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -860,7 +873,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -942,14 +955,18 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
@@ -972,7 +989,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -1087,9 +1104,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1166,10 +1186,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1267,13 +1290,17 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
@@ -1362,9 +1389,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1457,10 +1487,13 @@
* @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1598,13 +1631,17 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
HAL_StatusTypeDef status;
uint32_t *tmp;
@@ -1823,7 +1860,7 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1938,11 +1975,12 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* Disable the USART DMA Tx request if enabled */
@@ -2071,13 +2109,14 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
@@ -2283,7 +2322,8 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2338,6 +2378,14 @@
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
@@ -2636,8 +2684,8 @@
*/
/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief USART Peripheral State and Error functions
- *
+ * @brief USART Peripheral State and Error functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -2683,8 +2731,8 @@
*/
/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
+ * @{
+ */
/**
* @brief Initialize the callbacks to their default values.
@@ -2715,7 +2763,8 @@
static void USART_EndTransfer(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* At end of process, restore husart->State to Ready */
@@ -3045,7 +3094,7 @@
husart->TxCpltCallback(husart);
#else
HAL_USART_TxCpltCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
}
@@ -3083,7 +3132,7 @@
husart->RxCpltCallback(husart);
#else
HAL_USART_RxCpltCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
@@ -3093,7 +3142,7 @@
husart->TxRxCpltCallback(husart);
#else
HAL_USART_TxRxCpltCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
husart->State = HAL_USART_STATE_READY;
}
@@ -3122,7 +3171,7 @@
husart->ErrorCallback(husart);
#else
HAL_USART_ErrorCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
@@ -3143,7 +3192,7 @@
husart->ErrorCallback(husart);
#else
HAL_USART_ErrorCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
@@ -3187,7 +3236,7 @@
husart->AbortCpltCallback(husart);
#else
HAL_USART_AbortCpltCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
@@ -3232,7 +3281,7 @@
husart->AbortCpltCallback(husart);
#else
HAL_USART_AbortCpltCallback(husart);
-#endif
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
#endif
@@ -3245,7 +3294,8 @@
* @param Timeout timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
@@ -3281,6 +3331,7 @@
uint32_t usartdiv = 0x00000000;
PLL3_ClocksTypeDef pll3_clocks;
PLL4_ClocksTypeDef pll4_clocks;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -3327,13 +3378,16 @@
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PCLK5:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK5Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK5Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PLL3Q:
HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
@@ -3392,7 +3446,7 @@
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -3861,7 +3915,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
@@ -3995,7 +4050,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart_ex.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart_ex.c
index 0e7bcc9..fced1de 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart_ex.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_usart_ex.c
@@ -54,11 +54,17 @@
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* UART RX FIFO depth */
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+ * @{
+ */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@@ -237,7 +243,7 @@
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
- husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
husart->State = HAL_USART_STATE_READY;
@@ -497,8 +503,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{
@@ -509,10 +515,14 @@
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
- rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
- tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
- husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_wwdg.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_wwdg.c
index d5c7bb9..e19946b 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_wwdg.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_wwdg.c
@@ -81,12 +81,12 @@
(++) MspInitCallback : WWDG MspInit.
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
- corresponding legacy weak (surcharged) functions:
+ corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
@@ -270,7 +270,7 @@
/**
* @brief Unregister a WWDG Callback
- * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_adc.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_adc.c
index 236edd5..8df1c5f 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_adc.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_adc.c
@@ -80,7 +80,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
- ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
@@ -100,7 +100,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
- ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
@@ -108,7 +108,7 @@
)
#define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
- ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
+ (((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
|| ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
|| ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
|| ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
@@ -127,14 +127,14 @@
)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
- ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
@@ -157,24 +157,24 @@
)
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
- ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
+ (((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
|| ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|| ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
|| ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
)
#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
- ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
@@ -193,7 +193,7 @@
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
@@ -207,7 +207,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
@@ -230,25 +230,25 @@
)
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
- ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
)
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
@@ -256,7 +256,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
@@ -267,12 +267,12 @@
)
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
- ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
)
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
- ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
+ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
@@ -283,10 +283,10 @@
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) \
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
@@ -313,7 +313,7 @@
* the same ADC common instance to their default reset values.
* @note This function is performing a hard reset, using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* To de-initialize only 1 ADC instance, use
@@ -372,7 +372,7 @@
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
+ /* On this STM32 series, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
@@ -459,7 +459,7 @@
* is in an unknown state.
* In this case, perform a hard reset using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* Refer to function @ref LL_ADC_CommonDeInit().
@@ -705,10 +705,10 @@
/* ADC instance is in an unknown state */
/* Need to performing a hard reset of ADC instance, using high level */
/* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
status = ERROR;
@@ -785,6 +785,7 @@
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
+
return status;
}
@@ -847,6 +848,11 @@
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
@@ -865,7 +871,7 @@
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
@@ -925,7 +931,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
@@ -961,6 +967,12 @@
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -992,7 +1004,7 @@
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_delayblock.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_delayblock.c
index e5d5ed8..ff0e422 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_delayblock.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_delayblock.c
@@ -3,26 +3,26 @@
* @file stm32mp1xx_ll_delayblock.c
* @author MCD Application Team
* @brief DelayBlock Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the Delay Block peripheral:
* + input clock frequency range 25MHz to 208MHz
* + up to 12 oversampling phases
- *
+ *
@verbatim
==============================================================================
##### DelayBlock peripheral features #####
- ==============================================================================
+ ==============================================================================
[..] The Delay block is used to generate an Output clock which is de-phased from the Input
clock. The phase of the Output clock is programmed by FW. The Output clock is then used
to clock the receive data in i.e. a SDMMC or QSPI interface.
The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
and recenter the Output clock phase to the receive data.
-
+
[..] The Delay Block features include the following:
(+) Input clock frequency range 25MHz to 208MHz.
(+) Up to 12 oversampling phases.
-
+
##### How to use this driver #####
==============================================================================
[..]
@@ -31,8 +31,8 @@
The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
and configure the Output clock phase.
The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
-
-
+
+
@endverbatim
******************************************************************************
* @attention
@@ -46,7 +46,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -73,15 +73,15 @@
* @{
*/
-/** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
@@ -99,13 +99,13 @@
assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN;
-
+
while((tuningOn != 0) && (i < DLYB_MAX_UNIT))
{
-
+
DLYBx->CFGR = 12 | (i << 8);
HAL_Delay(1);
- if(((DLYBx->CFGR & DLYB_CFGR_LNGF) != 0)
+ if(((DLYBx->CFGR & DLYB_CFGR_LNGF) != 0)
&& ((DLYBx->CFGR & DLYB_CFGR_LNG) != 0)
&& ((DLYBx->CFGR & DLYB_CFGR_LNG) != (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)))
{
@@ -114,7 +114,7 @@
i++;
}
-
+
if(DLYB_MAX_UNIT != i)
{
@@ -127,7 +127,7 @@
if(0 != N)
{
MODIFY_REG(DLYBx->CFGR, DLYB_CFGR_SEL, ((N/2)+1));
-
+
/* Disable Selection phase */
DLYBx->CR = DLYB_CR_DEN;
return HAL_OK;
@@ -137,7 +137,7 @@
/* Disable DLYB */
DelayBlock_Disable(DLYBx);
return HAL_ERROR;
-
+
}
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_sdmmc.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_sdmmc.c
index 3628a76..a2049fb 100755
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_sdmmc.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_sdmmc.c
@@ -3,22 +3,22 @@
* @file stm32mp1xx_ll_sdmmc.c
* @author MCD Application Team
* @brief SDMMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the SDMMC peripheral:
* + Initialization/de-initialization functions
* + I/O operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### SDMMC peripheral features #####
- ==============================================================================
+ ==============================================================================
[..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
devices.
-
+
[..] The SDMMC features include the following:
(+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit.
@@ -40,35 +40,35 @@
that interfaces with the SDMMC peripheral.
According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
is used in the device's driver to perform SDMMC operations and functionalities.
-
+
This driver is almost transparent for the final user, it is only used to implement other
functionalities of the external device.
-
+
[..]
(+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R.
Before start working with SDMMC peripheral make sure that the PLL is well configured.
The SDMMC peripheral uses two clock signals:
(++) PLL1_Q bus clock (default after reset)
(++) PLL2_R bus clock
-
+
(+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
peripheral.
- (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
+ (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
-
- (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
- and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
-
- (+) When using the DMA mode
+
+ (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
+ and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
+
+ (+) When using the DMA mode
(++) Configure the IDMA mode (Single buffer or double)
(++) Configure the buffer address
(++) Configure Data Path State Machine
-
- (+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the SDMMC_SendCommand(SDMMCx),
+
+ (+) To control the CPSM (Command Path State Machine) and send
+ commands to the card use the SDMMC_SendCommand(SDMMCx),
SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
- to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
+ to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
to the selected command to be sent.
The parameters that should be filled are:
(++) Command Argument
@@ -76,16 +76,16 @@
(++) Command Response type
(++) Command Wait
(++) CPSM Status (Enable or Disable).
-
+
-@@- To check if the command is well received, read the SDMMC_CMDRESP
register using the SDMMC_GetCommandResponse().
The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
SDMMC_GetResponse() function.
-
- (+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
+
+ (+) To control the DPSM (Data Path State Machine) and send/receive
+ data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
-
+
*** Read Operations ***
=======================
[..]
@@ -98,14 +98,14 @@
(++) Data Transfer direction: should be from card (To SDMMC)
(++) Data Transfer mode
(++) DPSM Status (Enable or Disable)
-
+
(#) Configure the SDMMC resources to receive the data from the card
according to selected transfer mode (Refer to Step 8, 9 and 10).
-
+
(#) Send the selected Read command (refer to step 11).
-
+
(#) Use the SDMMC flags/interrupts to check the transfer status.
-
+
*** Write Operations ***
========================
[..]
@@ -118,23 +118,23 @@
(++) Data Transfer direction: should be to card (To CARD)
(++) Data Transfer mode
(++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDMMC resources to send the data to the card according to
+
+ (#) Configure the SDMMC resources to send the data to the card according to
selected transfer mode.
-
+
(#) Send the selected Write command.
-
+
(#) Use the SDMMC flags/interrupts to check the transfer status.
-
+
*** Command management operations ***
=====================================
[..]
- (#) The commands used for Read/Write/Erase operations are managed in
- separate functions.
+ (#) The commands used for Read/Write/Erase operations are managed in
+ separate functions.
Each function allows to send the needed command with the related argument,
then check the response.
By the same approach, you could implement a command and check the response.
-
+
@endverbatim
******************************************************************************
* @attention
@@ -148,7 +148,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
@@ -182,15 +182,15 @@
* @{
*/
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization/de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
@@ -199,7 +199,7 @@
* @brief Initializes the SDMMC according to the specified
* parameters in the SDMMC_InitTypeDef and create the associated handle.
* @param SDMMCx: Pointer to SDMMC register base
- * @param Init: SDMMC initialization structure
+ * @param Init: SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
@@ -208,22 +208,22 @@
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
- assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
+ assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
-
+
/* Set SDMMC configuration parameters */
tmpreg |= (Init.ClockEdge |\
Init.ClockPowerSave |\
Init.BusWide |\
Init.HardwareFlowControl |\
Init.ClockDiv
- );
+ );
/* Write to SDMMC CLKCR */
- MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
return HAL_OK;
}
@@ -233,15 +233,15 @@
* @}
*/
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- * @brief Data transfers functions
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### I/O operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the SDMMC data
+ This subsection provides a set of functions allowing to manage the SDMMC data
transfers.
@endverbatim
@@ -249,25 +249,25 @@
*/
/**
- * @brief Read data (word) from Rx FIFO in blocking mode (polling)
+ * @brief Read data (word) from Rx FIFO in blocking mode (polling)
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
{
- /* Read data from Rx FIFO */
+ /* Read data from Rx FIFO */
return (SDMMCx->FIFO);
}
/**
- * @brief Write data (word) to Tx FIFO in blocking mode (polling)
+ * @brief Write data (word) to Tx FIFO in blocking mode (polling)
* @param SDMMCx: Pointer to SDMMC register base
* @param pWriteData: pointer to data to write
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
-{
- /* Write data to FIFO */
+{
+ /* Write data to FIFO */
SDMMCx->FIFO = *pWriteData;
return HAL_OK;
@@ -277,15 +277,15 @@
* @}
*/
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- * @brief management functions
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the SDMMC data
+ This subsection provides a set of functions allowing to control the SDMMC data
transfers.
@endverbatim
@@ -293,37 +293,37 @@
*/
/**
- * @brief Set SDMMC Power state to ON.
+ * @brief Set SDMMC Power state to ON.
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
-{
- /* Set power state to ON */
+{
+ /* Set power state to ON */
SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
-
- /* 1ms: required power up waiting time before starting the SD initialization
+
+ /* 1ms: required power up waiting time before starting the SD initialization
sequence */
HAL_Delay(2);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Set SDMMC Power state to Power-Cycle.
+ * @brief Set SDMMC Power state to Power-Cycle.
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
-{
- /* Set power state to Power Cycle*/
+{
+ /* Set power state to Power Cycle*/
SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Set SDMMC Power state to OFF.
+ * @brief Set SDMMC Power state to OFF.
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
@@ -331,18 +331,18 @@
{
/* Set power state to OFF */
SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
-
+
return HAL_OK;
}
/**
- * @brief Get SDMMC Power state.
+ * @brief Get SDMMC Power state.
* @param SDMMCx: Pointer to SDMMC register base
- * @retval Power status of the controller. The returned value can be one of the
+ * @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
* - 0x02: Power UP
- * - 0x03: Power ON
+ * - 0x03: Power ON
*/
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
{
@@ -351,16 +351,16 @@
/**
* @brief Configure the SDMMC command path according to the specified parameters in
- * SDMMC_CmdInitTypeDef structure and send the command
+ * SDMMC_CmdInitTypeDef structure and send the command
* @param SDMMCx: Pointer to SDMMC register base
- * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+ * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
{
uint32_t tmpreg = 0;
-
+
/* Check the parameters */
assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
assert_param(IS_SDMMC_RESPONSE(Command->Response));
@@ -375,10 +375,10 @@
Command->Response |\
Command->WaitForInterrupt |\
Command->CPSM);
-
+
/* Write to SDMMC CMD register */
MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
-
+
return HAL_OK;
}
@@ -395,13 +395,13 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Response: Specifies the SDMMC response register.
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Response: Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDMMC_RESP1: Response Register 1
* @arg SDMMC_RESP2: Response Register 2
* @arg SDMMC_RESP3: Response Register 3
- * @arg SDMMC_RESP4: Response Register 4
+ * @arg SDMMC_RESP4: Response Register 4
* @retval The Corresponding response register value
*/
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
@@ -410,25 +410,25 @@
/* Check the parameters */
assert_param(IS_SDMMC_RESP(Response));
-
+
/* Get the response */
tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
-
+
return (*(__IO uint32_t *) tmp);
-}
+}
/**
- * @brief Configure the SDMMC data path according to the specified
+ * @brief Configure the SDMMC data path according to the specified
* parameters in the SDMMC_DataInitTypeDef.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Data : pointer to a SDMMC_DataInitTypeDef structure
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Data : pointer to a SDMMC_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
{
uint32_t tmpreg = 0;
-
+
/* Check the parameters */
assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
@@ -447,7 +447,7 @@
Data->TransferDir |\
Data->TransferMode |\
Data->DPSM);
-
+
/* Write to SDMMC DCTRL */
MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
@@ -467,7 +467,7 @@
/**
* @brief Get the FIFO data
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval Data received
*/
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
@@ -477,7 +477,7 @@
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
* This parameter can be:
* @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
@@ -491,8 +491,8 @@
/* Set SDMMC read wait mode */
MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -500,13 +500,13 @@
*/
-/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
- * @brief Data transfers functions
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### Commands management functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the needed commands.
@@ -516,22 +516,22 @@
/**
* @brief Send the Data Block Lenght command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
@@ -540,22 +540,22 @@
/**
* @brief Send the Read Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
@@ -564,22 +564,22 @@
/**
* @brief Send the Read Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
@@ -588,22 +588,22 @@
/**
* @brief Send the Write Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
@@ -612,22 +612,22 @@
/**
* @brief Send the Write Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
@@ -636,22 +636,22 @@
/**
* @brief Send the Start Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
@@ -660,22 +660,22 @@
/**
* @brief Send the End Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
@@ -684,22 +684,22 @@
/**
* @brief Send the Start Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
@@ -708,22 +708,22 @@
/**
* @brief Send the End Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
@@ -732,22 +732,22 @@
/**
* @brief Send the Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
@@ -756,14 +756,14 @@
/**
* @brief Send the Stop Transfer command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD12 STOP_TRANSMISSION */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
@@ -775,7 +775,7 @@
__SDMMC_CMDTRANS_DISABLE(SDMMCx);
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
@@ -786,15 +786,15 @@
/**
* @brief Send the Select Deselect command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param addr: Address of the card to be selected
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param addr: Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD7 SDMMC_SEL_DESEL_CARD */
sdmmc_cmdinit.Argument = (uint32_t)Addr;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
@@ -802,7 +802,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
@@ -811,21 +811,21 @@
/**
* @brief Send the Go Idle State command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdError(SDMMCx);
@@ -834,14 +834,14 @@
/**
* @brief Send the Operating Condition command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD8 to verify SD card interface operating condition */
/* Argument: - [31:12]: Reserved (shall be set to '0')
- [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
@@ -853,7 +853,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp7(SDMMCx);
@@ -861,25 +861,25 @@
}
/**
- * @brief Send the Application command to verify that that the next command
+ * @brief Send the Application command to verify that that the next command
* is an application specific com-mand rather than a standard command
* and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = (uint32_t)Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
/* If there is a HAL_ERROR, it is a MMC card, else
it is a SD card: SD card 2.0 (voltage range mismatch)
@@ -890,9 +890,9 @@
}
/**
- * @brief Send the command asking the accessed card to send its operating
+ * @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @param Argument: Command Argument
* @retval HAL status
*/
@@ -900,14 +900,14 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDMMCx);
@@ -924,14 +924,14 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
@@ -947,7 +947,7 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD51 SD_APP_SEND_SCR */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
@@ -955,7 +955,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
@@ -971,7 +971,7 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD2 ALL_SEND_CID */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
@@ -979,7 +979,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDMMCx);
@@ -996,7 +996,7 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD9 SEND_CSD */
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
@@ -1004,7 +1004,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDMMCx);
@@ -1013,15 +1013,15 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param pRCA: Card RCA
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param pRCA: Card RCA
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD3 SD_CMD_SET_REL_ADDR */
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
@@ -1029,7 +1029,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
@@ -1046,14 +1046,14 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
@@ -1062,21 +1062,21 @@
/**
* @brief Send the Status register command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = 0;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
@@ -1084,9 +1084,9 @@
}
/**
- * @brief Sends host capacity support information and activates the card's
+ * @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @parame Argument: Argument used for the command
* @retval HAL status
*/
@@ -1094,14 +1094,14 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDMMCx);
@@ -1110,7 +1110,7 @@
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @parame Argument: Argument used for the command
* @retval HAL status
*/
@@ -1118,7 +1118,7 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
/* CMD Response: R1 */
sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/
@@ -1127,7 +1127,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
@@ -1135,7 +1135,7 @@
}
/**
- * @brief Send the command asking the accessed card to send its operating
+ * @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
* @param None
* @retval HAL status
@@ -1144,14 +1144,14 @@
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
sdmmc_cmdinit.Argument = 0x00000000;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
@@ -1160,15 +1160,15 @@
/**
* @brief Send the Send EXT_CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
-
+
/* Send CMD9 SEND_CSD */
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
@@ -1176,7 +1176,7 @@
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
+
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
@@ -1188,11 +1188,11 @@
* @}
*/
-/* Private function ----------------------------------------------------------*/
+/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
-
+
/**
* @brief Checks for error conditions for CMD0.
* @param hsd: SD handle
@@ -1203,74 +1203,74 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
-
+
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
+
return SDMMC_ERROR_NONE;
}
/**
* @brief Checks for error conditions for R1 response.
* @param hsd: SD handle
- * @param SD_CMD: The sent command index
+ * @param SD_CMD: The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
{
uint32_t response_r1;
-
+
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END));
-
+
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
+
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
+
return SDMMC_ERROR_CMD_CRC_FAIL;
}
else
{
/* Nothing to do */
}
-
+
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
+
/* Check response received is of desired command */
if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
-
+
/* We have received response, retrieve it for analysis */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
-
+
if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
{
return SDMMC_ERROR_NONE;
@@ -1363,26 +1363,26 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
+
if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
+
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
+
return SDMMC_ERROR_CMD_CRC_FAIL;
}
else
@@ -1405,28 +1405,28 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
+
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
+
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else
- {
+ {
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
}
-
+
return SDMMC_ERROR_NONE;
}
@@ -1434,60 +1434,60 @@
* @brief Checks for error conditions for R6 (RCA) response.
* @param hsd: SD handle
* @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
- * address RCA
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * address RCA
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
{
uint32_t response_r1;
-
+
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
+
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
+
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
+
return SDMMC_ERROR_CMD_CRC_FAIL;
}
else
{
/* Nothing to do */
}
-
+
/* Check response received is of desired command */
if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
-
+
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
+
/* We have received response, retrieve it. */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
-
+
if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
{
*pRCA = (uint16_t) (response_r1 >> 16);
-
+
return SDMMC_ERROR_NONE;
}
else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
@@ -1514,29 +1514,29 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
+
do
{
if (count-- == 0U)
{
return SDMMC_ERROR_TIMEOUT;
}
-
+
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
+
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
-
+
else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
+
return SDMMC_ERROR_CMD_CRC_FAIL;
}
else
@@ -1549,9 +1549,9 @@
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
}
-
+
return SDMMC_ERROR_NONE;
-
+
}
/**
diff --git a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_usart.c b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_usart.c
index f75f3c3..b14d925 100644
--- a/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_usart.c
+++ b/stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_ll_usart.c
@@ -22,11 +22,11 @@
#include "stm32mp1xx_ll_usart.h"
#include "stm32mp1xx_ll_rcc.h"
#include "stm32mp1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32MP1xx_LL_Driver
* @{
@@ -41,31 +41,23 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
*/
#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
- || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
* divided by the smallest oversampling used on the USART (i.e. 8) */
@@ -78,42 +70,42 @@
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
@@ -219,8 +211,9 @@
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -271,7 +264,8 @@
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
@@ -371,13 +365,15 @@
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@@ -392,37 +388,25 @@
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/* Else (USART not in Disabled state => return ERROR */
else
@@ -443,9 +427,12 @@
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
}
/**
diff --git a/stm32cube/stm32mp1xx/soc/stm32mp151axx_ca7.h b/stm32cube/stm32mp1xx/soc/stm32mp151axx_ca7.h
index 4c6da15..8b0bf83 100644
--- a/stm32cube/stm32mp1xx/soc/stm32mp151axx_ca7.h
+++ b/stm32cube/stm32mp1xx/soc/stm32mp151axx_ca7.h
@@ -88,7 +88,7 @@
PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */
TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */
RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */
- RESERVED_36 = 36, /*!< RESERVED interrupt */
+ TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */
RCC_IRQn = 37, /*!< RCC global Interrupt */
EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */
@@ -329,8 +329,8 @@
__IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
__IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
uint32_t RESERVED10; /*!< Reserved, 0x0CC */
- __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */
- uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
+ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */
+ uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
__IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */
@@ -344,7 +344,6 @@
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
} ADC_Common_TypeDef;
@@ -430,6 +429,224 @@
__IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */
} DAC_TypeDef;
+/*
+ * @brief DDRCTRL block description (DDRCTRL)
+ */
+typedef struct
+{
+ __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */
+ __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */
+ uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
+ __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */
+ __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */
+ __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */
+ __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */
+ __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */
+ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
+ __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */
+ __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */
+ __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */
+ uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
+ __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */
+ uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
+ __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */
+ __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */
+ uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
+ __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */
+ uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
+ __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */
+ __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */
+ __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */
+ __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */
+ __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */
+ __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */
+ __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */
+ uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
+ __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */
+ uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
+ __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */
+ __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */
+ __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */
+ __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */
+ __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */
+ __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */
+ __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */
+ __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */
+ __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */
+ uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
+ __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */
+ __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */
+ uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
+ __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */
+ __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */
+ __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */
+ __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */
+ __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */
+ __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */
+ __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */
+ uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */
+ __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */
+ __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */
+ __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */
+ uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */
+ __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */
+ uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
+ __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */
+ uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */
+ __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */
+ uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
+ __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */
+ __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */
+ __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */
+ __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */
+ __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */
+ __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */
+ uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
+ __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */
+ __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */
+ __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */
+ uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
+ __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */
+ __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */
+ uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
+ __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */
+ __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */
+ uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */
+ __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */
+ uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */
+ __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */
+ uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */
+ __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */
+ uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
+ __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */
+ __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */
+ __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */
+ __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */
+ __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */
+ uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
+ __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */
+ __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */
+ uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
+ __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */
+ __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */
+ uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
+ __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */
+ __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */
+ __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */
+ __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */
+ uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
+ __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */
+ __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */
+ __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */
+ __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */
+ __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */
+ uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
+ __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */
+ __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */
+ uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
+ __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */
+ __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */
+ __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */
+ __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */
+ __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */
+} DDRCTRL_TypeDef;
+
+/*
+ * @brief DDRPERFM block description (DDRPERFM)
+ */
+typedef struct
+{
+ __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */
+ __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */
+ __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */
+ __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */
+ __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */
+ __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */
+ __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */
+ __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */
+ uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
+ __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */
+ __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */
+ __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */
+ uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */
+ __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */
+ uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
+ __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */
+ __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */
+ __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */
+ __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */
+} DDRPERFM_TypeDef;
+
+/*
+ * @brief DDRPHYC block description (DDRPHYC)
+ */
+typedef struct
+{
+ __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */
+ __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */
+ __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */
+ __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */
+ __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */
+ __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */
+ __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */
+ __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */
+ __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */
+ __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */
+ __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */
+ __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */
+ __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */
+ __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */
+ __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */
+ __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */
+ __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */
+ __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */
+ __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */
+ __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */
+ __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */
+ __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */
+ __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */
+ __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */
+ uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
+ __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */
+ __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */
+ __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */
+ __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */
+ __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */
+ __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */
+ uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
+ __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */
+ __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */
+ __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */
+ __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */
+ __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */
+ __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */
+ uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
+ __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */
+ __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */
+ __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */
+ __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */
+ __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */
+ __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */
+ uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
+ __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */
+ __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */
+ __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */
+ __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */
+ __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */
+ __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */
+ uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
+ __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */
+ __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */
+ __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */
+ __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */
+ __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */
+ __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */
+} DDRPHYC_TypeDef;
+
/**
* @brief DFSDM module registers
*/
@@ -871,14 +1088,11 @@
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
- __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
- __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
+ __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
- __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
+ __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
- __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
- __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
+ __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
@@ -1020,18 +1234,18 @@
{
__IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */
__IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */
- __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */
__IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */
__IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */
__IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */
__IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */
- __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
+ uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
__IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */
- __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
+ uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
__IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */
- uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */
+ uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */
__IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */
@@ -1194,110 +1408,6 @@
/**
- * @brief DDRPHYC DDR Physical Interface Control
- */
-typedef struct
-{
- __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */
- __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */
- __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */
- __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */
- __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */
- __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */
- __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */
- __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */
- __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */
- __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */
- __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */
- __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */
- __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */
- __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */
- __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */
- __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */
- __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */
- __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */
- __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */
- __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */
- __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */
- __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */
- __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */
- __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */
- uint32_t RESERVED0[24]; /*!< Reserved */
- __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */
- __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */
- __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */
- __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */
- __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */
- __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */
- __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */
- __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */
- uint32_t RESERVED1[8]; /*!< Reserved */
- __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */
- __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */
- __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */
- __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */
- __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */
- __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */
- __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */
- __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */
- __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */
- __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */
- __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */
- __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */
- __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */
- __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */
- __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */
- __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */
- __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */
- uint32_t RESERVED2[13]; /*!< Reserved */
- __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */
- __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */
- __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */
- __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */
- __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */
- __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */
- uint32_t RESERVED3[12]; /*!< Reserved */
- __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */
- __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */
- __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */
- __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */
- __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */
- __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */
- uint32_t RESERVED4[10]; /*!< Reserved */
- __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */
- __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */
- __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */
- __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */
- __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */
- __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */
- uint32_t RESERVED5[10]; /*!< Reserved */
- __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */
- __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */
- __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */
- __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */
- __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */
- __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */
- uint32_t RESERVED6[10]; /*!< Reserved */
- __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */
- __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */
- __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */
- __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */
- __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */
- __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */
-}DDRPHYC_TypeDef;
-
-
-/**
- * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL)
- */
-typedef struct
-{
- __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */
- /* @TODO : TypeDef to be compleated */
-}DDRC_TypeDef;
-
-
-/**
* @brief USBPHYC USB HS PHY Control
*/
typedef struct
@@ -1375,11 +1485,35 @@
*/
typedef struct
{
- __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */
- /* @TODO : TypeDef to be compleated if needed*/
+ __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */
+ uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */
+ __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */
+ __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
+ __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */
+ uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
+ __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */
+ __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
+ __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
+ __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */
}STGENC_TypeDef;
/**
+ * @brief STGENR System Timestamp Generator Read
+ */
+typedef struct
+{
+ __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */
+ __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */
+ uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
+ __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */
+ __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
+ __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
+ __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
+} STGENR_TypeDef;
+
+
+/**
* @brief Firewall
*/
@@ -1708,7 +1842,7 @@
__IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */
__IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */
__IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */
- __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */
+ __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */
__IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */
__IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */
@@ -1770,36 +1904,36 @@
typedef struct
{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
- __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
- uint32_t RESERVED; /*!< Reserved */
- __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
- uint32_t RESERVED1; /*!< Reserved */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
- __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
- __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
- __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
- __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
- __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
- uint32_t RESERVED2[227]; /*!< Reserved */
- __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
- __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
- __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
- __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved */
+ __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED1; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
+ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
+ __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
+ uint32_t RESERVED2[227]; /*!< Reserved */
+ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
} RTC_TypeDef;
@@ -1865,7 +1999,6 @@
__IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */
-
} TAMP_TypeDef;
@@ -1965,7 +2098,7 @@
__IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
__IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */
uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */
__IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */
@@ -2278,17 +2411,16 @@
/**
* @brief RNG
*/
-
typedef struct
{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
- __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
- __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
- __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
- __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
- __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;
/**
@@ -2556,20 +2688,20 @@
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
-#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
+#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
+#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
#define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */
#define RETRAM_BASE MCU_AHB_RETRAM
-#define SRAM_BASE MCU_AHB_SRAM
+#define SRAM_BASE AHB_SRAM
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
-#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
+#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
-#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
-#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
-#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
-#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
-#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
+#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
+#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
+#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
+#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
/*!< Device electronic signature memory map */
#define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */
@@ -2578,69 +2710,83 @@
#define DV_BASE (0x50081000L) /*!< Device Version register base address */
/*!< Peripheral memory map */
-#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
-#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
-#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
-#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
-#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
-#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
-#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
-#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
-#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
-#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
-#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
+#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
+#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
+#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
+#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
+#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
+#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
+#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
+#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
+#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
+#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
+#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
-/*!< MCU_APB1 */
-#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000)
-#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000)
-#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000)
-#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000)
-#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000)
-#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000)
-#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000)
-#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000)
-#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000)
-#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000)
-#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000)
-#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000)
-#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000)
-#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000)
-#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000)
-#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000)
-#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000)
-#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000)
-#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000)
-#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000)
-#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000)
-#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000)
-#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000)
-#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000)
-#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000)
-#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000)
-#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000)
+#define MCU_AHB_SRAM AHB_SRAM
+#define MCU_AHB_RETRAM AHB_RETRAM
+#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE
+#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE
+#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE
+#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE
+#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE
+#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE
+#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE
+#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE
+#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE
+#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE
+#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE
-/*!< MCU_APB2 */
-#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000)
-#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000)
-#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000)
-#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000)
-#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000)
-#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000)
-#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000)
-#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000)
-#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000)
+/*!< APB1 */
+#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000)
+#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000)
+#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000)
+#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000)
+#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000)
+#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000)
+#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000)
+#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000)
+#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000)
+#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000)
+#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000)
+#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000)
+#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000)
+#define USART2_BASE (APB1_PERIPH_BASE + 0xE000)
+#define USART3_BASE (APB1_PERIPH_BASE + 0xF000)
+#define UART4_BASE (APB1_PERIPH_BASE + 0x10000)
+#define UART5_BASE (APB1_PERIPH_BASE + 0x11000)
+#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000)
+#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000)
+#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000)
+#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000)
+#define CEC_BASE (APB1_PERIPH_BASE + 0x16000)
+#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000)
+#define UART7_BASE (APB1_PERIPH_BASE + 0x18000)
+#define UART8_BASE (APB1_PERIPH_BASE + 0x19000)
+#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000)
+
+/*!< APB2 */
+#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2_PERIPH_BASE + 0x3000)
+#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000)
+#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000)
+#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000)
+#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000)
+#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000)
+#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000)
+#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000)
+#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000)
+#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000)
#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
-#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000)
+#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
@@ -2656,42 +2802,42 @@
#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300)
#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380)
-/*!< MCU_AHB2 */
-#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000)
-#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000)
-#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000)
-#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000)
-#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100)
-#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300)
-#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000)
-#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000)
-#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000)
+/*!< AHB2 */
+#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000)
+#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000)
+#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000)
+#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000)
+#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100)
+#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300)
+#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000)
+#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000)
+#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000)
-/*!< MCU_AHB3 */
-#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000)
-#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000)
-#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000)
-#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310)
-#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000)
-#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000)
-#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000)
+/*!< AHB3 */
+#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000)
+#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000)
+#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000)
+#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310)
+#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000)
+#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000)
+#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000)
-/*!< MCU_AHB4 */
-#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000)
-#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000)
-#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000)
-#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000)
-#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000)
-#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000)
-#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000)
-#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000)
-#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000)
-#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000)
-#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000)
-#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000)
-#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000)
-#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000)
+/*!< AHB4 */
+#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000)
+#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000)
+#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000)
+#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000)
+#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000)
+#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000)
+#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000)
+#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000)
+#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000)
+#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000)
+#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000)
+#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000)
+#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000)
+#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000)
#define AIEC_C1_BASE (AIEC_BASE + 0x0080)
#define AIEC_C2_BASE (AIEC_BASE + 0x00C0)
/* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/
@@ -2700,71 +2846,72 @@
#define EXTI_C2_BASE AIEC_C2_BASE
-/*!< MCU_APB3 */
-#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000)
-#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000)
-#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000)
-#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000)
-#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000)
-#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000)
-#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000)
+/*!< APB3 */
+#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000)
+#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000)
+#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000)
+#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000)
+#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000)
+#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000)
+#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000)
#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
-#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000)
-#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000)
-#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000)
+#define DTS_BASE (APB3_PERIPH_BASE + 0x8000)
+#define PMB_BASE (APB3_PERIPH_BASE + 0x9000)
+#define HDP_BASE (APB3_PERIPH_BASE + 0xA000)
-/*!< MCU_AHB4 _APB_Debug */
+/*!< AHB4 _APB_Debug */
#define DBGMCU_BASE ((uint32_t )0x50081000)
-/*!< MCU_AHB5 */
-#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000)
-#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000)
-#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310)
-#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000)
-#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000)
+/*!< AHB5 */
+#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000)
+#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000)
+#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310)
+#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000)
+#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000)
/*!< GPV */
/*!< MPU_AHB6 */
-#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000)
-#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000)
-#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000)
-#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000)
-#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000)
-#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000)
-#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000)
-#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000)
-#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000)
-#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000)
+#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000)
+#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000)
+#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000)
+#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000)
+#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000)
+#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000)
+#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000)
+#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000)
+#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000)
+#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000)
#define ETH_MAC_BASE (ETH_BASE)
-#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000)
-#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000)
+#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000)
+#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000)
/*!< MPU_APB4 */
-#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000)
+#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000)
-#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000)
-#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000)
-#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000)
-#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000)
+#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000)
+#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000)
+#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000)
+#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000)
+#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000)
+#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000)
#define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100)
#define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200)
/*!< MPU_APB5 */
-#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000)
-#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000)
-#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000)
-#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000)
-#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000)
-#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000)
-#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000)
-#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000)
-#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000)
-#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000)
-#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000)
+#define USART1_BASE (APB5_PERIPH_BASE + 0x0000)
+#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000)
+#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000)
+#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000)
+#define RTC_BASE (APB5_PERIPH_BASE + 0x4000)
+#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000)
+#define TZC_BASE (APB5_PERIPH_BASE + 0x6000)
+#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000)
+#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000)
+#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000)
+#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000)
@@ -2802,6 +2949,7 @@
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
@@ -2828,7 +2976,6 @@
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
-
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
@@ -3008,6 +3155,7 @@
#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE)
+
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
@@ -3028,7 +3176,6 @@
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -3077,7 +3224,8 @@
#define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE)
#define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE)
-#define DDRC ((DDRC_TypeDef *)DDRC_BASE)
+#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE)
+#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE)
#define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
@@ -3086,7 +3234,7 @@
#define TZC ((TZC_TypeDef *)TZC_BASE)
#define TZPC ((TZPC_TypeDef *)TZPC_BASE)
#define STGENC ((STGENC_TypeDef *)STGENC_BASE)
-
+#define STGENR ((STGENR_TypeDef *)STGENR_BASE)
#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
@@ -3454,7 +3602,6 @@
#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
/******************** Bit definition for ADC_SMPR1 register ********************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -3682,6 +3829,7 @@
#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */
#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */
+
/******************** Bit definition for ADC_LTR2 register ********************/
#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */
#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
@@ -3955,7 +4103,7 @@
#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
@@ -4226,7 +4374,7 @@
/******************** Bit definition for ADC_JDR1 register ********************/
#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
@@ -4263,7 +4411,7 @@
/******************** Bit definition for ADC_JDR2 register ********************/
#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
@@ -4300,7 +4448,7 @@
/******************** Bit definition for ADC_JDR3 register ********************/
#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
@@ -4337,7 +4485,7 @@
/******************** Bit definition for ADC_JDR4 register ********************/
#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
@@ -4712,6 +4860,97 @@
#define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
#define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for ADC_VERR register ******************/
+#define ADC_VERR_MINREV_Pos (0U)
+#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */
+#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */
+#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */
+#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */
+#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */
+#define ADC_VERR_MAJREV_Pos (4U)
+#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */
+#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */
+#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */
+#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */
+#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */
+
+/***************** Bit definition for ADC_IPDR register ******************/
+#define ADC_IPDR_ID_Pos (0U)
+#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */
+#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
+#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
+#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
+#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
+#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
+#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
+#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
+#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
+#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */
+#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */
+#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */
+#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */
+#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */
+#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */
+#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */
+#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */
+#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */
+#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */
+#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */
+#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */
+#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */
+#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */
+#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */
+#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */
+#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */
+#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */
+#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */
+#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */
+#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */
+#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */
+#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */
+#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for ADC_SIDR register ******************/
+#define ADC_SIDR_SID_Pos (0U)
+#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */
+#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */
+#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */
+#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */
+#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */
+#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */
+#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */
+#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */
+#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */
+#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */
+#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */
+#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */
+#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */
+#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */
+#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */
+#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */
+#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */
+#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */
+#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */
+#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */
+#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */
+#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */
+#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */
+#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */
+#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */
+#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */
+#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */
+#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */
+#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */
+#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */
+#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */
+#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */
+#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */
+
/******************************************************************************/
/* */
/* VREFBUF */
@@ -5600,6 +5839,4571 @@
/******************************************************************************/
/* */
+/* DDRCTRL block description (DDRCTRL) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for DDRCTRL_MSTR register *****************/
+#define DDRCTRL_MSTR_DDR3_Pos (0U)
+#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */
+#define DDRCTRL_MSTR_LPDDR2_Pos (2U)
+#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */
+#define DDRCTRL_MSTR_LPDDR3_Pos (3U)
+#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */
+#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */
+#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U)
+#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */
+#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U)
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U)
+#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */
+#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U)
+#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */
+#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */
+
+/***************** Bit definition for DDRCTRL_STAT register *****************/
+#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U)
+#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */
+#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */
+#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U)
+#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */
+#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */
+#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U)
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */
+
+/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/
+#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U)
+#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */
+#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U)
+#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */
+#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */
+#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U)
+#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */
+#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U)
+#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */
+#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */
+
+/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/
+#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U)
+#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */
+#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */
+#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */
+#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */
+#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */
+#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */
+#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */
+#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */
+#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */
+#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */
+#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */
+#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */
+#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */
+
+/**************** Bit definition for DDRCTRL_MRSTAT register ****************/
+#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U)
+#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */
+
+/*************** Bit definition for DDRCTRL_DERATEEN register ***************/
+#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U)
+#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U)
+#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */
+#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U)
+#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */
+
+/************** Bit definition for DDRCTRL_DERATEINT register ***************/
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U)
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_PWRCTL register ****************/
+#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U)
+#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */
+#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U)
+#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U)
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U)
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */
+#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U)
+#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U)
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
+
+/**************** Bit definition for DDRCTRL_PWRTMG register ****************/
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U)
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U)
+#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/
+#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U)
+#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U)
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U)
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U)
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U)
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U)
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U)
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U)
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U)
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */
+
+/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U)
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U)
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */
+
+/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */
+
+/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U)
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U)
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */
+
+/**************** Bit definition for DDRCTRL_INIT0 register *****************/
+#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U)
+#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */
+#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U)
+#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */
+#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT1 register *****************/
+#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U)
+#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */
+#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */
+#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U)
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */
+
+/**************** Bit definition for DDRCTRL_INIT2 register *****************/
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U)
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U)
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */
+
+/**************** Bit definition for DDRCTRL_INIT3 register *****************/
+#define DDRCTRL_INIT3_EMR_Pos (0U)
+#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */
+#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_INIT3_MR_Pos (16U)
+#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */
+#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */
+#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */
+#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */
+#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */
+#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */
+#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT4 register *****************/
+#define DDRCTRL_INIT4_EMR3_Pos (0U)
+#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */
+#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */
+#define DDRCTRL_INIT4_EMR2_Pos (16U)
+#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */
+#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */
+#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */
+#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */
+#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */
+#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */
+#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT5 register *****************/
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U)
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U)
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U)
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U)
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U)
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U)
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U)
+#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */
+#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U)
+#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */
+#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/
+#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U)
+#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */
+#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */
+#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U)
+#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */
+#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U)
+#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */
+#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/
+#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U)
+#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */
+#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U)
+#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
+#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U)
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U)
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/
+#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U)
+#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */
+#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
+#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U)
+#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */
+#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */
+#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U)
+#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */
+#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */
+#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/
+#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U)
+#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */
+#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U)
+#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */
+#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U)
+#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */
+#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U)
+#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */
+#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/
+#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U)
+#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */
+#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U)
+#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */
+#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U)
+#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U)
+#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/
+#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U)
+#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */
+#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U)
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U)
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/
+#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U)
+#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */
+#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U)
+#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/
+#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U)
+#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */
+#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U)
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */
+
+/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/
+#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U)
+#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */
+#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */
+#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */
+
+/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U)
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U)
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */
+
+/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U)
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U)
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U)
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U)
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U)
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */
+
+/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U)
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U)
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/
+#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U)
+#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */
+
+/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U)
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */
+
+/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U)
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U)
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U)
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U)
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U)
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U)
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U)
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */
+
+/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U)
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U)
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U)
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U)
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U)
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U)
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */
+
+/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U)
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U)
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U)
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
+
+/*************** Bit definition for DDRCTRL_DFIMISC register ****************/
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U)
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U)
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */
+#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U)
+#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U)
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */
+
+/*************** Bit definition for DDRCTRL_DFISTAT register ****************/
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U)
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */
+#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U)
+#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */
+
+/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U)
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U)
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U)
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U)
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */
+
+/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */
+
+/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U)
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */
+
+/**************** Bit definition for DDRCTRL_ODTCFG register ****************/
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U)
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U)
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U)
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U)
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */
+
+/**************** Bit definition for DDRCTRL_ODTMAP register ****************/
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U)
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U)
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */
+
+/**************** Bit definition for DDRCTRL_SCHED register *****************/
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U)
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */
+#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U)
+#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */
+#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U)
+#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U)
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U)
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U)
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */
+
+/**************** Bit definition for DDRCTRL_SCHED1 register ****************/
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U)
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */
+
+/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRCTRL_DBG0 register *****************/
+#define DDRCTRL_DBG0_DIS_WC_Pos (0U)
+#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U)
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */
+
+/***************** Bit definition for DDRCTRL_DBG1 register *****************/
+#define DDRCTRL_DBG1_DIS_DQ_Pos (0U)
+#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */
+#define DDRCTRL_DBG1_DIS_HIF_Pos (1U)
+#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */
+
+/**************** Bit definition for DDRCTRL_DBGCAM register ****************/
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U)
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U)
+#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U)
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U)
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */
+
+/**************** Bit definition for DDRCTRL_DBGCMD register ****************/
+#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U)
+#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U)
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */
+#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U)
+#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */
+
+/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U)
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U)
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U)
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */
+
+/**************** Bit definition for DDRCTRL_SWCTL register *****************/
+#define DDRCTRL_SWCTL_SW_DONE_Pos (0U)
+#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */
+
+/**************** Bit definition for DDRCTRL_SWSTAT register ****************/
+#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U)
+#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */
+
+/************** Bit definition for DDRCTRL_POISONCFG register ***************/
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U)
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U)
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U)
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U)
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U)
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U)
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */
+
+/************** Bit definition for DDRCTRL_POISONSTAT register **************/
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U)
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U)
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U)
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U)
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */
+
+/**************** Bit definition for DDRCTRL_PSTAT register *****************/
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U)
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U)
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */
+
+/**************** Bit definition for DDRCTRL_PCCFG register *****************/
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U)
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U)
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */
+#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U)
+#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */
+
+/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U)
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */
+
+/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+
+/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/
+#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U)
+#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */
+
+/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U)
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U)
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U)
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U)
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */
+
+/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U)
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */
+
+/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+
+/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/
+#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U)
+#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */
+
+/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U)
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U)
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U)
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U)
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */
+
+/******************************************************************************/
+/* */
+/* DDRPERFM block description (DDRPERFM) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for DDRPERFM_CTL register *****************/
+#define DDRPERFM_CTL_START_Pos (0U)
+#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */
+#define DDRPERFM_CTL_STOP_Pos (1U)
+#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */
+
+/***************** Bit definition for DDRPERFM_CFG register *****************/
+#define DDRPERFM_CFG_EN_Pos (0U)
+#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */
+#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */
+#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CFG_SEL_Pos (16U)
+#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */
+#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */
+#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */
+
+/*************** Bit definition for DDRPERFM_STATUS register ****************/
+#define DDRPERFM_STATUS_COVF_Pos (0U)
+#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */
+#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */
+#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */
+#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */
+#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */
+#define DDRPERFM_STATUS_BUSY_Pos (16U)
+#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */
+#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */
+#define DDRPERFM_STATUS_TOVF_Pos (31U)
+#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */
+#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */
+
+/***************** Bit definition for DDRPERFM_CCR register *****************/
+#define DDRPERFM_CCR_CCLR_Pos (0U)
+#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */
+#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */
+#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CCR_TCLR_Pos (31U)
+#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */
+#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */
+
+/***************** Bit definition for DDRPERFM_IER register *****************/
+#define DDRPERFM_IER_OVFIE_Pos (0U)
+#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */
+#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */
+
+/***************** Bit definition for DDRPERFM_ISR register *****************/
+#define DDRPERFM_ISR_OVFF_Pos (0U)
+#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */
+
+/***************** Bit definition for DDRPERFM_ICR register *****************/
+#define DDRPERFM_ICR_OVF_Pos (0U)
+#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */
+
+/**************** Bit definition for DDRPERFM_TCNT register *****************/
+#define DDRPERFM_TCNT_CNT_Pos (0U)
+#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */
+#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT0 register *****************/
+#define DDRPERFM_CNT0_CNT_Pos (0U)
+#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT1 register *****************/
+#define DDRPERFM_CNT1_CNT_Pos (0U)
+#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT2 register *****************/
+#define DDRPERFM_CNT2_CNT_Pos (0U)
+#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT3 register *****************/
+#define DDRPERFM_CNT3_CNT_Pos (0U)
+#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_HWCFG register ****************/
+#define DDRPERFM_HWCFG_NCNT_Pos (0U)
+#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */
+#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */
+#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */
+
+/***************** Bit definition for DDRPERFM_VER register *****************/
+#define DDRPERFM_VER_MINREV_Pos (0U)
+#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */
+#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */
+#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */
+#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */
+#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */
+#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */
+#define DDRPERFM_VER_MAJREV_Pos (4U)
+#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */
+#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */
+#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */
+#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */
+#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */
+#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */
+
+/***************** Bit definition for DDRPERFM_ID register ******************/
+#define DDRPERFM_ID_ID_Pos (0U)
+#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */
+#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */
+#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */
+#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */
+#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */
+#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */
+#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */
+#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */
+#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */
+#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */
+#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */
+#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */
+#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */
+#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */
+#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */
+#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */
+#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */
+#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */
+#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */
+#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */
+#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */
+#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */
+#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */
+#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */
+#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */
+#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */
+#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */
+#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */
+#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */
+#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */
+#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */
+#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPERFM_SID register *****************/
+#define DDRPERFM_SID_SID_Pos (0U)
+#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */
+#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */
+#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */
+#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */
+#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */
+#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */
+#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */
+#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */
+#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */
+#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */
+#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */
+#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */
+#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */
+#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */
+#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */
+#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */
+#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */
+#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */
+#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */
+#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */
+#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */
+#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */
+#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */
+#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */
+#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */
+#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */
+#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */
+#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */
+#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */
+#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */
+#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */
+#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */
+#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */
+
+/******************************************************************************/
+/* */
+/* DDRPHYC block description (DDRPHYC) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for DDRPHYC_RIDR register *****************/
+#define DDRPHYC_RIDR_PUBMNR_Pos (0U)
+#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */
+#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */
+#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */
+#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */
+#define DDRPHYC_RIDR_PUBMDR_Pos (4U)
+#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */
+#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_RIDR_PUBMJR_Pos (8U)
+#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */
+#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_RIDR_PHYMNR_Pos (12U)
+#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */
+#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */
+#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */
+#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */
+#define DDRPHYC_RIDR_PHYMDR_Pos (16U)
+#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */
+#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */
+#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */
+#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */
+#define DDRPHYC_RIDR_PHYMJR_Pos (20U)
+#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */
+#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */
+#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */
+#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */
+#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */
+#define DDRPHYC_RIDR_UDRID_Pos (24U)
+#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
+#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */
+#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */
+#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */
+#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */
+#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */
+#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */
+#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */
+#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_PIR register ******************/
+#define DDRPHYC_PIR_INIT_Pos (0U)
+#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */
+#define DDRPHYC_PIR_DLLSRST_Pos (1U)
+#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_PIR_DLLLOCK_Pos (2U)
+#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */
+#define DDRPHYC_PIR_ZCAL_Pos (3U)
+#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */
+#define DDRPHYC_PIR_ITMSRST_Pos (4U)
+#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */
+#define DDRPHYC_PIR_DRAMRST_Pos (5U)
+#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */
+#define DDRPHYC_PIR_DRAMINIT_Pos (6U)
+#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */
+#define DDRPHYC_PIR_QSTRN_Pos (7U)
+#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */
+#define DDRPHYC_PIR_RVTRN_Pos (8U)
+#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */
+#define DDRPHYC_PIR_ICPC_Pos (16U)
+#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */
+#define DDRPHYC_PIR_DLLBYP_Pos (17U)
+#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */
+#define DDRPHYC_PIR_CTLDINIT_Pos (18U)
+#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */
+#define DDRPHYC_PIR_CLRSR_Pos (28U)
+#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */
+#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */
+#define DDRPHYC_PIR_LOCKBYP_Pos (29U)
+#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */
+#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */
+#define DDRPHYC_PIR_ZCALBYP_Pos (30U)
+#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */
+#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */
+#define DDRPHYC_PIR_INITBYP_Pos (31U)
+#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */
+
+/***************** Bit definition for DDRPHYC_PGCR register *****************/
+#define DDRPHYC_PGCR_ITMDMD_Pos (0U)
+#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */
+#define DDRPHYC_PGCR_DQSCFG_Pos (1U)
+#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */
+#define DDRPHYC_PGCR_DFTCMP_Pos (2U)
+#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */
+#define DDRPHYC_PGCR_DFTLMT_Pos (3U)
+#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */
+#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */
+#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PGCR_DTOSEL_Pos (5U)
+#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */
+#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */
+#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PGCR_CKEN_Pos (9U)
+#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */
+#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PGCR_CKDV_Pos (12U)
+#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */
+#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */
+#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PGCR_CKINV_Pos (14U)
+#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */
+#define DDRPHYC_PGCR_IOLB_Pos (15U)
+#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */
+#define DDRPHYC_PGCR_IODDRM_Pos (16U)
+#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */
+#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */
+#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PGCR_RANKEN_Pos (18U)
+#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */
+#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */
+#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PGCR_ZKSEL_Pos (22U)
+#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */
+#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */
+#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PGCR_PDDISDX_Pos (24U)
+#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */
+#define DDRPHYC_PGCR_RFSHDT_Pos (25U)
+#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */
+#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */
+#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */
+#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */
+#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */
+#define DDRPHYC_PGCR_LBDQSS_Pos (29U)
+#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */
+#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */
+#define DDRPHYC_PGCR_LBGDQS_Pos (30U)
+#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */
+#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */
+#define DDRPHYC_PGCR_LBMODE_Pos (31U)
+#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */
+
+/***************** Bit definition for DDRPHYC_PGSR register *****************/
+#define DDRPHYC_PGSR_IDONE_Pos (0U)
+#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */
+#define DDRPHYC_PGSR_DLDONE_Pos (1U)
+#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */
+#define DDRPHYC_PGSR_ZCDDONE_Pos (2U)
+#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */
+#define DDRPHYC_PGSR_DIDONE_Pos (3U)
+#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */
+#define DDRPHYC_PGSR_DTDONE_Pos (4U)
+#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_PGSR_DTERR_Pos (5U)
+#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_PGSR_DTIERR_Pos (6U)
+#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_PGSR_DFTERR_Pos (7U)
+#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_PGSR_RVERR_Pos (8U)
+#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */
+#define DDRPHYC_PGSR_RVEIRR_Pos (9U)
+#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */
+#define DDRPHYC_PGSR_TQ_Pos (31U)
+#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */
+
+/**************** Bit definition for DDRPHYC_DLLGCR register ****************/
+#define DDRPHYC_DLLGCR_DRES_Pos (0U)
+#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */
+#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DLLGCR_IPUMP_Pos (2U)
+#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */
+#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */
+#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DLLGCR_TESTEN_Pos (5U)
+#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */
+#define DDRPHYC_DLLGCR_DTC_Pos (6U)
+#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */
+#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DLLGCR_ATC_Pos (9U)
+#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */
+#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DLLGCR_TESTSW_Pos (11U)
+#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */
+#define DDRPHYC_DLLGCR_MBIAS_Pos (12U)
+#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */
+#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */
+#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U)
+#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */
+#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DLLGCR_BPS200_Pos (23U)
+#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */
+#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U)
+#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */
+#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U)
+#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */
+#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U)
+#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */
+#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U)
+#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */
+#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */
+#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/
+#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */
+#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */
+#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */
+#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */
+
+/***************** Bit definition for DDRPHYC_PTR0 register *****************/
+#define DDRPHYC_PTR0_TDLLSRST_Pos (0U)
+#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */
+#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U)
+#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */
+#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */
+#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR0_TITMSRST_Pos (18U)
+#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */
+#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */
+#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */
+
+/***************** Bit definition for DDRPHYC_PTR1 register *****************/
+#define DDRPHYC_PTR1_TDINIT0_Pos (0U)
+#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */
+#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */
+#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR1_TDINIT1_Pos (19U)
+#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */
+#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */
+#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */
+
+/***************** Bit definition for DDRPHYC_PTR2 register *****************/
+#define DDRPHYC_PTR2_TDINIT2_Pos (0U)
+#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */
+#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */
+#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR2_TDINIT3_Pos (17U)
+#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */
+#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */
+#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */
+
+/**************** Bit definition for DDRPHYC_ACIOCR register ****************/
+#define DDRPHYC_ACIOCR_ACIOM_Pos (0U)
+#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */
+#define DDRPHYC_ACIOCR_ACOE_Pos (1U)
+#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */
+#define DDRPHYC_ACIOCR_ACODT_Pos (2U)
+#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */
+#define DDRPHYC_ACIOCR_ACPDD_Pos (3U)
+#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */
+#define DDRPHYC_ACIOCR_ACPDR_Pos (4U)
+#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */
+#define DDRPHYC_ACIOCR_CKODT_Pos (5U)
+#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */
+#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ACIOCR_CKPDD_Pos (8U)
+#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */
+#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */
+#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ACIOCR_CKPDR_Pos (11U)
+#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */
+#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */
+#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ACIOCR_RANKODT_Pos (14U)
+#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */
+#define DDRPHYC_ACIOCR_CSPDD_Pos (18U)
+#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */
+#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U)
+#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */
+#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */
+#define DDRPHYC_ACIOCR_RSTODT_Pos (26U)
+#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */
+#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */
+#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U)
+#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */
+#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */
+#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U)
+#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */
+#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */
+#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U)
+#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */
+#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */
+#define DDRPHYC_ACIOCR_ACSR_Pos (30U)
+#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */
+#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */
+#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_DXCCR register *****************/
+#define DDRPHYC_DXCCR_DXODT_Pos (0U)
+#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */
+#define DDRPHYC_DXCCR_DXIOM_Pos (1U)
+#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DXCCR_DXPDD_Pos (2U)
+#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */
+#define DDRPHYC_DXCCR_DXPDR_Pos (3U)
+#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */
+#define DDRPHYC_DXCCR_DQSRES_Pos (4U)
+#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */
+#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DXCCR_DQSNRES_Pos (8U)
+#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */
+#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DXCCR_DQSNRST_Pos (14U)
+#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */
+#define DDRPHYC_DXCCR_RVSEL_Pos (15U)
+#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */
+#define DDRPHYC_DXCCR_AWDT_Pos (16U)
+#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */
+
+/**************** Bit definition for DDRPHYC_DSGCR register *****************/
+#define DDRPHYC_DSGCR_PUREN_Pos (0U)
+#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */
+#define DDRPHYC_DSGCR_BDISEN_Pos (1U)
+#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */
+#define DDRPHYC_DSGCR_ZUEN_Pos (2U)
+#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */
+#define DDRPHYC_DSGCR_LPIOPD_Pos (3U)
+#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */
+#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U)
+#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */
+#define DDRPHYC_DSGCR_DQSGX_Pos (5U)
+#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */
+#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DSGCR_DQSGE_Pos (8U)
+#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
+#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */
+#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DSGCR_NOBUB_Pos (11U)
+#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */
+#define DDRPHYC_DSGCR_FXDLAT_Pos (12U)
+#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */
+#define DDRPHYC_DSGCR_CKEPDD_Pos (16U)
+#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */
+#define DDRPHYC_DSGCR_ODTPDD_Pos (20U)
+#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */
+#define DDRPHYC_DSGCR_NL2PD_Pos (24U)
+#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */
+#define DDRPHYC_DSGCR_NL2OE_Pos (25U)
+#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */
+#define DDRPHYC_DSGCR_TPDPD_Pos (26U)
+#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */
+#define DDRPHYC_DSGCR_TPDOE_Pos (27U)
+#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */
+#define DDRPHYC_DSGCR_CKOE_Pos (28U)
+#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */
+#define DDRPHYC_DSGCR_ODTOE_Pos (29U)
+#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */
+#define DDRPHYC_DSGCR_RSTOE_Pos (30U)
+#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */
+#define DDRPHYC_DSGCR_CKEOE_Pos (31U)
+#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */
+
+/***************** Bit definition for DDRPHYC_DCR register ******************/
+#define DDRPHYC_DCR_DDRMD_Pos (0U)
+#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */
+#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DCR_DDR8BNK_Pos (3U)
+#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */
+#define DDRPHYC_DCR_PDQ_Pos (4U)
+#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */
+#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */
+#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DCR_MPRDQ_Pos (7U)
+#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */
+#define DDRPHYC_DCR_DDRTYPE_Pos (8U)
+#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */
+#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */
+#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DCR_NOSRA_Pos (27U)
+#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */
+#define DDRPHYC_DCR_DDR2T_Pos (28U)
+#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */
+#define DDRPHYC_DCR_UDIMM_Pos (29U)
+#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */
+#define DDRPHYC_DCR_RDIMM_Pos (30U)
+#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */
+#define DDRPHYC_DCR_TPD_Pos (31U)
+#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */
+
+/**************** Bit definition for DDRPHYC_DTPR0 register *****************/
+#define DDRPHYC_DTPR0_TMRD_Pos (0U)
+#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */
+#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR0_TRTP_Pos (2U)
+#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */
+#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */
+#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR0_TWTR_Pos (5U)
+#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */
+#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR0_TRP_Pos (8U)
+#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */
+#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR0_TRCD_Pos (12U)
+#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */
+#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTPR0_TRAS_Pos (16U)
+#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */
+#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */
+#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR0_TRRD_Pos (21U)
+#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */
+#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */
+#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR0_TRC_Pos (25U)
+#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */
+#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */
+#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTPR0_TCCD_Pos (31U)
+#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */
+
+/**************** Bit definition for DDRPHYC_DTPR1 register *****************/
+#define DDRPHYC_DTPR1_TAOND_Pos (0U)
+#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
+#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR1_TRTW_Pos (2U)
+#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */
+#define DDRPHYC_DTPR1_TFAW_Pos (3U)
+#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
+#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */
+#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR1_TMOD_Pos (9U)
+#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */
+#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR1_TRTODT_Pos (11U)
+#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */
+#define DDRPHYC_DTPR1_TRFC_Pos (16U)
+#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */
+#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U)
+#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */
+#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U)
+#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */
+#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DTPR2 register *****************/
+#define DDRPHYC_DTPR2_TXS_Pos (0U)
+#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */
+#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */
+#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR2_TXP_Pos (10U)
+#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */
+#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */
+#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTPR2_TCKE_Pos (15U)
+#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */
+#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */
+#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR2_TDLLK_Pos (19U)
+#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */
+#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */
+#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/
+#define DDRPHYC_DDR3_MR0_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR0_CL0_Pos (2U)
+#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */
+#define DDRPHYC_DDR3_MR0_BT_Pos (3U)
+#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */
+#define DDRPHYC_DDR3_MR0_CL_Pos (4U)
+#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */
+#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */
+#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR0_TM_Pos (7U)
+#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */
+#define DDRPHYC_DDR3_MR0_DR_Pos (8U)
+#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */
+#define DDRPHYC_DDR3_MR0_WR_Pos (9U)
+#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DDR3_MR0_PD_Pos (12U)
+#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */
+#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U)
+#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */
+#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/
+#define DDRPHYC_DDR3_MR1_DE_Pos (0U)
+#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */
+#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U)
+#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */
+#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U)
+#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_AL_Pos (3U)
+#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */
+#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */
+#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U)
+#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */
+#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U)
+#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U)
+#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */
+#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U)
+#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U)
+#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */
+#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U)
+#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */
+#define DDRPHYC_DDR3_MR1_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_BT_Pos (3U)
+#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */
+#define DDRPHYC_DDR3_MR1_WC_Pos (4U)
+#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */
+#define DDRPHYC_DDR3_MR1_NWR_Pos (5U)
+#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR1_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_NWR_Pos (5U)
+#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/
+#define DDRPHYC_DDR3_MR2_PASR_Pos (0U)
+#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */
+#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_CWL_Pos (3U)
+#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */
+#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR2_ASR_Pos (6U)
+#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */
+#define DDRPHYC_DDR3_MR2_SRT_Pos (7U)
+#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */
+#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U)
+#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */
+#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U)
+#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */
+#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U)
+#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */
+#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U)
+#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+#define DDRPHYC_DDR3_MR2_WL_Pos (6U)
+#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+#define DDRPHYC_DDR3_MR2_WR_Pos (7U)
+#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/
+#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U)
+#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */
+#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR3_MPR_Pos (2U)
+#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */
+
+/**************** Bit definition for DDRPHYC_ODTCR register *****************/
+#define DDRPHYC_ODTCR_RDODT_Pos (0U)
+#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */
+#define DDRPHYC_ODTCR_WRODT_Pos (16U)
+#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */
+
+/***************** Bit definition for DDRPHYC_DTAR register *****************/
+#define DDRPHYC_DTAR_DTCOL_Pos (0U)
+#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */
+#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */
+#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTAR_DTROW_Pos (12U)
+#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */
+#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */
+#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTAR_DTBANK_Pos (28U)
+#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */
+#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */
+#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTAR_DTMPR_Pos (31U)
+#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */
+
+/**************** Bit definition for DDRPHYC_DTDR0 register *****************/
+#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U)
+#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */
+#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U)
+#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */
+#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U)
+#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U)
+#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */
+#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_DTDR1 register *****************/
+#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U)
+#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */
+#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U)
+#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */
+#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U)
+#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U)
+#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */
+#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_GPR0 register *****************/
+#define DDRPHYC_GPR0_GPR0_Pos (0U)
+#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */
+#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */
+#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */
+#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */
+#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */
+#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */
+#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */
+#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */
+#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */
+#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */
+#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */
+#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */
+#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */
+#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */
+#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */
+#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */
+#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */
+#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */
+#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */
+#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */
+#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */
+#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */
+#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */
+#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */
+#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */
+#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_GPR1 register *****************/
+#define DDRPHYC_GPR1_GPR1_Pos (0U)
+#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */
+#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */
+#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */
+#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */
+#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */
+#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */
+#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */
+#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */
+#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */
+#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */
+#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */
+#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */
+#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */
+#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */
+#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */
+#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */
+#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */
+#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */
+#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */
+#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */
+#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */
+#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */
+#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */
+#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */
+#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */
+#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */
+#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */
+#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */
+#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */
+#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/
+#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U)
+#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */
+#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */
+#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */
+#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U)
+#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */
+#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */
+#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U)
+#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */
+#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */
+#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U)
+#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */
+#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U)
+#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */
+
+/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/
+#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U)
+#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */
+#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */
+#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */
+
+/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/
+#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U)
+#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */
+#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */
+#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */
+#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U)
+#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */
+#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U)
+#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */
+
+/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/
+#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U)
+#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
+#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */
+#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U)
+#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
+#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */
+#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0SR1_OPD_Pos (4U)
+#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */
+#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */
+#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0SR1_OPU_Pos (6U)
+#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */
+#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */
+#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */
+
+/**************** Bit definition for DDRPHYC_DX0GCR register ****************/
+#define DDRPHYC_DX0GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX0GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX0GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX0GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX0GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX0GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX0GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX0GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX0GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/
+#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX0GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/
+#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/
+#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/
+#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/
+#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX1GCR register ****************/
+#define DDRPHYC_DX1GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX1GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX1GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX1GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX1GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX1GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX1GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX1GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX1GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/
+#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX1GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/
+#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/
+#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/
+#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/
+#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX2GCR register ****************/
+#define DDRPHYC_DX2GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX2GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX2GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX2GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX2GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX2GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX2GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX2GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX2GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/
+#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX2GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/
+#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/
+#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/
+#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/
+#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX3GCR register ****************/
+#define DDRPHYC_DX3GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX3GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX3GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX3GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX3GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX3GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX3GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX3GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX3GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/
+#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX3GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/
+#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/
+#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/
+#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/
+#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/******************************************************************************/
+/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
@@ -16656,6 +21460,7 @@
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
/******************************************************************************/
/* */
/* Inter-Processor Communication Controller (IPCC) */
@@ -17337,7 +22142,7 @@
#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
#define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
#define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
-#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */
+#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
#define MDMA_CTCR_DBURST_Pos (15U)
#define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
@@ -18218,766 +23023,2333 @@
/* */
/******************************************************************************/
/******************** Bit definition for RCC_TZCR register********************/
-#define RCC_TZCR_TZEN_Pos (0U)
-#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
-#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/
-#define RCC_TZCR_MCKPROT_Pos (1U)
-#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
-#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/
+#define RCC_TZCR_TZEN_Pos (0U)
+#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
+#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */
+#define RCC_TZCR_MCKPROT_Pos (1U)
+#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
+#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */
-/******************** Bit definition for RCC_OCENSETR register********************/
-#define RCC_OCENSETR_HSION_Pos (0U)
-#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/
-#define RCC_OCENSETR_HSIKERON_Pos (1U)
-#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
-#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_CSION_Pos (4U)
-#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
-#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/
-#define RCC_OCENSETR_CSIKERON_Pos (5U)
-#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
-#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_DIGBYP_Pos (7U)
-#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */
-#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/
-#define RCC_OCENSETR_HSEON_Pos (8U)
-#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
-#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/
-#define RCC_OCENSETR_HSEKERON_Pos (9U)
-#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
-#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_HSEBYP_Pos (10U)
-#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
-#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/
-#define RCC_OCENSETR_HSECSSON_Pos (11U)
-#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
-#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/
+/***************** Bit definition for RCC_OCENSETR register *****************/
+#define RCC_OCENSETR_HSION_Pos (0U)
+#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */
+#define RCC_OCENSETR_HSIKERON_Pos (1U)
+#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */
+#define RCC_OCENSETR_CSION_Pos (4U)
+#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */
+#define RCC_OCENSETR_CSIKERON_Pos (5U)
+#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */
+#define RCC_OCENSETR_DIGBYP_Pos (7U)
+#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */
+#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */
+#define RCC_OCENSETR_HSEON_Pos (8U)
+#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */
+#define RCC_OCENSETR_HSEKERON_Pos (9U)
+#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */
+#define RCC_OCENSETR_HSEBYP_Pos (10U)
+#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */
+#define RCC_OCENSETR_HSECSSON_Pos (11U)
+#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
+#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */
-/******************** Bit definition for RCC_OCENCLRR register********************/
-#define RCC_OCENCLRR_HSION_Pos (0U)
-#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/
-#define RCC_OCENCLRR_HSIKERON_Pos (1U)
-#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
-#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/
-#define RCC_OCENCLRR_CSION_Pos (4U)
-#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
-#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/
-#define RCC_OCENCLRR_CSIKERON_Pos (5U)
-#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
-#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/
-#define RCC_OCENCLRR_DIGBYP_Pos (7U)
-#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */
-#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/
-#define RCC_OCENCLRR_HSEON_Pos (8U)
-#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
-#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/
-#define RCC_OCENCLRR_HSEKERON_Pos (9U)
-#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
-#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/
-#define RCC_OCENCLRR_HSEBYP_Pos (10U)
-#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
-#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/
+/***************** Bit definition for RCC_OCENCLRR register *****************/
+#define RCC_OCENCLRR_HSION_Pos (0U)
+#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */
+#define RCC_OCENCLRR_HSIKERON_Pos (1U)
+#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */
+#define RCC_OCENCLRR_CSION_Pos (4U)
+#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */
+#define RCC_OCENCLRR_CSIKERON_Pos (5U)
+#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */
+#define RCC_OCENCLRR_DIGBYP_Pos (7U)
+#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */
+#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */
+#define RCC_OCENCLRR_HSEON_Pos (8U)
+#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */
+#define RCC_OCENCLRR_HSEKERON_Pos (9U)
+#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */
+#define RCC_OCENCLRR_HSEBYP_Pos (10U)
+#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */
-/******************** Bit definition for RCC_OCRDYR register********************/
-#define RCC_OCRDYR_HSIRDY_Pos (0U)
-#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */
-#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/
-#define RCC_OCRDYR_HSIDIVRDY_Pos (2U)
-#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
-#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/
-#define RCC_OCRDYR_CSIRDY_Pos (4U)
-#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */
-#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/
-#define RCC_OCRDYR_HSERDY_Pos (8U)
-#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */
-#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/
-#define RCC_OCRDYR_AXICKRDY_Pos (24U)
-#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
-#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/
-#define RCC_OCRDYR_CKREST_Pos (25U)
-#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */
-#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/
+/***************** Bit definition for RCC_HSICFGR register ******************/
+#define RCC_HSICFGR_HSIDIV_Pos (0U)
+#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */
+#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSITRIM_Pos (8U)
+#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */
+#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */
+#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */
+#define RCC_HSICFGR_HSICAL_Pos (16U)
+#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */
+#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */
+#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */
+#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */
+#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */
+#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */
+#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */
+#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */
+#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */
+#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */
+#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */
-/******************** Bit definition for RCC_DBGCFGR register********************/
-#define RCC_DBGCFGR_TRACEDIV_Pos (0U)
-#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
-#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/
-#define RCC_DBGCFGR_DBGCKEN_Pos (8U)
-#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
-#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/
-#define RCC_DBGCFGR_TRACECKEN_Pos (9U)
-#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
-#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/
-#define RCC_DBGCFGR_DBGRST_Pos (12U)
-#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
-#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/
+/***************** Bit definition for RCC_CSICFGR register ******************/
+#define RCC_CSICFGR_CSITRIM_Pos (8U)
+#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */
+#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_CSICFGR_CSICAL_Pos (16U)
+#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */
+#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */
+#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */
+#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */
+#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */
+#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */
+#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */
+#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */
+#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */
-/******************** Bit definition for RCC_HSICFGR register********************/
-#define RCC_HSICFGR_HSIDIV_Pos (0U)
-#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos)
-#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/
-#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/
-#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */
-#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */
-#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */
+/***************** Bit definition for RCC_MPCKSELR register *****************/
+#define RCC_MPCKSELR_MPUSRC_Pos (0U)
+#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */
+#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
+#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
+#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
+#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */
-#define RCC_HSICFGR_HSITRIM_Pos (8U)
-#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos)
-#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/
+/**************** Bit definition for RCC_ASSCKSELR register *****************/
+#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
+#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
+#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
+#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
+#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
+#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
+#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */
-#define RCC_HSICFGR_HSICAL_Pos (16U)
-#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos)
-#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/
+/**************** Bit definition for RCC_RCK12SELR register *****************/
+#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
+#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */
+#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
+#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */
-/******************** Bit definition for RCC_CSICFGR register********************/
-#define RCC_CSICFGR_CSITRIM_Pos (8U)
-#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos)
-#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/
+/***************** Bit definition for RCC_MPCKDIVR register *****************/
+#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
+#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */
+#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
+#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
+#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
+#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
+#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */
-#define RCC_CSICFGR_CSICAL_Pos (16U)
-#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos)
-#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/
+/***************** Bit definition for RCC_AXIDIVR register ******************/
+#define RCC_AXIDIVR_AXIDIV_Pos (0U)
+#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */
+#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
+#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
+#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
+#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
+#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */
-/******************** Bit definition for RCC_MCO1CFGR register********************/
-#define RCC_MCO1CFGR_MCO1SEL_Pos (0U)
-#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
-#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/
-#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */
-#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
-#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
-#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */
-#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
+/***************** Bit definition for RCC_APB4DIVR register *****************/
+#define RCC_APB4DIVR_APB4DIV_Pos (0U)
+#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */
+#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
+#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */
-#define RCC_MCO1CFGR_MCO1DIV_Pos (4U)
-#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
-#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/
-#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */
-#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
-#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
-#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */
-#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
-#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */
-#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */
-#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */
-#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
-#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */
-#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */
-#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */
-#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */
-#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */
-#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */
-#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
+/***************** Bit definition for RCC_APB5DIVR register *****************/
+#define RCC_APB5DIVR_APB5DIV_Pos (0U)
+#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */
+#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
+#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */
-#define RCC_MCO1CFGR_MCO1ON_Pos (12U)
-#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
-#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/
+/***************** Bit definition for RCC_RTCDIVR register ******************/
+#define RCC_RTCDIVR_RTCDIV_Pos (0U)
+#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
+#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */
+#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */
+#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */
+#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */
+#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */
+#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */
+#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */
-/******************** Bit definition for RCC_MCO2CFGR register********************/
-#define RCC_MCO2CFGR_MCO2SEL_Pos (0U)
-#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
-#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/
-#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */
-#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
-#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
-#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */
-#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
-#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */
+/**************** Bit definition for RCC_MSSCKSELR register *****************/
+#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
+#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */
+#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
+#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
+#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
+#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */
-#define RCC_MCO2CFGR_MCO2DIV_Pos (4U)
-#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
-#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/
-#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */
-#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
-#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
-#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */
-#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
-#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */
-#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */
-#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */
-#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
-#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */
-#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */
-#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */
-#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */
-#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */
-#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */
-#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
+/****************** Bit definition for RCC_PLL1CR register ******************/
+#define RCC_PLL1CR_PLLON_Pos (0U)
+#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */
+#define RCC_PLL1CR_PLL1RDY_Pos (1U)
+#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */
+#define RCC_PLL1CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */
+#define RCC_PLL1CR_DIVPEN_Pos (4U)
+#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */
+#define RCC_PLL1CR_DIVQEN_Pos (5U)
+#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */
+#define RCC_PLL1CR_DIVREN_Pos (6U)
+#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */
-#define RCC_MCO2CFGR_MCO2ON_Pos (12U)
-#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
-#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/
+/**************** Bit definition for RCC_PLL1CFGR1 register *****************/
+#define RCC_PLL1CFGR1_DIVN_Pos (0U)
+#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */
+#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CFGR1_DIVM1_Pos (16U)
+#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
+#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */
+#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */
-/******************** Bit definition for RCC_MPCKSELR register********************/
-#define RCC_MPCKSELR_MPUSRC_Pos (0U)
-#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
-#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/
-#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */
-#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
-#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
-#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_PLL1CFGR2 register *****************/
+#define RCC_PLL1CFGR2_DIVP_Pos (0U)
+#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */
+#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */
+#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL1CFGR2_DIVR_Pos (16U)
+#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */
+#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */
+/**************** Bit definition for RCC_PLL1FRACR register *****************/
+#define RCC_PLL1FRACR_FRACV_Pos (3U)
+#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */
+#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL1FRACR_FRACLE_Pos (16U)
+#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */
-#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
-#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/
+/***************** Bit definition for RCC_PLL1CSGR register *****************/
+#define RCC_PLL1CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */
+#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */
+#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */
+#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */
+#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */
+#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */
+#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */
+#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */
+#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */
+#define RCC_PLL1CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */
+#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */
+#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */
+#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */
+#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */
+#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */
+#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */
+#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */
+#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */
-/******************** Bit definition for RCC_ASSCKSELR register********************/
-#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
-#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
-#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/
-#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */
-#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
-#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
-#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */
-#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
-#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */
-#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */
-#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+/****************** Bit definition for RCC_PLL2CR register ******************/
+#define RCC_PLL2CR_PLLON_Pos (0U)
+#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */
+#define RCC_PLL2CR_PLL2RDY_Pos (1U)
+#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+#define RCC_PLL2CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */
+#define RCC_PLL2CR_DIVPEN_Pos (4U)
+#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */
+#define RCC_PLL2CR_DIVQEN_Pos (5U)
+#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */
+#define RCC_PLL2CR_DIVREN_Pos (6U)
+#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */
-#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
-#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/
+/**************** Bit definition for RCC_PLL2CFGR1 register *****************/
+#define RCC_PLL2CFGR1_DIVN_Pos (0U)
+#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */
+#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
+#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
+#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */
+#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */
-/******************** Bit definition for RCC_MSSCKSELR register********************/
-#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
-#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
-#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/
-#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */
-#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
-#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
-#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_PLL2CFGR2 register *****************/
+#define RCC_PLL2CFGR2_DIVP_Pos (0U)
+#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */
+#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */
+#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL2CFGR2_DIVR_Pos (16U)
+#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */
+#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */
-#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
-#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/
+/**************** Bit definition for RCC_PLL2FRACR register *****************/
+#define RCC_PLL2FRACR_FRACV_Pos (3U)
+#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */
+#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL2FRACR_FRACLE_Pos (16U)
+#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */
-/******************** Bit definition for RCC_RCK12SELR register********************/
-#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
-#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/
-#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */
-#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */
-#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */
-#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */
+/***************** Bit definition for RCC_PLL2CSGR register *****************/
+#define RCC_PLL2CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */
+#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */
+#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */
+#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */
+#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */
+#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */
+#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */
+#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */
+#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */
+#define RCC_PLL2CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */
+#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */
+#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */
+#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */
+#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */
+#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */
+#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */
+#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */
+#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */
-#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
-#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/
+/*************** Bit definition for RCC_I2C46CKSELR register ****************/
+#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U)
+#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */
+#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RCK3SELR register********************/
-#define RCC_RCK3SELR_PLL3SRC_Pos (0U)
-#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/
-#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_SPI6CKSELR register ****************/
+#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U)
+#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */
+#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
-#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U)
-#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/
+/*************** Bit definition for RCC_UART1CKSELR register ****************/
+#define RCC_UART1CKSELR_UART1SRC_Pos (0U)
+#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */
+#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RCK4SELR register********************/
-#define RCC_RCK4SELR_PLL4SRC_Pos (0U)
-#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/
-#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_RNG1CKSELR register ****************/
+#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U)
+#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
+#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */
+#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
+#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U)
-#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/
+/**************** Bit definition for RCC_CPERCKSELR register ****************/
+#define RCC_CPERCKSELR_CKPERSRC_Pos (0U)
+#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
+#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */
+#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
+#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_TIMG1PRER register********************/
-#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U)
-#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
-#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/
-#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */
- /*corresponding to a division by 1 or 2, else it is equal to
- 2 x Fck_pclk1 (default after reset)*/
-#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is
- corresponding to division by 1, 2 or 4, else it is equal to
- 4 x Fck_pclk1 */
+/*************** Bit definition for RCC_STGENCKSELR register ****************/
+#define RCC_STGENCKSELR_STGENSRC_Pos (0U)
+#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
+#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */
+#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
+#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
-#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U)
-#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
-#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/
+/***************** Bit definition for RCC_DDRITFCR register *****************/
+#define RCC_DDRITFCR_DDRC1EN_Pos (0U)
+#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */
+#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */
+#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U)
+#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */
+#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRC2EN_Pos (2U)
+#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */
+#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */
+#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U)
+#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */
+#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U)
+#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */
+#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */
+#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U)
+#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U)
+#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */
+#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */
+#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U)
+#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */
+#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */
+#define RCC_DDRITFCR_AXIDCGEN_Pos (8U)
+#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */
+#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */
+#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U)
+#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */
+#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */
+#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U)
+#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
+#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */
+#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
+#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
+#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
+#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U)
+#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */
+#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */
+#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U)
+#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */
+#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */
+#define RCC_DDRITFCR_DDRCORERST_Pos (16U)
+#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */
+#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */
+#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U)
+#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */
+#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */
+#define RCC_DDRITFCR_DPHYRST_Pos (18U)
+#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */
+#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */
+#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U)
+#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */
+#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */
+#define RCC_DDRITFCR_DDRCKMOD_Pos (20U)
+#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
+#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */
+#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
+#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
+#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */
+#define RCC_DDRITFCR_GSKPMOD_Pos (23U)
+#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */
+#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */
+#define RCC_DDRITFCR_GSKPCTRL_Pos (24U)
+#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */
+#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */
+#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U)
+#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */
+#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */
+#define RCC_DDRITFCR_GSKP_DUR_Pos (28U)
+#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */
+#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */
+#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */
+#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */
+#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */
+#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */
-/******************** Bit definition for RCC_TIMG2PRER register********************/
-#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U)
-#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
-#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/
-#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */
- /*corresponding to a division by 1 or 2, else it is equal
- to 2 x Fck_pclk2 (default after reset)*/
-#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is
- corresponding to division by 1, 2 or 4, else it is equal to
- 4 x Fck_pclk2 */
+/**************** Bit definition for RCC_MP_BOOTCR register *****************/
+#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U)
+#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */
+#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U)
+#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */
+
+/*************** Bit definition for RCC_MP_SREQSETR register ****************/
+#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */
+#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */
+
+/*************** Bit definition for RCC_MP_SREQCLRR register ****************/
+#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */
+#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */
+
+/****************** Bit definition for RCC_MP_GCR register ******************/
+#define RCC_MP_GCR_BOOT_MCU_Pos (0U)
+#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
+#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */
+
+/**************** Bit definition for RCC_MP_APRSTCR register ****************/
+#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U)
+#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */
+#define RCC_MP_APRSTCR_RSTTO_Pos (8U)
+#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */
+#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */
+#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */
+#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */
+#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */
+#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */
+#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */
+#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */
+
+/**************** Bit definition for RCC_MP_APRSTSR register ****************/
+#define RCC_MP_APRSTSR_RSTTOV_Pos (8U)
+#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */
+#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */
+#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */
+#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */
+#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */
+#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */
+#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */
+#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */
+#define RCC_BDCR_LSEBYP_Pos (1U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */
+#define RCC_BDCR_LSERDY_Pos (2U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */
+#define RCC_BDCR_DIGBYP_Pos (3U)
+#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */
+#define RCC_BDCR_LSEDRV_Pos (4U)
+#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */
+#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON_Pos (8U)
+#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */
+#define RCC_BDCR_LSECSSD_Pos (9U)
+#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */
+#define RCC_BDCR_RTCSRC_Pos (16U)
+#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
+#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */
+#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */
+#define RCC_BDCR_RTCCKEN_Pos (20U)
+#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */
+#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_VSWRST_Pos (31U)
+#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */
+
+/***************** Bit definition for RCC_RDLSICR register ******************/
+#define RCC_RDLSICR_LSION_Pos (0U)
+#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */
+#define RCC_RDLSICR_LSIRDY_Pos (1U)
+#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */
+#define RCC_RDLSICR_MRD_Pos (16U)
+#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */
+#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */
+#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */
+#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */
+#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */
+#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */
+#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */
+#define RCC_RDLSICR_EADLY_Pos (24U)
+#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */
+#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */
+#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */
+#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */
+#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */
+#define RCC_RDLSICR_SPARE_Pos (27U)
+#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */
+#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */
+#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */
+#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */
+#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */
+#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */
+#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for RCC_APB4RSTSETR register ****************/
+#define RCC_APB4RSTSETR_LTDCRST_Pos (0U)
+#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */
+#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */
+#define RCC_APB4RSTSETR_DSIRST_Pos (4U)
+#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */
+#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */
+#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U)
+#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */
+#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */
+#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U)
+#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */
+
+/*************** Bit definition for RCC_APB4RSTCLRR register ****************/
+#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U)
+#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */
+#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */
+#define RCC_APB4RSTCLRR_DSIRST_Pos (4U)
+#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */
+#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */
+#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U)
+#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */
+#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */
+#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U)
+#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */
+
+/*************** Bit definition for RCC_APB5RSTSETR register ****************/
+#define RCC_APB5RSTSETR_SPI6RST_Pos (0U)
+#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */
+#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */
+#define RCC_APB5RSTSETR_I2C4RST_Pos (2U)
+#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */
+#define RCC_APB5RSTSETR_I2C6RST_Pos (3U)
+#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */
+#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */
+#define RCC_APB5RSTSETR_USART1RST_Pos (4U)
+#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */
+#define RCC_APB5RSTSETR_STGENRST_Pos (20U)
+#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */
+#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */
+
+/*************** Bit definition for RCC_APB5RSTCLRR register ****************/
+#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U)
+#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */
+#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */
+#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U)
+#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */
+#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U)
+#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */
+#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */
+#define RCC_APB5RSTCLRR_USART1RST_Pos (4U)
+#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */
+#define RCC_APB5RSTCLRR_STGENRST_Pos (20U)
+#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */
+#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */
+
+/*************** Bit definition for RCC_AHB5RSTSETR register ****************/
+#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U)
+#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */
+#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U)
+#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */
+#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U)
+#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */
+#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U)
+#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */
+#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U)
+#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */
+
+/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/
+#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U)
+#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */
+#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U)
+#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */
+#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U)
+#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */
+#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U)
+#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */
+#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U)
+#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */
+
+/*************** Bit definition for RCC_AHB6RSTSETR register ****************/
+#define RCC_AHB6RSTSETR_GPURST_Pos (5U)
+#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */
+#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */
+#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U)
+#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */
+#define RCC_AHB6RSTSETR_FMCRST_Pos (12U)
+#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */
+#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U)
+#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */
+#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U)
+#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */
+#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U)
+#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */
+#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */
+#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U)
+#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */
+#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */
+#define RCC_AHB6RSTSETR_USBHRST_Pos (24U)
+#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */
+#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */
+
+/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/
+#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U)
+#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */
+#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U)
+#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */
+#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U)
+#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */
+#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U)
+#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */
+#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U)
+#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */
+#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */
+#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U)
+#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */
+#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */
+#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U)
+#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */
+#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */
+
+/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/
+#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U)
+#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */
+#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */
+
+/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/
+#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U)
+#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */
+#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */
+
+/************** Bit definition for RCC_MP_APB4ENSETR register ***************/
+#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U)
+#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U)
+#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U)
+#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U)
+#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */
+#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U)
+#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U)
+#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/
+#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U)
+#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U)
+#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U)
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U)
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */
+#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U)
+#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U)
+#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */
+
+/************** Bit definition for RCC_MP_APB5ENSETR register ***************/
+#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U)
+#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U)
+#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U)
+#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U)
+#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U)
+#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */
+#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U)
+#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */
+#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U)
+#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */
+#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U)
+#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */
+#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U)
+#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U)
+#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/
+#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U)
+#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U)
+#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U)
+#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U)
+#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U)
+#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */
+#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U)
+#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */
+#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U)
+#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */
+#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U)
+#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U)
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */
+#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U)
+#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U)
+#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */
+
+/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/
+#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U)
+#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U)
+#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U)
+#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U)
+#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U)
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
+#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U)
+#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */
+
+/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/
+#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U)
+#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U)
+#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U)
+#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U)
+#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U)
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
+#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U)
+#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */
+
+/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/
+#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U)
+#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U)
+#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U)
+#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */
+#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U)
+#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */
+#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U)
+#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */
+#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U)
+#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U)
+#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U)
+#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U)
+#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U)
+#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U)
+#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/
+#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U)
+#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U)
+#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U)
+#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */
+#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U)
+#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */
+#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U)
+#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */
+#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U)
+#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U)
+#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U)
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U)
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U)
+#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U)
+#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */
+
+/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/
+#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+
+/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB4ENSETR register ***************/
+#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U)
+#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U)
+#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U)
+#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U)
+#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U)
+#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/
+#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U)
+#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U)
+#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U)
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U)
+#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U)
+#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */
+
+/************** Bit definition for RCC_MC_APB5ENSETR register ***************/
+#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U)
+#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U)
+#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U)
+#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U)
+#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U)
+#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */
+#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U)
+#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */
+#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U)
+#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */
+#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U)
+#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U)
+#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U)
+#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/
+#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U)
+#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U)
+#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U)
+#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U)
+#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U)
+#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */
+#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U)
+#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */
+#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U)
+#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */
+#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U)
+#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U)
+#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U)
+#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */
+
+/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/
+#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U)
+#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U)
+#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U)
+#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U)
+#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U)
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
-#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U)
-#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
-#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/
+/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/
+#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U)
+#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U)
+#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U)
+#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U)
+#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U)
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
-/******************** Bit definition for RCC_RTCDIVR register********************/
-#define RCC_RTCDIVR_RTCDIV_Pos (0U)
-#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
-#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/
-#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos)
+/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/
+#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U)
+#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U)
+#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U)
+#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */
+#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U)
+#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */
+#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U)
+#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */
+#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U)
+#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U)
+#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U)
+#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U)
+#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U)
+#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U)
+#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */
-#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/
+/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/
+#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U)
+#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U)
+#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U)
+#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */
+#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U)
+#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */
+#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U)
+#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */
+#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U)
+#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U)
+#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U)
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U)
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U)
+#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U)
+#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */
-/******************** Bit definition for RCC_MPCKDIVR register********************/
-#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
-#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
-#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/
-#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */
-#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
-#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
-#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */
-#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
-#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */
-#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */
-#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_APB4LPENSETR register **************/
+#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U)
+#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U)
+#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U)
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U)
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U)
+#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U)
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */
-#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
-#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/
+/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U)
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U)
+#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U)
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U)
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U)
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U)
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */
-/******************** Bit definition for RCC_AXIDIVR register********************/
-#define RCC_AXIDIVR_AXIDIV_Pos (0U)
-#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
-#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/
-#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */
-#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
-#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
-#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */
-#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
-#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */
-#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */
-#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_APB5LPENSETR register **************/
+#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U)
+#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U)
+#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U)
+#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U)
+#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U)
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U)
+#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U)
+#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U)
+#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U)
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U)
+#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U)
+#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U)
+#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */
-#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
-#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/
+/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U)
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U)
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U)
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U)
+#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U)
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U)
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U)
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U)
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U)
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U)
+#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U)
+#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U)
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */
-/******************** Bit definition for RCC_APB4DIVR register********************/
-#define RCC_APB4DIVR_APB4DIV_Pos (0U)
-#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */
-#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
-#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */
-#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */
-#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U)
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U)
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U)
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U)
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
-#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/
+/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U)
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U)
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U)
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U)
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-/******************** Bit definition for RCC_APB5DIVR register********************/
-#define RCC_APB5DIVR_APB5DIV_Pos (0U)
-#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/
-#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
-#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */
-#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */
-#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/
+#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U)
+#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U)
+#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U)
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U)
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U)
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U)
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U)
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U)
+#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U)
+#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U)
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U)
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U)
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U)
+#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
-#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/
+/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U)
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U)
+#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U)
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U)
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U)
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U)
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U)
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U)
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U)
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U)
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U)
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U)
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U)
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-/******************** Bit definition for RCC_MCUDIVR register********************/
-#define RCC_MCUDIVR_MCUDIV_Pos (0U)
-#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
-#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/
-#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */
-#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
-#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
-#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */
-#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
-#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */
-#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */
-#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */
-#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
-#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */
-/* @note others: ck_mcuss divided by 512 */
+/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U)
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
-#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U)
-#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/
-/******************** Bit definition for RCC_APB1DIVR register********************/
-#define RCC_APB1DIVR_APB1DIV_Pos (0U)
-#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/
-#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
-/* @note others: ck_hclk/16 */
+/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U)
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
-#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U)
-#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/
+/************* Bit definition for RCC_MC_APB4LPENSETR register **************/
+#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U)
+#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U)
+#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U)
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U)
+#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U)
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */
-/******************** Bit definition for RCC_APB2DIV register********************/
-#define RCC_APB2DIVR_APB2DIV_Pos (0U)
-#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/
-#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
-/* @note others: ck_hclk/16 */
+/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U)
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U)
+#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U)
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U)
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U)
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */
-#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U)
-#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/
+/************* Bit definition for RCC_MC_APB5LPENSETR register **************/
+#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U)
+#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U)
+#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U)
+#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U)
+#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U)
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U)
+#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U)
+#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U)
+#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U)
+#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U)
+#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U)
+#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */
-/******************** Bit definition for RCC_APB3DIV register********************/
-#define RCC_APB3DIVR_APB3DIV_Pos (0U)
-#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/
-#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */
-/* @note others: ck_hclk/16 */
+/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/
+#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U)
+#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U)
+#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U)
+#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U)
+#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U)
+#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U)
+#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U)
+#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U)
+#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U)
+#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U)
+#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U)
+#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */
-#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U)
-#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/
+/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/
+#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U)
+#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U)
+#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U)
+#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U)
+#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-/******************** Bit definition for RCC_PLL1CR register********************/
-#define RCC_PLL1CR_PLLON_Pos (0U)
-#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */
-#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/
-#define RCC_PLL1CR_PLL1RDY_Pos (1U)
-#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
-#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/
-#define RCC_PLL1CR_SSCG_CTRL_Pos (2U)
-#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
-#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/
-#define RCC_PLL1CR_DIVPEN_Pos (4U)
-#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */
-#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/
-#define RCC_PLL1CR_DIVQEN_Pos (5U)
-#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */
-#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/
-#define RCC_PLL1CR_DIVREN_Pos (6U)
-#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */
-#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/
+/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/
+#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U)
+#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U)
+#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U)
+#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U)
+#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-/******************** Bit definition for RCC_PLL1CFGR1 register********************/
-#define RCC_PLL1CFGR1_DIVN_Pos (0U)
-#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
-#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/
-/* @note Valid division rations for DIVN: between 25 and 100 */
-#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
-#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
-#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
+/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/
+#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U)
+#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U)
+#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U)
+#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U)
+#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U)
+#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U)
+#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U)
+#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U)
+#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U)
+#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U)
+#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U)
+#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U)
+#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U)
+#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-#define RCC_PLL1CFGR1_DIVM1_Pos (16U)
-#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
-#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/
+/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/
+#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U)
+#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U)
+#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U)
+#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U)
+#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U)
+#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U)
+#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U)
+#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U)
+#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U)
+#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U)
+#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U)
+#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U)
+#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U)
+#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-/* @note "y" division factor must be an integer value between 1 and 64 */
-#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/
+#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */
+#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */
+#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */
+#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */
+#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */
+#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */
+#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */
+#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */
+#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U)
+#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */
+#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U)
+#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */
-/******************** Bit definition for RCC_PLL1CFGR2 register********************/
-/* @TODO To compleate as needed */
-#define RCC_PLL1CFGR2_DIVP_Pos (0U)
-#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
-#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/
-#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */
-#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
-#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
+/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/
+#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U)
+#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */
+#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */
+#define RCC_MP_GRSTCSETR_MCURST_Pos (1U)
+#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */
+#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */
+#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U)
+#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */
+#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */
+#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U)
+#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */
+#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */
-#define RCC_PLL1CFGR2_DIVQ_Pos (8U)
-#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
-#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/
-#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */
-#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
-#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/
+#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */
+#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */
+#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */
+#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */
+#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */
+#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */
+#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */
+#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */
+#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U)
+#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */
+#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */
+#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */
+#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U)
+#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */
+#define RCC_MP_RSTSCLRR_SPARE_Pos (15U)
+#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */
+#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */
-#define RCC_PLL1CFGR2_DIVR_Pos (16U)
-#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
-#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/
-#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */
-#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
-#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U)
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U)
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */
-/******************** Bit definition for RCC_PLL1FRACR register********************/
-#define RCC_PLL1FRACR_FRACV_Pos (3U)
-#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
-#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/
-/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U)
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U)
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */
-#define RCC_PLL1FRACR_FRACLE_Pos (16U)
-#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
-#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/
+/***************** Bit definition for RCC_MP_CIER register ******************/
+#define RCC_MP_CIER_LSIRDYIE_Pos (0U)
+#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */
+#define RCC_MP_CIER_LSERDYIE_Pos (1U)
+#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */
+#define RCC_MP_CIER_HSIRDYIE_Pos (2U)
+#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */
+#define RCC_MP_CIER_HSERDYIE_Pos (3U)
+#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */
+#define RCC_MP_CIER_CSIRDYIE_Pos (4U)
+#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */
+#define RCC_MP_CIER_PLL1DYIE_Pos (8U)
+#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
+#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */
+#define RCC_MP_CIER_PLL2DYIE_Pos (9U)
+#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
+#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */
+#define RCC_MP_CIER_PLL3DYIE_Pos (10U)
+#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
+#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */
+#define RCC_MP_CIER_PLL4DYIE_Pos (11U)
+#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
+#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */
+#define RCC_MP_CIER_LSECSSIE_Pos (16U)
+#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
+#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */
+#define RCC_MP_CIER_WKUPIE_Pos (20U)
+#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */
+#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */
-/******************** Bit definition for RCC_PLL1CSGR register********************/
-#define RCC_PLL1CSGR_MOD_PER_Pos (0U)
-#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
-#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/
-#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U)
-#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
-#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
-#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U)
-#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
-#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
-#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U)
-#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
-#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
-#define RCC_PLL1CSGR_INC_STEP_Pos (16U)
-#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
-#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/
+/***************** Bit definition for RCC_MP_CIFR register ******************/
+#define RCC_MP_CIFR_LSIRDYF_Pos (0U)
+#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */
+#define RCC_MP_CIFR_LSERDYF_Pos (1U)
+#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */
+#define RCC_MP_CIFR_HSIRDYF_Pos (2U)
+#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */
+#define RCC_MP_CIFR_HSERDYF_Pos (3U)
+#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */
+#define RCC_MP_CIFR_CSIRDYF_Pos (4U)
+#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */
+#define RCC_MP_CIFR_PLL1DYF_Pos (8U)
+#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
+#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */
+#define RCC_MP_CIFR_PLL2DYF_Pos (9U)
+#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
+#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */
+#define RCC_MP_CIFR_PLL3DYF_Pos (10U)
+#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
+#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */
+#define RCC_MP_CIFR_PLL4DYF_Pos (11U)
+#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
+#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */
+#define RCC_MP_CIFR_LSECSSF_Pos (16U)
+#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
+#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */
+#define RCC_MP_CIFR_WKUPF_Pos (20U)
+#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */
+#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */
-/******************** Bit definition for RCC_PLL2CR register********************/
-#define RCC_PLL2CR_PLLON_Pos (0U)
-#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */
-#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/
-#define RCC_PLL2CR_PLL2RDY_Pos (1U)
-#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
-#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/
-#define RCC_PLL2CR_SSCG_CTRL_Pos (2U)
-#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
-#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/
-#define RCC_PLL2CR_DIVPEN_Pos (4U)
-#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */
-#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/
-#define RCC_PLL2CR_DIVQEN_Pos (5U)
-#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */
-#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/
-#define RCC_PLL2CR_DIVREN_Pos (6U)
-#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */
-#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/
-/******************** Bit definition for RCC_PLL2CFGR1 register********************/
-#define RCC_PLL2CFGR1_DIVN_Pos (0U)
-#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
-#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/
-/* @note Valid division rations for DIVN: between 25 and 100 */
-#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
-#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
-#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
+/**************** Bit definition for RCC_PWRLPDLYCR register ****************/
+#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */
+#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */
+#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U)
+#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */
+#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */
-#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
-#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
-#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
-#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/
-/* @note "y" division factor must be an integer value between 1 and 64 */
-#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+/*************** Bit definition for RCC_MP_RSTSSETR register ****************/
+#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U)
+#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U)
+#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */
+#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U)
+#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */
+#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U)
+#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */
+#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U)
+#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */
+#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U)
+#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */
+#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U)
+#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */
+#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U)
+#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */
+#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U)
+#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */
+#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U)
+#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */
+#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */
+#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U)
+#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
+#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */
+#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U)
+#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */
+#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U)
+#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */
+#define RCC_MP_RSTSSETR_SPARE_Pos (15U)
+#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */
+#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */
-/******************** Bit definition for RCC_PLL2CFGR2 register********************/
-/* @TODO To compleate as needed */
-#define RCC_PLL2CFGR2_DIVP_Pos (0U)
-#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
-#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/
-#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */
-#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
-#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
+/***************** Bit definition for RCC_MCO1CFGR register *****************/
+#define RCC_MCO1CFGR_MCO1SEL_Pos (0U)
+#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
+#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */
+#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
+#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
+#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
+#define RCC_MCO1CFGR_MCO1DIV_Pos (4U)
+#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
+#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */
+#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
+#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
+#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
+#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
+#define RCC_MCO1CFGR_MCO1ON_Pos (12U)
+#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
+#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */
-#define RCC_PLL2CFGR2_DIVQ_Pos (8U)
-#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
-#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/
-#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */
-#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
-#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+/***************** Bit definition for RCC_MCO2CFGR register *****************/
+#define RCC_MCO2CFGR_MCO2SEL_Pos (0U)
+#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
+#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */
+#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
+#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
+#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
+#define RCC_MCO2CFGR_MCO2DIV_Pos (4U)
+#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
+#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */
+#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
+#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
+#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
+#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
+#define RCC_MCO2CFGR_MCO2ON_Pos (12U)
+#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
+#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */
-#define RCC_PLL2CFGR2_DIVR_Pos (16U)
-#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
-#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/
-#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */
-#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
-#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+/****************** Bit definition for RCC_OCRDYR register ******************/
+#define RCC_OCRDYR_HSIRDY_Pos (0U)
+#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */
+#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */
+#define RCC_OCRDYR_HSIDIVRDY_Pos (2U)
+#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
+#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */
+#define RCC_OCRDYR_CSIRDY_Pos (4U)
+#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */
+#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */
+#define RCC_OCRDYR_HSERDY_Pos (8U)
+#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */
+#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */
+#define RCC_OCRDYR_MPUCKRDY_Pos (23U)
+#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */
+#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */
+#define RCC_OCRDYR_AXICKRDY_Pos (24U)
+#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
+#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */
+#define RCC_OCRDYR_CKREST_Pos (25U)
+#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */
+#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */
-/******************** Bit definition for RCC_PLL2FRACR register********************/
-#define RCC_PLL2FRACR_FRACV_Pos (3U)
-#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
-#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/
-/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+/***************** Bit definition for RCC_DBGCFGR register ******************/
+#define RCC_DBGCFGR_TRACEDIV_Pos (0U)
+#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
+#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */
+#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */
+#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */
+#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */
+#define RCC_DBGCFGR_DBGCKEN_Pos (8U)
+#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
+#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */
+#define RCC_DBGCFGR_TRACECKEN_Pos (9U)
+#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
+#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */
+#define RCC_DBGCFGR_DBGRST_Pos (12U)
+#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
+#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */
-#define RCC_PLL2FRACR_FRACLE_Pos (16U)
-#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
-#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/
+/***************** Bit definition for RCC_RCK3SELR register *****************/
+#define RCC_RCK3SELR_PLL3SRC_Pos (0U)
+#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */
+#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U)
+#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */
-/******************** Bit definition for RCC_PLL2CSGR register********************/
-#define RCC_PLL2CSGR_MOD_PER_Pos (0U)
-#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
-#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/
-#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U)
-#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
-#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
-#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U)
-#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
-#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
-#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U)
-#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
-#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
-#define RCC_PLL2CSGR_INC_STEP_Pos (16U)
-#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
-#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/
+/***************** Bit definition for RCC_RCK4SELR register *****************/
+#define RCC_RCK4SELR_PLL4SRC_Pos (0U)
+#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */
+#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U)
+#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */
-/******************** Bit definition for RCC_PLL3CR register********************/
-#define RCC_PLL3CR_PLLON_Pos (0U)
-#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */
-#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/
-#define RCC_PLL3CR_PLL3RDY_Pos (1U)
-#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */
-#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/
-#define RCC_PLL3CR_SSCG_CTRL_Pos (2U)
-#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
-#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/
-#define RCC_PLL3CR_DIVPEN_Pos (4U)
-#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */
-#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/
-#define RCC_PLL3CR_DIVQEN_Pos (5U)
-#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */
-#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/
-#define RCC_PLL3CR_DIVREN_Pos (6U)
-#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */
-#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/
+/**************** Bit definition for RCC_TIMG1PRER register *****************/
+#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U)
+#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
+#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */
+#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U)
+#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
+#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */
-/******************** Bit definition for RCC_PLL3CFGR1 register********************/
-#define RCC_PLL3CFGR1_DIVN_Pos (0U)
-#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */
-#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/
-/* @note Valid division rations for DIVN: between 25 and 200 */
-#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
-#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
-#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
+/**************** Bit definition for RCC_TIMG2PRER register *****************/
+#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U)
+#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
+#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */
+#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U)
+#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
+#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */
+/***************** Bit definition for RCC_MCUDIVR register ******************/
+#define RCC_MCUDIVR_MCUDIV_Pos (0U)
+#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
+#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */
+#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
+#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
+#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
+#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
+#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U)
+#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */
-#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
-#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
-#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */
-#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/
-/* @note "y" division factor must be an integer value between 1 and 64 */
-#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+/***************** Bit definition for RCC_APB1DIVR register *****************/
+#define RCC_APB1DIVR_APB1DIV_Pos (0U)
+#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */
+#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U)
+#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */
-#define RCC_PLL3CFGR1_IFRGE_Pos (24U)
-#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */
-#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/
-#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */
- /* between 4 and 8 MHz (default after reset) */
-#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is
- between 8 and 16 MHz */
-/* @note other IFRGE values are reserved */
+/***************** Bit definition for RCC_APB2DIVR register *****************/
+#define RCC_APB2DIVR_APB2DIV_Pos (0U)
+#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */
+#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U)
+#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */
-/******************** Bit definition for RCC_PLL3CFGR2 register********************/
-/* @TODO To compleate as needed */
-#define RCC_PLL3CFGR2_DIVP_Pos (0U)
-#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
-#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/
-#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */
-#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */
-#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
+/***************** Bit definition for RCC_APB3DIVR register *****************/
+#define RCC_APB3DIVR_APB3DIV_Pos (0U)
+#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */
+#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U)
+#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */
-#define RCC_PLL3CFGR2_DIVQ_Pos (8U)
-#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
-#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/
-#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */
-#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */
-#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+/****************** Bit definition for RCC_PLL3CR register ******************/
+#define RCC_PLL3CR_PLLON_Pos (0U)
+#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */
+#define RCC_PLL3CR_PLL3RDY_Pos (1U)
+#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
+#define RCC_PLL3CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */
+#define RCC_PLL3CR_DIVPEN_Pos (4U)
+#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */
+#define RCC_PLL3CR_DIVQEN_Pos (5U)
+#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */
+#define RCC_PLL3CR_DIVREN_Pos (6U)
+#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */
-#define RCC_PLL3CFGR2_DIVR_Pos (16U)
-#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
-#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/
-#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */
-#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */
-#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+/**************** Bit definition for RCC_PLL3CFGR1 register *****************/
+#define RCC_PLL3CFGR1_DIVN_Pos (0U)
+#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */
+#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
+#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */
+#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */
+#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */
+#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */
+#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */
+#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */
+#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLL3CFGR1_IFRGE_Pos (24U)
+#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */
+#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */
+#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */
+#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */
-/******************** Bit definition for RCC_PLL3FRACR register********************/
-#define RCC_PLL3FRACR_FRACV_Pos (3U)
-#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
-#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/
-/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+/**************** Bit definition for RCC_PLL3CFGR2 register *****************/
+#define RCC_PLL3CFGR2_DIVP_Pos (0U)
+#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */
+#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL3CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */
+#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL3CFGR2_DIVR_Pos (16U)
+#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */
+#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */
-#define RCC_PLL3FRACR_FRACLE_Pos (16U)
-#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */
-#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/
+/**************** Bit definition for RCC_PLL3FRACR register *****************/
+#define RCC_PLL3FRACR_FRACV_Pos (3U)
+#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */
+#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL3FRACR_FRACLE_Pos (16U)
+#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */
/******************** Bit definition for RCC_PLL3CSGR register********************/
#define RCC_PLL3CSGR_MOD_PER_Pos (0U)
@@ -18994,85 +25366,110 @@
#define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
#define RCC_PLL3CSGR_INC_STEP_Pos (16U)
#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL3CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/
-/******************** Bit definition for RCC_PLL4CR register********************/
-#define RCC_PLL4CR_PLLON_Pos (0U)
-#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */
-#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/
-#define RCC_PLL4CR_PLL4RDY_Pos (1U)
-#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */
-#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/
-#define RCC_PLL4CR_SSCG_CTRL_Pos (2U)
-#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
-#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/
-#define RCC_PLL4CR_DIVPEN_Pos (4U)
-#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */
-#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/
-#define RCC_PLL4CR_DIVQEN_Pos (5U)
-#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */
-#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/
-#define RCC_PLL4CR_DIVREN_Pos (6U)
-#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */
-#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/
+/****************** Bit definition for RCC_PLL4CR register ******************/
+#define RCC_PLL4CR_PLLON_Pos (0U)
+#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */
+#define RCC_PLL4CR_PLL4RDY_Pos (1U)
+#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */
+#define RCC_PLL4CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/
+#define RCC_PLL4CR_DIVPEN_Pos (4U)
+#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */
+#define RCC_PLL4CR_DIVQEN_Pos (5U)
+#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */
+#define RCC_PLL4CR_DIVREN_Pos (6U)
+#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */
-/******************** Bit definition for RCC_PLL4CFGR1 register********************/
-#define RCC_PLL4CFGR1_DIVN_Pos (0U)
-#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */
-#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/
-/* @note Valid division rations for DIVN: between 25 and 200 */
-#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
-#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
-#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
+/**************** Bit definition for RCC_PLL4CFGR1 register *****************/
+#define RCC_PLL4CFGR1_DIVN_Pos (0U)
+#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */
+#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
+#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */
+#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */
+#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */
+#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */
+#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */
+#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */
+#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */
+#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */
+#define RCC_PLL4CFGR1_IFRGE_Pos (24U)
+#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */
+#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */
+#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */
+#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */
-#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
-#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
-#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */
-#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/
-/* @note "y" division factor must be an integer value between 1 and 64 */
-#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+/**************** Bit definition for RCC_PLL4CFGR2 register *****************/
+#define RCC_PLL4CFGR2_DIVP_Pos (0U)
+#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */
+#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL4CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */
+#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL4CFGR2_DIVR_Pos (16U)
+#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */
+#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */
-#define RCC_PLL4CFGR1_IFRGE_Pos (24U)
-#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */
-#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/
-#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */
- /*between 4 and 8 MHz (default after reset) */
-#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is
- between 8 and 16 MHz */
-/* @note other IFRGE values are reserved */
-
-/******************** Bit definition for RCC_PLL4CFGR2 register********************/
-/* @TODO To compleate as needed */
-#define RCC_PLL4CFGR2_DIVP_Pos (0U)
-#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
-#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/
-#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */
-#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */
-#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
-
-#define RCC_PLL4CFGR2_DIVQ_Pos (8U)
-#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
-#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/
-#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */
-#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */
-#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
-
-#define RCC_PLL4CFGR2_DIVR_Pos (16U)
-#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
-#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/
-#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */
-#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */
-#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
-
-/******************** Bit definition for RCC_PLL4FRACR register********************/
-#define RCC_PLL4FRACR_FRACV_Pos (3U)
-#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
-#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/
-/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
-
-#define RCC_PLL4FRACR_FRACLE_Pos (16U)
-#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */
-#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/
+/**************** Bit definition for RCC_PLL4FRACR register *****************/
+#define RCC_PLL4FRACR_FRACV_Pos (3U)
+#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */
+#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL4FRACR_FRACLE_Pos (16U)
+#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */
/******************** Bit definition for RCC_PLL4CSGR register********************/
#define RCC_PLL4CSGR_MOD_PER_Pos (0U)
@@ -19091,1912 +25488,2853 @@
#define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/
-/******************** Bit definition for RCC_I2C12CKSELR register********************/
-#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U)
-#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */
-#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/
-#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */
-#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */
-#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */
-#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */
+/*************** Bit definition for RCC_I2C12CKSELR register ****************/
+#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U)
+#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */
+#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_I2C35CKSELR register********************/
-#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U)
-#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */
-#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/
-#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */
-#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */
-#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */
-#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */
+/*************** Bit definition for RCC_I2C35CKSELR register ****************/
+#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U)
+#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */
+#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_I2C46CKSELR register********************/
-#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U)
-#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
-#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/
-#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */
-#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
-#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
-#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_SAI1CKSELR register ****************/
+#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U)
+#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */
+#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SAI1CKSELR register********************/
-#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U)
-#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */
-#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/
-#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */
-#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */
-#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */
-#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */
-#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */
+/**************** Bit definition for RCC_SAI2CKSELR register ****************/
+#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U)
+#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */
+#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SAI2CKSELR register********************/
-#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U)
-#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */
-#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/
-#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */
-#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */
-#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */
-#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */
-#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */
-#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */
+/**************** Bit definition for RCC_SAI3CKSELR register ****************/
+#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U)
+#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */
+#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SAI3CKSELR register********************/
-#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U)
-#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */
-#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/
-#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */
-#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */
-#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */
-#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */
-#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */
+/**************** Bit definition for RCC_SAI4CKSELR register ****************/
+#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U)
+#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */
+#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SAI4CKSELR register********************/
-#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U)
-#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */
-#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/
-#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */
-#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */
-#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */
-#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */
-#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/
+#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U)
+#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */
+#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SPI2S1CKSELR register********************/
-#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U)
-#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */
-#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/
-#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */
-#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */
-#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */
-#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */
-#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */
+/************** Bit definition for RCC_SPI2S23CKSELR register ***************/
+#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U)
+#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */
+#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SPI2S23CKSELR register********************/
-#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U)
-#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */
-#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/
-#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */
-#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */
-#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */
-#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */
-#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_SPI45CKSELR register ****************/
+#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U)
+#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */
+#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SPI45CKSELR register********************/
-#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U)
-#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */
-#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/
-#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */
-#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */
-#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */
-#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */
-#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_UART6CKSELR register ****************/
+#define RCC_UART6CKSELR_UART6SRC_Pos (0U)
+#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */
+#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_SPI6CKSELR register********************/
-#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U)
-#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
-#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/
-#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */
-#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
-#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
-#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */
-#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
-#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */
+/*************** Bit definition for RCC_UART24CKSELR register ***************/
+#define RCC_UART24CKSELR_UART24SRC_Pos (0U)
+#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */
+#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_UART6CKSELR register********************/
-#define RCC_UART6CKSELR_UART6SRC_Pos (0U)
-#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */
-#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/
-#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */
-#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */
-#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */
-#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */
-#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_UART35CKSELR register ***************/
+#define RCC_UART35CKSELR_UART35SRC_Pos (0U)
+#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */
+#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_UART24CKSELR register********************/
-#define RCC_UART24CKSELR_UART24SRC_Pos (0U)
-#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */
-#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/
-#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */
-#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */
-#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */
-#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */
-#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_UART78CKSELR register ***************/
+#define RCC_UART78CKSELR_UART78SRC_Pos (0U)
+#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */
+#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_UART35CKSELR register********************/
-#define RCC_UART35CKSELR_UART35SRC_Pos (0U)
-#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */
-#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/
-#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */
-#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */
-#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */
-#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */
-#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */
+/************** Bit definition for RCC_SDMMC12CKSELR register ***************/
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U)
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_UART78CKSELR register********************/
-#define RCC_UART78CKSELR_UART78SRC_Pos (0U)
-#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */
-#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/
-#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */
-#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */
-#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */
-#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */
-#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */
+/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U)
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_UART1CKSELR register********************/
-#define RCC_UART1CKSELR_UART1SRC_Pos (0U)
-#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
-#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/
-#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */
-#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
-#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
-#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */
-#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
-#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */
+/**************** Bit definition for RCC_ETHCKSELR register *****************/
+#define RCC_ETHCKSELR_ETHSRC_Pos (0U)
+#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */
+#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */
+#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */
+#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */
+#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U)
+#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
+#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */
+#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */
+#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */
+#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */
+#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */
-/******************** Bit definition for RCC_SDMMC12CKSELR register********************/
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U)
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
-#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */
-#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_QSPICKSELR register ****************/
+#define RCC_QSPICKSELR_QSPISRC_Pos (0U)
+#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
+#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */
+#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */
+#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_SDMMC3CKSELR register********************/
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U)
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
-#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */
-#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_FMCCKSELR register *****************/
+#define RCC_FMCCKSELR_FMCSRC_Pos (0U)
+#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
+#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */
+#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */
+#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_ETHCKSELR register********************/
-#define RCC_ETHCKSELR_ETHSRC_Pos (0U)
-#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */
-#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/
-#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */
-#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */
-#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */
+/*************** Bit definition for RCC_FDCANCKSELR register ****************/
+#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U)
+#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
+#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */
+#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */
+#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */
-#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U)
-#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
-#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/
-#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */
-#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */
-#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */
-#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */
-#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */
-#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */
-#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */
-#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */
-#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */
-#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */
-#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */
-#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */
-#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */
-#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */
-#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */
-#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
+/*************** Bit definition for RCC_SPDIFCKSELR register ****************/
+#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U)
+#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */
+#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */
+#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */
+#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_QSPICKSELR register********************/
-#define RCC_QSPICKSELR_QSPISRC_Pos (0U)
-#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
-#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/
-#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */
-#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */
-#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */
-#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_CECCKSELR register *****************/
+#define RCC_CECCKSELR_CECSRC_Pos (0U)
+#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */
+#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */
+#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */
+#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_FMCCKSELR register********************/
-#define RCC_FMCCKSELR_FMCSRC_Pos (0U)
-#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
-#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/
-#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */
-#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */
-#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */
-#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_USBCKSELR register *****************/
+#define RCC_USBCKSELR_USBPHYSRC_Pos (0U)
+#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */
+#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */
+#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */
+#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */
+#define RCC_USBCKSELR_USBOSRC_Pos (4U)
+#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
+#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */
+/**************** Bit definition for RCC_RNG2CKSELR register ****************/
+#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U)
+#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
+#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */
+#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */
+#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_SPDIFCKSELR register********************/
-#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U)
-#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */
-#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/
-#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */
-#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */
-#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */
+/**************** Bit definition for RCC_DSICKSELR register *****************/
+#define RCC_DSICKSELR_DSISRC_Pos (0U)
+#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
+#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */
-/******************** Bit definition for RCC_CECCKSELR register********************/
-#define RCC_CECCKSELR_CECSRC_Pos (0U)
-#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */
-#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/
-#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */
-#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */
-#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */
+/**************** Bit definition for RCC_ADCCKSELR register *****************/
+#define RCC_ADCCKSELR_ADCSRC_Pos (0U)
+#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */
+#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */
+#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */
+#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_USBCKSELR register********************/
-#define RCC_USBCKSELR_USBPHYSRC_Pos (0U)
-#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */
-#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/
-#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */
-#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */
-#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */
+/************** Bit definition for RCC_LPTIM45CKSELR register ***************/
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U)
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */
-#define RCC_USBCKSELR_USBOSRC_Pos (4U)
-#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
-#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/
-#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */
-#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
+/************** Bit definition for RCC_LPTIM23CKSELR register ***************/
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U)
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RNG1CKSELR register********************/
-#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U)
-#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
-#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/
-#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */
-#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
-#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
-#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
+/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U)
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RNG2CKSELR register********************/
-#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U)
-#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
-#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/
-#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */
-#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */
-#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */
-#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
+/*************** Bit definition for RCC_APB1RSTSETR register ****************/
+#define RCC_APB1RSTSETR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */
+#define RCC_APB1RSTSETR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */
+#define RCC_APB1RSTSETR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */
+#define RCC_APB1RSTSETR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */
+#define RCC_APB1RSTSETR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */
+#define RCC_APB1RSTSETR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */
+#define RCC_APB1RSTSETR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */
+#define RCC_APB1RSTSETR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */
+#define RCC_APB1RSTSETR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */
+#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U)
+#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */
+#define RCC_APB1RSTSETR_SPI2RST_Pos (11U)
+#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */
+#define RCC_APB1RSTSETR_SPI3RST_Pos (12U)
+#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */
+#define RCC_APB1RSTSETR_USART2RST_Pos (14U)
+#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */
+#define RCC_APB1RSTSETR_USART3RST_Pos (15U)
+#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */
+#define RCC_APB1RSTSETR_UART4RST_Pos (16U)
+#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */
+#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */
+#define RCC_APB1RSTSETR_UART5RST_Pos (17U)
+#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */
+#define RCC_APB1RSTSETR_UART7RST_Pos (18U)
+#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */
+#define RCC_APB1RSTSETR_UART8RST_Pos (19U)
+#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */
+#define RCC_APB1RSTSETR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */
+#define RCC_APB1RSTSETR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */
+#define RCC_APB1RSTSETR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */
+#define RCC_APB1RSTSETR_I2C5RST_Pos (24U)
+#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */
+#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U)
+#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */
+#define RCC_APB1RSTSETR_CECRST_Pos (27U)
+#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */
+#define RCC_APB1RSTSETR_DAC12RST_Pos (29U)
+#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */
+#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U)
+#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */
-/******************** Bit definition for RCC_CPERCKSELR register********************/
-#define RCC_CPERCKSELR_CKPERSRC_Pos (0U)
-#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
-#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/
-#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */
-#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
-#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
-#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
+/*************** Bit definition for RCC_APB1RSTCLRR register ****************/
+#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */
+#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */
+#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */
+#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */
+#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */
+#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */
+#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */
+#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */
+#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */
+#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U)
+#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */
+#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U)
+#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */
+#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U)
+#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */
+#define RCC_APB1RSTCLRR_USART2RST_Pos (14U)
+#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */
+#define RCC_APB1RSTCLRR_USART3RST_Pos (15U)
+#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */
+#define RCC_APB1RSTCLRR_UART4RST_Pos (16U)
+#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */
+#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */
+#define RCC_APB1RSTCLRR_UART5RST_Pos (17U)
+#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */
+#define RCC_APB1RSTCLRR_UART7RST_Pos (18U)
+#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */
+#define RCC_APB1RSTCLRR_UART8RST_Pos (19U)
+#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */
+#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */
+#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */
+#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */
+#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U)
+#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */
+#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U)
+#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */
+#define RCC_APB1RSTCLRR_CECRST_Pos (27U)
+#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */
+#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U)
+#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */
+#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U)
+#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */
-/******************** Bit definition for RCC_CSTGENCKSELR register******************/
-#define RCC_STGENCKSELR_STGENSRC_Pos (0U)
-#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
-#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/
-#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */
-#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
-#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
+/*************** Bit definition for RCC_APB2RSTSETR register ****************/
+#define RCC_APB2RSTSETR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */
+#define RCC_APB2RSTSETR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */
+#define RCC_APB2RSTSETR_TIM15RST_Pos (2U)
+#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */
+#define RCC_APB2RSTSETR_TIM16RST_Pos (3U)
+#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */
+#define RCC_APB2RSTSETR_TIM17RST_Pos (4U)
+#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */
+#define RCC_APB2RSTSETR_SPI1RST_Pos (8U)
+#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */
+#define RCC_APB2RSTSETR_SPI4RST_Pos (9U)
+#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */
+#define RCC_APB2RSTSETR_SPI5RST_Pos (10U)
+#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */
+#define RCC_APB2RSTSETR_USART6RST_Pos (13U)
+#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */
+#define RCC_APB2RSTSETR_SAI1RST_Pos (16U)
+#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */
+#define RCC_APB2RSTSETR_SAI2RST_Pos (17U)
+#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */
+#define RCC_APB2RSTSETR_SAI3RST_Pos (18U)
+#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */
+#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U)
+#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */
+#define RCC_APB2RSTSETR_FDCANRST_Pos (24U)
+#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */
-/******************** Bit definition for RCC_DDRITFCR register*********************/
-#define RCC_DDRITFCR_DDRC1EN B(0)
-#define RCC_DDRITFCR_DDRC1LPEN B(1)
-#define RCC_DDRITFCR_DDRC2EN B(2)
-#define RCC_DDRITFCR_DDRC2LPEN B(3)
-#define RCC_DDRITFCR_DDRPHYCEN B(4)
-#define RCC_DDRITFCR_DDRPHYCLPEN B(5)
-#define RCC_DDRITFCR_DDRCAPBEN B(6)
-#define RCC_DDRITFCR_DDRCAPBLPEN B(7)
-#define RCC_DDRITFCR_AXIDCGEN B(8)
-#define RCC_DDRITFCR_DDRPHYCAPBEN B(9)
-#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10)
+/*************** Bit definition for RCC_APB2RSTCLRR register ****************/
+#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */
+#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */
+#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U)
+#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */
+#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U)
+#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */
+#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U)
+#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */
+#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U)
+#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */
+#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U)
+#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */
+#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U)
+#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */
+#define RCC_APB2RSTCLRR_USART6RST_Pos (13U)
+#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */
+#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U)
+#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */
+#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U)
+#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */
+#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U)
+#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */
+#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U)
+#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */
+#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U)
+#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */
-#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U)
-#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
-#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/
-#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */
-#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */
-#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
-#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */
-#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
-#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */
-#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */
-#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */
-#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
-#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */
-#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */
-#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */
-#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */
-#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */
-#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
-#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
+/*************** Bit definition for RCC_APB3RSTSETR register ****************/
+#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U)
+#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */
+#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U)
+#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */
+#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U)
+#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */
+#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U)
+#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */
+#define RCC_APB3RSTSETR_SAI4RST_Pos (8U)
+#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */
+#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */
+#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U)
+#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */
+#define RCC_APB3RSTSETR_VREFRST_Pos (13U)
+#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */
+#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */
+#define RCC_APB3RSTSETR_DTSRST_Pos (16U)
+#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */
+#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */
-#define RCC_DDRITFCR_DDRCAPBRST B(14)
-#define RCC_DDRITFCR_DDRCAXIRST B(15)
-#define RCC_DDRITFCR_DDRCORERST B(16)
-#define RCC_DDRITFCR_DPHYAPBRST B(17)
-#define RCC_DDRITFCR_DPHYRST B(18)
-#define RCC_DDRITFCR_DPHYCTLRST B(19)
+/*************** Bit definition for RCC_APB3RSTCLRR register ****************/
+#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U)
+#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */
+#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U)
+#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */
+#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U)
+#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */
+#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U)
+#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */
+#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U)
+#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */
+#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */
+#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U)
+#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */
+#define RCC_APB3RSTCLRR_VREFRST_Pos (13U)
+#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */
+#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */
+#define RCC_APB3RSTCLRR_DTSRST_Pos (16U)
+#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */
+#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */
-#define RCC_DDRITFCR_DDRCKMOD_Pos (20U)
-#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
-#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/
-#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */
-#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
-#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
-#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */
-#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */
+/*************** Bit definition for RCC_AHB2RSTSETR register ****************/
+#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U)
+#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */
+#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U)
+#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */
+#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U)
+#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */
+#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U)
+#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */
+#define RCC_AHB2RSTSETR_USBORST_Pos (8U)
+#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */
+#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */
+#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U)
+#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */
+/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/
+#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U)
+#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */
+#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U)
+#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */
+#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U)
+#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */
+#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U)
+#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */
+#define RCC_AHB2RSTCLRR_USBORST_Pos (8U)
+#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */
+#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */
+#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U)
+#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */
-/******************** Bit definition for RCC_ADCCKSELR register********************/
-#define RCC_ADCCKSELR_ADCSRC_Pos (0U)
-#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */
-#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/
-#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */
-#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */
-#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */
+/*************** Bit definition for RCC_AHB3RSTSETR register ****************/
+#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U)
+#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */
+#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U)
+#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */
+#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U)
+#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */
+#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U)
+#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */
+#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U)
+#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */
+#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U)
+#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */
+#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */
+#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U)
+#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */
-/******************** Bit definition for RCC_LPTIM45CKSELR register********************/
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U)
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */
-#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */
+/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/
+#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U)
+#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */
+#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U)
+#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */
+#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U)
+#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */
+#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U)
+#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */
+#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U)
+#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */
+#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U)
+#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */
+#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */
+#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U)
+#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */
-/******************** Bit definition for RCC_LPTIM23CKSELR register********************/
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U)
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */
-#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */
+/*************** Bit definition for RCC_AHB4RSTSETR register ****************/
+#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U)
+#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */
+#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U)
+#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */
+#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U)
+#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */
+#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U)
+#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */
+#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U)
+#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */
+#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U)
+#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */
+#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U)
+#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */
+#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U)
+#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */
+#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U)
+#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */
+#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U)
+#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */
+#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U)
+#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */
-/******************** Bit definition for RCC_LPTIM1CKSELR register********************/
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U)
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */
-#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */
+/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/
+#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U)
+#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */
+#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U)
+#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */
+#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U)
+#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */
+#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U)
+#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */
+#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U)
+#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */
+#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U)
+#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */
+#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U)
+#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */
+#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U)
+#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */
+#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U)
+#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */
+#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U)
+#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */
+#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U)
+#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */
-/******************** Bit definition for RCC_MP_BOOTCR register*********************/
-#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U)
-#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
-#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/
-#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U)
-#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
-#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/
+/************** Bit definition for RCC_MP_APB1ENSETR register ***************/
+#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U)
+#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U)
+#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U)
+#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U)
+#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U)
+#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U)
+#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U)
+#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U)
+#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U)
+#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U)
+#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U)
+#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U)
+#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U)
+#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */
+#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U)
+#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U)
+#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U)
+#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U)
+#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U)
+#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */
+#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U)
+#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U)
+#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U)
+#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U)
+#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U)
+#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */
+#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_CECEN_Pos (27U)
+#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U)
+#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */
+#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U)
+#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */
+#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */
-/******************** Bit definition for RCC_MP_SREQSETR register********************/
-/* @note The MCU cannot access to this register */
-#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U)
-#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
-#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
-#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U)
-#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
-#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
+/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/
+#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U)
+#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U)
+#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U)
+#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U)
+#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U)
+#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U)
+#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U)
+#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U)
+#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U)
+#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U)
+#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U)
+#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U)
+#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U)
+#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */
+#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U)
+#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U)
+#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U)
+#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U)
+#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U)
+#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */
+#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U)
+#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U)
+#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U)
+#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U)
+#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U)
+#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */
+#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U)
+#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U)
+#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */
+#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U)
+#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */
+#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */
-/******************** Bit definition for RCC_MP_SREQCLRR register********************/
-/* @note The MCU cannot access to this register */
-#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U)
-#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
-#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
-#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U)
-#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
-#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
+/************** Bit definition for RCC_MP_APB2ENSETR register ***************/
+#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U)
+#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U)
+#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U)
+#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U)
+#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U)
+#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U)
+#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U)
+#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U)
+#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */
+#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U)
+#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U)
+#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U)
+#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U)
+#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U)
+#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U)
+#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */
+#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U)
+#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */
-/******************** Bit definition for RCC_MP_GCR register********************/
-#define RCC_MP_GCR_BOOT_MCU_Pos (0U)
-#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
-#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/
-#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */
-#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
+/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/
+#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U)
+#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U)
+#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U)
+#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U)
+#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U)
+#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U)
+#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U)
+#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U)
+#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */
+#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U)
+#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U)
+#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U)
+#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U)
+#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U)
+#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U)
+#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */
+#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U)
+#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */
-/******************** Bit definition for RCC_MP_APRSTCR register ********************/
-#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U)
-#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
-#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/
-#define RCC_MP_APRSTCR_RSTTO_Pos (8U)
-#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
-#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/
+/************** Bit definition for RCC_MP_APB3ENSETR register ***************/
+#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U)
+#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U)
+#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U)
+#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U)
+#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U)
+#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U)
+#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U)
+#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U)
+#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */
+#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U)
+#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */
-/******************** Bit definition for RCC_MP_APRSTSR register ********************/
-#define RCC_MP_APRSTSR_RSTTOV_Pos (8U)
-#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
-#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/
+/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/
+#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U)
+#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U)
+#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U)
+#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U)
+#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U)
+#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U)
+#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U)
+#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U)
+#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */
+#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U)
+#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */
-/******************* Bit definition for RCC_BDCR register ********************/
-#define RCC_BDCR_LSEON_Pos (0U)
-#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
-#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/
-#define RCC_BDCR_LSEBYP_Pos (1U)
-#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */
-#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/
-#define RCC_BDCR_LSERDY_Pos (2U)
-#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */
-#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/
+/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/
+#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U)
+#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */
+#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U)
+#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */
+#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U)
+#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */
+#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U)
+#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */
+#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U)
+#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */
+#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U)
+#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */
-#define RCC_BDCR_DIGBYP_Pos (3U)
-#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */
-#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */
+/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/
+#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U)
+#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */
+#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U)
+#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */
+#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U)
+#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */
+#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U)
+#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */
+#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U)
+#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */
+#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U)
+#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */
-#define RCC_BDCR_LSEDRV_Pos (4U)
-#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
-#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/
-#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */
-#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
-#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */
-#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
+/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/
+#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U)
+#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U)
+#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U)
+#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U)
+#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U)
+#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U)
+#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */
+#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U)
+#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */
-#define RCC_BDCR_LSECSSON_Pos (8U)
-#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */
-#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/
-#define RCC_BDCR_LSECSSD_Pos (9U)
-#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */
-#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/
+/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/
+#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U)
+#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U)
+#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U)
+#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U)
+#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U)
+#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U)
+#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */
+#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U)
+#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */
-#define RCC_BDCR_RTCSRC_Pos (16U)
-#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
-#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/
-#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */
-#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */
-#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */
-#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
+/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/
+#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U)
+#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U)
+#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U)
+#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U)
+#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U)
+#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U)
+#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U)
+#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U)
+#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U)
+#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U)
+#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */
+#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U)
+#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */
-#define RCC_BDCR_RTCCKEN_Pos (20U)
-#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */
-#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/
-#define RCC_BDCR_VSWRST_Pos (31U)
-#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
-#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/
+/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/
+#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U)
+#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U)
+#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U)
+#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U)
+#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U)
+#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U)
+#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U)
+#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U)
+#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U)
+#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U)
+#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */
+#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U)
+#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */
-/******************* Bit definition for RCC_RDLSICR register ********************/
-#define RCC_RDLSICR_LSION_Pos (0U)
-#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */
-#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/
-#define RCC_RDLSICR_LSIRDY_Pos (1U)
-#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
-#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/
-#define RCC_RDLSICR_MRD_Pos (16U)
-#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */
-#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/
-#define RCC_RDLSICR_EADLY_Pos (24U)
-#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */
-#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/
-#define RCC_RDLSICR_SPARE_Pos (27U)
-#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */
-#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/
+/************** Bit definition for RCC_MP_MLAHBENSETR register **************/
+#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U)
+#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */
-/******************* Bit definition for RCC_MP_CIER register *******************/
-#define RCC_MP_CIER_LSIRDYIE_Pos (0U)
-#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
-#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
-#define RCC_MP_CIER_LSERDYIE_Pos (1U)
-#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
-#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
-#define RCC_MP_CIER_HSIRDYIE_Pos (2U)
-#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
-#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
-#define RCC_MP_CIER_HSERDYIE_Pos (3U)
-#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
-#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
-#define RCC_MP_CIER_CSIRDYIE_Pos (4U)
-#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
-#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
-#define RCC_MP_CIER_PLL1DYIE_Pos (8U)
-#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
-#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
-#define RCC_MP_CIER_PLL2DYIE_Pos (9U)
-#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
-#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
-#define RCC_MP_CIER_PLL3DYIE_Pos (10U)
-#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
-#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
-#define RCC_MP_CIER_PLL4DYIE_Pos (11U)
-#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
-#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
-#define RCC_MP_CIER_LSECSSIE_Pos (16U)
-#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
-#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
-#define RCC_MP_CIER_WKUPIE_Pos (20U)
-#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */
-#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
+/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/
+#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U)
+#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */
-/******************* Bit definition for RCC_MP_CIFR register ********************/
-#define RCC_MP_CIFR_LSIRDYF_Pos (0U)
-#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
-#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
-#define RCC_MP_CIFR_LSERDYF_Pos (1U)
-#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
-#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
-#define RCC_MP_CIFR_HSIRDYF_Pos (2U)
-#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
-#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
-#define RCC_MP_CIFR_HSERDYF_Pos (3U)
-#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
-#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
-#define RCC_MP_CIFR_CSIRDYF_Pos (4U)
-#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
-#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
-#define RCC_MP_CIFR_PLL1DYF_Pos (8U)
-#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
-#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
-#define RCC_MP_CIFR_PLL2DYF_Pos (9U)
-#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
-#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
-#define RCC_MP_CIFR_PLL3DYF_Pos (10U)
-#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
-#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
-#define RCC_MP_CIFR_PLL4DYF_Pos (11U)
-#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
-#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
-#define RCC_MP_CIFR_LSECSSF_Pos (16U)
-#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
-#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
-#define RCC_MP_CIFR_WKUPF_Pos (20U)
-#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */
-#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
+/************** Bit definition for RCC_MC_APB1ENSETR register ***************/
+#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U)
+#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U)
+#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U)
+#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U)
+#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U)
+#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U)
+#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U)
+#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U)
+#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U)
+#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U)
+#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U)
+#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U)
+#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U)
+#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */
+#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U)
+#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */
+#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U)
+#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U)
+#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U)
+#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U)
+#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */
+#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U)
+#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U)
+#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U)
+#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U)
+#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U)
+#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */
+#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_CECEN_Pos (27U)
+#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U)
+#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */
+#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U)
+#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */
+#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U)
+#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */
+#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */
-/******************* Bit definition for RCC_MC_CIER register *******************/
-#define RCC_MC_CIER_LSIRDYIE_Pos (0U)
-#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
-#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
-#define RCC_MC_CIER_LSERDYIE_Pos (1U)
-#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
-#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
-#define RCC_MC_CIER_HSIRDYIE_Pos (2U)
-#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
-#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
-#define RCC_MC_CIER_HSERDYIE_Pos (3U)
-#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
-#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
-#define RCC_MC_CIER_CSIRDYIE_Pos (4U)
-#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
-#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
-#define RCC_MC_CIER_PLL1DYIE_Pos (8U)
-#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
-#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
-#define RCC_MC_CIER_PLL2DYIE_Pos (9U)
-#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
-#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
-#define RCC_MC_CIER_PLL3DYIE_Pos (10U)
-#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
-#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
-#define RCC_MC_CIER_PLL4DYIE_Pos (11U)
-#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
-#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
-#define RCC_MC_CIER_LSECSSIE_Pos (16U)
-#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
-#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
-#define RCC_MC_CIER_WKUPIE_Pos (20U)
-#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */
-#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
+/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/
+#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U)
+#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U)
+#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U)
+#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U)
+#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U)
+#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U)
+#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U)
+#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U)
+#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U)
+#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U)
+#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U)
+#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U)
+#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U)
+#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */
+#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U)
+#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */
+#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U)
+#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U)
+#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U)
+#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U)
+#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */
+#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U)
+#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U)
+#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U)
+#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U)
+#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U)
+#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */
+#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U)
+#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U)
+#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */
+#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U)
+#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */
+#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */
-/******************* Bit definition for RCC_MC_CIFR register ********************/
-#define RCC_MC_CIFR_LSIRDYF_Pos (0U)
-#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
-#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
-#define RCC_MC_CIFR_LSERDYF_Pos (1U)
-#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
-#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
-#define RCC_MC_CIFR_HSIRDYF_Pos (2U)
-#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
-#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
-#define RCC_MC_CIFR_HSERDYF_Pos (3U)
-#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
-#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
-#define RCC_MC_CIFR_CSIRDYF_Pos (4U)
-#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
-#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
-#define RCC_MC_CIFR_PLL1DYF_Pos (8U)
-#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
-#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
-#define RCC_MC_CIFR_PLL2DYF_Pos (9U)
-#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
-#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
-#define RCC_MC_CIFR_PLL3DYF_Pos (10U)
-#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
-#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
-#define RCC_MC_CIFR_PLL4DYF_Pos (11U)
-#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
-#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
-#define RCC_MC_CIFR_LSECSSF_Pos (16U)
-#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
-#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
-#define RCC_MC_CIFR_WKUPF_Pos (20U)
-#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */
-#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
+/************** Bit definition for RCC_MC_APB2ENSETR register ***************/
+#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U)
+#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U)
+#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U)
+#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U)
+#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U)
+#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U)
+#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U)
+#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U)
+#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */
+#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U)
+#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U)
+#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U)
+#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U)
+#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U)
+#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U)
+#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */
+#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U)
+#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */
+/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/
+#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U)
+#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U)
+#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U)
+#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U)
+#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U)
+#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U)
+#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U)
+#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U)
+#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */
+#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U)
+#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U)
+#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U)
+#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U)
+#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U)
+#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U)
+#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */
+#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U)
+#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */
-/******************* Bit definition for RCC_PWRLPDLYCR register ********************/
-#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U)
-#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */
-#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/
-#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */
-#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */
-#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U)
-#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */
-#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/
+/************** Bit definition for RCC_MC_APB3ENSETR register ***************/
+#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U)
+#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U)
+#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U)
+#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U)
+#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U)
+#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U)
+#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U)
+#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U)
+#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */
+#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U)
+#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */
-#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/
+/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/
+#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U)
+#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U)
+#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U)
+#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U)
+#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U)
+#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U)
+#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U)
+#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U)
+#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */
+#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U)
+#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */
+/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/
+#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U)
+#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */
+#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U)
+#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */
+#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U)
+#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */
+#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U)
+#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */
+#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U)
+#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */
+#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U)
+#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */
-/******************* Bit definition for RCC_MP_RSTSSETR register *********************/
-/*!< This register is dedicated to the BOOTROM code in order to update the reset source.
- * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a
- * system reset (nreset), or an exit from Standby or CStandby.
- *@note The application software shall not use this register. In order to identify the
- * reset source, the MPU application must use RCC MPU Reset Status Clear Register
- * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status
- * Clear Register (RCC_MC_RSTSCLRR).
- *@note Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '1'.
- *@note The register is located in VDDCORE.
- *@note If TZEN = '1', this register can only be modified in secure mode.
- */
-#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U)
-#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */
-#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/
+/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/
+#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U)
+#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */
+#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U)
+#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */
+#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U)
+#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */
+#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U)
+#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */
+#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U)
+#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */
+#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U)
+#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */
-#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U)
-#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */
-#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/
+/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/
+#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U)
+#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U)
+#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U)
+#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U)
+#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U)
+#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U)
+#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */
+#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U)
+#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */
-#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U)
-#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */
-#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/
+/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/
+#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U)
+#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U)
+#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U)
+#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U)
+#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U)
+#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U)
+#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */
+#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U)
+#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */
-#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U)
-#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */
-#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/
+#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U)
+#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U)
+#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U)
+#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U)
+#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U)
+#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U)
+#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U)
+#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U)
+#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U)
+#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U)
+#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */
+#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U)
+#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */
-#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U)
-#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */
-#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/
+/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/
+#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U)
+#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U)
+#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U)
+#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U)
+#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U)
+#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U)
+#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U)
+#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U)
+#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U)
+#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U)
+#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */
+#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U)
+#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */
-#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U)
-#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */
-#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/
+/************** Bit definition for RCC_MC_AXIMENSETR register ***************/
+#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U)
+#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */
-#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U)
-#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */
-#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/
+/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/
+#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U)
+#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */
-#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U)
-#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */
-#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+/************** Bit definition for RCC_MC_MLAHBENSETR register **************/
+#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U)
+#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */
-#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U)
-#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */
-#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/
+#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U)
+#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */
-#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U)
-#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */
-#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/
-
-#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U)
-#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
-#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
-
-#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U)
-#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */
-#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
-
-#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U)
-#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */
-#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
-
-#define RCC_MP_RSTSSETR_SPARE_Pos (15U)
-#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */
-#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/
-
-/******************* Bit definition for RCC_APB1RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_APB1RSTSETR_TIM2RST B(0)
-#define RCC_APB1RSTSETR_TIM3RST B(1)
-#define RCC_APB1RSTSETR_TIM4RST B(2)
-#define RCC_APB1RSTSETR_TIM5RST B(3)
-#define RCC_APB1RSTSETR_TIM6RST B(4)
-#define RCC_APB1RSTSETR_TIM7RST B(5)
-#define RCC_APB1RSTSETR_TIM12RST B(6)
-#define RCC_APB1RSTSETR_TIM13RST B(7)
-#define RCC_APB1RSTSETR_TIM14RST B(8)
-#define RCC_APB1RSTSETR_LPTIM1RST B(9)
-#define RCC_APB1RSTSETR_SPI2RST B(11)
-#define RCC_APB1RSTSETR_SPI3RST B(12)
-#define RCC_APB1RSTSETR_USART2RST B(14)
-#define RCC_APB1RSTSETR_USART3RST B(15)
-#define RCC_APB1RSTSETR_UART4RST B(16)
-#define RCC_APB1RSTSETR_UART5RST B(17)
-#define RCC_APB1RSTSETR_UART7RST B(18)
-#define RCC_APB1RSTSETR_UART8RST B(19)
-#define RCC_APB1RSTSETR_I2C1RST B(21)
-#define RCC_APB1RSTSETR_I2C2RST B(22)
-#define RCC_APB1RSTSETR_I2C3RST B(23)
-#define RCC_APB1RSTSETR_I2C5RST B(24)
-#define RCC_APB1RSTSETR_SPDIFRST B(26)
-#define RCC_APB1RSTSETR_CECRST B(27)
-#define RCC_APB1RSTSETR_DAC12RST B(29)
-#define RCC_APB1RSTSETR_MDIOSRST B(31)
-
-/******************* Bit definition for RCC_APB1RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_APB1RSTCLRR_TIM2RST B(0)
-#define RCC_APB1RSTCLRR_TIM3RST B(1)
-#define RCC_APB1RSTCLRR_TIM4RST B(2)
-#define RCC_APB1RSTCLRR_TIM5RST B(3)
-#define RCC_APB1RSTCLRR_TIM6RST B(4)
-#define RCC_APB1RSTCLRR_TIM7RST B(5)
-#define RCC_APB1RSTCLRR_TIM12RST B(6)
-#define RCC_APB1RSTCLRR_TIM13RST B(7)
-#define RCC_APB1RSTCLRR_TIM14RST B(8)
-#define RCC_APB1RSTCLRR_LPTIM1RST B(9)
-#define RCC_APB1RSTCLRR_SPI2RST B(11)
-#define RCC_APB1RSTCLRR_SPI3RST B(12)
-#define RCC_APB1RSTCLRR_USART2RST B(14)
-#define RCC_APB1RSTCLRR_USART3RST B(15)
-#define RCC_APB1RSTCLRR_UART4RST B(16)
-#define RCC_APB1RSTCLRR_UART5RST B(17)
-#define RCC_APB1RSTCLRR_UART7RST B(18)
-#define RCC_APB1RSTCLRR_UART8RST B(19)
-#define RCC_APB1RSTCLRR_I2C1RST B(21)
-#define RCC_APB1RSTCLRR_I2C2RST B(22)
-#define RCC_APB1RSTCLRR_I2C3RST B(23)
-#define RCC_APB1RSTCLRR_I2C5RST B(24)
-#define RCC_APB1RSTCLRR_SPDIFRST B(26)
-#define RCC_APB1RSTCLRR_CECRST B(27)
-#define RCC_APB1RSTCLRR_DAC12RST B(29)
-#define RCC_APB1RSTCLRR_MDIOSRST B(31)
-
-/******************* Bit definition for RCC_APB2RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_APB2RSTSETR_TIM1RST B(0)
-#define RCC_APB2RSTSETR_TIM8RST B(1)
-#define RCC_APB2RSTSETR_TIM15RST B(2)
-#define RCC_APB2RSTSETR_TIM16RST B(3)
-#define RCC_APB2RSTSETR_TIM17RST B(4)
-#define RCC_APB2RSTSETR_SPI1RST B(8)
-#define RCC_APB2RSTSETR_SPI4RST B(9)
-#define RCC_APB2RSTSETR_SPI5RST B(10)
-#define RCC_APB2RSTSETR_USART6RST B(13)
-#define RCC_APB2RSTSETR_SAI1RST B(16)
-#define RCC_APB2RSTSETR_SAI2RST B(17)
-#define RCC_APB2RSTSETR_SAI3RST B(18)
-#define RCC_APB2RSTSETR_DFSDMRST B(20)
-
-/******************* Bit definition for RCC_APB2RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_APB2RSTCLRR_TIM1RST B(0)
-#define RCC_APB2RSTCLRR_TIM8RST B(1)
-#define RCC_APB2RSTCLRR_TIM15RST B(2)
-#define RCC_APB2RSTCLRR_TIM16RST B(3)
-#define RCC_APB2RSTCLRR_TIM17RST B(4)
-#define RCC_APB2RSTCLRR_SPI1RST B(8)
-#define RCC_APB2RSTCLRR_SPI4RST B(9)
-#define RCC_APB2RSTCLRR_SPI5RST B(10)
-#define RCC_APB2RSTCLRR_USART6RST B(13)
-#define RCC_APB2RSTCLRR_SAI1RST B(16)
-#define RCC_APB2RSTCLRR_SAI2RST B(17)
-#define RCC_APB2RSTCLRR_SAI3RST B(18)
-#define RCC_APB2RSTCLRR_DFSDMRST B(20)
-
-/******************* Bit definition for RCC_APB3RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_APB3RSTSETR_LPTIM2RST B(0)
-#define RCC_APB3RSTSETR_LPTIM3RST B(1)
-#define RCC_APB3RSTSETR_LPTIM4RST B(2)
-#define RCC_APB3RSTSETR_LPTIM5RST B(3)
-#define RCC_APB3RSTSETR_SAI4RST B(8)
-#define RCC_APB3RSTSETR_SYSCFGRST B(11)
-#define RCC_APB3RSTSETR_VREFRST B(13)
-#define RCC_APB3RSTSETR_DTSRST B(16)
-#define RCC_APB3RSTSETR_PMBCTRLRST B(17)
-
-/******************* Bit definition for RCC_APB3RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_APB3RSTCLRR_LPTIM2RST B(0)
-#define RCC_APB3RSTCLRR_LPTIM3RST B(1)
-#define RCC_APB3RSTCLRR_LPTIM4RST B(2)
-#define RCC_APB3RSTCLRR_LPTIM5RST B(3)
-#define RCC_APB3RSTCLRR_SAI4RST B(8)
-#define RCC_APB3RSTCLRR_SYSCFGRST B(11)
-#define RCC_APB3RSTCLRR_VREFRST B(13)
-#define RCC_APB3RSTCLRR_DTSRST B(16)
-#define RCC_APB3RSTCLRR_PMBCTRLRST B(17)
-
-/******************* Bit definition for RCC_AHB2RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_AHB2RSTSETR_DMA1RST B(0)
-#define RCC_AHB2RSTSETR_DMA2RST B(1)
-#define RCC_AHB2RSTSETR_DMAMUXRST B(2)
-#define RCC_AHB2RSTSETR_ADC12RST B(5)
-#define RCC_AHB2RSTSETR_USBORST B(8)
-#define RCC_AHB2RSTSETR_SDMMC3RST B(16)
-
-/******************* Bit definition for RCC_AHB2RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_AHB2RSTCLRR_DMA1RST B(0)
-#define RCC_AHB2RSTCLRR_DMA2RST B(1)
-#define RCC_AHB2RSTCLRR_DMAMUXRST B(2)
-#define RCC_AHB2RSTCLRR_ADC12RST B(5)
-#define RCC_AHB2RSTCLRR_USBORST B(8)
-#define RCC_AHB2RSTCLRR_SDMMC3RST B(16)
-
-/******************* Bit definition for RCC_AHB3RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_AHB3RSTSETR_DCMIRST B(0)
-#define RCC_AHB3RSTSETR_HASH2RST B(5)
-#define RCC_AHB3RSTSETR_RNG2RST B(6)
-#define RCC_AHB3RSTSETR_CRC2RST B(7)
-#define RCC_AHB3RSTSETR_HSEMRST B(11)
-#define RCC_AHB3RSTSETR_IPCCRST B(12)
-
-/******************* Bit definition for RCC_AHB3RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_AHB3RSTCLRR_DCMIRST B(0)
-#define RCC_AHB3RSTCLRR_HASH2RST B(5)
-#define RCC_AHB3RSTCLRR_RNG2RST B(6)
-#define RCC_AHB3RSTCLRR_CRC2RST B(7)
-#define RCC_AHB3RSTCLRR_HSEMRST B(11)
-#define RCC_AHB3RSTCLRR_IPCCRST B(12)
-
-/******************* Bit definition for RCC_AHB4RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_AHB4RSTSETR_GPIOARST B(0)
-#define RCC_AHB4RSTSETR_GPIOBRST B(1)
-#define RCC_AHB4RSTSETR_GPIOCRST B(2)
-#define RCC_AHB4RSTSETR_GPIODRST B(3)
-#define RCC_AHB4RSTSETR_GPIOERST B(4)
-#define RCC_AHB4RSTSETR_GPIOFRST B(5)
-#define RCC_AHB4RSTSETR_GPIOGRST B(6)
-#define RCC_AHB4RSTSETR_GPIOHRST B(7)
-#define RCC_AHB4RSTSETR_GPIOIRST B(8)
-#define RCC_AHB4RSTSETR_GPIOJRST B(9)
-#define RCC_AHB4RSTSETR_GPIOKRST B(10)
-
-/******************* Bit definition for RCC_AHB4RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_AHB4RSTCLRR_GPIOARST B(0)
-#define RCC_AHB4RSTCLRR_GPIOBRST B(1)
-#define RCC_AHB4RSTCLRR_GPIOCRST B(2)
-#define RCC_AHB4RSTCLRR_GPIODRST B(3)
-#define RCC_AHB4RSTCLRR_GPIOERST B(4)
-#define RCC_AHB4RSTCLRR_GPIOFRST B(5)
-#define RCC_AHB4RSTCLRR_GPIOGRST B(6)
-#define RCC_AHB4RSTCLRR_GPIOHRST B(7)
-#define RCC_AHB4RSTCLRR_GPIOIRST B(8)
-#define RCC_AHB4RSTCLRR_GPIOJRST B(9)
-#define RCC_AHB4RSTCLRR_GPIOKRST B(10)
-
-/******************* Bit definition for RCC_APB4RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_APB4RSTSETR_LTDCRST B(0)
-#define RCC_APB4RSTSETR_DDRPERFMRST B(8)
-#define RCC_APB4RSTSETR_USBPHYRST B(16)
-
-/******************* Bit definition for RCC_APB4RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_APB4RSTCLRR_LTDCRST B(0)
-#define RCC_APB4RSTCLRR_DDRPERFMRST B(8)
-#define RCC_APB4RSTCLRR_USBPHYRST B(16)
-
-/******************* Bit definition for RCC_APB5RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_APB5RSTSETR_SPI6RST B(0)
-#define RCC_APB5RSTSETR_I2C4RST B(2)
-#define RCC_APB5RSTSETR_I2C6RST B(3)
-#define RCC_APB5RSTSETR_USART1RST B(4)
-#define RCC_APB5RSTSETR_STGENRST B(20)
-
-/******************* Bit definition for RCC_APB5RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_APB5RSTCLRR_SPI6RST B(0)
-#define RCC_APB5RSTCLRR_I2C4RST B(2)
-#define RCC_APB5RSTCLRR_I2C6RST B(3)
-#define RCC_APB5RSTCLRR_USART1RST B(4)
-#define RCC_APB5RSTCLRR_STGENRST B(20)
-
-/******************* Bit definition for RCC_AHB5RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_AHB5RSTSETR_GPIOZRST B(0)
-#define RCC_AHB5RSTSETR_HASH1RST B(5)
-#define RCC_AHB5RSTSETR_RNG1RST B(6)
-#define RCC_AHB5RSTSETR_AXIMCRST B(16)
-
-/******************* Bit definition for RCC_AHB5RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_AHB5RSTCLRR_GPIOZRST B(0)
-#define RCC_AHB5RSTCLRR_HASH1RST B(5)
-#define RCC_AHB5RSTCLRR_RNG1RST B(6)
-#define RCC_AHB5RSTCLRR_AXIMCRST B(16)
-
-/******************* Bit definition for RCC_AHB6RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_AHB6RSTSETR_ETHMACRST B(10)
-#define RCC_AHB6RSTSETR_FMCRST B(12)
-#define RCC_AHB6RSTSETR_QSPIRST B(14)
-#define RCC_AHB6RSTSETR_SDMMC1RST B(16)
-#define RCC_AHB6RSTSETR_SDMMC2RST B(17)
-#define RCC_AHB6RSTSETR_CRC1RST B(20)
-#define RCC_AHB6RSTSETR_USBHRST B(24)
-
-/******************* Bit definition for RCC_AHB6RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_AHB6RSTCLRR_ETHMACRST B(10)
-#define RCC_AHB6RSTCLRR_FMCRST B(12)
-#define RCC_AHB6RSTCLRR_QSPIRST B(14)
-#define RCC_AHB6RSTCLRR_SDMMC1RST B(16)
-#define RCC_AHB6RSTCLRR_SDMMC2RST B(17)
-#define RCC_AHB6RSTCLRR_CRC1RST B(20)
-#define RCC_AHB6RSTCLRR_USBHRST B(24)
-
-/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/
-/*!< This register is used to activate the reset of the corresponding peripheral */
-#define RCC_TZAHB6RSTSETR_MDMARST B(0)
-
-/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/
-/*!< This register is used to release the reset of the corresponding peripheral */
-#define RCC_TZAHB6RSTCLRR_MDMARST B(0)
-
-/******************* Bit definition for RCC_MP_GRSTCSETR register ************/
-/*!< This register is used by the MPU in order to generate either a MCU reset
- * or a system reset or a reset of one of the two MPU processors. Writing '0' has
- * no effect, reading will return the effective values of the corresponding bits.
- * Writing a '1' activates the reset */
-#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U)
-#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */
-#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */
-#define RCC_MP_GRSTCSETR_MCURST_Pos (1U)
-#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */
-#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */
-#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U)
-#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */
-#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/
-#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U)
-#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */
-#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/
-
-/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_APB1ENSETR_TIM2EN B(0)
-#define RCC_MC_APB1ENSETR_TIM3EN B(1)
-#define RCC_MC_APB1ENSETR_TIM4EN B(2)
-#define RCC_MC_APB1ENSETR_TIM5EN B(3)
-#define RCC_MC_APB1ENSETR_TIM6EN B(4)
-#define RCC_MC_APB1ENSETR_TIM7EN B(5)
-#define RCC_MC_APB1ENSETR_TIM12EN B(6)
-#define RCC_MC_APB1ENSETR_TIM13EN B(7)
-#define RCC_MC_APB1ENSETR_TIM14EN B(8)
-#define RCC_MC_APB1ENSETR_LPTIM1EN B(9)
-#define RCC_MC_APB1ENSETR_SPI2EN B(11)
-#define RCC_MC_APB1ENSETR_SPI3EN B(12)
-#define RCC_MC_APB1ENSETR_USART2EN B(14)
-#define RCC_MC_APB1ENSETR_USART3EN B(15)
-#define RCC_MC_APB1ENSETR_UART4EN B(16)
-#define RCC_MC_APB1ENSETR_UART5EN B(17)
-#define RCC_MC_APB1ENSETR_UART7EN B(18)
-#define RCC_MC_APB1ENSETR_UART8EN B(19)
-#define RCC_MC_APB1ENSETR_I2C1EN B(21)
-#define RCC_MC_APB1ENSETR_I2C2EN B(22)
-#define RCC_MC_APB1ENSETR_I2C3EN B(23)
-#define RCC_MC_APB1ENSETR_I2C5EN B(24)
-#define RCC_MC_APB1ENSETR_SPDIFEN B(26)
-#define RCC_MC_APB1ENSETR_CECEN B(27)
-#define RCC_MC_APB1ENSETR_WWDG1EN B(28)
-#define RCC_MC_APB1ENSETR_DAC12EN B(29)
-#define RCC_MC_APB1ENSETR_MDIOSEN B(31)
-
-/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
-peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_APB1ENCLRR_TIM2EN B(0)
-#define RCC_MC_APB1ENCLRR_TIM3EN B(1)
-#define RCC_MC_APB1ENCLRR_TIM4EN B(2)
-#define RCC_MC_APB1ENCLRR_TIM5EN B(3)
-#define RCC_MC_APB1ENCLRR_TIM6EN B(4)
-#define RCC_MC_APB1ENCLRR_TIM7EN B(5)
-#define RCC_MC_APB1ENCLRR_TIM12EN B(6)
-#define RCC_MC_APB1ENCLRR_TIM13EN B(7)
-#define RCC_MC_APB1ENCLRR_TIM14EN B(8)
-#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9)
-#define RCC_MC_APB1ENCLRR_SPI2EN B(11)
-#define RCC_MC_APB1ENCLRR_SPI3EN B(12)
-#define RCC_MC_APB1ENCLRR_USART2EN B(14)
-#define RCC_MC_APB1ENCLRR_USART3EN B(15)
-#define RCC_MC_APB1ENCLRR_UART4EN B(16)
-#define RCC_MC_APB1ENCLRR_UART5EN B(17)
-#define RCC_MC_APB1ENCLRR_UART7EN B(18)
-#define RCC_MC_APB1ENCLRR_UART8EN B(19)
-#define RCC_MC_APB1ENCLRR_I2C1EN B(21)
-#define RCC_MC_APB1ENCLRR_I2C2EN B(22)
-#define RCC_MC_APB1ENCLRR_I2C3EN B(23)
-#define RCC_MC_APB1ENCLRR_I2C5EN B(24)
-#define RCC_MC_APB1ENCLRR_SPDIFEN B(26)
-#define RCC_MC_APB1ENCLRR_CECEN B(27)
-#define RCC_MC_APB1ENCLRR_WWDG1EN B(28)
-#define RCC_MC_APB1ENCLRR_DAC12EN B(29)
-#define RCC_MC_APB1ENCLRR_MDIOSEN B(31)
-
-/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_APB2ENSETR_TIM1EN B(0)
-#define RCC_MC_APB2ENSETR_TIM8EN B(1)
-#define RCC_MC_APB2ENSETR_TIM15EN B(2)
-#define RCC_MC_APB2ENSETR_TIM16EN B(3)
-#define RCC_MC_APB2ENSETR_TIM17EN B(4)
-#define RCC_MC_APB2ENSETR_SPI1EN B(8)
-#define RCC_MC_APB2ENSETR_SPI4EN B(9)
-#define RCC_MC_APB2ENSETR_SPI5EN B(10)
-#define RCC_MC_APB2ENSETR_USART6EN B(13)
-#define RCC_MC_APB2ENSETR_SAI1EN B(16)
-#define RCC_MC_APB2ENSETR_SAI2EN B(17)
-#define RCC_MC_APB2ENSETR_SAI3EN B(18)
-#define RCC_MC_APB2ENSETR_DFSDMEN B(20)
-#define RCC_MC_APB2ENSETR_ADFSDMEN B(21)
-
-/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_APB2ENCLRR_TIM1EN B(0)
-#define RCC_MC_APB2ENCLRR_TIM8EN B(1)
-#define RCC_MC_APB2ENCLRR_TIM15EN B(2)
-#define RCC_MC_APB2ENCLRR_TIM16EN B(3)
-#define RCC_MC_APB2ENCLRR_TIM17EN B(4)
-#define RCC_MC_APB2ENCLRR_SPI1EN B(8)
-#define RCC_MC_APB2ENCLRR_SPI4EN B(9)
-#define RCC_MC_APB2ENCLRR_SPI5EN B(10)
-#define RCC_MC_APB2ENCLRR_USART6EN B(13)
-#define RCC_MC_APB2ENCLRR_SAI1EN B(16)
-#define RCC_MC_APB2ENCLRR_SAI2EN B(17)
-#define RCC_MC_APB2ENCLRR_SAI3EN B(18)
-#define RCC_MC_APB2ENCLRR_DFSDMEN B(20)
-#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21)
-
-/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_APB3ENSETR_LPTIM2EN B(0)
-#define RCC_MC_APB3ENSETR_LPTIM3EN B(1)
-#define RCC_MC_APB3ENSETR_LPTIM4EN B(2)
-#define RCC_MC_APB3ENSETR_LPTIM5EN B(3)
-#define RCC_MC_APB3ENSETR_SAI4EN B(8)
-#define RCC_MC_APB3ENSETR_SYSCFGEN B(11)
-#define RCC_MC_APB3ENSETR_VREFEN B(13)
-#define RCC_MC_APB3ENSETR_DTSEN B(16)
-#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17)
-#define RCC_MC_APB3ENSETR_HDPEN B(20)
-
-/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0)
-#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1)
-#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2)
-#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3)
-#define RCC_MC_APB3ENCLRR_SAI4EN B(8)
-#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11)
-#define RCC_MC_APB3ENCLRR_VREFEN B(13)
-#define RCC_MC_APB3ENCLRR_DTSEN B(16)
-#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17)
-#define RCC_MC_APB3ENCLRR_HDPEN B(20)
-
-/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_APB4ENSETR_LTDCEN B(0)
-#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8)
-#define RCC_MC_APB4ENSETR_USBPHYEN B(16)
-#define RCC_MC_APB4ENSETR_STGENROEN B(20)
-
-/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
-#define RCC_MP_APB4ENSETR_LTDCEN B(0)
-#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15)
-#define RCC_MP_APB4ENSETR_USBPHYEN B(16)
-#define RCC_MP_APB4ENSETR_STGENROEN B(20)
-
-/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_APB4ENCLRR_LTDCEN B(0)
-#define RCC_MC_APB4ENCLRR_USBPHYEN B(16)
-#define RCC_MC_APB4ENCLRR_STGENROEN B(20)
-
-/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MP_APB4ENCLRR_LTDCEN B(0)
-#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15)
-#define RCC_MP_APB4ENCLRR_USBPHYEN B(16)
-#define RCC_MP_APB4ENCLRR_STGENROEN B(20)
-
-/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_APB5ENSETR_SPI6EN B(0)
-#define RCC_MC_APB5ENSETR_I2C4EN B(2)
-#define RCC_MC_APB5ENSETR_I2C6EN B(3)
-#define RCC_MC_APB5ENSETR_USART1EN B(4)
-#define RCC_MC_APB5ENSETR_RTCAPBEN B(8)
-#define RCC_MC_APB5ENSETR_TZC1EN B(11)
-#define RCC_MC_APB5ENSETR_TZC2EN B(12)
-#define RCC_MC_APB5ENSETR_TZPCEN B(13)
-#define RCC_MC_APB5ENSETR_BSECEN B(16)
-#define RCC_MC_APB5ENSETR_STGENEN B(20)
-
-/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MPU.
- * This bit can also be used to test if IWDG1 peripheral clock is enabled
- * If TZEN = 1, this register can only be modified in secure mode. */
-#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15)
-
-/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_APB5ENCLRR_SPI6EN B(0)
-#define RCC_MC_APB5ENCLRR_I2C4EN B(2)
-#define RCC_MC_APB5ENCLRR_I2C6EN B(3)
-#define RCC_MC_APB5ENCLRR_USART1EN B(4)
-#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8)
-#define RCC_MC_APB5ENCLRR_TZC1EN B(11)
-#define RCC_MC_APB5ENCLRR_TZC2EN B(12)
-#define RCC_MC_APB5ENCLRR_TZPCEN B(13)
-#define RCC_MC_APB5ENCLRR_BSECEN B(16)
-#define RCC_MC_APB5ENCLRR_STGENEN B(20)
-
-/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AHB5ENSETR_GPIOZEN B(0)
-#define RCC_MC_AHB5ENSETR_HASH1EN B(5)
-#define RCC_MC_AHB5ENSETR_RNG1EN B(6)
-#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8)
-#define RCC_MC_AHB5ENSETR_AXIMC B(16)
-
-/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0)
-#define RCC_MC_AHB5ENCLRR_HASH1EN B(5)
-#define RCC_MC_AHB5ENCLRR_RNG1EN B(6)
-#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8)
-
-/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AHB6ENSETR_MDMAEN B(0)
-#define RCC_MC_AHB6ENSETR_ETHCKEN B(7)
-#define RCC_MC_AHB6ENSETR_ETHTXEN B(8)
-#define RCC_MC_AHB6ENSETR_ETHRXEN B(9)
-#define RCC_MC_AHB6ENSETR_ETHMACEN B(10)
-#define RCC_MC_AHB6ENSETR_FMCEN B(12)
-#define RCC_MC_AHB6ENSETR_QSPIEN B(14)
-#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16)
-#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17)
-#define RCC_MC_AHB6ENSETR_CRC1EN B(20)
-#define RCC_MC_AHB6ENSETR_USBHEN B(24)
-
-/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AHB6ENCLRR_MDMAEN B(0)
-#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7)
-#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8)
-#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9)
-#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10)
-#define RCC_MC_AHB6ENCLRR_FMCEN B(12)
-#define RCC_MC_AHB6ENCLRR_QSPIEN B(14)
-#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16)
-#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17)
-#define RCC_MC_AHB6ENCLRR_CRC1EN B(20)
-#define RCC_MC_AHB6ENCLRR_USBHEN B(24)
-
-/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
-#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0)
-
-/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MPU */
-#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0)
-
-/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AHB2ENSETR_DMA1EN B(0)
-#define RCC_MC_AHB2ENSETR_DMA2EN B(1)
-#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2)
-#define RCC_MC_AHB2ENSETR_ADC12EN B(5)
-#define RCC_MC_AHB2ENSETR_USBOEN B(8)
-#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16)
-
-/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AHB2ENCLRR_DMA1EN B(0)
-#define RCC_MC_AHB2ENCLRR_DMA2EN B(1)
-#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2)
-#define RCC_MC_AHB2ENCLRR_ADC12EN B(5)
-#define RCC_MC_AHB2ENCLRR_USBOEN B(8)
-#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16)
-
-/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AHB3ENSETR_DCMIEN B(0)
-#define RCC_MC_AHB3ENSETR_HASH2EN B(5)
-#define RCC_MC_AHB3ENSETR_RNG2EN B(6)
-#define RCC_MC_AHB3ENSETR_CRC2EN B(7)
-#define RCC_MC_AHB3ENSETR_HSEMEN B(11)
-#define RCC_MC_AHB3ENSETR_IPCCEN B(12)
-
-/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AHB3ENCLRR_DCMIEN B(0)
-#define RCC_MC_AHB3ENCLRR_HASH2EN B(5)
-#define RCC_MC_AHB3ENCLRR_RNG2EN B(6)
-#define RCC_MC_AHB3ENCLRR_CRC2EN B(7)
-#define RCC_MC_AHB3ENCLRR_HSEMEN B(11)
-#define RCC_MC_AHB3ENCLRR_IPCCEN B(12)
-
-/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AHB4ENSETR_GPIOAEN B(0)
-#define RCC_MC_AHB4ENSETR_GPIOBEN B(1)
-#define RCC_MC_AHB4ENSETR_GPIOCEN B(2)
-#define RCC_MC_AHB4ENSETR_GPIODEN B(3)
-#define RCC_MC_AHB4ENSETR_GPIOEEN B(4)
-#define RCC_MC_AHB4ENSETR_GPIOFEN B(5)
-#define RCC_MC_AHB4ENSETR_GPIOGEN B(6)
-#define RCC_MC_AHB4ENSETR_GPIOHEN B(7)
-#define RCC_MC_AHB4ENSETR_GPIOIEN B(8)
-#define RCC_MC_AHB4ENSETR_GPIOJEN B(9)
-#define RCC_MC_AHB4ENSETR_GPIOKEN B(10)
-
-/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0)
-#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1)
-#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2)
-#define RCC_MC_AHB4ENCLRR_GPIODEN B(3)
-#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4)
-#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5)
-#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6)
-#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7)
-#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8)
-#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9)
-#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10)
-
-/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_AXIMENSETR_SYSRAMEN B(0)
-
-/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0)
-
-/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/
-/*!< This register is used to set the peripheral clock enable bit of the corresponding
- * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
-#define RCC_MC_MLAHBENSETR_RETRAMEN B(4)
-
-/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/
-/*!< This register is used to clear the peripheral clock enable bit of the corresponding
- * peripheral. It shall be used to deallocate a peripheral from MCU */
-#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4)
-
-
-/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0)
-#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1)
-#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2)
-#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3)
-#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4)
-#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5)
-#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6)
-#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7)
-#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8)
-#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9)
-#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11)
-#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12)
-#define RCC_MC_APB1LPENSETR_USART2LPEN B(14)
-#define RCC_MC_APB1LPENSETR_USART3LPEN B(15)
-#define RCC_MC_APB1LPENSETR_UART4LPEN B(16)
-#define RCC_MC_APB1LPENSETR_UART5LPEN B(17)
-#define RCC_MC_APB1LPENSETR_UART7LPEN B(18)
-#define RCC_MC_APB1LPENSETR_UART8LPEN B(19)
-#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21)
-#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22)
-#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23)
-#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24)
-#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26)
-#define RCC_MC_APB1LPENSETR_CECLPEN B(27)
-#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28)
-#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29)
-#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31)
-
-/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0)
-#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1)
-#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2)
-#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3)
-#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4)
-#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5)
-#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6)
-#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7)
-#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8)
-#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9)
-#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11)
-#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12)
-#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14)
-#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15)
-#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16)
-#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17)
-#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18)
-#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19)
-#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21)
-#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22)
-#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23)
-#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24)
-#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26)
-#define RCC_MC_APB1LPENCLRR_CECLPEN B(27)
-#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28)
-#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29)
-#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31)
-
-/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0)
-#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1)
-#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2)
-#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3)
-#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4)
-#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8)
-#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9)
-#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10)
-#define RCC_MC_APB2LPENSETR_USART6LPEN B(13)
-#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16)
-#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17)
-#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18)
-#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20)
-#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21)
-
-/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0)
-#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1)
-#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2)
-#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3)
-#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4)
-#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8)
-#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9)
-#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10)
-#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13)
-#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16)
-#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17)
-#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18)
-#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20)
-#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21)
-
-/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0)
-#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1)
-#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2)
-#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3)
-#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8)
-#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11)
-#define RCC_MC_APB3LPENSETR_VREFLPEN B(13)
-#define RCC_MC_APB3LPENSETR_DTSLPEN B(16)
-#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17)
-
-/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0)
-#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1)
-#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2)
-#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3)
-#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8)
-#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11)
-#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13)
-#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16)
-#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17)
-
-/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0)
-#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16)
-#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20)
-#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21)
-
-/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/
-/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0)
-#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15)
-#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16)
-#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20)
-#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21)
-
-/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0)
-#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16)
-#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20)
-#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21)
-
-/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0)
-#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15)
-#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16)
-#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20)
-#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21)
-
-/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0)
-#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2)
-#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3)
-#define RCC_MC_APB5LPENSETR_USART1LPEN B(4)
-#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8)
-#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11)
-#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12)
-#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13)
-#define RCC_MC_APB5LPENSETR_BSECLPEN B(16)
-#define RCC_MC_APB5LPENSETR_STGENLPEN B(20)
-#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21)
-
-
-/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0)
-#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2)
-#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3)
-#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4)
-#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8)
-#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11)
-#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12)
-#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13)
-#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16)
-#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20)
-#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21)
-
-/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0)
-#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5)
-#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6)
-#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8)
-
-/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0)
-#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5)
-#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6)
-#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8)
-
-/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0)
-#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7)
-#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8)
-#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9)
-#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10)
-#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11)
-#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12)
-#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14)
-#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16)
-#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17)
-#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20)
-#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24)
-
-/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0)
-#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7)
-#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8)
-#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9)
-#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10)
-#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11)
-#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12)
-#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14)
-#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16)
-#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17)
-#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20)
-#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24)
-
-/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0)
-
-/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0)
-
-/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0)
-#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1)
-#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2)
-#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5)
-#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8)
-#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16)
-
-/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0)
-#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1)
-#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2)
-#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5)
-#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8)
-#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16)
-
-/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0)
-#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5)
-#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6)
-#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7)
-#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11)
-#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12)
-
-/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0)
-#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5)
-#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6)
-#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7)
-#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11)
-#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12)
-
-/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0)
-#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1)
-#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2)
-#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3)
-#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4)
-#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5)
-#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6)
-#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7)
-#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8)
-#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9)
-#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10)
-
-/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0)
-#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1)
-#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2)
-#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3)
-#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4)
-#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5)
-#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6)
-#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7)
-#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8)
-#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9)
-#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10)
-
-/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0)
-
-/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0)
-
-/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/
-/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
- * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
- * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
-#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0)
-#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1)
-#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2)
-#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4)
-
-/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/
-/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
- * peripheral. Writing '0' has no effect, reading will return the effective values of the
- * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
-#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0)
-#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1)
-#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2)
-#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4)
-
-
-/******************* Bit definition for RCC_BR_RSTSCLRR register ************/
-/*!< This register is used by the BOOTROM to check the reset source.
- * Writing "0" has no effect, reading will return the effective values of the corresponding
- * bits. Writing a '1' clears the corresponding bit to '0'
- *
- * @note In order to identify the reset source, the MPU application must use
- * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application
- * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).
- * @note This register except MPUP[1:0]RSTF flags is located into VDD domain,
- * and is reset by por_rst reset.
- * @note If TZEN = '1', this register can only be modified in secure mode.
- */
-#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U)
-#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
-#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
-
-#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U)
-#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
-#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
-
-#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U)
-#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
-#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
-
-#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U)
-#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
-#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
-
-#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U)
-#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
-#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
-
-#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U)
-#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
-#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+/************* Bit definition for RCC_MP_APB1LPENSETR register **************/
+#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U)
+#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U)
+#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U)
+#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U)
+#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U)
+#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U)
+#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U)
+#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U)
+#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U)
+#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U)
+#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U)
+#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U)
+#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U)
+#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U)
+#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U)
+#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U)
+#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U)
+#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U)
+#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */
+#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U)
+#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U)
+#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U)
+#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U)
+#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U)
+#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */
+#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U)
+#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U)
+#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U)
+#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */
+#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */
-#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U)
-#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
-#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/
+#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U)
+#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U)
+#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U)
+#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U)
+#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U)
+#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U)
+#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U)
+#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U)
+#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U)
+#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U)
+#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U)
+#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U)
+#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U)
+#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U)
+#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U)
+#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U)
+#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U)
+#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U)
+#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */
+#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U)
+#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U)
+#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U)
+#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U)
+#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U)
+#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */
+#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U)
+#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U)
+#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U)
+#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */
+#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */
-#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U)
-#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
-#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+/************* Bit definition for RCC_MP_APB2LPENSETR register **************/
+#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U)
+#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U)
+#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U)
+#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U)
+#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U)
+#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U)
+#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U)
+#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U)
+#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U)
+#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U)
+#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U)
+#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U)
+#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U)
+#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U)
+#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U)
+#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */
-#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U)
-#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
-#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/
+#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U)
+#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U)
+#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U)
+#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U)
+#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U)
+#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U)
+#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U)
+#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U)
+#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U)
+#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U)
+#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U)
+#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U)
+#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U)
+#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U)
+#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U)
+#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */
-#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U)
-#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
-#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
+/************* Bit definition for RCC_MP_APB3LPENSETR register **************/
+#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U)
+#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U)
+#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U)
+#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U)
+#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U)
+#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U)
+#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U)
+#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U)
+#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */
-#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U)
-#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
-#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
+/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/
+#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U)
+#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U)
+#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U)
+#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U)
+#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U)
+#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U)
+#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U)
+#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U)
+#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */
+/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/
+#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U)
+#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U)
+#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U)
+#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U)
+#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U)
+#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U)
+#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */
-/******************* Bit definition for RCC_MC_RSTSCLRR register ************/
-/*!< This register is used by the MCU to check the reset source.
- * Writing "0" has no effect, reading will return the effective values of the corresponding
- * bits. Writing a "1" clears the corresponding bit to 0
- * @note This register is located into VDD domain, and is reset by rst_por reset.
- */
-#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U)
-#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
-#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
+/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/
+#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U)
+#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U)
+#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U)
+#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U)
+#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U)
+#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U)
+#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U)
-#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
-#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
+/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/
+#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U)
+#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U)
+#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U)
+#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U)
+#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U)
+#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U)
+#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U)
+#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U)
-#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
-#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
+/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/
+#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U)
+#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U)
+#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U)
+#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U)
+#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U)
+#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U)
+#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U)
+#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U)
-#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
-#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/
+#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U)
+#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U)
+#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U)
+#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U)
+#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U)
+#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U)
+#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U)
+#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U)
+#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U)
+#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U)
+#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U)
+#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U)
-#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
-#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
+/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/
+#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U)
+#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U)
+#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U)
+#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U)
+#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U)
+#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U)
+#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U)
+#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U)
+#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U)
+#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U)
+#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U)
+#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U)
-#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */
-#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/
+/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/
+#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U)
+#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U)
-#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
-#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/
+#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U)
+#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U)
-#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
-#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/
+#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U)
+#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U)
+#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U)
+#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U)
+#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U)
-#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
-#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/
+#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U)
+#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U)
+#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U)
+#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */
+#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U)
+#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U)
-#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
-#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+/************* Bit definition for RCC_MC_APB1LPENSETR register **************/
+#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U)
+#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U)
+#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U)
+#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U)
+#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U)
+#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U)
+#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U)
+#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U)
+#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U)
+#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U)
+#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U)
+#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U)
+#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U)
+#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U)
+#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U)
+#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U)
+#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U)
+#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U)
+#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */
+#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U)
+#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U)
+#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U)
+#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U)
+#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U)
+#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */
+#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U)
+#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U)
+#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U)
+#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U)
+#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */
+#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */
-#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U)
-#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */
-#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/
+/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/
+#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U)
+#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U)
+#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U)
+#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U)
+#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U)
+#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U)
+#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U)
+#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U)
+#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U)
+#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U)
+#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U)
+#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U)
+#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U)
+#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U)
+#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U)
+#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U)
+#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U)
+#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U)
+#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */
+#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U)
+#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U)
+#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U)
+#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U)
+#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U)
+#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */
+#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U)
+#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U)
+#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U)
+#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U)
+#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */
+#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */
-/******************* Bit definition for RCC_MP_RSTSCLRR register ************/
-/*!< This register is used by the MPU to check the reset source. This register is updated
- * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or
- * exit from STANDBY or CSTANDBY.
- *
- * @note Writing '0' has no effect, reading will return the effective values of
- * the corresponding bits. Writing a '1' clears the corresponding bit to '0'.
- * @note The register is located in VDD_CORE.
- * @note If TZEN = '1', this register can only be modified in secure mode.
- */
-#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U)
-#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
-#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
+/************* Bit definition for RCC_MC_APB2LPENSETR register **************/
+#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U)
+#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U)
+#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U)
+#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U)
+#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U)
+#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U)
+#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U)
+#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U)
+#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U)
+#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U)
+#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U)
+#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U)
+#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U)
+#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U)
+#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U)
+#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U)
-#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
-#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
+/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/
+#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U)
+#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U)
+#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U)
+#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U)
+#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U)
+#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U)
+#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U)
+#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U)
+#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U)
+#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U)
+#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U)
+#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U)
+#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U)
+#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U)
+#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U)
+#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U)
-#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
-#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
+/************* Bit definition for RCC_MC_APB3LPENSETR register **************/
+#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U)
+#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U)
+#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U)
+#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U)
+#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U)
+#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U)
+#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U)
+#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U)
+#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U)
-#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
-#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/
+#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U)
+#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U)
+#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U)
+#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U)
+#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U)
+#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U)
+#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U)
+#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U)
+#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U)
-#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
-#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
+/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/
+#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U)
+#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U)
+#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U)
+#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U)
+#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U)
+#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U)
+#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U)
-#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
-#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/
+#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U)
+#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U)
+#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U)
+#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U)
+#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U)
+#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U)
+#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U)
-#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
-#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/
+#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U)
+#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U)
+#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U)
+#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U)
+#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U)
+#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U)
+#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U)
+#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U)
-#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
-#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/
+#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U)
+#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U)
+#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U)
+#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U)
+#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U)
+#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U)
+#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U)
+#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U)
-#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
-#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/
+#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U)
+#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U)
+#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U)
+#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U)
+#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U)
+#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U)
+#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U)
+#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U)
+#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U)
+#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U)
+#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U)
+#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U)
-#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */
-#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/
+/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/
+#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U)
+#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U)
+#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U)
+#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U)
+#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U)
+#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U)
+#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U)
+#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U)
+#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U)
+#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U)
+#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */
+#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U)
+#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U)
-#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
-#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
+/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/
+#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U)
+#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U)
-#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
-#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
+/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/
+#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U)
+#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U)
-#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
-#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
+/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/
+#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U)
+#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U)
+#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U)
+#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U)
+#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */
-#define RCC_MP_RSTSCLRR_SPARE_Pos (15U)
-#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */
-#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/
+/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/
+#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U)
+#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U)
+#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U)
+#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */
+#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U)
+#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */
-/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/
-/*!< This register is used by the MPU in order to freeze the IWDGs clocks.
- * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby)
- * the MPU is allowed to write it once.
- * Writing "0" has no effect, reading will return the effective values of the corresponding
- * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be
- * modified in secure mode.
- */
-#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0)
-#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1)
+/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/
+#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */
+#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */
+#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */
+#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */
+#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U)
+#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */
+#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */
+#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */
+#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */
+#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */
+#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */
+#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U)
+#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */
+#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */
+/***************** Bit definition for RCC_MC_CIER register ******************/
+#define RCC_MC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */
+#define RCC_MC_CIER_LSERDYIE_Pos (1U)
+#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */
+#define RCC_MC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */
+#define RCC_MC_CIER_HSERDYIE_Pos (3U)
+#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */
+#define RCC_MC_CIER_CSIRDYIE_Pos (4U)
+#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */
+#define RCC_MC_CIER_PLL1DYIE_Pos (8U)
+#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
+#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */
+#define RCC_MC_CIER_PLL2DYIE_Pos (9U)
+#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
+#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */
+#define RCC_MC_CIER_PLL3DYIE_Pos (10U)
+#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
+#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */
+#define RCC_MC_CIER_PLL4DYIE_Pos (11U)
+#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
+#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */
+#define RCC_MC_CIER_LSECSSIE_Pos (16U)
+#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
+#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */
+#define RCC_MC_CIER_WKUPIE_Pos (20U)
+#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */
+#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */
-/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/
-/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks.
- * Writing "0" has no effect, reading will return the effective values of the corresponding
- * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only
- * be modified in secure mode.
- */
-#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0)
-#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1)
+/***************** Bit definition for RCC_MC_CIFR register ******************/
+#define RCC_MC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */
+#define RCC_MC_CIFR_LSERDYF_Pos (1U)
+#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */
+#define RCC_MC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */
+#define RCC_MC_CIFR_HSERDYF_Pos (3U)
+#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */
+#define RCC_MC_CIFR_CSIRDYF_Pos (4U)
+#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */
+#define RCC_MC_CIFR_PLL1DYF_Pos (8U)
+#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
+#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */
+#define RCC_MC_CIFR_PLL2DYF_Pos (9U)
+#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
+#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */
+#define RCC_MC_CIFR_PLL3DYF_Pos (10U)
+#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
+#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */
+#define RCC_MC_CIFR_PLL4DYF_Pos (11U)
+#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
+#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */
+#define RCC_MC_CIFR_LSECSSF_Pos (16U)
+#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
+#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */
+#define RCC_MC_CIFR_WKUPF_Pos (20U)
+#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */
+#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */
-/******************* Bit definition for RCC_VERR register ************/
-/*!< This register gives the IP version. */
-#define RCC_VERR_MINREV_Pos (0U)
-#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */
-#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk
-#define RCC_VERR_MAJREV_Pos (4U)
-#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
-#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk
+/******************* Bit definition for RCC_VERR register *******************/
+#define RCC_VERR_MINREV_Pos (0U)
+#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */
+#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */
+#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */
+#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */
+#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */
+#define RCC_VERR_MAJREV_Pos (4U)
+#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */
+#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */
+#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */
+#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */
+#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */
-/******************* Bit definition for RCC_IDR register ************/
-/*!< This register gives the unique identifier of the RCC */
-#define RCC_VERR_ID_Pos (0U)
-#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */
-#define RCC_VERR_ID RCC_VERR_ID_Msk
+/******************* Bit definition for RCC_IDR register ********************/
+#define RCC_IDR_ID_Pos (0U)
+#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */
+#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */
+#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */
+#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */
+#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */
+#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */
+#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */
+#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */
+#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */
+#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */
+#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */
+#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */
+#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */
+#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */
+#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */
+#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */
+#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */
+#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */
+#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */
+#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */
+#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */
+#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */
+#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */
+#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */
+#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */
+#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */
+#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */
+#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */
+#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */
+#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */
+#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */
+#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */
+#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */
-/******************* Bit definition for RCC_IDR register ************/
-/*!< This register gives the decoding space, which is for the RCC of 4 kB */
-#define RCC_VERR_SIDR_Pos (0U)
-#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */
-#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk
+/******************* Bit definition for RCC_SIDR register *******************/
+#define RCC_SIDR_SID_Pos (0U)
+#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */
+#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */
+#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */
+#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */
+#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */
+#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */
+#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */
+#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */
+#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */
+#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */
+#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */
+#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */
+#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */
+#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */
+#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */
+#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */
+#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */
+#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */
+#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */
+#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */
+#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */
+#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */
+#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */
+#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */
+#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */
+#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */
+#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */
+#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */
+#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */
+#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */
+#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */
+#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */
+#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
@@ -21179,7 +28517,6 @@
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
-
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
@@ -21793,42 +29130,42 @@
/******************** Bits definition for TAMP_CR2 register ***************/
-#define TAMP_CR2_TAMPNOERASE_Pos (0U)
-#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */
-#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk
-#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
-#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
-#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
-#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
-#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
-#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
-#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
-#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
-#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMPMSK_Pos (16U)
-#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */
-#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk
-#define TAMP_CR2_TAMP1MSK_Pos (16U)
-#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
-#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
-#define TAMP_CR2_TAMP2MSK_Pos (17U)
-#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
-#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
-#define TAMP_CR2_TAMP3MSK_Pos (18U)
-#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
-#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
-#define TAMP_CR2_TAMPTRG_Pos (24U)
-#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */
-#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk
-#define TAMP_CR2_TAMP1TRG_Pos (24U)
-#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
-#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
-#define TAMP_CR2_TAMP2TRG_Pos (25U)
-#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
-#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
-#define TAMP_CR2_TAMP3TRG_Pos (26U)
-#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
-#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
+#define TAMP_CR2_TAMPNOERASE_Pos (0U)
+#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */
+#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk
+#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
+#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
+#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
+#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
+#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
+#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
+#define TAMP_CR2_TAMPMSK_Pos (16U)
+#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */
+#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk
+#define TAMP_CR2_TAMP1MSK_Pos (16U)
+#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos (17U)
+#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos (18U)
+#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_TAMPTRG_Pos (24U)
+#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */
+#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk
+#define TAMP_CR2_TAMP1TRG_Pos (24U)
+#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos (25U)
+#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos (26U)
+#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
+#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
@@ -21852,78 +29189,81 @@
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
+
/******************** Bits definition for TAMP_ATCR1 register ***************/
-#define TAMP_ATCR1_TAMPAM_Pos (0U)
-#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */
-#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk
-#define TAMP_ATCR1_TAMP1AM_Pos (0U)
-#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
-#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
-#define TAMP_ATCR1_TAMP2AM_Pos (1U)
-#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
-#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
-#define TAMP_ATCR1_TAMP3AM_Pos (2U)
-#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
-#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
-#define TAMP_ATCR1_TAMP4AM_Pos (3U)
-#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
-#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
-#define TAMP_ATCR1_TAMP5AM_Pos (4U)
-#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
-#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
-#define TAMP_ATCR1_TAMP6AM_Pos (6U)
-#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000020 */
-#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
-#define TAMP_ATCR1_TAMP7AM_Pos (6U)
-#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
-#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
-#define TAMP_ATCR1_TAMP8AM_Pos (7U)
-#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */
-#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk
-#define TAMP_ATCR1_ATOSEL1_Pos (8U)
-#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
-#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
-#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
-#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
-#define TAMP_ATCR1_ATOSEL2_Pos (10U)
-#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
-#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
-#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
-#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
-#define TAMP_ATCR1_ATOSEL3_Pos (12U)
-#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
-#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
-#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
-#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
-#define TAMP_ATCR1_ATOSEL4_Pos (14U)
-#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
-#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
-#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
-#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
-#define TAMP_ATCR1_ATCKSEL_Pos (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
-#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
-#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
-#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
-#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
-#define TAMP_ATCR1_ATPER_Pos (24U)
-#define TAMP_ATCR1_ATPER_Msk (0x7UL <<TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
-#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
-#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
-#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
-#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
-#define TAMP_ATCR1_ATOSHARE_Pos (30U)
-#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
-#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
-#define TAMP_ATCR1_FLTEN_Pos (31U)
-#define TAMP_ATCR1_FLTEN_Msk (0x1UL <<TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
-#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
+#define TAMP_ATCR1_TAMPAM_Pos (0U)
+#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */
+#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk
+#define TAMP_ATCR1_TAMP1AM_Pos (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos (6U)
+#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000020 */
+#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_TAMP8AM_Pos (7U)
+#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */
+#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
+#define TAMP_ATCR1_ATPER_Pos (24U)
+#define TAMP_ATCR1_ATPER_Msk (0x7UL <<TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos (31U)
+#define TAMP_ATCR1_FLTEN_Msk (0x1UL <<TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
+
/******************** Bits definition for TAMP_ATSEEDR register ***************/
#define TAMP_ATSEEDR_SEED_Pos (0U)
#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFU << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
+
/******************** Bits definition for TAMP_ATOR register ***************/
#define TAMP_ATOR_PRNG_Pos (0U)
#define TAMP_ATOR_PRNG_Msk (0xFFU << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
@@ -21943,6 +29283,7 @@
#define TAMP_ATOR_INITS_Msk (0x1U << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
+
/******************** Bits definition for TAMP_SMCR register ***************/
#define TAMP_SMCR_BKPRWDPROT_Pos (0U)
#define TAMP_SMCR_BKPRWDPROT_Msk (0xFFU << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x000000FF */
@@ -21970,6 +29311,7 @@
#define TAMP_SMCR_TAMPDPROT_Msk (0x1U << TAMP_SMCR_TAMPDPROT_Pos) /*!< 0x80000000 */
#define TAMP_SMCR_TAMPDPROT TAMP_SMCR_TAMPDPROT_Msk
+
/******************** Bits definition for TAMP_IER register ***************/
#define TAMP_IER_TAMPIE_Pos (0U)
#define TAMP_IER_TAMPIE_Msk (0x7U << TAMP_IER_TAMPIE_Pos) /*!< 0x000000FF */
@@ -22020,7 +29362,7 @@
#define TAMP_SR_TAMP3F_Msk (0x1U << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMPF_Pos (16U)
-#define TAMP_SR_ITAMPF_Msk (0x9FU << TAMP_SR_ITAMPF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_SR_ITAMPF_Msk (0x9FU << TAMP_SR_ITAMPF_Pos) /*!< 0xFFFF0000 */
#define TAMP_SR_ITAMPF TAMP_SR_ITAMPF_Msk
#define TAMP_SR_ITAMP1F_Pos (16U)
#define TAMP_SR_ITAMP1F_Msk (0x1U << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
@@ -22056,7 +29398,7 @@
#define TAMP_MISR_TAMP3MF_Msk (0x1U << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMPMF_Pos (16U)
-#define TAMP_MISR_ITAMPMF_Msk (0x9FU << TAMP_MISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_MISR_ITAMPMF_Msk (0x9FU << TAMP_MISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
#define TAMP_MISR_ITAMPMF TAMP_MISR_ITAMPMF_Msk
#define TAMP_MISR_ITAMP1MF_Pos (16U)
#define TAMP_MISR_ITAMP1MF_Msk (0x1U << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
@@ -22128,7 +29470,7 @@
#define TAMP_SCR_CTAMP3F_Msk (0x1U << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMPF_Pos (16U)
-#define TAMP_SCR_CITAMPF_Msk (0x9FU << TAMP_SCR_CITAMPF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_SCR_CITAMPF_Msk (0x9FU << TAMP_SCR_CITAMPF_Pos) /*!< 0xFFFF0000 */
#define TAMP_SCR_CITAMPF TAMP_SCR_CITAMPF_Msk
#define TAMP_SCR_CITAMP1F_Pos (16U)
#define TAMP_SCR_CITAMP1F_Msk (0x1U << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
@@ -22151,9 +29493,9 @@
/******************** Bits definition for TAMP_OR register (TAMP_CFGR) ****************/
-#define TAMP_CFGR_OUT3_RMP_Pos (0U)
-#define TAMP_CFGR_OUT3_RMP_Msk (0x1U << TAMP_CFGR_OUT3_RMP_Pos) /*!< 0x00000001 */
-#define TAMP_CFGR_OUT3_RMP TAMP_CFGR_OUT3_RMP_Msk
+#define TAMP_CFGR_OUT3_RMP_Pos (0U)
+#define TAMP_CFGR_OUT3_RMP_Msk (0x1U << TAMP_CFGR_OUT3_RMP_Pos) /*!< 0x00000001 */
+#define TAMP_CFGR_OUT3_RMP TAMP_CFGR_OUT3_RMP_Msk
/******************** Bits definition for TAMP_COUNTR register ****************/
@@ -23289,12 +30631,12 @@
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
-#define SDMMC_STA_CPSMACT_Pos (12U)
-#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
-#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
-#define SDMMC_STA_DPSMACT_Pos (13U)
-#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
-#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
+#define SDMMC_STA_DPSMACT_Pos (12U)
+#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!< Data path state machine active */
+#define SDMMC_STA_CPSMACT_Pos (13U)
+#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@@ -23498,6 +30840,30 @@
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
+/***************** Bit definition for SDMMC_IDMABSIZER register **************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFFL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of bytes per buffer */
+
+/***************** Bit definition for SDMMC_IDMALAR register ***************/
+#define SDMMC_IDMALAR_IDMALA_Pos (0U)
+#define SDMMC_IDMALAR_IDMALA_Msk (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos) /*!< 0x00003FFF */
+#define SDMMC_IDMALAR_IDMALA SDMMC_IDMALAR_IDMALA_Msk /*!< Linked list item address offset */
+#define SDMMC_IDMALAR_ABR_Pos (29U)
+#define SDMMC_IDMALAR_ABR_Msk (0x1UL << SDMMC_IDMALAR_ABR_Pos) /*!< 0x20000000 */
+#define SDMMC_IDMALAR_ABR SDMMC_IDMALAR_ABR_Msk /*!< Acknowledge linked list buffer ready */
+#define SDMMC_IDMALAR_ULS_Pos (30U)
+#define SDMMC_IDMALAR_ULS_Msk (0x1UL << SDMMC_IDMALAR_ULS_Pos) /*!< 0x40000000 */
+#define SDMMC_IDMALAR_ULS SDMMC_IDMALAR_ULS_Msk /*!< Update Size from linked list */
+#define SDMMC_IDMALAR_ULA_Pos (31U)
+#define SDMMC_IDMALAR_ULA_Msk (0x1UL << SDMMC_IDMALAR_ULA_Pos) /*!< 0x80000000 */
+#define SDMMC_IDMALAR_ULA SDMMC_IDMALAR_ULA_Msk /*!< Update Address from linked list */
+
+/***************** Bit definition for SDMMC_IDMABAR register ***************/
+#define SDMMC_IDMABAR_IDMABAR_Pos (0U)
+#define SDMMC_IDMABAR_IDMABAR_Msk (0xFFFFFFFFUL << SDMMC_IDMABAR_IDMABAR_Pos)/*!< 0xFFFFFFFF */
+#define SDMMC_IDMABAR_IDMABAR SDMMC_IDMABAR_IDMABAR_Msk /*!< linked list memory base register */
+
/********************** Bit definition for SDMMC_VERR register *****************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
@@ -24254,6 +31620,8 @@
/* SYSCFG */
/* */
/******************************************************************************/
+/****************** Constant for SYSCFG *****************/
+#define SYSCFG_ANALOG_CONNECT_SUPPORT /*!< analog connection between the ANAx and PAx */
/****************** Bit definition for SYSCFG_BOOTR register *****************/
#define SYSCFG_BOOTR_BOOT0_Pos (0U)
#define SYSCFG_BOOTR_BOOT0_Msk (0x1U << SYSCFG_BOOTR_BOOT0_Pos) /*!< 0x00000001 */
@@ -24274,7 +31642,6 @@
#define SYSCFG_BOOTR_BOOT2_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT2_PD_Pos) /*!< 0x00000040 */
#define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-down disable */
-
/****************** Bit definition for SYSCFG_PMCSETR register ******************/
#define SYSCFG_PMCSETR_I2C1_FMP_Pos (0U)
#define SYSCFG_PMCSETR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C1_FMP_Pos) /*!< 0x00000001 */
@@ -24305,13 +31672,15 @@
#define SYSCFG_PMCSETR_ETH_CLK_SEL_Pos (16U)
#define SYSCFG_PMCSETR_ETH_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_CLK_SEL_Pos) /*!< 0x00010000 */
-#define SYSCFG_PMCSETR_ETH_CLK_SEL SYSCFG_PMCSETR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
+#define SYSCFG_PMCSETR_ETH_CLK_SEL SYSCFG_PMCSETR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK from RCC is used regardless AFMux */
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos (17U)
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos) /*!< 0x00020000 */
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk /*!< Ethernet 50MHz RMII clock selection */
+
#define SYSCFG_PMCSETR_ETH_SELMII_Pos (20U)
#define SYSCFG_PMCSETR_ETH_SELMII_Msk (0x1U << SYSCFG_PMCSETR_ETH_SELMII_Pos) /*!< 0x00100000 */
#define SYSCFG_PMCSETR_ETH_SELMII_SEL SYSCFG_PMCSETR_ETH_SELMII_Msk /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
+
#define SYSCFG_PMCSETR_ETH_SEL_Pos (21U)
#define SYSCFG_PMCSETR_ETH_SEL_Msk (0x7U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00E00000 */
#define SYSCFG_PMCSETR_ETH_SEL SYSCFG_PMCSETR_ETH_SEL_Msk /*!< Ethernet PHY Interface Selection */
@@ -24329,6 +31698,7 @@
#define SYSCFG_PMCSETR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCSETR_ANA1_SEL_Pos) /*!< 0x02000000 */
#define SYSCFG_PMCSETR_ANA1_SEL_SEL SYSCFG_PMCSETR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
+
/****************** Bit definition for SYSCFG_PMCCLRR register ******************/
#define SYSCFG_PMCCLRR_I2C1_FMP_Pos (0U)
#define SYSCFG_PMCCLRR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C1_FMP_Pos) /*!< 0x00000001 */
@@ -24383,39 +31753,42 @@
#define SYSCFG_PMCCLRR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ANA1_SEL_Pos) /*!< 0x02000000 */
#define SYSCFG_PMCCLRR_ANA1_SEL_SEL SYSCFG_PMCCLRR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
+
+
+
/****************** Bit definition for SYSCFG_IOCTRLSETR register *****************/
#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos (0U)
-#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
-#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos (1U)
-#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
-#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos (2U)
-#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
-#define SYSCFG_IOCTRLSETR_HSLVEN_ETH SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos (3U)
-#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
-#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos (4U)
-#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
-#define SYSCFG_IOCTRLSETR_HSLVEN_SPI SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
/****************** Bit definition for SYSCFG_IOCTRLCLRR register *****************/
#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos (0U)
-#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
-#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos (1U)
-#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
-#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos (2U)
-#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
-#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos (3U)
-#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
-#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos (4U)
-#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
-#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
/****************** Bit definition for SYSCFG_ICNR register ********************/
#define SYSCFG_ICNR_AXI_M0_Pos (0U)
@@ -24452,54 +31825,53 @@
/****************** Bit definition for SYSCFG_CMPCR register ********************/
#define SYSCFG_CMPCR_SW_CTRL_Pos (1U)
#define SYSCFG_CMPCR_SW_CTRL_Msk (0x1U << SYSCFG_CMPCR_SW_CTRL_Pos) /*!< 0x00000002 */
-#define SYSCFG_CMPCR_SW_CTRL SYSCFG_CMPCR_SW_CTRL_Msk /*!< Compensation Software Control */
+#define SYSCFG_CMPCR_SW_CTRL SYSCFG_CMPCR_SW_CTRL_Msk /*!< Compensation Software Control */
#define SYSCFG_CMPCR_READY_Pos (8U)
-#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
-#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!< Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!< Compensation cell ready flag */
#define SYSCFG_CMPCR_RANSRC_Pos (16U)
-#define SYSCFG_CMPCR_RANSRC_Msk (0xFU << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x000F0000 */
-#define SYSCFG_CMPCR_RANSRC SYSCFG_CMPCR_RANSRC_Msk /*!< NMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
-#define SYSCFG_CMPCR_RANSRC_0 (0x1U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00010000 */
-#define SYSCFG_CMPCR_RANSRC_1 (0x2U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00020000 */
-#define SYSCFG_CMPCR_RANSRC_2 (0x4U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00040000 */
-#define SYSCFG_CMPCR_RANSRC_3 (0x8U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00080000 */
+#define SYSCFG_CMPCR_RANSRC_Msk (0xFU << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x000F0000 */
+#define SYSCFG_CMPCR_RANSRC SYSCFG_CMPCR_RANSRC_Msk /*!< NMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
+#define SYSCFG_CMPCR_RANSRC_0 (0x1U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00010000 */
+#define SYSCFG_CMPCR_RANSRC_1 (0x2U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00020000 */
+#define SYSCFG_CMPCR_RANSRC_2 (0x4U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00040000 */
+#define SYSCFG_CMPCR_RANSRC_3 (0x8U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00080000 */
#define SYSCFG_CMPCR_RAPSRC_Pos (20U)
-#define SYSCFG_CMPCR_RAPSRC_Msk (0xFU << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00F00000 */
-#define SYSCFG_CMPCR_RAPSRC SYSCFG_CMPCR_RAPSRC_Msk /*!< PMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
-#define SYSCFG_CMPCR_RAPSRC_0 (0x1U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00100000 */
-#define SYSCFG_CMPCR_RAPSRC_1 (0x2U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00200000 */
-#define SYSCFG_CMPCR_RAPSRC_2 (0x4U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00400000 */
-#define SYSCFG_CMPCR_RAPSRC_3 (0x8U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00800000 */
+#define SYSCFG_CMPCR_RAPSRC_Msk (0xFU << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00F00000 */
+#define SYSCFG_CMPCR_RAPSRC SYSCFG_CMPCR_RAPSRC_Msk /*!< PMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
+#define SYSCFG_CMPCR_RAPSRC_0 (0x1U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00100000 */
+#define SYSCFG_CMPCR_RAPSRC_1 (0x2U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00200000 */
+#define SYSCFG_CMPCR_RAPSRC_2 (0x4U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00400000 */
+#define SYSCFG_CMPCR_RAPSRC_3 (0x8U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00800000 */
#define SYSCFG_CMPCR_ANSRC_Pos (24U)
-#define SYSCFG_CMPCR_ANSRC_Msk (0xFU << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x0F000000 */
-#define SYSCFG_CMPCR_ANSRC SYSCFG_CMPCR_ANSRC_Msk /*!< NMOS I/O Compensation value provided by compensation cell */
-#define SYSCFG_CMPCR_ANSRC_0 (0x1U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x01000000 */
-#define SYSCFG_CMPCR_ANSRC_1 (0x2U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x02000000 */
-#define SYSCFG_CMPCR_ANSRC_2 (0x4U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x04000000 */
-#define SYSCFG_CMPCR_ANSRC_3 (0x8U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x08000000 */
+#define SYSCFG_CMPCR_ANSRC_Msk (0xFU << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x0F000000 */
+#define SYSCFG_CMPCR_ANSRC SYSCFG_CMPCR_ANSRC_Msk /*!< NMOS I/O Compensation value provided by compensation cell */
+#define SYSCFG_CMPCR_ANSRC_0 (0x1U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x01000000 */
+#define SYSCFG_CMPCR_ANSRC_1 (0x2U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x02000000 */
+#define SYSCFG_CMPCR_ANSRC_2 (0x4U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x04000000 */
+#define SYSCFG_CMPCR_ANSRC_3 (0x8U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x08000000 */
#define SYSCFG_CMPCR_APSRC_Pos (28U)
-#define SYSCFG_CMPCR_APSRC_Msk (0xFU << SYSCFG_CMPCR_APSRC_Pos) /*!< 0xF0000000 */
-#define SYSCFG_CMPCR_APSRC SYSCFG_CMPCR_APSRC_Msk /*!< PMOS I/O Compensation value provided by compensation cell */
-#define SYSCFG_CMPCR_APSRC_0 (0x1U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x10000000 */
-#define SYSCFG_CMPCR_APSRC_1 (0x2U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x20000000 */
-#define SYSCFG_CMPCR_APSRC_2 (0x4U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x40000000 */
-#define SYSCFG_CMPCR_APSRC_3 (0x8U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x80000000 */
+#define SYSCFG_CMPCR_APSRC_Msk (0xFU << SYSCFG_CMPCR_APSRC_Pos) /*!< 0xF0000000 */
+#define SYSCFG_CMPCR_APSRC SYSCFG_CMPCR_APSRC_Msk /*!< PMOS I/O Compensation value provided by compensation cell */
+#define SYSCFG_CMPCR_APSRC_0 (0x1U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x10000000 */
+#define SYSCFG_CMPCR_APSRC_1 (0x2U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x20000000 */
+#define SYSCFG_CMPCR_APSRC_2 (0x4U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x40000000 */
+#define SYSCFG_CMPCR_APSRC_3 (0x8U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x80000000 */
/****************** Bit definition for SYSCFG_CMPENSETR register ********************/
#define SYSCFG_CMPENSETR_MPU_EN_Pos (0U)
#define SYSCFG_CMPENSETR_MPU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MPU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENSETR_MPU_EN SYSCFG_CMPENSETR_MPU_EN_Msk /*!< Compensation cell enable */
#define SYSCFG_CMPENSETR_MCU_EN_Pos (1U)
-#define SYSCFG_CMPENSETR_MCU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MCU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENSETR_MCU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MCU_EN_Pos) /*!< 0x00000002 */
#define SYSCFG_CMPENSETR_MCU_EN SYSCFG_CMPENSETR_MCU_EN_Msk /*!< Compensation cell enable */
-
/****************** Bit definition for SYSCFG_CMPENCLRR register ********************/
#define SYSCFG_CMPENCLRR_MPU_EN_Pos (0U)
#define SYSCFG_CMPENCLRR_MPU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MPU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENCLRR_MPU_EN SYSCFG_CMPENCLRR_MPU_EN_Msk /*!< Compensation cell disable */
-#define SYSCFG_CMPENCLRR_MCU_EN_Pos (0U)
-#define SYSCFG_CMPENCLRR_MCU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MCU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENCLRR_MCU_EN_Pos (1U)
+#define SYSCFG_CMPENCLRR_MCU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MCU_EN_Pos) /*!< 0x00000002 */
#define SYSCFG_CMPENCLRR_MCU_EN SYSCFG_CMPENCLRR_MCU_EN_Msk /*!< Compensation cell disable */
/****************** Bit definition for SYSCFG_CBR register ******************/
@@ -24510,6 +31882,15 @@
#define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!< PVD lock enable bit */
+
+
+
+
+
+
+
+
+
/********************** Bit definition for SYSCFG_VERR register *****************/
#define SYSCFG_VERR_MINREV_Pos (0U)
#define SYSCFG_VERR_MINREV_Msk (0xFU << SYSCFG_VERR_MINREV_Pos) /*!< 0x0000000F */
@@ -28244,7 +35625,6 @@
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
-
/******************************** MDMA Request Generator Instances **************/
#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
((INSTANCE) == MDMA_Channel1) || \
@@ -28891,7 +36271,7 @@
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
/******************************* BSEC VERSION ********************************/
-#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VER)
+#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* TZPC VERSION ********************************/
#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
@@ -28906,7 +36286,7 @@
#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
-/******************************* SYSCFG VERSION ********************************/
+/******************************* EXTI VERSION ********************************/
#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* PWR VERSION ********************************/
@@ -28952,10 +36332,10 @@
#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* RNG VERSION ********************************/
-#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER)
+#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* HASH VERSION ********************************/
-#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER)
+#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DCMI VERSION ********************************/
@@ -29004,7 +36384,7 @@
#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DAC VERSION ********************************/
-#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
+#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* USBPHYC VERSION ********************************/
diff --git a/stm32cube/stm32mp1xx/soc/stm32mp151axx_cm4.h b/stm32cube/stm32mp1xx/soc/stm32mp151axx_cm4.h
index 0dea237..909d7bd 100644
--- a/stm32cube/stm32mp1xx/soc/stm32mp151axx_cm4.h
+++ b/stm32cube/stm32mp1xx/soc/stm32mp151axx_cm4.h
@@ -295,8 +295,8 @@
__IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
__IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
uint32_t RESERVED10; /*!< Reserved, 0x0CC */
- __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */
- uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
+ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */
+ uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
__IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */
@@ -310,7 +310,6 @@
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
} ADC_Common_TypeDef;
@@ -396,6 +395,224 @@
__IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */
} DAC_TypeDef;
+/*
+ * @brief DDRCTRL block description (DDRCTRL)
+ */
+typedef struct
+{
+ __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */
+ __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */
+ uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
+ __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */
+ __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */
+ __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */
+ __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */
+ __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */
+ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
+ __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */
+ __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */
+ __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */
+ uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
+ __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */
+ uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
+ __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */
+ __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */
+ uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
+ __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */
+ uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
+ __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */
+ __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */
+ __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */
+ __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */
+ __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */
+ __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */
+ __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */
+ uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
+ __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */
+ uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
+ __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */
+ __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */
+ __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */
+ __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */
+ __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */
+ __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */
+ __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */
+ __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */
+ __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */
+ uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
+ __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */
+ __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */
+ uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
+ __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */
+ __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */
+ __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */
+ __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */
+ __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */
+ __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */
+ __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */
+ uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */
+ __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */
+ __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */
+ __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */
+ uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */
+ __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */
+ uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
+ __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */
+ uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */
+ __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */
+ uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
+ __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */
+ __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */
+ __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */
+ __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */
+ __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */
+ __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */
+ uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
+ __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */
+ __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */
+ __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */
+ uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
+ __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */
+ __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */
+ uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
+ __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */
+ __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */
+ uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */
+ __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */
+ uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */
+ __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */
+ uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */
+ __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */
+ uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
+ __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */
+ __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */
+ __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */
+ __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */
+ __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */
+ uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
+ __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */
+ __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */
+ uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
+ __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */
+ __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */
+ uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
+ __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */
+ __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */
+ __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */
+ __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */
+ uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
+ __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */
+ __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */
+ __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */
+ __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */
+ __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */
+ uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
+ __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */
+ __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */
+ uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
+ __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */
+ __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */
+ __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */
+ __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */
+ __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */
+} DDRCTRL_TypeDef;
+
+/*
+ * @brief DDRPERFM block description (DDRPERFM)
+ */
+typedef struct
+{
+ __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */
+ __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */
+ __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */
+ __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */
+ __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */
+ __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */
+ __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */
+ __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */
+ uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
+ __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */
+ __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */
+ __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */
+ uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */
+ __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */
+ uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
+ __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */
+ __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */
+ __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */
+ __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */
+} DDRPERFM_TypeDef;
+
+/*
+ * @brief DDRPHYC block description (DDRPHYC)
+ */
+typedef struct
+{
+ __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */
+ __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */
+ __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */
+ __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */
+ __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */
+ __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */
+ __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */
+ __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */
+ __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */
+ __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */
+ __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */
+ __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */
+ __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */
+ __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */
+ __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */
+ __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */
+ __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */
+ __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */
+ __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */
+ __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */
+ __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */
+ __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */
+ __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */
+ __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */
+ uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
+ __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */
+ __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */
+ __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */
+ __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */
+ __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */
+ __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */
+ uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
+ __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */
+ __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */
+ __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */
+ __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */
+ __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */
+ __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */
+ uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
+ __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */
+ __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */
+ __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */
+ __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */
+ __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */
+ __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */
+ uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
+ __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */
+ __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */
+ __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */
+ __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */
+ __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */
+ __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */
+ uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
+ __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */
+ __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */
+ __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */
+ __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */
+ __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */
+ __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */
+} DDRPHYC_TypeDef;
+
/**
* @brief DFSDM module registers
*/
@@ -837,14 +1054,11 @@
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
- __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
- __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
+ __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
- __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
+ __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
- __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
- __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
+ __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
@@ -986,18 +1200,18 @@
{
__IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */
__IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */
- __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */
__IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */
__IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */
__IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */
__IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */
- __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
+ uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
__IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */
- __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
+ uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
__IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */
- uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */
+ uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */
__IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */
@@ -1160,110 +1374,6 @@
/**
- * @brief DDRPHYC DDR Physical Interface Control
- */
-typedef struct
-{
- __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */
- __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */
- __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */
- __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */
- __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */
- __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */
- __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */
- __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */
- __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */
- __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */
- __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */
- __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */
- __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */
- __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */
- __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */
- __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */
- __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */
- __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */
- __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */
- __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */
- __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */
- __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */
- __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */
- __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */
- uint32_t RESERVED0[24]; /*!< Reserved */
- __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */
- __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */
- __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */
- __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */
- __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */
- __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */
- __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */
- __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */
- uint32_t RESERVED1[8]; /*!< Reserved */
- __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */
- __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */
- __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */
- __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */
- __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */
- __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */
- __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */
- __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */
- __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */
- __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */
- __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */
- __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */
- __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */
- __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */
- __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */
- __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */
- __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */
- uint32_t RESERVED2[13]; /*!< Reserved */
- __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */
- __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */
- __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */
- __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */
- __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */
- __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */
- uint32_t RESERVED3[12]; /*!< Reserved */
- __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */
- __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */
- __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */
- __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */
- __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */
- __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */
- uint32_t RESERVED4[10]; /*!< Reserved */
- __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */
- __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */
- __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */
- __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */
- __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */
- __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */
- uint32_t RESERVED5[10]; /*!< Reserved */
- __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */
- __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */
- __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */
- __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */
- __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */
- __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */
- uint32_t RESERVED6[10]; /*!< Reserved */
- __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */
- __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */
- __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */
- __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */
- __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */
- __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */
-}DDRPHYC_TypeDef;
-
-
-/**
- * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL)
- */
-typedef struct
-{
- __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */
- /* @TODO : TypeDef to be compleated */
-}DDRC_TypeDef;
-
-
-/**
* @brief USBPHYC USB HS PHY Control
*/
typedef struct
@@ -1341,11 +1451,35 @@
*/
typedef struct
{
- __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */
- /* @TODO : TypeDef to be compleated if needed*/
+ __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */
+ uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */
+ __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */
+ __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */
+ uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
+ __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */
+ uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
+ __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */
+ __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
+ __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
+ __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */
}STGENC_TypeDef;
/**
+ * @brief STGENR System Timestamp Generator Read
+ */
+typedef struct
+{
+ __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */
+ __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */
+ uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
+ __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */
+ __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
+ __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
+ __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
+} STGENR_TypeDef;
+
+
+/**
* @brief Firewall
*/
@@ -1674,7 +1808,7 @@
__IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */
__IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */
__IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */
- __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */
+ __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */
__IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */
__IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */
@@ -1736,36 +1870,36 @@
typedef struct
{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
- __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
- uint32_t RESERVED; /*!< Reserved */
- __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
- uint32_t RESERVED1; /*!< Reserved */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
- __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
- __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
- __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
- __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
- __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
- uint32_t RESERVED2[227]; /*!< Reserved */
- __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
- __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
- __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
- __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved */
+ __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED1; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
+ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
+ __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
+ uint32_t RESERVED2[227]; /*!< Reserved */
+ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
} RTC_TypeDef;
@@ -1831,7 +1965,6 @@
__IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */
-
} TAMP_TypeDef;
@@ -1931,7 +2064,7 @@
__IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
__IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */
uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */
__IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */
@@ -2244,17 +2377,16 @@
/**
* @brief RNG
*/
-
typedef struct
{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
- __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
- __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
- __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
- __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
- __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;
/**
@@ -2522,20 +2654,20 @@
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
-#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
+#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
+#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
#define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */
#define RETRAM_BASE MCU_AHB_RETRAM
-#define SRAM_BASE MCU_AHB_SRAM
+#define SRAM_BASE AHB_SRAM
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
-#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
+#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
-#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
-#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
-#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
-#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
-#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
+#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
+#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
+#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
+#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
/*!< Device electronic signature memory map */
#define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */
@@ -2544,69 +2676,83 @@
#define DV_BASE (0x50081000L) /*!< Device Version register base address */
/*!< Peripheral memory map */
-#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
-#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
-#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
-#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
-#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
-#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
-#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
-#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
-#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
-#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
-#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
+#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
+#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
+#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
+#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
+#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
+#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
+#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
+#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
+#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
+#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
+#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
-/*!< MCU_APB1 */
-#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000)
-#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000)
-#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000)
-#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000)
-#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000)
-#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000)
-#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000)
-#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000)
-#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000)
-#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000)
-#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000)
-#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000)
-#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000)
-#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000)
-#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000)
-#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000)
-#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000)
-#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000)
-#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000)
-#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000)
-#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000)
-#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000)
-#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000)
-#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000)
-#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000)
-#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000)
-#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000)
+#define MCU_AHB_SRAM AHB_SRAM
+#define MCU_AHB_RETRAM AHB_RETRAM
+#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE
+#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE
+#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE
+#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE
+#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE
+#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE
+#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE
+#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE
+#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE
+#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE
+#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE
-/*!< MCU_APB2 */
-#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000)
-#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000)
-#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000)
-#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000)
-#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000)
-#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000)
-#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000)
-#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000)
-#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000)
+/*!< APB1 */
+#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000)
+#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000)
+#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000)
+#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000)
+#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000)
+#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000)
+#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000)
+#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000)
+#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000)
+#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000)
+#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000)
+#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000)
+#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000)
+#define USART2_BASE (APB1_PERIPH_BASE + 0xE000)
+#define USART3_BASE (APB1_PERIPH_BASE + 0xF000)
+#define UART4_BASE (APB1_PERIPH_BASE + 0x10000)
+#define UART5_BASE (APB1_PERIPH_BASE + 0x11000)
+#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000)
+#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000)
+#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000)
+#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000)
+#define CEC_BASE (APB1_PERIPH_BASE + 0x16000)
+#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000)
+#define UART7_BASE (APB1_PERIPH_BASE + 0x18000)
+#define UART8_BASE (APB1_PERIPH_BASE + 0x19000)
+#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000)
+
+/*!< APB2 */
+#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2_PERIPH_BASE + 0x3000)
+#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000)
+#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000)
+#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000)
+#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000)
+#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000)
+#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000)
+#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000)
+#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000)
+#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000)
#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
-#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000)
+#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
@@ -2622,42 +2768,42 @@
#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300)
#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380)
-/*!< MCU_AHB2 */
-#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000)
-#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000)
-#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000)
-#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000)
-#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100)
-#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300)
-#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000)
-#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000)
-#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000)
+/*!< AHB2 */
+#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000)
+#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000)
+#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000)
+#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000)
+#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100)
+#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300)
+#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000)
+#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000)
+#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000)
-/*!< MCU_AHB3 */
-#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000)
-#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000)
-#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000)
-#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310)
-#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000)
-#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000)
-#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000)
+/*!< AHB3 */
+#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000)
+#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000)
+#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000)
+#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310)
+#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000)
+#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000)
+#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000)
-/*!< MCU_AHB4 */
-#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000)
-#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000)
-#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000)
-#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000)
-#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000)
-#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000)
-#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000)
-#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000)
-#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000)
-#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000)
-#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000)
-#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000)
-#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000)
-#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000)
+/*!< AHB4 */
+#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000)
+#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000)
+#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000)
+#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000)
+#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000)
+#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000)
+#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000)
+#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000)
+#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000)
+#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000)
+#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000)
+#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000)
+#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000)
+#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000)
#define AIEC_C1_BASE (AIEC_BASE + 0x0080)
#define AIEC_C2_BASE (AIEC_BASE + 0x00C0)
/* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/
@@ -2666,71 +2812,72 @@
#define EXTI_C2_BASE AIEC_C2_BASE
-/*!< MCU_APB3 */
-#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000)
-#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000)
-#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000)
-#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000)
-#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000)
-#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000)
-#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000)
+/*!< APB3 */
+#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000)
+#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000)
+#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000)
+#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000)
+#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000)
+#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000)
+#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000)
#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
-#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000)
-#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000)
-#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000)
+#define DTS_BASE (APB3_PERIPH_BASE + 0x8000)
+#define PMB_BASE (APB3_PERIPH_BASE + 0x9000)
+#define HDP_BASE (APB3_PERIPH_BASE + 0xA000)
-/*!< MCU_AHB4 _APB_Debug */
+/*!< AHB4 _APB_Debug */
#define DBGMCU_BASE ((uint32_t )0x50081000)
-/*!< MCU_AHB5 */
-#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000)
-#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000)
-#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310)
-#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000)
-#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000)
+/*!< AHB5 */
+#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000)
+#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000)
+#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310)
+#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000)
+#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000)
/*!< GPV */
/*!< MPU_AHB6 */
-#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000)
-#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000)
-#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000)
-#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000)
-#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000)
-#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000)
-#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000)
-#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000)
-#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000)
-#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000)
+#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000)
+#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000)
+#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000)
+#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000)
+#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000)
+#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000)
+#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000)
+#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000)
+#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000)
+#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000)
#define ETH_MAC_BASE (ETH_BASE)
-#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000)
-#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000)
+#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000)
+#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000)
/*!< MPU_APB4 */
-#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000)
+#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000)
-#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000)
-#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000)
-#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000)
-#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000)
+#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000)
+#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000)
+#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000)
+#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000)
+#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000)
+#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000)
#define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100)
#define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200)
/*!< MPU_APB5 */
-#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000)
-#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000)
-#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000)
-#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000)
-#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000)
-#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000)
-#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000)
-#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000)
-#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000)
-#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000)
-#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000)
+#define USART1_BASE (APB5_PERIPH_BASE + 0x0000)
+#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000)
+#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000)
+#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000)
+#define RTC_BASE (APB5_PERIPH_BASE + 0x4000)
+#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000)
+#define TZC_BASE (APB5_PERIPH_BASE + 0x6000)
+#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000)
+#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000)
+#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000)
+#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000)
@@ -2768,6 +2915,7 @@
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
@@ -2794,7 +2942,6 @@
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
-
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
@@ -2974,6 +3121,7 @@
#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE)
+
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
@@ -2994,7 +3142,6 @@
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -3043,7 +3190,8 @@
#define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE)
#define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE)
-#define DDRC ((DDRC_TypeDef *)DDRC_BASE)
+#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE)
+#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE)
#define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
@@ -3052,7 +3200,7 @@
#define TZC ((TZC_TypeDef *)TZC_BASE)
#define TZPC ((TZPC_TypeDef *)TZPC_BASE)
#define STGENC ((STGENC_TypeDef *)STGENC_BASE)
-
+#define STGENR ((STGENR_TypeDef *)STGENR_BASE)
#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
@@ -3420,7 +3568,6 @@
#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
/******************** Bit definition for ADC_SMPR1 register ********************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -3648,6 +3795,7 @@
#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */
#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */
+
/******************** Bit definition for ADC_LTR2 register ********************/
#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */
#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
@@ -3921,7 +4069,7 @@
#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
@@ -4192,7 +4340,7 @@
/******************** Bit definition for ADC_JDR1 register ********************/
#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
@@ -4229,7 +4377,7 @@
/******************** Bit definition for ADC_JDR2 register ********************/
#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
@@ -4266,7 +4414,7 @@
/******************** Bit definition for ADC_JDR3 register ********************/
#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
@@ -4303,7 +4451,7 @@
/******************** Bit definition for ADC_JDR4 register ********************/
#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
@@ -4678,6 +4826,97 @@
#define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
#define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for ADC_VERR register ******************/
+#define ADC_VERR_MINREV_Pos (0U)
+#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */
+#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */
+#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */
+#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */
+#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */
+#define ADC_VERR_MAJREV_Pos (4U)
+#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */
+#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */
+#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */
+#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */
+#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */
+
+/***************** Bit definition for ADC_IPDR register ******************/
+#define ADC_IPDR_ID_Pos (0U)
+#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */
+#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
+#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
+#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
+#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
+#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
+#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
+#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
+#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
+#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */
+#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */
+#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */
+#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */
+#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */
+#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */
+#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */
+#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */
+#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */
+#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */
+#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */
+#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */
+#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */
+#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */
+#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */
+#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */
+#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */
+#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */
+#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */
+#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */
+#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */
+#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */
+#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */
+#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for ADC_SIDR register ******************/
+#define ADC_SIDR_SID_Pos (0U)
+#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */
+#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */
+#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */
+#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */
+#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */
+#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */
+#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */
+#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */
+#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */
+#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */
+#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */
+#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */
+#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */
+#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */
+#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */
+#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */
+#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */
+#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */
+#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */
+#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */
+#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */
+#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */
+#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */
+#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */
+#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */
+#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */
+#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */
+#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */
+#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */
+#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */
+#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */
+#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */
+#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */
+
/******************************************************************************/
/* */
/* VREFBUF */
@@ -5566,6 +5805,4571 @@
/******************************************************************************/
/* */
+/* DDRCTRL block description (DDRCTRL) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for DDRCTRL_MSTR register *****************/
+#define DDRCTRL_MSTR_DDR3_Pos (0U)
+#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */
+#define DDRCTRL_MSTR_LPDDR2_Pos (2U)
+#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */
+#define DDRCTRL_MSTR_LPDDR3_Pos (3U)
+#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */
+#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */
+#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U)
+#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */
+#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U)
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U)
+#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */
+#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U)
+#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */
+#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */
+
+/***************** Bit definition for DDRCTRL_STAT register *****************/
+#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U)
+#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */
+#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */
+#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U)
+#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */
+#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */
+#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U)
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */
+#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */
+
+/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/
+#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U)
+#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */
+#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U)
+#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */
+#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */
+#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U)
+#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */
+#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U)
+#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */
+#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */
+
+/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/
+#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U)
+#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */
+#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */
+#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */
+#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */
+#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */
+#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */
+#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */
+#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */
+#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */
+#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */
+#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */
+#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */
+#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */
+#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */
+
+/**************** Bit definition for DDRCTRL_MRSTAT register ****************/
+#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U)
+#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */
+
+/*************** Bit definition for DDRCTRL_DERATEEN register ***************/
+#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U)
+#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U)
+#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */
+#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U)
+#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */
+
+/************** Bit definition for DDRCTRL_DERATEINT register ***************/
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U)
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */
+#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_PWRCTL register ****************/
+#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U)
+#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */
+#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U)
+#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U)
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U)
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */
+#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U)
+#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U)
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
+
+/**************** Bit definition for DDRCTRL_PWRTMG register ****************/
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U)
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U)
+#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/
+#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U)
+#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U)
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U)
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U)
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */
+#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U)
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */
+#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U)
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U)
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */
+#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U)
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U)
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */
+
+/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U)
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */
+#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U)
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */
+#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */
+
+/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U)
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */
+
+/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U)
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U)
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */
+#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */
+
+/**************** Bit definition for DDRCTRL_INIT0 register *****************/
+#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U)
+#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */
+#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U)
+#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */
+#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT1 register *****************/
+#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U)
+#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */
+#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */
+#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U)
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */
+
+/**************** Bit definition for DDRCTRL_INIT2 register *****************/
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U)
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U)
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */
+
+/**************** Bit definition for DDRCTRL_INIT3 register *****************/
+#define DDRCTRL_INIT3_EMR_Pos (0U)
+#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */
+#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_INIT3_MR_Pos (16U)
+#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */
+#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */
+#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */
+#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */
+#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */
+#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */
+#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT4 register *****************/
+#define DDRCTRL_INIT4_EMR3_Pos (0U)
+#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */
+#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */
+#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */
+#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */
+#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */
+#define DDRCTRL_INIT4_EMR2_Pos (16U)
+#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */
+#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */
+#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */
+#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */
+#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */
+#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */
+#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */
+#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRCTRL_INIT5 register *****************/
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U)
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U)
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */
+#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U)
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U)
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U)
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U)
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U)
+#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */
+#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U)
+#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */
+#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/
+#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U)
+#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */
+#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */
+#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U)
+#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */
+#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U)
+#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */
+#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/
+#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U)
+#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */
+#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U)
+#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
+#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U)
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U)
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/
+#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U)
+#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */
+#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
+#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U)
+#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */
+#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */
+#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U)
+#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */
+#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */
+#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/
+#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U)
+#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */
+#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U)
+#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */
+#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U)
+#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */
+#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U)
+#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */
+#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/
+#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U)
+#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */
+#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U)
+#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */
+#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U)
+#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U)
+#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/
+#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U)
+#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */
+#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U)
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U)
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/
+#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U)
+#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */
+#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U)
+#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */
+
+/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/
+#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U)
+#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */
+#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U)
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */
+
+/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/
+#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U)
+#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */
+#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */
+#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */
+
+/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U)
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U)
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */
+
+/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U)
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U)
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U)
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */
+#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U)
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */
+#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U)
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */
+#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */
+
+/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U)
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U)
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */
+#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/
+#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U)
+#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */
+
+/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U)
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */
+
+/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U)
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U)
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U)
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U)
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U)
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U)
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U)
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */
+
+/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U)
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U)
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U)
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U)
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U)
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U)
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U)
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */
+
+/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U)
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U)
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */
+#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */
+
+/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U)
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */
+#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
+
+/*************** Bit definition for DDRCTRL_DFIMISC register ****************/
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U)
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U)
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */
+#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U)
+#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U)
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */
+
+/*************** Bit definition for DDRCTRL_DFISTAT register ****************/
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U)
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */
+#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U)
+#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */
+
+/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U)
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U)
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U)
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U)
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U)
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U)
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U)
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U)
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U)
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */
+#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */
+
+/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U)
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */
+
+/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U)
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */
+
+/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U)
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */
+
+/**************** Bit definition for DDRCTRL_ODTCFG register ****************/
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U)
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U)
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */
+#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U)
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */
+#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U)
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */
+#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */
+
+/**************** Bit definition for DDRCTRL_ODTMAP register ****************/
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U)
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */
+#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U)
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */
+
+/**************** Bit definition for DDRCTRL_SCHED register *****************/
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U)
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */
+#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U)
+#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */
+#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U)
+#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U)
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */
+#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U)
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */
+#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U)
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */
+#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */
+
+/**************** Bit definition for DDRCTRL_SCHED1 register ****************/
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U)
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */
+#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */
+
+/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U)
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U)
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */
+#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRCTRL_DBG0 register *****************/
+#define DDRCTRL_DBG0_DIS_WC_Pos (0U)
+#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U)
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */
+
+/***************** Bit definition for DDRCTRL_DBG1 register *****************/
+#define DDRCTRL_DBG1_DIS_DQ_Pos (0U)
+#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */
+#define DDRCTRL_DBG1_DIS_HIF_Pos (1U)
+#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */
+
+/**************** Bit definition for DDRCTRL_DBGCAM register ****************/
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U)
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */
+#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */
+#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U)
+#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */
+#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U)
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U)
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */
+
+/**************** Bit definition for DDRCTRL_DBGCMD register ****************/
+#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U)
+#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U)
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */
+#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U)
+#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */
+
+/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U)
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U)
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U)
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */
+
+/**************** Bit definition for DDRCTRL_SWCTL register *****************/
+#define DDRCTRL_SWCTL_SW_DONE_Pos (0U)
+#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */
+
+/**************** Bit definition for DDRCTRL_SWSTAT register ****************/
+#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U)
+#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */
+#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */
+
+/************** Bit definition for DDRCTRL_POISONCFG register ***************/
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U)
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U)
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U)
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */
+#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U)
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U)
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U)
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */
+
+/************** Bit definition for DDRCTRL_POISONSTAT register **************/
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U)
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U)
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U)
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U)
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */
+#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */
+
+/**************** Bit definition for DDRCTRL_PSTAT register *****************/
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U)
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U)
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U)
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */
+
+/**************** Bit definition for DDRCTRL_PCCFG register *****************/
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U)
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U)
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */
+#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U)
+#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */
+
+/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U)
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */
+
+/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+
+/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/
+#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U)
+#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */
+
+/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U)
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U)
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U)
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U)
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */
+
+/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U)
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */
+
+/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U)
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U)
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U)
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U)
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */
+#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */
+
+/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/
+#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U)
+#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */
+
+/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U)
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U)
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U)
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */
+
+/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U)
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U)
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */
+#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */
+
+/******************************************************************************/
+/* */
+/* DDRPERFM block description (DDRPERFM) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for DDRPERFM_CTL register *****************/
+#define DDRPERFM_CTL_START_Pos (0U)
+#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */
+#define DDRPERFM_CTL_STOP_Pos (1U)
+#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */
+
+/***************** Bit definition for DDRPERFM_CFG register *****************/
+#define DDRPERFM_CFG_EN_Pos (0U)
+#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */
+#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */
+#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CFG_SEL_Pos (16U)
+#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */
+#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */
+#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */
+
+/*************** Bit definition for DDRPERFM_STATUS register ****************/
+#define DDRPERFM_STATUS_COVF_Pos (0U)
+#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */
+#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */
+#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */
+#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */
+#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */
+#define DDRPERFM_STATUS_BUSY_Pos (16U)
+#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */
+#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */
+#define DDRPERFM_STATUS_TOVF_Pos (31U)
+#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */
+#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */
+
+/***************** Bit definition for DDRPERFM_CCR register *****************/
+#define DDRPERFM_CCR_CCLR_Pos (0U)
+#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */
+#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */
+#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CCR_TCLR_Pos (31U)
+#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */
+#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */
+
+/***************** Bit definition for DDRPERFM_IER register *****************/
+#define DDRPERFM_IER_OVFIE_Pos (0U)
+#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */
+#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */
+
+/***************** Bit definition for DDRPERFM_ISR register *****************/
+#define DDRPERFM_ISR_OVFF_Pos (0U)
+#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */
+
+/***************** Bit definition for DDRPERFM_ICR register *****************/
+#define DDRPERFM_ICR_OVF_Pos (0U)
+#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */
+
+/**************** Bit definition for DDRPERFM_TCNT register *****************/
+#define DDRPERFM_TCNT_CNT_Pos (0U)
+#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */
+#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT0 register *****************/
+#define DDRPERFM_CNT0_CNT_Pos (0U)
+#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT1 register *****************/
+#define DDRPERFM_CNT1_CNT_Pos (0U)
+#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT2 register *****************/
+#define DDRPERFM_CNT2_CNT_Pos (0U)
+#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_CNT3 register *****************/
+#define DDRPERFM_CNT3_CNT_Pos (0U)
+#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */
+#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */
+#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */
+#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */
+#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */
+#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */
+#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */
+#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */
+#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */
+#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */
+#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */
+#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */
+#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */
+#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */
+#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */
+#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */
+#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */
+#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */
+#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */
+#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */
+#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */
+#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */
+#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */
+#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */
+#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */
+#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */
+#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */
+#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */
+#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */
+#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPERFM_HWCFG register ****************/
+#define DDRPERFM_HWCFG_NCNT_Pos (0U)
+#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */
+#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */
+#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */
+#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */
+#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */
+#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */
+
+/***************** Bit definition for DDRPERFM_VER register *****************/
+#define DDRPERFM_VER_MINREV_Pos (0U)
+#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */
+#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */
+#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */
+#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */
+#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */
+#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */
+#define DDRPERFM_VER_MAJREV_Pos (4U)
+#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */
+#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */
+#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */
+#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */
+#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */
+#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */
+
+/***************** Bit definition for DDRPERFM_ID register ******************/
+#define DDRPERFM_ID_ID_Pos (0U)
+#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */
+#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */
+#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */
+#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */
+#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */
+#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */
+#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */
+#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */
+#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */
+#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */
+#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */
+#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */
+#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */
+#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */
+#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */
+#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */
+#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */
+#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */
+#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */
+#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */
+#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */
+#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */
+#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */
+#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */
+#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */
+#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */
+#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */
+#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */
+#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */
+#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */
+#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */
+#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */
+#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPERFM_SID register *****************/
+#define DDRPERFM_SID_SID_Pos (0U)
+#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */
+#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */
+#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */
+#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */
+#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */
+#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */
+#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */
+#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */
+#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */
+#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */
+#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */
+#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */
+#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */
+#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */
+#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */
+#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */
+#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */
+#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */
+#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */
+#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */
+#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */
+#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */
+#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */
+#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */
+#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */
+#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */
+#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */
+#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */
+#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */
+#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */
+#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */
+#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */
+#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */
+#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */
+
+/******************************************************************************/
+/* */
+/* DDRPHYC block description (DDRPHYC) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for DDRPHYC_RIDR register *****************/
+#define DDRPHYC_RIDR_PUBMNR_Pos (0U)
+#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */
+#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */
+#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */
+#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */
+#define DDRPHYC_RIDR_PUBMDR_Pos (4U)
+#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */
+#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_RIDR_PUBMJR_Pos (8U)
+#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */
+#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_RIDR_PHYMNR_Pos (12U)
+#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */
+#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */
+#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */
+#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */
+#define DDRPHYC_RIDR_PHYMDR_Pos (16U)
+#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */
+#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */
+#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */
+#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */
+#define DDRPHYC_RIDR_PHYMJR_Pos (20U)
+#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */
+#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */
+#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */
+#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */
+#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */
+#define DDRPHYC_RIDR_UDRID_Pos (24U)
+#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
+#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */
+#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */
+#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */
+#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */
+#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */
+#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */
+#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */
+#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_PIR register ******************/
+#define DDRPHYC_PIR_INIT_Pos (0U)
+#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */
+#define DDRPHYC_PIR_DLLSRST_Pos (1U)
+#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_PIR_DLLLOCK_Pos (2U)
+#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */
+#define DDRPHYC_PIR_ZCAL_Pos (3U)
+#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */
+#define DDRPHYC_PIR_ITMSRST_Pos (4U)
+#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */
+#define DDRPHYC_PIR_DRAMRST_Pos (5U)
+#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */
+#define DDRPHYC_PIR_DRAMINIT_Pos (6U)
+#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */
+#define DDRPHYC_PIR_QSTRN_Pos (7U)
+#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */
+#define DDRPHYC_PIR_RVTRN_Pos (8U)
+#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */
+#define DDRPHYC_PIR_ICPC_Pos (16U)
+#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */
+#define DDRPHYC_PIR_DLLBYP_Pos (17U)
+#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */
+#define DDRPHYC_PIR_CTLDINIT_Pos (18U)
+#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */
+#define DDRPHYC_PIR_CLRSR_Pos (28U)
+#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */
+#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */
+#define DDRPHYC_PIR_LOCKBYP_Pos (29U)
+#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */
+#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */
+#define DDRPHYC_PIR_ZCALBYP_Pos (30U)
+#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */
+#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */
+#define DDRPHYC_PIR_INITBYP_Pos (31U)
+#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */
+
+/***************** Bit definition for DDRPHYC_PGCR register *****************/
+#define DDRPHYC_PGCR_ITMDMD_Pos (0U)
+#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */
+#define DDRPHYC_PGCR_DQSCFG_Pos (1U)
+#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */
+#define DDRPHYC_PGCR_DFTCMP_Pos (2U)
+#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */
+#define DDRPHYC_PGCR_DFTLMT_Pos (3U)
+#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */
+#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */
+#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PGCR_DTOSEL_Pos (5U)
+#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */
+#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */
+#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PGCR_CKEN_Pos (9U)
+#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */
+#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PGCR_CKDV_Pos (12U)
+#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */
+#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */
+#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PGCR_CKINV_Pos (14U)
+#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */
+#define DDRPHYC_PGCR_IOLB_Pos (15U)
+#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */
+#define DDRPHYC_PGCR_IODDRM_Pos (16U)
+#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */
+#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */
+#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PGCR_RANKEN_Pos (18U)
+#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */
+#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */
+#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PGCR_ZKSEL_Pos (22U)
+#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */
+#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */
+#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PGCR_PDDISDX_Pos (24U)
+#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */
+#define DDRPHYC_PGCR_RFSHDT_Pos (25U)
+#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */
+#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */
+#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */
+#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */
+#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */
+#define DDRPHYC_PGCR_LBDQSS_Pos (29U)
+#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */
+#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */
+#define DDRPHYC_PGCR_LBGDQS_Pos (30U)
+#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */
+#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */
+#define DDRPHYC_PGCR_LBMODE_Pos (31U)
+#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */
+
+/***************** Bit definition for DDRPHYC_PGSR register *****************/
+#define DDRPHYC_PGSR_IDONE_Pos (0U)
+#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */
+#define DDRPHYC_PGSR_DLDONE_Pos (1U)
+#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */
+#define DDRPHYC_PGSR_ZCDDONE_Pos (2U)
+#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */
+#define DDRPHYC_PGSR_DIDONE_Pos (3U)
+#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */
+#define DDRPHYC_PGSR_DTDONE_Pos (4U)
+#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_PGSR_DTERR_Pos (5U)
+#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_PGSR_DTIERR_Pos (6U)
+#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_PGSR_DFTERR_Pos (7U)
+#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_PGSR_RVERR_Pos (8U)
+#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */
+#define DDRPHYC_PGSR_RVEIRR_Pos (9U)
+#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */
+#define DDRPHYC_PGSR_TQ_Pos (31U)
+#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */
+#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */
+
+/**************** Bit definition for DDRPHYC_DLLGCR register ****************/
+#define DDRPHYC_DLLGCR_DRES_Pos (0U)
+#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */
+#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DLLGCR_IPUMP_Pos (2U)
+#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */
+#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */
+#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DLLGCR_TESTEN_Pos (5U)
+#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */
+#define DDRPHYC_DLLGCR_DTC_Pos (6U)
+#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */
+#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DLLGCR_ATC_Pos (9U)
+#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */
+#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DLLGCR_TESTSW_Pos (11U)
+#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */
+#define DDRPHYC_DLLGCR_MBIAS_Pos (12U)
+#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */
+#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */
+#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U)
+#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */
+#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DLLGCR_BPS200_Pos (23U)
+#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */
+#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U)
+#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */
+#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U)
+#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */
+#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U)
+#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */
+#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U)
+#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */
+#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */
+#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/
+#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */
+#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */
+#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */
+#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */
+
+/***************** Bit definition for DDRPHYC_PTR0 register *****************/
+#define DDRPHYC_PTR0_TDLLSRST_Pos (0U)
+#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */
+#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */
+#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U)
+#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */
+#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */
+#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR0_TITMSRST_Pos (18U)
+#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */
+#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */
+#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */
+
+/***************** Bit definition for DDRPHYC_PTR1 register *****************/
+#define DDRPHYC_PTR1_TDINIT0_Pos (0U)
+#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */
+#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */
+#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR1_TDINIT1_Pos (19U)
+#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */
+#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */
+#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */
+
+/***************** Bit definition for DDRPHYC_PTR2 register *****************/
+#define DDRPHYC_PTR2_TDINIT2_Pos (0U)
+#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */
+#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */
+#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */
+#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */
+#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */
+#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */
+#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */
+#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */
+#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */
+#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */
+#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */
+#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */
+#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */
+#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */
+#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */
+#define DDRPHYC_PTR2_TDINIT3_Pos (17U)
+#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */
+#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */
+#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */
+#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */
+#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */
+#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */
+#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */
+#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */
+#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */
+#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */
+
+/**************** Bit definition for DDRPHYC_ACIOCR register ****************/
+#define DDRPHYC_ACIOCR_ACIOM_Pos (0U)
+#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */
+#define DDRPHYC_ACIOCR_ACOE_Pos (1U)
+#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */
+#define DDRPHYC_ACIOCR_ACODT_Pos (2U)
+#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */
+#define DDRPHYC_ACIOCR_ACPDD_Pos (3U)
+#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */
+#define DDRPHYC_ACIOCR_ACPDR_Pos (4U)
+#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */
+#define DDRPHYC_ACIOCR_CKODT_Pos (5U)
+#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */
+#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ACIOCR_CKPDD_Pos (8U)
+#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */
+#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */
+#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ACIOCR_CKPDR_Pos (11U)
+#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */
+#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */
+#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ACIOCR_RANKODT_Pos (14U)
+#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */
+#define DDRPHYC_ACIOCR_CSPDD_Pos (18U)
+#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */
+#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U)
+#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */
+#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */
+#define DDRPHYC_ACIOCR_RSTODT_Pos (26U)
+#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */
+#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */
+#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U)
+#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */
+#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */
+#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U)
+#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */
+#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */
+#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U)
+#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */
+#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */
+#define DDRPHYC_ACIOCR_ACSR_Pos (30U)
+#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */
+#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */
+#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_DXCCR register *****************/
+#define DDRPHYC_DXCCR_DXODT_Pos (0U)
+#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */
+#define DDRPHYC_DXCCR_DXIOM_Pos (1U)
+#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DXCCR_DXPDD_Pos (2U)
+#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */
+#define DDRPHYC_DXCCR_DXPDR_Pos (3U)
+#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */
+#define DDRPHYC_DXCCR_DQSRES_Pos (4U)
+#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */
+#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DXCCR_DQSNRES_Pos (8U)
+#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */
+#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DXCCR_DQSNRST_Pos (14U)
+#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */
+#define DDRPHYC_DXCCR_RVSEL_Pos (15U)
+#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */
+#define DDRPHYC_DXCCR_AWDT_Pos (16U)
+#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */
+
+/**************** Bit definition for DDRPHYC_DSGCR register *****************/
+#define DDRPHYC_DSGCR_PUREN_Pos (0U)
+#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */
+#define DDRPHYC_DSGCR_BDISEN_Pos (1U)
+#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */
+#define DDRPHYC_DSGCR_ZUEN_Pos (2U)
+#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */
+#define DDRPHYC_DSGCR_LPIOPD_Pos (3U)
+#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */
+#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U)
+#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */
+#define DDRPHYC_DSGCR_DQSGX_Pos (5U)
+#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */
+#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DSGCR_DQSGE_Pos (8U)
+#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */
+#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */
+#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DSGCR_NOBUB_Pos (11U)
+#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */
+#define DDRPHYC_DSGCR_FXDLAT_Pos (12U)
+#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */
+#define DDRPHYC_DSGCR_CKEPDD_Pos (16U)
+#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */
+#define DDRPHYC_DSGCR_ODTPDD_Pos (20U)
+#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */
+#define DDRPHYC_DSGCR_NL2PD_Pos (24U)
+#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */
+#define DDRPHYC_DSGCR_NL2OE_Pos (25U)
+#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */
+#define DDRPHYC_DSGCR_TPDPD_Pos (26U)
+#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */
+#define DDRPHYC_DSGCR_TPDOE_Pos (27U)
+#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */
+#define DDRPHYC_DSGCR_CKOE_Pos (28U)
+#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */
+#define DDRPHYC_DSGCR_ODTOE_Pos (29U)
+#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */
+#define DDRPHYC_DSGCR_RSTOE_Pos (30U)
+#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */
+#define DDRPHYC_DSGCR_CKEOE_Pos (31U)
+#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */
+
+/***************** Bit definition for DDRPHYC_DCR register ******************/
+#define DDRPHYC_DCR_DDRMD_Pos (0U)
+#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */
+#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DCR_DDR8BNK_Pos (3U)
+#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */
+#define DDRPHYC_DCR_PDQ_Pos (4U)
+#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */
+#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */
+#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DCR_MPRDQ_Pos (7U)
+#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */
+#define DDRPHYC_DCR_DDRTYPE_Pos (8U)
+#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */
+#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */
+#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DCR_NOSRA_Pos (27U)
+#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */
+#define DDRPHYC_DCR_DDR2T_Pos (28U)
+#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */
+#define DDRPHYC_DCR_UDIMM_Pos (29U)
+#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */
+#define DDRPHYC_DCR_RDIMM_Pos (30U)
+#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */
+#define DDRPHYC_DCR_TPD_Pos (31U)
+#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */
+
+/**************** Bit definition for DDRPHYC_DTPR0 register *****************/
+#define DDRPHYC_DTPR0_TMRD_Pos (0U)
+#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */
+#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR0_TRTP_Pos (2U)
+#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */
+#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */
+#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR0_TWTR_Pos (5U)
+#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */
+#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR0_TRP_Pos (8U)
+#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */
+#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR0_TRCD_Pos (12U)
+#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */
+#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTPR0_TRAS_Pos (16U)
+#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */
+#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */
+#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR0_TRRD_Pos (21U)
+#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */
+#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */
+#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR0_TRC_Pos (25U)
+#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */
+#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */
+#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTPR0_TCCD_Pos (31U)
+#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */
+
+/**************** Bit definition for DDRPHYC_DTPR1 register *****************/
+#define DDRPHYC_DTPR1_TAOND_Pos (0U)
+#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */
+#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR1_TRTW_Pos (2U)
+#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */
+#define DDRPHYC_DTPR1_TFAW_Pos (3U)
+#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
+#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */
+#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR1_TMOD_Pos (9U)
+#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */
+#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR1_TRTODT_Pos (11U)
+#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */
+#define DDRPHYC_DTPR1_TRFC_Pos (16U)
+#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */
+#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U)
+#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */
+#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U)
+#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */
+#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DTPR2 register *****************/
+#define DDRPHYC_DTPR2_TXS_Pos (0U)
+#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */
+#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */
+#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTPR2_TXP_Pos (10U)
+#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */
+#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */
+#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTPR2_TCKE_Pos (15U)
+#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */
+#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */
+#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTPR2_TDLLK_Pos (19U)
+#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */
+#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */
+#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/
+#define DDRPHYC_DDR3_MR0_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR0_CL0_Pos (2U)
+#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */
+#define DDRPHYC_DDR3_MR0_BT_Pos (3U)
+#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */
+#define DDRPHYC_DDR3_MR0_CL_Pos (4U)
+#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */
+#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */
+#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR0_TM_Pos (7U)
+#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */
+#define DDRPHYC_DDR3_MR0_DR_Pos (8U)
+#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */
+#define DDRPHYC_DDR3_MR0_WR_Pos (9U)
+#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DDR3_MR0_PD_Pos (12U)
+#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */
+#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U)
+#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */
+#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/
+#define DDRPHYC_DDR3_MR1_DE_Pos (0U)
+#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */
+#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U)
+#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */
+#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U)
+#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_AL_Pos (3U)
+#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */
+#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */
+#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U)
+#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */
+#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U)
+#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U)
+#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */
+#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U)
+#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */
+#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U)
+#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */
+#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U)
+#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */
+#define DDRPHYC_DDR3_MR1_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_BT_Pos (3U)
+#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */
+#define DDRPHYC_DDR3_MR1_WC_Pos (4U)
+#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */
+#define DDRPHYC_DDR3_MR1_NWR_Pos (5U)
+#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR1_BL_Pos (0U)
+#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */
+#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR1_NWR_Pos (5U)
+#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */
+#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */
+#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/
+#define DDRPHYC_DDR3_MR2_PASR_Pos (0U)
+#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */
+#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_CWL_Pos (3U)
+#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */
+#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DDR3_MR2_ASR_Pos (6U)
+#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */
+#define DDRPHYC_DDR3_MR2_SRT_Pos (7U)
+#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */
+#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U)
+#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */
+#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */
+#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U)
+#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */
+#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U)
+#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */
+#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U)
+#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+#define DDRPHYC_DDR3_MR2_WL_Pos (6U)
+#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+#define DDRPHYC_DDR3_MR2_WR_Pos (7U)
+#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */
+
+/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/
+#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U)
+#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */
+#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */
+#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DDR3_MR3_MPR_Pos (2U)
+#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */
+
+/**************** Bit definition for DDRPHYC_ODTCR register *****************/
+#define DDRPHYC_ODTCR_RDODT_Pos (0U)
+#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */
+#define DDRPHYC_ODTCR_WRODT_Pos (16U)
+#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */
+
+/***************** Bit definition for DDRPHYC_DTAR register *****************/
+#define DDRPHYC_DTAR_DTCOL_Pos (0U)
+#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */
+#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */
+#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTAR_DTROW_Pos (12U)
+#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */
+#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */
+#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTAR_DTBANK_Pos (28U)
+#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */
+#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */
+#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTAR_DTMPR_Pos (31U)
+#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */
+
+/**************** Bit definition for DDRPHYC_DTDR0 register *****************/
+#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U)
+#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */
+#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U)
+#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */
+#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U)
+#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U)
+#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */
+#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_DTDR1 register *****************/
+#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U)
+#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */
+#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U)
+#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */
+#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U)
+#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */
+#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */
+#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U)
+#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */
+#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */
+#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_GPR0 register *****************/
+#define DDRPHYC_GPR0_GPR0_Pos (0U)
+#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */
+#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */
+#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */
+#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */
+#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */
+#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */
+#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */
+#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */
+#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */
+#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */
+#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */
+#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */
+#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */
+#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */
+#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */
+#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */
+#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */
+#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */
+#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */
+#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */
+#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */
+#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */
+#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */
+#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */
+#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */
+#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */
+#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */
+#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */
+#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */
+#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for DDRPHYC_GPR1 register *****************/
+#define DDRPHYC_GPR1_GPR1_Pos (0U)
+#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */
+#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */
+#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */
+#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */
+#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */
+#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */
+#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */
+#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */
+#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */
+#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */
+#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */
+#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */
+#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */
+#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */
+#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */
+#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */
+#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */
+#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */
+#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */
+#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */
+#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */
+#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */
+#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */
+#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */
+#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */
+#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */
+#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */
+#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */
+#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */
+#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/
+#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U)
+#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */
+#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */
+#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */
+#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U)
+#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */
+#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */
+#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U)
+#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */
+#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */
+#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U)
+#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */
+#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U)
+#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */
+
+/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/
+#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U)
+#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */
+#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */
+#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */
+
+/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/
+#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U)
+#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */
+#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */
+#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */
+#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */
+#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U)
+#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */
+#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */
+#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U)
+#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */
+#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */
+
+/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/
+#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U)
+#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */
+#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */
+#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */
+#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */
+#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U)
+#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */
+#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */
+#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */
+#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */
+#define DDRPHYC_ZQ0SR1_OPD_Pos (4U)
+#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */
+#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */
+#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */
+#define DDRPHYC_ZQ0SR1_OPU_Pos (6U)
+#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */
+#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */
+#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */
+#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */
+
+/**************** Bit definition for DDRPHYC_DX0GCR register ****************/
+#define DDRPHYC_DX0GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX0GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX0GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX0GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX0GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX0GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX0GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX0GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX0GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/
+#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX0GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/
+#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/
+#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/
+#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/
+#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX1GCR register ****************/
+#define DDRPHYC_DX1GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX1GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX1GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX1GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX1GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX1GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX1GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX1GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX1GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/
+#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX1GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/
+#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/
+#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/
+#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/
+#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX2GCR register ****************/
+#define DDRPHYC_DX2GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX2GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX2GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX2GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX2GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX2GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX2GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX2GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX2GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/
+#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX2GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/
+#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/
+#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/
+#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/
+#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for DDRPHYC_DX3GCR register ****************/
+#define DDRPHYC_DX3GCR_DXEN_Pos (0U)
+#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */
+#define DDRPHYC_DX3GCR_DQSODT_Pos (1U)
+#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */
+#define DDRPHYC_DX3GCR_DQODT_Pos (2U)
+#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */
+#define DDRPHYC_DX3GCR_DXIOM_Pos (3U)
+#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */
+#define DDRPHYC_DX3GCR_DXPDD_Pos (4U)
+#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
+#define DDRPHYC_DX3GCR_DXPDR_Pos (5U)
+#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */
+#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U)
+#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
+#define DDRPHYC_DX3GCR_DSEN_Pos (7U)
+#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */
+#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */
+#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U)
+#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */
+#define DDRPHYC_DX3GCR_DQRTT_Pos (10U)
+#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */
+#define DDRPHYC_DX3GCR_RTTOH_Pos (11U)
+#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */
+#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */
+#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U)
+#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */
+#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U)
+#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */
+#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */
+#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */
+
+/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/
+#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U)
+#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */
+#define DDRPHYC_DX3GSR0_DTERR_Pos (4U)
+#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */
+#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U)
+#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */
+#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U)
+#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */
+#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */
+#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/
+#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U)
+#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */
+#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U)
+#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */
+#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */
+#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3GSR1_RVERR_Pos (12U)
+#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */
+#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U)
+#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */
+#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U)
+#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */
+#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */
+
+/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/
+#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U)
+#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */
+#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U)
+#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */
+#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */
+#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U)
+#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */
+#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */
+#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U)
+#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */
+#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */
+#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U)
+#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */
+#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U)
+#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */
+#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U)
+#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */
+#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U)
+#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */
+#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U)
+#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */
+#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U)
+#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */
+#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */
+
+/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/
+#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U)
+#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */
+#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */
+#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */
+#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U)
+#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */
+#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */
+#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */
+#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */
+#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */
+#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */
+#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U)
+#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */
+#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */
+#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */
+#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */
+#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */
+#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */
+#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U)
+#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */
+#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */
+#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */
+#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U)
+#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */
+#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */
+#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */
+#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U)
+#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */
+#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */
+#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U)
+#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */
+#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U)
+#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */
+#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */
+#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/
+#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U)
+#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */
+#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */
+#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */
+#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */
+#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */
+#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U)
+#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */
+#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */
+#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */
+#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U)
+#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */
+#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */
+#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U)
+#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */
+#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U)
+#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */
+#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */
+#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */
+
+/******************************************************************************/
+/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
@@ -11526,7 +16330,7 @@
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
-#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
@@ -16622,6 +21426,7 @@
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
/******************************************************************************/
/* */
/* Inter-Processor Communication Controller (IPCC) */
@@ -17303,7 +22108,7 @@
#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
#define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
#define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
-#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */
+#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
#define MDMA_CTCR_DBURST_Pos (15U)
#define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
@@ -17686,109 +22491,109 @@
#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
/******************** Bit definition for PWR_CR2 register ********************/
-#define PWR_CR2_BREN_Pos (0U)
+#define PWR_CR2_BREN_Pos (0U)
#define PWR_CR2_BREN_Msk (0x1U << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
-#define PWR_CR2_RREN_Pos (1U)
+#define PWR_CR2_RREN_Pos (1U)
#define PWR_CR2_RREN_Msk (0x1U << PWR_CR2_RREN_Pos) /*!< 0x00000002 */
#define PWR_CR2_RREN PWR_CR2_RREN_Msk /*!< Retention Regulator enable */
-#define PWR_CR2_MONEN_Pos (4U)
+#define PWR_CR2_MONEN_Pos (4U)
#define PWR_CR2_MONEN_Msk (0x1U << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
-#define PWR_CR2_BRRDY_Pos (16U)
+#define PWR_CR2_BRRDY_Pos (16U)
#define PWR_CR2_BRRDY_Msk (0x1U << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup Regulator ready */
-#define PWR_CR2_RRRDY_Pos (17U)
+#define PWR_CR2_RRRDY_Pos (17U)
#define PWR_CR2_RRRDY_Msk (0x1U << PWR_CR2_RRRDY_Pos) /*!< 0x00020000 */
#define PWR_CR2_RRRDY PWR_CR2_RRRDY_Msk /*!< Retention Regulator ready */
-#define PWR_CR2_VBATL_Pos (20U)
+#define PWR_CR2_VBATL_Pos (20U)
#define PWR_CR2_VBATL_Msk (0x1U << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level equal or below low threshold */
-#define PWR_CR2_VBATH_Pos (21U)
+#define PWR_CR2_VBATH_Pos (21U)
#define PWR_CR2_VBATH_Msk (0x1U << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level equal or above high threshold */
-#define PWR_CR2_TEMPL_Pos (22U)
+#define PWR_CR2_TEMPL_Pos (22U)
#define PWR_CR2_TEMPL_Msk (0x1U << PWR_CR2_TEMPL_Pos) /*!< 0x00300000 */
#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level equal or below low threshold */
-#define PWR_CR2_TEMPH_Pos (23U)
+#define PWR_CR2_TEMPH_Pos (23U)
#define PWR_CR2_TEMPH_Msk (0x1U << PWR_CR2_TEMPH_Pos) /*!< 0x00400000 */
#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level equal or below high threshold */
/******************** Bit definition for PWR_CR3 register ********************/
-#define PWR_CR3_VBE_Pos (8U)
+#define PWR_CR3_VBE_Pos (8U)
#define PWR_CR3_VBE_Msk (0x1U << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
-#define PWR_CR3_VBRS_Pos (9U)
+#define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
-#define PWR_CR3_DDRSREN_Pos (10U)
+#define PWR_CR3_DDRSREN_Pos (10U)
#define PWR_CR3_DDRSREN_Msk (0x1U << PWR_CR3_DDRSREN_Pos) /*!< 0x00000400 */
#define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refresh in standby mode enable */
-#define PWR_CR3_DDRSRDIS_Pos (11U)
+#define PWR_CR3_DDRSRDIS_Pos (11U)
#define PWR_CR3_DDRSRDIS_Msk (0x1U << PWR_CR3_DDRSRDIS_Pos) /*!< 0x00000800 */
#define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refresh retention after standby disable */
-#define PWR_CR3_DDRRETEN_Pos (12U)
+#define PWR_CR3_DDRRETEN_Pos (12U)
#define PWR_CR3_DDRRETEN_Msk (0x1U << PWR_CR3_DDRRETEN_Pos) /*!< 0x00001000 */
#define PWR_CR3_DDRRETEN PWR_CR3_DDRRETEN_Msk /*!< DDR retention enable */
#define PWR_CR3_POPL_Pos (17U)
#define PWR_CR3_POPL_Msk (0x1FU << PWR_CR3_POPL_Pos) /*!< 0x003E0000 */
#define PWR_CR3_POPL PWR_CR3_POPL_Msk /*!< PWR_ON pulse low configuration */
-#define PWR_CR3_USB33DEN_Pos (24U)
+#define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< USB33DEN: USB 3.3V voltage level detector enable */
-#define PWR_CR3_USB33RDY_Pos (26U)
+#define PWR_CR3_USB33RDY_Pos (26U)
#define PWR_CR3_USB33RDY_Msk (0x1U << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
-#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB 3.3V supply ready */
-#define PWR_CR3_REG18EN_Pos (28U)
+#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB 3.3V supply ready */
+#define PWR_CR3_REG18EN_Pos (28U)
#define PWR_CR3_REG18EN_Msk (0x1U << PWR_CR3_REG18EN_Pos) /*!< 0x10000000 */
#define PWR_CR3_REG18EN PWR_CR3_REG18EN_Msk /*!< 1V8 regulator enable */
-#define PWR_CR3_REG18RDY_Pos (29U)
+#define PWR_CR3_REG18RDY_Pos (29U)
#define PWR_CR3_REG18RDY_Msk (0x1U << PWR_CR3_REG18RDY_Pos) /*!< 0x20000000 */
#define PWR_CR3_REG18RDY PWR_CR3_REG18RDY_Msk /*!< 1V8 regulator supply ready */
-#define PWR_CR3_REG11EN_Pos (30U)
+#define PWR_CR3_REG11EN_Pos (30U)
#define PWR_CR3_REG11EN_Msk (0x1U << PWR_CR3_REG11EN_Pos) /*!< 0x40000000 */
#define PWR_CR3_REG11EN PWR_CR3_REG11EN_Msk /*!< 1V1 regulator enable */
-#define PWR_CR3_REG11RDY_Pos (31U)
+#define PWR_CR3_REG11RDY_Pos (31U)
#define PWR_CR3_REG11RDY_Msk (0x1U << PWR_CR3_REG11RDY_Pos) /*!< 0x80000000 */
#define PWR_CR3_REG11RDY PWR_CR3_REG11RDY_Msk /*!< 1V1 regulator supply ready */
/******************** Bit definition for PWR_MPUCR register ********************/
-#define PWR_MPUCR_PDDS_Pos (0U)
+#define PWR_MPUCR_PDDS_Pos (0U)
#define PWR_MPUCR_PDDS_Msk (0x1U << PWR_MPUCR_PDDS_Pos) /*!< 0x00000001 */
#define PWR_MPUCR_PDDS PWR_MPUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
-#define PWR_MPUCR_CSTBYDIS_Pos (3U)
+#define PWR_MPUCR_CSTBYDIS_Pos (3U)
#define PWR_MPUCR_CSTBYDIS_Msk (0x1U << PWR_MPUCR_CSTBYDIS_Pos) /*!< 0x00000008 */
#define PWR_MPUCR_CSTBYDIS PWR_MPUCR_CSTBYDIS_Msk /*!< MPU CStandby mode disable */
-#define PWR_MPUCR_STOPF_Pos (5U)
+#define PWR_MPUCR_STOPF_Pos (5U)
#define PWR_MPUCR_STOPF_Msk (0x1U << PWR_MPUCR_STOPF_Pos) /*!< 0x00000020 */
#define PWR_MPUCR_STOPF PWR_MPUCR_STOPF_Msk /*!< Stop Flag */
-#define PWR_MPUCR_SBF_Pos (6U)
+#define PWR_MPUCR_SBF_Pos (6U)
#define PWR_MPUCR_SBF_Msk (0x1U << PWR_MPUCR_SBF_Pos) /*!< 0x00000040 */
#define PWR_MPUCR_SBF PWR_MPUCR_SBF_Msk /*!< System Standby Flag */
-#define PWR_MPUCR_SBF_MPU_Pos (7U)
+#define PWR_MPUCR_SBF_MPU_Pos (7U)
#define PWR_MPUCR_SBF_MPU_Msk (0x1U << PWR_MPUCR_SBF_MPU_Pos) /*!< 0x00000080 */
#define PWR_MPUCR_SBF_MPU PWR_MPUCR_SBF_MPU_Msk /*!< MPU Standby Flag */
-#define PWR_MPUCR_CSSF_Pos (9U)
+#define PWR_MPUCR_CSSF_Pos (9U)
#define PWR_MPUCR_CSSF_Msk (0x1U << PWR_MPUCR_CSSF_Pos) /*!< 0x00000200 */
#define PWR_MPUCR_CSSF PWR_MPUCR_CSSF_Msk /*!< Clear MCU STANDBY, STOP and HOLD flags.(always read as 0) */
-#define PWR_MPUCR_STANDBYWFIL2_Pos (15U)
+#define PWR_MPUCR_STANDBYWFIL2_Pos (15U)
#define PWR_MPUCR_STANDBYWFIL2_Msk (0x1U << PWR_MPUCR_STANDBYWFIL2_Pos) /*!< 0x00008000 */
#define PWR_MPUCR_STANDBYWFIL2 PWR_MPUCR_STANDBYWFIL2_Msk /*!< MPU system idle indication */
/******************** Bit definition for PWR_MCUCR register ********************/
-#define PWR_MCUCR_PDDS_Pos (0U)
+#define PWR_MCUCR_PDDS_Pos (0U)
#define PWR_MCUCR_PDDS_Msk (0x1U << PWR_MCUCR_PDDS_Pos) /*!< 0x00000001 */
#define PWR_MCUCR_PDDS PWR_MCUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
-#define PWR_MCUCR_STOPF_Pos (5U)
+#define PWR_MCUCR_STOPF_Pos (5U)
#define PWR_MCUCR_STOPF_Msk (0x1U << PWR_MCUCR_STOPF_Pos) /*!< 0x00000020 */
#define PWR_MCUCR_STOPF PWR_MCUCR_STOPF_Msk /*!< Stop Flag */
-#define PWR_MCUCR_SBF_Pos (6U)
+#define PWR_MCUCR_SBF_Pos (6U)
#define PWR_MCUCR_SBF_Msk (0x1U << PWR_MCUCR_SBF_Pos) /*!< 0x00000040 */
#define PWR_MCUCR_SBF PWR_MCUCR_SBF_Msk /*!< System Standby Flag */
-#define PWR_MCUCR_CSSF_Pos (9U)
+#define PWR_MCUCR_CSSF_Pos (9U)
#define PWR_MCUCR_CSSF_Msk (0x1U << PWR_MCUCR_CSSF_Pos) /*!< 0x00000200 */
#define PWR_MCUCR_CSSF PWR_MCUCR_CSSF_Msk /*!< Clear MCU Standby, Stop flags */
-#define PWR_MCUCR_DEEPSLEEP_Pos (15U)
+#define PWR_MCUCR_DEEPSLEEP_Pos (15U)
#define PWR_MCUCR_DEEPSLEEP_Msk (0x1U << PWR_MCUCR_DEEPSLEEP_Pos) /*!< 0x00008000 */
#define PWR_MCUCR_DEEPSLEEP PWR_MCUCR_DEEPSLEEP_Msk /*!< MCU system idle indication */
@@ -17938,109 +22743,109 @@
/* */
/******************************************************************************/
/****************** Bit definition for BSEC_OTP_CONFIG register *****************/
-#define BSEC_OTP_CONFIG_PWRUP_Pos (0U)
+#define BSEC_OTP_CONFIG_PWRUP_Pos (0U)
#define BSEC_OTP_CONFIG_PWRUP_Msk (0x1U << BSEC_OTP_CONFIG_PWRUP_Pos) /*!< 0x00000001 */
#define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up control */
-#define BSEC_OTP_CONFIG_FRC_Pos (1U)
+#define BSEC_OTP_CONFIG_FRC_Pos (1U)
#define BSEC_OTP_CONFIG_FRC_Msk (0x3U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000006 */
#define BSEC_OTP_CONFIG_FRC BSEC_OTP_CONFIG_FRC_Msk /*!< OTP clock frequency range selection */
#define BSEC_OTP_CONFIG_FRC_0 (0x1U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000002 */
#define BSEC_OTP_CONFIG_FRC_1 (0x2U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000004 */
-#define BSEC_OTP_CONFIG_PRGWIDTH_Pos (3U)
+#define BSEC_OTP_CONFIG_PRGWIDTH_Pos (3U)
#define BSEC_OTP_CONFIG_PRGWIDTH_Msk (0xFU << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000078 */
#define BSEC_OTP_CONFIG_PRGWIDTH BSEC_OTP_CONFIG_PRGWIDTH_Msk /*!< OTP programming pulse width */
#define BSEC_OTP_CONFIG_PRGWIDTH_0 (0x1U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000008 */
#define BSEC_OTP_CONFIG_PRGWIDTH_1 (0x2U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000010 */
#define BSEC_OTP_CONFIG_PRGWIDTH_2 (0x4U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000020 */
#define BSEC_OTP_CONFIG_PRGWIDTH_3 (0x8U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000040 */
-#define BSEC_OTP_CONFIG_TREAD_Pos (7U)
+#define BSEC_OTP_CONFIG_TREAD_Pos (7U)
#define BSEC_OTP_CONFIG_TREAD_Msk (0x3U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000180 */
#define BSEC_OTP_CONFIG_TREAD BSEC_OTP_CONFIG_TREAD_Msk /*!< set OTP reading current level */
#define BSEC_OTP_CONFIG_TREAD_0 (0x1U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000080 */
#define BSEC_OTP_CONFIG_TREAD_1 (0x2U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000100 */
/****************** Bit definition for BSEC_OTP_CONTROL register ****************/
-#define BSEC_OTP_CONTROL_ADDR_Pos (0U)
+#define BSEC_OTP_CONTROL_ADDR_Pos (0U)
#define BSEC_OTP_CONTROL_ADDR_Msk (0x7FU << BSEC_OTP_CONTROL_ADDR_Pos) /*!< 0x0000007F */
#define BSEC_OTP_CONTROL_ADDR BSEC_OTP_CONTROL_ADDR_Msk /*!< OTP word address */
-#define BSEC_OTP_CONTROL_PROG_Pos (8U)
+#define BSEC_OTP_CONTROL_PROG_Pos (8U)
#define BSEC_OTP_CONTROL_PROG_Msk (0x1U << BSEC_OTP_CONTROL_PROG_Pos) /*!< 0x00000100 */
#define BSEC_OTP_CONTROL_PROG BSEC_OTP_CONTROL_PROG_Msk /*!< OTP operation control */
-#define BSEC_OTP_CONTROL_LOCK_Pos (9U)
+#define BSEC_OTP_CONTROL_LOCK_Pos (9U)
#define BSEC_OTP_CONTROL_LOCK_Msk (0x1U << BSEC_OTP_CONTROL_LOCK_Pos) /*!< 0x00000200 */
#define BSEC_OTP_CONTROL_LOCK BSEC_OTP_CONTROL_LOCK_Msk /*!< OTP permanent word lock control */
/****************** Bit definition for BSEC_OTP_STATUS register *****************/
-#define BSEC_OTP_STATUS_SECURE_Pos (0U)
+#define BSEC_OTP_STATUS_SECURE_Pos (0U)
#define BSEC_OTP_STATUS_SECURE_Msk (0x1U << BSEC_OTP_STATUS_SECURE_Pos) /*!< 0x00000001 */
#define BSEC_OTP_STATUS_SECURE BSEC_OTP_STATUS_SECURE_Msk /*!< OTP secured mode */
-#define BSEC_OTP_STATUS_FULLDBG_Pos (1U)
+#define BSEC_OTP_STATUS_FULLDBG_Pos (1U)
#define BSEC_OTP_STATUS_FULLDBG_Msk (0x1U << BSEC_OTP_STATUS_FULLDBG_Pos) /*!< 0x00000002 */
#define BSEC_OTP_STATUS_FULLDBG BSEC_OTP_STATUS_FULLDBG_Msk /*!< OTP mode in full debug */
-#define BSEC_OTP_STATUS_INVALID_Pos (2U)
+#define BSEC_OTP_STATUS_INVALID_Pos (2U)
#define BSEC_OTP_STATUS_INVALID_Msk (0x1U << BSEC_OTP_STATUS_INVALID_Pos) /*!< 0x00000004 */
#define BSEC_OTP_STATUS_INVALID BSEC_OTP_STATUS_INVALID_Msk /*!< OTP invalid mode */
-#define BSEC_OTP_STATUS_BUSY_Pos (3U)
+#define BSEC_OTP_STATUS_BUSY_Pos (3U)
#define BSEC_OTP_STATUS_BUSY_Msk (0x1U << BSEC_OTP_STATUS_BUSY_Pos) /*!< 0x00000008 */
#define BSEC_OTP_STATUS_BUSY BSEC_OTP_STATUS_BUSY_Msk /*!< OTP operation status */
-#define BSEC_OTP_STATUS_PROGFAIL_Pos (4U)
+#define BSEC_OTP_STATUS_PROGFAIL_Pos (4U)
#define BSEC_OTP_STATUS_PROGFAIL_Msk (0x1U << BSEC_OTP_STATUS_PROGFAIL_Pos) /*!< 0x00000010 */
#define BSEC_OTP_STATUS_PROGFAIL BSEC_OTP_STATUS_PROGFAIL_Msk /*!< last programming status */
-#define BSEC_OTP_STATUS_PWRON_Pos (5U)
+#define BSEC_OTP_STATUS_PWRON_Pos (5U)
#define BSEC_OTP_STATUS_PWRON_Msk (0x1U << BSEC_OTP_STATUS_PWRON_Pos) /*!< 0x00000020 */
#define BSEC_OTP_STATUS_PWRON BSEC_OTP_STATUS_PWRON_Msk /*!< OTP power status */
-#define BSEC_OTP_STATUS_BIST1LOCK_Pos (6U)
+#define BSEC_OTP_STATUS_BIST1LOCK_Pos (6U)
#define BSEC_OTP_STATUS_BIST1LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST1LOCK_Pos) /*!< 0x00000040 */
#define BSEC_OTP_STATUS_BIST1LOCK BSEC_OTP_STATUS_BIST1LOCK_Msk /*!< BIST1 locked */
-#define BSEC_OTP_STATUS_BIST2LOCK_Pos (7U)
+#define BSEC_OTP_STATUS_BIST2LOCK_Pos (7U)
#define BSEC_OTP_STATUS_BIST2LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST2LOCK_Pos) /*!< 0x00000080 */
#define BSEC_OTP_STATUS_BIST2LOCK BSEC_OTP_STATUS_BIST2LOCK_Msk /*!< BIST2 locked */
/****************** Bit definition for BSEC_OTP_LOCK register ********************/
-#define BSEC_OTP_LOCK_OTP_Pos (0U)
+#define BSEC_OTP_LOCK_OTP_Pos (0U)
#define BSEC_OTP_LOCK_OTP_Msk (0x1U << BSEC_OTP_LOCK_OTP_Pos) /*!< 0x00000001 */
#define BSEC_OTP_LOCK_OTP BSEC_OTP_LOCK_OTP_Msk /*!< upper OTP read lock */
-#define BSEC_OTP_LOCK_DENREG_Pos (2U)
+#define BSEC_OTP_LOCK_DENREG_Pos (2U)
#define BSEC_OTP_LOCK_DENREG_Msk (0x1U << BSEC_OTP_LOCK_DENREG_Pos) /*!< 0x00000004 */
#define BSEC_OTP_LOCK_DENREG BSEC_OTP_LOCK_DENREG_Msk /*!< debug enable register sticky lock */
-#define BSEC_OTP_LOCK_FENREG_Pos (3U)
+#define BSEC_OTP_LOCK_FENREG_Pos (3U)
#define BSEC_OTP_LOCK_FENREG_Msk (0x1U << BSEC_OTP_LOCK_FENREG_Pos) /*!< 0x00000008 */
#define BSEC_OTP_LOCK_FENREG BSEC_OTP_LOCK_FENREG_Msk /*!< feature enable register sticky lock */
-#define BSEC_OTP_LOCK_GPLOCK_Pos (4U)
+#define BSEC_OTP_LOCK_GPLOCK_Pos (4U)
#define BSEC_OTP_LOCK_GPLOCK_Msk (0x1U << BSEC_OTP_LOCK_GPLOCK_Pos) /*!< 0x00000010 */
#define BSEC_OTP_LOCK_GPLOCK BSEC_OTP_LOCK_GPLOCK_Msk /*!< programming sticky lock */
/******************** Bit definition for BSEC_DENABLE register********************/
-#define BSEC_DENABLE_DFTEN_Pos (0U)
+#define BSEC_DENABLE_DFTEN_Pos (0U)
#define BSEC_DENABLE_DFTEN_Msk (0x1U << BSEC_DENABLE_DFTEN_Pos) /*!< 0x00000001 */
#define BSEC_DENABLE_DFTEN BSEC_DENABLE_DFTEN_Msk /*!< DFT enable with signal dften */
-#define BSEC_DENABLE_DBGEN_Pos (1U)
+#define BSEC_DENABLE_DBGEN_Pos (1U)
#define BSEC_DENABLE_DBGEN_Msk (0x1U << BSEC_DENABLE_DBGEN_Pos) /*!< 0x00000002 */
#define BSEC_DENABLE_DBGEN BSEC_DENABLE_DBGEN_Msk /*!< debug enable with signal dbgen */
-#define BSEC_DENABLE_NIDEN_Pos (2U)
+#define BSEC_DENABLE_NIDEN_Pos (2U)
#define BSEC_DENABLE_NIDEN_Msk (0x1U << BSEC_DENABLE_NIDEN_Pos) /*!< 0x00000004 */
#define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive debug enable with signal niden */
-#define BSEC_DENABLE_DEVICEEN_Pos (3U)
+#define BSEC_DENABLE_DEVICEEN_Pos (3U)
#define BSEC_DENABLE_DEVICEEN_Msk (0x1U << BSEC_DENABLE_DEVICEEN_Pos) /*!< 0x00000008 */
#define BSEC_DENABLE_DEVICEEN BSEC_DENABLE_DEVICEEN_Msk /*!< controls access to debug component via external debug port by signal deviceen */
-#define BSEC_DENABLE_HDPEN_Pos (4U)
+#define BSEC_DENABLE_HDPEN_Pos (4U)
#define BSEC_DENABLE_HDPEN_Msk (0x1U << BSEC_DENABLE_HDPEN_Pos) /*!< 0x00000010 */
#define BSEC_DENABLE_HDPEN BSEC_DENABLE_HDPEN_Msk /*!< hardware debug port enable with signal hdpen */
-#define BSEC_DENABLE_SPIDEN_Pos (5U)
+#define BSEC_DENABLE_SPIDEN_Pos (5U)
#define BSEC_DENABLE_SPIDEN_Msk (0x1U << BSEC_DENABLE_SPIDEN_Pos) /*!< 0x00000020 */
#define BSEC_DENABLE_SPIDEN BSEC_DENABLE_SPIDEN_Msk /*!< secure privilege invasive debug enable with signal spniden */
-#define BSEC_DENABLE_SPNIDEN_Pos (6U)
+#define BSEC_DENABLE_SPNIDEN_Pos (6U)
#define BSEC_DENABLE_SPNIDEN_Msk (0x1U << BSEC_DENABLE_SPNIDEN_Pos) /*!< 0x00000040 */
#define BSEC_DENABLE_SPNIDEN BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable with signal spiden */
-#define BSEC_DENABLE_CP15SDISABLE_Pos (7U)
+#define BSEC_DENABLE_CP15SDISABLE_Pos (7U)
#define BSEC_DENABLE_CP15SDISABLE_Msk (0x3U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000180 */
#define BSEC_DENABLE_CP15SDISABLE BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers disable CPDISABLE[0] applies to CPU0. CPDISABLE[1] applies to CPU1 */
#define BSEC_DENABLE_CP15SDISABLE_0 (0x1U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000080 */
#define BSEC_DENABLE_CP15SDISABLE_1 (0x2U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000100 */
-#define BSEC_DENABLE_CFGSDISABLE_Pos (9U)
+#define BSEC_DENABLE_CFGSDISABLE_Pos (9U)
#define BSEC_DENABLE_CFGSDISABLE_Msk (0x1U << BSEC_DENABLE_CFGSDISABLE_Pos) /*!< 0x00000200 */
#define BSEC_DENABLE_CFGSDISABLE BSEC_DENABLE_CFGSDISABLE_Msk /*!< write access to secure GIC registers disable with signal cfgsdisable */
-#define BSEC_DENABLE_DBGSWENABLE_Pos (10U)
+#define BSEC_DENABLE_DBGSWENABLE_Pos (10U)
#define BSEC_DENABLE_DBGSWENABLE_Msk (0x1U << BSEC_DENABLE_DBGSWENABLE_Pos) /*!< 0x00000400 */
#define BSEC_DENABLE_DBGSWENABLE BSEC_DENABLE_DBGSWENABLE_Msk /*!< control self hosted debug enable with signal dbgswenable */
@@ -18184,766 +22989,2333 @@
/* */
/******************************************************************************/
/******************** Bit definition for RCC_TZCR register********************/
-#define RCC_TZCR_TZEN_Pos (0U)
-#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
-#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/
-#define RCC_TZCR_MCKPROT_Pos (1U)
-#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
-#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/
+#define RCC_TZCR_TZEN_Pos (0U)
+#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
+#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */
+#define RCC_TZCR_MCKPROT_Pos (1U)
+#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
+#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */
-/******************** Bit definition for RCC_OCENSETR register********************/
-#define RCC_OCENSETR_HSION_Pos (0U)
-#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/
-#define RCC_OCENSETR_HSIKERON_Pos (1U)
-#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
-#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_CSION_Pos (4U)
-#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
-#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/
-#define RCC_OCENSETR_CSIKERON_Pos (5U)
-#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
-#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_DIGBYP_Pos (7U)
-#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */
-#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/
-#define RCC_OCENSETR_HSEON_Pos (8U)
-#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
-#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/
-#define RCC_OCENSETR_HSEKERON_Pos (9U)
-#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
-#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/
-#define RCC_OCENSETR_HSEBYP_Pos (10U)
-#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
-#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/
-#define RCC_OCENSETR_HSECSSON_Pos (11U)
-#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
-#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/
+/***************** Bit definition for RCC_OCENSETR register *****************/
+#define RCC_OCENSETR_HSION_Pos (0U)
+#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */
+#define RCC_OCENSETR_HSIKERON_Pos (1U)
+#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */
+#define RCC_OCENSETR_CSION_Pos (4U)
+#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */
+#define RCC_OCENSETR_CSIKERON_Pos (5U)
+#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */
+#define RCC_OCENSETR_DIGBYP_Pos (7U)
+#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */
+#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */
+#define RCC_OCENSETR_HSEON_Pos (8U)
+#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */
+#define RCC_OCENSETR_HSEKERON_Pos (9U)
+#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */
+#define RCC_OCENSETR_HSEBYP_Pos (10U)
+#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */
+#define RCC_OCENSETR_HSECSSON_Pos (11U)
+#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
+#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */
-/******************** Bit definition for RCC_OCENCLRR register********************/
-#define RCC_OCENCLRR_HSION_Pos (0U)
-#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/
-#define RCC_OCENCLRR_HSIKERON_Pos (1U)
-#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
-#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/
-#define RCC_OCENCLRR_CSION_Pos (4U)
-#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
-#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/
-#define RCC_OCENCLRR_CSIKERON_Pos (5U)
-#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
-#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/
-#define RCC_OCENCLRR_DIGBYP_Pos (7U)
-#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */
-#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/
-#define RCC_OCENCLRR_HSEON_Pos (8U)
-#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
-#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/
-#define RCC_OCENCLRR_HSEKERON_Pos (9U)
-#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
-#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/
-#define RCC_OCENCLRR_HSEBYP_Pos (10U)
-#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
-#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/
+/***************** Bit definition for RCC_OCENCLRR register *****************/
+#define RCC_OCENCLRR_HSION_Pos (0U)
+#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */
+#define RCC_OCENCLRR_HSIKERON_Pos (1U)
+#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */
+#define RCC_OCENCLRR_CSION_Pos (4U)
+#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */
+#define RCC_OCENCLRR_CSIKERON_Pos (5U)
+#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */
+#define RCC_OCENCLRR_DIGBYP_Pos (7U)
+#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */
+#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */
+#define RCC_OCENCLRR_HSEON_Pos (8U)
+#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */
+#define RCC_OCENCLRR_HSEKERON_Pos (9U)
+#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */
+#define RCC_OCENCLRR_HSEBYP_Pos (10U)
+#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */
-/******************** Bit definition for RCC_OCRDYR register********************/
-#define RCC_OCRDYR_HSIRDY_Pos (0U)
-#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */
-#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/
-#define RCC_OCRDYR_HSIDIVRDY_Pos (2U)
-#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
-#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/
-#define RCC_OCRDYR_CSIRDY_Pos (4U)
-#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */
-#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/
-#define RCC_OCRDYR_HSERDY_Pos (8U)
-#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */
-#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/
-#define RCC_OCRDYR_AXICKRDY_Pos (24U)
-#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
-#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/
-#define RCC_OCRDYR_CKREST_Pos (25U)
-#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */
-#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/
+/***************** Bit definition for RCC_HSICFGR register ******************/
+#define RCC_HSICFGR_HSIDIV_Pos (0U)
+#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */
+#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSITRIM_Pos (8U)
+#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */
+#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */
+#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */
+#define RCC_HSICFGR_HSICAL_Pos (16U)
+#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */
+#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */
+#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */
+#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */
+#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */
+#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */
+#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */
+#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */
+#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */
+#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */
+#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */
-/******************** Bit definition for RCC_DBGCFGR register********************/
-#define RCC_DBGCFGR_TRACEDIV_Pos (0U)
-#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
-#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/
-#define RCC_DBGCFGR_DBGCKEN_Pos (8U)
-#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
-#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/
-#define RCC_DBGCFGR_TRACECKEN_Pos (9U)
-#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
-#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/
-#define RCC_DBGCFGR_DBGRST_Pos (12U)
-#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
-#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/
+/***************** Bit definition for RCC_CSICFGR register ******************/
+#define RCC_CSICFGR_CSITRIM_Pos (8U)
+#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */
+#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_CSICFGR_CSICAL_Pos (16U)
+#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */
+#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */
+#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */
+#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */
+#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */
+#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */
+#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */
+#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */
+#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */
-/******************** Bit definition for RCC_HSICFGR register********************/
-#define RCC_HSICFGR_HSIDIV_Pos (0U)
-#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos)
-#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/
-#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/
-#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */
-#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */
-#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */
+/***************** Bit definition for RCC_MPCKSELR register *****************/
+#define RCC_MPCKSELR_MPUSRC_Pos (0U)
+#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */
+#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
+#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
+#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
+#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */
-#define RCC_HSICFGR_HSITRIM_Pos (8U)
-#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos)
-#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/
+/**************** Bit definition for RCC_ASSCKSELR register *****************/
+#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
+#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
+#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
+#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
+#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
+#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
+#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */
-#define RCC_HSICFGR_HSICAL_Pos (16U)
-#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos)
-#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/
+/**************** Bit definition for RCC_RCK12SELR register *****************/
+#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
+#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */
+#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
+#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */
-/******************** Bit definition for RCC_CSICFGR register********************/
-#define RCC_CSICFGR_CSITRIM_Pos (8U)
-#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos)
-#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/
+/***************** Bit definition for RCC_MPCKDIVR register *****************/
+#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
+#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */
+#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
+#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
+#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
+#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
+#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */
-#define RCC_CSICFGR_CSICAL_Pos (16U)
-#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos)
-#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/
+/***************** Bit definition for RCC_AXIDIVR register ******************/
+#define RCC_AXIDIVR_AXIDIV_Pos (0U)
+#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */
+#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
+#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
+#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
+#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
+#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */
-/******************** Bit definition for RCC_MCO1CFGR register********************/
-#define RCC_MCO1CFGR_MCO1SEL_Pos (0U)
-#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
-#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/
-#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */
-#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
-#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
-#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */
-#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
+/***************** Bit definition for RCC_APB4DIVR register *****************/
+#define RCC_APB4DIVR_APB4DIV_Pos (0U)
+#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */
+#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
+#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */
-#define RCC_MCO1CFGR_MCO1DIV_Pos (4U)
-#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
-#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/
-#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */
-#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
-#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
-#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */
-#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
-#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */
-#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */
-#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */
-#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
-#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */
-#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */
-#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */
-#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */
-#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */
-#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */
-#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
+/***************** Bit definition for RCC_APB5DIVR register *****************/
+#define RCC_APB5DIVR_APB5DIV_Pos (0U)
+#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */
+#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
+#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */
-#define RCC_MCO1CFGR_MCO1ON_Pos (12U)
-#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
-#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/
+/***************** Bit definition for RCC_RTCDIVR register ******************/
+#define RCC_RTCDIVR_RTCDIV_Pos (0U)
+#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
+#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */
+#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */
+#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */
+#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */
+#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */
+#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */
+#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */
-/******************** Bit definition for RCC_MCO2CFGR register********************/
-#define RCC_MCO2CFGR_MCO2SEL_Pos (0U)
-#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
-#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/
-#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */
-#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
-#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
-#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */
-#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
-#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */
+/**************** Bit definition for RCC_MSSCKSELR register *****************/
+#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
+#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */
+#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
+#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
+#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
+#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */
-#define RCC_MCO2CFGR_MCO2DIV_Pos (4U)
-#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
-#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/
-#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */
-#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
-#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
-#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */
-#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
-#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */
-#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */
-#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */
-#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
-#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */
-#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */
-#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */
-#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */
-#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */
-#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */
-#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
+/****************** Bit definition for RCC_PLL1CR register ******************/
+#define RCC_PLL1CR_PLLON_Pos (0U)
+#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */
+#define RCC_PLL1CR_PLL1RDY_Pos (1U)
+#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */
+#define RCC_PLL1CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */
+#define RCC_PLL1CR_DIVPEN_Pos (4U)
+#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */
+#define RCC_PLL1CR_DIVQEN_Pos (5U)
+#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */
+#define RCC_PLL1CR_DIVREN_Pos (6U)
+#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */
-#define RCC_MCO2CFGR_MCO2ON_Pos (12U)
-#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
-#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/
+/**************** Bit definition for RCC_PLL1CFGR1 register *****************/
+#define RCC_PLL1CFGR1_DIVN_Pos (0U)
+#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */
+#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CFGR1_DIVM1_Pos (16U)
+#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
+#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */
+#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */
-/******************** Bit definition for RCC_MPCKSELR register********************/
-#define RCC_MPCKSELR_MPUSRC_Pos (0U)
-#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
-#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/
-#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */
-#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
-#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
-#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_PLL1CFGR2 register *****************/
+#define RCC_PLL1CFGR2_DIVP_Pos (0U)
+#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */
+#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */
+#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL1CFGR2_DIVR_Pos (16U)
+#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */
+#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */
+/**************** Bit definition for RCC_PLL1FRACR register *****************/
+#define RCC_PLL1FRACR_FRACV_Pos (3U)
+#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */
+#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL1FRACR_FRACLE_Pos (16U)
+#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */
-#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
-#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/
+/***************** Bit definition for RCC_PLL1CSGR register *****************/
+#define RCC_PLL1CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */
+#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */
+#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */
+#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */
+#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */
+#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */
+#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */
+#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */
+#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */
+#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */
+#define RCC_PLL1CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */
+#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */
+#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */
+#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */
+#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */
+#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */
+#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */
+#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */
+#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */
+#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */
+#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */
+#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */
+#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */
-/******************** Bit definition for RCC_ASSCKSELR register********************/
-#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
-#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
-#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/
-#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */
-#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
-#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
-#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */
-#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
-#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */
-#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */
-#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+/****************** Bit definition for RCC_PLL2CR register ******************/
+#define RCC_PLL2CR_PLLON_Pos (0U)
+#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */
+#define RCC_PLL2CR_PLL2RDY_Pos (1U)
+#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+#define RCC_PLL2CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */
+#define RCC_PLL2CR_DIVPEN_Pos (4U)
+#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */
+#define RCC_PLL2CR_DIVQEN_Pos (5U)
+#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */
+#define RCC_PLL2CR_DIVREN_Pos (6U)
+#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */
-#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
-#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/
+/**************** Bit definition for RCC_PLL2CFGR1 register *****************/
+#define RCC_PLL2CFGR1_DIVN_Pos (0U)
+#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */
+#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */
+#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
+#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
+#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */
+#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */
-/******************** Bit definition for RCC_MSSCKSELR register********************/
-#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
-#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
-#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/
-#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */
-#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
-#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
-#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_PLL2CFGR2 register *****************/
+#define RCC_PLL2CFGR2_DIVP_Pos (0U)
+#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */
+#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */
+#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */
+#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */
+#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */
+#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */
+#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */
+#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */
+#define RCC_PLL2CFGR2_DIVR_Pos (16U)
+#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */
+#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */
+#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */
-#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
-#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/
+/**************** Bit definition for RCC_PLL2FRACR register *****************/
+#define RCC_PLL2FRACR_FRACV_Pos (3U)
+#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */
+#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */
+#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */
+#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */
+#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */
+#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */
+#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */
+#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */
+#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */
+#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */
+#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */
+#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */
+#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */
+#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */
+#define RCC_PLL2FRACR_FRACLE_Pos (16U)
+#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */
-/******************** Bit definition for RCC_RCK12SELR register********************/
-#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
-#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/
-#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */
-#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */
-#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */
-#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */
+/***************** Bit definition for RCC_PLL2CSGR register *****************/
+#define RCC_PLL2CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */
+#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */
+#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */
+#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */
+#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */
+#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */
+#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */
+#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */
+#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */
+#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */
+#define RCC_PLL2CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */
+#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */
+#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */
+#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */
+#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */
+#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */
+#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */
+#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */
+#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */
+#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */
+#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */
+#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */
+#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */
-#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
-#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/
+/*************** Bit definition for RCC_I2C46CKSELR register ****************/
+#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U)
+#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */
+#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RCK3SELR register********************/
-#define RCC_RCK3SELR_PLL3SRC_Pos (0U)
-#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/
-#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_SPI6CKSELR register ****************/
+#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U)
+#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */
+#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
-#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U)
-#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/
+/*************** Bit definition for RCC_UART1CKSELR register ****************/
+#define RCC_UART1CKSELR_UART1SRC_Pos (0U)
+#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */
+#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
-/******************** Bit definition for RCC_RCK4SELR register********************/
-#define RCC_RCK4SELR_PLL4SRC_Pos (0U)
-#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
-#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/
-#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */
-#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
-#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
+/**************** Bit definition for RCC_RNG1CKSELR register ****************/
+#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U)
+#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
+#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */
+#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
+#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
-#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U)
-#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
-#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/
+/**************** Bit definition for RCC_CPERCKSELR register ****************/
+#define RCC_CPERCKSELR_CKPERSRC_Pos (0U)
+#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
+#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */
+#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
+#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
-/******************** Bit definition for RCC_TIMG1PRER register********************/
-#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U)
-#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
-#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/
-#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */
- /*corresponding to a division by 1 or 2, else it is equal to
- 2 x Fck_pclk1 (default after reset)*/
-#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is
- corresponding to division by 1, 2 or 4, else it is equal to
- 4 x Fck_pclk1 */
+/*************** Bit definition for RCC_STGENCKSELR register ****************/
+#define RCC_STGENCKSELR_STGENSRC_Pos (0U)
+#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
+#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */
+#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
+#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
-#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U)
-#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
-#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/
+/***************** Bit definition for RCC_DDRITFCR register *****************/
+#define RCC_DDRITFCR_DDRC1EN_Pos (0U)
+#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */
+#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */
+#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U)
+#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */
+#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRC2EN_Pos (2U)
+#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */
+#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */
+#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U)
+#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */
+#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U)
+#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */
+#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */
+#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U)
+#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */
+#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U)
+#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */
+#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */
+#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U)
+#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */
+#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */
+#define RCC_DDRITFCR_AXIDCGEN_Pos (8U)
+#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */
+#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */
+#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U)
+#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */
+#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */
+#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U)
+#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
+#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */
+#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
+#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
+#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
+#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U)
+#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */
+#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */
+#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U)
+#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */
+#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */
+#define RCC_DDRITFCR_DDRCORERST_Pos (16U)
+#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */
+#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */
+#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U)
+#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */
+#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */
+#define RCC_DDRITFCR_DPHYRST_Pos (18U)
+#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */
+#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */
+#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U)
+#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */
+#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */
+#define RCC_DDRITFCR_DDRCKMOD_Pos (20U)
+#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
+#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */
+#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
+#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
+#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */
+#define RCC_DDRITFCR_GSKPMOD_Pos (23U)
+#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */
+#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */
+#define RCC_DDRITFCR_GSKPCTRL_Pos (24U)
+#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */
+#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */
+#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U)
+#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */
+#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */
+#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */
+#define RCC_DDRITFCR_GSKP_DUR_Pos (28U)
+#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */
+#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */
+#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */
+#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */
+#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */
+#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */
-/******************** Bit definition for RCC_TIMG2PRER register********************/
-#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U)
-#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
-#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/
-#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */
- /*corresponding to a division by 1 or 2, else it is equal
- to 2 x Fck_pclk2 (default after reset)*/
-#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is
- corresponding to division by 1, 2 or 4, else it is equal to
- 4 x Fck_pclk2 */
+/**************** Bit definition for RCC_MP_BOOTCR register *****************/
+#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U)
+#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */
+#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U)
+#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */
+
+/*************** Bit definition for RCC_MP_SREQSETR register ****************/
+#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */
+#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */
+
+/*************** Bit definition for RCC_MP_SREQCLRR register ****************/
+#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */
+#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */
+
+/****************** Bit definition for RCC_MP_GCR register ******************/
+#define RCC_MP_GCR_BOOT_MCU_Pos (0U)
+#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
+#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */
+
+/**************** Bit definition for RCC_MP_APRSTCR register ****************/
+#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U)
+#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */
+#define RCC_MP_APRSTCR_RSTTO_Pos (8U)
+#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */
+#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */
+#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */
+#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */
+#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */
+#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */
+#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */
+#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */
+
+/**************** Bit definition for RCC_MP_APRSTSR register ****************/
+#define RCC_MP_APRSTSR_RSTTOV_Pos (8U)
+#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */
+#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */
+#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */
+#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */
+#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */
+#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */
+#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */
+#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */
+#define RCC_BDCR_LSEBYP_Pos (1U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */
+#define RCC_BDCR_LSERDY_Pos (2U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */
+#define RCC_BDCR_DIGBYP_Pos (3U)
+#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */
+#define RCC_BDCR_LSEDRV_Pos (4U)
+#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */
+#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON_Pos (8U)
+#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */
+#define RCC_BDCR_LSECSSD_Pos (9U)
+#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */
+#define RCC_BDCR_RTCSRC_Pos (16U)
+#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
+#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */
+#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */
+#define RCC_BDCR_RTCCKEN_Pos (20U)
+#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */
+#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_VSWRST_Pos (31U)
+#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */
+
+/***************** Bit definition for RCC_RDLSICR register ******************/
+#define RCC_RDLSICR_LSION_Pos (0U)
+#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */
+#define RCC_RDLSICR_LSIRDY_Pos (1U)
+#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */
+#define RCC_RDLSICR_MRD_Pos (16U)
+#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */
+#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */
+#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */
+#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */
+#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */
+#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */
+#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */
+#define RCC_RDLSICR_EADLY_Pos (24U)
+#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */
+#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */
+#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */
+#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */
+#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */
+#define RCC_RDLSICR_SPARE_Pos (27U)
+#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */
+#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */
+#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */
+#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */
+#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */
+#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */
+#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */
+
+/*************** Bit definition for RCC_APB4RSTSETR register ****************/
+#define RCC_APB4RSTSETR_LTDCRST_Pos (0U)
+#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */
+#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */
+#define RCC_APB4RSTSETR_DSIRST_Pos (4U)
+#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */
+#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */
+#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U)
+#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */
+#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */
+#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U)
+#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */
+
+/*************** Bit definition for RCC_APB4RSTCLRR register ****************/
+#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U)
+#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */
+#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */
+#define RCC_APB4RSTCLRR_DSIRST_Pos (4U)
+#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */
+#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */
+#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U)
+#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */
+#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */
+#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U)
+#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */
+
+/*************** Bit definition for RCC_APB5RSTSETR register ****************/
+#define RCC_APB5RSTSETR_SPI6RST_Pos (0U)
+#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */
+#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */
+#define RCC_APB5RSTSETR_I2C4RST_Pos (2U)
+#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */
+#define RCC_APB5RSTSETR_I2C6RST_Pos (3U)
+#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */
+#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */
+#define RCC_APB5RSTSETR_USART1RST_Pos (4U)
+#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */
+#define RCC_APB5RSTSETR_STGENRST_Pos (20U)
+#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */
+#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */
+
+/*************** Bit definition for RCC_APB5RSTCLRR register ****************/
+#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U)
+#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */
+#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */
+#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U)
+#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */
+#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U)
+#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */
+#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */
+#define RCC_APB5RSTCLRR_USART1RST_Pos (4U)
+#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */
+#define RCC_APB5RSTCLRR_STGENRST_Pos (20U)
+#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */
+#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */
+
+/*************** Bit definition for RCC_AHB5RSTSETR register ****************/
+#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U)
+#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */
+#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U)
+#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */
+#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U)
+#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */
+#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U)
+#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */
+#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U)
+#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */
+
+/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/
+#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U)
+#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */
+#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U)
+#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */
+#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U)
+#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */
+#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */
+#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U)
+#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */
+#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U)
+#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */
+
+/*************** Bit definition for RCC_AHB6RSTSETR register ****************/
+#define RCC_AHB6RSTSETR_GPURST_Pos (5U)
+#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */
+#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */
+#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U)
+#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */
+#define RCC_AHB6RSTSETR_FMCRST_Pos (12U)
+#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */
+#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U)
+#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */
+#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U)
+#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */
+#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U)
+#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */
+#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */
+#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U)
+#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */
+#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */
+#define RCC_AHB6RSTSETR_USBHRST_Pos (24U)
+#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */
+#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */
+
+/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/
+#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U)
+#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */
+#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U)
+#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */
+#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U)
+#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */
+#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U)
+#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */
+#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */
+#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U)
+#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */
+#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */
+#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U)
+#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */
+#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */
+#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U)
+#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */
+#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */
+
+/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/
+#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U)
+#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */
+#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */
+
+/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/
+#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U)
+#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */
+#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */
+
+/************** Bit definition for RCC_MP_APB4ENSETR register ***************/
+#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U)
+#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U)
+#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U)
+#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U)
+#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */
+#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U)
+#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */
+#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U)
+#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/
+#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U)
+#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U)
+#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U)
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U)
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */
+#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U)
+#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */
+#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U)
+#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */
+
+/************** Bit definition for RCC_MP_APB5ENSETR register ***************/
+#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U)
+#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U)
+#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U)
+#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U)
+#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U)
+#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */
+#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U)
+#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */
+#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U)
+#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */
+#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U)
+#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */
+#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U)
+#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */
+#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U)
+#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/
+#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U)
+#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U)
+#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U)
+#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U)
+#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U)
+#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */
+#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U)
+#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */
+#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U)
+#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */
+#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U)
+#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U)
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */
+#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U)
+#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */
+#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U)
+#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */
+
+/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/
+#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U)
+#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U)
+#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U)
+#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U)
+#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U)
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
+#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U)
+#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */
+
+/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/
+#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U)
+#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U)
+#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U)
+#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U)
+#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U)
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
+#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U)
+#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */
+
+/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/
+#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U)
+#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U)
+#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U)
+#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */
+#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U)
+#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */
+#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U)
+#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */
+#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U)
+#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U)
+#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U)
+#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U)
+#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U)
+#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U)
+#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */
+
+/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/
+#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U)
+#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U)
+#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U)
+#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */
+#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U)
+#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */
+#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U)
+#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */
+#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U)
+#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U)
+#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U)
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U)
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U)
+#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U)
+#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */
+
+/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/
+#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+
+/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB4ENSETR register ***************/
+#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U)
+#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U)
+#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U)
+#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U)
+#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */
+#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U)
+#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/
+#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U)
+#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U)
+#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U)
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */
+#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U)
+#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */
+#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U)
+#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */
+
+/************** Bit definition for RCC_MC_APB5ENSETR register ***************/
+#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U)
+#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U)
+#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U)
+#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U)
+#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U)
+#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */
+#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U)
+#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */
+#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U)
+#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */
+#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U)
+#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U)
+#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */
+#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U)
+#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */
+
+/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/
+#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U)
+#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U)
+#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U)
+#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U)
+#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U)
+#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */
+#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U)
+#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */
+#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U)
+#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */
+#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */
+#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U)
+#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */
+#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U)
+#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */
+#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U)
+#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */
+
+/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/
+#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U)
+#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U)
+#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U)
+#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U)
+#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U)
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
-#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U)
-#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
-#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/
+/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/
+#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U)
+#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U)
+#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */
+#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U)
+#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U)
+#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */
+#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U)
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */
-/******************** Bit definition for RCC_RTCDIVR register********************/
-#define RCC_RTCDIVR_RTCDIV_Pos (0U)
-#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
-#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/
-#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos)
-#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos)
+/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/
+#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U)
+#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U)
+#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U)
+#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U)
+#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */
+#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U)
+#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */
+#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U)
+#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */
+#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U)
+#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U)
+#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U)
+#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U)
+#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U)
+#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U)
+#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */
-#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/
+/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/
+#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U)
+#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U)
+#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */
+#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U)
+#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */
+#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */
+#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U)
+#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */
+#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U)
+#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */
+#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */
+#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U)
+#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */
+#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */
+#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U)
+#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */
+#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U)
+#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */
+#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U)
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U)
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U)
+#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */
+#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */
+#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U)
+#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */
+#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */
-/******************** Bit definition for RCC_MPCKDIVR register********************/
-#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
-#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
-#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/
-#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */
-#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
-#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
-#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */
-#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
-#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */
-#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */
-#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_APB4LPENSETR register **************/
+#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U)
+#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U)
+#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U)
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U)
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U)
+#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U)
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */
-#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
-#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/
+/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U)
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U)
+#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U)
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U)
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U)
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U)
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */
-/******************** Bit definition for RCC_AXIDIVR register********************/
-#define RCC_AXIDIVR_AXIDIV_Pos (0U)
-#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
-#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/
-#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */
-#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
-#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
-#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */
-#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
-#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */
-#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */
-#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_APB5LPENSETR register **************/
+#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U)
+#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U)
+#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U)
+#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U)
+#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U)
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U)
+#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U)
+#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U)
+#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U)
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U)
+#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U)
+#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U)
+#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */
-#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
-#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/
+/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U)
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U)
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U)
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U)
+#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U)
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U)
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U)
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U)
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U)
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U)
+#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U)
+#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U)
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */
-/******************** Bit definition for RCC_APB4DIVR register********************/
-#define RCC_APB4DIVR_APB4DIV_Pos (0U)
-#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */
-#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
-#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */
-#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */
-#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U)
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U)
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U)
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U)
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
-#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/
+/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U)
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U)
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U)
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U)
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U)
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */
-/******************** Bit definition for RCC_APB5DIVR register********************/
-#define RCC_APB5DIVR_APB5DIV_Pos (0U)
-#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/
-#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
-#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */
-#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */
-#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/
+#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U)
+#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U)
+#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U)
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U)
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U)
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U)
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U)
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U)
+#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U)
+#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U)
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U)
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U)
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U)
+#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
-#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/
+/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U)
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U)
+#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */
+#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U)
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U)
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U)
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U)
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U)
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U)
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U)
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U)
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U)
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U)
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U)
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */
-/******************** Bit definition for RCC_MCUDIVR register********************/
-#define RCC_MCUDIVR_MCUDIV_Pos (0U)
-#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
-#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/
-#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */
-#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
-#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
-#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */
-#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
-#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */
-#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */
-#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */
-#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
-#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */
-/* @note others: ck_mcuss divided by 512 */
+/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U)
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
-#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U)
-#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/
-/******************** Bit definition for RCC_APB1DIVR register********************/
-#define RCC_APB1DIVR_APB1DIV_Pos (0U)
-#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/
-#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
-/* @note others: ck_hclk/16 */
+/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U)
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */
-#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U)
-#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/
+/************* Bit definition for RCC_MC_APB4LPENSETR register **************/
+#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U)
+#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U)
+#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U)
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U)
+#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U)
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */
-/******************** Bit definition for RCC_APB2DIV register********************/
-#define RCC_APB2DIVR_APB2DIV_Pos (0U)
-#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
-#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/
-#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */
-#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
-#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
-#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */
-#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
-/* @note others: ck_hclk/16 */
+/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U)
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U)
+#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U)
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U)
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U)
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U)
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */
-#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U)
-#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
-#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/
+/************* Bit definition for RCC_MC_APB5LPENSETR register **************/
+#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U)
+#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */
+#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U)
+#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U)
+#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */
+#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U)
+#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U)
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U)
+#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */
+#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */
+#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U)
+#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */
+#d