)]}' { "log": [ { "commit": "2c4ca6832fa6b306ee6a7010bfb80a3f2596f824", "tree": "b978d8fba715be02c4f33013cc94e12267e2c86c", "parents": [ "6e8533b05630a1e06d39a61270dcbf6d0662b3b5" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Oct 22 15:39:47 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Oct 22 15:39:47 2019" }, "message": "[InstCombine] Signed saturation patterns\n\nThis adds an instcombine matcher for code that attempts to perform signed\nsaturating arithmetic by casting to a higher type. Unsigned cases are already\nmatched, this adds extra matches for the more complex signed cases, which\ninvolves matching the min(max(add a b)) nodes with proper extends to ensure\nlegality.\n\nDifferential Revision: https://reviews.llvm.org/D68651\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375505 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "6e8533b05630a1e06d39a61270dcbf6d0662b3b5", "tree": "4b7027c8e93078607cad5d7e183b42243e56e72c", "parents": [ "e6fb6db5680e297e0b99739dcfbdb4d72ddd752b" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Oct 22 14:49:40 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Tue Oct 22 14:49:40 2019" }, "message": "[InstCombine] Signed saturation tests. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375503 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "e6fb6db5680e297e0b99739dcfbdb4d72ddd752b", "tree": "21969fd96012bfba3cfbd70379a9f615d38185ca", "parents": [ "ee57dd49214a7ca74f0b01111bf0ce16d42cecb5" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 14:25:37 2019" }, "committer": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 14:25:37 2019" }, "message": "[MIParser] Set RegClassOrRegBank during instruction parsing\n\nMachineRegisterInfo::createGenericVirtualRegister sets\nRegClassOrRegBank to static_cast\u003cRegisterBank *\u003e(nullptr).\nMIParser on the other hand doesn\u0027t. When we attempt to constrain\nRegister Class on such VReg, additional COPY is generated.\nThis way we avoid COPY instructions showing in test that have MIR\ninput while they are not present with llvm-ir input that was used\nto create given MIR for a -run-pass test.\n\nDifferential Revision: https://reviews.llvm.org/D68946\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "ee57dd49214a7ca74f0b01111bf0ce16d42cecb5", "tree": "b8303681706acf70021efcdd4031e2d292315541", "parents": [ "a461b7a03cde32cd6560dcbcea23ec51dfd1e522" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 13:51:57 2019" }, "committer": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 13:51:57 2019" }, "message": "[MIPS GlobalISel] Select MSA vector generic and builtin add\n\nSelect vector G_ADD for MIPS32 with MSA. We have to set bank\nfor vector operands to fprb and selectImpl will do the rest.\n__builtin_msa_addv_\u003cformat\u003e will be transformed into G_ADD\nin legalizeIntrinsic and selected in the same way.\n__builtin_msa_addvi_\u003cformat\u003e will be directly selected into\nADDVI_\u003cformat\u003e in legalizeIntrinsic. MIR tests for it have\nunnecessary additional copies. Capture current state of tests\nwith run-pass\u003dlegalizer with a test in test/CodeGen/MIR/Mips.\n\nDifferential Revision: https://reviews.llvm.org/D68984\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375501 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "a461b7a03cde32cd6560dcbcea23ec51dfd1e522", "tree": "2a33036b1a7a382a92c89bb845ad3808285de945", "parents": [ "31ec98d4e0ebdcc2df0759eebb9450ead50ed4af" ], "author": { "name": "Eugene Leviant", "email": "eleviant@accesssoftek.com", "time": "Tue Oct 22 12:57:23 2019" }, "committer": { "name": "Eugene Leviant", "email": "eleviant@accesssoftek.com", "time": "Tue Oct 22 12:57:23 2019" }, "message": "[ThinLTO] Add code comment. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375500 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "31ec98d4e0ebdcc2df0759eebb9450ead50ed4af", "tree": "03af754b1ce4919778ad6fb7fd02d412daac8002", "parents": [ "8b6d26ec6649ab1d1c5c525eadfaebb3ce7fa95d" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 12:55:32 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 12:55:32 2019" }, "message": "[Alignment][NFC] Convert StoreInst to MaybeAlign\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: hiraditya, jfb, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69303\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375499 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "8b6d26ec6649ab1d1c5c525eadfaebb3ce7fa95d", "tree": "b802e80ca9ed74e8e6efe70467c586eb15adee12", "parents": [ "4a0e8977ca0ab9377b5b18a0673d255e79e81c4a" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 12:35:55 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 12:35:55 2019" }, "message": "[Alignment][NFC] Convert LoadInst to MaybeAlign\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: hiraditya, jfb, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69302\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375498 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "4a0e8977ca0ab9377b5b18a0673d255e79e81c4a", "tree": "9e2f9536003bd78a8b31dcf622fc52ca92c2bc1e", "parents": [ "77450cd6096f48aee164cf7efc12bd20cd563ffc" ], "author": { "name": "Nemanja Ivanovic", "email": "nemanja.i.ibm@gmail.com", "time": "Tue Oct 22 12:20:38 2019" }, "committer": { "name": "Nemanja Ivanovic", "email": "nemanja.i.ibm@gmail.com", "time": "Tue Oct 22 12:20:38 2019" }, "message": "[PowerPC] Turn on CR-Logical reducer pass\n\nThis re-commits r375152 which was pulled in r375233 because it broke\nthe EXPENSIVE_CHECKS bot on Windows.\n\nThe reason for the failure was a bug in the pass that the commit turned\non by default. This patch fixes that bug and turns the pass back on.\nThis patch has been verified on the buildbot that originally failed\nthanks to Simon Pilgrim.\n\nDifferential revision: https://reviews.llvm.org/D52431\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375497 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "77450cd6096f48aee164cf7efc12bd20cd563ffc", "tree": "98c19903997b154a7676776285d341543fa43b17", "parents": [ "672893cf12a38c4b71feb91fe268dc499f6bc817" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 11:57:52 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 11:57:52 2019" }, "message": "[Alignment][NFC] Use MaybeAlign in AttrBuilder\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69300\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375496 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "672893cf12a38c4b71feb91fe268dc499f6bc817", "tree": "15a4e9b683fcb4543681115955bca2fcb424e618", "parents": [ "55b4ec919455c3ca2254064e58b1bdc77d9ada7d" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 09:51:06 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Tue Oct 22 09:51:06 2019" }, "message": "[Alignment][NFC] Attributes use Align/MaybeAlign\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: jholewinski, hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69278\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375495 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "55b4ec919455c3ca2254064e58b1bdc77d9ada7d", "tree": "c60d11b62fd7a276fffb493065b7dd03cc05f70d", "parents": [ "5cd00d15af3c8387d497ba5945a3d88c9177685f" ], "author": { "name": "Eugene Leviant", "email": "eleviant@accesssoftek.com", "time": "Tue Oct 22 09:24:12 2019" }, "committer": { "name": "Eugene Leviant", "email": "eleviant@accesssoftek.com", "time": "Tue Oct 22 09:24:12 2019" }, "message": "[ThinLTO] Don\u0027t internalize during promotion\n\nDifferential revision: https://reviews.llvm.org/D69107\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375493 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "5cd00d15af3c8387d497ba5945a3d88c9177685f", "tree": "d0efc67d236af90b76714730c9c6895c8a838532", "parents": [ "d35e5f8dded4c884ca25ca88f184e1505cad106c" ], "author": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Tue Oct 22 08:52:45 2019" }, "committer": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Tue Oct 22 08:52:45 2019" }, "message": "[LLVMDebugInfoPDB] - Use cantFail() instead of assert().\n\nCurrently injected-sources-native.test fails with \"Expected\u003cT\u003e\nvalue was in success state.\n(Note: Expected\u003cT\u003e values in success mode must still be checked\nprior to being destroyed)\"\nwhen llvm is compiled with LLVM_ENABLE_ABI_BREAKING_CHECKS in Release.\n\nThe problem is that getStringForID returns Expected\u003cStringRef\u003e\nand Expected value must always be checked, even if it is in success state.\nChecking with assert only helps in Debug and is wrong.\n\nDifferential revision: https://reviews.llvm.org/D69251\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375492 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d35e5f8dded4c884ca25ca88f184e1505cad106c", "tree": "702181bf47f3089f5eb70edac89797e5fc3e1000", "parents": [ "5205202f41907377b35223fef500f2d5679995c4" ], "author": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Tue Oct 22 06:36:27 2019" }, "committer": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Tue Oct 22 06:36:27 2019" }, "message": "[CMake] [WinMsvc] Look for includes and libs in ${MSVC_BASE}/atlmfc\n\nThis is necessary if building with the DIA SDK enabled.\n\nDifferential Revision: https://reviews.llvm.org/D69240\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375486 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "5205202f41907377b35223fef500f2d5679995c4", "tree": "a2a9b9a9d3cac9dd9b13a2356c66562398600fa1", "parents": [ "719615b78fc3d8a27c955e72e3fd9a806b9cd069" ], "author": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Tue Oct 22 06:36:21 2019" }, "committer": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Tue Oct 22 06:36:21 2019" }, "message": "[CMake] Allow overriding MSVC_DIA_SDK_DIR via CMake\n\nThis eases using it in cross-msvc setups.\n\nDifferential Revision: https://reviews.llvm.org/D69239\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375485 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "719615b78fc3d8a27c955e72e3fd9a806b9cd069", "tree": "b8ac85afbf2c33134c074d565d59ccabd0274d83", "parents": [ "eab745a12b2b1273174a164cf5291694990372df" ], "author": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Tue Oct 22 05:09:35 2019" }, "committer": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Tue Oct 22 05:09:35 2019" }, "message": "gn build: Merge r375483\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375484 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "eab745a12b2b1273174a164cf5291694990372df", "tree": "45cbb621f5650b2ecdd36cbe91a01cd6203caf02", "parents": [ "9c3636fbb60037b5e1ec93a760700320e2a42e0c" ], "author": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Tue Oct 22 01:13:30 2019" }, "committer": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Tue Oct 22 01:13:30 2019" }, "message": "[lit] Move increase_process_limit to ParallelRun\n\nIncreasing the process limit only makes sense when we use multiple\nprocesses.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375474 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "9c3636fbb60037b5e1ec93a760700320e2a42e0c", "tree": "34d67d4ed826336dbb6fbbcb1af860563f76e097", "parents": [ "1e4c44b0d4d0c9febe6859b43ca0dcdfffa810a1" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 23:41:40 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 23:41:40 2019" }, "message": "[X86][BMI] Pull out schedule classes from bmi_andn\u003c\u003e and bmi_bls\u003c\u003e\n\nStop hardwiring classes\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375470 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "1e4c44b0d4d0c9febe6859b43ca0dcdfffa810a1", "tree": "f1ecd4554c167d58cc55cdad253ec0db802bc3c8", "parents": [ "d8c44a50c79df693503b9b1310572aa6501eb056" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 22:36:31 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 22:36:31 2019" }, "message": "[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) -\u003e MOVMSK+CMP reduction combine\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375463 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d8c44a50c79df693503b9b1310572aa6501eb056", "tree": "b84ffd08733bf008919461f7144a21c462ff9b79", "parents": [ "88e224ab979f051c45870027387c9de5eec90889" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 22:36:07 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 22:36:07 2019" }, "message": "[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) movmsk v2X64 tests\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375462 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "88e224ab979f051c45870027387c9de5eec90889", "tree": "3cc1225fa217d9a0b88172f7697c99f6461f5c5a", "parents": [ "34e11f6a0ac26fedba586002ac3df3f398cf5e7e" ], "author": { "name": "Lang Hames", "email": "lhames@gmail.com", "time": "Mon Oct 21 22:29:29 2019" }, "committer": { "name": "Lang Hames", "email": "lhames@gmail.com", "time": "Mon Oct 21 22:29:29 2019" }, "message": "[examples] Add a dependency on ExecutionEngine to LLJITWithObjectCache example.\n\nExecutionEngine.cpp contains the anchor() for the ObjectCache base class, so we\nneed an explicit dependency on it.\n\nPatch by Stephen Neuendorffer. Thanks Stephen!\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375461 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "34e11f6a0ac26fedba586002ac3df3f398cf5e7e", "tree": "63898c3f1e55d35e6e147799b70ea769e7c4766e", "parents": [ "6556cd04b75ffa4a0b467b6893f5eeda85c76b02" ], "author": { "name": "Austin Kerbow", "email": "Austin.Kerbow@amd.com", "time": "Mon Oct 21 22:18:26 2019" }, "committer": { "name": "Austin Kerbow", "email": "Austin.Kerbow@amd.com", "time": "Mon Oct 21 22:18:26 2019" }, "message": "AMDGPU/GlobalISel: Legalize fast unsafe FDIV\n\nReviewers: arsenm\n\nReviewed By: arsenm\n\nSubscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69231\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375460 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "6556cd04b75ffa4a0b467b6893f5eeda85c76b02", "tree": "451d1a0ca830a4a93a3119a78faff88560e53e65", "parents": [ "e672b94bb1e75d2ac528a56fda11a641b3f1fb2e" ], "author": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Mon Oct 21 21:57:18 2019" }, "committer": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Mon Oct 21 21:57:18 2019" }, "message": "[lit] Simplify test scheduling via multiprocessing.Pool\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375458 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "e672b94bb1e75d2ac528a56fda11a641b3f1fb2e", "tree": "5693a95f919d49c8cdff4fd754ea6633f14bdc24", "parents": [ "4d5ceef545f84faaa50859e845b55f84bac242da" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 21:49:44 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 21:49:44 2019" }, "message": "AMDGPU: Select basic interp directly from intrinsics\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375457 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "4d5ceef545f84faaa50859e845b55f84bac242da", "tree": "42e371b2dbe1c5ac5e275fdee2f630b5eb4e122a", "parents": [ "d8ca3c0d57a0db1a34ef78e860e4504593c69347" ], "author": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Mon Oct 21 21:41:59 2019" }, "committer": { "name": "Julian Lettner", "email": "jlettner@apple.com", "time": "Mon Oct 21 21:41:59 2019" }, "message": "[lit] Remove redundancy from names and comments\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375456 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d8ca3c0d57a0db1a34ef78e860e4504593c69347", "tree": "5200e74a52c0d089b44529a3c7be695c50f121f0", "parents": [ "c1a274e767a383f9ebf3d015b12d27fa5cba1b7a" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 21:31:19 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 21:31:19 2019" }, "message": "[CVP] No-wrap deduction for `shl`\n\nSummary:\nThis is the last `OverflowingBinaryOperator` for which we don\u0027t deduce flags.\nD69217 taught `ConstantRange::makeGuaranteedNoWrapRegion()` about it.\n\nThe effect is better than of the `mul` patch (D69203):\n\n| statistic | old | new | delta | % change |\n| correlated-value-propagation.NumAddNUW | 7145 | 7144 | -1 | -0.0140% |\n| correlated-value-propagation.NumAddNW | 12126 | 12125 | -1 | -0.0082% |\n| correlated-value-propagation.NumAnd | 443 | 446 | 3 | 0.6772% |\n| correlated-value-propagation.NumNSW | 5986 | 7158 | 1172 | 19.5790% |\n| correlated-value-propagation.NumNUW | 10512 | 13304 | 2792 | 26.5601% |\n| correlated-value-propagation.NumNW | 16498 | 20462 | 3964 | 24.0272% |\n| correlated-value-propagation.NumShlNSW | 0 | 1172 | 1172 | |\n| correlated-value-propagation.NumShlNUW | 0 | 2793 | 2793 | |\n| correlated-value-propagation.NumShlNW | 0 | 3965 | 3965 | |\n| instcount.NumAShrInst | 13824 | 13790 | -34 | -0.2459% |\n| instcount.NumAddInst | 277584 | 277586 | 2 | 0.0007% |\n| instcount.NumAndInst | 66061 | 66056 | -5 | -0.0076% |\n| instcount.NumBrInst | 709153 | 709147 | -6 | -0.0008% |\n| instcount.NumICmpInst | 483709 | 483708 | -1 | -0.0002% |\n| instcount.NumSExtInst | 79497 | 79496 | -1 | -0.0013% |\n| instcount.NumShlInst | 40691 | 40654 | -37 | -0.0909% |\n| instcount.NumSubInst | 61997 | 61996 | -1 | -0.0016% |\n| instcount.NumZExtInst | 68208 | 68211 | 3 | 0.0044% |\n| instcount.TotalBlocks | 843916 | 843910 | -6 | -0.0007% |\n| instcount.TotalInsts | 7387528 | 7387448 | -80 | -0.0011% |\n\nReviewers: nikic, reames, sanjoy, timshen\n\nReviewed By: nikic\n\nSubscribers: hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69277\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375455 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "c1a274e767a383f9ebf3d015b12d27fa5cba1b7a", "tree": "efdc0c1e8e8c1c674c9d83eaaed99112388a394e", "parents": [ "208bbb179720222f412df69505810970bc69a359" ], "author": { "name": "Quentin Colombet", "email": "quentin.colombet@gmail.com", "time": "Mon Oct 21 20:39:58 2019" }, "committer": { "name": "Quentin Colombet", "email": "quentin.colombet@gmail.com", "time": "Mon Oct 21 20:39:58 2019" }, "message": "[GISel][CombinerHelper] Add a combine turning shuffle_vector into concat_vectors\n\nTeach the CombinerHelper how to turn shuffle_vectors, that\nconcatenate vectors, into concat_vectors and add this combine\nto the AArch64 pre-legalizer combiner.\n\nDifferential Revision: https://reviews.llvm.org/D69149\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375452 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "208bbb179720222f412df69505810970bc69a359", "tree": "ba809a666f9a2466dd6e935b3620495099f24231", "parents": [ "fdc698b726543ec9a3066a8f98d95161c4b4d9f1" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:53:49 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:53:49 2019" }, "message": "AMDGPU: Use CopyToReg for interp intrinsic lowering\n\nThis doesn\u0027t use the default value, so doesn\u0027t benefit from the hack\nto help optimize it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375450 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "fdc698b726543ec9a3066a8f98d95161c4b4d9f1", "tree": "6d5300e4b5483148013eefef8155d58d3646aa70", "parents": [ "ab2c9f7c797d71e54387f4900b8a4efd28f3d8f5" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:53:46 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:53:46 2019" }, "message": "AMDGPU: Erase redundant redefs of m0 in SIFoldOperands\n\nOnly handle simple inter-block redefs of m0 to the same value. This\navoids interference from redefs of m0 in SILoadStoreOptimzer. I was\ninitially teaching that pass to ignore redefs of m0, but having them\nnot exist beforehand is much simpler.\n\nThis is in preparation for deleting the current special m0 handling in\nSIFixSGPRCopies to allow the register coalescer to handle the\ndifficult cases.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375449 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "ab2c9f7c797d71e54387f4900b8a4efd28f3d8f5", "tree": "6852b719e3c6d5500e153f2246fc44d46fc01e3a", "parents": [ "12be54ce900b8dc853b9bce54f0249aa76826b12" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:42:29 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:42:29 2019" }, "message": "AMDGPU: Stop adding m0 implicit def to SGPR spills\n\nr375293 removed the SGPR spilling with scalar stores path, so this is\nno longer necessary. This also always had the defect of adding the def\neven when this path wasn\u0027t in use.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375448 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "12be54ce900b8dc853b9bce54f0249aa76826b12", "tree": "df1480104eca986faaafbb81d5bb90a2a9e6a500", "parents": [ "6e6c5e79c99dc0eca108cd4bcaa4e31b9c64ea35" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:42:26 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Mon Oct 21 19:42:26 2019" }, "message": "AMDGPU: Slightly restructure m0 init code\n\nThis will allow using another operation to produce the glue in a\nfuture change.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375447 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "6e6c5e79c99dc0eca108cd4bcaa4e31b9c64ea35", "tree": "33b3712ec7c13b12111df5ebffd301c7aa7b4357", "parents": [ "b1407138d45ba368aefd73f33ecb25f09432531a" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Mon Oct 21 19:25:27 2019" }, "committer": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Mon Oct 21 19:25:27 2019" }, "message": "[AMDGPU] Select AGPR in PHI operand legalization\n\nIf a PHI defines AGPR legalize its operands to AGPR.\nAt the moment we can get an AGPR PHI with VGPR operands.\nI am not aware of any problems as it seems to be handled\ngracefully in RA, but this is not right anyway.\n\nIt also slightly decreases VGPR pressure in some cases\nbecause we do not have to a copy via VGPR.\n\nDifferential Revision: https://reviews.llvm.org/D69206\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375446 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b1407138d45ba368aefd73f33ecb25f09432531a", "tree": "87ff4b7a3a9a111862f89f8ab6ab98014b53a4de", "parents": [ "f5e25f84faff6c548ca1a767269cc0e32dc34095" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 19:19:50 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 19:19:50 2019" }, "message": "[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.\n\nThis doesn\u0027t need to be just for bitops, but the ops do need to be fully associative.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375445 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "f5e25f84faff6c548ca1a767269cc0e32dc34095", "tree": "d78a6485fa6621ad42dd15da04761d0b4fb31992", "parents": [ "c0f32bd5527a61d4c6ef09b18015aab7e85f9649" ], "author": { "name": "Sander de Smalen", "email": "sander.desmalen@arm.com", "time": "Mon Oct 21 19:11:40 2019" }, "committer": { "name": "Sander de Smalen", "email": "sander.desmalen@arm.com", "time": "Mon Oct 21 19:11:40 2019" }, "message": "Reverted r375425 as it broke some buildbots.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375444 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "c0f32bd5527a61d4c6ef09b18015aab7e85f9649", "tree": "7e259d5a9a599f56aa2d0218689f38ecbcb98b17", "parents": [ "b172b0f36f0158f1ee4adc6003c28b6fa8b1e4a7" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 18:35:26 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 18:35:26 2019" }, "message": "[NFC][CVP] Add `shl` no-wrap deduction test coverage\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375441 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b172b0f36f0158f1ee4adc6003c28b6fa8b1e4a7", "tree": "5a8d32bbb739e65f094cc20bd691431e17fe9173", "parents": [ "aa0a5ffb56c3d082c6e866637b97e0134213425d" ], "author": { "name": "Bjorn Pettersson", "email": "bjorn.a.pettersson@ericsson.com", "time": "Mon Oct 21 17:51:54 2019" }, "committer": { "name": "Bjorn Pettersson", "email": "bjorn.a.pettersson@ericsson.com", "time": "Mon Oct 21 17:51:54 2019" }, "message": "Prune Pass.h include from DataLayout.h. NFCI\n\nSummary:\nReduce include dependencies by no longer including Pass.h from\nDataLayout.h. That include seemed irrelevant to DataLayout, as\nwell as being irrelevant to several users of DataLayout.\n\nReviewers: rnk\n\nReviewed By: rnk\n\nSubscribers: mehdi_amini, hiraditya, cfe-commits, llvm-commits\n\nTags: #clang, #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69261\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375436 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "aa0a5ffb56c3d082c6e866637b97e0134213425d", "tree": "5f854353f14bb275e5ede9eb7801d351a5076c3e", "parents": [ "a3e4f5daf681d72384ef5d4121357f36a94d7a6a" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:45:51 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:45:51 2019" }, "message": "[PowerPC] Regenerate test for D52431\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375435 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "a3e4f5daf681d72384ef5d4121357f36a94d7a6a", "tree": "3ae9a6d38bfcaf9a9e934aed917793cc0cde582b", "parents": [ "25c29219cb2aaa60d1c80c7ce225f0b24ccaea36" ], "author": { "name": "Raphael Isemann", "email": "teemperor@gmail.com", "time": "Mon Oct 21 17:43:38 2019" }, "committer": { "name": "Raphael Isemann", "email": "teemperor@gmail.com", "time": "Mon Oct 21 17:43:38 2019" }, "message": "[NFC] Add missing include to fix modules build\n\nThis header doesn\u0027t seem to be parsable on its own and breaks the module build therefore with\nthe following error:\n\nWhile building module \u0027LLVM_Backend\u0027 imported from llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:14:\nIn file included from \u003cmodule-includes\u003e:62:\nllvm-project/llvm/include/llvm/CodeGen/MachinePipeliner.h:91:20: error: declaration of \u0027AAResultsWrapperPass\u0027 must be imported from module \u0027LLVM_Analysis.AliasAnalysis\u0027 before it is required\n AU.addRequired\u003cAAResultsWrapperPass\u003e();\n ^\nllvm-project/llvm/include/llvm/Analysis/AliasAnalysis.h:1157:7: note: previous declaration is here\nclass AAResultsWrapperPass : public FunctionPass {\n ^\nllvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:14:10: fatal error: could not build module \u0027LLVM_Backend\u0027\n ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n2 errors generated.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375433 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "25c29219cb2aaa60d1c80c7ce225f0b24ccaea36", "tree": "e8168a9bf4f0aa25e8dc63d7d216d9bc2451e105", "parents": [ "2ae2f592484cb2df6e7f9eaabc48daef75ddb380" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:16:03 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:16:03 2019" }, "message": "SystemZISelLowering - supportedAddressingMode - silence static analyzer dyn_cast\u003c\u003e null dereference warning. NFCI.\n\nThe static analyzer is warning about a potential null dereference, but we should be able to use cast\u003c\u003e directly and if not assert will fire for us.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375430 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "2ae2f592484cb2df6e7f9eaabc48daef75ddb380", "tree": "8a072da8263f2b9209125c96814d2ff3c6e885fe", "parents": [ "c4c5944aa91fa4bec6456398e9a0ee7ec2649fd4" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:49 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:49 2019" }, "message": "GVNHoist - silence static analyzer dyn_cast\u003c\u003e null dereference warning in hasEHOrLoadsOnPath call. NFCI.\n\nThe static analyzer is warning about a potential null dereference, but we should be able to use cast\u003c\u003e directly and if not assert will fire for us.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375429 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "c4c5944aa91fa4bec6456398e9a0ee7ec2649fd4", "tree": "9b5e62bbde64d8ce48061c936dc8408ac4fccbea", "parents": [ "b0db20ce62f8ecfe79fcb328008aed4473e2d793" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:37 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:37 2019" }, "message": "GuardWidening - silence static analyzer null dereference warning with assertion. NFCI.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375428 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b0db20ce62f8ecfe79fcb328008aed4473e2d793", "tree": "4a687cced263345bb925cc1ac160ef4bf89907e0", "parents": [ "72157fef87a5bb4aa1578cf75877ec6020a3b44f" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:25 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:25 2019" }, "message": "CrossDSOCFI - silence static analyzer dyn_cast\u003c\u003e null dereference warning. NFCI.\n\nThe static analyzer is warning about a potential null dereference, but we should be able to use cast\u003c\u003e directly and if not assert will fire for us.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375427 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "72157fef87a5bb4aa1578cf75877ec6020a3b44f", "tree": "e96c0d5c270f674c2421fb202e484983b91b75b1", "parents": [ "4548d296c18172691dc3f00fb6fb14fddbcd01f4" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:05 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Mon Oct 21 17:15:05 2019" }, "message": "IndVarSimplify - silence static analyzer dyn_cast\u003c\u003e null dereference warning. NFCI.\n\nThe static analyzer is warning about a potential null dereference, but we should be able to use cast\u003c\u003e directly and if not assert will fire for us.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375426 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "4548d296c18172691dc3f00fb6fb14fddbcd01f4", "tree": "153d4caa2136ab8ef2976b127134a136da3b8071", "parents": [ "c994a35a0db9118662b9670542c29dd0b43e5af8" ], "author": { "name": "Sander de Smalen", "email": "sander.desmalen@arm.com", "time": "Mon Oct 21 17:12:56 2019" }, "committer": { "name": "Sander de Smalen", "email": "sander.desmalen@arm.com", "time": "Mon Oct 21 17:12:56 2019" }, "message": "[AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2)\n\nCommit message from D66935:\n\nThis patch fixes a bug exposed by D65653 where a subsequent invocation\nof `determineCalleeSaves` ends up with a different size for the callee\nsave area, leading to different frame-offsets in debug information.\n\nIn the invocation by PEI, `determineCalleeSaves` tries to determine\nwhether it needs to spill an extra callee-saved register to get an\nemergency spill slot. To do this, it calls \u0027estimateStackSize\u0027 and\nmanually adds the size of the callee-saves to this. PEI then allocates\nthe spill objects for the callee saves and the remaining frame layout\nis calculated accordingly.\n\nA second invocation in LiveDebugValues causes estimateStackSize to return\nthe size of the stack frame including the callee-saves. Given that the\nsize of the callee-saves is added to this, these callee-saves are counted\ntwice, which leads `determineCalleeSaves` to believe the stack has\nbecome big enough to require spilling an extra callee-save as emergency\nspillslot. It then updates CalleeSavedStackSize with a larger value.\n\nSince CalleeSavedStackSize is used in the calculation of the frame\noffset in getFrameIndexReference, this leads to incorrect offsets for\nvariables/locals when this information is recalculated after PEI.\n\nThis patch fixes the lldb unit tests in `functionalities/thread/concurrent_events/*`\n\nChanges after D66935:\n\nEnsures AArch64FunctionInfo::getCalleeSavedStackSize does not return\nthe uninitialized CalleeSavedStackSize when running `llc` on a specific\npass where the MIR code has already been expected to have gone through PEI.\n\nInstead, getCalleeSavedStackSize (when passed the MachineFrameInfo) will try\nto recalculate the CalleeSavedStackSize from the CalleeSavedInfo. In debug\nmode, the compiler will assert the recalculated size equals the cached\nsize as calculated through a call to determineCalleeSaves.\n\nThis fixes two tests:\n test/DebugInfo/AArch64/asan-stack-vars.mir\n test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir\nthat otherwise fail when compiled using msan.\n\nReviewed By: omjavaid, efriedma\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D68783\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375425 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "c994a35a0db9118662b9670542c29dd0b43e5af8", "tree": "1dda658ecaa235aaeb89a07cb9bc8e8e915de5d6", "parents": [ "ff6e4d503c7bb8ce6557fa2ff7afa839db58a85b" ], "author": { "name": "Xiangling Liao", "email": "xiangxdh@gmail.com", "time": "Mon Oct 21 15:36:13 2019" }, "committer": { "name": "Xiangling Liao", "email": "xiangxdh@gmail.com", "time": "Mon Oct 21 15:36:13 2019" }, "message": "[NFC] Cleanup with variable name IsPPC64 \u0026 IsDarwin\n\nClean up PPCAsmPrinter with IsPPC64 and IsDarwin.\n\nDifferential Revision: https://reviews.llvm.org/D69259\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375420 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "ff6e4d503c7bb8ce6557fa2ff7afa839db58a85b", "tree": "36a0cb41cc73afb8025eb7760f09aadc9acbe3f5", "parents": [ "a3253c0261b44ba89ffa6e1adeaf227d085ec490" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 15:10:26 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 15:10:26 2019" }, "message": "[Alignment][NFC] Finish transition for `Loads`\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: hiraditya, asbirlea, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69253\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375419 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "a3253c0261b44ba89ffa6e1adeaf227d085ec490", "tree": "5a8c1ac4d9a184074b16255944375616034ac86b", "parents": [ "4bdbcfddafb2d3a3efabc626939c0f1c53038700" ], "author": { "name": "Jay Foad", "email": "jay.foad@gmail.com", "time": "Mon Oct 21 15:01:59 2019" }, "committer": { "name": "Jay Foad", "email": "jay.foad@gmail.com", "time": "Mon Oct 21 15:01:59 2019" }, "message": "Pre-commit test cases for D64713.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375418 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "4bdbcfddafb2d3a3efabc626939c0f1c53038700", "tree": "51f702b56332dd9423e30847de1a506bba0a5bd8", "parents": [ "9694ebf5f74421ebab8c9dc85affb1a470d589ec" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 14:51:49 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 14:51:49 2019" }, "message": "[Types] Define a getWithNewBitWidth for Types and make use of it\n\nThis is designed to change the bitwidth of a type without altering the number\nof vector lanes. Also useful in D68651. Otherwise an NFC.\n\nDifferential Revision: https://reviews.llvm.org/D69139\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375417 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "9694ebf5f74421ebab8c9dc85affb1a470d589ec", "tree": "89b522b9e41224db7c49b365a0d3bae653912442", "parents": [ "8c479efe736fe2731ba5f9c76c0d6ef72758fbad" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 14:49:28 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 14:49:28 2019" }, "message": "[Alignment][NFC] Instructions::getLoadStoreAlignment\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nSubscribers: hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69256\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375416 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "8c479efe736fe2731ba5f9c76c0d6ef72758fbad", "tree": "ca762cf9057e9f78faf1acd6ed6b0e80e3dccc31", "parents": [ "471eaccd514a164b7be7c73be3b3f44f7f77ac70" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 14:06:49 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 14:06:49 2019" }, "message": "[ARM] Extra qdadd patterns\n\nThis adds some new qdadd patterns to go along with the other recently added\nqadd\u0027s.\n\nDifferential Revision: https://reviews.llvm.org/D68999\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375414 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "471eaccd514a164b7be7c73be3b3f44f7f77ac70", "tree": "b298c10674f6c35a6d44ea9022d9b5559609fee9", "parents": [ "d00dbb86c0f3d60eb4db569f9b15c8b3bf48c3db" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 13:58:33 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 13:58:33 2019" }, "message": "[Alignment][NFC] Add a helper function to DataLayout\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69258\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375413 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d00dbb86c0f3d60eb4db569f9b15c8b3bf48c3db", "tree": "86d401c5474e1017685b0aa76088fa8526d3a44f", "parents": [ "68b7d2e0925f44adc9e23b32c7299520702dcbe9" ], "author": { "name": "Owen Reynolds", "email": "gbreynoo@gmail.com", "time": "Mon Oct 21 13:13:31 2019" }, "committer": { "name": "Owen Reynolds", "email": "gbreynoo@gmail.com", "time": "Mon Oct 21 13:13:31 2019" }, "message": "[docs][llvm-ar] Update llvm-ar command guide\n\nThe llvm-ar command guide had not been updated in some time, it was\nmissing current functionality and contained information that was out\nof date. This change:\n- Updates the use of reStructuredText directives, as seen in other tools\n command guides.\n- Updates the command synopsis.\n- Updates the descriptions of the tool behaviour.\n- Updates the options section.\n- Adds details of MRI script functionality.\n- Removes the sections \"Standards\" and \"File Format\"\n\nDifferential Revision: https://reviews.llvm.org/D68998\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375412 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "68b7d2e0925f44adc9e23b32c7299520702dcbe9", "tree": "d83d5e3cde734c7dd65c047aab2bd72a6a23e64b", "parents": [ "0e61c30e7d918be651096b9bf0d9c89ca31aa094" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 12:33:46 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 12:33:46 2019" }, "message": "[ARM] Add qadd lowering from a sadd_sat\n\nThis lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the\nsame time.\n\nThe qadd instruction sets the q flag, but we already have many cases where we\ndo not model this in llvm.\n\nDifferential Revision: https://reviews.llvm.org/D68976\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375411 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "0e61c30e7d918be651096b9bf0d9c89ca31aa094", "tree": "1b4020f2f5278b30eb295a40ad5382c10d732b94", "parents": [ "91d68c5d934da0b7af61542ad09a12f7a370770f" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 12:05:33 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 12:05:33 2019" }, "message": "[Alignment][NFC] TargetCallingConv::setByValAlign\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69248\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375410 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "91d68c5d934da0b7af61542ad09a12f7a370770f", "tree": "7c29f4703ffef8bb0b3937e526db826f50e8e7bb", "parents": [ "cc870b19ca17467315a5da769d680c24f3153bc8" ], "author": { "name": "Jay Foad", "email": "jay.foad@gmail.com", "time": "Mon Oct 21 11:32:41 2019" }, "committer": { "name": "Jay Foad", "email": "jay.foad@gmail.com", "time": "Mon Oct 21 11:32:41 2019" }, "message": "Simplify usage of setFPAttrs.\n\nIn some cases using the return value of setFPAttrs simplifies the code.\nIn other cases it complicates the code with ugly casts, so stop doing\nit. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375409 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "cc870b19ca17467315a5da769d680c24f3153bc8", "tree": "4efb0124c2374a682c395e4c0183f4f2a8fa1dc3", "parents": [ "f69d71733b06ed87cfa874ac5f9613458ce8c0e0" ], "author": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 11:06:38 2019" }, "committer": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 11:06:38 2019" }, "message": "[llvm/Object] - Make ELFObjectFile::getRelocatedSection return Expected\u003csection_iterator\u003e\n\nIt returns just a section_iterator currently and have a report_fatal_error call inside.\nThis change adds a way to return errors and handle them on caller sides.\n\nThe patch also changes/improves current users and adds test cases.\n\nDifferential revision: https://reviews.llvm.org/D69167\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375408 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "f69d71733b06ed87cfa874ac5f9613458ce8c0e0", "tree": "fa919eb99cdb9429cb3225ddc3fb515927cd82e4", "parents": [ "db084dfbfd4f9f16b2802afb0f73b167982f2cc0" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 11:01:55 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 11:01:55 2019" }, "message": "[Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAlignmentForCallingConv\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: sdardis, hiraditya, jrtc27, atanasyan, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69243\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375407 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "db084dfbfd4f9f16b2802afb0f73b167982f2cc0", "tree": "3cf6a7c0dce558ae945d7f78bd65a42ac23ceb74", "parents": [ "685ae98920d70210aef0cb70edb49640dec48aac" ], "author": { "name": "David Carlier", "email": "devnexen@gmail.com", "time": "Mon Oct 21 10:44:20 2019" }, "committer": { "name": "David Carlier", "email": "devnexen@gmail.com", "time": "Mon Oct 21 10:44:20 2019" }, "message": "Fix llvm signal tests build.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375406 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "685ae98920d70210aef0cb70edb49640dec48aac", "tree": "a0075f377124316c270b4af39131644aec1df038", "parents": [ "63b9649758d269176eda84f153cec6738d2edc4a" ], "author": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 10:40:43 2019" }, "committer": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 10:40:43 2019" }, "message": "[obj2yaml] - Fix a comment. NFC.\n\nI forgot to address this nit before committing..\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375405 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "63b9649758d269176eda84f153cec6738d2edc4a", "tree": "bf9057e378216e7ef5eef75227a5c2f65e199c54", "parents": [ "7fc698b06acd483d3ad8ee5a64703fd67e021b1c" ], "author": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 10:38:03 2019" }, "committer": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Mon Oct 21 10:38:03 2019" }, "message": "[obj2yaml] - Stop triggering UB when dumping corrupted strings.\n\nWe have a following code to find quote type:\n\nif (isspace(S.front()) || isspace(S.back()))\n...\n\nProblem is that:\n\n\"int isspace( int ch ): The behavior is undefined if the value of\nch is not representable as unsigned char and is not equal to EOF.\"\n(https://en.cppreference.com/w/cpp/string/byte/isspace)\n\nThis patch shows how this UB can be triggered and fixes an issue.\n\nDifferential revision: https://reviews.llvm.org/D69160\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375404 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "7fc698b06acd483d3ad8ee5a64703fd67e021b1c", "tree": "79184fb0fd46dce69f4589e912a85e978a89c8b5", "parents": [ "32893f05023880a92132df22fff315abeb241638" ], "author": { "name": "Sam Elliott", "email": "selliott@lowrisc.org", "time": "Mon Oct 21 10:00:34 2019" }, "committer": { "name": "Sam Elliott", "email": "selliott@lowrisc.org", "time": "Mon Oct 21 10:00:34 2019" }, "message": "[MemCpyOpt] Fixing Incorrect Code Motion while Handling Aggregate Type Values\n\nSummary:\nWhen MemCpyOpt is handling aggregate type values, if an instruction (let\u0027s call it P) between the targeting load (L) and store (S) clobbers the source pointer of L, it will try to hoist S before P. This process will also hoist S\u0027s data dependency instructions.\n\nHowever, the current implementation has a bug that if one of S\u0027s dependency instructions is //also// a user of P, MemCpyOpt will not prevent it from being hoisted above P and cause a use-before-define error. For example, in the newly added test file (i.e. `aggregate-type-crash.ll`), it will try to hoist both `store %my_struct %1, %my_struct* %3` and its dependent, `%3 \u003d bitcast i8* %2 to %my_struct*`, above `%2 \u003d call i8* @my_malloc(%my_struct* %0)`. Creating the following BB:\n```\nentry:\n %1 \u003d bitcast i8* %4 to %my_struct*\n %2 \u003d bitcast %my_struct* %1 to i8*\n %3 \u003d bitcast %my_struct* %0 to i8*\n call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %2, i8* align 4 %3, i64 8, i1 false)\n %4 \u003d call i8* @my_malloc(%my_struct* %0)\n ret void\n```\nWhere there is a use-before-define error between `%1` and `%4`.\n\nUpdate: The compiler for the Pony Programming Language [also encounter the same bug](https://github.com/ponylang/ponyc/issues/3140)\n\nPatch by Min-Yih Hsu (myhsu)\n\nReviewers: eugenis, pcc, dblaikie, dneilson, t.p.northover, lattner\n\nReviewed By: eugenis\n\nSubscribers: lenary, hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D66060\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375403 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "32893f05023880a92132df22fff315abeb241638", "tree": "9697c179b4c9416968fde2012e1713d3ecdb9f49", "parents": [ "7f7fc30dedbd7c9396c434e1bd5692d5acd19974" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 09:53:38 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 09:53:38 2019" }, "message": "[ARM] Lower sadd_sat to qadd8 and qadd16\n\nLower the target independent signed saturating intrinsics to qadd8 and qadd16.\nThis custom lowers them from a sadd_sat, catching the node early before it is\npromoted. It also adds a QADD8b and QADD16b node to mean the bottom \"lane\" of a\nqadd8/qadd16, so that we can call demand bits on it to show that it does not\nuse the upper bits.\n\nAlso handles QSUB8 and QSUB16.\n\nDifferential Revision: https://reviews.llvm.org/D68974\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375402 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "7f7fc30dedbd7c9396c434e1bd5692d5acd19974", "tree": "523ddb33949caeb28b3d4fe15b3db3c0ce7e1d27", "parents": [ "2bcdb486ddd1669fb4e473d592801ee8e6de5d9d" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 09:43:37 2019" }, "committer": { "name": "David Green", "email": "david.green@arm.com", "time": "Mon Oct 21 09:43:37 2019" }, "message": "[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375401 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "2bcdb486ddd1669fb4e473d592801ee8e6de5d9d", "tree": "3faadb6d34aa874b8cb7e44471668881812725d2", "parents": [ "475d7dd7ac626ba67768b03681a43568508aa91e" ], "author": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 08:31:25 2019" }, "committer": { "name": "Guillaume Chatelet", "email": "gchatelet@google.com", "time": "Mon Oct 21 08:31:25 2019" }, "message": "Use Align for TFL::TransientStackAlignment\n\nSummary:\nThis is patch is part of a series to introduce an Alignment type.\nSee this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html\nSee this patch for the introduction of the type: https://reviews.llvm.org/D64790\n\nReviewers: courbet\n\nSubscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69216\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375398 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "475d7dd7ac626ba67768b03681a43568508aa91e", "tree": "329c57c6cfe91c94f23660c1134ca32255cbdce7", "parents": [ "3ddad0b0b188880d74774950b08bf0320868ff38" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 08:21:54 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 08:21:54 2019" }, "message": "[NFC][InstCombine] Fixup comments\n\nAs noted in post-commit review of rL375378375378.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375397 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "3ddad0b0b188880d74774950b08bf0320868ff38", "tree": "91467721a03851ecc3bfb87f5715acd6932cb0e4", "parents": [ "ec10cb25d93412b1ca0da354f9b52fe4fdfccc87" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 08:21:44 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Mon Oct 21 08:21:44 2019" }, "message": "[CVP] Deduce no-wrap on `mul`\n\nSummary:\n`ConstantRange::makeGuaranteedNoWrapRegion()` knows how to deal with `mul`\nsince rL335646, there is exhaustive test coverage.\nThis is already used by CVP\u0027s `processOverflowIntrinsic()`,\nand by SCEV\u0027s `StrengthenNoWrapFlags()`\n\nThat being said, currently, this doesn\u0027t help much in the end:\n| statistic | old | new | delta | percentage |\n| correlated-value-propagation.NumMulNSW | 4 | 275 | 271 | 6775.00% |\n| correlated-value-propagation.NumMulNUW | 4 | 1323 | 1319 | 32975.00% |\n| correlated-value-propagation.NumMulNW | 8 | 1598 | 1590 | 19875.00% |\n| correlated-value-propagation.NumNSW | 5715 | 5986 | 271 | 4.74% |\n| correlated-value-propagation.NumNUW | 9193 | 10512 | 1319 | 14.35% |\n| correlated-value-propagation.NumNW | 14908 | 16498 | 1590 | 10.67% |\n| instcount.NumAddInst | 275871 | 275869 | -2 | 0.00% |\n| instcount.NumBrInst | 708234 | 708232 | -2 | 0.00% |\n| instcount.NumMulInst | 43812 | 43810 | -2 | 0.00% |\n| instcount.NumPHIInst | 316786 | 316784 | -2 | 0.00% |\n| instcount.NumTruncInst | 62165 | 62167 | 2 | 0.00% |\n| instcount.NumUDivInst | 2528 | 2526 | -2 | -0.08% |\n| instcount.TotalBlocks | 842995 | 842993 | -2 | 0.00% |\n| instcount.TotalInsts | 7376486 | 7376478 | -8 | 0.00% |\n(^ test-suite plain, tests still pass)\n\nReviewers: nikic, reames, luqmana, sanjoy, timshen\n\nReviewed By: reames\n\nSubscribers: hiraditya, javed.absar, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69203\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375396 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "ec10cb25d93412b1ca0da354f9b52fe4fdfccc87", "tree": "8589a5cd5634feb9056146785950c27ddbea1afc", "parents": [ "919bed3ee7cfb3d62eb89c6c9205dece376024d6" ], "author": { "name": "Piotr Sobczak", "email": "piotr.sobczak@amd.com", "time": "Mon Oct 21 08:12:47 2019" }, "committer": { "name": "Piotr Sobczak", "email": "piotr.sobczak@amd.com", "time": "Mon Oct 21 08:12:47 2019" }, "message": "[InstCombine] Allow values with multiple users in SimplifyDemandedVectorElts\n\nSummary:\nAllow for ignoring the check for a single use in SimplifyDemandedVectorElts\nto be able to simplify operands if DemandedElts is known to contain\nthe union of elements used by all users.\nIt is a responsibility of a caller of SimplifyDemandedVectorElts to\nsupply correct DemandedElts.\n\nSimplify a series of extractelement instructions if only a subset of\nelements is used.\n\nReviewers: reames, arsenm, majnemer, nhaehnle\n\nReviewed By: nhaehnle\n\nSubscribers: wdng, jvesely, nhaehnle, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D67345\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375395 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "919bed3ee7cfb3d62eb89c6c9205dece376024d6", "tree": "e69852f50666b2660bbb56c7995ffaf7dc48c803", "parents": [ "9cc8630a8051ee9e5edcae57237065b2f2e561a1" ], "author": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Mon Oct 21 08:06:38 2019" }, "committer": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Mon Oct 21 08:06:38 2019" }, "message": "gn build: Merge r375390\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375393 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "9cc8630a8051ee9e5edcae57237065b2f2e561a1", "tree": "2318748418a153355379c3e8189545ea573785f0", "parents": [ "53fb41197cba7b7aa935ee34ab7c1a1637d0abf1" ], "author": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Mon Oct 21 08:02:34 2019" }, "committer": { "name": "Martin Storsjo", "email": "martin@martin.st", "time": "Mon Oct 21 08:02:34 2019" }, "message": "[LLDB] [Windows] Initial support for ARM register contexts\n\nDifferential Revision: https://reviews.llvm.org/D69226\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375392 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "53fb41197cba7b7aa935ee34ab7c1a1637d0abf1", "tree": "14fdbaf155cfff8a1e4c4d8a61f1e809e5011da2", "parents": [ "adc79ba5dbc5860b7c848229a7485f0ab477896a" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.rouban@azul.com", "time": "Mon Oct 21 06:52:08 2019" }, "committer": { "name": "Yevgeny Rouban", "email": "yevgeny.rouban@azul.com", "time": "Mon Oct 21 06:52:08 2019" }, "message": "[IR] Fix mayReadFromMemory() for writeonly calls\n\nCurrent implementation of Instruction::mayReadFromMemory()\nreturns !doesNotAccessMemory() which is !ReadNone. This\ndoes not take into account that the writeonly attribute\nalso indicates that the call does not read from memory.\n\nThe patch changes the predicate to !doesNotReadMemory()\nthat reflects the intended behavior.\n\nDifferential Revision: https://reviews.llvm.org/D69086\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375389 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "adc79ba5dbc5860b7c848229a7485f0ab477896a", "tree": "5c4fe8486f41b4a33fb9d966b1613c7982008493", "parents": [ "cd2c0994762c867b7060512f640b4ee71ce57362" ], "author": { "name": "Yonghong Song", "email": "yhs@fb.com", "time": "Mon Oct 21 03:22:03 2019" }, "committer": { "name": "Yonghong Song", "email": "yhs@fb.com", "time": "Mon Oct 21 03:22:03 2019" }, "message": "[BPF] fix indirect call assembly code\n\nCurrently, for indirect call, the assembly code printed out as\n callx \u003cimm\u003e\nThis is not right, it should be\n callx \u003creg\u003e\n\nFixed the issue with proper format.\n\nDifferential Revision: https://reviews.llvm.org/D69229\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375386 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "cd2c0994762c867b7060512f640b4ee71ce57362", "tree": "b32622cf5f15b090535288425f056f88c719a49e", "parents": [ "463d8212b2f35004301c8f5b56788907aa011f0a" ], "author": { "name": "Johannes Doerfert", "email": "jdoerfert@anl.gov", "time": "Mon Oct 21 01:29:10 2019" }, "committer": { "name": "Johannes Doerfert", "email": "jdoerfert@anl.gov", "time": "Mon Oct 21 01:29:10 2019" }, "message": "[Attributor][FIX] Silence sign-compare warning\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375384 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "463d8212b2f35004301c8f5b56788907aa011f0a", "tree": "ace0bd6f2926ee3ce84738799f98673a79851d36", "parents": [ "f5c1edb2b95a6d03e0b93a3d2ed14033b638da38" ], "author": { "name": "Johannes Doerfert", "email": "jdoerfert@anl.gov", "time": "Mon Oct 21 00:48:42 2019" }, "committer": { "name": "Johannes Doerfert", "email": "jdoerfert@anl.gov", "time": "Mon Oct 21 00:48:42 2019" }, "message": "[Attributor] Teach AANoCapture to use information in-flight more aggressively\n\nAAReturnedValues, AAMemoryBehavior, and AANoUnwind, can provide\ninformation that helps during the tracking or even justifies no-capture.\nWe now use this information and enable no-capture in some test cases\ndesigned a long while a ago for these cases.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375382 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "f5c1edb2b95a6d03e0b93a3d2ed14033b638da38", "tree": "e4a5fd1632fd9e7fbb472911f722b57fcdad17f1", "parents": [ "d1d5cb769843c1328f39f565288bf463af8a73d0" ], "author": { "name": "Craig Topper", "email": "craig.topper@intel.com", "time": "Sun Oct 20 23:54:19 2019" }, "committer": { "name": "Craig Topper", "email": "craig.topper@intel.com", "time": "Sun Oct 20 23:54:19 2019" }, "message": "[X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and emitting X86ISD::FHADD in LowerUINT_TO_FP_i64.\n\nThis was a regression from r375341.\n\nFixes PR43729.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375381 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d1d5cb769843c1328f39f565288bf463af8a73d0", "tree": "55ec985e4fa067689a7adfc21d189487b9541823", "parents": [ "9efd72ad02a8f149d9786dafbb8f1d27f1e4bb1e" ], "author": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sun Oct 20 23:44:01 2019" }, "committer": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sun Oct 20 23:44:01 2019" }, "message": "[IndVars] Add a todo to reflect a further oppurtunity identified in D69009\n\nNikita pointed out an oppurtunity, might as well document it in the code.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375380 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "9efd72ad02a8f149d9786dafbb8f1d27f1e4bb1e", "tree": "233344fd2ee7c641151183498d5731c1c617a15d", "parents": [ "b93a52f5fec53c51628fa923f8a573f9f6ce2c98" ], "author": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sun Oct 20 23:38:02 2019" }, "committer": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sun Oct 20 23:38:02 2019" }, "message": "[IndVars] Eliminate loop exits with equivalent exit counts\n\nWe can end up with two loop exits whose exit counts are equivalent, but whose textual representation is different and non-obvious. For the sub-case where we have a series of exits which dominate one another (common), eliminate any exits which would iterate *after* a previous exit on the exiting iteration.\n\nAs noted in the TODO being removed, I\u0027d always thought this was a good idea, but I\u0027ve now seen this in a real workload as well.\n\nInterestingly, in review, Nikita pointed out there\u0027s let another oppurtunity to leverage SCEV\u0027s reasoning. If we kept track of the min of dominanting exits so far, we could discharge exits with EC \u003e\u003d MDE. This is less powerful than the existing transform (since later exits aren\u0027t considered), but potentially more powerful for any case where SCEV can prove a \u003e\u003d b, but neither a \u003d\u003d b or a \u003e b. I don\u0027t have an example to illustrate that oppurtunity, but won\u0027t be suprised if we find one and return to handle that case as well. \n\nDifferential Revision: https://reviews.llvm.org/D69009\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375379 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b93a52f5fec53c51628fa923f8a573f9f6ce2c98", "tree": "abb104ee4e7b8fd3f25181f164f62caf76912223", "parents": [ "150b0bedb7f0aa3af89dbd75a3f046b76260c191" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 20:52:06 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 20:52:06 2019" }, "message": "[InstCombine] conditional sign-extend of high-bit-extract: \u0027or\u0027 pattern.\n\nIn this pattern, all the \"magic\" bits that we\u0027d `add` are all\nhigh sign bits, and in the value we\u0027d be adding to they are all unset,\nnot unexpectedly, so we can have an `or` there:\nhttps://rise4fun.com/Alive/ups\n\nIt is possible that `haveNoCommonBitsSet()` should be taught about this\npattern so that we never have an `add` variant, but the reasoning would\nneed to be recursive (because of that `select`), so i\u0027m not really sure\nthat would be worth it just yet.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375378 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "150b0bedb7f0aa3af89dbd75a3f046b76260c191", "tree": "ac4bf80dd1215309a62eff909357959c1b63675f", "parents": [ "b7aa2ef391f765dccd54d5a28ec4762a03ce090c" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 20:51:37 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 20:51:37 2019" }, "message": "[NFC][InstCombine] conditional sign-extend of high-bit-extract: \u0027and\u0027 pat. can be \u0027or\u0027 pattern.\n\nIn this pattern, all the \"magic\" bits that we\u0027d add are all\nhigh sign bits, and in the value we\u0027d be adding to they are all unset,\nnot unexpectedly, so we can have an `or` there:\nhttps://rise4fun.com/Alive/ups\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375377 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b7aa2ef391f765dccd54d5a28ec4762a03ce090c", "tree": "55f4e97bcb992c52ee9cb7b2ad211d73659d4f08", "parents": [ "eec7ef7443ddbd32d9328160c31a628642198dc8" ], "author": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Sun Oct 20 20:44:56 2019" }, "committer": { "name": "GN Sync Bot", "email": "llvmgnsyncbot@gmail.com", "time": "Sun Oct 20 20:44:56 2019" }, "message": "gn build: Merge r375375\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375376 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "eec7ef7443ddbd32d9328160c31a628642198dc8", "tree": "c5c236d98e335279c7bedc70a74ab6973ab213f5", "parents": [ "e568120da32e6cddfb7c9bcc8eca172175fc6f51" ], "author": { "name": "Vladimir Vereschaka", "email": "vvereschaka@accesssoftek.com", "time": "Sun Oct 20 20:39:33 2019" }, "committer": { "name": "Vladimir Vereschaka", "email": "vvereschaka@accesssoftek.com", "time": "Sun Oct 20 20:39:33 2019" }, "message": "Reverted r375254 as it has broken some build bots for a long time.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375375 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "e568120da32e6cddfb7c9bcc8eca172175fc6f51", "tree": "62f4025df2866dcfe137a5ab45dfa4db401bb0e2", "parents": [ "2b0c82a99f57f3314f5a97692791a9e5767bdf72" ], "author": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 20:19:42 2019" }, "committer": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 20:19:42 2019" }, "message": "[InstCombine] Fold uadd.sat(a, b) \u003d\u003d 0 and usub.sat(a, b) \u003d\u003d 0\n\nThis adds folds for comparing uadd.sat/usub.sat with zero:\n\n * uadd.sat(a, b) \u003d\u003d 0 \u003d\u003e a \u003d\u003d 0 \u0026\u0026 b \u003d\u003d 0 \u003d\u003e (a | b) \u003d\u003d 0\n * usub.sat(a, b) \u003d\u003d 0 \u003d\u003e a \u003c\u003d b\n\nAnd inverted forms for !\u003d.\n\nDifferential Revision: https://reviews.llvm.org/D69224\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375374 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "2b0c82a99f57f3314f5a97692791a9e5767bdf72", "tree": "906d04e635a6afdba44ff3eb54c2c7a9f588a8af", "parents": [ "3ab0cb15c09776e346e9983492952d3aed6c4276" ], "author": { "name": "Zinovy Nis", "email": "zinovy.nis@gmail.com", "time": "Sun Oct 20 20:01:16 2019" }, "committer": { "name": "Zinovy Nis", "email": "zinovy.nis@gmail.com", "time": "Sun Oct 20 20:01:16 2019" }, "message": "Fix buildbot error in SIRegisterInfo.cpp.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375373 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "3ab0cb15c09776e346e9983492952d3aed6c4276", "tree": "ed1a7497cebf22451e8a6508a37d2e2576c4062f", "parents": [ "32d24a32499cde9bc29007725db22de076d5b0e0" ], "author": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 19:50:31 2019" }, "committer": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 19:50:31 2019" }, "message": "[InstCombine] Add tests for uadd/sub.sat(a, b) \u003d\u003d 0; NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375372 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "32d24a32499cde9bc29007725db22de076d5b0e0", "tree": "e976d3b28e4265306e534af305acacafb57885c4", "parents": [ "7bd6e166d9c76d62f76e801f9b55a84de03eb733" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 19:38:50 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 19:38:50 2019" }, "message": "[InstCombine] Shift amount reassociation in shifty sign bit test (PR43595)\n\nSummary:\nThis problem consists of several parts:\n* Basic sign bit extraction - `trunc? (?shr %x, (bitwidth(x)-1))`.\n This is trivial, and easy to do, we have a fold for it.\n* Shift amount reassociation - if we have two identical shifts,\n and we can simplify-add their shift amounts together,\n then we likely can just perform them as a single shift.\n But this is finicky, has one-use restrictions,\n and shift opcodes must be identical.\n\nBut there is a super-pattern where both of these work together.\nto produce sign bit test from two shifts + comparison.\nWe do indeed already handle this in most cases.\nBut since we get that fold transitively, it has one-use restrictions.\nAnd what\u0027s worse, in this case the right-shifts aren\u0027t required to be\nidentical, and we can\u0027t handle that transitively:\n\nIf the total shift amount is bitwidth-1, only a sign bit will remain\nin the output value. But if we look at this from the perspective of\ntwo shifts, we can\u0027t fold - we can\u0027t possibly know what bit pattern\nwe\u0027d produce via two shifts, it will be *some* kind of a mask\nproduced from original sign bit, but we just can\u0027t tell it\u0027s shape:\nhttps://rise4fun.com/Alive/cM0 https://rise4fun.com/Alive/9IN\n\nBut it will *only* contain sign bit and zeros.\nSo from the perspective of sign bit test, we\u0027re good:\nhttps://rise4fun.com/Alive/FRz https://rise4fun.com/Alive/qBU\nSuperb!\n\nSo the simplest solution is to extend `reassociateShiftAmtsOfTwoSameDirectionShifts()` to also have a\nsudo-analysis mode that will ignore extra-uses, and will only check\nwhether a) those are two right shifts and b) they end up with bitwidth(x)-1\nshift amount and return either the original value that we sign-checking,\nor null.\n\nThis does not have any functionality change for\nthe existing `reassociateShiftAmtsOfTwoSameDirectionShifts()`.\n\nAll that being said, as disscussed in the review, this yet again\nincreases usage of instsimplify in instcombine as utility.\nSome day that may need to be reevaluated.\n\nhttps://bugs.llvm.org/show_bug.cgi?id\u003d43595\n\nReviewers: spatel, efriedma, vsk\n\nReviewed By: spatel\n\nSubscribers: xbolva00, hiraditya, llvm-commits\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D68930\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375371 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "7bd6e166d9c76d62f76e801f9b55a84de03eb733", "tree": "fa8498ec24832b84d92bc1e1cf8561ad41496727", "parents": [ "467514942a5076757f238930fae0a7a6e9004af2" ], "author": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 19:36:55 2019" }, "committer": { "name": "Roman Lebedev", "email": "lebedev.ri@gmail.com", "time": "Sun Oct 20 19:36:55 2019" }, "message": "[ConstantRange] makeGuaranteedNoWrapRegion(): `shl` support\n\nSummary:\nIf all the shifts amount are already poison-producing,\nthen we can add more poison-producing flags ontop:\nhttps://rise4fun.com/Alive/Ocwi\n\nOtherwise, we should only consider the possible range of shift amts that don\u0027t result in poison.\n\nFor unsigned range not not overflow, we must not shift out any set bits,\nand the actual limit for `x` can be computed by backtransforming\nthe maximal value we could ever get out of the `shl` - `-1` through\n`lshr`. If the `x` is any larger than that then it will overflow.\n\nLikewise for signed range, but just in signed domain..\n\nThis is based on the general idea outlined by @nikic in https://reviews.llvm.org/D68672#1714990\n\nReviewers: nikic, sanjoy\n\nReviewed By: nikic\n\nSubscribers: hiraditya, llvm-commits, nikic\n\nTags: #llvm\n\nDifferential Revision: https://reviews.llvm.org/D69217\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375370 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "467514942a5076757f238930fae0a7a6e9004af2", "tree": "51d9e9446038bf867b57520344c55648203de830", "parents": [ "2df5f8ca5d5077143e731a6d62e4b9162435f199" ], "author": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 18:59:14 2019" }, "committer": { "name": "Nikita Popov", "email": "nikita.ppv@gmail.com", "time": "Sun Oct 20 18:59:14 2019" }, "message": "[ConstantRange] Optimize nowrap region test, remove redundant tests; NFC\n\nEnumerate one less constant range in TestNoWrapRegionExhaustive,\nwhich was unnecessary. This allows us to bump the bit count from\n3 to 5 while keeping reasonable timing.\n\nDrop four tests for multiply nowrap regions, as these cover subsets\nof the exhaustive test. They do use a wider bitwidth, but I don\u0027t\nthink it\u0027s worthwhile to have them additionally now.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375369 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "2df5f8ca5d5077143e731a6d62e4b9162435f199", "tree": "20fb48e29c805e0873e0359e0c9a299f018fdb3c", "parents": [ "f154896069faaf2b5f3c54df345de31041657848" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 17:44:17 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 17:44:17 2019" }, "message": "AMDGPU: Increase vcc liveness scan threshold\n\nAvoids a test regression in a future patch. Also add debug printing on\nthis case, so I waste less time debugging folds in the future.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375367 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "f154896069faaf2b5f3c54df345de31041657848", "tree": "409fb041a26c0f1fa3b70bf78292e764d0f1899d", "parents": [ "d8b4d6f7e1bf66ee263e9889a10afa3076c30c9d" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 17:34:44 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 17:34:44 2019" }, "message": "AMDGPU: Split flat offsets that don\u0027t fit in DAG\n\nWe handle it this way for some other address spaces.\n\nSince r349196, SILoadStoreOptimizer has been trying to do this. This\nis after SIFoldOperands runs, which can change the addressing\npatterns. It\u0027s simpler to just split this earlier.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375366 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "d8b4d6f7e1bf66ee263e9889a10afa3076c30c9d", "tree": "0e8a306c9b8e553a7c7a82f4bc1168b322c64ad6", "parents": [ "2f75f816882d3d4890ebe05d801e0a74a2008780" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:56:10 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:56:10 2019" }, "message": "AMDGPU: Fix missing OPERAND_IMMEDIATE\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375365 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "2f75f816882d3d4890ebe05d801e0a74a2008780", "tree": "77db4b6b96c42862dfcb3afe3f865cd17f9646a0", "parents": [ "01d98c6ec5a3e768c614d83c9fbc29a45cb45600" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:33:21 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:33:21 2019" }, "message": "AMDGPU: Add baseline tests for flat offset splitting\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375364 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "01d98c6ec5a3e768c614d83c9fbc29a45cb45600", "tree": "1d572a2f87dda0c52934769bedb7f9a2d2aae5c5", "parents": [ "38d435315618d1aa63cc49a44db5ac343ed3b0bb" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:26:26 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 16:26:26 2019" }, "message": "AMDGPU: Don\u0027t re-get the subtarget\n\nIt\u0027s already available in the class.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375363 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "38d435315618d1aa63cc49a44db5ac343ed3b0bb", "tree": "9964f2ff043b7290b3725df00c5555804fc9cf8a", "parents": [ "9873f72649f604b86dcc219f1dbec65176b5cc6b" ], "author": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Sun Oct 20 14:47:17 2019" }, "committer": { "name": "George Rimar", "email": "grimar@accesssoftek.com", "time": "Sun Oct 20 14:47:17 2019" }, "message": "[yaml2obj][obj2yaml] - Do not create a symbol table by default.\n\nThis patch tries to resolve problems faced in D68943\nand uses some of the code written by Konrad Wilhelm Kleine\nin that patch.\n\nPreviously, yaml2obj tool always created a .symtab section.\nThis patch changes that. With it we only create it when\nhave a \"Symbols:\" tag in the YAML document or when\nwe need to create it because it is used by another section(s).\n\nobj2yaml follows the new behavior and does not print \"Symbols:\"\nanymore when there is no symbol table.\n\nDifferential revision: https://reviews.llvm.org/D69041\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375361 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "9873f72649f604b86dcc219f1dbec65176b5cc6b", "tree": "7b28e80901b4f8895042feea3f89038240bedf3d", "parents": [ "b0113baebf46e178c694624e469ae3fea6ad562f" ], "author": { "name": "Zinovy Nis", "email": "zinovy.nis@gmail.com", "time": "Sun Oct 20 07:55:50 2019" }, "committer": { "name": "Zinovy Nis", "email": "zinovy.nis@gmail.com", "time": "Sun Oct 20 07:55:50 2019" }, "message": "Fix minor warning in DWARFVerifier.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375357 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "b0113baebf46e178c694624e469ae3fea6ad562f", "tree": "8db5b00dd6e7169bb5b8f57e973da986a264be5b", "parents": [ "c6240320003b308f1ed304f5d656ede5a0748bd0" ], "author": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 07:46:04 2019" }, "committer": { "name": "Matt Arsenault", "email": "Matthew.Arsenault@amd.com", "time": "Sun Oct 20 07:46:04 2019" }, "message": "AMDGPU: Don\u0027t error on calls to null or undef\n\nCalls to constants should probably be generally handled.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375356 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "c6240320003b308f1ed304f5d656ede5a0748bd0", "tree": "166a77d72a6ea12790329df9125dbcd4c07f57fa", "parents": [ "f7d6a8bc694dc2b96d5b2625b40f32e7ed444b4f" ], "author": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sat Oct 19 17:23:02 2019" }, "committer": { "name": "Philip Reames", "email": "listmail@philipreames.com", "time": "Sat Oct 19 17:23:02 2019" }, "message": "[SCEV] Simplify umin/max of zext and sext of the same value\n\nThis is a common idiom which arises after induction variables are widened, and we have two or more exit conditions. Interestingly, we don\u0027t have instcombine or instsimplify support for this either.\n\nDifferential Revision: https://reviews.llvm.org/D69006\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375349 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "f7d6a8bc694dc2b96d5b2625b40f32e7ed444b4f", "tree": "22b3c65ff2681baead1549ded32593c72536466d", "parents": [ "0d04cbb5783c50f77f8d4c136f2dd529aa112ff9" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 16:58:24 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 16:58:24 2019" }, "message": "[X86] Pulled out helper to decode target shuffle element sentinel values to \u0027Zeroable\u0027 known undef/zero bits. NFCI.\n\nRenamed \u0027resolveTargetShuffleAndZeroables\u0027 to \u0027resolveTargetShuffleFromZeroables\u0027 to match.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375348 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "0d04cbb5783c50f77f8d4c136f2dd529aa112ff9", "tree": "c766b5eda681befa867e399008f3e627e65c50bb", "parents": [ "316641232816e55c56eed1ac49e7e8f214444382" ], "author": { "name": "Sanjay Patel", "email": "spatel@rotateright.com", "time": "Sat Oct 19 16:57:02 2019" }, "committer": { "name": "Sanjay Patel", "email": "spatel@rotateright.com", "time": "Sat Oct 19 16:57:02 2019" }, "message": "[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)\n\nProvides a TLI hook to allow targets to relax the emission of shifts, thus enabling\ncodegen improvements on targets with no multiple shift instructions and cheap selects\nor branches.\n\nContributes to a Fix for PR43559:\nhttps://bugs.llvm.org/show_bug.cgi?id\u003d43559\n\nPatch by: @joanlluch (Joan LLuch)\n\nDifferential Revision: https://reviews.llvm.org/D69116\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375347 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "316641232816e55c56eed1ac49e7e8f214444382", "tree": "dc4ed0fa8dfceb3200db1e60c3b2b2392e22195c", "parents": [ "896dde46eea0205a12164e7f7fdd34bfccb770a4" ], "author": { "name": "Nemanja Ivanovic", "email": "nemanja.i.ibm@gmail.com", "time": "Sat Oct 19 16:40:26 2019" }, "committer": { "name": "Nemanja Ivanovic", "email": "nemanja.i.ibm@gmail.com", "time": "Sat Oct 19 16:40:26 2019" }, "message": "[ARM] Add dependency on GlobalISel for unit tests to fix shared libs build\n\nThe unit test uses GlobalISel but the dependency is not listed in the\nCMakeLists.txt file which causes failures in shared libs build with GCC.\n\nThis just adds the dependency.\n\nDifferential revision: https://reviews.llvm.org/D69064\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375346 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "896dde46eea0205a12164e7f7fdd34bfccb770a4", "tree": "9fc08f70bfd889aa06c2530b0c671100589f37f7", "parents": [ "200d59f918b7df9672f4872a3e4be2eaf3433b65" ], "author": { "name": "Sanjay Patel", "email": "spatel@rotateright.com", "time": "Sat Oct 19 16:29:32 2019" }, "committer": { "name": "Sanjay Patel", "email": "spatel@rotateright.com", "time": "Sat Oct 19 16:29:32 2019" }, "message": "[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC\n\nPatch by: @joanlluch (Joan LLuch)\n\nDifferential Revision: https://reviews.llvm.org/D69099\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375345 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "200d59f918b7df9672f4872a3e4be2eaf3433b65", "tree": "3fe25baba73191fb04554c7cc4c06d425180d917", "parents": [ "39580be1ee0c1ca9d532985d8f0fa27afab6d453" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 13:18:02 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 13:18:02 2019" }, "message": "[X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack args\n\ntryToWidenViaDuplication lowers using the shuffle_v8i16(unpack_v16i8(shuffle_v8i16(x),shuffle_v8i16(x))) pattern, but the unpack only needs the even/odd 16i8 args if the original v16i8 shuffle mask references the even/odd elements - which isn\u0027t true for many extension style shuffles.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375342 91177308-0d34-0410-b5e6-96231b3b80d8\n" }, { "commit": "39580be1ee0c1ca9d532985d8f0fa27afab6d453", "tree": "649b603056df162121564feaaec580e615a2215c", "parents": [ "0b2777c548667bb5f1161343abb052753d707a0f" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 11:53:48 2019" }, "committer": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Sat Oct 19 11:53:48 2019" }, "message": "[X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops\n\nWe were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea.\n\nDifferential Revision: https://reviews.llvm.org/D69175\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375341 91177308-0d34-0410-b5e6-96231b3b80d8\n" } ], "next": "0b2777c548667bb5f1161343abb052753d707a0f" }