Merge tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu into staging
Third RISC-V PR for QEMU 8.0
* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM
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# gpg: Signature made Tue 07 Feb 2023 07:08:52 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu: (32 commits)
hw/riscv: virt: Simplify virt_{get,set}_aclint()
target/riscv: fix SBI getchar handler for KVM
target/riscv: fix ctzw behavior
target/riscv: fix for virtual instr exception
target/riscv: add a MAINTAINERS entry for XThead* extension support
RISC-V: Adding XTheadFmv ISA extension
RISC-V: Add initial support for T-Head C906
RISC-V: Set minimum priv version for Zfh to 1.11
RISC-V: Adding T-Head FMemIdx extension
RISC-V: Adding T-Head MemIdx extension
RISC-V: Adding T-Head MemPair extension
RISC-V: Adding T-Head multiply-accumulate instructions
RISC-V: Adding XTheadCondMov ISA extension
RISC-V: Adding XTheadBs ISA extension
RISC-V: Adding XTheadBb ISA extension
RISC-V: Adding XTheadBa ISA extension
RISC-V: Adding XTheadSync ISA extension
RISC-V: Adding XTheadCmo ISA extension
hw/riscv: change riscv_compute_fdt_addr() semantics
hw/riscv: split fdt address calculation from fdt load
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index fa10eca..96e25f6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -295,6 +295,14 @@
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RISC-V XThead* extensions
+M: Christoph Muellner <christoph.muellner@vrull.eu>
+M: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/insn_trans/trans_xthead.c.inc
+F: target/riscv/xthead*.decode
+
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
L: qemu-riscv@nongnu.org
diff --git a/disas/riscv.c b/disas/riscv.c
index d216b9c..ddda687 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1626,9 +1626,9 @@
{ "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -1647,7 +1647,7 @@
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2594276..c7e0e50 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -249,29 +249,64 @@
}
}
-uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+/*
+ * This function makes an assumption that the DRAM interval
+ * 'dram_base' + 'dram_size' is contiguous.
+ *
+ * Considering that 'dram_end' is the lowest value between
+ * the end of the DRAM block and MachineState->ram_size, the
+ * FDT location will vary according to 'dram_base':
+ *
+ * - if 'dram_base' is less that 3072 MiB, the FDT will be
+ * put at the lowest value between 3072 MiB and 'dram_end';
+ *
+ * - if 'dram_base' is higher than 3072 MiB, the FDT will be
+ * put at 'dram_end'.
+ *
+ * The FDT is fdt_packed() during the calculation.
+ */
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
+ MachineState *ms)
{
- uint64_t temp, fdt_addr;
- hwaddr dram_end = dram_base + mem_size;
- int ret, fdtsize = fdt_totalsize(fdt);
+ int ret = fdt_pack(ms->fdt);
+ hwaddr dram_end, temp;
+ int fdtsize;
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+
+ fdtsize = fdt_totalsize(ms->fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
exit(1);
}
/*
+ * A dram_size == 0, usually from a MemMapEntry[].size element,
+ * means that the DRAM block goes all the way to ms->ram_size.
+ */
+ dram_end = dram_base;
+ dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size;
+
+ /*
* We should put fdt as far as possible to avoid kernel/initrd overwriting
* its content. But it should be addressable by 32 bit system as well.
* Thus, put it at an 2MB aligned address that less than fdt size from the
* end of dram or 3GB whichever is lesser.
*/
temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
- ret = fdt_pack(fdt);
- /* Should only fail if we've built a corrupted tree */
- g_assert(ret == 0);
+ return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+}
+
+/*
+ * 'fdt_addr' is received as hwaddr because boards might put
+ * the FDT beyond 32-bit addressing boundary.
+ */
+void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
+{
+ uint32_t fdtsize = fdt_totalsize(fdt);
+
/* copy in the device tree */
qemu_fdt_dumpdtb(fdt, fdtsize);
@@ -279,8 +314,6 @@
&address_space_memory);
qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
-
- return fdt_addr;
}
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
@@ -356,6 +389,15 @@
reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
}
+ if (!harts->harts[0].cfg.ext_icsr) {
+ /*
+ * The Zicsr extension has been disabled, so let's ensure we don't
+ * run the CSR instruction. Let's fill the address with a non
+ * compressed nop.
+ */
+ reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
+ }
+
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
reset_vec[i] = cpu_to_le32(reset_vec[i]);
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 82ae5e7..2b91e49 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -641,8 +641,11 @@
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
/* Load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 64d5d43..353f030 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -31,47 +31,47 @@
/*
* This version of the OpenTitan machine currently supports
* OpenTitan RTL version:
- * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
+ * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
*
* MMIO mapping as per (specified commit):
* lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
*/
static const MemMapEntry ibex_memmap[] = {
- [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
- [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
- [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
- [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
- [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
- [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
- [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
- [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
- [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
- [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
- [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
- [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
- [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
- [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
- [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
- [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
- [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
- [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
- [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
- [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
- [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
- [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
- [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
- [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
- [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
- [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
- [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 },
- [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
- [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
- [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
- [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
- [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
- [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
- [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
- [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
+ [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
+ [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
+ [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
+ [IBEX_DEV_UART] = { 0x40000000, 0x40 },
+ [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
+ [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
+ [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
+ [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
+ [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
+ [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
+ [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
+ [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
+ [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
+ [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
+ [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
+ [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
+ [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
+ [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
+ [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
+ [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
+ [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
+ [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
+ [IBEX_DEV_AES] = { 0x41100000, 0x100 },
+ [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
+ [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
+ [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
+ [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
+ [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
+ [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
+ [IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
+ [IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
+ [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
+ [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
+ [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
+ [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
static void opentitan_board_init(MachineState *machine)
@@ -294,12 +294,12 @@
memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
- create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
- memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
+ memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
- create_unimplemented_device("riscv.lowrisc.ibex.peri",
- memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
+ memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
}
static Property lowrisc_ibex_soc_props[] = {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2fb6ee2..d3ab7a9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -616,9 +616,11 @@
kernel_entry = 0;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index badc11e..cc3f6da 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -56,7 +56,7 @@
uint64_t addr, size;
unsigned long clint_addr;
int cpu, socket;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t *clint_cells;
uint32_t cpu_phandle, intc_phandle, phandle = 1;
char *name, *mem_name, *clint_name, *clust_name;
@@ -65,7 +65,7 @@
"sifive,clint0", "riscv,clint0"
};
- fdt = mc->fdt = create_device_tree(&fdt_size);
+ fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@@ -96,7 +96,7 @@
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
qemu_fdt_add_subnode(fdt, clust_name);
@@ -121,7 +121,7 @@
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, cpu_name, socket);
+ riscv_socket_fdt_write_id(ms, cpu_name, socket);
qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -147,14 +147,14 @@
g_free(cpu_name);
}
- addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
+ addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
+ size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
qemu_fdt_add_subnode(fdt, mem_name);
qemu_fdt_setprop_cells(fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, mem_name, socket);
+ riscv_socket_fdt_write_id(ms, mem_name, socket);
g_free(mem_name);
clint_addr = memmap[SPIKE_CLINT].base +
@@ -167,14 +167,14 @@
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, clint_name, socket);
+ riscv_socket_fdt_write_id(ms, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
g_free(clust_name);
}
- riscv_socket_fdt_write_distance_matrix(mc);
+ riscv_socket_fdt_write_distance_matrix(ms);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
@@ -324,9 +324,10 @@
kernel_entry = 0;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
+ memmap[SPIKE_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a11b4b..b81081c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -227,7 +227,7 @@
{
int cpu;
uint32_t cpu_phandle;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
char *name, *cpu_name, *core_name, *intc_name;
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
@@ -236,40 +236,40 @@
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
- qemu_fdt_add_subnode(mc->fdt, cpu_name);
+ qemu_fdt_add_subnode(ms->fdt, cpu_name);
if (riscv_feature(&s->soc[socket].harts[cpu].env,
RISCV_FEATURE_MMU)) {
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
} else {
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
"riscv,none");
}
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
- qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, cpu_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
+ riscv_socket_fdt_write_id(ms, cpu_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
intc_phandles[cpu] = (*phandle)++;
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
- qemu_fdt_add_subnode(mc->fdt, intc_name);
- qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
+ qemu_fdt_add_subnode(ms->fdt, intc_name);
+ qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
"riscv,cpu-intc");
- qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+ qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
- qemu_fdt_add_subnode(mc->fdt, core_name);
- qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
+ qemu_fdt_add_subnode(ms->fdt, core_name);
+ qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
g_free(core_name);
g_free(intc_name);
@@ -282,16 +282,16 @@
{
char *mem_name;
uint64_t addr, size;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
- addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
+ addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
+ size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
- qemu_fdt_add_subnode(mc->fdt, mem_name);
- qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, mem_name);
+ qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
- qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, mem_name, socket);
+ qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
+ riscv_socket_fdt_write_id(ms, mem_name, socket);
g_free(mem_name);
}
@@ -303,7 +303,7 @@
char *clint_name;
uint32_t *clint_cells;
unsigned long clint_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
@@ -319,15 +319,15 @@
clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
- qemu_fdt_add_subnode(mc->fdt, clint_name);
- qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, clint_name);
+ qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
(char **)&clint_compat,
ARRAY_SIZE(clint_compat));
- qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
- qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, clint_name, socket);
+ riscv_socket_fdt_write_id(ms, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
@@ -344,7 +344,7 @@
uint32_t *aclint_mswi_cells;
uint32_t *aclint_sswi_cells;
uint32_t *aclint_mtimer_cells;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
@@ -363,16 +363,16 @@
if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
name = g_strdup_printf("/soc/mswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, name, socket);
+ qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
}
@@ -386,33 +386,33 @@
size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
}
name = g_strdup_printf("/soc/mtimer@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mtimer");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
0x0, RISCV_ACLINT_DEFAULT_MTIME);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mtimer_cells, aclint_cells_size);
- riscv_socket_fdt_write_id(mc, name, socket);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
addr = memmap[VIRT_ACLINT_SSWI].base +
(memmap[VIRT_ACLINT_SSWI].size * socket);
name = g_strdup_printf("/soc/sswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-sswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_sswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, name, socket);
+ qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
}
@@ -430,7 +430,7 @@
char *plic_name;
uint32_t *plic_cells;
unsigned long plic_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
static const char * const plic_compat[2] = {
"sifive,plic-1.0.0", "riscv,plic0"
};
@@ -456,27 +456,27 @@
plic_phandles[socket] = (*phandle)++;
plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
- qemu_fdt_add_subnode(mc->fdt, plic_name);
- qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ qemu_fdt_add_subnode(ms->fdt, plic_name);
+ qemu_fdt_setprop_cell(ms->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ qemu_fdt_setprop_cell(ms->fdt, plic_name,
"#address-cells", FDT_PLIC_ADDR_CELLS);
- qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
+ qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
- qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+ qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
VIRT_IRQCHIP_NUM_SOURCES - 1);
- riscv_socket_fdt_write_id(mc, plic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+ riscv_socket_fdt_write_id(ms, plic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
plic_phandles[socket]);
if (!socket) {
- platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+ platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
@@ -504,22 +504,23 @@
{
int cpu, socket;
char *imsic_name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
+ int socket_count = riscv_socket_count(ms);
uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
*msi_m_phandle = (*phandle)++;
*msi_s_phandle = (*phandle)++;
- imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
- imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+ imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
+ imsic_regs = g_new0(uint32_t, socket_count * 4);
/* M-level IMSIC node */
- for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
}
imsic_max_hart_per_socket = 0;
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
imsic_addr = memmap[VIRT_IMSIC_M].base +
socket * VIRT_IMSIC_GROUP_MAX_SIZE;
imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
@@ -533,41 +534,41 @@
}
imsic_name = g_strdup_printf("/soc/imsics@%lx",
(unsigned long)memmap[VIRT_IMSIC_M].base);
- qemu_fdt_add_subnode(mc->fdt, imsic_name);
- qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, imsic_name);
+ qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
"riscv,imsics");
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
FDT_IMSIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
- imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
- qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
- riscv_socket_count(mc) * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
+ socket_count * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
- if (riscv_socket_count(mc) > 1) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ if (socket_count > 1) {
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
- imsic_num_bits(riscv_socket_count(mc)));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(socket_count));
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
IMSIC_MMIO_GROUP_MIN_SHIFT);
}
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
g_free(imsic_name);
/* S-level IMSIC node */
- for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
}
imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
imsic_max_hart_per_socket = 0;
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
imsic_addr = memmap[VIRT_IMSIC_S].base +
socket * VIRT_IMSIC_GROUP_MAX_SIZE;
imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
@@ -582,34 +583,34 @@
}
imsic_name = g_strdup_printf("/soc/imsics@%lx",
(unsigned long)memmap[VIRT_IMSIC_S].base);
- qemu_fdt_add_subnode(mc->fdt, imsic_name);
- qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, imsic_name);
+ qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
"riscv,imsics");
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
FDT_IMSIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
- imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
- qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
- riscv_socket_count(mc) * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
+ socket_count * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
if (imsic_guest_bits) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
imsic_guest_bits);
}
- if (riscv_socket_count(mc) > 1) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ if (socket_count > 1) {
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
- imsic_num_bits(riscv_socket_count(mc)));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(socket_count));
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
IMSIC_MMIO_GROUP_MIN_SHIFT);
}
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
g_free(imsic_name);
g_free(imsic_regs);
@@ -628,7 +629,7 @@
char *aplic_name;
uint32_t *aplic_cells;
unsigned long aplic_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t aplic_m_phandle, aplic_s_phandle;
aplic_m_phandle = (*phandle)++;
@@ -643,28 +644,28 @@
aplic_addr = memmap[VIRT_APLIC_M].base +
(memmap[VIRT_APLIC_M].size * socket);
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
- qemu_fdt_add_subnode(mc->fdt, aplic_name);
- qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
- qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ qemu_fdt_add_subnode(ms->fdt, aplic_name);
+ qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
} else {
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
msi_m_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
aplic_s_phandle);
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
- riscv_socket_fdt_write_id(mc, aplic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
+ riscv_socket_fdt_write_id(ms, aplic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
g_free(aplic_name);
/* S-level APLIC node */
@@ -675,27 +676,27 @@
aplic_addr = memmap[VIRT_APLIC_S].base +
(memmap[VIRT_APLIC_S].size * socket);
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
- qemu_fdt_add_subnode(mc->fdt, aplic_name);
- qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
- qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ qemu_fdt_add_subnode(ms->fdt, aplic_name);
+ qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
} else {
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
msi_s_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
- riscv_socket_fdt_write_id(mc, aplic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+ riscv_socket_fdt_write_id(ms, aplic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
if (!socket) {
- platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+ platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
@@ -710,13 +711,13 @@
static void create_fdt_pmu(RISCVVirtState *s)
{
char *pmu_name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
RISCVCPU hart = s->soc[0].harts[0];
pmu_name = g_strdup_printf("/soc/pmu");
- qemu_fdt_add_subnode(mc->fdt, pmu_name);
- qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
- riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
+ qemu_fdt_add_subnode(ms->fdt, pmu_name);
+ qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
+ riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
g_free(pmu_name);
}
@@ -730,25 +731,26 @@
{
char *clust_name;
int socket, phandle_pos;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
+ int socket_count = riscv_socket_count(ms);
- qemu_fdt_add_subnode(mc->fdt, "/cpus");
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
+ qemu_fdt_add_subnode(ms->fdt, "/cpus");
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
- qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
- intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+ intc_phandles = g_new0(uint32_t, ms->smp.cpus);
- phandle_pos = mc->smp.cpus;
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos = ms->smp.cpus;
+ for (socket = (socket_count - 1); socket >= 0; socket--) {
phandle_pos -= s->soc[socket].num_harts;
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
- qemu_fdt_add_subnode(mc->fdt, clust_name);
+ qemu_fdt_add_subnode(ms->fdt, clust_name);
create_fdt_socket_cpus(s, socket, clust_name, phandle,
&intc_phandles[phandle_pos]);
@@ -774,8 +776,8 @@
*msi_pcie_phandle = msi_s_phandle;
}
- phandle_pos = mc->smp.cpus;
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos = ms->smp.cpus;
+ for (socket = (socket_count - 1); socket >= 0; socket--) {
phandle_pos -= s->soc[socket].num_harts;
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@@ -790,7 +792,7 @@
g_free(intc_phandles);
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
if (socket == 0) {
*irq_mmio_phandle = xplic_phandles[socket];
*irq_virtio_phandle = xplic_phandles[socket];
@@ -805,7 +807,7 @@
}
}
- riscv_socket_fdt_write_distance_matrix(mc);
+ riscv_socket_fdt_write_distance_matrix(ms);
}
static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
@@ -813,23 +815,23 @@
{
int i;
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
for (i = 0; i < VIRTIO_COUNT; i++) {
name = g_strdup_printf("/soc/virtio_mmio@%lx",
(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
0x0, memmap[VIRT_VIRTIO].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_virtio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
VIRTIO_IRQ + i);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
VIRTIO_IRQ + i, 0x4);
}
g_free(name);
@@ -841,29 +843,29 @@
uint32_t msi_pcie_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/pci@%lx",
(long) memmap[VIRT_PCIE_ECAM].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
FDT_PCI_ADDR_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
FDT_PCI_INT_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"pci-host-ecam-generic");
- qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
- qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
- qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
+ qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
+ qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
- qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
- qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
- qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
+ qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
1, FDT_PCI_RANGE_IOPORT, 2, 0,
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
1, FDT_PCI_RANGE_MMIO,
@@ -873,7 +875,7 @@
2, virt_high_pcie_memmap.base,
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
- create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
+ create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
g_free(name);
}
@@ -882,39 +884,39 @@
{
char *name;
uint32_t test_phandle;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
test_phandle = (*phandle)++;
name = g_strdup_printf("/soc/test@%lx",
(long)memmap[VIRT_TEST].base);
- qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_add_subnode(ms->fdt, name);
{
static const char * const compat[3] = {
"sifive,test1", "sifive,test0", "syscon"
};
- qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
+ qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
(char **)&compat, ARRAY_SIZE(compat));
}
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
- test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
+ qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
+ test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
g_free(name);
name = g_strdup_printf("/reboot");
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
- qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
g_free(name);
name = g_strdup_printf("/poweroff");
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
- qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
g_free(name);
}
@@ -922,24 +924,24 @@
uint32_t irq_mmio_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_UART0].base,
0x0, memmap[VIRT_UART0].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
}
- qemu_fdt_add_subnode(mc->fdt, "/chosen");
- qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
+ qemu_fdt_add_subnode(ms->fdt, "/chosen");
+ qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
g_free(name);
}
@@ -947,20 +949,20 @@
uint32_t irq_mmio_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"google,goldfish-rtc");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
}
g_free(name);
}
@@ -968,68 +970,68 @@
static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
name = g_strdup_printf("/flash@%" PRIx64, flashbase);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
+ qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, flashbase, 2, flashsize,
2, flashbase + flashsize, 2, flashsize);
- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
+ qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
g_free(name);
}
static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
{
char *nodename;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
hwaddr base = memmap[VIRT_FW_CFG].base;
hwaddr size = memmap[VIRT_FW_CFG].size;
nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
- qemu_fdt_add_subnode(mc->fdt, nodename);
- qemu_fdt_setprop_string(mc->fdt, nodename,
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename,
"compatible", "qemu,fw-cfg-mmio");
- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2, base, 2, size);
- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
g_free(nodename);
}
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
{
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
uint8_t rng_seed[32];
- if (mc->dtb) {
- mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
- if (!mc->fdt) {
+ if (ms->dtb) {
+ ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+ if (!ms->fdt) {
error_report("load_device_tree() failed");
exit(1);
}
} else {
- mc->fdt = create_device_tree(&s->fdt_size);
- if (!mc->fdt) {
+ ms->fdt = create_device_tree(&s->fdt_size);
+ if (!ms->fdt) {
error_report("create_device_tree() failed");
exit(1);
}
}
- qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
- qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
- qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
+ qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
+ qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
- qemu_fdt_add_subnode(mc->fdt, "/soc");
- qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
- qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
+ qemu_fdt_add_subnode(ms->fdt, "/soc");
+ qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
&irq_pcie_phandle, &irq_virtio_phandle,
@@ -1051,7 +1053,8 @@
/* Pass seed to RNG */
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
- qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
+ rng_seed, sizeof(rng_seed));
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
@@ -1103,14 +1106,14 @@
return dev;
}
-static FWCfgState *create_fw_cfg(const MachineState *mc)
+static FWCfgState *create_fw_cfg(const MachineState *ms)
{
hwaddr base = virt_memmap[VIRT_FW_CFG].base;
FWCfgState *fw_cfg;
fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
&address_space_memory);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
return fw_cfg;
}
@@ -1300,9 +1303,11 @@
start_addr = virt_memmap[VIRT_FLASH].base;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
+ memmap[VIRT_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
@@ -1328,9 +1333,10 @@
char *soc_name;
DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
int i, base_hartid, hart_count;
+ int socket_count = riscv_socket_count(machine);
/* Check socket count limit */
- if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
+ if (VIRT_SOCKETS_MAX < socket_count) {
error_report("number of sockets/nodes should be less than %d",
VIRT_SOCKETS_MAX);
exit(1);
@@ -1338,7 +1344,7 @@
/* Initialize sockets */
mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
- for (i = 0; i < riscv_socket_count(machine); i++) {
+ for (i = 0; i < socket_count; i++) {
if (!riscv_socket_check_hartids(machine, i)) {
error_report("discontinuous hartids in socket%d", i);
exit(1);
@@ -1577,16 +1583,14 @@
static bool virt_get_aclint(Object *obj, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
return s->have_aclint;
}
static void virt_set_aclint(Object *obj, bool value, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
s->have_aclint = value;
}
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f94653a..511390f 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -47,7 +47,9 @@
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
-uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
+uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
+ MachineState *ms);
+void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
hwaddr rom_base, hwaddr rom_size,
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 7659d1b..c40b050 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -94,9 +94,9 @@
IBEX_DEV_EDNO,
IBEX_DEV_EDN1,
IBEX_DEV_ALERT_HANDLER,
- IBEX_DEV_NMI_GEN,
+ IBEX_DEV_SRAM_CTRL,
IBEX_DEV_OTBN,
- IBEX_DEV_PERI,
+ IBEX_DEV_IBEX_CFG,
};
enum {
@@ -108,11 +108,11 @@
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
- IBEX_TIMER_TIMEREXPIRED0_0 = 127,
- IBEX_SPI_HOST0_ERR_IRQ = 134,
- IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
- IBEX_SPI_HOST1_ERR_IRQ = 136,
- IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
+ IBEX_TIMER_TIMEREXPIRED0_0 = 124,
+ IBEX_SPI_HOST0_ERR_IRQ = 131,
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132,
+ IBEX_SPI_HOST1_ERR_IRQ = 133,
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134,
};
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 14a7027..0dd2f0c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -22,6 +22,7 @@
#include "qemu/ctype.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "cpu_vendorid.h"
#include "pmu.h"
#include "internals.h"
#include "time_helper.h"
@@ -77,7 +78,7 @@
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
- ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+ ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
@@ -109,6 +110,17 @@
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
+ ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
+ ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
+ ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+ ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
+ ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
+ ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
+ ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
+ ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
+ ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
+ ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
@@ -271,6 +283,35 @@
cpu->cfg.mmu = false;
}
+static void rv64_thead_c906_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_priv_version(env, PRIV_VERSION_1_11_0);
+
+ cpu->cfg.ext_g = true;
+ cpu->cfg.ext_c = true;
+ cpu->cfg.ext_u = true;
+ cpu->cfg.ext_s = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.ext_zfh = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.ext_xtheadba = true;
+ cpu->cfg.ext_xtheadbb = true;
+ cpu->cfg.ext_xtheadbs = true;
+ cpu->cfg.ext_xtheadcmo = true;
+ cpu->cfg.ext_xtheadcondmov = true;
+ cpu->cfg.ext_xtheadfmemidx = true;
+ cpu->cfg.ext_xtheadmac = true;
+ cpu->cfg.ext_xtheadmemidx = true;
+ cpu->cfg.ext_xtheadmempair = true;
+ cpu->cfg.ext_xtheadsync = true;
+
+ cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+}
+
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
@@ -1088,6 +1129,17 @@
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* Vendor-specific custom extensions */
+ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
+ DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
+ DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
+ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+ DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
+ DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
+ DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
+ DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
+ DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
+ DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
+ DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
/* These are experimental so mark with 'x-' */
@@ -1351,6 +1403,7 @@
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bcf0826..7128438 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -53,6 +53,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
@@ -473,6 +474,17 @@
uint64_t mimpid;
/* Vendor-specific custom extensions */
+ bool ext_xtheadba;
+ bool ext_xtheadbb;
+ bool ext_xtheadbs;
+ bool ext_xtheadcmo;
+ bool ext_xtheadcondmov;
+ bool ext_xtheadfmemidx;
+ bool ext_xtheadfmv;
+ bool ext_xtheadmac;
+ bool ext_xtheadmemidx;
+ bool ext_xtheadmempair;
+ bool ext_xtheadsync;
bool ext_XVentanaCondOps;
uint8_t pmu_num;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9a28816..ad8d826 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -621,8 +621,6 @@
vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
}
- /* No need to update mip for VSTIP */
- mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
vstip = env->vstime_irq ? MIP_VSTIP : 0;
QEMU_IOTHREAD_LOCK_GUARD();
@@ -1641,6 +1639,12 @@
case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
tval = env->bins;
break;
+ case RISCV_EXCP_BREAKPOINT:
+ if (cs->watchpoint_hit) {
+ tval = cs->watchpoint_hit->hitaddr;
+ cs->watchpoint_hit = NULL;
+ }
+ break;
default:
break;
}
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
new file mode 100644
index 0000000..a5aa249
--- /dev/null
+++ b/target/riscv/cpu_vendorid.h
@@ -0,0 +1,6 @@
+#ifndef TARGET_RISCV_CPU_VENDORID_H
+#define TARGET_RISCV_CPU_VENDORID_H
+
+#define THEAD_VENDOR_ID 0x5b7
+
+#endif /* TARGET_RISCV_CPU_VENDORID_H */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 62e6c4a..fa17d77 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3045,6 +3045,8 @@
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3054,6 +3056,12 @@
} else {
env->htimedelta = val;
}
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
@@ -3071,11 +3079,19 @@
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index bf4840a..b091293 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -761,7 +761,6 @@
if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) {
- cs->watchpoint_hit = NULL;
do_trigger_action(env, DBG_ACTION_BP);
}
} else {
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 58a30f0..0497370 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -109,6 +109,7 @@
DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
+DEF_HELPER_1(tlb_flush_all, void, env)
/* Native Debug */
DEF_HELPER_1(itrigger_match, void, env)
#endif
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 45db82c..5f194a4 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -20,8 +20,10 @@
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
- TCGv src1 = get_address(ctx, a->rs1, 0);
+ TCGv src1;
+ decode_save_opc(ctx);
+ src1 = get_address(ctx, a->rs1, 0);
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
@@ -43,6 +45,7 @@
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
+ decode_save_opc(ctx);
src1 = get_address(ctx, a->rs1, 0);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
@@ -81,9 +84,10 @@
MemOp mop)
{
TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_address(ctx, a->rs1, 0);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ decode_save_opc(ctx);
+ src1 = get_address(ctx, a->rs1, 0);
func(dest, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index e2b8329..990bc94 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -401,6 +401,7 @@
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
+ ctx->ol = MXL_RV32;
return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
}
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 1397c1c..6e3159b 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -38,6 +38,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ decode_save_opc(ctx);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
@@ -52,6 +53,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ decode_save_opc(ctx);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
return true;
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index a1d3eb5..965e1f8 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -38,6 +38,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
+ decode_save_opc(ctx);
addr = get_address(ctx, a->rs1, a->imm);
dest = cpu_fpr[a->rd];
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
@@ -54,6 +55,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
+ decode_save_opc(ctx);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
return true;
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 4f8aecd..9248b48 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -36,6 +36,7 @@
#ifdef CONFIG_USER_ONLY
return false;
#else
+ decode_save_opc(ctx);
if (check_access(ctx)) {
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -82,6 +83,7 @@
#ifdef CONFIG_USER_ONLY
return false;
#else
+ decode_save_opc(ctx);
if (check_access(ctx)) {
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
@@ -135,6 +137,7 @@
static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
void (*func)(TCGv, TCGv_env, TCGv))
{
+ decode_save_opc(ctx);
if (check_access(ctx)) {
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 5c69b88..4496f21 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -261,6 +261,7 @@
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
+ decode_save_opc(ctx);
if (get_xl(ctx) == MXL_RV128) {
return gen_load_i128(ctx, a, memop);
} else {
@@ -350,6 +351,7 @@
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
+ decode_save_opc(ctx);
if (get_xl(ctx) == MXL_RV128) {
return gen_store_i128(ctx, a, memop);
} else {
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 5d07150..2ad5716 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -49,6 +49,7 @@
REQUIRE_FPU;
REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
@@ -71,6 +72,7 @@
REQUIRE_FPU;
REQUIRE_ZFH_OR_ZFHMIN(ctx);
+ decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = tcg_temp_new();
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
index 2682bd9..f3cd7d5 100644
--- a/target/riscv/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -28,6 +28,7 @@
/* Do the same as sfence.vma currently */
REQUIRE_EXT(ctx, RVS);
#ifndef CONFIG_USER_ONLY
+ decode_save_opc(ctx);
gen_helper_tlb_flush(cpu_env);
return true;
#endif
@@ -56,6 +57,7 @@
/* Do the same as hfence.vvma currently */
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
+ decode_save_opc(ctx);
gen_helper_hyp_tlb_flush(cpu_env);
return true;
#endif
@@ -68,6 +70,7 @@
/* Do the same as hfence.gvma currently */
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
+ decode_save_opc(ctx);
gen_helper_hyp_gvma_tlb_flush(cpu_env);
return true;
#endif
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
new file mode 100644
index 0000000..be87c34
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -0,0 +1,1094 @@
+/*
+ * RISC-V translation routines for the T-Head vendor extensions (xthead*).
+ *
+ * Copyright (c) 2022 VRULL GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_XTHEADBA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadba) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADBB(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadbb) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADBS(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadbs) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADCMO(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadcmo) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADCONDMOV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadcondmov) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADFMEMIDX(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADFMV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadfmv) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADMAC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadmac) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADMEMIDX(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadmemidx) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADMEMPAIR(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadmempair) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_XTHEADSYNC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadsync) { \
+ return false; \
+ } \
+} while (0)
+
+/*
+ * Calculate and return the address for indexed mem operations:
+ * If !zext_offs, then the address is rs1 + (rs2 << imm2).
+ * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
+ int imm2, bool zext_offs)
+{
+ TCGv src2 = get_gpr(ctx, rs2, EXT_NONE);
+ TCGv offs = tcg_temp_new();
+
+ if (zext_offs) {
+ tcg_gen_extract_tl(offs, src2, 0, 32);
+ tcg_gen_shli_tl(offs, offs, imm2);
+ } else {
+ tcg_gen_shli_tl(offs, src2, imm2);
+ }
+
+ TCGv addr = get_address_indexed(ctx, rs1, offs);
+
+ tcg_temp_free(offs);
+ return addr;
+}
+
+/* XTheadBa */
+
+/*
+ * th.addsl is similar to sh[123]add (from Zba), but not an
+ * alternative encoding: while sh[123] applies the shift to rs1,
+ * th.addsl shifts rs2.
+ */
+
+#define GEN_TH_ADDSL(SHAMT) \
+static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ tcg_gen_shli_tl(t, arg2, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg1); \
+ tcg_temp_free(t); \
+}
+
+GEN_TH_ADDSL(1)
+GEN_TH_ADDSL(2)
+GEN_TH_ADDSL(3)
+
+#define GEN_TRANS_TH_ADDSL(SHAMT) \
+static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
+ arg_th_addsl##SHAMT * a) \
+{ \
+ REQUIRE_XTHEADBA(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
+}
+
+GEN_TRANS_TH_ADDSL(1)
+GEN_TRANS_TH_ADDSL(2)
+GEN_TRANS_TH_ADDSL(3)
+
+/* XTheadBb */
+
+/* th.srri is an alternate encoding for rori (from Zbb) */
+static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+ tcg_gen_rotri_tl, gen_roriw, NULL);
+}
+
+/* th.srriw is an alternate encoding for roriw (from Zbb) */
+static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ REQUIRE_64BIT(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
+}
+
+/* th.ext and th.extu perform signed/unsigned bitfield extraction */
+static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a,
+ void (*f)(TCGv, TCGv, unsigned int, unsigned int))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
+
+ if (a->lsb <= a->msb) {
+ f(dest, source, a->lsb, a->msb - a->lsb + 1);
+ gen_set_gpr(ctx, a->rd, dest);
+ }
+ return true;
+}
+
+static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl);
+}
+
+static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_th_bfextract(ctx, a, tcg_gen_extract_tl);
+}
+
+/* th.ff0: find first zero (clz on an inverted input) */
+static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ int olen = get_olen(ctx);
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_not_tl(t, src1);
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ gen_clzw(dest, t);
+ } else {
+ g_assert_not_reached();
+ }
+ } else {
+ gen_clz(dest, t);
+ }
+
+ tcg_temp_free(t);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_th_ff0(ctx, a, EXT_NONE);
+}
+
+/* th.ff1 is an alternate encoding for clz (from Zbb) */
+static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
+}
+
+static void gen_th_revw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS);
+}
+
+/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */
+static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+
+ return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw);
+}
+
+/* th.revw is a sign-extended byte-swap of the lower word */
+static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_th_revw);
+}
+
+/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */
+static void gen_th_tstnbz(TCGv ret, TCGv source1)
+{
+ gen_orc_b(ret, source1);
+ tcg_gen_not_tl(ret, ret);
+}
+
+static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a)
+{
+ REQUIRE_XTHEADBB(ctx);
+ return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz);
+}
+
+/* XTheadBs */
+
+/* th.tst is an alternate encoding for bexti (from Zbs) */
+static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
+{
+ REQUIRE_XTHEADBS(ctx);
+ return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
+}
+
+/* XTheadCmo */
+
+static inline int priv_level(DisasContext *ctx)
+{
+#ifdef CONFIG_USER_ONLY
+ return PRV_U;
+#else
+ /* Priv level is part of mem_idx. */
+ return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
+#endif
+}
+
+/* Test if priv level is M, S, or U (cannot fail). */
+#define REQUIRE_PRIV_MSU(ctx)
+
+/* Test if priv level is M or S. */
+#define REQUIRE_PRIV_MS(ctx) \
+do { \
+ int priv = priv_level(ctx); \
+ if (!(priv == PRV_M || \
+ priv == PRV_S)) { \
+ return false; \
+ } \
+} while (0)
+
+#define NOP_PRIVCHECK(insn, extcheck, privcheck) \
+static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \
+{ \
+ (void) a; \
+ extcheck(ctx); \
+ privcheck(ctx); \
+ return true; \
+}
+
+NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+
+NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+
+NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+
+/* XTheadCondMov */
+
+static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv old = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
+static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
+{
+ REQUIRE_XTHEADCONDMOV(ctx);
+ return gen_th_condmove(ctx, a, TCG_COND_EQ);
+}
+
+/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
+static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
+{
+ REQUIRE_XTHEADCONDMOV(ctx);
+ return gen_th_condmove(ctx, a, TCG_COND_NE);
+}
+
+/* XTheadFMem */
+
+/*
+ * Load 64-bit float from indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv_i64 rd = cpu_fpr[a->rd];
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+ tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
+ if ((memop & MO_SIZE) == MO_32) {
+ gen_nanbox_s(rd, rd);
+ }
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+/*
+ * Store 64-bit float to indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv_i64 rd = cpu_fpr[a->rd];
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+ tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
+
+ return true;
+}
+
+static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fload_idx(ctx, a, MO_TEUQ, false);
+}
+
+static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fload_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fload_idx(ctx, a, MO_TEUQ, true);
+}
+
+static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fload_idx(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fstore_idx(ctx, a, MO_TEUQ, false);
+}
+
+static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fstore_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fstore_idx(ctx, a, MO_TEUQ, true);
+}
+
+static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fstore_idx(ctx, a, MO_TEUL, true);
+}
+
+/* XTheadFmv */
+
+static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a)
+{
+ REQUIRE_XTHEADFMV(ctx);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, src1);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
+ tcg_temp_free_i64(t1);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a)
+{
+ REQUIRE_XTHEADFMV(ctx);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ TCGv dst;
+ TCGv_i64 t1;
+
+ dst = dest_gpr(ctx, a->rd);
+ t1 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
+ tcg_gen_trunc_i64_tl(dst, t1);
+ gen_set_gpr(ctx, a->rd, dst);
+ tcg_temp_free_i64(t1);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+/* XTheadMac */
+
+static bool gen_th_mac(DisasContext *ctx, arg_r *a,
+ void (*accumulate_func)(TCGv, TCGv, TCGv),
+ void (*extend_operand_func)(TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv tmp = tcg_temp_new();
+
+ if (extend_operand_func) {
+ TCGv tmp2 = tcg_temp_new();
+ extend_operand_func(tmp, src1);
+ extend_operand_func(tmp2, src2);
+ tcg_gen_mul_tl(tmp, tmp, tmp2);
+ tcg_temp_free(tmp2);
+ } else {
+ tcg_gen_mul_tl(tmp, src1, src2);
+ }
+
+ accumulate_func(dest, src0, tmp);
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(tmp);
+
+ return true;
+}
+
+/* th.mula: "rd = rd + rs1 * rs2" */
+static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
+}
+
+/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl);
+}
+
+/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */
+static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ REQUIRE_64BIT(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
+}
+
+/* th.muls: "rd = rd - rs1 * rs2" */
+static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
+}
+
+/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl);
+}
+
+/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */
+static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ REQUIRE_64BIT(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
+}
+
+/* XTheadMemIdx */
+
+/*
+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the load address is rs1.
+ * If preinc, then the load address is rs1 + (imm5) << imm2).
+ */
+static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
+ bool preinc)
+{
+ if (a->rs1 == a->rd) {
+ return false;
+ }
+
+ int imm = a->imm5 << a->imm2;
+ TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
+ TCGv rd = dest_gpr(ctx, a->rd);
+ TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
+ tcg_gen_addi_tl(rs1, rs1, imm);
+ gen_set_gpr(ctx, a->rd, rd);
+ gen_set_gpr(ctx, a->rs1, rs1);
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+/*
+ * Store with memop to indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the store address is rs1.
+ * If preinc, then the store address is rs1 + (imm5) << imm2).
+ */
+static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
+ bool preinc)
+{
+ int imm = a->imm5 << a->imm2;
+ TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
+ TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+ tcg_gen_addi_tl(rs1, rs1, imm);
+ gen_set_gpr(ctx, a->rs1, rs1);
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_inc(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_inc(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_inc(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_inc(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TEUW, false);
+}
+
+static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_TEUW, true);
+}
+
+static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_SB, true);
+}
+
+static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_UB, false);
+}
+
+static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_inc(ctx, a, MO_UB, true);
+}
+
+static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_store_inc(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_store_inc(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_inc(ctx, a, MO_SB, true);
+}
+
+/*
+ * Load with memop from indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv rd = dest_gpr(ctx, a->rd);
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+ tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd, rd);
+
+ return true;
+}
+
+/*
+ * Store with memop to indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+
+ return true;
+}
+
+static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_idx(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TEUW, false);
+}
+
+static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_UB, false);
+}
+
+static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_store_idx(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_SB, false);
+}
+static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_idx(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_load_idx(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_TEUW, true);
+}
+
+static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_SB, true);
+}
+
+static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_load_idx(ctx, a, MO_UB, true);
+}
+
+static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_store_idx(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADMEMIDX(ctx);
+ return gen_store_idx(ctx, a, MO_SB, true);
+}
+
+/* XTheadMemPair */
+
+static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+ int shamt)
+{
+ if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
+ return false;
+ }
+
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv addr1 = tcg_temp_new();
+ TCGv addr2 = tcg_temp_new();
+ int imm = a->sh2 << shamt;
+
+ addr1 = get_address(ctx, a->rs, imm);
+ addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
+
+ tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);
+ tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd1, t1);
+ gen_set_gpr(ctx, a->rd2, t2);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_temp_free(addr1);
+ tcg_temp_free(addr2);
+ return true;
+}
+
+static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TESQ, 4);
+}
+
+static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TESL, 3);
+}
+
+static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TEUL, 3);
+}
+
+static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+ int shamt)
+{
+ if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
+ return false;
+ }
+
+ TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
+ TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
+ TCGv addr1 = tcg_temp_new();
+ TCGv addr2 = tcg_temp_new();
+ int imm = a->sh2 << shamt;
+
+ addr1 = get_address(ctx, a->rs, imm);
+ addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
+
+ tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
+ tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);
+
+ tcg_temp_free(addr1);
+ tcg_temp_free(addr2);
+ return true;
+}
+
+static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_storepair_tl(ctx, a, MO_TESQ, 4);
+}
+
+static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_storepair_tl(ctx, a, MO_TESL, 3);
+}
+
+/* XTheadSync */
+
+static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
+{
+ (void) a;
+ REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+ REQUIRE_PRIV_MS(ctx);
+ gen_helper_tlb_flush_all(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+#ifndef CONFIG_USER_ONLY
+static void gen_th_sync_local(DisasContext *ctx)
+{
+ /*
+ * Emulate out-of-order barriers with pipeline flush
+ * by exiting the translation block.
+ */
+ gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+}
+#endif
+
+static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a)
+{
+ (void) a;
+ REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+ REQUIRE_PRIV_MSU(ctx);
+
+ /*
+ * th.sync is an out-of-order barrier.
+ */
+ gen_th_sync_local(ctx);
+
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a)
+{
+ (void) a;
+ REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+ REQUIRE_PRIV_MSU(ctx);
+
+ /*
+ * th.sync.i is th.sync plus pipeline flush.
+ */
+ gen_th_sync_local(ctx);
+
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a)
+{
+ /* This instruction has the same behaviour like th.sync.i. */
+ return trans_th_sync_i(ctx, a);
+}
+
+static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a)
+{
+ /* This instruction has the same behaviour like th.sync. */
+ return trans_th_sync(ctx, a);
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 30f2145..0f932a5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -467,10 +467,11 @@
case SBI_EXT_0_1_CONSOLE_GETCHAR:
ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
if (ret == sizeof(ch)) {
- run->riscv_sbi.args[0] = ch;
+ run->riscv_sbi.ret[0] = ch;
} else {
- run->riscv_sbi.args[0] = -1;
+ run->riscv_sbi.ret[0] = -1;
}
+ ret = 0;
break;
default:
qemu_log_mask(LOG_UNIMP,
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index ba25164..5dee37a 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -2,6 +2,7 @@
gen = [
decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
]
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 878bcb0..48f918b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -258,6 +258,12 @@
}
}
+void helper_tlb_flush_all(CPURISCVState *env)
+{
+ CPUState *cs = env_cpu(env);
+ tlb_flush_all_cpus_synced(cs);
+}
+
void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 8cce667..b654f91 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -27,7 +27,7 @@
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
- riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
@@ -57,16 +57,44 @@
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+ } else {
+ riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
}
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
return;
}
+ /* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
+ } else {
+ riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
}
- /* Clear the [V]STIP bit in mip */
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
+
+ /*
+ * Sstc specification says the following about timer interrupt:
+ * "A supervisor timer interrupt becomes pending - as reflected in
+ * the STIP bit in the mip and sip registers - whenever time contains
+ * a value greater than or equal to stimecmp, treating the values
+ * as unsigned integers. Writes to stimecmp are guaranteed to be
+ * reflected in STIP eventually, but not necessarily immediately.
+ * The interrupt remains posted until stimecmp becomes greater
+ * than time - typically as a result of writing stimecmp."
+ *
+ * When timecmp = UINT64_MAX, the time CSR will eventually reach
+ * timecmp value but on next timer tick the time CSR will wrap-around
+ * and become zero which is less than UINT64_MAX. Now, the timer
+ * interrupt behaves like a level triggered interrupt so it will
+ * become 1 when time = timecmp = UINT64_MAX and next timer tick
+ * it will become 0 again because time = 0 < timecmp = UINT64_MAX.
+ *
+ * Based on above, we don't re-start the QEMU timer when timecmp
+ * equals UINT64_MAX.
+ */
+ if (timecmp == UINT64_MAX) {
+ return;
+ }
/* otherwise, set up the future timer interrupt */
diff = timecmp - rtc_r;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 01cc30a..772f9d7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -130,6 +130,16 @@
return true;
}
+static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
+{
+ return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
+ ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
+ ctx->cfg_ptr->ext_xtheadcondmov ||
+ ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
+ ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
+ ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
+}
+
#define MATERIALISE_EXT_PREDICATE(ext) \
static bool has_ ## ext ## _p(DisasContext *ctx) \
{ \
@@ -589,6 +599,24 @@
return addr;
}
+/* Compute a canonical address from a register plus reg offset. */
+static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
+{
+ TCGv addr = temp_new(ctx);
+ TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+ tcg_gen_add_tl(addr, src1, offs);
+ if (ctx->pm_mask_enabled) {
+ tcg_gen_andc_tl(addr, addr, pm_mask);
+ } else if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32u_tl(addr, addr);
+ }
+ if (ctx->pm_base_enabled) {
+ tcg_gen_or_tl(addr, addr, pm_base);
+ }
+ return addr;
+}
+
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -1080,6 +1108,8 @@
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
+#include "decode-xthead.c.inc"
+#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
@@ -1106,6 +1136,7 @@
bool (*decode_func)(DisasContext *, uint32_t);
} decoders[] = {
{ always_true_p, decode_insn32 },
+ { has_xthead_p, decode_xthead },
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps },
};
@@ -1182,6 +1213,7 @@
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
+ ctx->virt_inst_excp = false;
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
new file mode 100644
index 0000000..d1d104b
--- /dev/null
+++ b/target/riscv/xthead.decode
@@ -0,0 +1,185 @@
+#
+# Translation routines for the instructions of the XThead* ISA extensions
+#
+# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
+# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# The documentation of the ISA extensions can be found here:
+# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
+
+# Fields:
+%rd 7:5
+%rd1 7:5
+%rs 15:5
+%rs1 15:5
+%rd2 20:5
+%rs2 20:5
+%sh5 20:5
+%imm5 20:s5
+%sh6 20:6
+%sh2 25:2
+%imm2 25:2
+
+# Argument sets
+&r rd rs1 rs2 !extern
+&r2 rd rs1 !extern
+&shift shamt rs1 rd !extern
+&th_bfext msb lsb rs1 rd
+&th_pair rd1 rs rd2 sh2
+&th_memidx rd rs1 rs2 imm2
+&th_meminc rd rs1 imm5 imm2
+
+# Formats
+@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
+@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
+@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
+@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
+@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2
+@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2
+
+# XTheadBa
+# Instead of defining a new encoding, we simply use the decoder to
+# extract the imm[0:1] field and dispatch to separate translation
+# functions (mirroring the `sh[123]add` instructions from Zba and
+# the regular RVI `add` instruction.
+#
+# The only difference between sh[123]add and addsl is that the shift
+# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
+#
+# Note that shift-by-0 is a valid operation according to the manual.
+# This will be equivalent to a regular add.
+add 0000000 ..... ..... 001 ..... 0001011 @r
+th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
+th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
+th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
+
+# XTheadBb
+th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext
+th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext
+th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2
+th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2
+th_srri 000100 ...... ..... 001 ..... 0001011 @sh6
+th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5
+th_rev 1000001 00000 ..... 001 ..... 0001011 @r2
+th_revw 1001000 00000 ..... 001 ..... 0001011 @r2
+th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2
+
+# XTheadBs
+th_tst 100010 ...... ..... 001 ..... 0001011 @sh6
+
+# XTheadCmo
+th_dcache_call 0000000 00001 00000 000 00000 0001011
+th_dcache_ciall 0000000 00011 00000 000 00000 0001011
+th_dcache_iall 0000000 00010 00000 000 00000 0001011
+th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm
+th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm
+th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm
+th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm
+th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm
+th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm
+th_icache_iall 0000000 10000 00000 000 00000 0001011
+th_icache_ialls 0000000 10001 00000 000 00000 0001011
+th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm
+th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm
+th_l2cache_call 0000000 10101 00000 000 00000 0001011
+th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
+th_l2cache_iall 0000000 10110 00000 000 00000 0001011
+
+# XTheadCondMov
+th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
+th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
+
+# XTheadFMemIdx
+th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx
+
+# XTheadFmv
+th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2
+th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2
+
+# XTheadMac
+th_mula 00100 00 ..... ..... 001 ..... 0001011 @r
+th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r
+th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r
+th_muls 00100 01 ..... ..... 001 ..... 0001011 @r
+th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r
+th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r
+
+# XTheadMemIdx
+th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc
+
+th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx
+
+th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx
+
+# XTheadMemPair
+th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair
+th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair
+th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair
+th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair
+th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair
+
+# XTheadSync
+th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
+th_sync 0000000 11000 00000 000 00000 0001011
+th_sync_i 0000000 11010 00000 000 00000 0001011
+th_sync_is 0000000 11011 00000 000 00000 0001011
+th_sync_s 0000000 11001 00000 000 00000 0001011
